1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell Octeon EP (EndPoint) Ethernet Driver
4 * Copyright (C) 2020 Marvell.
12 #define IQ_SEND_STOP 1
13 #define IQ_SEND_FAILED -1
15 #define TX_BUFTYPE_NONE 0
16 #define TX_BUFTYPE_NET 1
17 #define TX_BUFTYPE_NET_SG 2
18 #define NUM_TX_BUFTYPES 3
20 /* Hardware format for Scatter/Gather list
22 * 63 48|47 32|31 16|15 0
23 * -----------------------------------------
24 * | Len 0 | Len 1 | Len 2 | Len 3 |
25 * -----------------------------------------
27 * -----------------------------------------
29 * -----------------------------------------
31 * -----------------------------------------
33 * -----------------------------------------
35 struct octep_tx_sglist_desc {
37 dma_addr_t dma_ptr[4];
40 /* Each Scatter/Gather entry sent to hardwar hold four pointers.
41 * So, number of entries required is (MAX_SKB_FRAGS + 1)/4, where '+1'
42 * is for main skb which also goes as a gather buffer to Octeon hardware.
43 * To allocate sufficient SGLIST entries for a packet with max fragments,
44 * align by adding 3 before calcuating max SGLIST entries per packet.
46 #define OCTEP_SGLIST_ENTRIES_PER_PKT ((MAX_SKB_FRAGS + 1 + 3) / 4)
47 #define OCTEP_SGLIST_SIZE_PER_PKT \
48 (OCTEP_SGLIST_ENTRIES_PER_PKT * sizeof(struct octep_tx_sglist_desc))
50 struct octep_tx_buffer {
53 struct octep_tx_sglist_desc *sglist;
54 dma_addr_t sglist_dma;
58 #define OCTEP_IQ_TXBUFF_INFO_SIZE (sizeof(struct octep_tx_buffer))
60 /* Hardware interface Tx statistics */
61 struct octep_iface_tx_stats {
62 /* Packets dropped due to excessive collisions */
65 /* Packets dropped due to excessive deferral */
68 /* Packets sent that experienced multiple collisions before successful
73 /* Packets sent that experienced a single collision before successful
78 /* Total octets sent on the interface */
81 /* Total frames sent on the interface */
84 /* Packets sent with an octet count < 64 */
87 /* Packets sent with an octet count == 64 */
90 /* Packets sent with an octet count of 65–127 */
93 /* Packets sent with an octet count of 128–255 */
96 /* Packets sent with an octet count of 256–511 */
99 /* Packets sent with an octet count of 512–1023 */
102 /* Packets sent with an octet count of 1024-1518 */
105 /* Packets sent with an octet count of > 1518 */
108 /* Packets sent to a broadcast DMAC */
111 /* Packets sent to the multicast DMAC */
114 /* Packets sent that experienced a transmit underflow and were
119 /* Control/PAUSE packets sent */
123 /* Input Queue statistics. Each input queue has four stats fields. */
124 struct octep_iq_stats {
125 /* Instructions posted to this queue. */
128 /* Instructions copied by hardware for processing. */
131 /* Instructions that could not be processed. */
134 /* Bytes sent through this queue. */
137 /* Gather entries sent through this queue. */
140 /* Number of transmit failures due to TX_BUSY */
143 /* Number of times the queue is restarted */
147 /* The instruction (input) queue.
148 * The input queue is used to post raw (instruction) mode data or packet
149 * data to Octeon device from the host. Each input queue (up to 4) for
150 * a Octeon device has one such structure to represent it.
155 struct octep_device *octep_dev;
156 struct net_device *netdev;
158 struct netdev_queue *netdev_q;
160 /* Index in input ring where driver should write the next packet */
161 u16 host_write_index;
163 /* Index in input ring where Octeon is expected to read next packet */
164 u16 octep_read_index;
166 /* This index aids in finding the window in the queue where Octeon
167 * has read the commands.
171 /* Statistics for this input queue. */
172 struct octep_iq_stats stats;
174 /* This field keeps track of the instructions pending in this queue. */
175 atomic_t instr_pending;
177 /* Pointer to the Virtual Base addr of the input ring. */
178 struct octep_tx_desc_hw *desc_ring;
180 /* DMA mapped base address of the input descriptor ring. */
181 dma_addr_t desc_ring_dma;
183 /* Info of Tx buffers pending completion. */
184 struct octep_tx_buffer *buff_info;
186 /* Base pointer to Scatter/Gather lists for all ring descriptors. */
187 struct octep_tx_sglist_desc *sglist;
189 /* DMA mapped addr of Scatter Gather Lists */
190 dma_addr_t sglist_dma;
192 /* Octeon doorbell register for the ring. */
193 u8 __iomem *doorbell_reg;
195 /* Octeon instruction count register for this ring. */
196 u8 __iomem *inst_cnt_reg;
198 /* interrupt level register for this ring */
199 u8 __iomem *intr_lvl_reg;
201 /* Maximum no. of instructions in this queue. */
210 /* Number of instructions pending to be posted to Octeon. */
213 /* The max. number of instructions that can be held pending by the
214 * driver before ringing doorbell.
219 /* Hardware Tx Instruction Header */
220 struct octep_instr_hdr {
230 /* Front Data size */
233 /* No. of entries in gather list */
236 /* Gather indicator 1=gather*/
243 /* Hardware Tx completion response header */
244 struct octep_instr_resp_hdr {
248 /* PCIe port to use for response */
251 /* Scatter indicator 1=scatter */
254 /* Size of Expected result OR no. of entries in scatter list */
257 /* Desired destination port for result */
260 /* Opcode Specific parameters */
263 /* Opcode for the return packet */
267 /* 64-byte Tx instruction format.
268 * Format of instruction for a 64-byte mode input queue.
270 * only first 16-bytes (dptr and ih) are mandatory; rest are optional
271 * and filled by the driver based on firmware/hardware capabilities.
272 * These optional headers together called Front Data and its size is
273 * described by ih->fsz.
275 struct octep_tx_desc_hw {
276 /* Pointer where the input data is available. */
279 /* Instruction Header. */
281 struct octep_instr_hdr ih;
285 /* Pointer where the response for a RAW mode packet will be written
290 /* Input Instruction Response Header. */
291 struct octep_instr_resp_hdr irh;
293 /* Additional headers available in a 64-byte instruction. */
297 #define OCTEP_IQ_DESC_SIZE (sizeof(struct octep_tx_desc_hw))
298 #endif /* _OCTEP_TX_H_ */