1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
5 * Copyright (C) 2014 Marvell
7 * Marcin Wojtas <mw@semihalf.com>
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/platform_device.h>
15 #include <linux/skbuff.h>
16 #include <linux/inetdevice.h>
17 #include <linux/mbus.h>
18 #include <linux/module.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/interrupt.h>
21 #include <linux/cpumask.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_mdio.h>
25 #include <linux/of_net.h>
26 #include <linux/of_address.h>
27 #include <linux/of_device.h>
28 #include <linux/phy.h>
29 #include <linux/phylink.h>
30 #include <linux/phy/phy.h>
31 #include <linux/ptp_classify.h>
32 #include <linux/clk.h>
33 #include <linux/hrtimer.h>
34 #include <linux/ktime.h>
35 #include <linux/regmap.h>
36 #include <uapi/linux/ppp_defs.h>
40 #include <linux/bpf_trace.h>
43 #include "mvpp2_prs.h"
44 #include "mvpp2_cls.h"
46 enum mvpp2_bm_pool_log_num {
56 } mvpp2_pools[MVPP2_BM_POOLS_NUM];
58 /* The prototype is added here to be used in start_dev when using ACPI. This
59 * will be removed once phylink is used for all modes (dt+ACPI).
61 static void mvpp2_acpi_start(struct mvpp2_port *port);
64 #define MVPP2_QDIST_SINGLE_MODE 0
65 #define MVPP2_QDIST_MULTI_MODE 1
67 static int queue_mode = MVPP2_QDIST_MULTI_MODE;
69 module_param(queue_mode, int, 0444);
70 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)");
72 /* Utility/helper methods */
74 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
76 writel(data, priv->swth_base[0] + offset);
79 u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
81 return readl(priv->swth_base[0] + offset);
84 static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset)
86 return readl_relaxed(priv->swth_base[0] + offset);
89 static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu)
91 return cpu % priv->nthreads;
94 static void mvpp2_cm3_write(struct mvpp2 *priv, u32 offset, u32 data)
96 writel(data, priv->cm3_base + offset);
99 static u32 mvpp2_cm3_read(struct mvpp2 *priv, u32 offset)
101 return readl(priv->cm3_base + offset);
104 static struct page_pool *
105 mvpp2_create_page_pool(struct device *dev, int num, int len,
106 enum dma_data_direction dma_dir)
108 struct page_pool_params pp_params = {
109 /* internal DMA mapping in page_pool */
110 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
115 .offset = MVPP2_SKB_HEADROOM,
119 return page_pool_create(&pp_params);
122 /* These accessors should be used to access:
124 * - per-thread registers, where each thread has its own copy of the
127 * MVPP2_BM_VIRT_ALLOC_REG
128 * MVPP2_BM_ADDR_HIGH_ALLOC
129 * MVPP22_BM_ADDR_HIGH_RLS_REG
130 * MVPP2_BM_VIRT_RLS_REG
131 * MVPP2_ISR_RX_TX_CAUSE_REG
132 * MVPP2_ISR_RX_TX_MASK_REG
134 * MVPP2_AGGR_TXQ_UPDATE_REG
135 * MVPP2_TXQ_RSVD_REQ_REG
136 * MVPP2_TXQ_RSVD_RSLT_REG
140 * - global registers that must be accessed through a specific thread
141 * window, because they are related to an access to a per-thread
144 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG)
145 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG)
146 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG)
147 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG)
148 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG)
149 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG)
150 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG)
151 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG)
152 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG)
153 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG)
154 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG)
155 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG)
156 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG)
158 static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread,
159 u32 offset, u32 data)
161 writel(data, priv->swth_base[thread] + offset);
164 static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread,
167 return readl(priv->swth_base[thread] + offset);
170 static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread,
171 u32 offset, u32 data)
173 writel_relaxed(data, priv->swth_base[thread] + offset);
176 static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread,
179 return readl_relaxed(priv->swth_base[thread] + offset);
182 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,
183 struct mvpp2_tx_desc *tx_desc)
185 if (port->priv->hw_version == MVPP21)
186 return le32_to_cpu(tx_desc->pp21.buf_dma_addr);
188 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) &
192 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
193 struct mvpp2_tx_desc *tx_desc,
196 dma_addr_t addr, offset;
198 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN;
199 offset = dma_addr & MVPP2_TX_DESC_ALIGN;
201 if (port->priv->hw_version == MVPP21) {
202 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr);
203 tx_desc->pp21.packet_offset = offset;
205 __le64 val = cpu_to_le64(addr);
207 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK);
208 tx_desc->pp22.buf_dma_addr_ptp |= val;
209 tx_desc->pp22.packet_offset = offset;
213 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port,
214 struct mvpp2_tx_desc *tx_desc)
216 if (port->priv->hw_version == MVPP21)
217 return le16_to_cpu(tx_desc->pp21.data_size);
219 return le16_to_cpu(tx_desc->pp22.data_size);
222 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
223 struct mvpp2_tx_desc *tx_desc,
226 if (port->priv->hw_version == MVPP21)
227 tx_desc->pp21.data_size = cpu_to_le16(size);
229 tx_desc->pp22.data_size = cpu_to_le16(size);
232 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
233 struct mvpp2_tx_desc *tx_desc,
236 if (port->priv->hw_version == MVPP21)
237 tx_desc->pp21.phys_txq = txq;
239 tx_desc->pp22.phys_txq = txq;
242 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
243 struct mvpp2_tx_desc *tx_desc,
244 unsigned int command)
246 if (port->priv->hw_version == MVPP21)
247 tx_desc->pp21.command = cpu_to_le32(command);
249 tx_desc->pp22.command = cpu_to_le32(command);
252 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port,
253 struct mvpp2_tx_desc *tx_desc)
255 if (port->priv->hw_version == MVPP21)
256 return tx_desc->pp21.packet_offset;
258 return tx_desc->pp22.packet_offset;
261 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
262 struct mvpp2_rx_desc *rx_desc)
264 if (port->priv->hw_version == MVPP21)
265 return le32_to_cpu(rx_desc->pp21.buf_dma_addr);
267 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) &
271 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
272 struct mvpp2_rx_desc *rx_desc)
274 if (port->priv->hw_version == MVPP21)
275 return le32_to_cpu(rx_desc->pp21.buf_cookie);
277 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) &
281 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
282 struct mvpp2_rx_desc *rx_desc)
284 if (port->priv->hw_version == MVPP21)
285 return le16_to_cpu(rx_desc->pp21.data_size);
287 return le16_to_cpu(rx_desc->pp22.data_size);
290 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
291 struct mvpp2_rx_desc *rx_desc)
293 if (port->priv->hw_version == MVPP21)
294 return le32_to_cpu(rx_desc->pp21.status);
296 return le32_to_cpu(rx_desc->pp22.status);
299 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
301 txq_pcpu->txq_get_index++;
302 if (txq_pcpu->txq_get_index == txq_pcpu->size)
303 txq_pcpu->txq_get_index = 0;
306 static void mvpp2_txq_inc_put(struct mvpp2_port *port,
307 struct mvpp2_txq_pcpu *txq_pcpu,
309 struct mvpp2_tx_desc *tx_desc,
310 enum mvpp2_tx_buf_type buf_type)
312 struct mvpp2_txq_pcpu_buf *tx_buf =
313 txq_pcpu->buffs + txq_pcpu->txq_put_index;
314 tx_buf->type = buf_type;
315 if (buf_type == MVPP2_TYPE_SKB)
319 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc);
320 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) +
321 mvpp2_txdesc_offset_get(port, tx_desc);
322 txq_pcpu->txq_put_index++;
323 if (txq_pcpu->txq_put_index == txq_pcpu->size)
324 txq_pcpu->txq_put_index = 0;
327 /* Get number of maximum RXQ */
328 static int mvpp2_get_nrxqs(struct mvpp2 *priv)
332 if (priv->hw_version >= MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
335 /* According to the PPv2.2 datasheet and our experiments on
336 * PPv2.1, RX queues have an allocation granularity of 4 (when
337 * more than a single one on PPv2.2).
338 * Round up to nearest multiple of 4.
340 nrxqs = (num_possible_cpus() + 3) & ~0x3;
341 if (nrxqs > MVPP2_PORT_MAX_RXQ)
342 nrxqs = MVPP2_PORT_MAX_RXQ;
347 /* Get number of physical egress port */
348 static inline int mvpp2_egress_port(struct mvpp2_port *port)
350 return MVPP2_MAX_TCONT + port->id;
353 /* Get number of physical TXQ */
354 static inline int mvpp2_txq_phys(int port, int txq)
356 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
359 /* Returns a struct page if page_pool is set, otherwise a buffer */
360 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool,
361 struct page_pool *page_pool)
364 return page_pool_dev_alloc_pages(page_pool);
366 if (likely(pool->frag_size <= PAGE_SIZE))
367 return netdev_alloc_frag(pool->frag_size);
369 return kmalloc(pool->frag_size, GFP_ATOMIC);
372 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool,
373 struct page_pool *page_pool, void *data)
376 page_pool_put_full_page(page_pool, virt_to_head_page(data), false);
377 else if (likely(pool->frag_size <= PAGE_SIZE))
383 /* Buffer Manager configuration routines */
386 static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv,
387 struct mvpp2_bm_pool *bm_pool, int size)
391 /* Number of buffer pointers must be a multiple of 16, as per
392 * hardware constraints
394 if (!IS_ALIGNED(size, 16))
397 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 and PPv2.3 needs 16
398 * bytes per buffer pointer
400 if (priv->hw_version == MVPP21)
401 bm_pool->size_bytes = 2 * sizeof(u32) * size;
403 bm_pool->size_bytes = 2 * sizeof(u64) * size;
405 bm_pool->virt_addr = dma_alloc_coherent(dev, bm_pool->size_bytes,
408 if (!bm_pool->virt_addr)
411 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
412 MVPP2_BM_POOL_PTR_ALIGN)) {
413 dma_free_coherent(dev, bm_pool->size_bytes,
414 bm_pool->virt_addr, bm_pool->dma_addr);
415 dev_err(dev, "BM pool %d is not %d bytes aligned\n",
416 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
420 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
421 lower_32_bits(bm_pool->dma_addr));
422 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
424 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
425 val |= MVPP2_BM_START_MASK;
427 val &= ~MVPP2_BM_LOW_THRESH_MASK;
428 val &= ~MVPP2_BM_HIGH_THRESH_MASK;
430 /* Set 8 Pools BPPI threshold for MVPP23 */
431 if (priv->hw_version == MVPP23) {
432 val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP23_BM_BPPI_LOW_THRESH);
433 val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP23_BM_BPPI_HIGH_THRESH);
435 val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP2_BM_BPPI_LOW_THRESH);
436 val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP2_BM_BPPI_HIGH_THRESH);
439 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
441 bm_pool->size = size;
442 bm_pool->pkt_size = 0;
443 bm_pool->buf_num = 0;
448 /* Set pool buffer size */
449 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
450 struct mvpp2_bm_pool *bm_pool,
455 bm_pool->buf_size = buf_size;
457 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
458 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
461 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
462 struct mvpp2_bm_pool *bm_pool,
463 dma_addr_t *dma_addr,
464 phys_addr_t *phys_addr)
466 unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu());
468 *dma_addr = mvpp2_thread_read(priv, thread,
469 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
470 *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG);
472 if (priv->hw_version >= MVPP22) {
474 u32 dma_addr_highbits, phys_addr_highbits;
476 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC);
477 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK);
478 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >>
479 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT;
481 if (sizeof(dma_addr_t) == 8)
482 *dma_addr |= (u64)dma_addr_highbits << 32;
484 if (sizeof(phys_addr_t) == 8)
485 *phys_addr |= (u64)phys_addr_highbits << 32;
491 /* Free all buffers from the pool */
492 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv,
493 struct mvpp2_bm_pool *bm_pool, int buf_num)
495 struct page_pool *pp = NULL;
498 if (buf_num > bm_pool->buf_num) {
499 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n",
500 bm_pool->id, buf_num);
501 buf_num = bm_pool->buf_num;
504 if (priv->percpu_pools)
505 pp = priv->page_pool[bm_pool->id];
507 for (i = 0; i < buf_num; i++) {
508 dma_addr_t buf_dma_addr;
509 phys_addr_t buf_phys_addr;
512 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool,
513 &buf_dma_addr, &buf_phys_addr);
516 dma_unmap_single(dev, buf_dma_addr,
517 bm_pool->buf_size, DMA_FROM_DEVICE);
519 data = (void *)phys_to_virt(buf_phys_addr);
523 mvpp2_frag_free(bm_pool, pp, data);
526 /* Update BM driver with number of buffers removed from pool */
527 bm_pool->buf_num -= i;
530 /* Check number of buffers in BM pool */
531 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool)
535 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) &
536 MVPP22_BM_POOL_PTRS_NUM_MASK;
537 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) &
538 MVPP2_BM_BPPI_PTR_NUM_MASK;
540 /* HW has one buffer ready which is not reflected in the counters */
548 static int mvpp2_bm_pool_destroy(struct device *dev, struct mvpp2 *priv,
549 struct mvpp2_bm_pool *bm_pool)
554 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
555 mvpp2_bm_bufs_free(dev, priv, bm_pool, buf_num);
557 /* Check buffer counters after free */
558 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
560 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n",
561 bm_pool->id, bm_pool->buf_num);
565 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
566 val |= MVPP2_BM_STOP_MASK;
567 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
569 if (priv->percpu_pools) {
570 page_pool_destroy(priv->page_pool[bm_pool->id]);
571 priv->page_pool[bm_pool->id] = NULL;
574 dma_free_coherent(dev, bm_pool->size_bytes,
580 static int mvpp2_bm_pools_init(struct device *dev, struct mvpp2 *priv)
582 int i, err, size, poolnum = MVPP2_BM_POOLS_NUM;
583 struct mvpp2_bm_pool *bm_pool;
585 if (priv->percpu_pools)
586 poolnum = mvpp2_get_nrxqs(priv) * 2;
588 /* Create all pools with maximum size */
589 size = MVPP2_BM_POOL_SIZE_MAX;
590 for (i = 0; i < poolnum; i++) {
591 bm_pool = &priv->bm_pools[i];
593 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
595 goto err_unroll_pools;
596 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
601 dev_err(dev, "failed to create BM pool %d, size %d\n", i, size);
602 for (i = i - 1; i >= 0; i--)
603 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
607 /* Routine enable PPv23 8 pool mode */
608 static void mvpp23_bm_set_8pool_mode(struct mvpp2 *priv)
612 val = mvpp2_read(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG);
613 val |= MVPP23_BM_8POOL_MODE;
614 mvpp2_write(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG, val);
617 static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv)
619 enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
620 int i, err, poolnum = MVPP2_BM_POOLS_NUM;
621 struct mvpp2_port *port;
623 if (priv->percpu_pools) {
624 for (i = 0; i < priv->port_count; i++) {
625 port = priv->port_list[i];
626 if (port->xdp_prog) {
627 dma_dir = DMA_BIDIRECTIONAL;
632 poolnum = mvpp2_get_nrxqs(priv) * 2;
633 for (i = 0; i < poolnum; i++) {
634 /* the pool in use */
635 int pn = i / (poolnum / 2);
638 mvpp2_create_page_pool(dev,
639 mvpp2_pools[pn].buf_num,
640 mvpp2_pools[pn].pkt_size,
642 if (IS_ERR(priv->page_pool[i])) {
645 for (j = 0; j < i; j++) {
646 page_pool_destroy(priv->page_pool[j]);
647 priv->page_pool[j] = NULL;
649 return PTR_ERR(priv->page_pool[i]);
654 dev_info(dev, "using %d %s buffers\n", poolnum,
655 priv->percpu_pools ? "per-cpu" : "shared");
657 for (i = 0; i < poolnum; i++) {
658 /* Mask BM all interrupts */
659 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
660 /* Clear BM cause register */
661 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
664 /* Allocate and initialize BM pools */
665 priv->bm_pools = devm_kcalloc(dev, poolnum,
666 sizeof(*priv->bm_pools), GFP_KERNEL);
670 if (priv->hw_version == MVPP23)
671 mvpp23_bm_set_8pool_mode(priv);
673 err = mvpp2_bm_pools_init(dev, priv);
679 static void mvpp2_setup_bm_pool(void)
682 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM;
683 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE;
686 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM;
687 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE;
690 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM;
691 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE;
694 /* Attach long pool to rxq */
695 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
696 int lrxq, int long_pool)
701 /* Get queue physical ID */
702 prxq = port->rxqs[lrxq]->id;
704 if (port->priv->hw_version == MVPP21)
705 mask = MVPP21_RXQ_POOL_LONG_MASK;
707 mask = MVPP22_RXQ_POOL_LONG_MASK;
709 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
711 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
712 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
715 /* Attach short pool to rxq */
716 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port,
717 int lrxq, int short_pool)
722 /* Get queue physical ID */
723 prxq = port->rxqs[lrxq]->id;
725 if (port->priv->hw_version == MVPP21)
726 mask = MVPP21_RXQ_POOL_SHORT_MASK;
728 mask = MVPP22_RXQ_POOL_SHORT_MASK;
730 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
732 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask;
733 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
736 static void *mvpp2_buf_alloc(struct mvpp2_port *port,
737 struct mvpp2_bm_pool *bm_pool,
738 struct page_pool *page_pool,
739 dma_addr_t *buf_dma_addr,
740 phys_addr_t *buf_phys_addr,
747 data = mvpp2_frag_alloc(bm_pool, page_pool);
752 page = (struct page *)data;
753 dma_addr = page_pool_get_dma_addr(page);
754 data = page_to_virt(page);
756 dma_addr = dma_map_single(port->dev->dev.parent, data,
757 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size),
759 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
760 mvpp2_frag_free(bm_pool, NULL, data);
764 *buf_dma_addr = dma_addr;
765 *buf_phys_addr = virt_to_phys(data);
770 /* Routine enable flow control for RXQs condition */
771 static void mvpp2_rxq_enable_fc(struct mvpp2_port *port)
773 int val, cm3_state, host_id, q;
774 int fq = port->first_rxq;
777 spin_lock_irqsave(&port->priv->mss_spinlock, flags);
779 /* Remove Flow control enable bit to prevent race between FW and Kernel
780 * If Flow control was enabled, it would be re-enabled.
782 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
783 cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
784 val &= ~FLOW_CONTROL_ENABLE_BIT;
785 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
787 /* Set same Flow control for all RXQs */
788 for (q = 0; q < port->nrxqs; q++) {
789 /* Set stop and start Flow control RXQ thresholds */
790 val = MSS_THRESHOLD_START;
791 val |= (MSS_THRESHOLD_STOP << MSS_RXQ_TRESH_STOP_OFFS);
792 mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val);
794 val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq));
795 /* Set RXQ port ID */
796 val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq));
797 val |= (port->id << MSS_RXQ_ASS_Q_BASE(q, fq));
798 val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq)
799 + MSS_RXQ_ASS_HOSTID_OFFS));
801 /* Calculate RXQ host ID:
802 * In Single queue mode: Host ID equal to Host ID used for
803 * shared RX interrupt
804 * In Multi queue mode: Host ID equal to number of
805 * RXQ ID / number of CoS queues
806 * In Single resource mode: Host ID always equal to 0
808 if (queue_mode == MVPP2_QDIST_SINGLE_MODE)
809 host_id = port->nqvecs;
810 else if (queue_mode == MVPP2_QDIST_MULTI_MODE)
815 /* Set RXQ host ID */
816 val |= (host_id << (MSS_RXQ_ASS_Q_BASE(q, fq)
817 + MSS_RXQ_ASS_HOSTID_OFFS));
819 mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val);
822 /* Notify Firmware that Flow control config space ready for update */
823 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
824 val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
826 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
828 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
831 /* Routine disable flow control for RXQs condition */
832 static void mvpp2_rxq_disable_fc(struct mvpp2_port *port)
834 int val, cm3_state, q;
836 int fq = port->first_rxq;
838 spin_lock_irqsave(&port->priv->mss_spinlock, flags);
840 /* Remove Flow control enable bit to prevent race between FW and Kernel
841 * If Flow control was enabled, it would be re-enabled.
843 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
844 cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
845 val &= ~FLOW_CONTROL_ENABLE_BIT;
846 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
848 /* Disable Flow control for all RXQs */
849 for (q = 0; q < port->nrxqs; q++) {
850 /* Set threshold 0 to disable Flow control */
852 val |= (0 << MSS_RXQ_TRESH_STOP_OFFS);
853 mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val);
855 val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq));
857 val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq));
859 val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq)
860 + MSS_RXQ_ASS_HOSTID_OFFS));
862 mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val);
865 /* Notify Firmware that Flow control config space ready for update */
866 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
867 val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
869 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
871 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
874 /* Routine disable/enable flow control for BM pool condition */
875 static void mvpp2_bm_pool_update_fc(struct mvpp2_port *port,
876 struct mvpp2_bm_pool *pool,
882 spin_lock_irqsave(&port->priv->mss_spinlock, flags);
884 /* Remove Flow control enable bit to prevent race between FW and Kernel
885 * If Flow control were enabled, it would be re-enabled.
887 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
888 cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
889 val &= ~FLOW_CONTROL_ENABLE_BIT;
890 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
892 /* Check if BM pool should be enabled/disable */
894 /* Set BM pool start and stop thresholds per port */
895 val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id));
896 val |= MSS_BUF_POOL_PORT_OFFS(port->id);
897 val &= ~MSS_BUF_POOL_START_MASK;
898 val |= (MSS_THRESHOLD_START << MSS_BUF_POOL_START_OFFS);
899 val &= ~MSS_BUF_POOL_STOP_MASK;
900 val |= MSS_THRESHOLD_STOP;
901 mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val);
903 /* Remove BM pool from the port */
904 val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id));
905 val &= ~MSS_BUF_POOL_PORT_OFFS(port->id);
907 /* Zero BM pool start and stop thresholds to disable pool
908 * flow control if pool empty (not used by any port)
910 if (!pool->buf_num) {
911 val &= ~MSS_BUF_POOL_START_MASK;
912 val &= ~MSS_BUF_POOL_STOP_MASK;
915 mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val);
918 /* Notify Firmware that Flow control config space ready for update */
919 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
920 val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
922 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
924 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
927 /* disable/enable flow control for BM pool on all ports */
928 static void mvpp2_bm_pool_update_priv_fc(struct mvpp2 *priv, bool en)
930 struct mvpp2_port *port;
933 for (i = 0; i < priv->port_count; i++) {
934 port = priv->port_list[i];
935 if (port->priv->percpu_pools) {
936 for (i = 0; i < port->nrxqs; i++)
937 mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i],
940 mvpp2_bm_pool_update_fc(port, port->pool_long, port->tx_fc & en);
941 mvpp2_bm_pool_update_fc(port, port->pool_short, port->tx_fc & en);
946 static int mvpp2_enable_global_fc(struct mvpp2 *priv)
948 int val, timeout = 0;
950 /* Enable global flow control. In this stage global
951 * flow control enabled, but still disabled per port.
953 val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
954 val |= FLOW_CONTROL_ENABLE_BIT;
955 mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
957 /* Check if Firmware running and disable FC if not*/
958 val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
959 mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
961 while (timeout < MSS_FC_MAX_TIMEOUT) {
962 val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
964 if (!(val & FLOW_CONTROL_UPDATE_COMMAND_BIT))
966 usleep_range(10, 20);
970 priv->global_tx_fc = false;
974 /* Release buffer to BM */
975 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
976 dma_addr_t buf_dma_addr,
977 phys_addr_t buf_phys_addr)
979 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
980 unsigned long flags = 0;
982 if (test_bit(thread, &port->priv->lock_map))
983 spin_lock_irqsave(&port->bm_lock[thread], flags);
985 if (port->priv->hw_version >= MVPP22) {
988 if (sizeof(dma_addr_t) == 8)
989 val |= upper_32_bits(buf_dma_addr) &
990 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
992 if (sizeof(phys_addr_t) == 8)
993 val |= (upper_32_bits(buf_phys_addr)
994 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
995 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
997 mvpp2_thread_write_relaxed(port->priv, thread,
998 MVPP22_BM_ADDR_HIGH_RLS_REG, val);
1001 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
1002 * returned in the "cookie" field of the RX
1003 * descriptor. Instead of storing the virtual address, we
1004 * store the physical address
1006 mvpp2_thread_write_relaxed(port->priv, thread,
1007 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
1008 mvpp2_thread_write_relaxed(port->priv, thread,
1009 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
1011 if (test_bit(thread, &port->priv->lock_map))
1012 spin_unlock_irqrestore(&port->bm_lock[thread], flags);
1017 /* Allocate buffers for the pool */
1018 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
1019 struct mvpp2_bm_pool *bm_pool, int buf_num)
1021 int i, buf_size, total_size;
1022 dma_addr_t dma_addr;
1023 phys_addr_t phys_addr;
1024 struct page_pool *pp = NULL;
1027 if (port->priv->percpu_pools &&
1028 bm_pool->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
1029 netdev_err(port->dev,
1030 "attempted to use jumbo frames with per-cpu pools");
1034 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size);
1035 total_size = MVPP2_RX_TOTAL_SIZE(buf_size);
1038 (buf_num + bm_pool->buf_num > bm_pool->size)) {
1039 netdev_err(port->dev,
1040 "cannot allocate %d buffers for pool %d\n",
1041 buf_num, bm_pool->id);
1045 if (port->priv->percpu_pools)
1046 pp = port->priv->page_pool[bm_pool->id];
1047 for (i = 0; i < buf_num; i++) {
1048 buf = mvpp2_buf_alloc(port, bm_pool, pp, &dma_addr,
1049 &phys_addr, GFP_KERNEL);
1053 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr,
1057 /* Update BM driver with number of buffers added to pool */
1058 bm_pool->buf_num += i;
1060 netdev_dbg(port->dev,
1061 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n",
1062 bm_pool->id, bm_pool->pkt_size, buf_size, total_size);
1064 netdev_dbg(port->dev,
1065 "pool %d: %d of %d buffers added\n",
1066 bm_pool->id, i, buf_num);
1070 /* Notify the driver that BM pool is being used as specific type and return the
1071 * pool pointer on success
1073 static struct mvpp2_bm_pool *
1074 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size)
1076 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
1079 if ((port->priv->percpu_pools && pool > mvpp2_get_nrxqs(port->priv) * 2) ||
1080 (!port->priv->percpu_pools && pool >= MVPP2_BM_POOLS_NUM)) {
1081 netdev_err(port->dev, "Invalid pool %d\n", pool);
1085 /* Allocate buffers in case BM pool is used as long pool, but packet
1086 * size doesn't match MTU or BM pool hasn't being used yet
1088 if (new_pool->pkt_size == 0) {
1091 /* Set default buffer number or free all the buffers in case
1092 * the pool is not empty
1094 pkts_num = new_pool->buf_num;
1095 if (pkts_num == 0) {
1096 if (port->priv->percpu_pools) {
1097 if (pool < port->nrxqs)
1098 pkts_num = mvpp2_pools[MVPP2_BM_SHORT].buf_num;
1100 pkts_num = mvpp2_pools[MVPP2_BM_LONG].buf_num;
1102 pkts_num = mvpp2_pools[pool].buf_num;
1105 mvpp2_bm_bufs_free(port->dev->dev.parent,
1106 port->priv, new_pool, pkts_num);
1109 new_pool->pkt_size = pkt_size;
1110 new_pool->frag_size =
1111 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
1112 MVPP2_SKB_SHINFO_SIZE;
1114 /* Allocate buffers for this pool */
1115 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
1116 if (num != pkts_num) {
1117 WARN(1, "pool %d: %d of %d allocated\n",
1118 new_pool->id, num, pkts_num);
1123 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
1124 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
1129 static struct mvpp2_bm_pool *
1130 mvpp2_bm_pool_use_percpu(struct mvpp2_port *port, int type,
1131 unsigned int pool, int pkt_size)
1133 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
1136 if (pool > port->nrxqs * 2) {
1137 netdev_err(port->dev, "Invalid pool %d\n", pool);
1141 /* Allocate buffers in case BM pool is used as long pool, but packet
1142 * size doesn't match MTU or BM pool hasn't being used yet
1144 if (new_pool->pkt_size == 0) {
1147 /* Set default buffer number or free all the buffers in case
1148 * the pool is not empty
1150 pkts_num = new_pool->buf_num;
1152 pkts_num = mvpp2_pools[type].buf_num;
1154 mvpp2_bm_bufs_free(port->dev->dev.parent,
1155 port->priv, new_pool, pkts_num);
1157 new_pool->pkt_size = pkt_size;
1158 new_pool->frag_size =
1159 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
1160 MVPP2_SKB_SHINFO_SIZE;
1162 /* Allocate buffers for this pool */
1163 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
1164 if (num != pkts_num) {
1165 WARN(1, "pool %d: %d of %d allocated\n",
1166 new_pool->id, num, pkts_num);
1171 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
1172 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
1177 /* Initialize pools for swf, shared buffers variant */
1178 static int mvpp2_swf_bm_pool_init_shared(struct mvpp2_port *port)
1180 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool;
1183 /* If port pkt_size is higher than 1518B:
1184 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
1185 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
1187 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
1188 long_log_pool = MVPP2_BM_JUMBO;
1189 short_log_pool = MVPP2_BM_LONG;
1191 long_log_pool = MVPP2_BM_LONG;
1192 short_log_pool = MVPP2_BM_SHORT;
1195 if (!port->pool_long) {
1197 mvpp2_bm_pool_use(port, long_log_pool,
1198 mvpp2_pools[long_log_pool].pkt_size);
1199 if (!port->pool_long)
1202 port->pool_long->port_map |= BIT(port->id);
1204 for (rxq = 0; rxq < port->nrxqs; rxq++)
1205 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
1208 if (!port->pool_short) {
1210 mvpp2_bm_pool_use(port, short_log_pool,
1211 mvpp2_pools[short_log_pool].pkt_size);
1212 if (!port->pool_short)
1215 port->pool_short->port_map |= BIT(port->id);
1217 for (rxq = 0; rxq < port->nrxqs; rxq++)
1218 mvpp2_rxq_short_pool_set(port, rxq,
1219 port->pool_short->id);
1225 /* Initialize pools for swf, percpu buffers variant */
1226 static int mvpp2_swf_bm_pool_init_percpu(struct mvpp2_port *port)
1228 struct mvpp2_bm_pool *bm_pool;
1231 for (i = 0; i < port->nrxqs; i++) {
1232 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_SHORT, i,
1233 mvpp2_pools[MVPP2_BM_SHORT].pkt_size);
1237 bm_pool->port_map |= BIT(port->id);
1238 mvpp2_rxq_short_pool_set(port, i, bm_pool->id);
1241 for (i = 0; i < port->nrxqs; i++) {
1242 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_LONG, i + port->nrxqs,
1243 mvpp2_pools[MVPP2_BM_LONG].pkt_size);
1247 bm_pool->port_map |= BIT(port->id);
1248 mvpp2_rxq_long_pool_set(port, i, bm_pool->id);
1251 port->pool_long = NULL;
1252 port->pool_short = NULL;
1257 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
1259 if (port->priv->percpu_pools)
1260 return mvpp2_swf_bm_pool_init_percpu(port);
1262 return mvpp2_swf_bm_pool_init_shared(port);
1265 static void mvpp2_set_hw_csum(struct mvpp2_port *port,
1266 enum mvpp2_bm_pool_log_num new_long_pool)
1268 const netdev_features_t csums = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1270 /* Update L4 checksum when jumbo enable/disable on port.
1271 * Only port 0 supports hardware checksum offload due to
1272 * the Tx FIFO size limitation.
1273 * Also, don't set NETIF_F_HW_CSUM because L3_offset in TX descriptor
1274 * has 7 bits, so the maximum L3 offset is 128.
1276 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
1277 port->dev->features &= ~csums;
1278 port->dev->hw_features &= ~csums;
1280 port->dev->features |= csums;
1281 port->dev->hw_features |= csums;
1285 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
1287 struct mvpp2_port *port = netdev_priv(dev);
1288 enum mvpp2_bm_pool_log_num new_long_pool;
1289 int pkt_size = MVPP2_RX_PKT_SIZE(mtu);
1291 if (port->priv->percpu_pools)
1294 /* If port MTU is higher than 1518B:
1295 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
1296 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
1298 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
1299 new_long_pool = MVPP2_BM_JUMBO;
1301 new_long_pool = MVPP2_BM_LONG;
1303 if (new_long_pool != port->pool_long->id) {
1305 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
1306 mvpp2_bm_pool_update_fc(port,
1310 mvpp2_bm_pool_update_fc(port, port->pool_long,
1314 /* Remove port from old short & long pool */
1315 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id,
1316 port->pool_long->pkt_size);
1317 port->pool_long->port_map &= ~BIT(port->id);
1318 port->pool_long = NULL;
1320 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id,
1321 port->pool_short->pkt_size);
1322 port->pool_short->port_map &= ~BIT(port->id);
1323 port->pool_short = NULL;
1325 port->pkt_size = pkt_size;
1327 /* Add port to new short & long pool */
1328 mvpp2_swf_bm_pool_init(port);
1330 mvpp2_set_hw_csum(port, new_long_pool);
1333 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
1334 mvpp2_bm_pool_update_fc(port, port->pool_long,
1337 mvpp2_bm_pool_update_fc(port, port->pool_short,
1341 /* Update L4 checksum when jumbo enable/disable on port */
1342 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
1343 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
1344 dev->hw_features &= ~(NETIF_F_IP_CSUM |
1347 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1348 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1354 dev->wanted_features = dev->features;
1356 netdev_update_features(dev);
1360 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port)
1362 int i, sw_thread_mask = 0;
1364 for (i = 0; i < port->nqvecs; i++)
1365 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
1367 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1368 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask));
1371 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port)
1373 int i, sw_thread_mask = 0;
1375 for (i = 0; i < port->nqvecs; i++)
1376 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
1378 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1379 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask));
1382 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec)
1384 struct mvpp2_port *port = qvec->port;
1386 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1387 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask));
1390 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec)
1392 struct mvpp2_port *port = qvec->port;
1394 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
1395 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask));
1398 /* Mask the current thread's Rx/Tx interrupts
1399 * Called by on_each_cpu(), guaranteed to run with migration disabled,
1400 * using smp_processor_id() is OK.
1402 static void mvpp2_interrupts_mask(void *arg)
1404 struct mvpp2_port *port = arg;
1405 int cpu = smp_processor_id();
1408 /* If the thread isn't used, don't do anything */
1409 if (cpu > port->priv->nthreads)
1412 thread = mvpp2_cpu_to_thread(port->priv, cpu);
1414 mvpp2_thread_write(port->priv, thread,
1415 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
1416 mvpp2_thread_write(port->priv, thread,
1417 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 0);
1420 /* Unmask the current thread's Rx/Tx interrupts.
1421 * Called by on_each_cpu(), guaranteed to run with migration disabled,
1422 * using smp_processor_id() is OK.
1424 static void mvpp2_interrupts_unmask(void *arg)
1426 struct mvpp2_port *port = arg;
1427 int cpu = smp_processor_id();
1430 /* If the thread isn't used, don't do anything */
1431 if (cpu >= port->priv->nthreads)
1434 thread = mvpp2_cpu_to_thread(port->priv, cpu);
1436 val = MVPP2_CAUSE_MISC_SUM_MASK |
1437 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
1438 if (port->has_tx_irqs)
1439 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
1441 mvpp2_thread_write(port->priv, thread,
1442 MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
1443 mvpp2_thread_write(port->priv, thread,
1444 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id),
1445 MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK);
1449 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
1454 if (port->priv->hw_version == MVPP21)
1460 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22);
1462 for (i = 0; i < port->nqvecs; i++) {
1463 struct mvpp2_queue_vector *v = port->qvecs + i;
1465 if (v->type != MVPP2_QUEUE_VECTOR_SHARED)
1468 mvpp2_thread_write(port->priv, v->sw_thread_id,
1469 MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
1470 mvpp2_thread_write(port->priv, v->sw_thread_id,
1471 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id),
1472 MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK);
1476 /* Only GOP port 0 has an XLG MAC */
1477 static bool mvpp2_port_supports_xlg(struct mvpp2_port *port)
1479 return port->gop_id == 0;
1482 static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port)
1484 return !(port->priv->hw_version >= MVPP22 && port->gop_id == 0);
1487 /* Port configuration routines */
1488 static bool mvpp2_is_xlg(phy_interface_t interface)
1490 return interface == PHY_INTERFACE_MODE_10GBASER ||
1491 interface == PHY_INTERFACE_MODE_XAUI;
1494 static void mvpp2_modify(void __iomem *ptr, u32 mask, u32 set)
1498 old = val = readl(ptr);
1505 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port)
1507 struct mvpp2 *priv = port->priv;
1510 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1511 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT;
1512 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1514 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
1515 if (port->gop_id == 2)
1516 val |= GENCONF_CTRL0_PORT2_RGMII;
1517 else if (port->gop_id == 3)
1518 val |= GENCONF_CTRL0_PORT3_RGMII_MII;
1519 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1522 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port)
1524 struct mvpp2 *priv = port->priv;
1527 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1528 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT |
1529 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE;
1530 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1532 if (port->gop_id > 1) {
1533 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
1534 if (port->gop_id == 2)
1535 val &= ~GENCONF_CTRL0_PORT2_RGMII;
1536 else if (port->gop_id == 3)
1537 val &= ~GENCONF_CTRL0_PORT3_RGMII_MII;
1538 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1542 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port)
1544 struct mvpp2 *priv = port->priv;
1545 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1546 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1549 val = readl(xpcs + MVPP22_XPCS_CFG0);
1550 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) |
1551 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3));
1552 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2);
1553 writel(val, xpcs + MVPP22_XPCS_CFG0);
1555 val = readl(mpcs + MVPP22_MPCS_CTRL);
1556 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN;
1557 writel(val, mpcs + MVPP22_MPCS_CTRL);
1559 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1560 val &= ~MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7);
1561 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1);
1562 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1565 static void mvpp22_gop_fca_enable_periodic(struct mvpp2_port *port, bool en)
1567 struct mvpp2 *priv = port->priv;
1568 void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id);
1571 val = readl(fca + MVPP22_FCA_CONTROL_REG);
1572 val &= ~MVPP22_FCA_ENABLE_PERIODIC;
1574 val |= MVPP22_FCA_ENABLE_PERIODIC;
1575 writel(val, fca + MVPP22_FCA_CONTROL_REG);
1578 static void mvpp22_gop_fca_set_timer(struct mvpp2_port *port, u32 timer)
1580 struct mvpp2 *priv = port->priv;
1581 void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id);
1584 lsb = timer & MVPP22_FCA_REG_MASK;
1585 msb = timer >> MVPP22_FCA_REG_SIZE;
1587 writel(lsb, fca + MVPP22_PERIODIC_COUNTER_LSB_REG);
1588 writel(msb, fca + MVPP22_PERIODIC_COUNTER_MSB_REG);
1591 /* Set Flow Control timer x100 faster than pause quanta to ensure that link
1592 * partner won't send traffic if port is in XOFF mode.
1594 static void mvpp22_gop_fca_set_periodic_timer(struct mvpp2_port *port)
1598 timer = (port->priv->tclk / (USEC_PER_SEC * FC_CLK_DIVIDER))
1601 mvpp22_gop_fca_enable_periodic(port, false);
1603 mvpp22_gop_fca_set_timer(port, timer);
1605 mvpp22_gop_fca_enable_periodic(port, true);
1608 static int mvpp22_gop_init(struct mvpp2_port *port)
1610 struct mvpp2 *priv = port->priv;
1613 if (!priv->sysctrl_base)
1616 switch (port->phy_interface) {
1617 case PHY_INTERFACE_MODE_RGMII:
1618 case PHY_INTERFACE_MODE_RGMII_ID:
1619 case PHY_INTERFACE_MODE_RGMII_RXID:
1620 case PHY_INTERFACE_MODE_RGMII_TXID:
1621 if (!mvpp2_port_supports_rgmii(port))
1623 mvpp22_gop_init_rgmii(port);
1625 case PHY_INTERFACE_MODE_SGMII:
1626 case PHY_INTERFACE_MODE_1000BASEX:
1627 case PHY_INTERFACE_MODE_2500BASEX:
1628 mvpp22_gop_init_sgmii(port);
1630 case PHY_INTERFACE_MODE_10GBASER:
1631 if (!mvpp2_port_supports_xlg(port))
1633 mvpp22_gop_init_10gkr(port);
1636 goto unsupported_conf;
1639 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val);
1640 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) |
1641 GENCONF_PORT_CTRL1_EN(port->gop_id);
1642 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val);
1644 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1645 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR;
1646 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1648 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val);
1649 val |= GENCONF_SOFT_RESET1_GOP;
1650 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val);
1652 mvpp22_gop_fca_set_periodic_timer(port);
1658 netdev_err(port->dev, "Invalid port configuration\n");
1662 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
1666 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1667 phy_interface_mode_is_8023z(port->phy_interface) ||
1668 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1669 /* Enable the GMAC link status irq for this port */
1670 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1671 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1672 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1675 if (mvpp2_port_supports_xlg(port)) {
1676 /* Enable the XLG/GIG irqs for this port */
1677 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1678 if (mvpp2_is_xlg(port->phy_interface))
1679 val |= MVPP22_XLG_EXT_INT_MASK_XLG;
1681 val |= MVPP22_XLG_EXT_INT_MASK_GIG;
1682 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1686 static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
1690 if (mvpp2_port_supports_xlg(port)) {
1691 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1692 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG |
1693 MVPP22_XLG_EXT_INT_MASK_GIG);
1694 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1697 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1698 phy_interface_mode_is_8023z(port->phy_interface) ||
1699 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1700 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1701 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1702 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1706 static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
1710 mvpp2_modify(port->base + MVPP22_GMAC_INT_SUM_MASK,
1711 MVPP22_GMAC_INT_SUM_MASK_PTP,
1712 MVPP22_GMAC_INT_SUM_MASK_PTP);
1714 if (port->phylink ||
1715 phy_interface_mode_is_rgmii(port->phy_interface) ||
1716 phy_interface_mode_is_8023z(port->phy_interface) ||
1717 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
1718 val = readl(port->base + MVPP22_GMAC_INT_MASK);
1719 val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
1720 writel(val, port->base + MVPP22_GMAC_INT_MASK);
1723 if (mvpp2_port_supports_xlg(port)) {
1724 val = readl(port->base + MVPP22_XLG_INT_MASK);
1725 val |= MVPP22_XLG_INT_MASK_LINK;
1726 writel(val, port->base + MVPP22_XLG_INT_MASK);
1728 mvpp2_modify(port->base + MVPP22_XLG_EXT_INT_MASK,
1729 MVPP22_XLG_EXT_INT_MASK_PTP,
1730 MVPP22_XLG_EXT_INT_MASK_PTP);
1733 mvpp22_gop_unmask_irq(port);
1736 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes).
1738 * The PHY mode used by the PPv2 driver comes from the network subsystem, while
1739 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they
1742 * The COMPHY configures the serdes lanes regardless of the actual use of the
1743 * lanes by the physical layer. This is why configurations like
1744 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid.
1746 static int mvpp22_comphy_init(struct mvpp2_port *port)
1753 ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET,
1754 port->phy_interface);
1758 return phy_power_on(port->comphy);
1761 static void mvpp2_port_enable(struct mvpp2_port *port)
1765 if (mvpp2_port_supports_xlg(port) &&
1766 mvpp2_is_xlg(port->phy_interface)) {
1767 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1768 val |= MVPP22_XLG_CTRL0_PORT_EN;
1769 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS;
1770 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1772 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1773 val |= MVPP2_GMAC_PORT_EN_MASK;
1774 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
1775 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1779 static void mvpp2_port_disable(struct mvpp2_port *port)
1783 if (mvpp2_port_supports_xlg(port) &&
1784 mvpp2_is_xlg(port->phy_interface)) {
1785 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1786 val &= ~MVPP22_XLG_CTRL0_PORT_EN;
1787 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1790 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1791 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
1792 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1795 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
1796 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
1800 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
1801 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
1802 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1805 /* Configure loopback port */
1806 static void mvpp2_port_loopback_set(struct mvpp2_port *port,
1807 const struct phylink_link_state *state)
1811 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
1813 if (state->speed == 1000)
1814 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
1816 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
1818 if (phy_interface_mode_is_8023z(state->interface) ||
1819 state->interface == PHY_INTERFACE_MODE_SGMII)
1820 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
1822 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
1824 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1828 ETHTOOL_XDP_REDIRECT,
1834 ETHTOOL_XDP_XMIT_ERR,
1837 struct mvpp2_ethtool_counter {
1838 unsigned int offset;
1839 const char string[ETH_GSTRING_LEN];
1843 static u64 mvpp2_read_count(struct mvpp2_port *port,
1844 const struct mvpp2_ethtool_counter *counter)
1848 val = readl(port->stats_base + counter->offset);
1849 if (counter->reg_is_64b)
1850 val += (u64)readl(port->stats_base + counter->offset + 4) << 32;
1855 /* Some counters are accessed indirectly by first writing an index to
1856 * MVPP2_CTRS_IDX. The index can represent various resources depending on the
1857 * register we access, it can be a hit counter for some classification tables,
1858 * a counter specific to a rxq, a txq or a buffer pool.
1860 static u32 mvpp2_read_index(struct mvpp2 *priv, u32 index, u32 reg)
1862 mvpp2_write(priv, MVPP2_CTRS_IDX, index);
1863 return mvpp2_read(priv, reg);
1866 /* Due to the fact that software statistics and hardware statistics are, by
1867 * design, incremented at different moments in the chain of packet processing,
1868 * it is very likely that incoming packets could have been dropped after being
1869 * counted by hardware but before reaching software statistics (most probably
1870 * multicast packets), and in the oppposite way, during transmission, FCS bytes
1871 * are added in between as well as TSO skb will be split and header bytes added.
1872 * Hence, statistics gathered from userspace with ifconfig (software) and
1873 * ethtool (hardware) cannot be compared.
1875 static const struct mvpp2_ethtool_counter mvpp2_ethtool_mib_regs[] = {
1876 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true },
1877 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" },
1878 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" },
1879 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" },
1880 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" },
1881 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" },
1882 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" },
1883 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" },
1884 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" },
1885 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" },
1886 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" },
1887 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" },
1888 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true },
1889 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" },
1890 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" },
1891 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" },
1892 { MVPP2_MIB_FC_SENT, "fc_sent" },
1893 { MVPP2_MIB_FC_RCVD, "fc_received" },
1894 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" },
1895 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" },
1896 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" },
1897 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" },
1898 { MVPP2_MIB_JABBER_RCVD, "jabber_received" },
1899 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" },
1900 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" },
1901 { MVPP2_MIB_COLLISION, "collision" },
1902 { MVPP2_MIB_LATE_COLLISION, "late_collision" },
1905 static const struct mvpp2_ethtool_counter mvpp2_ethtool_port_regs[] = {
1906 { MVPP2_OVERRUN_ETH_DROP, "rx_fifo_or_parser_overrun_drops" },
1907 { MVPP2_CLS_ETH_DROP, "rx_classifier_drops" },
1910 static const struct mvpp2_ethtool_counter mvpp2_ethtool_txq_regs[] = {
1911 { MVPP2_TX_DESC_ENQ_CTR, "txq_%d_desc_enqueue" },
1912 { MVPP2_TX_DESC_ENQ_TO_DDR_CTR, "txq_%d_desc_enqueue_to_ddr" },
1913 { MVPP2_TX_BUFF_ENQ_TO_DDR_CTR, "txq_%d_buff_euqueue_to_ddr" },
1914 { MVPP2_TX_DESC_ENQ_HW_FWD_CTR, "txq_%d_desc_hardware_forwarded" },
1915 { MVPP2_TX_PKTS_DEQ_CTR, "txq_%d_packets_dequeued" },
1916 { MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR, "txq_%d_queue_full_drops" },
1917 { MVPP2_TX_PKTS_EARLY_DROP_CTR, "txq_%d_packets_early_drops" },
1918 { MVPP2_TX_PKTS_BM_DROP_CTR, "txq_%d_packets_bm_drops" },
1919 { MVPP2_TX_PKTS_BM_MC_DROP_CTR, "txq_%d_packets_rep_bm_drops" },
1922 static const struct mvpp2_ethtool_counter mvpp2_ethtool_rxq_regs[] = {
1923 { MVPP2_RX_DESC_ENQ_CTR, "rxq_%d_desc_enqueue" },
1924 { MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR, "rxq_%d_queue_full_drops" },
1925 { MVPP2_RX_PKTS_EARLY_DROP_CTR, "rxq_%d_packets_early_drops" },
1926 { MVPP2_RX_PKTS_BM_DROP_CTR, "rxq_%d_packets_bm_drops" },
1929 static const struct mvpp2_ethtool_counter mvpp2_ethtool_xdp[] = {
1930 { ETHTOOL_XDP_REDIRECT, "rx_xdp_redirect", },
1931 { ETHTOOL_XDP_PASS, "rx_xdp_pass", },
1932 { ETHTOOL_XDP_DROP, "rx_xdp_drop", },
1933 { ETHTOOL_XDP_TX, "rx_xdp_tx", },
1934 { ETHTOOL_XDP_TX_ERR, "rx_xdp_tx_errors", },
1935 { ETHTOOL_XDP_XMIT, "tx_xdp_xmit", },
1936 { ETHTOOL_XDP_XMIT_ERR, "tx_xdp_xmit_errors", },
1939 #define MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs) (ARRAY_SIZE(mvpp2_ethtool_mib_regs) + \
1940 ARRAY_SIZE(mvpp2_ethtool_port_regs) + \
1941 (ARRAY_SIZE(mvpp2_ethtool_txq_regs) * (ntxqs)) + \
1942 (ARRAY_SIZE(mvpp2_ethtool_rxq_regs) * (nrxqs)) + \
1943 ARRAY_SIZE(mvpp2_ethtool_xdp))
1945 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset,
1948 struct mvpp2_port *port = netdev_priv(netdev);
1951 if (sset != ETH_SS_STATS)
1954 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) {
1955 strscpy(data, mvpp2_ethtool_mib_regs[i].string,
1957 data += ETH_GSTRING_LEN;
1960 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) {
1961 strscpy(data, mvpp2_ethtool_port_regs[i].string,
1963 data += ETH_GSTRING_LEN;
1966 for (q = 0; q < port->ntxqs; q++) {
1967 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) {
1968 snprintf(data, ETH_GSTRING_LEN,
1969 mvpp2_ethtool_txq_regs[i].string, q);
1970 data += ETH_GSTRING_LEN;
1974 for (q = 0; q < port->nrxqs; q++) {
1975 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) {
1976 snprintf(data, ETH_GSTRING_LEN,
1977 mvpp2_ethtool_rxq_regs[i].string,
1979 data += ETH_GSTRING_LEN;
1983 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_xdp); i++) {
1984 strscpy(data, mvpp2_ethtool_xdp[i].string,
1986 data += ETH_GSTRING_LEN;
1991 mvpp2_get_xdp_stats(struct mvpp2_port *port, struct mvpp2_pcpu_stats *xdp_stats)
1996 /* Gather XDP Statistics */
1997 for_each_possible_cpu(cpu) {
1998 struct mvpp2_pcpu_stats *cpu_stats;
2007 cpu_stats = per_cpu_ptr(port->stats, cpu);
2009 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
2010 xdp_redirect = cpu_stats->xdp_redirect;
2011 xdp_pass = cpu_stats->xdp_pass;
2012 xdp_drop = cpu_stats->xdp_drop;
2013 xdp_xmit = cpu_stats->xdp_xmit;
2014 xdp_xmit_err = cpu_stats->xdp_xmit_err;
2015 xdp_tx = cpu_stats->xdp_tx;
2016 xdp_tx_err = cpu_stats->xdp_tx_err;
2017 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
2019 xdp_stats->xdp_redirect += xdp_redirect;
2020 xdp_stats->xdp_pass += xdp_pass;
2021 xdp_stats->xdp_drop += xdp_drop;
2022 xdp_stats->xdp_xmit += xdp_xmit;
2023 xdp_stats->xdp_xmit_err += xdp_xmit_err;
2024 xdp_stats->xdp_tx += xdp_tx;
2025 xdp_stats->xdp_tx_err += xdp_tx_err;
2029 static void mvpp2_read_stats(struct mvpp2_port *port)
2031 struct mvpp2_pcpu_stats xdp_stats = {};
2032 const struct mvpp2_ethtool_counter *s;
2036 pstats = port->ethtool_stats;
2038 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++)
2039 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_mib_regs[i]);
2041 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++)
2042 *pstats++ += mvpp2_read(port->priv,
2043 mvpp2_ethtool_port_regs[i].offset +
2046 for (q = 0; q < port->ntxqs; q++)
2047 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++)
2048 *pstats++ += mvpp2_read_index(port->priv,
2049 MVPP22_CTRS_TX_CTR(port->id, q),
2050 mvpp2_ethtool_txq_regs[i].offset);
2052 /* Rxqs are numbered from 0 from the user standpoint, but not from the
2053 * driver's. We need to add the port->first_rxq offset.
2055 for (q = 0; q < port->nrxqs; q++)
2056 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++)
2057 *pstats++ += mvpp2_read_index(port->priv,
2058 port->first_rxq + q,
2059 mvpp2_ethtool_rxq_regs[i].offset);
2061 /* Gather XDP Statistics */
2062 mvpp2_get_xdp_stats(port, &xdp_stats);
2064 for (i = 0, s = mvpp2_ethtool_xdp;
2065 s < mvpp2_ethtool_xdp + ARRAY_SIZE(mvpp2_ethtool_xdp);
2067 switch (s->offset) {
2068 case ETHTOOL_XDP_REDIRECT:
2069 *pstats++ = xdp_stats.xdp_redirect;
2071 case ETHTOOL_XDP_PASS:
2072 *pstats++ = xdp_stats.xdp_pass;
2074 case ETHTOOL_XDP_DROP:
2075 *pstats++ = xdp_stats.xdp_drop;
2077 case ETHTOOL_XDP_TX:
2078 *pstats++ = xdp_stats.xdp_tx;
2080 case ETHTOOL_XDP_TX_ERR:
2081 *pstats++ = xdp_stats.xdp_tx_err;
2083 case ETHTOOL_XDP_XMIT:
2084 *pstats++ = xdp_stats.xdp_xmit;
2086 case ETHTOOL_XDP_XMIT_ERR:
2087 *pstats++ = xdp_stats.xdp_xmit_err;
2093 static void mvpp2_gather_hw_statistics(struct work_struct *work)
2095 struct delayed_work *del_work = to_delayed_work(work);
2096 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port,
2099 mutex_lock(&port->gather_stats_lock);
2101 mvpp2_read_stats(port);
2103 /* No need to read again the counters right after this function if it
2104 * was called asynchronously by the user (ie. use of ethtool).
2106 cancel_delayed_work(&port->stats_work);
2107 queue_delayed_work(port->priv->stats_queue, &port->stats_work,
2108 MVPP2_MIB_COUNTERS_STATS_DELAY);
2110 mutex_unlock(&port->gather_stats_lock);
2113 static void mvpp2_ethtool_get_stats(struct net_device *dev,
2114 struct ethtool_stats *stats, u64 *data)
2116 struct mvpp2_port *port = netdev_priv(dev);
2118 /* Update statistics for the given port, then take the lock to avoid
2119 * concurrent accesses on the ethtool_stats structure during its copy.
2121 mvpp2_gather_hw_statistics(&port->stats_work.work);
2123 mutex_lock(&port->gather_stats_lock);
2124 memcpy(data, port->ethtool_stats,
2125 sizeof(u64) * MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs));
2126 mutex_unlock(&port->gather_stats_lock);
2129 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset)
2131 struct mvpp2_port *port = netdev_priv(dev);
2133 if (sset == ETH_SS_STATS)
2134 return MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs);
2139 static void mvpp2_mac_reset_assert(struct mvpp2_port *port)
2143 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) |
2144 MVPP2_GMAC_PORT_RESET_MASK;
2145 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
2147 if (port->priv->hw_version >= MVPP22 && port->gop_id == 0) {
2148 val = readl(port->base + MVPP22_XLG_CTRL0_REG) &
2149 ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
2150 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
2154 static void mvpp22_pcs_reset_assert(struct mvpp2_port *port)
2156 struct mvpp2 *priv = port->priv;
2157 void __iomem *mpcs, *xpcs;
2160 if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
2163 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
2164 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
2166 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
2167 val &= ~(MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX);
2168 val |= MVPP22_MPCS_CLK_RESET_DIV_SET;
2169 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
2171 val = readl(xpcs + MVPP22_XPCS_CFG0);
2172 writel(val & ~MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
2175 static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port)
2177 struct mvpp2 *priv = port->priv;
2178 void __iomem *mpcs, *xpcs;
2181 if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
2184 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
2185 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
2187 switch (port->phy_interface) {
2188 case PHY_INTERFACE_MODE_10GBASER:
2189 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
2190 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX |
2191 MAC_CLK_RESET_SD_TX;
2192 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET;
2193 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
2195 case PHY_INTERFACE_MODE_XAUI:
2196 case PHY_INTERFACE_MODE_RXAUI:
2197 val = readl(xpcs + MVPP22_XPCS_CFG0);
2198 writel(val | MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0);
2205 /* Change maximum receive size of the port */
2206 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
2210 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
2211 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
2212 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2213 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
2214 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
2217 /* Change maximum receive size of the port */
2218 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port)
2222 val = readl(port->base + MVPP22_XLG_CTRL1_REG);
2223 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK;
2224 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
2225 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS;
2226 writel(val, port->base + MVPP22_XLG_CTRL1_REG);
2229 /* Set defaults to the MVPP2 port */
2230 static void mvpp2_defaults_set(struct mvpp2_port *port)
2232 int tx_port_num, val, queue, lrxq;
2234 if (port->priv->hw_version == MVPP21) {
2235 /* Update TX FIFO MIN Threshold */
2236 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2237 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
2238 /* Min. TX threshold must be less than minimal packet length */
2239 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
2240 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
2243 /* Disable Legacy WRR, Disable EJP, Release from reset */
2244 tx_port_num = mvpp2_egress_port(port);
2245 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
2247 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
2249 /* Set TXQ scheduling to Round-Robin */
2250 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0);
2252 /* Close bandwidth for all queues */
2253 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++)
2254 mvpp2_write(port->priv,
2255 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(queue), 0);
2257 /* Set refill period to 1 usec, refill tokens
2258 * and bucket size to maximum
2260 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,
2261 port->priv->tclk / USEC_PER_SEC);
2262 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
2263 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
2264 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
2265 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
2266 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
2267 val = MVPP2_TXP_TOKEN_SIZE_MAX;
2268 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2270 /* Set MaximumLowLatencyPacketSize value to 256 */
2271 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
2272 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
2273 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
2275 /* Enable Rx cache snoop */
2276 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
2277 queue = port->rxqs[lrxq]->id;
2278 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2279 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
2280 MVPP2_SNOOP_BUF_HDR_MASK;
2281 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2284 /* At default, mask all interrupts to all present cpus */
2285 mvpp2_interrupts_disable(port);
2288 /* Enable/disable receiving packets */
2289 static void mvpp2_ingress_enable(struct mvpp2_port *port)
2294 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
2295 queue = port->rxqs[lrxq]->id;
2296 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2297 val &= ~MVPP2_RXQ_DISABLE_MASK;
2298 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2302 static void mvpp2_ingress_disable(struct mvpp2_port *port)
2307 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
2308 queue = port->rxqs[lrxq]->id;
2309 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
2310 val |= MVPP2_RXQ_DISABLE_MASK;
2311 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
2315 /* Enable transmit via physical egress queue
2316 * - HW starts take descriptors from DRAM
2318 static void mvpp2_egress_enable(struct mvpp2_port *port)
2322 int tx_port_num = mvpp2_egress_port(port);
2324 /* Enable all initialized TXs. */
2326 for (queue = 0; queue < port->ntxqs; queue++) {
2327 struct mvpp2_tx_queue *txq = port->txqs[queue];
2330 qmap |= (1 << queue);
2333 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2334 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
2337 /* Disable transmit via physical egress queue
2338 * - HW doesn't take descriptors from DRAM
2340 static void mvpp2_egress_disable(struct mvpp2_port *port)
2344 int tx_port_num = mvpp2_egress_port(port);
2346 /* Issue stop command for active channels only */
2347 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2348 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
2349 MVPP2_TXP_SCHED_ENQ_MASK;
2351 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
2352 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
2354 /* Wait for all Tx activity to terminate. */
2357 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
2358 netdev_warn(port->dev,
2359 "Tx stop timed out, status=0x%08x\n",
2366 /* Check port TX Command register that all
2367 * Tx queues are stopped
2369 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
2370 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
2373 /* Rx descriptors helper methods */
2375 /* Get number of Rx descriptors occupied by received packets */
2377 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
2379 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
2381 return val & MVPP2_RXQ_OCCUPIED_MASK;
2384 /* Update Rx queue status with the number of occupied and available
2385 * Rx descriptor slots.
2388 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
2389 int used_count, int free_count)
2391 /* Decrement the number of used descriptors and increment count
2392 * increment the number of free descriptors.
2394 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
2396 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
2399 /* Get pointer to next RX descriptor to be processed by SW */
2400 static inline struct mvpp2_rx_desc *
2401 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
2403 int rx_desc = rxq->next_desc_to_proc;
2405 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
2406 prefetch(rxq->descs + rxq->next_desc_to_proc);
2407 return rxq->descs + rx_desc;
2410 /* Set rx queue offset */
2411 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
2412 int prxq, int offset)
2416 /* Convert offset from bytes to units of 32 bytes */
2417 offset = offset >> 5;
2419 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
2420 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
2423 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
2424 MVPP2_RXQ_PACKET_OFFSET_MASK);
2426 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
2429 /* Tx descriptors helper methods */
2431 /* Get pointer to next Tx descriptor to be processed (send) by HW */
2432 static struct mvpp2_tx_desc *
2433 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
2435 int tx_desc = txq->next_desc_to_proc;
2437 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
2438 return txq->descs + tx_desc;
2441 /* Update HW with number of aggregated Tx descriptors to be sent
2443 * Called only from mvpp2_tx(), so migration is disabled, using
2444 * smp_processor_id() is OK.
2446 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
2448 /* aggregated access - relevant TXQ number is written in TX desc */
2449 mvpp2_thread_write(port->priv,
2450 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2451 MVPP2_AGGR_TXQ_UPDATE_REG, pending);
2454 /* Check if there are enough free descriptors in aggregated txq.
2455 * If not, update the number of occupied descriptors and repeat the check.
2457 * Called only from mvpp2_tx(), so migration is disabled, using
2458 * smp_processor_id() is OK.
2460 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port,
2461 struct mvpp2_tx_queue *aggr_txq, int num)
2463 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) {
2464 /* Update number of occupied aggregated Tx descriptors */
2465 unsigned int thread =
2466 mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2467 u32 val = mvpp2_read_relaxed(port->priv,
2468 MVPP2_AGGR_TXQ_STATUS_REG(thread));
2470 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK;
2472 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE)
2478 /* Reserved Tx descriptors allocation request
2480 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called
2481 * only by mvpp2_tx(), so migration is disabled, using
2482 * smp_processor_id() is OK.
2484 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port,
2485 struct mvpp2_tx_queue *txq, int num)
2487 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2488 struct mvpp2 *priv = port->priv;
2491 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num;
2492 mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val);
2494 val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG);
2496 return val & MVPP2_TXQ_RSVD_RSLT_MASK;
2499 /* Check if there are enough reserved descriptors for transmission.
2500 * If not, request chunk of reserved descriptors and check again.
2502 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port,
2503 struct mvpp2_tx_queue *txq,
2504 struct mvpp2_txq_pcpu *txq_pcpu,
2507 int req, desc_count;
2508 unsigned int thread;
2510 if (txq_pcpu->reserved_num >= num)
2513 /* Not enough descriptors reserved! Update the reserved descriptor
2514 * count and check again.
2518 /* Compute total of used descriptors */
2519 for (thread = 0; thread < port->priv->nthreads; thread++) {
2520 struct mvpp2_txq_pcpu *txq_pcpu_aux;
2522 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread);
2523 desc_count += txq_pcpu_aux->count;
2524 desc_count += txq_pcpu_aux->reserved_num;
2527 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num);
2531 (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK)))
2534 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req);
2536 /* OK, the descriptor could have been updated: check again. */
2537 if (txq_pcpu->reserved_num < num)
2542 /* Release the last allocated Tx descriptor. Useful to handle DMA
2543 * mapping failures in the Tx path.
2545 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq)
2547 if (txq->next_desc_to_proc == 0)
2548 txq->next_desc_to_proc = txq->last_desc - 1;
2550 txq->next_desc_to_proc--;
2553 /* Set Tx descriptors fields relevant for CSUM calculation */
2554 static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto,
2555 int ip_hdr_len, int l4_proto)
2559 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
2560 * G_L4_chk, L4_type required only for checksum calculation
2562 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT);
2563 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT);
2564 command |= MVPP2_TXD_IP_CSUM_DISABLE;
2566 if (l3_proto == htons(ETH_P_IP)) {
2567 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */
2568 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */
2570 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */
2573 if (l4_proto == IPPROTO_TCP) {
2574 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */
2575 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
2576 } else if (l4_proto == IPPROTO_UDP) {
2577 command |= MVPP2_TXD_L4_UDP; /* enable UDP */
2578 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
2580 command |= MVPP2_TXD_L4_CSUM_NOT;
2586 /* Get number of sent descriptors and decrement counter.
2587 * The number of sent descriptors is returned.
2590 * Called only from mvpp2_txq_done(), called from mvpp2_tx()
2591 * (migration disabled) and from the TX completion tasklet (migration
2592 * disabled) so using smp_processor_id() is OK.
2594 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
2595 struct mvpp2_tx_queue *txq)
2599 /* Reading status reg resets transmitted descriptor counter */
2600 val = mvpp2_thread_read_relaxed(port->priv,
2601 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2602 MVPP2_TXQ_SENT_REG(txq->id));
2604 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
2605 MVPP2_TRANSMITTED_COUNT_OFFSET;
2608 /* Called through on_each_cpu(), so runs on all CPUs, with migration
2609 * disabled, therefore using smp_processor_id() is OK.
2611 static void mvpp2_txq_sent_counter_clear(void *arg)
2613 struct mvpp2_port *port = arg;
2616 /* If the thread isn't used, don't do anything */
2617 if (smp_processor_id() >= port->priv->nthreads)
2620 for (queue = 0; queue < port->ntxqs; queue++) {
2621 int id = port->txqs[queue]->id;
2623 mvpp2_thread_read(port->priv,
2624 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
2625 MVPP2_TXQ_SENT_REG(id));
2629 /* Set max sizes for Tx queues */
2630 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
2633 int txq, tx_port_num;
2635 mtu = port->pkt_size * 8;
2636 if (mtu > MVPP2_TXP_MTU_MAX)
2637 mtu = MVPP2_TXP_MTU_MAX;
2639 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
2642 /* Indirect access to registers */
2643 tx_port_num = mvpp2_egress_port(port);
2644 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2647 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
2648 val &= ~MVPP2_TXP_MTU_MAX;
2650 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
2652 /* TXP token size and all TXQs token size must be larger that MTU */
2653 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
2654 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
2657 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
2659 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
2662 for (txq = 0; txq < port->ntxqs; txq++) {
2663 val = mvpp2_read(port->priv,
2664 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
2665 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
2669 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
2671 mvpp2_write(port->priv,
2672 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
2678 /* Set the number of non-occupied descriptors threshold */
2679 static void mvpp2_set_rxq_free_tresh(struct mvpp2_port *port,
2680 struct mvpp2_rx_queue *rxq)
2684 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
2686 val = mvpp2_read(port->priv, MVPP2_RXQ_THRESH_REG);
2687 val &= ~MVPP2_RXQ_NON_OCCUPIED_MASK;
2688 val |= MSS_THRESHOLD_STOP << MVPP2_RXQ_NON_OCCUPIED_OFFSET;
2689 mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val);
2692 /* Set the number of packets that will be received before Rx interrupt
2693 * will be generated by HW.
2695 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
2696 struct mvpp2_rx_queue *rxq)
2698 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2700 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)
2701 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;
2703 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2704 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG,
2710 /* For some reason in the LSP this is done on each CPU. Why ? */
2711 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port,
2712 struct mvpp2_tx_queue *txq)
2714 unsigned int thread;
2717 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK)
2718 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK;
2720 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET);
2721 /* PKT-coalescing registers are per-queue + per-thread */
2722 for (thread = 0; thread < MVPP2_MAX_THREADS; thread++) {
2723 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2724 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val);
2728 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
2730 u64 tmp = (u64)clk_hz * usec;
2732 do_div(tmp, USEC_PER_SEC);
2734 return tmp > U32_MAX ? U32_MAX : tmp;
2737 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz)
2739 u64 tmp = (u64)cycles * USEC_PER_SEC;
2741 do_div(tmp, clk_hz);
2743 return tmp > U32_MAX ? U32_MAX : tmp;
2746 /* Set the time delay in usec before Rx interrupt */
2747 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port,
2748 struct mvpp2_rx_queue *rxq)
2750 unsigned long freq = port->priv->tclk;
2751 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
2753 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) {
2755 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq);
2757 /* re-evaluate to get actual register value */
2758 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
2761 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
2764 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port)
2766 unsigned long freq = port->priv->tclk;
2767 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
2769 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) {
2770 port->tx_time_coal =
2771 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq);
2773 /* re-evaluate to get actual register value */
2774 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
2777 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val);
2780 /* Free Tx queue skbuffs */
2781 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
2782 struct mvpp2_tx_queue *txq,
2783 struct mvpp2_txq_pcpu *txq_pcpu, int num)
2785 struct xdp_frame_bulk bq;
2788 xdp_frame_bulk_init(&bq);
2790 rcu_read_lock(); /* need for xdp_return_frame_bulk */
2792 for (i = 0; i < num; i++) {
2793 struct mvpp2_txq_pcpu_buf *tx_buf =
2794 txq_pcpu->buffs + txq_pcpu->txq_get_index;
2796 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma) &&
2797 tx_buf->type != MVPP2_TYPE_XDP_TX)
2798 dma_unmap_single(port->dev->dev.parent, tx_buf->dma,
2799 tx_buf->size, DMA_TO_DEVICE);
2800 if (tx_buf->type == MVPP2_TYPE_SKB && tx_buf->skb)
2801 dev_kfree_skb_any(tx_buf->skb);
2802 else if (tx_buf->type == MVPP2_TYPE_XDP_TX ||
2803 tx_buf->type == MVPP2_TYPE_XDP_NDO)
2804 xdp_return_frame_bulk(tx_buf->xdpf, &bq);
2806 mvpp2_txq_inc_get(txq_pcpu);
2808 xdp_flush_frame_bulk(&bq);
2813 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
2816 int queue = fls(cause) - 1;
2818 return port->rxqs[queue];
2821 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
2824 int queue = fls(cause) - 1;
2826 return port->txqs[queue];
2829 /* Handle end of transmission */
2830 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
2831 struct mvpp2_txq_pcpu *txq_pcpu)
2833 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id);
2836 if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id()))
2837 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n");
2839 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
2842 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done);
2844 txq_pcpu->count -= tx_done;
2846 if (netif_tx_queue_stopped(nq))
2847 if (txq_pcpu->count <= txq_pcpu->wake_threshold)
2848 netif_tx_wake_queue(nq);
2851 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause,
2852 unsigned int thread)
2854 struct mvpp2_tx_queue *txq;
2855 struct mvpp2_txq_pcpu *txq_pcpu;
2856 unsigned int tx_todo = 0;
2859 txq = mvpp2_get_tx_queue(port, cause);
2863 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2865 if (txq_pcpu->count) {
2866 mvpp2_txq_done(port, txq, txq_pcpu);
2867 tx_todo += txq_pcpu->count;
2870 cause &= ~(1 << txq->log_id);
2875 /* Rx/Tx queue initialization/cleanup methods */
2877 /* Allocate and initialize descriptors for aggr TXQ */
2878 static int mvpp2_aggr_txq_init(struct platform_device *pdev,
2879 struct mvpp2_tx_queue *aggr_txq,
2880 unsigned int thread, struct mvpp2 *priv)
2884 /* Allocate memory for TX descriptors */
2885 aggr_txq->descs = dma_alloc_coherent(&pdev->dev,
2886 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
2887 &aggr_txq->descs_dma, GFP_KERNEL);
2888 if (!aggr_txq->descs)
2891 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1;
2893 /* Aggr TXQ no reset WA */
2894 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
2895 MVPP2_AGGR_TXQ_INDEX_REG(thread));
2897 /* Set Tx descriptors queue starting address indirect
2900 if (priv->hw_version == MVPP21)
2901 txq_dma = aggr_txq->descs_dma;
2903 txq_dma = aggr_txq->descs_dma >>
2904 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
2906 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma);
2907 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread),
2908 MVPP2_AGGR_TXQ_SIZE);
2913 /* Create a specified Rx queue */
2914 static int mvpp2_rxq_init(struct mvpp2_port *port,
2915 struct mvpp2_rx_queue *rxq)
2917 struct mvpp2 *priv = port->priv;
2918 unsigned int thread;
2922 rxq->size = port->rx_ring_size;
2924 /* Allocate memory for RX descriptors */
2925 rxq->descs = dma_alloc_coherent(port->dev->dev.parent,
2926 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2927 &rxq->descs_dma, GFP_KERNEL);
2931 rxq->last_desc = rxq->size - 1;
2933 /* Zero occupied and non-occupied counters - direct access */
2934 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2936 /* Set Rx descriptors queue starting address - indirect access */
2937 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2938 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2939 if (port->priv->hw_version == MVPP21)
2940 rxq_dma = rxq->descs_dma;
2942 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
2943 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
2944 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
2945 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0);
2949 mvpp2_rxq_offset_set(port, rxq->id, MVPP2_SKB_HEADROOM);
2951 /* Set coalescing pkts and time */
2952 mvpp2_rx_pkts_coal_set(port, rxq);
2953 mvpp2_rx_time_coal_set(port, rxq);
2955 /* Set the number of non occupied descriptors threshold */
2956 mvpp2_set_rxq_free_tresh(port, rxq);
2958 /* Add number of descriptors ready for receiving packets */
2959 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
2961 if (priv->percpu_pools) {
2962 err = xdp_rxq_info_reg(&rxq->xdp_rxq_short, port->dev, rxq->id, 0);
2966 err = xdp_rxq_info_reg(&rxq->xdp_rxq_long, port->dev, rxq->id, 0);
2968 goto err_unregister_rxq_short;
2970 /* Every RXQ has a pool for short and another for long packets */
2971 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_short,
2973 priv->page_pool[rxq->logic_rxq]);
2975 goto err_unregister_rxq_long;
2977 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_long,
2979 priv->page_pool[rxq->logic_rxq +
2982 goto err_unregister_mem_rxq_short;
2987 err_unregister_mem_rxq_short:
2988 xdp_rxq_info_unreg_mem_model(&rxq->xdp_rxq_short);
2989 err_unregister_rxq_long:
2990 xdp_rxq_info_unreg(&rxq->xdp_rxq_long);
2991 err_unregister_rxq_short:
2992 xdp_rxq_info_unreg(&rxq->xdp_rxq_short);
2994 dma_free_coherent(port->dev->dev.parent,
2995 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2996 rxq->descs, rxq->descs_dma);
3000 /* Push packets received by the RXQ to BM pool */
3001 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
3002 struct mvpp2_rx_queue *rxq)
3006 rx_received = mvpp2_rxq_received(port, rxq->id);
3010 for (i = 0; i < rx_received; i++) {
3011 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
3012 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
3015 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >>
3016 MVPP2_RXD_BM_POOL_ID_OFFS;
3018 mvpp2_bm_pool_put(port, pool,
3019 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
3020 mvpp2_rxdesc_cookie_get(port, rx_desc));
3022 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
3025 /* Cleanup Rx queue */
3026 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
3027 struct mvpp2_rx_queue *rxq)
3029 unsigned int thread;
3031 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_short))
3032 xdp_rxq_info_unreg(&rxq->xdp_rxq_short);
3034 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_long))
3035 xdp_rxq_info_unreg(&rxq->xdp_rxq_long);
3037 mvpp2_rxq_drop_pkts(port, rxq);
3040 dma_free_coherent(port->dev->dev.parent,
3041 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
3047 rxq->next_desc_to_proc = 0;
3050 /* Clear Rx descriptors queue starting address and size;
3051 * free descriptor number
3053 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
3054 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3055 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
3056 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0);
3057 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0);
3061 /* Create and initialize a Tx queue */
3062 static int mvpp2_txq_init(struct mvpp2_port *port,
3063 struct mvpp2_tx_queue *txq)
3066 unsigned int thread;
3067 int desc, desc_per_txq, tx_port_num;
3068 struct mvpp2_txq_pcpu *txq_pcpu;
3070 txq->size = port->tx_ring_size;
3072 /* Allocate memory for Tx descriptors */
3073 txq->descs = dma_alloc_coherent(port->dev->dev.parent,
3074 txq->size * MVPP2_DESC_ALIGNED_SIZE,
3075 &txq->descs_dma, GFP_KERNEL);
3079 txq->last_desc = txq->size - 1;
3081 /* Set Tx descriptors queue starting address - indirect access */
3082 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3083 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
3084 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG,
3086 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG,
3087 txq->size & MVPP2_TXQ_DESC_SIZE_MASK);
3088 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0);
3089 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG,
3090 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
3091 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG);
3092 val &= ~MVPP2_TXQ_PENDING_MASK;
3093 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val);
3095 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
3096 * for each existing TXQ.
3097 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
3098 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS
3101 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
3102 (txq->log_id * desc_per_txq);
3104 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG,
3105 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
3106 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
3109 /* WRR / EJP configuration - indirect access */
3110 tx_port_num = mvpp2_egress_port(port);
3111 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
3113 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
3114 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
3115 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
3116 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
3117 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
3119 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
3120 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
3123 for (thread = 0; thread < port->priv->nthreads; thread++) {
3124 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3125 txq_pcpu->size = txq->size;
3126 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size,
3127 sizeof(*txq_pcpu->buffs),
3129 if (!txq_pcpu->buffs)
3132 txq_pcpu->count = 0;
3133 txq_pcpu->reserved_num = 0;
3134 txq_pcpu->txq_put_index = 0;
3135 txq_pcpu->txq_get_index = 0;
3136 txq_pcpu->tso_headers = NULL;
3138 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS;
3139 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2;
3141 txq_pcpu->tso_headers =
3142 dma_alloc_coherent(port->dev->dev.parent,
3143 txq_pcpu->size * TSO_HEADER_SIZE,
3144 &txq_pcpu->tso_headers_dma,
3146 if (!txq_pcpu->tso_headers)
3153 /* Free allocated TXQ resources */
3154 static void mvpp2_txq_deinit(struct mvpp2_port *port,
3155 struct mvpp2_tx_queue *txq)
3157 struct mvpp2_txq_pcpu *txq_pcpu;
3158 unsigned int thread;
3160 for (thread = 0; thread < port->priv->nthreads; thread++) {
3161 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3162 kfree(txq_pcpu->buffs);
3164 if (txq_pcpu->tso_headers)
3165 dma_free_coherent(port->dev->dev.parent,
3166 txq_pcpu->size * TSO_HEADER_SIZE,
3167 txq_pcpu->tso_headers,
3168 txq_pcpu->tso_headers_dma);
3170 txq_pcpu->tso_headers = NULL;
3174 dma_free_coherent(port->dev->dev.parent,
3175 txq->size * MVPP2_DESC_ALIGNED_SIZE,
3176 txq->descs, txq->descs_dma);
3180 txq->next_desc_to_proc = 0;
3183 /* Set minimum bandwidth for disabled TXQs */
3184 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0);
3186 /* Set Tx descriptors queue starting address and size */
3187 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3188 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
3189 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0);
3190 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0);
3194 /* Cleanup Tx ports */
3195 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
3197 struct mvpp2_txq_pcpu *txq_pcpu;
3199 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
3202 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
3203 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG);
3204 val |= MVPP2_TXQ_DRAIN_EN_MASK;
3205 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
3207 /* The napi queue has been stopped so wait for all packets
3208 * to be transmitted.
3212 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
3213 netdev_warn(port->dev,
3214 "port %d: cleaning queue %d timed out\n",
3215 port->id, txq->log_id);
3221 pending = mvpp2_thread_read(port->priv, thread,
3222 MVPP2_TXQ_PENDING_REG);
3223 pending &= MVPP2_TXQ_PENDING_MASK;
3226 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
3227 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
3230 for (thread = 0; thread < port->priv->nthreads; thread++) {
3231 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3233 /* Release all packets */
3234 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
3237 txq_pcpu->count = 0;
3238 txq_pcpu->txq_put_index = 0;
3239 txq_pcpu->txq_get_index = 0;
3243 /* Cleanup all Tx queues */
3244 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
3246 struct mvpp2_tx_queue *txq;
3250 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
3252 /* Reset Tx ports and delete Tx queues */
3253 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
3254 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3256 for (queue = 0; queue < port->ntxqs; queue++) {
3257 txq = port->txqs[queue];
3258 mvpp2_txq_clean(port, txq);
3259 mvpp2_txq_deinit(port, txq);
3262 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
3264 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
3265 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
3268 /* Cleanup all Rx queues */
3269 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
3273 for (queue = 0; queue < port->nrxqs; queue++)
3274 mvpp2_rxq_deinit(port, port->rxqs[queue]);
3277 mvpp2_rxq_disable_fc(port);
3280 /* Init all Rx queues for port */
3281 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
3285 for (queue = 0; queue < port->nrxqs; queue++) {
3286 err = mvpp2_rxq_init(port, port->rxqs[queue]);
3292 mvpp2_rxq_enable_fc(port);
3297 mvpp2_cleanup_rxqs(port);
3301 /* Init all tx queues for port */
3302 static int mvpp2_setup_txqs(struct mvpp2_port *port)
3304 struct mvpp2_tx_queue *txq;
3307 for (queue = 0; queue < port->ntxqs; queue++) {
3308 txq = port->txqs[queue];
3309 err = mvpp2_txq_init(port, txq);
3313 /* Assign this queue to a CPU */
3314 if (queue < num_possible_cpus())
3315 netif_set_xps_queue(port->dev, cpumask_of(queue), queue);
3318 if (port->has_tx_irqs) {
3319 mvpp2_tx_time_coal_set(port);
3320 for (queue = 0; queue < port->ntxqs; queue++) {
3321 txq = port->txqs[queue];
3322 mvpp2_tx_pkts_coal_set(port, txq);
3326 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
3330 mvpp2_cleanup_txqs(port);
3334 /* The callback for per-port interrupt */
3335 static irqreturn_t mvpp2_isr(int irq, void *dev_id)
3337 struct mvpp2_queue_vector *qv = dev_id;
3339 mvpp2_qvec_interrupt_disable(qv);
3341 napi_schedule(&qv->napi);
3346 static void mvpp2_isr_handle_ptp_queue(struct mvpp2_port *port, int nq)
3348 struct skb_shared_hwtstamps shhwtstamps;
3349 struct mvpp2_hwtstamp_queue *queue;
3350 struct sk_buff *skb;
3351 void __iomem *ptp_q;
3355 ptp_q = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
3357 ptp_q += MVPP22_PTP_TX_Q1_R0 - MVPP22_PTP_TX_Q0_R0;
3359 queue = &port->tx_hwtstamp_queue[nq];
3362 r0 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R0) & 0xffff;
3366 r1 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R1) & 0xffff;
3367 r2 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R2) & 0xffff;
3369 id = (r0 >> 1) & 31;
3371 skb = queue->skb[id];
3372 queue->skb[id] = NULL;
3374 u32 ts = r2 << 19 | r1 << 3 | r0 >> 13;
3376 mvpp22_tai_tstamp(port->priv->tai, ts, &shhwtstamps);
3377 skb_tstamp_tx(skb, &shhwtstamps);
3378 dev_kfree_skb_any(skb);
3383 static void mvpp2_isr_handle_ptp(struct mvpp2_port *port)
3388 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
3389 val = readl(ptp + MVPP22_PTP_INT_CAUSE);
3390 if (val & MVPP22_PTP_INT_CAUSE_QUEUE0)
3391 mvpp2_isr_handle_ptp_queue(port, 0);
3392 if (val & MVPP22_PTP_INT_CAUSE_QUEUE1)
3393 mvpp2_isr_handle_ptp_queue(port, 1);
3396 static void mvpp2_isr_handle_link(struct mvpp2_port *port, bool link)
3398 struct net_device *dev = port->dev;
3400 if (port->phylink) {
3401 phylink_mac_change(port->phylink, link);
3405 if (!netif_running(dev))
3409 mvpp2_interrupts_enable(port);
3411 mvpp2_egress_enable(port);
3412 mvpp2_ingress_enable(port);
3413 netif_carrier_on(dev);
3414 netif_tx_wake_all_queues(dev);
3416 netif_tx_stop_all_queues(dev);
3417 netif_carrier_off(dev);
3418 mvpp2_ingress_disable(port);
3419 mvpp2_egress_disable(port);
3421 mvpp2_interrupts_disable(port);
3425 static void mvpp2_isr_handle_xlg(struct mvpp2_port *port)
3430 val = readl(port->base + MVPP22_XLG_INT_STAT);
3431 if (val & MVPP22_XLG_INT_STAT_LINK) {
3432 val = readl(port->base + MVPP22_XLG_STATUS);
3433 link = (val & MVPP22_XLG_STATUS_LINK_UP);
3434 mvpp2_isr_handle_link(port, link);
3438 static void mvpp2_isr_handle_gmac_internal(struct mvpp2_port *port)
3443 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
3444 phy_interface_mode_is_8023z(port->phy_interface) ||
3445 port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
3446 val = readl(port->base + MVPP22_GMAC_INT_STAT);
3447 if (val & MVPP22_GMAC_INT_STAT_LINK) {
3448 val = readl(port->base + MVPP2_GMAC_STATUS0);
3449 link = (val & MVPP2_GMAC_STATUS0_LINK_UP);
3450 mvpp2_isr_handle_link(port, link);
3455 /* Per-port interrupt for link status changes */
3456 static irqreturn_t mvpp2_port_isr(int irq, void *dev_id)
3458 struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
3461 mvpp22_gop_mask_irq(port);
3463 if (mvpp2_port_supports_xlg(port) &&
3464 mvpp2_is_xlg(port->phy_interface)) {
3465 /* Check the external status register */
3466 val = readl(port->base + MVPP22_XLG_EXT_INT_STAT);
3467 if (val & MVPP22_XLG_EXT_INT_STAT_XLG)
3468 mvpp2_isr_handle_xlg(port);
3469 if (val & MVPP22_XLG_EXT_INT_STAT_PTP)
3470 mvpp2_isr_handle_ptp(port);
3472 /* If it's not the XLG, we must be using the GMAC.
3473 * Check the summary status.
3475 val = readl(port->base + MVPP22_GMAC_INT_SUM_STAT);
3476 if (val & MVPP22_GMAC_INT_SUM_STAT_INTERNAL)
3477 mvpp2_isr_handle_gmac_internal(port);
3478 if (val & MVPP22_GMAC_INT_SUM_STAT_PTP)
3479 mvpp2_isr_handle_ptp(port);
3482 mvpp22_gop_unmask_irq(port);
3486 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer)
3488 struct net_device *dev;
3489 struct mvpp2_port *port;
3490 struct mvpp2_port_pcpu *port_pcpu;
3491 unsigned int tx_todo, cause;
3493 port_pcpu = container_of(timer, struct mvpp2_port_pcpu, tx_done_timer);
3494 dev = port_pcpu->dev;
3496 if (!netif_running(dev))
3497 return HRTIMER_NORESTART;
3499 port_pcpu->timer_scheduled = false;
3500 port = netdev_priv(dev);
3502 /* Process all the Tx queues */
3503 cause = (1 << port->ntxqs) - 1;
3504 tx_todo = mvpp2_tx_done(port, cause,
3505 mvpp2_cpu_to_thread(port->priv, smp_processor_id()));
3507 /* Set the timer in case not all the packets were processed */
3508 if (tx_todo && !port_pcpu->timer_scheduled) {
3509 port_pcpu->timer_scheduled = true;
3510 hrtimer_forward_now(&port_pcpu->tx_done_timer,
3511 MVPP2_TXDONE_HRTIMER_PERIOD_NS);
3513 return HRTIMER_RESTART;
3515 return HRTIMER_NORESTART;
3518 /* Main RX/TX processing routines */
3520 /* Display more error info */
3521 static void mvpp2_rx_error(struct mvpp2_port *port,
3522 struct mvpp2_rx_desc *rx_desc)
3524 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
3525 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
3526 char *err_str = NULL;
3528 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
3529 case MVPP2_RXD_ERR_CRC:
3532 case MVPP2_RXD_ERR_OVERRUN:
3533 err_str = "overrun";
3535 case MVPP2_RXD_ERR_RESOURCE:
3536 err_str = "resource";
3539 if (err_str && net_ratelimit())
3540 netdev_err(port->dev,
3541 "bad rx status %08x (%s error), size=%zu\n",
3542 status, err_str, sz);
3545 /* Handle RX checksum offload */
3546 static int mvpp2_rx_csum(struct mvpp2_port *port, u32 status)
3548 if (((status & MVPP2_RXD_L3_IP4) &&
3549 !(status & MVPP2_RXD_IP4_HEADER_ERR)) ||
3550 (status & MVPP2_RXD_L3_IP6))
3551 if (((status & MVPP2_RXD_L4_UDP) ||
3552 (status & MVPP2_RXD_L4_TCP)) &&
3553 (status & MVPP2_RXD_L4_CSUM_OK))
3554 return CHECKSUM_UNNECESSARY;
3556 return CHECKSUM_NONE;
3559 /* Allocate a new skb and add it to BM pool */
3560 static int mvpp2_rx_refill(struct mvpp2_port *port,
3561 struct mvpp2_bm_pool *bm_pool,
3562 struct page_pool *page_pool, int pool)
3564 dma_addr_t dma_addr;
3565 phys_addr_t phys_addr;
3568 buf = mvpp2_buf_alloc(port, bm_pool, page_pool,
3569 &dma_addr, &phys_addr, GFP_ATOMIC);
3573 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
3578 /* Handle tx checksum */
3579 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb)
3581 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3584 __be16 l3_proto = vlan_get_protocol(skb);
3586 if (l3_proto == htons(ETH_P_IP)) {
3587 struct iphdr *ip4h = ip_hdr(skb);
3589 /* Calculate IPv4 checksum and L4 checksum */
3590 ip_hdr_len = ip4h->ihl;
3591 l4_proto = ip4h->protocol;
3592 } else if (l3_proto == htons(ETH_P_IPV6)) {
3593 struct ipv6hdr *ip6h = ipv6_hdr(skb);
3595 /* Read l4_protocol from one of IPv6 extra headers */
3596 if (skb_network_header_len(skb) > 0)
3597 ip_hdr_len = (skb_network_header_len(skb) >> 2);
3598 l4_proto = ip6h->nexthdr;
3600 return MVPP2_TXD_L4_CSUM_NOT;
3603 return mvpp2_txq_desc_csum(skb_network_offset(skb),
3604 l3_proto, ip_hdr_len, l4_proto);
3607 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE;
3610 static void mvpp2_xdp_finish_tx(struct mvpp2_port *port, u16 txq_id, int nxmit, int nxmit_byte)
3612 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3613 struct mvpp2_tx_queue *aggr_txq;
3614 struct mvpp2_txq_pcpu *txq_pcpu;
3615 struct mvpp2_tx_queue *txq;
3616 struct netdev_queue *nq;
3618 txq = port->txqs[txq_id];
3619 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3620 nq = netdev_get_tx_queue(port->dev, txq_id);
3621 aggr_txq = &port->priv->aggr_txqs[thread];
3623 txq_pcpu->reserved_num -= nxmit;
3624 txq_pcpu->count += nxmit;
3625 aggr_txq->count += nxmit;
3627 /* Enable transmit */
3629 mvpp2_aggr_txq_pend_desc_add(port, nxmit);
3631 if (txq_pcpu->count >= txq_pcpu->stop_threshold)
3632 netif_tx_stop_queue(nq);
3634 /* Finalize TX processing */
3635 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
3636 mvpp2_txq_done(port, txq, txq_pcpu);
3640 mvpp2_xdp_submit_frame(struct mvpp2_port *port, u16 txq_id,
3641 struct xdp_frame *xdpf, bool dma_map)
3643 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3644 u32 tx_cmd = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE |
3645 MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
3646 enum mvpp2_tx_buf_type buf_type;
3647 struct mvpp2_txq_pcpu *txq_pcpu;
3648 struct mvpp2_tx_queue *aggr_txq;
3649 struct mvpp2_tx_desc *tx_desc;
3650 struct mvpp2_tx_queue *txq;
3651 int ret = MVPP2_XDP_TX;
3652 dma_addr_t dma_addr;
3654 txq = port->txqs[txq_id];
3655 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
3656 aggr_txq = &port->priv->aggr_txqs[thread];
3658 /* Check number of available descriptors */
3659 if (mvpp2_aggr_desc_num_check(port, aggr_txq, 1) ||
3660 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 1)) {
3661 ret = MVPP2_XDP_DROPPED;
3665 /* Get a descriptor for the first part of the packet */
3666 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
3667 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
3668 mvpp2_txdesc_size_set(port, tx_desc, xdpf->len);
3671 /* XDP_REDIRECT or AF_XDP */
3672 dma_addr = dma_map_single(port->dev->dev.parent, xdpf->data,
3673 xdpf->len, DMA_TO_DEVICE);
3675 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
3676 mvpp2_txq_desc_put(txq);
3677 ret = MVPP2_XDP_DROPPED;
3681 buf_type = MVPP2_TYPE_XDP_NDO;
3684 struct page *page = virt_to_page(xdpf->data);
3686 dma_addr = page_pool_get_dma_addr(page) +
3687 sizeof(*xdpf) + xdpf->headroom;
3688 dma_sync_single_for_device(port->dev->dev.parent, dma_addr,
3689 xdpf->len, DMA_BIDIRECTIONAL);
3691 buf_type = MVPP2_TYPE_XDP_TX;
3694 mvpp2_txdesc_dma_addr_set(port, tx_desc, dma_addr);
3696 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
3697 mvpp2_txq_inc_put(port, txq_pcpu, xdpf, tx_desc, buf_type);
3704 mvpp2_xdp_xmit_back(struct mvpp2_port *port, struct xdp_buff *xdp)
3706 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
3707 struct xdp_frame *xdpf;
3711 xdpf = xdp_convert_buff_to_frame(xdp);
3712 if (unlikely(!xdpf))
3713 return MVPP2_XDP_DROPPED;
3715 /* The first of the TX queues are used for XPS,
3716 * the second half for XDP_TX
3718 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2);
3720 ret = mvpp2_xdp_submit_frame(port, txq_id, xdpf, false);
3721 if (ret == MVPP2_XDP_TX) {
3722 u64_stats_update_begin(&stats->syncp);
3723 stats->tx_bytes += xdpf->len;
3724 stats->tx_packets++;
3726 u64_stats_update_end(&stats->syncp);
3728 mvpp2_xdp_finish_tx(port, txq_id, 1, xdpf->len);
3730 u64_stats_update_begin(&stats->syncp);
3731 stats->xdp_tx_err++;
3732 u64_stats_update_end(&stats->syncp);
3739 mvpp2_xdp_xmit(struct net_device *dev, int num_frame,
3740 struct xdp_frame **frames, u32 flags)
3742 struct mvpp2_port *port = netdev_priv(dev);
3743 int i, nxmit_byte = 0, nxmit = 0;
3744 struct mvpp2_pcpu_stats *stats;
3748 if (unlikely(test_bit(0, &port->state)))
3751 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
3754 /* The first of the TX queues are used for XPS,
3755 * the second half for XDP_TX
3757 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2);
3759 for (i = 0; i < num_frame; i++) {
3760 ret = mvpp2_xdp_submit_frame(port, txq_id, frames[i], true);
3761 if (ret != MVPP2_XDP_TX)
3764 nxmit_byte += frames[i]->len;
3768 if (likely(nxmit > 0))
3769 mvpp2_xdp_finish_tx(port, txq_id, nxmit, nxmit_byte);
3771 stats = this_cpu_ptr(port->stats);
3772 u64_stats_update_begin(&stats->syncp);
3773 stats->tx_bytes += nxmit_byte;
3774 stats->tx_packets += nxmit;
3775 stats->xdp_xmit += nxmit;
3776 stats->xdp_xmit_err += num_frame - nxmit;
3777 u64_stats_update_end(&stats->syncp);
3783 mvpp2_run_xdp(struct mvpp2_port *port, struct bpf_prog *prog,
3784 struct xdp_buff *xdp, struct page_pool *pp,
3785 struct mvpp2_pcpu_stats *stats)
3787 unsigned int len, sync, err;
3791 len = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM;
3792 act = bpf_prog_run_xdp(prog, xdp);
3794 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */
3795 sync = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM;
3796 sync = max(sync, len);
3801 ret = MVPP2_XDP_PASS;
3804 err = xdp_do_redirect(port->dev, xdp, prog);
3805 if (unlikely(err)) {
3806 ret = MVPP2_XDP_DROPPED;
3807 page = virt_to_head_page(xdp->data);
3808 page_pool_put_page(pp, page, sync, true);
3810 ret = MVPP2_XDP_REDIR;
3811 stats->xdp_redirect++;
3815 ret = mvpp2_xdp_xmit_back(port, xdp);
3816 if (ret != MVPP2_XDP_TX) {
3817 page = virt_to_head_page(xdp->data);
3818 page_pool_put_page(pp, page, sync, true);
3822 bpf_warn_invalid_xdp_action(act);
3825 trace_xdp_exception(port->dev, prog, act);
3828 page = virt_to_head_page(xdp->data);
3829 page_pool_put_page(pp, page, sync, true);
3830 ret = MVPP2_XDP_DROPPED;
3838 static void mvpp2_buff_hdr_pool_put(struct mvpp2_port *port, struct mvpp2_rx_desc *rx_desc,
3839 int pool, u32 rx_status)
3841 phys_addr_t phys_addr, phys_addr_next;
3842 dma_addr_t dma_addr, dma_addr_next;
3843 struct mvpp2_buff_hdr *buff_hdr;
3845 phys_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
3846 dma_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
3849 buff_hdr = (struct mvpp2_buff_hdr *)phys_to_virt(phys_addr);
3851 phys_addr_next = le32_to_cpu(buff_hdr->next_phys_addr);
3852 dma_addr_next = le32_to_cpu(buff_hdr->next_dma_addr);
3854 if (port->priv->hw_version >= MVPP22) {
3855 phys_addr_next |= ((u64)buff_hdr->next_phys_addr_high << 32);
3856 dma_addr_next |= ((u64)buff_hdr->next_dma_addr_high << 32);
3859 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
3861 phys_addr = phys_addr_next;
3862 dma_addr = dma_addr_next;
3864 } while (!MVPP2_B_HDR_INFO_IS_LAST(le16_to_cpu(buff_hdr->info)));
3867 /* Main rx processing */
3868 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi,
3869 int rx_todo, struct mvpp2_rx_queue *rxq)
3871 struct net_device *dev = port->dev;
3872 struct mvpp2_pcpu_stats ps = {};
3873 enum dma_data_direction dma_dir;
3874 struct bpf_prog *xdp_prog;
3875 struct xdp_buff xdp;
3880 xdp_prog = READ_ONCE(port->xdp_prog);
3882 /* Get number of received packets and clamp the to-do */
3883 rx_received = mvpp2_rxq_received(port, rxq->id);
3884 if (rx_todo > rx_received)
3885 rx_todo = rx_received;
3887 while (rx_done < rx_todo) {
3888 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
3889 struct mvpp2_bm_pool *bm_pool;
3890 struct page_pool *pp = NULL;
3891 struct sk_buff *skb;
3892 unsigned int frag_size;
3893 dma_addr_t dma_addr;
3894 phys_addr_t phys_addr;
3895 u32 rx_status, timestamp;
3896 int pool, rx_bytes, err, ret;
3900 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
3901 data = (void *)phys_to_virt(phys_addr);
3902 page = virt_to_page(data);
3906 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
3907 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
3908 rx_bytes -= MVPP2_MH_SIZE;
3909 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
3911 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>
3912 MVPP2_RXD_BM_POOL_ID_OFFS;
3913 bm_pool = &port->priv->bm_pools[pool];
3915 if (port->priv->percpu_pools) {
3916 pp = port->priv->page_pool[pool];
3917 dma_dir = page_pool_get_dma_dir(pp);
3919 dma_dir = DMA_FROM_DEVICE;
3922 dma_sync_single_for_cpu(dev->dev.parent, dma_addr,
3923 rx_bytes + MVPP2_MH_SIZE,
3926 /* Buffer header not supported */
3927 if (rx_status & MVPP2_RXD_BUF_HDR)
3928 goto err_drop_frame;
3930 /* In case of an error, release the requested buffer pointer
3931 * to the Buffer Manager. This request process is controlled
3932 * by the hardware, and the information about the buffer is
3933 * comprised by the RX descriptor.
3935 if (rx_status & MVPP2_RXD_ERR_SUMMARY)
3936 goto err_drop_frame;
3938 /* Prefetch header */
3939 prefetch(data + MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM);
3941 if (bm_pool->frag_size > PAGE_SIZE)
3944 frag_size = bm_pool->frag_size;
3947 struct xdp_rxq_info *xdp_rxq;
3949 if (bm_pool->pkt_size == MVPP2_BM_SHORT_PKT_SIZE)
3950 xdp_rxq = &rxq->xdp_rxq_short;
3952 xdp_rxq = &rxq->xdp_rxq_long;
3954 xdp_init_buff(&xdp, PAGE_SIZE, xdp_rxq);
3955 xdp_prepare_buff(&xdp, data,
3956 MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM,
3959 ret = mvpp2_run_xdp(port, xdp_prog, &xdp, pp, &ps);
3963 err = mvpp2_rx_refill(port, bm_pool, pp, pool);
3965 netdev_err(port->dev, "failed to refill BM pools\n");
3966 goto err_drop_frame;
3970 ps.rx_bytes += rx_bytes;
3975 skb = build_skb(data, frag_size);
3977 netdev_warn(port->dev, "skb build failed\n");
3978 goto err_drop_frame;
3981 /* If we have RX hardware timestamping enabled, grab the
3982 * timestamp from the queue and convert.
3984 if (mvpp22_rx_hwtstamping(port)) {
3985 timestamp = le32_to_cpu(rx_desc->pp22.timestamp);
3986 mvpp22_tai_tstamp(port->priv->tai, timestamp,
3987 skb_hwtstamps(skb));
3990 err = mvpp2_rx_refill(port, bm_pool, pp, pool);
3992 netdev_err(port->dev, "failed to refill BM pools\n");
3993 dev_kfree_skb_any(skb);
3994 goto err_drop_frame;
3998 skb_mark_for_recycle(skb, page, pp);
4000 dma_unmap_single_attrs(dev->dev.parent, dma_addr,
4001 bm_pool->buf_size, DMA_FROM_DEVICE,
4002 DMA_ATTR_SKIP_CPU_SYNC);
4005 ps.rx_bytes += rx_bytes;
4007 skb_reserve(skb, MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM);
4008 skb_put(skb, rx_bytes);
4009 skb->ip_summed = mvpp2_rx_csum(port, rx_status);
4010 skb->protocol = eth_type_trans(skb, dev);
4012 napi_gro_receive(napi, skb);
4016 dev->stats.rx_errors++;
4017 mvpp2_rx_error(port, rx_desc);
4018 /* Return the buffer to the pool */
4019 if (rx_status & MVPP2_RXD_BUF_HDR)
4020 mvpp2_buff_hdr_pool_put(port, rx_desc, pool, rx_status);
4022 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
4025 if (xdp_ret & MVPP2_XDP_REDIR)
4028 if (ps.rx_packets) {
4029 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
4031 u64_stats_update_begin(&stats->syncp);
4032 stats->rx_packets += ps.rx_packets;
4033 stats->rx_bytes += ps.rx_bytes;
4035 stats->xdp_redirect += ps.xdp_redirect;
4036 stats->xdp_pass += ps.xdp_pass;
4037 stats->xdp_drop += ps.xdp_drop;
4038 u64_stats_update_end(&stats->syncp);
4041 /* Update Rx queue management counters */
4043 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done);
4049 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
4050 struct mvpp2_tx_desc *desc)
4052 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4053 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
4055 dma_addr_t buf_dma_addr =
4056 mvpp2_txdesc_dma_addr_get(port, desc);
4058 mvpp2_txdesc_size_get(port, desc);
4059 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr))
4060 dma_unmap_single(port->dev->dev.parent, buf_dma_addr,
4061 buf_sz, DMA_TO_DEVICE);
4062 mvpp2_txq_desc_put(txq);
4065 static void mvpp2_txdesc_clear_ptp(struct mvpp2_port *port,
4066 struct mvpp2_tx_desc *desc)
4068 /* We only need to clear the low bits */
4069 if (port->priv->hw_version >= MVPP22)
4070 desc->pp22.ptp_descriptor &=
4071 cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW);
4074 static bool mvpp2_tx_hw_tstamp(struct mvpp2_port *port,
4075 struct mvpp2_tx_desc *tx_desc,
4076 struct sk_buff *skb)
4078 struct mvpp2_hwtstamp_queue *queue;
4079 unsigned int mtype, type, i;
4080 struct ptp_header *hdr;
4083 if (port->priv->hw_version == MVPP21 ||
4084 port->tx_hwtstamp_type == HWTSTAMP_TX_OFF)
4087 type = ptp_classify_raw(skb);
4091 hdr = ptp_parse_header(skb, type);
4095 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4097 ptpdesc = MVPP22_PTP_MACTIMESTAMPINGEN |
4098 MVPP22_PTP_ACTION_CAPTURE;
4099 queue = &port->tx_hwtstamp_queue[0];
4101 switch (type & PTP_CLASS_VMASK) {
4103 ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV1);
4107 ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV2);
4108 mtype = hdr->tsmt & 15;
4109 /* Direct PTP Sync messages to queue 1 */
4111 ptpdesc |= MVPP22_PTP_TIMESTAMPQUEUESELECT;
4112 queue = &port->tx_hwtstamp_queue[1];
4117 /* Take a reference on the skb and insert into our queue */
4119 queue->next = (i + 1) & 31;
4121 dev_kfree_skb_any(queue->skb[i]);
4122 queue->skb[i] = skb_get(skb);
4124 ptpdesc |= MVPP22_PTP_TIMESTAMPENTRYID(i);
4128 * 6:4 - PTPPacketFormat
4129 * 7 - PTP_CF_WraparoundCheckEn
4130 * 9:8 - IngressTimestampSeconds[1:0]
4132 * 11 - MACTimestampingEn
4133 * 17:12 - PTP_TimestampQueueEntryID[5:0]
4134 * 18 - PTPTimestampQueueSelect
4135 * 19 - UDPChecksumUpdateEn
4136 * 27:20 - TimestampOffset
4137 * PTP, NTPTransmit, OWAMP/TWAMP - L3 to PTP header
4138 * NTPTs, Y.1731 - L3 to timestamp entry
4139 * 35:28 - UDP Checksum Offset
4141 * stored in tx descriptor bits 75:64 (11:0) and 191:168 (35:12)
4143 tx_desc->pp22.ptp_descriptor &=
4144 cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW);
4145 tx_desc->pp22.ptp_descriptor |=
4146 cpu_to_le32(ptpdesc & MVPP22_PTP_DESC_MASK_LOW);
4147 tx_desc->pp22.buf_dma_addr_ptp &= cpu_to_le64(~0xffffff0000000000ULL);
4148 tx_desc->pp22.buf_dma_addr_ptp |= cpu_to_le64((ptpdesc >> 12) << 40);
4153 /* Handle tx fragmentation processing */
4154 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
4155 struct mvpp2_tx_queue *aggr_txq,
4156 struct mvpp2_tx_queue *txq)
4158 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4159 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
4160 struct mvpp2_tx_desc *tx_desc;
4162 dma_addr_t buf_dma_addr;
4164 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4165 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4166 void *addr = skb_frag_address(frag);
4168 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4169 mvpp2_txdesc_clear_ptp(port, tx_desc);
4170 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4171 mvpp2_txdesc_size_set(port, tx_desc, skb_frag_size(frag));
4173 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr,
4174 skb_frag_size(frag),
4176 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) {
4177 mvpp2_txq_desc_put(txq);
4181 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
4183 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
4184 /* Last descriptor */
4185 mvpp2_txdesc_cmd_set(port, tx_desc,
4187 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
4189 /* Descriptor in the middle: Not First, Not Last */
4190 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
4191 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4197 /* Release all descriptors that were used to map fragments of
4198 * this packet, as well as the corresponding DMA mappings
4200 for (i = i - 1; i >= 0; i--) {
4201 tx_desc = txq->descs + i;
4202 tx_desc_unmap_put(port, txq, tx_desc);
4208 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb,
4209 struct net_device *dev,
4210 struct mvpp2_tx_queue *txq,
4211 struct mvpp2_tx_queue *aggr_txq,
4212 struct mvpp2_txq_pcpu *txq_pcpu,
4215 struct mvpp2_port *port = netdev_priv(dev);
4216 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4219 mvpp2_txdesc_clear_ptp(port, tx_desc);
4220 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4221 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz);
4223 addr = txq_pcpu->tso_headers_dma +
4224 txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
4225 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr);
4227 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) |
4229 MVPP2_TXD_PADDING_DISABLE);
4230 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4233 static inline int mvpp2_tso_put_data(struct sk_buff *skb,
4234 struct net_device *dev, struct tso_t *tso,
4235 struct mvpp2_tx_queue *txq,
4236 struct mvpp2_tx_queue *aggr_txq,
4237 struct mvpp2_txq_pcpu *txq_pcpu,
4238 int sz, bool left, bool last)
4240 struct mvpp2_port *port = netdev_priv(dev);
4241 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4242 dma_addr_t buf_dma_addr;
4244 mvpp2_txdesc_clear_ptp(port, tx_desc);
4245 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4246 mvpp2_txdesc_size_set(port, tx_desc, sz);
4248 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz,
4250 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
4251 mvpp2_txq_desc_put(txq);
4255 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
4258 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC);
4260 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
4264 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
4267 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4271 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev,
4272 struct mvpp2_tx_queue *txq,
4273 struct mvpp2_tx_queue *aggr_txq,
4274 struct mvpp2_txq_pcpu *txq_pcpu)
4276 struct mvpp2_port *port = netdev_priv(dev);
4277 int hdr_sz, i, len, descs = 0;
4280 /* Check number of available descriptors */
4281 if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) ||
4282 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu,
4283 tso_count_descs(skb)))
4286 hdr_sz = tso_start(skb, &tso);
4288 len = skb->len - hdr_sz;
4290 int left = min_t(int, skb_shinfo(skb)->gso_size, len);
4291 char *hdr = txq_pcpu->tso_headers +
4292 txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
4297 tso_build_hdr(skb, hdr, &tso, left, len == 0);
4298 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz);
4301 int sz = min_t(int, tso.size, left);
4305 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq,
4306 txq_pcpu, sz, left, len == 0))
4308 tso_build_data(skb, &tso, sz);
4315 for (i = descs - 1; i >= 0; i--) {
4316 struct mvpp2_tx_desc *tx_desc = txq->descs + i;
4317 tx_desc_unmap_put(port, txq, tx_desc);
4322 /* Main tx processing */
4323 static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
4325 struct mvpp2_port *port = netdev_priv(dev);
4326 struct mvpp2_tx_queue *txq, *aggr_txq;
4327 struct mvpp2_txq_pcpu *txq_pcpu;
4328 struct mvpp2_tx_desc *tx_desc;
4329 dma_addr_t buf_dma_addr;
4330 unsigned long flags = 0;
4331 unsigned int thread;
4336 thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4338 txq_id = skb_get_queue_mapping(skb);
4339 txq = port->txqs[txq_id];
4340 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
4341 aggr_txq = &port->priv->aggr_txqs[thread];
4343 if (test_bit(thread, &port->priv->lock_map))
4344 spin_lock_irqsave(&port->tx_lock[thread], flags);
4346 if (skb_is_gso(skb)) {
4347 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu);
4350 frags = skb_shinfo(skb)->nr_frags + 1;
4352 /* Check number of available descriptors */
4353 if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) ||
4354 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) {
4359 /* Get a descriptor for the first part of the packet */
4360 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
4361 if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ||
4362 !mvpp2_tx_hw_tstamp(port, tx_desc, skb))
4363 mvpp2_txdesc_clear_ptp(port, tx_desc);
4364 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
4365 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb));
4367 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data,
4368 skb_headlen(skb), DMA_TO_DEVICE);
4369 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
4370 mvpp2_txq_desc_put(txq);
4375 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
4377 tx_cmd = mvpp2_skb_tx_csum(port, skb);
4380 /* First and Last descriptor */
4381 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
4382 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
4383 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB);
4385 /* First but not Last */
4386 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE;
4387 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
4388 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB);
4390 /* Continue with other skb fragments */
4391 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {
4392 tx_desc_unmap_put(port, txq, tx_desc);
4399 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread);
4400 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
4402 txq_pcpu->reserved_num -= frags;
4403 txq_pcpu->count += frags;
4404 aggr_txq->count += frags;
4406 /* Enable transmit */
4408 mvpp2_aggr_txq_pend_desc_add(port, frags);
4410 if (txq_pcpu->count >= txq_pcpu->stop_threshold)
4411 netif_tx_stop_queue(nq);
4413 u64_stats_update_begin(&stats->syncp);
4414 stats->tx_packets++;
4415 stats->tx_bytes += skb->len;
4416 u64_stats_update_end(&stats->syncp);
4418 dev->stats.tx_dropped++;
4419 dev_kfree_skb_any(skb);
4422 /* Finalize TX processing */
4423 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
4424 mvpp2_txq_done(port, txq, txq_pcpu);
4426 /* Set the timer in case not all frags were processed */
4427 if (!port->has_tx_irqs && txq_pcpu->count <= frags &&
4428 txq_pcpu->count > 0) {
4429 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread);
4431 if (!port_pcpu->timer_scheduled) {
4432 port_pcpu->timer_scheduled = true;
4433 hrtimer_start(&port_pcpu->tx_done_timer,
4434 MVPP2_TXDONE_HRTIMER_PERIOD_NS,
4435 HRTIMER_MODE_REL_PINNED_SOFT);
4439 if (test_bit(thread, &port->priv->lock_map))
4440 spin_unlock_irqrestore(&port->tx_lock[thread], flags);
4442 return NETDEV_TX_OK;
4445 static inline void mvpp2_cause_error(struct net_device *dev, int cause)
4447 if (cause & MVPP2_CAUSE_FCS_ERR_MASK)
4448 netdev_err(dev, "FCS error\n");
4449 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK)
4450 netdev_err(dev, "rx fifo overrun error\n");
4451 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK)
4452 netdev_err(dev, "tx fifo underrun error\n");
4455 static int mvpp2_poll(struct napi_struct *napi, int budget)
4457 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc;
4459 struct mvpp2_port *port = netdev_priv(napi->dev);
4460 struct mvpp2_queue_vector *qv;
4461 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
4463 qv = container_of(napi, struct mvpp2_queue_vector, napi);
4465 /* Rx/Tx cause register
4467 * Bits 0-15: each bit indicates received packets on the Rx queue
4468 * (bit 0 is for Rx queue 0).
4470 * Bits 16-23: each bit indicates transmitted packets on the Tx queue
4471 * (bit 16 is for Tx queue 0).
4473 * Each CPU has its own Rx/Tx cause register
4475 cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id,
4476 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
4478 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
4480 mvpp2_cause_error(port->dev, cause_misc);
4482 /* Clear the cause register */
4483 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);
4484 mvpp2_thread_write(port->priv, thread,
4485 MVPP2_ISR_RX_TX_CAUSE_REG(port->id),
4486 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK);
4489 if (port->has_tx_irqs) {
4490 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
4492 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET;
4493 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id);
4497 /* Process RX packets */
4498 cause_rx = cause_rx_tx &
4499 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
4500 cause_rx <<= qv->first_rxq;
4501 cause_rx |= qv->pending_cause_rx;
4502 while (cause_rx && budget > 0) {
4504 struct mvpp2_rx_queue *rxq;
4506 rxq = mvpp2_get_rx_queue(port, cause_rx);
4510 count = mvpp2_rx(port, napi, budget, rxq);
4514 /* Clear the bit associated to this Rx queue
4515 * so that next iteration will continue from
4516 * the next Rx queue.
4518 cause_rx &= ~(1 << rxq->logic_rxq);
4524 napi_complete_done(napi, rx_done);
4526 mvpp2_qvec_interrupt_enable(qv);
4528 qv->pending_cause_rx = cause_rx;
4532 static void mvpp22_mode_reconfigure(struct mvpp2_port *port)
4536 /* Set the GMAC & XLG MAC in reset */
4537 mvpp2_mac_reset_assert(port);
4539 /* Set the MPCS and XPCS in reset */
4540 mvpp22_pcs_reset_assert(port);
4542 /* comphy reconfiguration */
4543 mvpp22_comphy_init(port);
4545 /* gop reconfiguration */
4546 mvpp22_gop_init(port);
4548 mvpp22_pcs_reset_deassert(port);
4550 if (mvpp2_port_supports_xlg(port)) {
4551 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG);
4552 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
4554 if (mvpp2_is_xlg(port->phy_interface))
4555 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G;
4557 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
4559 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG);
4562 if (mvpp2_port_supports_xlg(port) && mvpp2_is_xlg(port->phy_interface))
4563 mvpp2_xlg_max_rx_size_set(port);
4565 mvpp2_gmac_max_rx_size_set(port);
4568 /* Set hw internals when starting port */
4569 static void mvpp2_start_dev(struct mvpp2_port *port)
4573 mvpp2_txp_max_tx_size_set(port);
4575 for (i = 0; i < port->nqvecs; i++)
4576 napi_enable(&port->qvecs[i].napi);
4578 /* Enable interrupts on all threads */
4579 mvpp2_interrupts_enable(port);
4581 if (port->priv->hw_version >= MVPP22)
4582 mvpp22_mode_reconfigure(port);
4584 if (port->phylink) {
4585 phylink_start(port->phylink);
4587 mvpp2_acpi_start(port);
4590 netif_tx_start_all_queues(port->dev);
4592 clear_bit(0, &port->state);
4595 /* Set hw internals when stopping port */
4596 static void mvpp2_stop_dev(struct mvpp2_port *port)
4600 set_bit(0, &port->state);
4602 /* Disable interrupts on all threads */
4603 mvpp2_interrupts_disable(port);
4605 for (i = 0; i < port->nqvecs; i++)
4606 napi_disable(&port->qvecs[i].napi);
4609 phylink_stop(port->phylink);
4610 phy_power_off(port->comphy);
4613 static int mvpp2_check_ringparam_valid(struct net_device *dev,
4614 struct ethtool_ringparam *ring)
4616 u16 new_rx_pending = ring->rx_pending;
4617 u16 new_tx_pending = ring->tx_pending;
4619 if (ring->rx_pending == 0 || ring->tx_pending == 0)
4622 if (ring->rx_pending > MVPP2_MAX_RXD_MAX)
4623 new_rx_pending = MVPP2_MAX_RXD_MAX;
4624 else if (ring->rx_pending < MSS_THRESHOLD_START)
4625 new_rx_pending = MSS_THRESHOLD_START;
4626 else if (!IS_ALIGNED(ring->rx_pending, 16))
4627 new_rx_pending = ALIGN(ring->rx_pending, 16);
4629 if (ring->tx_pending > MVPP2_MAX_TXD_MAX)
4630 new_tx_pending = MVPP2_MAX_TXD_MAX;
4631 else if (!IS_ALIGNED(ring->tx_pending, 32))
4632 new_tx_pending = ALIGN(ring->tx_pending, 32);
4634 /* The Tx ring size cannot be smaller than the minimum number of
4635 * descriptors needed for TSO.
4637 if (new_tx_pending < MVPP2_MAX_SKB_DESCS)
4638 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32);
4640 if (ring->rx_pending != new_rx_pending) {
4641 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n",
4642 ring->rx_pending, new_rx_pending);
4643 ring->rx_pending = new_rx_pending;
4646 if (ring->tx_pending != new_tx_pending) {
4647 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n",
4648 ring->tx_pending, new_tx_pending);
4649 ring->tx_pending = new_tx_pending;
4655 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr)
4657 u32 mac_addr_l, mac_addr_m, mac_addr_h;
4659 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
4660 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE);
4661 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH);
4662 addr[0] = (mac_addr_h >> 24) & 0xFF;
4663 addr[1] = (mac_addr_h >> 16) & 0xFF;
4664 addr[2] = (mac_addr_h >> 8) & 0xFF;
4665 addr[3] = mac_addr_h & 0xFF;
4666 addr[4] = mac_addr_m & 0xFF;
4667 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF;
4670 static int mvpp2_irqs_init(struct mvpp2_port *port)
4674 for (i = 0; i < port->nqvecs; i++) {
4675 struct mvpp2_queue_vector *qv = port->qvecs + i;
4677 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
4678 qv->mask = kzalloc(cpumask_size(), GFP_KERNEL);
4684 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING);
4687 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv);
4691 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
4694 for_each_present_cpu(cpu) {
4695 if (mvpp2_cpu_to_thread(port->priv, cpu) ==
4697 cpumask_set_cpu(cpu, qv->mask);
4700 irq_set_affinity_hint(qv->irq, qv->mask);
4706 for (i = 0; i < port->nqvecs; i++) {
4707 struct mvpp2_queue_vector *qv = port->qvecs + i;
4709 irq_set_affinity_hint(qv->irq, NULL);
4712 free_irq(qv->irq, qv);
4718 static void mvpp2_irqs_deinit(struct mvpp2_port *port)
4722 for (i = 0; i < port->nqvecs; i++) {
4723 struct mvpp2_queue_vector *qv = port->qvecs + i;
4725 irq_set_affinity_hint(qv->irq, NULL);
4728 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING);
4729 free_irq(qv->irq, qv);
4733 static bool mvpp22_rss_is_supported(struct mvpp2_port *port)
4735 return (queue_mode == MVPP2_QDIST_MULTI_MODE) &&
4736 !(port->flags & MVPP2_F_LOOPBACK);
4739 static int mvpp2_open(struct net_device *dev)
4741 struct mvpp2_port *port = netdev_priv(dev);
4742 struct mvpp2 *priv = port->priv;
4743 unsigned char mac_bcast[ETH_ALEN] = {
4744 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4748 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true);
4750 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
4753 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true);
4755 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n");
4758 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH);
4760 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n");
4763 err = mvpp2_prs_def_flow(port);
4765 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
4769 /* Allocate the Rx/Tx queues */
4770 err = mvpp2_setup_rxqs(port);
4772 netdev_err(port->dev, "cannot allocate Rx queues\n");
4776 err = mvpp2_setup_txqs(port);
4778 netdev_err(port->dev, "cannot allocate Tx queues\n");
4779 goto err_cleanup_rxqs;
4782 err = mvpp2_irqs_init(port);
4784 netdev_err(port->dev, "cannot init IRQs\n");
4785 goto err_cleanup_txqs;
4788 if (port->phylink) {
4789 err = phylink_fwnode_phy_connect(port->phylink, port->fwnode, 0);
4791 netdev_err(port->dev, "could not attach PHY (%d)\n",
4799 if (priv->hw_version >= MVPP22 && port->port_irq) {
4800 err = request_irq(port->port_irq, mvpp2_port_isr, 0,
4803 netdev_err(port->dev,
4804 "cannot request port link/ptp IRQ %d\n",
4809 mvpp22_gop_setup_irq(port);
4811 /* In default link is down */
4812 netif_carrier_off(port->dev);
4820 netdev_err(port->dev,
4821 "invalid configuration: no dt or link IRQ");
4826 /* Unmask interrupts on all CPUs */
4827 on_each_cpu(mvpp2_interrupts_unmask, port, 1);
4828 mvpp2_shared_interrupt_mask_unmask(port, false);
4830 mvpp2_start_dev(port);
4832 /* Start hardware statistics gathering */
4833 queue_delayed_work(priv->stats_queue, &port->stats_work,
4834 MVPP2_MIB_COUNTERS_STATS_DELAY);
4839 mvpp2_irqs_deinit(port);
4841 mvpp2_cleanup_txqs(port);
4843 mvpp2_cleanup_rxqs(port);
4847 static int mvpp2_stop(struct net_device *dev)
4849 struct mvpp2_port *port = netdev_priv(dev);
4850 struct mvpp2_port_pcpu *port_pcpu;
4851 unsigned int thread;
4853 mvpp2_stop_dev(port);
4855 /* Mask interrupts on all threads */
4856 on_each_cpu(mvpp2_interrupts_mask, port, 1);
4857 mvpp2_shared_interrupt_mask_unmask(port, true);
4860 phylink_disconnect_phy(port->phylink);
4862 free_irq(port->port_irq, port);
4864 mvpp2_irqs_deinit(port);
4865 if (!port->has_tx_irqs) {
4866 for (thread = 0; thread < port->priv->nthreads; thread++) {
4867 port_pcpu = per_cpu_ptr(port->pcpu, thread);
4869 hrtimer_cancel(&port_pcpu->tx_done_timer);
4870 port_pcpu->timer_scheduled = false;
4873 mvpp2_cleanup_rxqs(port);
4874 mvpp2_cleanup_txqs(port);
4876 cancel_delayed_work_sync(&port->stats_work);
4878 mvpp2_mac_reset_assert(port);
4879 mvpp22_pcs_reset_assert(port);
4884 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port,
4885 struct netdev_hw_addr_list *list)
4887 struct netdev_hw_addr *ha;
4890 netdev_hw_addr_list_for_each(ha, list) {
4891 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true);
4899 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable)
4901 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER))
4902 mvpp2_prs_vid_enable_filtering(port);
4904 mvpp2_prs_vid_disable_filtering(port);
4906 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4907 MVPP2_PRS_L2_UNI_CAST, enable);
4909 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4910 MVPP2_PRS_L2_MULTI_CAST, enable);
4913 static void mvpp2_set_rx_mode(struct net_device *dev)
4915 struct mvpp2_port *port = netdev_priv(dev);
4917 /* Clear the whole UC and MC list */
4918 mvpp2_prs_mac_del_all(port);
4920 if (dev->flags & IFF_PROMISC) {
4921 mvpp2_set_rx_promisc(port, true);
4925 mvpp2_set_rx_promisc(port, false);
4927 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX ||
4928 mvpp2_prs_mac_da_accept_list(port, &dev->uc))
4929 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4930 MVPP2_PRS_L2_UNI_CAST, true);
4932 if (dev->flags & IFF_ALLMULTI) {
4933 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4934 MVPP2_PRS_L2_MULTI_CAST, true);
4938 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX ||
4939 mvpp2_prs_mac_da_accept_list(port, &dev->mc))
4940 mvpp2_prs_mac_promisc_set(port->priv, port->id,
4941 MVPP2_PRS_L2_MULTI_CAST, true);
4944 static int mvpp2_set_mac_address(struct net_device *dev, void *p)
4946 const struct sockaddr *addr = p;
4949 if (!is_valid_ether_addr(addr->sa_data))
4950 return -EADDRNOTAVAIL;
4952 err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
4954 /* Reconfigure parser accept the original MAC address */
4955 mvpp2_prs_update_mac_da(dev, dev->dev_addr);
4956 netdev_err(dev, "failed to change MAC address\n");
4961 /* Shut down all the ports, reconfigure the pools as percpu or shared,
4962 * then bring up again all ports.
4964 static int mvpp2_bm_switch_buffers(struct mvpp2 *priv, bool percpu)
4966 bool change_percpu = (percpu != priv->percpu_pools);
4967 int numbufs = MVPP2_BM_POOLS_NUM, i;
4968 struct mvpp2_port *port = NULL;
4969 bool status[MVPP2_MAX_PORTS];
4971 for (i = 0; i < priv->port_count; i++) {
4972 port = priv->port_list[i];
4973 status[i] = netif_running(port->dev);
4975 mvpp2_stop(port->dev);
4978 /* nrxqs is the same for all ports */
4979 if (priv->percpu_pools)
4980 numbufs = port->nrxqs * 2;
4983 mvpp2_bm_pool_update_priv_fc(priv, false);
4985 for (i = 0; i < numbufs; i++)
4986 mvpp2_bm_pool_destroy(port->dev->dev.parent, priv, &priv->bm_pools[i]);
4988 devm_kfree(port->dev->dev.parent, priv->bm_pools);
4989 priv->percpu_pools = percpu;
4990 mvpp2_bm_init(port->dev->dev.parent, priv);
4992 for (i = 0; i < priv->port_count; i++) {
4993 port = priv->port_list[i];
4994 mvpp2_swf_bm_pool_init(port);
4996 mvpp2_open(port->dev);
5000 mvpp2_bm_pool_update_priv_fc(priv, true);
5005 static int mvpp2_change_mtu(struct net_device *dev, int mtu)
5007 struct mvpp2_port *port = netdev_priv(dev);
5008 bool running = netif_running(dev);
5009 struct mvpp2 *priv = port->priv;
5012 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) {
5013 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu,
5014 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8));
5015 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8);
5018 if (MVPP2_RX_PKT_SIZE(mtu) > MVPP2_BM_LONG_PKT_SIZE) {
5019 if (port->xdp_prog) {
5020 netdev_err(dev, "Jumbo frames are not supported with XDP\n");
5023 if (priv->percpu_pools) {
5024 netdev_warn(dev, "mtu %d too high, switching to shared buffers", mtu);
5025 mvpp2_bm_switch_buffers(priv, false);
5031 for (i = 0; i < priv->port_count; i++)
5032 if (priv->port_list[i] != port &&
5033 MVPP2_RX_PKT_SIZE(priv->port_list[i]->dev->mtu) >
5034 MVPP2_BM_LONG_PKT_SIZE) {
5039 /* No port is using jumbo frames */
5041 dev_info(port->dev->dev.parent,
5042 "all ports have a low MTU, switching to per-cpu buffers");
5043 mvpp2_bm_switch_buffers(priv, true);
5048 mvpp2_stop_dev(port);
5050 err = mvpp2_bm_update_mtu(dev, mtu);
5052 netdev_err(dev, "failed to change MTU\n");
5053 /* Reconfigure BM to the original MTU */
5054 mvpp2_bm_update_mtu(dev, dev->mtu);
5056 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu);
5060 mvpp2_start_dev(port);
5061 mvpp2_egress_enable(port);
5062 mvpp2_ingress_enable(port);
5068 static int mvpp2_check_pagepool_dma(struct mvpp2_port *port)
5070 enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
5071 struct mvpp2 *priv = port->priv;
5074 if (!priv->percpu_pools)
5077 if (!priv->page_pool[0])
5080 for (i = 0; i < priv->port_count; i++) {
5081 port = priv->port_list[i];
5082 if (port->xdp_prog) {
5083 dma_dir = DMA_BIDIRECTIONAL;
5088 /* All pools are equal in terms of DMA direction */
5089 if (priv->page_pool[0]->p.dma_dir != dma_dir)
5090 err = mvpp2_bm_switch_buffers(priv, true);
5096 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5098 struct mvpp2_port *port = netdev_priv(dev);
5102 for_each_possible_cpu(cpu) {
5103 struct mvpp2_pcpu_stats *cpu_stats;
5109 cpu_stats = per_cpu_ptr(port->stats, cpu);
5111 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
5112 rx_packets = cpu_stats->rx_packets;
5113 rx_bytes = cpu_stats->rx_bytes;
5114 tx_packets = cpu_stats->tx_packets;
5115 tx_bytes = cpu_stats->tx_bytes;
5116 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
5118 stats->rx_packets += rx_packets;
5119 stats->rx_bytes += rx_bytes;
5120 stats->tx_packets += tx_packets;
5121 stats->tx_bytes += tx_bytes;
5124 stats->rx_errors = dev->stats.rx_errors;
5125 stats->rx_dropped = dev->stats.rx_dropped;
5126 stats->tx_dropped = dev->stats.tx_dropped;
5129 static int mvpp2_set_ts_config(struct mvpp2_port *port, struct ifreq *ifr)
5131 struct hwtstamp_config config;
5135 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5141 if (config.tx_type != HWTSTAMP_TX_OFF &&
5142 config.tx_type != HWTSTAMP_TX_ON)
5145 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id);
5148 if (config.tx_type != HWTSTAMP_TX_OFF) {
5149 gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_TX_RESET;
5150 int_mask |= MVPP22_PTP_INT_MASK_QUEUE1 |
5151 MVPP22_PTP_INT_MASK_QUEUE0;
5154 /* It seems we must also release the TX reset when enabling the TSU */
5155 if (config.rx_filter != HWTSTAMP_FILTER_NONE)
5156 gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_RX_RESET |
5157 MVPP22_PTP_GCR_TX_RESET;
5159 if (gcr & MVPP22_PTP_GCR_TSU_ENABLE)
5160 mvpp22_tai_start(port->priv->tai);
5162 if (config.rx_filter != HWTSTAMP_FILTER_NONE) {
5163 config.rx_filter = HWTSTAMP_FILTER_ALL;
5164 mvpp2_modify(ptp + MVPP22_PTP_GCR,
5165 MVPP22_PTP_GCR_RX_RESET |
5166 MVPP22_PTP_GCR_TX_RESET |
5167 MVPP22_PTP_GCR_TSU_ENABLE, gcr);
5168 port->rx_hwtstamp = true;
5170 port->rx_hwtstamp = false;
5171 mvpp2_modify(ptp + MVPP22_PTP_GCR,
5172 MVPP22_PTP_GCR_RX_RESET |
5173 MVPP22_PTP_GCR_TX_RESET |
5174 MVPP22_PTP_GCR_TSU_ENABLE, gcr);
5177 mvpp2_modify(ptp + MVPP22_PTP_INT_MASK,
5178 MVPP22_PTP_INT_MASK_QUEUE1 |
5179 MVPP22_PTP_INT_MASK_QUEUE0, int_mask);
5181 if (!(gcr & MVPP22_PTP_GCR_TSU_ENABLE))
5182 mvpp22_tai_stop(port->priv->tai);
5184 port->tx_hwtstamp_type = config.tx_type;
5186 if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
5192 static int mvpp2_get_ts_config(struct mvpp2_port *port, struct ifreq *ifr)
5194 struct hwtstamp_config config;
5196 memset(&config, 0, sizeof(config));
5198 config.tx_type = port->tx_hwtstamp_type;
5199 config.rx_filter = port->rx_hwtstamp ?
5200 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE;
5202 if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
5208 static int mvpp2_ethtool_get_ts_info(struct net_device *dev,
5209 struct ethtool_ts_info *info)
5211 struct mvpp2_port *port = netdev_priv(dev);
5213 if (!port->hwtstamp)
5216 info->phc_index = mvpp22_tai_ptp_clock_index(port->priv->tai);
5217 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
5218 SOF_TIMESTAMPING_RX_SOFTWARE |
5219 SOF_TIMESTAMPING_SOFTWARE |
5220 SOF_TIMESTAMPING_TX_HARDWARE |
5221 SOF_TIMESTAMPING_RX_HARDWARE |
5222 SOF_TIMESTAMPING_RAW_HARDWARE;
5223 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
5224 BIT(HWTSTAMP_TX_ON);
5225 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
5226 BIT(HWTSTAMP_FILTER_ALL);
5231 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5233 struct mvpp2_port *port = netdev_priv(dev);
5238 return mvpp2_set_ts_config(port, ifr);
5243 return mvpp2_get_ts_config(port, ifr);
5250 return phylink_mii_ioctl(port->phylink, ifr, cmd);
5253 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
5255 struct mvpp2_port *port = netdev_priv(dev);
5258 ret = mvpp2_prs_vid_entry_add(port, vid);
5260 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n",
5261 MVPP2_PRS_VLAN_FILT_MAX - 1);
5265 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
5267 struct mvpp2_port *port = netdev_priv(dev);
5269 mvpp2_prs_vid_entry_remove(port, vid);
5273 static int mvpp2_set_features(struct net_device *dev,
5274 netdev_features_t features)
5276 netdev_features_t changed = dev->features ^ features;
5277 struct mvpp2_port *port = netdev_priv(dev);
5279 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
5280 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) {
5281 mvpp2_prs_vid_enable_filtering(port);
5283 /* Invalidate all registered VID filters for this
5286 mvpp2_prs_vid_remove_all(port);
5288 mvpp2_prs_vid_disable_filtering(port);
5292 if (changed & NETIF_F_RXHASH) {
5293 if (features & NETIF_F_RXHASH)
5294 mvpp22_port_rss_enable(port);
5296 mvpp22_port_rss_disable(port);
5302 static int mvpp2_xdp_setup(struct mvpp2_port *port, struct netdev_bpf *bpf)
5304 struct bpf_prog *prog = bpf->prog, *old_prog;
5305 bool running = netif_running(port->dev);
5306 bool reset = !prog != !port->xdp_prog;
5308 if (port->dev->mtu > ETH_DATA_LEN) {
5309 NL_SET_ERR_MSG_MOD(bpf->extack, "XDP is not supported with jumbo frames enabled");
5313 if (!port->priv->percpu_pools) {
5314 NL_SET_ERR_MSG_MOD(bpf->extack, "Per CPU Pools required for XDP");
5318 if (port->ntxqs < num_possible_cpus() * 2) {
5319 NL_SET_ERR_MSG_MOD(bpf->extack, "XDP_TX needs two TX queues per CPU");
5323 /* device is up and bpf is added/removed, must setup the RX queues */
5324 if (running && reset)
5325 mvpp2_stop(port->dev);
5327 old_prog = xchg(&port->xdp_prog, prog);
5329 bpf_prog_put(old_prog);
5331 /* bpf is just replaced, RXQ and MTU are already setup */
5335 /* device was up, restore the link */
5337 mvpp2_open(port->dev);
5339 /* Check Page Pool DMA Direction */
5340 mvpp2_check_pagepool_dma(port);
5345 static int mvpp2_xdp(struct net_device *dev, struct netdev_bpf *xdp)
5347 struct mvpp2_port *port = netdev_priv(dev);
5349 switch (xdp->command) {
5350 case XDP_SETUP_PROG:
5351 return mvpp2_xdp_setup(port, xdp);
5357 /* Ethtool methods */
5359 static int mvpp2_ethtool_nway_reset(struct net_device *dev)
5361 struct mvpp2_port *port = netdev_priv(dev);
5366 return phylink_ethtool_nway_reset(port->phylink);
5369 /* Set interrupt coalescing for ethtools */
5370 static int mvpp2_ethtool_set_coalesce(struct net_device *dev,
5371 struct ethtool_coalesce *c)
5373 struct mvpp2_port *port = netdev_priv(dev);
5376 for (queue = 0; queue < port->nrxqs; queue++) {
5377 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
5379 rxq->time_coal = c->rx_coalesce_usecs;
5380 rxq->pkts_coal = c->rx_max_coalesced_frames;
5381 mvpp2_rx_pkts_coal_set(port, rxq);
5382 mvpp2_rx_time_coal_set(port, rxq);
5385 if (port->has_tx_irqs) {
5386 port->tx_time_coal = c->tx_coalesce_usecs;
5387 mvpp2_tx_time_coal_set(port);
5390 for (queue = 0; queue < port->ntxqs; queue++) {
5391 struct mvpp2_tx_queue *txq = port->txqs[queue];
5393 txq->done_pkts_coal = c->tx_max_coalesced_frames;
5395 if (port->has_tx_irqs)
5396 mvpp2_tx_pkts_coal_set(port, txq);
5402 /* get coalescing for ethtools */
5403 static int mvpp2_ethtool_get_coalesce(struct net_device *dev,
5404 struct ethtool_coalesce *c)
5406 struct mvpp2_port *port = netdev_priv(dev);
5408 c->rx_coalesce_usecs = port->rxqs[0]->time_coal;
5409 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal;
5410 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal;
5411 c->tx_coalesce_usecs = port->tx_time_coal;
5415 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev,
5416 struct ethtool_drvinfo *drvinfo)
5418 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME,
5419 sizeof(drvinfo->driver));
5420 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION,
5421 sizeof(drvinfo->version));
5422 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
5423 sizeof(drvinfo->bus_info));
5426 static void mvpp2_ethtool_get_ringparam(struct net_device *dev,
5427 struct ethtool_ringparam *ring)
5429 struct mvpp2_port *port = netdev_priv(dev);
5431 ring->rx_max_pending = MVPP2_MAX_RXD_MAX;
5432 ring->tx_max_pending = MVPP2_MAX_TXD_MAX;
5433 ring->rx_pending = port->rx_ring_size;
5434 ring->tx_pending = port->tx_ring_size;
5437 static int mvpp2_ethtool_set_ringparam(struct net_device *dev,
5438 struct ethtool_ringparam *ring)
5440 struct mvpp2_port *port = netdev_priv(dev);
5441 u16 prev_rx_ring_size = port->rx_ring_size;
5442 u16 prev_tx_ring_size = port->tx_ring_size;
5445 err = mvpp2_check_ringparam_valid(dev, ring);
5449 if (!netif_running(dev)) {
5450 port->rx_ring_size = ring->rx_pending;
5451 port->tx_ring_size = ring->tx_pending;
5455 /* The interface is running, so we have to force a
5456 * reallocation of the queues
5458 mvpp2_stop_dev(port);
5459 mvpp2_cleanup_rxqs(port);
5460 mvpp2_cleanup_txqs(port);
5462 port->rx_ring_size = ring->rx_pending;
5463 port->tx_ring_size = ring->tx_pending;
5465 err = mvpp2_setup_rxqs(port);
5467 /* Reallocate Rx queues with the original ring size */
5468 port->rx_ring_size = prev_rx_ring_size;
5469 ring->rx_pending = prev_rx_ring_size;
5470 err = mvpp2_setup_rxqs(port);
5474 err = mvpp2_setup_txqs(port);
5476 /* Reallocate Tx queues with the original ring size */
5477 port->tx_ring_size = prev_tx_ring_size;
5478 ring->tx_pending = prev_tx_ring_size;
5479 err = mvpp2_setup_txqs(port);
5481 goto err_clean_rxqs;
5484 mvpp2_start_dev(port);
5485 mvpp2_egress_enable(port);
5486 mvpp2_ingress_enable(port);
5491 mvpp2_cleanup_rxqs(port);
5493 netdev_err(dev, "failed to change ring parameters");
5497 static void mvpp2_ethtool_get_pause_param(struct net_device *dev,
5498 struct ethtool_pauseparam *pause)
5500 struct mvpp2_port *port = netdev_priv(dev);
5505 phylink_ethtool_get_pauseparam(port->phylink, pause);
5508 static int mvpp2_ethtool_set_pause_param(struct net_device *dev,
5509 struct ethtool_pauseparam *pause)
5511 struct mvpp2_port *port = netdev_priv(dev);
5516 return phylink_ethtool_set_pauseparam(port->phylink, pause);
5519 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev,
5520 struct ethtool_link_ksettings *cmd)
5522 struct mvpp2_port *port = netdev_priv(dev);
5527 return phylink_ethtool_ksettings_get(port->phylink, cmd);
5530 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev,
5531 const struct ethtool_link_ksettings *cmd)
5533 struct mvpp2_port *port = netdev_priv(dev);
5538 return phylink_ethtool_ksettings_set(port->phylink, cmd);
5541 static int mvpp2_ethtool_get_rxnfc(struct net_device *dev,
5542 struct ethtool_rxnfc *info, u32 *rules)
5544 struct mvpp2_port *port = netdev_priv(dev);
5545 int ret = 0, i, loc = 0;
5547 if (!mvpp22_rss_is_supported(port))
5550 switch (info->cmd) {
5552 ret = mvpp2_ethtool_rxfh_get(port, info);
5554 case ETHTOOL_GRXRINGS:
5555 info->data = port->nrxqs;
5557 case ETHTOOL_GRXCLSRLCNT:
5558 info->rule_cnt = port->n_rfs_rules;
5560 case ETHTOOL_GRXCLSRULE:
5561 ret = mvpp2_ethtool_cls_rule_get(port, info);
5563 case ETHTOOL_GRXCLSRLALL:
5564 for (i = 0; i < MVPP2_N_RFS_ENTRIES_PER_FLOW; i++) {
5565 if (port->rfs_rules[i])
5576 static int mvpp2_ethtool_set_rxnfc(struct net_device *dev,
5577 struct ethtool_rxnfc *info)
5579 struct mvpp2_port *port = netdev_priv(dev);
5582 if (!mvpp22_rss_is_supported(port))
5585 switch (info->cmd) {
5587 ret = mvpp2_ethtool_rxfh_set(port, info);
5589 case ETHTOOL_SRXCLSRLINS:
5590 ret = mvpp2_ethtool_cls_rule_ins(port, info);
5592 case ETHTOOL_SRXCLSRLDEL:
5593 ret = mvpp2_ethtool_cls_rule_del(port, info);
5601 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev)
5603 struct mvpp2_port *port = netdev_priv(dev);
5605 return mvpp22_rss_is_supported(port) ? MVPP22_RSS_TABLE_ENTRIES : 0;
5608 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
5611 struct mvpp2_port *port = netdev_priv(dev);
5614 if (!mvpp22_rss_is_supported(port))
5618 ret = mvpp22_port_rss_ctx_indir_get(port, 0, indir);
5621 *hfunc = ETH_RSS_HASH_CRC32;
5626 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
5627 const u8 *key, const u8 hfunc)
5629 struct mvpp2_port *port = netdev_priv(dev);
5632 if (!mvpp22_rss_is_supported(port))
5635 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
5642 ret = mvpp22_port_rss_ctx_indir_set(port, 0, indir);
5647 static int mvpp2_ethtool_get_rxfh_context(struct net_device *dev, u32 *indir,
5648 u8 *key, u8 *hfunc, u32 rss_context)
5650 struct mvpp2_port *port = netdev_priv(dev);
5653 if (!mvpp22_rss_is_supported(port))
5655 if (rss_context >= MVPP22_N_RSS_TABLES)
5659 *hfunc = ETH_RSS_HASH_CRC32;
5662 ret = mvpp22_port_rss_ctx_indir_get(port, rss_context, indir);
5667 static int mvpp2_ethtool_set_rxfh_context(struct net_device *dev,
5668 const u32 *indir, const u8 *key,
5669 const u8 hfunc, u32 *rss_context,
5672 struct mvpp2_port *port = netdev_priv(dev);
5675 if (!mvpp22_rss_is_supported(port))
5678 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
5685 return mvpp22_port_rss_ctx_delete(port, *rss_context);
5687 if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) {
5688 ret = mvpp22_port_rss_ctx_create(port, rss_context);
5693 return mvpp22_port_rss_ctx_indir_set(port, *rss_context, indir);
5697 static const struct net_device_ops mvpp2_netdev_ops = {
5698 .ndo_open = mvpp2_open,
5699 .ndo_stop = mvpp2_stop,
5700 .ndo_start_xmit = mvpp2_tx,
5701 .ndo_set_rx_mode = mvpp2_set_rx_mode,
5702 .ndo_set_mac_address = mvpp2_set_mac_address,
5703 .ndo_change_mtu = mvpp2_change_mtu,
5704 .ndo_get_stats64 = mvpp2_get_stats64,
5705 .ndo_eth_ioctl = mvpp2_ioctl,
5706 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid,
5707 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid,
5708 .ndo_set_features = mvpp2_set_features,
5709 .ndo_bpf = mvpp2_xdp,
5710 .ndo_xdp_xmit = mvpp2_xdp_xmit,
5713 static const struct ethtool_ops mvpp2_eth_tool_ops = {
5714 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
5715 ETHTOOL_COALESCE_MAX_FRAMES,
5716 .nway_reset = mvpp2_ethtool_nway_reset,
5717 .get_link = ethtool_op_get_link,
5718 .get_ts_info = mvpp2_ethtool_get_ts_info,
5719 .set_coalesce = mvpp2_ethtool_set_coalesce,
5720 .get_coalesce = mvpp2_ethtool_get_coalesce,
5721 .get_drvinfo = mvpp2_ethtool_get_drvinfo,
5722 .get_ringparam = mvpp2_ethtool_get_ringparam,
5723 .set_ringparam = mvpp2_ethtool_set_ringparam,
5724 .get_strings = mvpp2_ethtool_get_strings,
5725 .get_ethtool_stats = mvpp2_ethtool_get_stats,
5726 .get_sset_count = mvpp2_ethtool_get_sset_count,
5727 .get_pauseparam = mvpp2_ethtool_get_pause_param,
5728 .set_pauseparam = mvpp2_ethtool_set_pause_param,
5729 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings,
5730 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings,
5731 .get_rxnfc = mvpp2_ethtool_get_rxnfc,
5732 .set_rxnfc = mvpp2_ethtool_set_rxnfc,
5733 .get_rxfh_indir_size = mvpp2_ethtool_get_rxfh_indir_size,
5734 .get_rxfh = mvpp2_ethtool_get_rxfh,
5735 .set_rxfh = mvpp2_ethtool_set_rxfh,
5736 .get_rxfh_context = mvpp2_ethtool_get_rxfh_context,
5737 .set_rxfh_context = mvpp2_ethtool_set_rxfh_context,
5740 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that
5741 * had a single IRQ defined per-port.
5743 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port,
5744 struct device_node *port_node)
5746 struct mvpp2_queue_vector *v = &port->qvecs[0];
5749 v->nrxqs = port->nrxqs;
5750 v->type = MVPP2_QUEUE_VECTOR_SHARED;
5751 v->sw_thread_id = 0;
5752 v->sw_thread_mask = *cpumask_bits(cpu_online_mask);
5754 v->irq = irq_of_parse_and_map(port_node, 0);
5757 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
5765 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port,
5766 struct device_node *port_node)
5768 struct mvpp2 *priv = port->priv;
5769 struct mvpp2_queue_vector *v;
5772 switch (queue_mode) {
5773 case MVPP2_QDIST_SINGLE_MODE:
5774 port->nqvecs = priv->nthreads + 1;
5776 case MVPP2_QDIST_MULTI_MODE:
5777 port->nqvecs = priv->nthreads;
5781 for (i = 0; i < port->nqvecs; i++) {
5784 v = port->qvecs + i;
5787 v->type = MVPP2_QUEUE_VECTOR_PRIVATE;
5788 v->sw_thread_id = i;
5789 v->sw_thread_mask = BIT(i);
5791 if (port->flags & MVPP2_F_DT_COMPAT)
5792 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i);
5794 snprintf(irqname, sizeof(irqname), "hif%d", i);
5796 if (queue_mode == MVPP2_QDIST_MULTI_MODE) {
5799 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE &&
5800 i == (port->nqvecs - 1)) {
5802 v->nrxqs = port->nrxqs;
5803 v->type = MVPP2_QUEUE_VECTOR_SHARED;
5805 if (port->flags & MVPP2_F_DT_COMPAT)
5806 strncpy(irqname, "rx-shared", sizeof(irqname));
5810 v->irq = of_irq_get_byname(port_node, irqname);
5812 v->irq = fwnode_irq_get(port->fwnode, i);
5818 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
5825 for (i = 0; i < port->nqvecs; i++)
5826 irq_dispose_mapping(port->qvecs[i].irq);
5830 static int mvpp2_queue_vectors_init(struct mvpp2_port *port,
5831 struct device_node *port_node)
5833 if (port->has_tx_irqs)
5834 return mvpp2_multi_queue_vectors_init(port, port_node);
5836 return mvpp2_simple_queue_vectors_init(port, port_node);
5839 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port)
5843 for (i = 0; i < port->nqvecs; i++)
5844 irq_dispose_mapping(port->qvecs[i].irq);
5847 /* Configure Rx queue group interrupt for this port */
5848 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port)
5850 struct mvpp2 *priv = port->priv;
5854 if (priv->hw_version == MVPP21) {
5855 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
5860 /* Handle the more complicated PPv2.2 and PPv2.3 case */
5861 for (i = 0; i < port->nqvecs; i++) {
5862 struct mvpp2_queue_vector *qv = port->qvecs + i;
5867 val = qv->sw_thread_id;
5868 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET;
5869 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
5871 val = qv->first_rxq;
5872 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET;
5873 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
5877 /* Initialize port HW */
5878 static int mvpp2_port_init(struct mvpp2_port *port)
5880 struct device *dev = port->dev->dev.parent;
5881 struct mvpp2 *priv = port->priv;
5882 struct mvpp2_txq_pcpu *txq_pcpu;
5883 unsigned int thread;
5884 int queue, err, val;
5886 /* Checks for hardware constraints */
5887 if (port->first_rxq + port->nrxqs >
5888 MVPP2_MAX_PORTS * priv->max_port_rxqs)
5891 if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ)
5895 mvpp2_egress_disable(port);
5896 mvpp2_port_disable(port);
5898 if (mvpp2_is_xlg(port->phy_interface)) {
5899 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
5900 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
5901 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
5902 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
5904 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5905 val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
5906 val |= MVPP2_GMAC_FORCE_LINK_DOWN;
5907 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
5910 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC;
5912 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs),
5917 /* Associate physical Tx queues to this port and initialize.
5918 * The mapping is predefined.
5920 for (queue = 0; queue < port->ntxqs; queue++) {
5921 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
5922 struct mvpp2_tx_queue *txq;
5924 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
5927 goto err_free_percpu;
5930 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu);
5933 goto err_free_percpu;
5936 txq->id = queue_phy_id;
5937 txq->log_id = queue;
5938 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
5939 for (thread = 0; thread < priv->nthreads; thread++) {
5940 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
5941 txq_pcpu->thread = thread;
5944 port->txqs[queue] = txq;
5947 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs),
5951 goto err_free_percpu;
5954 /* Allocate and initialize Rx queue for this port */
5955 for (queue = 0; queue < port->nrxqs; queue++) {
5956 struct mvpp2_rx_queue *rxq;
5958 /* Map physical Rx queue to port's logical Rx queue */
5959 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
5962 goto err_free_percpu;
5964 /* Map this Rx queue to a physical queue */
5965 rxq->id = port->first_rxq + queue;
5966 rxq->port = port->id;
5967 rxq->logic_rxq = queue;
5969 port->rxqs[queue] = rxq;
5972 mvpp2_rx_irqs_setup(port);
5974 /* Create Rx descriptor rings */
5975 for (queue = 0; queue < port->nrxqs; queue++) {
5976 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
5978 rxq->size = port->rx_ring_size;
5979 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
5980 rxq->time_coal = MVPP2_RX_COAL_USEC;
5983 mvpp2_ingress_disable(port);
5985 /* Port default configuration */
5986 mvpp2_defaults_set(port);
5988 /* Port's classifier configuration */
5989 mvpp2_cls_oversize_rxq_set(port);
5990 mvpp2_cls_port_config(port);
5992 if (mvpp22_rss_is_supported(port))
5993 mvpp22_port_rss_init(port);
5995 /* Provide an initial Rx packet size */
5996 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu);
5998 /* Initialize pools for swf */
5999 err = mvpp2_swf_bm_pool_init(port);
6001 goto err_free_percpu;
6003 /* Clear all port stats */
6004 mvpp2_read_stats(port);
6005 memset(port->ethtool_stats, 0,
6006 MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs) * sizeof(u64));
6011 for (queue = 0; queue < port->ntxqs; queue++) {
6012 if (!port->txqs[queue])
6014 free_percpu(port->txqs[queue]->pcpu);
6019 static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node,
6020 unsigned long *flags)
6022 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2",
6026 for (i = 0; i < 5; i++)
6027 if (of_property_match_string(port_node, "interrupt-names",
6031 *flags |= MVPP2_F_DT_COMPAT;
6035 /* Checks if the port dt description has the required Tx interrupts:
6036 * - PPv2.1: there are no such interrupts.
6037 * - PPv2.2 and PPv2.3:
6038 * - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3]
6039 * - The new ones have: "hifX" with X in [0..8]
6041 * All those variants are supported to keep the backward compatibility.
6043 static bool mvpp2_port_has_irqs(struct mvpp2 *priv,
6044 struct device_node *port_node,
6045 unsigned long *flags)
6054 if (priv->hw_version == MVPP21)
6057 if (mvpp22_port_has_legacy_tx_irqs(port_node, flags))
6060 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
6061 snprintf(name, 5, "hif%d", i);
6062 if (of_property_match_string(port_node, "interrupt-names",
6070 static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv,
6071 struct fwnode_handle *fwnode,
6074 struct mvpp2_port *port = netdev_priv(dev);
6075 char hw_mac_addr[ETH_ALEN] = {0};
6076 char fw_mac_addr[ETH_ALEN];
6078 if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) {
6079 *mac_from = "firmware node";
6080 ether_addr_copy(dev->dev_addr, fw_mac_addr);
6084 if (priv->hw_version == MVPP21) {
6085 mvpp21_get_mac_address(port, hw_mac_addr);
6086 if (is_valid_ether_addr(hw_mac_addr)) {
6087 *mac_from = "hardware";
6088 ether_addr_copy(dev->dev_addr, hw_mac_addr);
6093 *mac_from = "random";
6094 eth_hw_addr_random(dev);
6097 static struct mvpp2_port *mvpp2_phylink_to_port(struct phylink_config *config)
6099 return container_of(config, struct mvpp2_port, phylink_config);
6102 static struct mvpp2_port *mvpp2_pcs_to_port(struct phylink_pcs *pcs)
6104 return container_of(pcs, struct mvpp2_port, phylink_pcs);
6107 static void mvpp2_xlg_pcs_get_state(struct phylink_pcs *pcs,
6108 struct phylink_link_state *state)
6110 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
6113 state->speed = SPEED_10000;
6115 state->an_complete = 1;
6117 val = readl(port->base + MVPP22_XLG_STATUS);
6118 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP);
6121 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
6122 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN)
6123 state->pause |= MLO_PAUSE_TX;
6124 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN)
6125 state->pause |= MLO_PAUSE_RX;
6128 static int mvpp2_xlg_pcs_config(struct phylink_pcs *pcs,
6130 phy_interface_t interface,
6131 const unsigned long *advertising,
6132 bool permit_pause_to_mac)
6137 static const struct phylink_pcs_ops mvpp2_phylink_xlg_pcs_ops = {
6138 .pcs_get_state = mvpp2_xlg_pcs_get_state,
6139 .pcs_config = mvpp2_xlg_pcs_config,
6142 static void mvpp2_gmac_pcs_get_state(struct phylink_pcs *pcs,
6143 struct phylink_link_state *state)
6145 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
6148 val = readl(port->base + MVPP2_GMAC_STATUS0);
6150 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE);
6151 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP);
6152 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX);
6154 switch (port->phy_interface) {
6155 case PHY_INTERFACE_MODE_1000BASEX:
6156 state->speed = SPEED_1000;
6158 case PHY_INTERFACE_MODE_2500BASEX:
6159 state->speed = SPEED_2500;
6162 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
6163 state->speed = SPEED_1000;
6164 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
6165 state->speed = SPEED_100;
6167 state->speed = SPEED_10;
6171 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE)
6172 state->pause |= MLO_PAUSE_RX;
6173 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE)
6174 state->pause |= MLO_PAUSE_TX;
6177 static int mvpp2_gmac_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
6178 phy_interface_t interface,
6179 const unsigned long *advertising,
6180 bool permit_pause_to_mac)
6182 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
6183 u32 mask, val, an, old_an, changed;
6185 mask = MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS |
6186 MVPP2_GMAC_IN_BAND_AUTONEG |
6187 MVPP2_GMAC_AN_SPEED_EN |
6188 MVPP2_GMAC_FLOW_CTRL_AUTONEG |
6189 MVPP2_GMAC_AN_DUPLEX_EN;
6191 if (phylink_autoneg_inband(mode)) {
6192 mask |= MVPP2_GMAC_CONFIG_MII_SPEED |
6193 MVPP2_GMAC_CONFIG_GMII_SPEED |
6194 MVPP2_GMAC_CONFIG_FULL_DUPLEX;
6195 val = MVPP2_GMAC_IN_BAND_AUTONEG;
6197 if (interface == PHY_INTERFACE_MODE_SGMII) {
6198 /* SGMII mode receives the speed and duplex from PHY */
6199 val |= MVPP2_GMAC_AN_SPEED_EN |
6200 MVPP2_GMAC_AN_DUPLEX_EN;
6202 /* 802.3z mode has fixed speed and duplex */
6203 val |= MVPP2_GMAC_CONFIG_GMII_SPEED |
6204 MVPP2_GMAC_CONFIG_FULL_DUPLEX;
6206 /* The FLOW_CTRL_AUTONEG bit selects either the hardware
6207 * automatically or the bits in MVPP22_GMAC_CTRL_4_REG
6208 * manually controls the GMAC pause modes.
6210 if (permit_pause_to_mac)
6211 val |= MVPP2_GMAC_FLOW_CTRL_AUTONEG;
6213 /* Configure advertisement bits */
6214 mask |= MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN;
6215 if (phylink_test(advertising, Pause))
6216 val |= MVPP2_GMAC_FC_ADV_EN;
6217 if (phylink_test(advertising, Asym_Pause))
6218 val |= MVPP2_GMAC_FC_ADV_ASM_EN;
6224 old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6225 an = (an & ~mask) | val;
6226 changed = an ^ old_an;
6228 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6230 /* We are only interested in the advertisement bits changing */
6231 return changed & (MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN);
6234 static void mvpp2_gmac_pcs_an_restart(struct phylink_pcs *pcs)
6236 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs);
6237 u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6239 writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN,
6240 port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6241 writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN,
6242 port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6245 static const struct phylink_pcs_ops mvpp2_phylink_gmac_pcs_ops = {
6246 .pcs_get_state = mvpp2_gmac_pcs_get_state,
6247 .pcs_config = mvpp2_gmac_pcs_config,
6248 .pcs_an_restart = mvpp2_gmac_pcs_an_restart,
6251 static void mvpp2_phylink_validate(struct phylink_config *config,
6252 unsigned long *supported,
6253 struct phylink_link_state *state)
6255 struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6256 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
6258 /* Invalid combinations */
6259 switch (state->interface) {
6260 case PHY_INTERFACE_MODE_10GBASER:
6261 case PHY_INTERFACE_MODE_XAUI:
6262 if (!mvpp2_port_supports_xlg(port))
6265 case PHY_INTERFACE_MODE_RGMII:
6266 case PHY_INTERFACE_MODE_RGMII_ID:
6267 case PHY_INTERFACE_MODE_RGMII_RXID:
6268 case PHY_INTERFACE_MODE_RGMII_TXID:
6269 if (!mvpp2_port_supports_rgmii(port))
6272 case PHY_INTERFACE_MODE_1000BASEX:
6273 case PHY_INTERFACE_MODE_2500BASEX:
6274 /* When in 802.3z mode, we must have AN enabled:
6275 * Bit 2 Field InBandAnEn In-band Auto-Negotiation enable. ...
6276 * When <PortType> = 1 (1000BASE-X) this field must be set to 1.
6278 if (!phylink_test(state->advertising, Autoneg))
6285 phylink_set(mask, Autoneg);
6286 phylink_set_port_modes(mask);
6288 if (port->priv->global_tx_fc) {
6289 phylink_set(mask, Pause);
6290 phylink_set(mask, Asym_Pause);
6293 switch (state->interface) {
6294 case PHY_INTERFACE_MODE_10GBASER:
6295 case PHY_INTERFACE_MODE_XAUI:
6296 case PHY_INTERFACE_MODE_NA:
6297 if (mvpp2_port_supports_xlg(port)) {
6298 phylink_set(mask, 10000baseT_Full);
6299 phylink_set(mask, 10000baseCR_Full);
6300 phylink_set(mask, 10000baseSR_Full);
6301 phylink_set(mask, 10000baseLR_Full);
6302 phylink_set(mask, 10000baseLRM_Full);
6303 phylink_set(mask, 10000baseER_Full);
6304 phylink_set(mask, 10000baseKR_Full);
6306 if (state->interface != PHY_INTERFACE_MODE_NA)
6309 case PHY_INTERFACE_MODE_RGMII:
6310 case PHY_INTERFACE_MODE_RGMII_ID:
6311 case PHY_INTERFACE_MODE_RGMII_RXID:
6312 case PHY_INTERFACE_MODE_RGMII_TXID:
6313 case PHY_INTERFACE_MODE_SGMII:
6314 phylink_set(mask, 10baseT_Half);
6315 phylink_set(mask, 10baseT_Full);
6316 phylink_set(mask, 100baseT_Half);
6317 phylink_set(mask, 100baseT_Full);
6318 phylink_set(mask, 1000baseT_Full);
6319 phylink_set(mask, 1000baseX_Full);
6320 if (state->interface != PHY_INTERFACE_MODE_NA)
6323 case PHY_INTERFACE_MODE_1000BASEX:
6324 case PHY_INTERFACE_MODE_2500BASEX:
6326 state->interface != PHY_INTERFACE_MODE_2500BASEX) {
6327 phylink_set(mask, 1000baseT_Full);
6328 phylink_set(mask, 1000baseX_Full);
6331 state->interface == PHY_INTERFACE_MODE_2500BASEX) {
6332 phylink_set(mask, 2500baseT_Full);
6333 phylink_set(mask, 2500baseX_Full);
6340 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
6341 bitmap_and(state->advertising, state->advertising, mask,
6342 __ETHTOOL_LINK_MODE_MASK_NBITS);
6344 phylink_helper_basex_speed(state);
6348 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
6351 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
6352 const struct phylink_link_state *state)
6356 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6357 MVPP22_XLG_CTRL0_MAC_RESET_DIS,
6358 MVPP22_XLG_CTRL0_MAC_RESET_DIS);
6359 mvpp2_modify(port->base + MVPP22_XLG_CTRL4_REG,
6360 MVPP22_XLG_CTRL4_MACMODSELECT_GMAC |
6361 MVPP22_XLG_CTRL4_EN_IDLE_CHECK |
6362 MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC,
6363 MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC);
6365 /* Wait for reset to deassert */
6367 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
6368 } while (!(val & MVPP22_XLG_CTRL0_MAC_RESET_DIS));
6371 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
6372 const struct phylink_link_state *state)
6374 u32 old_ctrl0, ctrl0;
6375 u32 old_ctrl2, ctrl2;
6376 u32 old_ctrl4, ctrl4;
6378 old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
6379 old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
6380 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
6382 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
6383 ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_FLOW_CTRL_MASK);
6385 /* Configure port type */
6386 if (phy_interface_mode_is_8023z(state->interface)) {
6387 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK;
6388 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
6389 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
6390 MVPP22_CTRL4_DP_CLK_SEL |
6391 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
6392 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
6393 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_INBAND_AN_MASK;
6394 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;
6395 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
6396 MVPP22_CTRL4_DP_CLK_SEL |
6397 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
6398 } else if (phy_interface_mode_is_rgmii(state->interface)) {
6399 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL;
6400 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |
6401 MVPP22_CTRL4_SYNC_BYPASS_DIS |
6402 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
6405 /* Configure negotiation style */
6406 if (!phylink_autoneg_inband(mode)) {
6407 /* Phy or fixed speed - no in-band AN, nothing to do, leave the
6408 * configured speed, duplex and flow control as-is.
6410 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
6411 /* SGMII in-band mode receives the speed and duplex from
6412 * the PHY. Flow control information is not received. */
6413 } else if (phy_interface_mode_is_8023z(state->interface)) {
6414 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can
6415 * they negotiate duplex: they are always operating with a fixed
6416 * speed of 1000/2500Mbps in full duplex, so force 1000/2500
6417 * speed and full duplex here.
6419 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK;
6422 if (old_ctrl0 != ctrl0)
6423 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG);
6424 if (old_ctrl2 != ctrl2)
6425 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
6426 if (old_ctrl4 != ctrl4)
6427 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG);
6430 static int mvpp2__mac_prepare(struct phylink_config *config, unsigned int mode,
6431 phy_interface_t interface)
6433 struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6435 /* Check for invalid configuration */
6436 if (mvpp2_is_xlg(interface) && port->gop_id != 0) {
6437 netdev_err(port->dev, "Invalid mode on %s\n", port->dev->name);
6441 if (port->phy_interface != interface ||
6442 phylink_autoneg_inband(mode)) {
6443 /* Force the link down when changing the interface or if in
6444 * in-band mode to ensure we do not change the configuration
6445 * while the hardware is indicating link is up. We force both
6446 * XLG and GMAC down to ensure that they're both in a known
6449 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG,
6450 MVPP2_GMAC_FORCE_LINK_PASS |
6451 MVPP2_GMAC_FORCE_LINK_DOWN,
6452 MVPP2_GMAC_FORCE_LINK_DOWN);
6454 if (mvpp2_port_supports_xlg(port))
6455 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6456 MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
6457 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN,
6458 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN);
6461 /* Make sure the port is disabled when reconfiguring the mode */
6462 mvpp2_port_disable(port);
6464 if (port->phy_interface != interface) {
6465 /* Place GMAC into reset */
6466 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG,
6467 MVPP2_GMAC_PORT_RESET_MASK,
6468 MVPP2_GMAC_PORT_RESET_MASK);
6470 if (port->priv->hw_version >= MVPP22) {
6471 mvpp22_gop_mask_irq(port);
6473 phy_power_off(port->comphy);
6477 /* Select the appropriate PCS operations depending on the
6478 * configured interface mode. We will only switch to a mode
6479 * that the validate() checks have already passed.
6481 if (mvpp2_is_xlg(interface))
6482 port->phylink_pcs.ops = &mvpp2_phylink_xlg_pcs_ops;
6484 port->phylink_pcs.ops = &mvpp2_phylink_gmac_pcs_ops;
6489 static int mvpp2_mac_prepare(struct phylink_config *config, unsigned int mode,
6490 phy_interface_t interface)
6492 struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6495 ret = mvpp2__mac_prepare(config, mode, interface);
6497 phylink_set_pcs(port->phylink, &port->phylink_pcs);
6502 static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode,
6503 const struct phylink_link_state *state)
6505 struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6507 /* mac (re)configuration */
6508 if (mvpp2_is_xlg(state->interface))
6509 mvpp2_xlg_config(port, mode, state);
6510 else if (phy_interface_mode_is_rgmii(state->interface) ||
6511 phy_interface_mode_is_8023z(state->interface) ||
6512 state->interface == PHY_INTERFACE_MODE_SGMII)
6513 mvpp2_gmac_config(port, mode, state);
6515 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK)
6516 mvpp2_port_loopback_set(port, state);
6519 static int mvpp2_mac_finish(struct phylink_config *config, unsigned int mode,
6520 phy_interface_t interface)
6522 struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6524 if (port->priv->hw_version >= MVPP22 &&
6525 port->phy_interface != interface) {
6526 port->phy_interface = interface;
6528 /* Reconfigure the serdes lanes */
6529 mvpp22_mode_reconfigure(port);
6531 /* Unmask interrupts */
6532 mvpp22_gop_unmask_irq(port);
6535 if (!mvpp2_is_xlg(interface)) {
6536 /* Release GMAC reset and wait */
6537 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG,
6538 MVPP2_GMAC_PORT_RESET_MASK, 0);
6540 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
6541 MVPP2_GMAC_PORT_RESET_MASK)
6545 mvpp2_port_enable(port);
6547 /* Allow the link to come up if in in-band mode, otherwise the
6548 * link is forced via mac_link_down()/mac_link_up()
6550 if (phylink_autoneg_inband(mode)) {
6551 if (mvpp2_is_xlg(interface))
6552 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6553 MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
6554 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN, 0);
6556 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG,
6557 MVPP2_GMAC_FORCE_LINK_PASS |
6558 MVPP2_GMAC_FORCE_LINK_DOWN, 0);
6564 static void mvpp2_mac_link_up(struct phylink_config *config,
6565 struct phy_device *phy,
6566 unsigned int mode, phy_interface_t interface,
6567 int speed, int duplex,
6568 bool tx_pause, bool rx_pause)
6570 struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6574 if (mvpp2_is_xlg(interface)) {
6575 if (!phylink_autoneg_inband(mode)) {
6576 val = MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
6578 val |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
6580 val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
6582 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
6583 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN |
6584 MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
6585 MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN |
6586 MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN, val);
6589 if (!phylink_autoneg_inband(mode)) {
6590 val = MVPP2_GMAC_FORCE_LINK_PASS;
6592 if (speed == SPEED_1000 || speed == SPEED_2500)
6593 val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
6594 else if (speed == SPEED_100)
6595 val |= MVPP2_GMAC_CONFIG_MII_SPEED;
6597 if (duplex == DUPLEX_FULL)
6598 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
6600 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG,
6601 MVPP2_GMAC_FORCE_LINK_DOWN |
6602 MVPP2_GMAC_FORCE_LINK_PASS |
6603 MVPP2_GMAC_CONFIG_MII_SPEED |
6604 MVPP2_GMAC_CONFIG_GMII_SPEED |
6605 MVPP2_GMAC_CONFIG_FULL_DUPLEX, val);
6608 /* We can always update the flow control enable bits;
6609 * these will only be effective if flow control AN
6610 * (MVPP2_GMAC_FLOW_CTRL_AUTONEG) is disabled.
6614 val |= MVPP22_CTRL4_TX_FC_EN;
6616 val |= MVPP22_CTRL4_RX_FC_EN;
6618 mvpp2_modify(port->base + MVPP22_GMAC_CTRL_4_REG,
6619 MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN,
6623 if (port->priv->global_tx_fc) {
6624 port->tx_fc = tx_pause;
6626 mvpp2_rxq_enable_fc(port);
6628 mvpp2_rxq_disable_fc(port);
6629 if (port->priv->percpu_pools) {
6630 for (i = 0; i < port->nrxqs; i++)
6631 mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i], tx_pause);
6633 mvpp2_bm_pool_update_fc(port, port->pool_long, tx_pause);
6634 mvpp2_bm_pool_update_fc(port, port->pool_short, tx_pause);
6636 if (port->priv->hw_version == MVPP23)
6637 mvpp23_rx_fifo_fc_en(port->priv, port->id, tx_pause);
6640 mvpp2_port_enable(port);
6642 mvpp2_egress_enable(port);
6643 mvpp2_ingress_enable(port);
6644 netif_tx_wake_all_queues(port->dev);
6647 static void mvpp2_mac_link_down(struct phylink_config *config,
6648 unsigned int mode, phy_interface_t interface)
6650 struct mvpp2_port *port = mvpp2_phylink_to_port(config);
6653 if (!phylink_autoneg_inband(mode)) {
6654 if (mvpp2_is_xlg(interface)) {
6655 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
6656 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
6657 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
6658 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
6660 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6661 val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
6662 val |= MVPP2_GMAC_FORCE_LINK_DOWN;
6663 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
6667 netif_tx_stop_all_queues(port->dev);
6668 mvpp2_egress_disable(port);
6669 mvpp2_ingress_disable(port);
6671 mvpp2_port_disable(port);
6674 static const struct phylink_mac_ops mvpp2_phylink_ops = {
6675 .validate = mvpp2_phylink_validate,
6676 .mac_prepare = mvpp2_mac_prepare,
6677 .mac_config = mvpp2_mac_config,
6678 .mac_finish = mvpp2_mac_finish,
6679 .mac_link_up = mvpp2_mac_link_up,
6680 .mac_link_down = mvpp2_mac_link_down,
6683 /* Work-around for ACPI */
6684 static void mvpp2_acpi_start(struct mvpp2_port *port)
6686 /* Phylink isn't used as of now for ACPI, so the MAC has to be
6687 * configured manually when the interface is started. This will
6688 * be removed as soon as the phylink ACPI support lands in.
6690 struct phylink_link_state state = {
6691 .interface = port->phy_interface,
6693 mvpp2__mac_prepare(&port->phylink_config, MLO_AN_INBAND,
6694 port->phy_interface);
6695 mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state);
6696 port->phylink_pcs.ops->pcs_config(&port->phylink_pcs, MLO_AN_INBAND,
6697 port->phy_interface,
6698 state.advertising, false);
6699 mvpp2_mac_finish(&port->phylink_config, MLO_AN_INBAND,
6700 port->phy_interface);
6701 mvpp2_mac_link_up(&port->phylink_config, NULL,
6702 MLO_AN_INBAND, port->phy_interface,
6703 SPEED_UNKNOWN, DUPLEX_UNKNOWN, false, false);
6706 /* In order to ensure backward compatibility for ACPI, check if the port
6707 * firmware node comprises the necessary description allowing to use phylink.
6709 static bool mvpp2_use_acpi_compat_mode(struct fwnode_handle *port_fwnode)
6711 if (!is_acpi_node(port_fwnode))
6714 return (!fwnode_property_present(port_fwnode, "phy-handle") &&
6715 !fwnode_property_present(port_fwnode, "managed") &&
6716 !fwnode_get_named_child_node(port_fwnode, "fixed-link"));
6719 /* Ports initialization */
6720 static int mvpp2_port_probe(struct platform_device *pdev,
6721 struct fwnode_handle *port_fwnode,
6724 struct phy *comphy = NULL;
6725 struct mvpp2_port *port;
6726 struct mvpp2_port_pcpu *port_pcpu;
6727 struct device_node *port_node = to_of_node(port_fwnode);
6728 netdev_features_t features;
6729 struct net_device *dev;
6730 struct phylink *phylink;
6731 char *mac_from = "";
6732 unsigned int ntxqs, nrxqs, thread;
6733 unsigned long flags = 0;
6739 has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags);
6740 if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) {
6742 "not enough IRQs to support multi queue mode\n");
6746 ntxqs = MVPP2_MAX_TXQ;
6747 nrxqs = mvpp2_get_nrxqs(priv);
6749 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs);
6753 phy_mode = fwnode_get_phy_mode(port_fwnode);
6755 dev_err(&pdev->dev, "incorrect phy mode\n");
6757 goto err_free_netdev;
6761 * Rewrite 10GBASE-KR to 10GBASE-R for compatibility with existing DT.
6762 * Existing usage of 10GBASE-KR is not correct; no backplane
6763 * negotiation is done, and this driver does not actually support
6766 if (phy_mode == PHY_INTERFACE_MODE_10GKR)
6767 phy_mode = PHY_INTERFACE_MODE_10GBASER;
6770 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL);
6771 if (IS_ERR(comphy)) {
6772 if (PTR_ERR(comphy) == -EPROBE_DEFER) {
6773 err = -EPROBE_DEFER;
6774 goto err_free_netdev;
6780 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) {
6782 dev_err(&pdev->dev, "missing port-id value\n");
6783 goto err_free_netdev;
6786 dev->tx_queue_len = MVPP2_MAX_TXD_MAX;
6787 dev->watchdog_timeo = 5 * HZ;
6788 dev->netdev_ops = &mvpp2_netdev_ops;
6789 dev->ethtool_ops = &mvpp2_eth_tool_ops;
6791 port = netdev_priv(dev);
6793 port->fwnode = port_fwnode;
6794 port->ntxqs = ntxqs;
6795 port->nrxqs = nrxqs;
6797 port->has_tx_irqs = has_tx_irqs;
6798 port->flags = flags;
6800 err = mvpp2_queue_vectors_init(port, port_node);
6802 goto err_free_netdev;
6805 port->port_irq = of_irq_get_byname(port_node, "link");
6807 port->port_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1);
6808 if (port->port_irq == -EPROBE_DEFER) {
6809 err = -EPROBE_DEFER;
6810 goto err_deinit_qvecs;
6812 if (port->port_irq <= 0)
6813 /* the link irq is optional */
6816 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback"))
6817 port->flags |= MVPP2_F_LOOPBACK;
6820 if (priv->hw_version == MVPP21)
6821 port->first_rxq = port->id * port->nrxqs;
6823 port->first_rxq = port->id * priv->max_port_rxqs;
6825 port->of_node = port_node;
6826 port->phy_interface = phy_mode;
6827 port->comphy = comphy;
6829 if (priv->hw_version == MVPP21) {
6830 port->base = devm_platform_ioremap_resource(pdev, 2 + id);
6831 if (IS_ERR(port->base)) {
6832 err = PTR_ERR(port->base);
6836 port->stats_base = port->priv->lms_base +
6837 MVPP21_MIB_COUNTERS_OFFSET +
6838 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ;
6840 if (fwnode_property_read_u32(port_fwnode, "gop-port-id",
6843 dev_err(&pdev->dev, "missing gop-port-id value\n");
6844 goto err_deinit_qvecs;
6847 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id);
6848 port->stats_base = port->priv->iface_base +
6849 MVPP22_MIB_COUNTERS_OFFSET +
6850 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ;
6852 /* We may want a property to describe whether we should use
6853 * MAC hardware timestamping.
6856 port->hwtstamp = true;
6859 /* Alloc per-cpu and ethtool stats */
6860 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);
6866 port->ethtool_stats = devm_kcalloc(&pdev->dev,
6867 MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs),
6868 sizeof(u64), GFP_KERNEL);
6869 if (!port->ethtool_stats) {
6871 goto err_free_stats;
6874 mutex_init(&port->gather_stats_lock);
6875 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics);
6877 mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from);
6879 port->tx_ring_size = MVPP2_MAX_TXD_DFLT;
6880 port->rx_ring_size = MVPP2_MAX_RXD_DFLT;
6881 SET_NETDEV_DEV(dev, &pdev->dev);
6883 err = mvpp2_port_init(port);
6885 dev_err(&pdev->dev, "failed to init port %d\n", id);
6886 goto err_free_stats;
6889 mvpp2_port_periodic_xon_disable(port);
6891 mvpp2_mac_reset_assert(port);
6892 mvpp22_pcs_reset_assert(port);
6894 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu);
6897 goto err_free_txq_pcpu;
6900 if (!port->has_tx_irqs) {
6901 for (thread = 0; thread < priv->nthreads; thread++) {
6902 port_pcpu = per_cpu_ptr(port->pcpu, thread);
6904 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC,
6905 HRTIMER_MODE_REL_PINNED_SOFT);
6906 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb;
6907 port_pcpu->timer_scheduled = false;
6908 port_pcpu->dev = dev;
6912 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6914 dev->features = features | NETIF_F_RXCSUM;
6915 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO |
6916 NETIF_F_HW_VLAN_CTAG_FILTER;
6918 if (mvpp22_rss_is_supported(port)) {
6919 dev->hw_features |= NETIF_F_RXHASH;
6920 dev->features |= NETIF_F_NTUPLE;
6923 if (!port->priv->percpu_pools)
6924 mvpp2_set_hw_csum(port, port->pool_long->id);
6926 dev->vlan_features |= features;
6927 dev->gso_max_segs = MVPP2_MAX_TSO_SEGS;
6928 dev->priv_flags |= IFF_UNICAST_FLT;
6930 /* MTU range: 68 - 9704 */
6931 dev->min_mtu = ETH_MIN_MTU;
6932 /* 9704 == 9728 - 20 and rounding to 8 */
6933 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE;
6934 dev->dev.of_node = port_node;
6936 if (!mvpp2_use_acpi_compat_mode(port_fwnode)) {
6937 port->phylink_config.dev = &dev->dev;
6938 port->phylink_config.type = PHYLINK_NETDEV;
6940 phylink = phylink_create(&port->phylink_config, port_fwnode,
6941 phy_mode, &mvpp2_phylink_ops);
6942 if (IS_ERR(phylink)) {
6943 err = PTR_ERR(phylink);
6944 goto err_free_port_pcpu;
6946 port->phylink = phylink;
6948 dev_warn(&pdev->dev, "Use link irqs for port#%d. FW update required\n", port->id);
6949 port->phylink = NULL;
6952 /* Cycle the comphy to power it down, saving 270mW per port -
6953 * don't worry about an error powering it up. When the comphy
6954 * driver does this, we can remove this code.
6957 err = mvpp22_comphy_init(port);
6959 phy_power_off(port->comphy);
6962 err = register_netdev(dev);
6964 dev_err(&pdev->dev, "failed to register netdev\n");
6967 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
6969 priv->port_list[priv->port_count++] = port;
6975 phylink_destroy(port->phylink);
6977 free_percpu(port->pcpu);
6979 for (i = 0; i < port->ntxqs; i++)
6980 free_percpu(port->txqs[i]->pcpu);
6982 free_percpu(port->stats);
6985 irq_dispose_mapping(port->port_irq);
6987 mvpp2_queue_vectors_deinit(port);
6993 /* Ports removal routine */
6994 static void mvpp2_port_remove(struct mvpp2_port *port)
6998 unregister_netdev(port->dev);
7000 phylink_destroy(port->phylink);
7001 free_percpu(port->pcpu);
7002 free_percpu(port->stats);
7003 for (i = 0; i < port->ntxqs; i++)
7004 free_percpu(port->txqs[i]->pcpu);
7005 mvpp2_queue_vectors_deinit(port);
7007 irq_dispose_mapping(port->port_irq);
7008 free_netdev(port->dev);
7011 /* Initialize decoding windows */
7012 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
7018 for (i = 0; i < 6; i++) {
7019 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
7020 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
7023 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
7028 for (i = 0; i < dram->num_cs; i++) {
7029 const struct mbus_dram_window *cs = dram->cs + i;
7031 mvpp2_write(priv, MVPP2_WIN_BASE(i),
7032 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
7033 dram->mbus_dram_target_id);
7035 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
7036 (cs->size - 1) & 0xffff0000);
7038 win_enable |= (1 << i);
7041 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
7044 /* Initialize Rx FIFO's */
7045 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
7049 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
7050 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
7051 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
7052 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
7053 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
7056 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
7057 MVPP2_RX_FIFO_PORT_MIN_PKT);
7058 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
7061 static void mvpp22_rx_fifo_set_hw(struct mvpp2 *priv, int port, int data_size)
7063 int attr_size = MVPP2_RX_FIFO_PORT_ATTR_SIZE(data_size);
7065 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), data_size);
7066 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), attr_size);
7069 /* Initialize TX FIFO's: the total FIFO size is 48kB on PPv2.2 and PPv2.3.
7070 * 4kB fixed space must be assigned for the loopback port.
7071 * Redistribute remaining avialable 44kB space among all active ports.
7072 * Guarantee minimum 32kB for 10G port and 8kB for port 1, capable of 2.5G
7075 static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
7077 int remaining_ports_count;
7078 unsigned long port_map;
7082 /* The loopback requires fixed 4kB of the FIFO space assignment. */
7083 mvpp22_rx_fifo_set_hw(priv, MVPP2_LOOPBACK_PORT_INDEX,
7084 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
7085 port_map = priv->port_map & ~BIT(MVPP2_LOOPBACK_PORT_INDEX);
7087 /* Set RX FIFO size to 0 for inactive ports. */
7088 for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX)
7089 mvpp22_rx_fifo_set_hw(priv, port, 0);
7091 /* Assign remaining RX FIFO space among all active ports. */
7092 size_remainder = MVPP2_RX_FIFO_PORT_DATA_SIZE_44KB;
7093 remaining_ports_count = hweight_long(port_map);
7095 for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) {
7096 if (remaining_ports_count == 1)
7097 size = size_remainder;
7099 size = max(size_remainder / remaining_ports_count,
7100 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB);
7102 size = max(size_remainder / remaining_ports_count,
7103 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB);
7105 size = size_remainder / remaining_ports_count;
7107 size_remainder -= size;
7108 remaining_ports_count--;
7110 mvpp22_rx_fifo_set_hw(priv, port, size);
7113 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
7114 MVPP2_RX_FIFO_PORT_MIN_PKT);
7115 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
7118 /* Configure Rx FIFO Flow control thresholds */
7119 static void mvpp23_rx_fifo_fc_set_tresh(struct mvpp2 *priv)
7123 /* Port 0: maximum speed -10Gb/s port
7124 * required by spec RX FIFO threshold 9KB
7125 * Port 1: maximum speed -5Gb/s port
7126 * required by spec RX FIFO threshold 4KB
7127 * Port 2: maximum speed -1Gb/s port
7128 * required by spec RX FIFO threshold 2KB
7131 /* Without loopback port */
7132 for (port = 0; port < (MVPP2_MAX_PORTS - 1); port++) {
7134 val = (MVPP23_PORT0_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
7135 << MVPP2_RX_FC_TRSH_OFFS;
7136 val &= MVPP2_RX_FC_TRSH_MASK;
7137 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
7138 } else if (port == 1) {
7139 val = (MVPP23_PORT1_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
7140 << MVPP2_RX_FC_TRSH_OFFS;
7141 val &= MVPP2_RX_FC_TRSH_MASK;
7142 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
7144 val = (MVPP23_PORT2_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
7145 << MVPP2_RX_FC_TRSH_OFFS;
7146 val &= MVPP2_RX_FC_TRSH_MASK;
7147 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
7152 /* Configure Rx FIFO Flow control thresholds */
7153 void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en)
7157 val = mvpp2_read(priv, MVPP2_RX_FC_REG(port));
7160 val |= MVPP2_RX_FC_EN;
7162 val &= ~MVPP2_RX_FC_EN;
7164 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
7167 static void mvpp22_tx_fifo_set_hw(struct mvpp2 *priv, int port, int size)
7169 int threshold = MVPP2_TX_FIFO_THRESHOLD(size);
7171 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size);
7172 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), threshold);
7175 /* Initialize TX FIFO's: the total FIFO size is 19kB on PPv2.2 and PPv2.3.
7176 * 1kB fixed space must be assigned for the loopback port.
7177 * Redistribute remaining avialable 18kB space among all active ports.
7178 * The 10G interface should use 10kB (which is maximum possible size
7181 static void mvpp22_tx_fifo_init(struct mvpp2 *priv)
7183 int remaining_ports_count;
7184 unsigned long port_map;
7188 /* The loopback requires fixed 1kB of the FIFO space assignment. */
7189 mvpp22_tx_fifo_set_hw(priv, MVPP2_LOOPBACK_PORT_INDEX,
7190 MVPP22_TX_FIFO_DATA_SIZE_1KB);
7191 port_map = priv->port_map & ~BIT(MVPP2_LOOPBACK_PORT_INDEX);
7193 /* Set TX FIFO size to 0 for inactive ports. */
7194 for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX)
7195 mvpp22_tx_fifo_set_hw(priv, port, 0);
7197 /* Assign remaining TX FIFO space among all active ports. */
7198 size_remainder = MVPP22_TX_FIFO_DATA_SIZE_18KB;
7199 remaining_ports_count = hweight_long(port_map);
7201 for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) {
7202 if (remaining_ports_count == 1)
7203 size = min(size_remainder,
7204 MVPP22_TX_FIFO_DATA_SIZE_10KB);
7206 size = MVPP22_TX_FIFO_DATA_SIZE_10KB;
7208 size = size_remainder / remaining_ports_count;
7210 size_remainder -= size;
7211 remaining_ports_count--;
7213 mvpp22_tx_fifo_set_hw(priv, port, size);
7217 static void mvpp2_axi_init(struct mvpp2 *priv)
7219 u32 val, rdval, wrval;
7221 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
7223 /* AXI Bridge Configuration */
7225 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
7226 << MVPP22_AXI_ATTR_CACHE_OFFS;
7227 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
7228 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
7230 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
7231 << MVPP22_AXI_ATTR_CACHE_OFFS;
7232 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
7233 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
7236 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
7237 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
7240 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
7241 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
7242 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
7243 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
7246 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
7247 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
7249 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
7250 << MVPP22_AXI_CODE_CACHE_OFFS;
7251 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
7252 << MVPP22_AXI_CODE_DOMAIN_OFFS;
7253 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
7254 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
7256 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
7257 << MVPP22_AXI_CODE_CACHE_OFFS;
7258 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
7259 << MVPP22_AXI_CODE_DOMAIN_OFFS;
7261 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
7263 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
7264 << MVPP22_AXI_CODE_CACHE_OFFS;
7265 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
7266 << MVPP22_AXI_CODE_DOMAIN_OFFS;
7268 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
7271 /* Initialize network controller common part HW */
7272 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
7274 const struct mbus_dram_target_info *dram_target_info;
7278 /* MBUS windows configuration */
7279 dram_target_info = mv_mbus_dram_info();
7280 if (dram_target_info)
7281 mvpp2_conf_mbus_windows(dram_target_info, priv);
7283 if (priv->hw_version >= MVPP22)
7284 mvpp2_axi_init(priv);
7286 /* Disable HW PHY polling */
7287 if (priv->hw_version == MVPP21) {
7288 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
7289 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
7290 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
7292 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
7293 val &= ~MVPP22_SMI_POLLING_EN;
7294 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
7297 /* Allocate and initialize aggregated TXQs */
7298 priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS,
7299 sizeof(*priv->aggr_txqs),
7301 if (!priv->aggr_txqs)
7304 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
7305 priv->aggr_txqs[i].id = i;
7306 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
7307 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv);
7313 if (priv->hw_version == MVPP21) {
7314 mvpp2_rx_fifo_init(priv);
7316 mvpp22_rx_fifo_init(priv);
7317 mvpp22_tx_fifo_init(priv);
7318 if (priv->hw_version == MVPP23)
7319 mvpp23_rx_fifo_fc_set_tresh(priv);
7322 if (priv->hw_version == MVPP21)
7323 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
7324 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
7326 /* Allow cache snoop when transmiting packets */
7327 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
7329 /* Buffer Manager initialization */
7330 err = mvpp2_bm_init(&pdev->dev, priv);
7334 /* Parser default initialization */
7335 err = mvpp2_prs_default_init(pdev, priv);
7339 /* Classifier default initialization */
7340 mvpp2_cls_init(priv);
7345 static int mvpp2_get_sram(struct platform_device *pdev,
7348 struct resource *res;
7350 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
7352 if (has_acpi_companion(&pdev->dev))
7353 dev_warn(&pdev->dev, "ACPI is too old, Flow control not supported\n");
7355 dev_warn(&pdev->dev, "DT is too old, Flow control not supported\n");
7359 priv->cm3_base = devm_ioremap_resource(&pdev->dev, res);
7361 return PTR_ERR_OR_ZERO(priv->cm3_base);
7364 static int mvpp2_probe(struct platform_device *pdev)
7366 struct fwnode_handle *fwnode = pdev->dev.fwnode;
7367 struct fwnode_handle *port_fwnode;
7369 struct resource *res;
7374 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
7378 priv->hw_version = (unsigned long)device_get_match_data(&pdev->dev);
7380 /* multi queue mode isn't supported on PPV2.1, fallback to single
7383 if (priv->hw_version == MVPP21)
7384 queue_mode = MVPP2_QDIST_SINGLE_MODE;
7386 base = devm_platform_ioremap_resource(pdev, 0);
7388 return PTR_ERR(base);
7390 if (priv->hw_version == MVPP21) {
7391 priv->lms_base = devm_platform_ioremap_resource(pdev, 1);
7392 if (IS_ERR(priv->lms_base))
7393 return PTR_ERR(priv->lms_base);
7395 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
7397 dev_err(&pdev->dev, "Invalid resource\n");
7400 if (has_acpi_companion(&pdev->dev)) {
7401 /* In case the MDIO memory region is declared in
7402 * the ACPI, it can already appear as 'in-use'
7403 * in the OS. Because it is overlapped by second
7404 * region of the network controller, make
7405 * sure it is released, before requesting it again.
7406 * The care is taken by mvpp2 driver to avoid
7407 * concurrent access to this memory region.
7409 release_resource(res);
7411 priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
7412 if (IS_ERR(priv->iface_base))
7413 return PTR_ERR(priv->iface_base);
7416 err = mvpp2_get_sram(pdev, priv);
7418 dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n");
7420 /* Enable global Flow Control only if handler to SRAM not NULL */
7422 priv->global_tx_fc = true;
7425 if (priv->hw_version >= MVPP22 && dev_of_node(&pdev->dev)) {
7426 priv->sysctrl_base =
7427 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
7428 "marvell,system-controller");
7429 if (IS_ERR(priv->sysctrl_base))
7430 /* The system controller regmap is optional for dt
7431 * compatibility reasons. When not provided, the
7432 * configuration of the GoP relies on the
7433 * firmware/bootloader.
7435 priv->sysctrl_base = NULL;
7438 if (priv->hw_version >= MVPP22 &&
7439 mvpp2_get_nrxqs(priv) * 2 <= MVPP2_BM_MAX_POOLS)
7440 priv->percpu_pools = 1;
7442 mvpp2_setup_bm_pool();
7445 priv->nthreads = min_t(unsigned int, num_present_cpus(),
7448 shared = num_present_cpus() - priv->nthreads;
7450 bitmap_fill(&priv->lock_map,
7451 min_t(int, shared, MVPP2_MAX_THREADS));
7453 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
7456 addr_space_sz = (priv->hw_version == MVPP21 ?
7457 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ);
7458 priv->swth_base[i] = base + i * addr_space_sz;
7461 if (priv->hw_version == MVPP21)
7462 priv->max_port_rxqs = 8;
7464 priv->max_port_rxqs = 32;
7466 if (dev_of_node(&pdev->dev)) {
7467 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
7468 if (IS_ERR(priv->pp_clk))
7469 return PTR_ERR(priv->pp_clk);
7470 err = clk_prepare_enable(priv->pp_clk);
7474 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
7475 if (IS_ERR(priv->gop_clk)) {
7476 err = PTR_ERR(priv->gop_clk);
7479 err = clk_prepare_enable(priv->gop_clk);
7483 if (priv->hw_version >= MVPP22) {
7484 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
7485 if (IS_ERR(priv->mg_clk)) {
7486 err = PTR_ERR(priv->mg_clk);
7490 err = clk_prepare_enable(priv->mg_clk);
7494 priv->mg_core_clk = devm_clk_get_optional(&pdev->dev, "mg_core_clk");
7495 if (IS_ERR(priv->mg_core_clk)) {
7496 err = PTR_ERR(priv->mg_core_clk);
7500 err = clk_prepare_enable(priv->mg_core_clk);
7505 priv->axi_clk = devm_clk_get_optional(&pdev->dev, "axi_clk");
7506 if (IS_ERR(priv->axi_clk)) {
7507 err = PTR_ERR(priv->axi_clk);
7508 goto err_mg_core_clk;
7511 err = clk_prepare_enable(priv->axi_clk);
7513 goto err_mg_core_clk;
7515 /* Get system's tclk rate */
7516 priv->tclk = clk_get_rate(priv->pp_clk);
7518 err = device_property_read_u32(&pdev->dev, "clock-frequency", &priv->tclk);
7520 dev_err(&pdev->dev, "missing clock-frequency value\n");
7525 if (priv->hw_version >= MVPP22) {
7526 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
7529 /* Sadly, the BM pools all share the same register to
7530 * store the high 32 bits of their address. So they
7531 * must all have the same high 32 bits, which forces
7532 * us to restrict coherent memory to DMA_BIT_MASK(32).
7534 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
7539 /* Map DTS-active ports. Should be done before FIFO mvpp2_init */
7540 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7541 if (!fwnode_property_read_u32(port_fwnode, "port-id", &i))
7542 priv->port_map |= BIT(i);
7545 if (mvpp2_read(priv, MVPP2_VER_ID_REG) == MVPP2_VER_PP23)
7546 priv->hw_version = MVPP23;
7549 spin_lock_init(&priv->mss_spinlock);
7551 /* Initialize network controller */
7552 err = mvpp2_init(pdev, priv);
7554 dev_err(&pdev->dev, "failed to initialize controller\n");
7558 err = mvpp22_tai_probe(&pdev->dev, priv);
7562 /* Initialize ports */
7563 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7564 err = mvpp2_port_probe(pdev, port_fwnode, priv);
7566 goto err_port_probe;
7569 if (priv->port_count == 0) {
7570 dev_err(&pdev->dev, "no ports enabled\n");
7575 /* Statistics must be gathered regularly because some of them (like
7576 * packets counters) are 32-bit registers and could overflow quite
7577 * quickly. For instance, a 10Gb link used at full bandwidth with the
7578 * smallest packets (64B) will overflow a 32-bit counter in less than
7579 * 30 seconds. Then, use a workqueue to fill 64-bit counters.
7581 snprintf(priv->queue_name, sizeof(priv->queue_name),
7582 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev),
7583 priv->port_count > 1 ? "+" : "");
7584 priv->stats_queue = create_singlethread_workqueue(priv->queue_name);
7585 if (!priv->stats_queue) {
7587 goto err_port_probe;
7590 if (priv->global_tx_fc && priv->hw_version >= MVPP22) {
7591 err = mvpp2_enable_global_fc(priv);
7593 dev_warn(&pdev->dev, "Minimum of CM3 firmware 18.09 and chip revision B0 required for flow control\n");
7596 mvpp2_dbgfs_init(priv, pdev->name);
7598 platform_set_drvdata(pdev, priv);
7602 fwnode_handle_put(port_fwnode);
7605 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7606 if (priv->port_list[i])
7607 mvpp2_port_remove(priv->port_list[i]);
7611 clk_disable_unprepare(priv->axi_clk);
7613 clk_disable_unprepare(priv->mg_core_clk);
7615 clk_disable_unprepare(priv->mg_clk);
7617 clk_disable_unprepare(priv->gop_clk);
7619 clk_disable_unprepare(priv->pp_clk);
7623 static int mvpp2_remove(struct platform_device *pdev)
7625 struct mvpp2 *priv = platform_get_drvdata(pdev);
7626 struct fwnode_handle *fwnode = pdev->dev.fwnode;
7627 int i = 0, poolnum = MVPP2_BM_POOLS_NUM;
7628 struct fwnode_handle *port_fwnode;
7630 mvpp2_dbgfs_cleanup(priv);
7632 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
7633 if (priv->port_list[i]) {
7634 mutex_destroy(&priv->port_list[i]->gather_stats_lock);
7635 mvpp2_port_remove(priv->port_list[i]);
7640 destroy_workqueue(priv->stats_queue);
7642 if (priv->percpu_pools)
7643 poolnum = mvpp2_get_nrxqs(priv) * 2;
7645 for (i = 0; i < poolnum; i++) {
7646 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i];
7648 mvpp2_bm_pool_destroy(&pdev->dev, priv, bm_pool);
7651 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
7652 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i];
7654 dma_free_coherent(&pdev->dev,
7655 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
7657 aggr_txq->descs_dma);
7660 if (is_acpi_node(port_fwnode))
7663 clk_disable_unprepare(priv->axi_clk);
7664 clk_disable_unprepare(priv->mg_core_clk);
7665 clk_disable_unprepare(priv->mg_clk);
7666 clk_disable_unprepare(priv->pp_clk);
7667 clk_disable_unprepare(priv->gop_clk);
7672 static const struct of_device_id mvpp2_match[] = {
7674 .compatible = "marvell,armada-375-pp2",
7675 .data = (void *)MVPP21,
7678 .compatible = "marvell,armada-7k-pp22",
7679 .data = (void *)MVPP22,
7683 MODULE_DEVICE_TABLE(of, mvpp2_match);
7686 static const struct acpi_device_id mvpp2_acpi_match[] = {
7687 { "MRVL0110", MVPP22 },
7690 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match);
7693 static struct platform_driver mvpp2_driver = {
7694 .probe = mvpp2_probe,
7695 .remove = mvpp2_remove,
7697 .name = MVPP2_DRIVER_NAME,
7698 .of_match_table = mvpp2_match,
7699 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match),
7703 module_platform_driver(mvpp2_driver);
7705 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
7706 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
7707 MODULE_LICENSE("GPL v2");