drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for Marvell PPv2 network controller for Armada 375 SoC.
   4  *
   5  * Copyright (C) 2014 Marvell
   6  *
   7  * Marcin Wojtas <mw@semihalf.com>
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/kernel.h>
  12 #include <linux/netdevice.h>
  13 #include <linux/etherdevice.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/skbuff.h>
  16 #include <linux/inetdevice.h>
  17 #include <linux/mbus.h>
  18 #include <linux/module.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/cpumask.h>
  22 #include <linux/of.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/of_mdio.h>
  25 #include <linux/of_net.h>
  26 #include <linux/of_address.h>
  27 #include <linux/of_device.h>
  28 #include <linux/phy.h>
  29 #include <linux/phylink.h>
  30 #include <linux/phy/phy.h>
  31 #include <linux/clk.h>
  32 #include <linux/hrtimer.h>
  33 #include <linux/ktime.h>
  34 #include <linux/regmap.h>
  35 #include <uapi/linux/ppp_defs.h>
  36 #include <net/ip.h>
  37 #include <net/ipv6.h>
  38 #include <net/tso.h>
  39
  40 #include "mvpp2.h"
  41 #include "mvpp2_prs.h"
  42 #include "mvpp2_cls.h"
  43
  44 enum mvpp2_bm_pool_log_num {
  45         MVPP2_BM_SHORT,
  46         MVPP2_BM_LONG,
  47         MVPP2_BM_JUMBO,
  48         MVPP2_BM_POOLS_NUM
  49 };
  50
  51 static struct {
  52         int pkt_size;
  53         int buf_num;
  54 } mvpp2_pools[MVPP2_BM_POOLS_NUM];
  55
  56 /* The prototype is added here to be used in start_dev when using ACPI. This
  57  * will be removed once phylink is used for all modes (dt+ACPI).
  58  */
  59 static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
  60                              const struct phylink_link_state *state);
  61 static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode,
  62                               phy_interface_t interface, struct phy_device *phy);
  63
  64 /* Queue modes */
  65 #define MVPP2_QDIST_SINGLE_MODE 0
  66 #define MVPP2_QDIST_MULTI_MODE  1
  67
  68 static int queue_mode = MVPP2_QDIST_MULTI_MODE;
  69
  70 module_param(queue_mode, int, 0444);
  71 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)");
  72
  73 /* Utility/helper methods */
  74
  75 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
  76 {
  77         writel(data, priv->swth_base[0] + offset);
  78 }
  79
  80 u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
  81 {
  82         return readl(priv->swth_base[0] + offset);
  83 }
  84
  85 u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset)
  86 {
  87         return readl_relaxed(priv->swth_base[0] + offset);
  88 }
  89 /* These accessors should be used to access:
  90  *
  91  * - per-CPU registers, where each CPU has its own copy of the
  92  *   register.
  93  *
  94  *   MVPP2_BM_VIRT_ALLOC_REG
  95  *   MVPP2_BM_ADDR_HIGH_ALLOC
  96  *   MVPP22_BM_ADDR_HIGH_RLS_REG
  97  *   MVPP2_BM_VIRT_RLS_REG
  98  *   MVPP2_ISR_RX_TX_CAUSE_REG
  99  *   MVPP2_ISR_RX_TX_MASK_REG
 100  *   MVPP2_TXQ_NUM_REG
 101  *   MVPP2_AGGR_TXQ_UPDATE_REG
 102  *   MVPP2_TXQ_RSVD_REQ_REG
 103  *   MVPP2_TXQ_RSVD_RSLT_REG
 104  *   MVPP2_TXQ_SENT_REG
 105  *   MVPP2_RXQ_NUM_REG
 106  *
 107  * - global registers that must be accessed through a specific CPU
 108  *   window, because they are related to an access to a per-CPU
 109  *   register
 110  *
 111  *   MVPP2_BM_PHY_ALLOC_REG    (related to MVPP2_BM_VIRT_ALLOC_REG)
 112  *   MVPP2_BM_PHY_RLS_REG      (related to MVPP2_BM_VIRT_RLS_REG)
 113  *   MVPP2_RXQ_THRESH_REG      (related to MVPP2_RXQ_NUM_REG)
 114  *   MVPP2_RXQ_DESC_ADDR_REG   (related to MVPP2_RXQ_NUM_REG)
 115  *   MVPP2_RXQ_DESC_SIZE_REG   (related to MVPP2_RXQ_NUM_REG)
 116  *   MVPP2_RXQ_INDEX_REG       (related to MVPP2_RXQ_NUM_REG)
 117  *   MVPP2_TXQ_PENDING_REG     (related to MVPP2_TXQ_NUM_REG)
 118  *   MVPP2_TXQ_DESC_ADDR_REG   (related to MVPP2_TXQ_NUM_REG)
 119  *   MVPP2_TXQ_DESC_SIZE_REG   (related to MVPP2_TXQ_NUM_REG)
 120  *   MVPP2_TXQ_INDEX_REG       (related to MVPP2_TXQ_NUM_REG)
 121  *   MVPP2_TXQ_PENDING_REG     (related to MVPP2_TXQ_NUM_REG)
 122  *   MVPP2_TXQ_PREF_BUF_REG    (related to MVPP2_TXQ_NUM_REG)
 123  *   MVPP2_TXQ_PREF_BUF_REG    (related to MVPP2_TXQ_NUM_REG)
 124  */
 125 void mvpp2_percpu_write(struct mvpp2 *priv, int cpu,
 126                                u32 offset, u32 data)
 127 {
 128         writel(data, priv->swth_base[cpu] + offset);
 129 }
 130
 131 u32 mvpp2_percpu_read(struct mvpp2 *priv, int cpu,
 132                              u32 offset)
 133 {
 134         return readl(priv->swth_base[cpu] + offset);
 135 }
 136
 137 void mvpp2_percpu_write_relaxed(struct mvpp2 *priv, int cpu,
 138                                        u32 offset, u32 data)
 139 {
 140         writel_relaxed(data, priv->swth_base[cpu] + offset);
 141 }
 142
 143 static u32 mvpp2_percpu_read_relaxed(struct mvpp2 *priv, int cpu,
 144                                      u32 offset)
 145 {
 146         return readl_relaxed(priv->swth_base[cpu] + offset);
 147 }
 148
 149 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,
 150                                             struct mvpp2_tx_desc *tx_desc)
 151 {
 152         if (port->priv->hw_version == MVPP21)
 153                 return le32_to_cpu(tx_desc->pp21.buf_dma_addr);
 154         else
 155                 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) &
 156                        MVPP2_DESC_DMA_MASK;
 157 }
 158
 159 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
 160                                       struct mvpp2_tx_desc *tx_desc,
 161                                       dma_addr_t dma_addr)
 162 {
 163         dma_addr_t addr, offset;
 164
 165         addr = dma_addr & ~MVPP2_TX_DESC_ALIGN;
 166         offset = dma_addr & MVPP2_TX_DESC_ALIGN;
 167
 168         if (port->priv->hw_version == MVPP21) {
 169                 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr);
 170                 tx_desc->pp21.packet_offset = offset;
 171         } else {
 172                 __le64 val = cpu_to_le64(addr);
 173
 174                 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK);
 175                 tx_desc->pp22.buf_dma_addr_ptp |= val;
 176                 tx_desc->pp22.packet_offset = offset;
 177         }
 178 }
 179
 180 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port,
 181                                     struct mvpp2_tx_desc *tx_desc)
 182 {
 183         if (port->priv->hw_version == MVPP21)
 184                 return le16_to_cpu(tx_desc->pp21.data_size);
 185         else
 186                 return le16_to_cpu(tx_desc->pp22.data_size);
 187 }
 188
 189 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
 190                                   struct mvpp2_tx_desc *tx_desc,
 191                                   size_t size)
 192 {
 193         if (port->priv->hw_version == MVPP21)
 194                 tx_desc->pp21.data_size = cpu_to_le16(size);
 195         else
 196                 tx_desc->pp22.data_size = cpu_to_le16(size);
 197 }
 198
 199 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
 200                                  struct mvpp2_tx_desc *tx_desc,
 201                                  unsigned int txq)
 202 {
 203         if (port->priv->hw_version == MVPP21)
 204                 tx_desc->pp21.phys_txq = txq;
 205         else
 206                 tx_desc->pp22.phys_txq = txq;
 207 }
 208
 209 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
 210                                  struct mvpp2_tx_desc *tx_desc,
 211                                  unsigned int command)
 212 {
 213         if (port->priv->hw_version == MVPP21)
 214                 tx_desc->pp21.command = cpu_to_le32(command);
 215         else
 216                 tx_desc->pp22.command = cpu_to_le32(command);
 217 }
 218
 219 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port,
 220                                             struct mvpp2_tx_desc *tx_desc)
 221 {
 222         if (port->priv->hw_version == MVPP21)
 223                 return tx_desc->pp21.packet_offset;
 224         else
 225                 return tx_desc->pp22.packet_offset;
 226 }
 227
 228 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
 229                                             struct mvpp2_rx_desc *rx_desc)
 230 {
 231         if (port->priv->hw_version == MVPP21)
 232                 return le32_to_cpu(rx_desc->pp21.buf_dma_addr);
 233         else
 234                 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) &
 235                        MVPP2_DESC_DMA_MASK;
 236 }
 237
 238 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
 239                                              struct mvpp2_rx_desc *rx_desc)
 240 {
 241         if (port->priv->hw_version == MVPP21)
 242                 return le32_to_cpu(rx_desc->pp21.buf_cookie);
 243         else
 244                 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) &
 245                        MVPP2_DESC_DMA_MASK;
 246 }
 247
 248 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
 249                                     struct mvpp2_rx_desc *rx_desc)
 250 {
 251         if (port->priv->hw_version == MVPP21)
 252                 return le16_to_cpu(rx_desc->pp21.data_size);
 253         else
 254                 return le16_to_cpu(rx_desc->pp22.data_size);
 255 }
 256
 257 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
 258                                    struct mvpp2_rx_desc *rx_desc)
 259 {
 260         if (port->priv->hw_version == MVPP21)
 261                 return le32_to_cpu(rx_desc->pp21.status);
 262         else
 263                 return le32_to_cpu(rx_desc->pp22.status);
 264 }
 265
 266 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
 267 {
 268         txq_pcpu->txq_get_index++;
 269         if (txq_pcpu->txq_get_index == txq_pcpu->size)
 270                 txq_pcpu->txq_get_index = 0;
 271 }
 272
 273 static void mvpp2_txq_inc_put(struct mvpp2_port *port,
 274                               struct mvpp2_txq_pcpu *txq_pcpu,
 275                               struct sk_buff *skb,
 276                               struct mvpp2_tx_desc *tx_desc)
 277 {
 278         struct mvpp2_txq_pcpu_buf *tx_buf =
 279                 txq_pcpu->buffs + txq_pcpu->txq_put_index;
 280         tx_buf->skb = skb;
 281         tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc);
 282         tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) +
 283                 mvpp2_txdesc_offset_get(port, tx_desc);
 284         txq_pcpu->txq_put_index++;
 285         if (txq_pcpu->txq_put_index == txq_pcpu->size)
 286                 txq_pcpu->txq_put_index = 0;
 287 }
 288
 289 /* Get number of physical egress port */
 290 static inline int mvpp2_egress_port(struct mvpp2_port *port)
 291 {
 292         return MVPP2_MAX_TCONT + port->id;
 293 }
 294
 295 /* Get number of physical TXQ */
 296 static inline int mvpp2_txq_phys(int port, int txq)
 297 {
 298         return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
 299 }
 300
 301 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool)
 302 {
 303         if (likely(pool->frag_size <= PAGE_SIZE))
 304                 return netdev_alloc_frag(pool->frag_size);
 305         else
 306                 return kmalloc(pool->frag_size, GFP_ATOMIC);
 307 }
 308
 309 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data)
 310 {
 311         if (likely(pool->frag_size <= PAGE_SIZE))
 312                 skb_free_frag(data);
 313         else
 314                 kfree(data);
 315 }
 316
 317 /* Buffer Manager configuration routines */
 318
 319 /* Create pool */
 320 static int mvpp2_bm_pool_create(struct platform_device *pdev,
 321                                 struct mvpp2 *priv,
 322                                 struct mvpp2_bm_pool *bm_pool, int size)
 323 {
 324         u32 val;
 325
 326         /* Number of buffer pointers must be a multiple of 16, as per
 327          * hardware constraints
 328          */
 329         if (!IS_ALIGNED(size, 16))
 330                 return -EINVAL;
 331
 332         /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16
 333          * bytes per buffer pointer
 334          */
 335         if (priv->hw_version == MVPP21)
 336                 bm_pool->size_bytes = 2 * sizeof(u32) * size;
 337         else
 338                 bm_pool->size_bytes = 2 * sizeof(u64) * size;
 339
 340         bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, bm_pool->size_bytes,
 341                                                 &bm_pool->dma_addr,
 342                                                 GFP_KERNEL);
 343         if (!bm_pool->virt_addr)
 344                 return -ENOMEM;
 345
 346         if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
 347                         MVPP2_BM_POOL_PTR_ALIGN)) {
 348                 dma_free_coherent(&pdev->dev, bm_pool->size_bytes,
 349                                   bm_pool->virt_addr, bm_pool->dma_addr);
 350                 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
 351                         bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
 352                 return -ENOMEM;
 353         }
 354
 355         mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
 356                     lower_32_bits(bm_pool->dma_addr));
 357         mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
 358
 359         val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
 360         val |= MVPP2_BM_START_MASK;
 361         mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
 362
 363         bm_pool->size = size;
 364         bm_pool->pkt_size = 0;
 365         bm_pool->buf_num = 0;
 366
 367         return 0;
 368 }
 369
 370 /* Set pool buffer size */
 371 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
 372                                       struct mvpp2_bm_pool *bm_pool,
 373                                       int buf_size)
 374 {
 375         u32 val;
 376
 377         bm_pool->buf_size = buf_size;
 378
 379         val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
 380         mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
 381 }
 382
 383 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
 384                                     struct mvpp2_bm_pool *bm_pool,
 385                                     dma_addr_t *dma_addr,
 386                                     phys_addr_t *phys_addr)
 387 {
 388         int cpu = get_cpu();
 389
 390         *dma_addr = mvpp2_percpu_read(priv, cpu,
 391                                       MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
 392         *phys_addr = mvpp2_percpu_read(priv, cpu, MVPP2_BM_VIRT_ALLOC_REG);
 393
 394         if (priv->hw_version == MVPP22) {
 395                 u32 val;
 396                 u32 dma_addr_highbits, phys_addr_highbits;
 397
 398                 val = mvpp2_percpu_read(priv, cpu, MVPP22_BM_ADDR_HIGH_ALLOC);
 399                 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK);
 400                 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >>
 401                         MVPP22_BM_ADDR_HIGH_VIRT_SHIFT;
 402
 403                 if (sizeof(dma_addr_t) == 8)
 404                         *dma_addr |= (u64)dma_addr_highbits << 32;
 405
 406                 if (sizeof(phys_addr_t) == 8)
 407                         *phys_addr |= (u64)phys_addr_highbits << 32;
 408         }
 409
 410         put_cpu();
 411 }
 412
 413 /* Free all buffers from the pool */
 414 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv,
 415                                struct mvpp2_bm_pool *bm_pool, int buf_num)
 416 {
 417         int i;
 418
 419         if (buf_num > bm_pool->buf_num) {
 420                 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n",
 421                      bm_pool->id, buf_num);
 422                 buf_num = bm_pool->buf_num;
 423         }
 424
 425         for (i = 0; i < buf_num; i++) {
 426                 dma_addr_t buf_dma_addr;
 427                 phys_addr_t buf_phys_addr;
 428                 void *data;
 429
 430                 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool,
 431                                         &buf_dma_addr, &buf_phys_addr);
 432
 433                 dma_unmap_single(dev, buf_dma_addr,
 434                                  bm_pool->buf_size, DMA_FROM_DEVICE);
 435
 436                 data = (void *)phys_to_virt(buf_phys_addr);
 437                 if (!data)
 438                         break;
 439
 440                 mvpp2_frag_free(bm_pool, data);
 441         }
 442
 443         /* Update BM driver with number of buffers removed from pool */
 444         bm_pool->buf_num -= i;
 445 }
 446
 447 /* Check number of buffers in BM pool */
 448 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool)
 449 {
 450         int buf_num = 0;
 451
 452         buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) &
 453                                     MVPP22_BM_POOL_PTRS_NUM_MASK;
 454         buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) &
 455                                     MVPP2_BM_BPPI_PTR_NUM_MASK;
 456
 457         /* HW has one buffer ready which is not reflected in the counters */
 458         if (buf_num)
 459                 buf_num += 1;
 460
 461         return buf_num;
 462 }
 463
 464 /* Cleanup pool */
 465 static int mvpp2_bm_pool_destroy(struct platform_device *pdev,
 466                                  struct mvpp2 *priv,
 467                                  struct mvpp2_bm_pool *bm_pool)
 468 {
 469         int buf_num;
 470         u32 val;
 471
 472         buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
 473         mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool, buf_num);
 474
 475         /* Check buffer counters after free */
 476         buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
 477         if (buf_num) {
 478                 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n",
 479                      bm_pool->id, bm_pool->buf_num);
 480                 return 0;
 481         }
 482
 483         val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
 484         val |= MVPP2_BM_STOP_MASK;
 485         mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
 486
 487         dma_free_coherent(&pdev->dev, bm_pool->size_bytes,
 488                           bm_pool->virt_addr,
 489                           bm_pool->dma_addr);
 490         return 0;
 491 }
 492
 493 static int mvpp2_bm_pools_init(struct platform_device *pdev,
 494                                struct mvpp2 *priv)
 495 {
 496         int i, err, size;
 497         struct mvpp2_bm_pool *bm_pool;
 498
 499         /* Create all pools with maximum size */
 500         size = MVPP2_BM_POOL_SIZE_MAX;
 501         for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
 502                 bm_pool = &priv->bm_pools[i];
 503                 bm_pool->id = i;
 504                 err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size);
 505                 if (err)
 506                         goto err_unroll_pools;
 507                 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
 508         }
 509         return 0;
 510
 511 err_unroll_pools:
 512         dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
 513         for (i = i - 1; i >= 0; i--)
 514                 mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]);
 515         return err;
 516 }
 517
 518 static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv)
 519 {
 520         int i, err;
 521
 522         for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
 523                 /* Mask BM all interrupts */
 524                 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
 525                 /* Clear BM cause register */
 526                 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
 527         }
 528
 529         /* Allocate and initialize BM pools */
 530         priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM,
 531                                       sizeof(*priv->bm_pools), GFP_KERNEL);
 532         if (!priv->bm_pools)
 533                 return -ENOMEM;
 534
 535         err = mvpp2_bm_pools_init(pdev, priv);
 536         if (err < 0)
 537                 return err;
 538         return 0;
 539 }
 540
 541 static void mvpp2_setup_bm_pool(void)
 542 {
 543         /* Short pool */
 544         mvpp2_pools[MVPP2_BM_SHORT].buf_num  = MVPP2_BM_SHORT_BUF_NUM;
 545         mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE;
 546
 547         /* Long pool */
 548         mvpp2_pools[MVPP2_BM_LONG].buf_num  = MVPP2_BM_LONG_BUF_NUM;
 549         mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE;
 550
 551         /* Jumbo pool */
 552         mvpp2_pools[MVPP2_BM_JUMBO].buf_num  = MVPP2_BM_JUMBO_BUF_NUM;
 553         mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE;
 554 }
 555
 556 /* Attach long pool to rxq */
 557 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
 558                                     int lrxq, int long_pool)
 559 {
 560         u32 val, mask;
 561         int prxq;
 562
 563         /* Get queue physical ID */
 564         prxq = port->rxqs[lrxq]->id;
 565
 566         if (port->priv->hw_version == MVPP21)
 567                 mask = MVPP21_RXQ_POOL_LONG_MASK;
 568         else
 569                 mask = MVPP22_RXQ_POOL_LONG_MASK;
 570
 571         val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
 572         val &= ~mask;
 573         val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
 574         mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
 575 }
 576
 577 /* Attach short pool to rxq */
 578 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port,
 579                                      int lrxq, int short_pool)
 580 {
 581         u32 val, mask;
 582         int prxq;
 583
 584         /* Get queue physical ID */
 585         prxq = port->rxqs[lrxq]->id;
 586
 587         if (port->priv->hw_version == MVPP21)
 588                 mask = MVPP21_RXQ_POOL_SHORT_MASK;
 589         else
 590                 mask = MVPP22_RXQ_POOL_SHORT_MASK;
 591
 592         val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
 593         val &= ~mask;
 594         val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask;
 595         mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
 596 }
 597
 598 static void *mvpp2_buf_alloc(struct mvpp2_port *port,
 599                              struct mvpp2_bm_pool *bm_pool,
 600                              dma_addr_t *buf_dma_addr,
 601                              phys_addr_t *buf_phys_addr,
 602                              gfp_t gfp_mask)
 603 {
 604         dma_addr_t dma_addr;
 605         void *data;
 606
 607         data = mvpp2_frag_alloc(bm_pool);
 608         if (!data)
 609                 return NULL;
 610
 611         dma_addr = dma_map_single(port->dev->dev.parent, data,
 612                                   MVPP2_RX_BUF_SIZE(bm_pool->pkt_size),
 613                                   DMA_FROM_DEVICE);
 614         if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
 615                 mvpp2_frag_free(bm_pool, data);
 616                 return NULL;
 617         }
 618         *buf_dma_addr = dma_addr;
 619         *buf_phys_addr = virt_to_phys(data);
 620
 621         return data;
 622 }
 623
 624 /* Release buffer to BM */
 625 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
 626                                      dma_addr_t buf_dma_addr,
 627                                      phys_addr_t buf_phys_addr)
 628 {
 629         int cpu = get_cpu();
 630
 631         if (port->priv->hw_version == MVPP22) {
 632                 u32 val = 0;
 633
 634                 if (sizeof(dma_addr_t) == 8)
 635                         val |= upper_32_bits(buf_dma_addr) &
 636                                 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
 637
 638                 if (sizeof(phys_addr_t) == 8)
 639                         val |= (upper_32_bits(buf_phys_addr)
 640                                 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
 641                                 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
 642
 643                 mvpp2_percpu_write_relaxed(port->priv, cpu,
 644                                            MVPP22_BM_ADDR_HIGH_RLS_REG, val);
 645         }
 646
 647         /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
 648          * returned in the "cookie" field of the RX
 649          * descriptor. Instead of storing the virtual address, we
 650          * store the physical address
 651          */
 652         mvpp2_percpu_write_relaxed(port->priv, cpu,
 653                                    MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
 654         mvpp2_percpu_write_relaxed(port->priv, cpu,
 655                                    MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
 656
 657         put_cpu();
 658 }
 659
 660 /* Allocate buffers for the pool */
 661 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
 662                              struct mvpp2_bm_pool *bm_pool, int buf_num)
 663 {
 664         int i, buf_size, total_size;
 665         dma_addr_t dma_addr;
 666         phys_addr_t phys_addr;
 667         void *buf;
 668
 669         buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size);
 670         total_size = MVPP2_RX_TOTAL_SIZE(buf_size);
 671
 672         if (buf_num < 0 ||
 673             (buf_num + bm_pool->buf_num > bm_pool->size)) {
 674                 netdev_err(port->dev,
 675                            "cannot allocate %d buffers for pool %d\n",
 676                            buf_num, bm_pool->id);
 677                 return 0;
 678         }
 679
 680         for (i = 0; i < buf_num; i++) {
 681                 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr,
 682                                       &phys_addr, GFP_KERNEL);
 683                 if (!buf)
 684                         break;
 685
 686                 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr,
 687                                   phys_addr);
 688         }
 689
 690         /* Update BM driver with number of buffers added to pool */
 691         bm_pool->buf_num += i;
 692
 693         netdev_dbg(port->dev,
 694                    "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n",
 695                    bm_pool->id, bm_pool->pkt_size, buf_size, total_size);
 696
 697         netdev_dbg(port->dev,
 698                    "pool %d: %d of %d buffers added\n",
 699                    bm_pool->id, i, buf_num);
 700         return i;
 701 }
 702
 703 /* Notify the driver that BM pool is being used as specific type and return the
 704  * pool pointer on success
 705  */
 706 static struct mvpp2_bm_pool *
 707 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size)
 708 {
 709         struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
 710         int num;
 711
 712         if (pool >= MVPP2_BM_POOLS_NUM) {
 713                 netdev_err(port->dev, "Invalid pool %d\n", pool);
 714                 return NULL;
 715         }
 716
 717         /* Allocate buffers in case BM pool is used as long pool, but packet
 718          * size doesn't match MTU or BM pool hasn't being used yet
 719          */
 720         if (new_pool->pkt_size == 0) {
 721                 int pkts_num;
 722
 723                 /* Set default buffer number or free all the buffers in case
 724                  * the pool is not empty
 725                  */
 726                 pkts_num = new_pool->buf_num;
 727                 if (pkts_num == 0)
 728                         pkts_num = mvpp2_pools[pool].buf_num;
 729                 else
 730                         mvpp2_bm_bufs_free(port->dev->dev.parent,
 731                                            port->priv, new_pool, pkts_num);
 732
 733                 new_pool->pkt_size = pkt_size;
 734                 new_pool->frag_size =
 735                         SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
 736                         MVPP2_SKB_SHINFO_SIZE;
 737
 738                 /* Allocate buffers for this pool */
 739                 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
 740                 if (num != pkts_num) {
 741                         WARN(1, "pool %d: %d of %d allocated\n",
 742                              new_pool->id, num, pkts_num);
 743                         return NULL;
 744                 }
 745         }
 746
 747         mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
 748                                   MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
 749
 750         return new_pool;
 751 }
 752
 753 /* Initialize pools for swf */
 754 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
 755 {
 756         int rxq;
 757         enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool;
 758
 759         /* If port pkt_size is higher than 1518B:
 760          * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
 761          * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
 762          */
 763         if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
 764                 long_log_pool = MVPP2_BM_JUMBO;
 765                 short_log_pool = MVPP2_BM_LONG;
 766         } else {
 767                 long_log_pool = MVPP2_BM_LONG;
 768                 short_log_pool = MVPP2_BM_SHORT;
 769         }
 770
 771         if (!port->pool_long) {
 772                 port->pool_long =
 773                         mvpp2_bm_pool_use(port, long_log_pool,
 774                                           mvpp2_pools[long_log_pool].pkt_size);
 775                 if (!port->pool_long)
 776                         return -ENOMEM;
 777
 778                 port->pool_long->port_map |= BIT(port->id);
 779
 780                 for (rxq = 0; rxq < port->nrxqs; rxq++)
 781                         mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
 782         }
 783
 784         if (!port->pool_short) {
 785                 port->pool_short =
 786                         mvpp2_bm_pool_use(port, short_log_pool,
 787                                           mvpp2_pools[short_log_pool].pkt_size);
 788                 if (!port->pool_short)
 789                         return -ENOMEM;
 790
 791                 port->pool_short->port_map |= BIT(port->id);
 792
 793                 for (rxq = 0; rxq < port->nrxqs; rxq++)
 794                         mvpp2_rxq_short_pool_set(port, rxq,
 795                                                  port->pool_short->id);
 796         }
 797
 798         return 0;
 799 }
 800
 801 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
 802 {
 803         struct mvpp2_port *port = netdev_priv(dev);
 804         enum mvpp2_bm_pool_log_num new_long_pool;
 805         int pkt_size = MVPP2_RX_PKT_SIZE(mtu);
 806
 807         /* If port MTU is higher than 1518B:
 808          * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
 809          * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
 810          */
 811         if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
 812                 new_long_pool = MVPP2_BM_JUMBO;
 813         else
 814                 new_long_pool = MVPP2_BM_LONG;
 815
 816         if (new_long_pool != port->pool_long->id) {
 817                 /* Remove port from old short & long pool */
 818                 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id,
 819                                                     port->pool_long->pkt_size);
 820                 port->pool_long->port_map &= ~BIT(port->id);
 821                 port->pool_long = NULL;
 822
 823                 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id,
 824                                                      port->pool_short->pkt_size);
 825                 port->pool_short->port_map &= ~BIT(port->id);
 826                 port->pool_short = NULL;
 827
 828                 port->pkt_size =  pkt_size;
 829
 830                 /* Add port to new short & long pool */
 831                 mvpp2_swf_bm_pool_init(port);
 832
 833                 /* Update L4 checksum when jumbo enable/disable on port */
 834                 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
 835                         dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
 836                         dev->hw_features &= ~(NETIF_F_IP_CSUM |
 837                                               NETIF_F_IPV6_CSUM);
 838                 } else {
 839                         dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
 840                         dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
 841                 }
 842         }
 843
 844         dev->mtu = mtu;
 845         dev->wanted_features = dev->features;
 846
 847         netdev_update_features(dev);
 848         return 0;
 849 }
 850
 851 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port)
 852 {
 853         int i, sw_thread_mask = 0;
 854
 855         for (i = 0; i < port->nqvecs; i++)
 856                 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
 857
 858         mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
 859                     MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask));
 860 }
 861
 862 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port)
 863 {
 864         int i, sw_thread_mask = 0;
 865
 866         for (i = 0; i < port->nqvecs; i++)
 867                 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
 868
 869         mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
 870                     MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask));
 871 }
 872
 873 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec)
 874 {
 875         struct mvpp2_port *port = qvec->port;
 876
 877         mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
 878                     MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask));
 879 }
 880
 881 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec)
 882 {
 883         struct mvpp2_port *port = qvec->port;
 884
 885         mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
 886                     MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask));
 887 }
 888
 889 /* Mask the current CPU's Rx/Tx interrupts
 890  * Called by on_each_cpu(), guaranteed to run with migration disabled,
 891  * using smp_processor_id() is OK.
 892  */
 893 static void mvpp2_interrupts_mask(void *arg)
 894 {
 895         struct mvpp2_port *port = arg;
 896
 897         mvpp2_percpu_write(port->priv, smp_processor_id(),
 898                            MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
 899 }
 900
 901 /* Unmask the current CPU's Rx/Tx interrupts.
 902  * Called by on_each_cpu(), guaranteed to run with migration disabled,
 903  * using smp_processor_id() is OK.
 904  */
 905 static void mvpp2_interrupts_unmask(void *arg)
 906 {
 907         struct mvpp2_port *port = arg;
 908         u32 val;
 909
 910         val = MVPP2_CAUSE_MISC_SUM_MASK |
 911                 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
 912         if (port->has_tx_irqs)
 913                 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
 914
 915         mvpp2_percpu_write(port->priv, smp_processor_id(),
 916                            MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
 917 }
 918
 919 static void
 920 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
 921 {
 922         u32 val;
 923         int i;
 924
 925         if (port->priv->hw_version != MVPP22)
 926                 return;
 927
 928         if (mask)
 929                 val = 0;
 930         else
 931                 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
 932
 933         for (i = 0; i < port->nqvecs; i++) {
 934                 struct mvpp2_queue_vector *v = port->qvecs + i;
 935
 936                 if (v->type != MVPP2_QUEUE_VECTOR_SHARED)
 937                         continue;
 938
 939                 mvpp2_percpu_write(port->priv, v->sw_thread_id,
 940                                    MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
 941         }
 942 }
 943
 944 /* Port configuration routines */
 945
 946 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port)
 947 {
 948         struct mvpp2 *priv = port->priv;
 949         u32 val;
 950
 951         regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
 952         val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT;
 953         regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
 954
 955         regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
 956         if (port->gop_id == 2)
 957                 val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII;
 958         else if (port->gop_id == 3)
 959                 val |= GENCONF_CTRL0_PORT1_RGMII_MII;
 960         regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
 961 }
 962
 963 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port)
 964 {
 965         struct mvpp2 *priv = port->priv;
 966         u32 val;
 967
 968         regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
 969         val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT |
 970                GENCONF_PORT_CTRL0_RX_DATA_SAMPLE;
 971         regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
 972
 973         if (port->gop_id > 1) {
 974                 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
 975                 if (port->gop_id == 2)
 976                         val &= ~GENCONF_CTRL0_PORT0_RGMII;
 977                 else if (port->gop_id == 3)
 978                         val &= ~GENCONF_CTRL0_PORT1_RGMII_MII;
 979                 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
 980         }
 981 }
 982
 983 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port)
 984 {
 985         struct mvpp2 *priv = port->priv;
 986         void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
 987         void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
 988         u32 val;
 989
 990         /* XPCS */
 991         val = readl(xpcs + MVPP22_XPCS_CFG0);
 992         val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) |
 993                  MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3));
 994         val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2);
 995         writel(val, xpcs + MVPP22_XPCS_CFG0);
 996
 997         /* MPCS */
 998         val = readl(mpcs + MVPP22_MPCS_CTRL);
 999         val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN;
1000         writel(val, mpcs + MVPP22_MPCS_CTRL);
1001
1002         val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1003         val &= ~(MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7) | MAC_CLK_RESET_MAC |
1004                  MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX);
1005         val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1);
1006         writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1007
1008         val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET;
1009         val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX;
1010         writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1011 }
1012
1013 static int mvpp22_gop_init(struct mvpp2_port *port)
1014 {
1015         struct mvpp2 *priv = port->priv;
1016         u32 val;
1017
1018         if (!priv->sysctrl_base)
1019                 return 0;
1020
1021         switch (port->phy_interface) {
1022         case PHY_INTERFACE_MODE_RGMII:
1023         case PHY_INTERFACE_MODE_RGMII_ID:
1024         case PHY_INTERFACE_MODE_RGMII_RXID:
1025         case PHY_INTERFACE_MODE_RGMII_TXID:
1026                 if (port->gop_id == 0)
1027                         goto invalid_conf;
1028                 mvpp22_gop_init_rgmii(port);
1029                 break;
1030         case PHY_INTERFACE_MODE_SGMII:
1031         case PHY_INTERFACE_MODE_1000BASEX:
1032         case PHY_INTERFACE_MODE_2500BASEX:
1033                 mvpp22_gop_init_sgmii(port);
1034                 break;
1035         case PHY_INTERFACE_MODE_10GKR:
1036                 if (port->gop_id != 0)
1037                         goto invalid_conf;
1038                 mvpp22_gop_init_10gkr(port);
1039                 break;
1040         default:
1041                 goto unsupported_conf;
1042         }
1043
1044         regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val);
1045         val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) |
1046                GENCONF_PORT_CTRL1_EN(port->gop_id);
1047         regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val);
1048
1049         regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1050         val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR;
1051         regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1052
1053         regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val);
1054         val |= GENCONF_SOFT_RESET1_GOP;
1055         regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val);
1056
1057 unsupported_conf:
1058         return 0;
1059
1060 invalid_conf:
1061         netdev_err(port->dev, "Invalid port configuration\n");
1062         return -EINVAL;
1063 }
1064
1065 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
1066 {
1067         u32 val;
1068
1069         if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1070             port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
1071             port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
1072             port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
1073                 /* Enable the GMAC link status irq for this port */
1074                 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1075                 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1076                 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1077         }
1078
1079         if (port->gop_id == 0) {
1080                 /* Enable the XLG/GIG irqs for this port */
1081                 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1082                 if (port->phy_interface == PHY_INTERFACE_MODE_10GKR)
1083                         val |= MVPP22_XLG_EXT_INT_MASK_XLG;
1084                 else
1085                         val |= MVPP22_XLG_EXT_INT_MASK_GIG;
1086                 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1087         }
1088 }
1089
1090 static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
1091 {
1092         u32 val;
1093
1094         if (port->gop_id == 0) {
1095                 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1096                 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG |
1097                          MVPP22_XLG_EXT_INT_MASK_GIG);
1098                 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1099         }
1100
1101         if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1102             port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
1103             port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
1104             port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
1105                 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1106                 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1107                 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1108         }
1109 }
1110
1111 static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
1112 {
1113         u32 val;
1114
1115         if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1116             port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
1117             port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
1118             port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
1119                 val = readl(port->base + MVPP22_GMAC_INT_MASK);
1120                 val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
1121                 writel(val, port->base + MVPP22_GMAC_INT_MASK);
1122         }
1123
1124         if (port->gop_id == 0) {
1125                 val = readl(port->base + MVPP22_XLG_INT_MASK);
1126                 val |= MVPP22_XLG_INT_MASK_LINK;
1127                 writel(val, port->base + MVPP22_XLG_INT_MASK);
1128         }
1129
1130         mvpp22_gop_unmask_irq(port);
1131 }
1132
1133 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes).
1134  *
1135  * The PHY mode used by the PPv2 driver comes from the network subsystem, while
1136  * the one given to the COMPHY comes from the generic PHY subsystem. Hence they
1137  * differ.
1138  *
1139  * The COMPHY configures the serdes lanes regardless of the actual use of the
1140  * lanes by the physical layer. This is why configurations like
1141  * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid.
1142  */
1143 static int mvpp22_comphy_init(struct mvpp2_port *port)
1144 {
1145         enum phy_mode mode;
1146         int ret;
1147
1148         if (!port->comphy)
1149                 return 0;
1150
1151         switch (port->phy_interface) {
1152         case PHY_INTERFACE_MODE_SGMII:
1153         case PHY_INTERFACE_MODE_1000BASEX:
1154                 mode = PHY_MODE_SGMII;
1155                 break;
1156         case PHY_INTERFACE_MODE_2500BASEX:
1157                 mode = PHY_MODE_2500SGMII;
1158                 break;
1159         case PHY_INTERFACE_MODE_10GKR:
1160                 mode = PHY_MODE_10GKR;
1161                 break;
1162         default:
1163                 return -EINVAL;
1164         }
1165
1166         ret = phy_set_mode(port->comphy, mode);
1167         if (ret)
1168                 return ret;
1169
1170         return phy_power_on(port->comphy);
1171 }
1172
1173 static void mvpp2_port_enable(struct mvpp2_port *port)
1174 {
1175         u32 val;
1176
1177         /* Only GOP port 0 has an XLG MAC */
1178         if (port->gop_id == 0 &&
1179             (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
1180              port->phy_interface == PHY_INTERFACE_MODE_10GKR)) {
1181                 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1182                 val |= MVPP22_XLG_CTRL0_PORT_EN |
1183                        MVPP22_XLG_CTRL0_MAC_RESET_DIS;
1184                 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS;
1185                 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1186         } else {
1187                 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1188                 val |= MVPP2_GMAC_PORT_EN_MASK;
1189                 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
1190                 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1191         }
1192 }
1193
1194 static void mvpp2_port_disable(struct mvpp2_port *port)
1195 {
1196         u32 val;
1197
1198         /* Only GOP port 0 has an XLG MAC */
1199         if (port->gop_id == 0 &&
1200             (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
1201              port->phy_interface == PHY_INTERFACE_MODE_10GKR)) {
1202                 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1203                 val &= ~MVPP22_XLG_CTRL0_PORT_EN;
1204                 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1205
1206                 /* Disable & reset should be done separately */
1207                 val &= ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
1208                 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1209         } else {
1210                 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1211                 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
1212                 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1213         }
1214 }
1215
1216 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
1217 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
1218 {
1219         u32 val;
1220
1221         val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
1222                     ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
1223         writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1224 }
1225
1226 /* Configure loopback port */
1227 static void mvpp2_port_loopback_set(struct mvpp2_port *port,
1228                                     const struct phylink_link_state *state)
1229 {
1230         u32 val;
1231
1232         val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
1233
1234         if (state->speed == 1000)
1235                 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
1236         else
1237                 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
1238
1239         if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
1240             port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
1241             port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
1242                 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
1243         else
1244                 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
1245
1246         writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1247 }
1248
1249 struct mvpp2_ethtool_counter {
1250         unsigned int offset;
1251         const char string[ETH_GSTRING_LEN];
1252         bool reg_is_64b;
1253 };
1254
1255 static u64 mvpp2_read_count(struct mvpp2_port *port,
1256                             const struct mvpp2_ethtool_counter *counter)
1257 {
1258         u64 val;
1259
1260         val = readl(port->stats_base + counter->offset);
1261         if (counter->reg_is_64b)
1262                 val += (u64)readl(port->stats_base + counter->offset + 4) << 32;
1263
1264         return val;
1265 }
1266
1267 /* Due to the fact that software statistics and hardware statistics are, by
1268  * design, incremented at different moments in the chain of packet processing,
1269  * it is very likely that incoming packets could have been dropped after being
1270  * counted by hardware but before reaching software statistics (most probably
1271  * multicast packets), and in the oppposite way, during transmission, FCS bytes
1272  * are added in between as well as TSO skb will be split and header bytes added.
1273  * Hence, statistics gathered from userspace with ifconfig (software) and
1274  * ethtool (hardware) cannot be compared.
1275  */
1276 static const struct mvpp2_ethtool_counter mvpp2_ethtool_regs[] = {
1277         { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true },
1278         { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" },
1279         { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" },
1280         { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" },
1281         { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" },
1282         { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" },
1283         { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" },
1284         { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" },
1285         { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" },
1286         { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" },
1287         { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" },
1288         { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" },
1289         { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true },
1290         { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" },
1291         { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" },
1292         { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" },
1293         { MVPP2_MIB_FC_SENT, "fc_sent" },
1294         { MVPP2_MIB_FC_RCVD, "fc_received" },
1295         { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" },
1296         { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" },
1297         { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" },
1298         { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" },
1299         { MVPP2_MIB_JABBER_RCVD, "jabber_received" },
1300         { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" },
1301         { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" },
1302         { MVPP2_MIB_COLLISION, "collision" },
1303         { MVPP2_MIB_LATE_COLLISION, "late_collision" },
1304 };
1305
1306 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset,
1307                                       u8 *data)
1308 {
1309         if (sset == ETH_SS_STATS) {
1310                 int i;
1311
1312                 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++)
1313                         memcpy(data + i * ETH_GSTRING_LEN,
1314                                &mvpp2_ethtool_regs[i].string, ETH_GSTRING_LEN);
1315         }
1316 }
1317
1318 static void mvpp2_gather_hw_statistics(struct work_struct *work)
1319 {
1320         struct delayed_work *del_work = to_delayed_work(work);
1321         struct mvpp2_port *port = container_of(del_work, struct mvpp2_port,
1322                                                stats_work);
1323         u64 *pstats;
1324         int i;
1325
1326         mutex_lock(&port->gather_stats_lock);
1327
1328         pstats = port->ethtool_stats;
1329         for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++)
1330                 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_regs[i]);
1331
1332         /* No need to read again the counters right after this function if it
1333          * was called asynchronously by the user (ie. use of ethtool).
1334          */
1335         cancel_delayed_work(&port->stats_work);
1336         queue_delayed_work(port->priv->stats_queue, &port->stats_work,
1337                            MVPP2_MIB_COUNTERS_STATS_DELAY);
1338
1339         mutex_unlock(&port->gather_stats_lock);
1340 }
1341
1342 static void mvpp2_ethtool_get_stats(struct net_device *dev,
1343                                     struct ethtool_stats *stats, u64 *data)
1344 {
1345         struct mvpp2_port *port = netdev_priv(dev);
1346
1347         /* Update statistics for the given port, then take the lock to avoid
1348          * concurrent accesses on the ethtool_stats structure during its copy.
1349          */
1350         mvpp2_gather_hw_statistics(&port->stats_work.work);
1351
1352         mutex_lock(&port->gather_stats_lock);
1353         memcpy(data, port->ethtool_stats,
1354                sizeof(u64) * ARRAY_SIZE(mvpp2_ethtool_regs));
1355         mutex_unlock(&port->gather_stats_lock);
1356 }
1357
1358 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset)
1359 {
1360         if (sset == ETH_SS_STATS)
1361                 return ARRAY_SIZE(mvpp2_ethtool_regs);
1362
1363         return -EOPNOTSUPP;
1364 }
1365
1366 static void mvpp2_port_reset(struct mvpp2_port *port)
1367 {
1368         u32 val;
1369         unsigned int i;
1370
1371         /* Read the GOP statistics to reset the hardware counters */
1372         for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++)
1373                 mvpp2_read_count(port, &mvpp2_ethtool_regs[i]);
1374
1375         val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
1376                     ~MVPP2_GMAC_PORT_RESET_MASK;
1377         writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
1378
1379         while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
1380                MVPP2_GMAC_PORT_RESET_MASK)
1381                 continue;
1382 }
1383
1384 /* Change maximum receive size of the port */
1385 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
1386 {
1387         u32 val;
1388
1389         val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1390         val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
1391         val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
1392                     MVPP2_GMAC_MAX_RX_SIZE_OFFS);
1393         writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1394 }
1395
1396 /* Change maximum receive size of the port */
1397 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port)
1398 {
1399         u32 val;
1400
1401         val =  readl(port->base + MVPP22_XLG_CTRL1_REG);
1402         val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK;
1403         val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
1404                MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS;
1405         writel(val, port->base + MVPP22_XLG_CTRL1_REG);
1406 }
1407
1408 /* Set defaults to the MVPP2 port */
1409 static void mvpp2_defaults_set(struct mvpp2_port *port)
1410 {
1411         int tx_port_num, val, queue, ptxq, lrxq;
1412
1413         if (port->priv->hw_version == MVPP21) {
1414                 /* Update TX FIFO MIN Threshold */
1415                 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
1416                 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
1417                 /* Min. TX threshold must be less than minimal packet length */
1418                 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
1419                 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
1420         }
1421
1422         /* Disable Legacy WRR, Disable EJP, Release from reset */
1423         tx_port_num = mvpp2_egress_port(port);
1424         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
1425                     tx_port_num);
1426         mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
1427
1428         /* Close bandwidth for all queues */
1429         for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
1430                 ptxq = mvpp2_txq_phys(port->id, queue);
1431                 mvpp2_write(port->priv,
1432                             MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
1433         }
1434
1435         /* Set refill period to 1 usec, refill tokens
1436          * and bucket size to maximum
1437          */
1438         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,
1439                     port->priv->tclk / USEC_PER_SEC);
1440         val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
1441         val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
1442         val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
1443         val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
1444         mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
1445         val = MVPP2_TXP_TOKEN_SIZE_MAX;
1446         mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
1447
1448         /* Set MaximumLowLatencyPacketSize value to 256 */
1449         mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
1450                     MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
1451                     MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
1452
1453         /* Enable Rx cache snoop */
1454         for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
1455                 queue = port->rxqs[lrxq]->id;
1456                 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1457                 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
1458                            MVPP2_SNOOP_BUF_HDR_MASK;
1459                 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1460         }
1461
1462         /* At default, mask all interrupts to all present cpus */
1463         mvpp2_interrupts_disable(port);
1464 }
1465
1466 /* Enable/disable receiving packets */
1467 static void mvpp2_ingress_enable(struct mvpp2_port *port)
1468 {
1469         u32 val;
1470         int lrxq, queue;
1471
1472         for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
1473                 queue = port->rxqs[lrxq]->id;
1474                 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1475                 val &= ~MVPP2_RXQ_DISABLE_MASK;
1476                 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1477         }
1478 }
1479
1480 static void mvpp2_ingress_disable(struct mvpp2_port *port)
1481 {
1482         u32 val;
1483         int lrxq, queue;
1484
1485         for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
1486                 queue = port->rxqs[lrxq]->id;
1487                 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1488                 val |= MVPP2_RXQ_DISABLE_MASK;
1489                 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1490         }
1491 }
1492
1493 /* Enable transmit via physical egress queue
1494  * - HW starts take descriptors from DRAM
1495  */
1496 static void mvpp2_egress_enable(struct mvpp2_port *port)
1497 {
1498         u32 qmap;
1499         int queue;
1500         int tx_port_num = mvpp2_egress_port(port);
1501
1502         /* Enable all initialized TXs. */
1503         qmap = 0;
1504         for (queue = 0; queue < port->ntxqs; queue++) {
1505                 struct mvpp2_tx_queue *txq = port->txqs[queue];
1506
1507                 if (txq->descs)
1508                         qmap |= (1 << queue);
1509         }
1510
1511         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1512         mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
1513 }
1514
1515 /* Disable transmit via physical egress queue
1516  * - HW doesn't take descriptors from DRAM
1517  */
1518 static void mvpp2_egress_disable(struct mvpp2_port *port)
1519 {
1520         u32 reg_data;
1521         int delay;
1522         int tx_port_num = mvpp2_egress_port(port);
1523
1524         /* Issue stop command for active channels only */
1525         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1526         reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
1527                     MVPP2_TXP_SCHED_ENQ_MASK;
1528         if (reg_data != 0)
1529                 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
1530                             (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
1531
1532         /* Wait for all Tx activity to terminate. */
1533         delay = 0;
1534         do {
1535                 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
1536                         netdev_warn(port->dev,
1537                                     "Tx stop timed out, status=0x%08x\n",
1538                                     reg_data);
1539                         break;
1540                 }
1541                 mdelay(1);
1542                 delay++;
1543
1544                 /* Check port TX Command register that all
1545                  * Tx queues are stopped
1546                  */
1547                 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
1548         } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
1549 }
1550
1551 /* Rx descriptors helper methods */
1552
1553 /* Get number of Rx descriptors occupied by received packets */
1554 static inline int
1555 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
1556 {
1557         u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
1558
1559         return val & MVPP2_RXQ_OCCUPIED_MASK;
1560 }
1561
1562 /* Update Rx queue status with the number of occupied and available
1563  * Rx descriptor slots.
1564  */
1565 static inline void
1566 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
1567                         int used_count, int free_count)
1568 {
1569         /* Decrement the number of used descriptors and increment count
1570          * increment the number of free descriptors.
1571          */
1572         u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
1573
1574         mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
1575 }
1576
1577 /* Get pointer to next RX descriptor to be processed by SW */
1578 static inline struct mvpp2_rx_desc *
1579 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
1580 {
1581         int rx_desc = rxq->next_desc_to_proc;
1582
1583         rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
1584         prefetch(rxq->descs + rxq->next_desc_to_proc);
1585         return rxq->descs + rx_desc;
1586 }
1587
1588 /* Set rx queue offset */
1589 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
1590                                  int prxq, int offset)
1591 {
1592         u32 val;
1593
1594         /* Convert offset from bytes to units of 32 bytes */
1595         offset = offset >> 5;
1596
1597         val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
1598         val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
1599
1600         /* Offset is in */
1601         val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
1602                     MVPP2_RXQ_PACKET_OFFSET_MASK);
1603
1604         mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
1605 }
1606
1607 /* Tx descriptors helper methods */
1608
1609 /* Get pointer to next Tx descriptor to be processed (send) by HW */
1610 static struct mvpp2_tx_desc *
1611 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
1612 {
1613         int tx_desc = txq->next_desc_to_proc;
1614
1615         txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
1616         return txq->descs + tx_desc;
1617 }
1618
1619 /* Update HW with number of aggregated Tx descriptors to be sent
1620  *
1621  * Called only from mvpp2_tx(), so migration is disabled, using
1622  * smp_processor_id() is OK.
1623  */
1624 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
1625 {
1626         /* aggregated access - relevant TXQ number is written in TX desc */
1627         mvpp2_percpu_write(port->priv, smp_processor_id(),
1628                            MVPP2_AGGR_TXQ_UPDATE_REG, pending);
1629 }
1630
1631 /* Check if there are enough free descriptors in aggregated txq.
1632  * If not, update the number of occupied descriptors and repeat the check.
1633  *
1634  * Called only from mvpp2_tx(), so migration is disabled, using
1635  * smp_processor_id() is OK.
1636  */
1637 static int mvpp2_aggr_desc_num_check(struct mvpp2 *priv,
1638                                      struct mvpp2_tx_queue *aggr_txq, int num)
1639 {
1640         if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) {
1641                 /* Update number of occupied aggregated Tx descriptors */
1642                 int cpu = smp_processor_id();
1643                 u32 val = mvpp2_read_relaxed(priv,
1644                                              MVPP2_AGGR_TXQ_STATUS_REG(cpu));
1645
1646                 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK;
1647
1648                 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE)
1649                         return -ENOMEM;
1650         }
1651         return 0;
1652 }
1653
1654 /* Reserved Tx descriptors allocation request
1655  *
1656  * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called
1657  * only by mvpp2_tx(), so migration is disabled, using
1658  * smp_processor_id() is OK.
1659  */
1660 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2 *priv,
1661                                          struct mvpp2_tx_queue *txq, int num)
1662 {
1663         u32 val;
1664         int cpu = smp_processor_id();
1665
1666         val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num;
1667         mvpp2_percpu_write_relaxed(priv, cpu, MVPP2_TXQ_RSVD_REQ_REG, val);
1668
1669         val = mvpp2_percpu_read_relaxed(priv, cpu, MVPP2_TXQ_RSVD_RSLT_REG);
1670
1671         return val & MVPP2_TXQ_RSVD_RSLT_MASK;
1672 }
1673
1674 /* Check if there are enough reserved descriptors for transmission.
1675  * If not, request chunk of reserved descriptors and check again.
1676  */
1677 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2 *priv,
1678                                             struct mvpp2_tx_queue *txq,
1679                                             struct mvpp2_txq_pcpu *txq_pcpu,
1680                                             int num)
1681 {
1682         int req, cpu, desc_count;
1683
1684         if (txq_pcpu->reserved_num >= num)
1685                 return 0;
1686
1687         /* Not enough descriptors reserved! Update the reserved descriptor
1688          * count and check again.
1689          */
1690
1691         desc_count = 0;
1692         /* Compute total of used descriptors */
1693         for_each_present_cpu(cpu) {
1694                 struct mvpp2_txq_pcpu *txq_pcpu_aux;
1695
1696                 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, cpu);
1697                 desc_count += txq_pcpu_aux->count;
1698                 desc_count += txq_pcpu_aux->reserved_num;
1699         }
1700
1701         req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num);
1702         desc_count += req;
1703
1704         if (desc_count >
1705            (txq->size - (num_present_cpus() * MVPP2_CPU_DESC_CHUNK)))
1706                 return -ENOMEM;
1707
1708         txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(priv, txq, req);
1709
1710         /* OK, the descriptor could have been updated: check again. */
1711         if (txq_pcpu->reserved_num < num)
1712                 return -ENOMEM;
1713         return 0;
1714 }
1715
1716 /* Release the last allocated Tx descriptor. Useful to handle DMA
1717  * mapping failures in the Tx path.
1718  */
1719 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq)
1720 {
1721         if (txq->next_desc_to_proc == 0)
1722                 txq->next_desc_to_proc = txq->last_desc - 1;
1723         else
1724                 txq->next_desc_to_proc--;
1725 }
1726
1727 /* Set Tx descriptors fields relevant for CSUM calculation */
1728 static u32 mvpp2_txq_desc_csum(int l3_offs, int l3_proto,
1729                                int ip_hdr_len, int l4_proto)
1730 {
1731         u32 command;
1732
1733         /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1734          * G_L4_chk, L4_type required only for checksum calculation
1735          */
1736         command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT);
1737         command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT);
1738         command |= MVPP2_TXD_IP_CSUM_DISABLE;
1739
1740         if (l3_proto == htons(ETH_P_IP)) {
1741                 command &= ~MVPP2_TXD_IP_CSUM_DISABLE;  /* enable IPv4 csum */
1742                 command &= ~MVPP2_TXD_L3_IP6;           /* enable IPv4 */
1743         } else {
1744                 command |= MVPP2_TXD_L3_IP6;            /* enable IPv6 */
1745         }
1746
1747         if (l4_proto == IPPROTO_TCP) {
1748                 command &= ~MVPP2_TXD_L4_UDP;           /* enable TCP */
1749                 command &= ~MVPP2_TXD_L4_CSUM_FRAG;     /* generate L4 csum */
1750         } else if (l4_proto == IPPROTO_UDP) {
1751                 command |= MVPP2_TXD_L4_UDP;            /* enable UDP */
1752                 command &= ~MVPP2_TXD_L4_CSUM_FRAG;     /* generate L4 csum */
1753         } else {
1754                 command |= MVPP2_TXD_L4_CSUM_NOT;
1755         }
1756
1757         return command;
1758 }
1759
1760 /* Get number of sent descriptors and decrement counter.
1761  * The number of sent descriptors is returned.
1762  * Per-CPU access
1763  *
1764  * Called only from mvpp2_txq_done(), called from mvpp2_tx()
1765  * (migration disabled) and from the TX completion tasklet (migration
1766  * disabled) so using smp_processor_id() is OK.
1767  */
1768 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
1769                                            struct mvpp2_tx_queue *txq)
1770 {
1771         u32 val;
1772
1773         /* Reading status reg resets transmitted descriptor counter */
1774         val = mvpp2_percpu_read_relaxed(port->priv, smp_processor_id(),
1775                                         MVPP2_TXQ_SENT_REG(txq->id));
1776
1777         return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
1778                 MVPP2_TRANSMITTED_COUNT_OFFSET;
1779 }
1780
1781 /* Called through on_each_cpu(), so runs on all CPUs, with migration
1782  * disabled, therefore using smp_processor_id() is OK.
1783  */
1784 static void mvpp2_txq_sent_counter_clear(void *arg)
1785 {
1786         struct mvpp2_port *port = arg;
1787         int queue;
1788
1789         for (queue = 0; queue < port->ntxqs; queue++) {
1790                 int id = port->txqs[queue]->id;
1791
1792                 mvpp2_percpu_read(port->priv, smp_processor_id(),
1793                                   MVPP2_TXQ_SENT_REG(id));
1794         }
1795 }
1796
1797 /* Set max sizes for Tx queues */
1798 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
1799 {
1800         u32     val, size, mtu;
1801         int     txq, tx_port_num;
1802
1803         mtu = port->pkt_size * 8;
1804         if (mtu > MVPP2_TXP_MTU_MAX)
1805                 mtu = MVPP2_TXP_MTU_MAX;
1806
1807         /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
1808         mtu = 3 * mtu;
1809
1810         /* Indirect access to registers */
1811         tx_port_num = mvpp2_egress_port(port);
1812         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1813
1814         /* Set MTU */
1815         val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
1816         val &= ~MVPP2_TXP_MTU_MAX;
1817         val |= mtu;
1818         mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
1819
1820         /* TXP token size and all TXQs token size must be larger that MTU */
1821         val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
1822         size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
1823         if (size < mtu) {
1824                 size = mtu;
1825                 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
1826                 val |= size;
1827                 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
1828         }
1829
1830         for (txq = 0; txq < port->ntxqs; txq++) {
1831                 val = mvpp2_read(port->priv,
1832                                  MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
1833                 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
1834
1835                 if (size < mtu) {
1836                         size = mtu;
1837                         val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
1838                         val |= size;
1839                         mvpp2_write(port->priv,
1840                                     MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
1841                                     val);
1842                 }
1843         }
1844 }
1845
1846 /* Set the number of packets that will be received before Rx interrupt
1847  * will be generated by HW.
1848  */
1849 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
1850                                    struct mvpp2_rx_queue *rxq)
1851 {
1852         int cpu = get_cpu();
1853
1854         if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)
1855                 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;
1856
1857         mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);
1858         mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_THRESH_REG,
1859                            rxq->pkts_coal);
1860
1861         put_cpu();
1862 }
1863
1864 /* For some reason in the LSP this is done on each CPU. Why ? */
1865 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port,
1866                                    struct mvpp2_tx_queue *txq)
1867 {
1868         int cpu = get_cpu();
1869         u32 val;
1870
1871         if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK)
1872                 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK;
1873
1874         val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET);
1875         mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);
1876         mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_THRESH_REG, val);
1877
1878         put_cpu();
1879 }
1880
1881 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
1882 {
1883         u64 tmp = (u64)clk_hz * usec;
1884
1885         do_div(tmp, USEC_PER_SEC);
1886
1887         return tmp > U32_MAX ? U32_MAX : tmp;
1888 }
1889
1890 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz)
1891 {
1892         u64 tmp = (u64)cycles * USEC_PER_SEC;
1893
1894         do_div(tmp, clk_hz);
1895
1896         return tmp > U32_MAX ? U32_MAX : tmp;
1897 }
1898
1899 /* Set the time delay in usec before Rx interrupt */
1900 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port,
1901                                    struct mvpp2_rx_queue *rxq)
1902 {
1903         unsigned long freq = port->priv->tclk;
1904         u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
1905
1906         if (val > MVPP2_MAX_ISR_RX_THRESHOLD) {
1907                 rxq->time_coal =
1908                         mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq);
1909
1910                 /* re-evaluate to get actual register value */
1911                 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
1912         }
1913
1914         mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
1915 }
1916
1917 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port)
1918 {
1919         unsigned long freq = port->priv->tclk;
1920         u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
1921
1922         if (val > MVPP2_MAX_ISR_TX_THRESHOLD) {
1923                 port->tx_time_coal =
1924                         mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq);
1925
1926                 /* re-evaluate to get actual register value */
1927                 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
1928         }
1929
1930         mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val);
1931 }
1932
1933 /* Free Tx queue skbuffs */
1934 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
1935                                 struct mvpp2_tx_queue *txq,
1936                                 struct mvpp2_txq_pcpu *txq_pcpu, int num)
1937 {
1938         int i;
1939
1940         for (i = 0; i < num; i++) {
1941                 struct mvpp2_txq_pcpu_buf *tx_buf =
1942                         txq_pcpu->buffs + txq_pcpu->txq_get_index;
1943
1944                 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma))
1945                         dma_unmap_single(port->dev->dev.parent, tx_buf->dma,
1946                                          tx_buf->size, DMA_TO_DEVICE);
1947                 if (tx_buf->skb)
1948                         dev_kfree_skb_any(tx_buf->skb);
1949
1950                 mvpp2_txq_inc_get(txq_pcpu);
1951         }
1952 }
1953
1954 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
1955                                                         u32 cause)
1956 {
1957         int queue = fls(cause) - 1;
1958
1959         return port->rxqs[queue];
1960 }
1961
1962 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
1963                                                         u32 cause)
1964 {
1965         int queue = fls(cause) - 1;
1966
1967         return port->txqs[queue];
1968 }
1969
1970 /* Handle end of transmission */
1971 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
1972                            struct mvpp2_txq_pcpu *txq_pcpu)
1973 {
1974         struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id);
1975         int tx_done;
1976
1977         if (txq_pcpu->cpu != smp_processor_id())
1978                 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n");
1979
1980         tx_done = mvpp2_txq_sent_desc_proc(port, txq);
1981         if (!tx_done)
1982                 return;
1983         mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done);
1984
1985         txq_pcpu->count -= tx_done;
1986
1987         if (netif_tx_queue_stopped(nq))
1988                 if (txq_pcpu->count <= txq_pcpu->wake_threshold)
1989                         netif_tx_wake_queue(nq);
1990 }
1991
1992 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause,
1993                                   int cpu)
1994 {
1995         struct mvpp2_tx_queue *txq;
1996         struct mvpp2_txq_pcpu *txq_pcpu;
1997         unsigned int tx_todo = 0;
1998
1999         while (cause) {
2000                 txq = mvpp2_get_tx_queue(port, cause);
2001                 if (!txq)
2002                         break;
2003
2004                 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
2005
2006                 if (txq_pcpu->count) {
2007                         mvpp2_txq_done(port, txq, txq_pcpu);
2008                         tx_todo += txq_pcpu->count;
2009                 }
2010
2011                 cause &= ~(1 << txq->log_id);
2012         }
2013         return tx_todo;
2014 }
2015
2016 /* Rx/Tx queue initialization/cleanup methods */
2017
2018 /* Allocate and initialize descriptors for aggr TXQ */
2019 static int mvpp2_aggr_txq_init(struct platform_device *pdev,
2020                                struct mvpp2_tx_queue *aggr_txq, int cpu,
2021                                struct mvpp2 *priv)
2022 {
2023         u32 txq_dma;
2024
2025         /* Allocate memory for TX descriptors */
2026         aggr_txq->descs = dma_zalloc_coherent(&pdev->dev,
2027                                 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
2028                                 &aggr_txq->descs_dma, GFP_KERNEL);
2029         if (!aggr_txq->descs)
2030                 return -ENOMEM;
2031
2032         aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1;
2033
2034         /* Aggr TXQ no reset WA */
2035         aggr_txq->next_desc_to_proc = mvpp2_read(priv,
2036                                                  MVPP2_AGGR_TXQ_INDEX_REG(cpu));
2037
2038         /* Set Tx descriptors queue starting address indirect
2039          * access
2040          */
2041         if (priv->hw_version == MVPP21)
2042                 txq_dma = aggr_txq->descs_dma;
2043         else
2044                 txq_dma = aggr_txq->descs_dma >>
2045                         MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
2046
2047         mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
2048         mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu),
2049                     MVPP2_AGGR_TXQ_SIZE);
2050
2051         return 0;
2052 }
2053
2054 /* Create a specified Rx queue */
2055 static int mvpp2_rxq_init(struct mvpp2_port *port,
2056                           struct mvpp2_rx_queue *rxq)
2057
2058 {
2059         u32 rxq_dma;
2060         int cpu;
2061
2062         rxq->size = port->rx_ring_size;
2063
2064         /* Allocate memory for RX descriptors */
2065         rxq->descs = dma_alloc_coherent(port->dev->dev.parent,
2066                                         rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2067                                         &rxq->descs_dma, GFP_KERNEL);
2068         if (!rxq->descs)
2069                 return -ENOMEM;
2070
2071         rxq->last_desc = rxq->size - 1;
2072
2073         /* Zero occupied and non-occupied counters - direct access */
2074         mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2075
2076         /* Set Rx descriptors queue starting address - indirect access */
2077         cpu = get_cpu();
2078         mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);
2079         if (port->priv->hw_version == MVPP21)
2080                 rxq_dma = rxq->descs_dma;
2081         else
2082                 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
2083         mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
2084         mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
2085         mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_INDEX_REG, 0);
2086         put_cpu();
2087
2088         /* Set Offset */
2089         mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
2090
2091         /* Set coalescing pkts and time */
2092         mvpp2_rx_pkts_coal_set(port, rxq);
2093         mvpp2_rx_time_coal_set(port, rxq);
2094
2095         /* Add number of descriptors ready for receiving packets */
2096         mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
2097
2098         return 0;
2099 }
2100
2101 /* Push packets received by the RXQ to BM pool */
2102 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
2103                                 struct mvpp2_rx_queue *rxq)
2104 {
2105         int rx_received, i;
2106
2107         rx_received = mvpp2_rxq_received(port, rxq->id);
2108         if (!rx_received)
2109                 return;
2110
2111         for (i = 0; i < rx_received; i++) {
2112                 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
2113                 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
2114                 int pool;
2115
2116                 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >>
2117                         MVPP2_RXD_BM_POOL_ID_OFFS;
2118
2119                 mvpp2_bm_pool_put(port, pool,
2120                                   mvpp2_rxdesc_dma_addr_get(port, rx_desc),
2121                                   mvpp2_rxdesc_cookie_get(port, rx_desc));
2122         }
2123         mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
2124 }
2125
2126 /* Cleanup Rx queue */
2127 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
2128                              struct mvpp2_rx_queue *rxq)
2129 {
2130         int cpu;
2131
2132         mvpp2_rxq_drop_pkts(port, rxq);
2133
2134         if (rxq->descs)
2135                 dma_free_coherent(port->dev->dev.parent,
2136                                   rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2137                                   rxq->descs,
2138                                   rxq->descs_dma);
2139
2140         rxq->descs             = NULL;
2141         rxq->last_desc         = 0;
2142         rxq->next_desc_to_proc = 0;
2143         rxq->descs_dma         = 0;
2144
2145         /* Clear Rx descriptors queue starting address and size;
2146          * free descriptor number
2147          */
2148         mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2149         cpu = get_cpu();
2150         mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);
2151         mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, 0);
2152         mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, 0);
2153         put_cpu();
2154 }
2155
2156 /* Create and initialize a Tx queue */
2157 static int mvpp2_txq_init(struct mvpp2_port *port,
2158                           struct mvpp2_tx_queue *txq)
2159 {
2160         u32 val;
2161         int cpu, desc, desc_per_txq, tx_port_num;
2162         struct mvpp2_txq_pcpu *txq_pcpu;
2163
2164         txq->size = port->tx_ring_size;
2165
2166         /* Allocate memory for Tx descriptors */
2167         txq->descs = dma_alloc_coherent(port->dev->dev.parent,
2168                                 txq->size * MVPP2_DESC_ALIGNED_SIZE,
2169                                 &txq->descs_dma, GFP_KERNEL);
2170         if (!txq->descs)
2171                 return -ENOMEM;
2172
2173         txq->last_desc = txq->size - 1;
2174
2175         /* Set Tx descriptors queue starting address - indirect access */
2176         cpu = get_cpu();
2177         mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);
2178         mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG,
2179                            txq->descs_dma);
2180         mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG,
2181                            txq->size & MVPP2_TXQ_DESC_SIZE_MASK);
2182         mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_INDEX_REG, 0);
2183         mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_RSVD_CLR_REG,
2184                            txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
2185         val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PENDING_REG);
2186         val &= ~MVPP2_TXQ_PENDING_MASK;
2187         mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PENDING_REG, val);
2188
2189         /* Calculate base address in prefetch buffer. We reserve 16 descriptors
2190          * for each existing TXQ.
2191          * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
2192          * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS
2193          */
2194         desc_per_txq = 16;
2195         desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
2196                (txq->log_id * desc_per_txq);
2197
2198         mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG,
2199                            MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
2200                            MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
2201         put_cpu();
2202
2203         /* WRR / EJP configuration - indirect access */
2204         tx_port_num = mvpp2_egress_port(port);
2205         mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2206
2207         val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
2208         val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
2209         val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
2210         val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
2211         mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
2212
2213         val = MVPP2_TXQ_TOKEN_SIZE_MAX;
2214         mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
2215                     val);
2216
2217         for_each_present_cpu(cpu) {
2218                 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
2219                 txq_pcpu->size = txq->size;
2220                 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size,
2221                                                 sizeof(*txq_pcpu->buffs),
2222                                                 GFP_KERNEL);
2223                 if (!txq_pcpu->buffs)
2224                         return -ENOMEM;
2225
2226                 txq_pcpu->count = 0;
2227                 txq_pcpu->reserved_num = 0;
2228                 txq_pcpu->txq_put_index = 0;
2229                 txq_pcpu->txq_get_index = 0;
2230                 txq_pcpu->tso_headers = NULL;
2231
2232                 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS;
2233                 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2;
2234
2235                 txq_pcpu->tso_headers =
2236                         dma_alloc_coherent(port->dev->dev.parent,
2237                                            txq_pcpu->size * TSO_HEADER_SIZE,
2238                                            &txq_pcpu->tso_headers_dma,
2239                                            GFP_KERNEL);
2240                 if (!txq_pcpu->tso_headers)
2241                         return -ENOMEM;
2242         }
2243
2244         return 0;
2245 }
2246
2247 /* Free allocated TXQ resources */
2248 static void mvpp2_txq_deinit(struct mvpp2_port *port,
2249                              struct mvpp2_tx_queue *txq)
2250 {
2251         struct mvpp2_txq_pcpu *txq_pcpu;
2252         int cpu;
2253
2254         for_each_present_cpu(cpu) {
2255                 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
2256                 kfree(txq_pcpu->buffs);
2257
2258                 if (txq_pcpu->tso_headers)
2259                         dma_free_coherent(port->dev->dev.parent,
2260                                           txq_pcpu->size * TSO_HEADER_SIZE,
2261                                           txq_pcpu->tso_headers,
2262                                           txq_pcpu->tso_headers_dma);
2263
2264                 txq_pcpu->tso_headers = NULL;
2265         }
2266
2267         if (txq->descs)
2268                 dma_free_coherent(port->dev->dev.parent,
2269                                   txq->size * MVPP2_DESC_ALIGNED_SIZE,
2270                                   txq->descs, txq->descs_dma);
2271
2272         txq->descs             = NULL;
2273         txq->last_desc         = 0;
2274         txq->next_desc_to_proc = 0;
2275         txq->descs_dma         = 0;
2276
2277         /* Set minimum bandwidth for disabled TXQs */
2278         mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
2279
2280         /* Set Tx descriptors queue starting address and size */
2281         cpu = get_cpu();
2282         mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);
2283         mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG, 0);
2284         mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG, 0);
2285         put_cpu();
2286 }
2287
2288 /* Cleanup Tx ports */
2289 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
2290 {
2291         struct mvpp2_txq_pcpu *txq_pcpu;
2292         int delay, pending, cpu;
2293         u32 val;
2294
2295         cpu = get_cpu();
2296         mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);
2297         val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG);
2298         val |= MVPP2_TXQ_DRAIN_EN_MASK;
2299         mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val);
2300
2301         /* The napi queue has been stopped so wait for all packets
2302          * to be transmitted.
2303          */
2304         delay = 0;
2305         do {
2306                 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
2307                         netdev_warn(port->dev,
2308                                     "port %d: cleaning queue %d timed out\n",
2309                                     port->id, txq->log_id);
2310                         break;
2311                 }
2312                 mdelay(1);
2313                 delay++;
2314
2315                 pending = mvpp2_percpu_read(port->priv, cpu,
2316                                             MVPP2_TXQ_PENDING_REG);
2317                 pending &= MVPP2_TXQ_PENDING_MASK;
2318         } while (pending);
2319
2320         val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
2321         mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val);
2322         put_cpu();
2323
2324         for_each_present_cpu(cpu) {
2325                 txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
2326
2327                 /* Release all packets */
2328                 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
2329
2330                 /* Reset queue */
2331                 txq_pcpu->count = 0;
2332                 txq_pcpu->txq_put_index = 0;
2333                 txq_pcpu->txq_get_index = 0;
2334         }
2335 }
2336
2337 /* Cleanup all Tx queues */
2338 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
2339 {
2340         struct mvpp2_tx_queue *txq;
2341         int queue;
2342         u32 val;
2343
2344         val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
2345
2346         /* Reset Tx ports and delete Tx queues */
2347         val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
2348         mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
2349
2350         for (queue = 0; queue < port->ntxqs; queue++) {
2351                 txq = port->txqs[queue];
2352                 mvpp2_txq_clean(port, txq);
2353                 mvpp2_txq_deinit(port, txq);
2354         }
2355
2356         on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
2357
2358         val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
2359         mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
2360 }
2361
2362 /* Cleanup all Rx queues */
2363 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
2364 {
2365         int queue;
2366
2367         for (queue = 0; queue < port->nrxqs; queue++)
2368                 mvpp2_rxq_deinit(port, port->rxqs[queue]);
2369 }
2370
2371 /* Init all Rx queues for port */
2372 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
2373 {
2374         int queue, err;
2375
2376         for (queue = 0; queue < port->nrxqs; queue++) {
2377                 err = mvpp2_rxq_init(port, port->rxqs[queue]);
2378                 if (err)
2379                         goto err_cleanup;
2380         }
2381         return 0;
2382
2383 err_cleanup:
2384         mvpp2_cleanup_rxqs(port);
2385         return err;
2386 }
2387
2388 /* Init all tx queues for port */
2389 static int mvpp2_setup_txqs(struct mvpp2_port *port)
2390 {
2391         struct mvpp2_tx_queue *txq;
2392         int queue, err;
2393
2394         for (queue = 0; queue < port->ntxqs; queue++) {
2395                 txq = port->txqs[queue];
2396                 err = mvpp2_txq_init(port, txq);
2397                 if (err)
2398                         goto err_cleanup;
2399         }
2400
2401         if (port->has_tx_irqs) {
2402                 mvpp2_tx_time_coal_set(port);
2403                 for (queue = 0; queue < port->ntxqs; queue++) {
2404                         txq = port->txqs[queue];
2405                         mvpp2_tx_pkts_coal_set(port, txq);
2406                 }
2407         }
2408
2409         on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
2410         return 0;
2411
2412 err_cleanup:
2413         mvpp2_cleanup_txqs(port);
2414         return err;
2415 }
2416
2417 /* The callback for per-port interrupt */
2418 static irqreturn_t mvpp2_isr(int irq, void *dev_id)
2419 {
2420         struct mvpp2_queue_vector *qv = dev_id;
2421
2422         mvpp2_qvec_interrupt_disable(qv);
2423
2424         napi_schedule(&qv->napi);
2425
2426         return IRQ_HANDLED;
2427 }
2428
2429 /* Per-port interrupt for link status changes */
2430 static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
2431 {
2432         struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
2433         struct net_device *dev = port->dev;
2434         bool event = false, link = false;
2435         u32 val;
2436
2437         mvpp22_gop_mask_irq(port);
2438
2439         if (port->gop_id == 0 &&
2440             port->phy_interface == PHY_INTERFACE_MODE_10GKR) {
2441                 val = readl(port->base + MVPP22_XLG_INT_STAT);
2442                 if (val & MVPP22_XLG_INT_STAT_LINK) {
2443                         event = true;
2444                         val = readl(port->base + MVPP22_XLG_STATUS);
2445                         if (val & MVPP22_XLG_STATUS_LINK_UP)
2446                                 link = true;
2447                 }
2448         } else if (phy_interface_mode_is_rgmii(port->phy_interface) ||
2449                    port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
2450                    port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
2451                    port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
2452                 val = readl(port->base + MVPP22_GMAC_INT_STAT);
2453                 if (val & MVPP22_GMAC_INT_STAT_LINK) {
2454                         event = true;
2455                         val = readl(port->base + MVPP2_GMAC_STATUS0);
2456                         if (val & MVPP2_GMAC_STATUS0_LINK_UP)
2457                                 link = true;
2458                 }
2459         }
2460
2461         if (port->phylink) {
2462                 phylink_mac_change(port->phylink, link);
2463                 goto handled;
2464         }
2465
2466         if (!netif_running(dev) || !event)
2467                 goto handled;
2468
2469         if (link) {
2470                 mvpp2_interrupts_enable(port);
2471
2472                 mvpp2_egress_enable(port);
2473                 mvpp2_ingress_enable(port);
2474                 netif_carrier_on(dev);
2475                 netif_tx_wake_all_queues(dev);
2476         } else {
2477                 netif_tx_stop_all_queues(dev);
2478                 netif_carrier_off(dev);
2479                 mvpp2_ingress_disable(port);
2480                 mvpp2_egress_disable(port);
2481
2482                 mvpp2_interrupts_disable(port);
2483         }
2484
2485 handled:
2486         mvpp22_gop_unmask_irq(port);
2487         return IRQ_HANDLED;
2488 }
2489
2490 static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu)
2491 {
2492         ktime_t interval;
2493
2494         if (!port_pcpu->timer_scheduled) {
2495                 port_pcpu->timer_scheduled = true;
2496                 interval = MVPP2_TXDONE_HRTIMER_PERIOD_NS;
2497                 hrtimer_start(&port_pcpu->tx_done_timer, interval,
2498                               HRTIMER_MODE_REL_PINNED);
2499         }
2500 }
2501
2502 static void mvpp2_tx_proc_cb(unsigned long data)
2503 {
2504         struct net_device *dev = (struct net_device *)data;
2505         struct mvpp2_port *port = netdev_priv(dev);
2506         struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu);
2507         unsigned int tx_todo, cause;
2508
2509         if (!netif_running(dev))
2510                 return;
2511         port_pcpu->timer_scheduled = false;
2512
2513         /* Process all the Tx queues */
2514         cause = (1 << port->ntxqs) - 1;
2515         tx_todo = mvpp2_tx_done(port, cause, smp_processor_id());
2516
2517         /* Set the timer in case not all the packets were processed */
2518         if (tx_todo)
2519                 mvpp2_timer_set(port_pcpu);
2520 }
2521
2522 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer)
2523 {
2524         struct mvpp2_port_pcpu *port_pcpu = container_of(timer,
2525                                                          struct mvpp2_port_pcpu,
2526                                                          tx_done_timer);
2527
2528         tasklet_schedule(&port_pcpu->tx_done_tasklet);
2529
2530         return HRTIMER_NORESTART;
2531 }
2532
2533 /* Main RX/TX processing routines */
2534
2535 /* Display more error info */
2536 static void mvpp2_rx_error(struct mvpp2_port *port,
2537                            struct mvpp2_rx_desc *rx_desc)
2538 {
2539         u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
2540         size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
2541         char *err_str = NULL;
2542
2543         switch (status & MVPP2_RXD_ERR_CODE_MASK) {
2544         case MVPP2_RXD_ERR_CRC:
2545                 err_str = "crc";
2546                 break;
2547         case MVPP2_RXD_ERR_OVERRUN:
2548                 err_str = "overrun";
2549                 break;
2550         case MVPP2_RXD_ERR_RESOURCE:
2551                 err_str = "resource";
2552                 break;
2553         }
2554         if (err_str && net_ratelimit())
2555                 netdev_err(port->dev,
2556                            "bad rx status %08x (%s error), size=%zu\n",
2557                            status, err_str, sz);
2558 }
2559
2560 /* Handle RX checksum offload */
2561 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status,
2562                           struct sk_buff *skb)
2563 {
2564         if (((status & MVPP2_RXD_L3_IP4) &&
2565              !(status & MVPP2_RXD_IP4_HEADER_ERR)) ||
2566             (status & MVPP2_RXD_L3_IP6))
2567                 if (((status & MVPP2_RXD_L4_UDP) ||
2568                      (status & MVPP2_RXD_L4_TCP)) &&
2569                      (status & MVPP2_RXD_L4_CSUM_OK)) {
2570                         skb->csum = 0;
2571                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2572                         return;
2573                 }
2574
2575         skb->ip_summed = CHECKSUM_NONE;
2576 }
2577
2578 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
2579 static int mvpp2_rx_refill(struct mvpp2_port *port,
2580                            struct mvpp2_bm_pool *bm_pool, int pool)
2581 {
2582         dma_addr_t dma_addr;
2583         phys_addr_t phys_addr;
2584         void *buf;
2585
2586         /* No recycle or too many buffers are in use, so allocate a new skb */
2587         buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr,
2588                               GFP_ATOMIC);
2589         if (!buf)
2590                 return -ENOMEM;
2591
2592         mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
2593
2594         return 0;
2595 }
2596
2597 /* Handle tx checksum */
2598 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb)
2599 {
2600         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2601                 int ip_hdr_len = 0;
2602                 u8 l4_proto;
2603
2604                 if (skb->protocol == htons(ETH_P_IP)) {
2605                         struct iphdr *ip4h = ip_hdr(skb);
2606
2607                         /* Calculate IPv4 checksum and L4 checksum */
2608                         ip_hdr_len = ip4h->ihl;
2609                         l4_proto = ip4h->protocol;
2610                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2611                         struct ipv6hdr *ip6h = ipv6_hdr(skb);
2612
2613                         /* Read l4_protocol from one of IPv6 extra headers */
2614                         if (skb_network_header_len(skb) > 0)
2615                                 ip_hdr_len = (skb_network_header_len(skb) >> 2);
2616                         l4_proto = ip6h->nexthdr;
2617                 } else {
2618                         return MVPP2_TXD_L4_CSUM_NOT;
2619                 }
2620
2621                 return mvpp2_txq_desc_csum(skb_network_offset(skb),
2622                                 skb->protocol, ip_hdr_len, l4_proto);
2623         }
2624
2625         return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE;
2626 }
2627
2628 /* Main rx processing */
2629 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi,
2630                     int rx_todo, struct mvpp2_rx_queue *rxq)
2631 {
2632         struct net_device *dev = port->dev;
2633         int rx_received;
2634         int rx_done = 0;
2635         u32 rcvd_pkts = 0;
2636         u32 rcvd_bytes = 0;
2637
2638         /* Get number of received packets and clamp the to-do */
2639         rx_received = mvpp2_rxq_received(port, rxq->id);
2640         if (rx_todo > rx_received)
2641                 rx_todo = rx_received;
2642
2643         while (rx_done < rx_todo) {
2644                 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
2645                 struct mvpp2_bm_pool *bm_pool;
2646                 struct sk_buff *skb;
2647                 unsigned int frag_size;
2648                 dma_addr_t dma_addr;
2649                 phys_addr_t phys_addr;
2650                 u32 rx_status;
2651                 int pool, rx_bytes, err;
2652                 void *data;
2653
2654                 rx_done++;
2655                 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
2656                 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
2657                 rx_bytes -= MVPP2_MH_SIZE;
2658                 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
2659                 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
2660                 data = (void *)phys_to_virt(phys_addr);
2661
2662                 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>
2663                         MVPP2_RXD_BM_POOL_ID_OFFS;
2664                 bm_pool = &port->priv->bm_pools[pool];
2665
2666                 /* In case of an error, release the requested buffer pointer
2667                  * to the Buffer Manager. This request process is controlled
2668                  * by the hardware, and the information about the buffer is
2669                  * comprised by the RX descriptor.
2670                  */
2671                 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
2672 err_drop_frame:
2673                         dev->stats.rx_errors++;
2674                         mvpp2_rx_error(port, rx_desc);
2675                         /* Return the buffer to the pool */
2676                         mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
2677                         continue;
2678                 }
2679
2680                 if (bm_pool->frag_size > PAGE_SIZE)
2681                         frag_size = 0;
2682                 else
2683                         frag_size = bm_pool->frag_size;
2684
2685                 skb = build_skb(data, frag_size);
2686                 if (!skb) {
2687                         netdev_warn(port->dev, "skb build failed\n");
2688                         goto err_drop_frame;
2689                 }
2690
2691                 err = mvpp2_rx_refill(port, bm_pool, pool);
2692                 if (err) {
2693                         netdev_err(port->dev, "failed to refill BM pools\n");
2694                         goto err_drop_frame;
2695                 }
2696
2697                 dma_unmap_single(dev->dev.parent, dma_addr,
2698                                  bm_pool->buf_size, DMA_FROM_DEVICE);
2699
2700                 rcvd_pkts++;
2701                 rcvd_bytes += rx_bytes;
2702
2703                 skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD);
2704                 skb_put(skb, rx_bytes);
2705                 skb->protocol = eth_type_trans(skb, dev);
2706                 mvpp2_rx_csum(port, rx_status, skb);
2707
2708                 napi_gro_receive(napi, skb);
2709         }
2710
2711         if (rcvd_pkts) {
2712                 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
2713
2714                 u64_stats_update_begin(&stats->syncp);
2715                 stats->rx_packets += rcvd_pkts;
2716                 stats->rx_bytes   += rcvd_bytes;
2717                 u64_stats_update_end(&stats->syncp);
2718         }
2719
2720         /* Update Rx queue management counters */
2721         wmb();
2722         mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done);
2723
2724         return rx_todo;
2725 }
2726
2727 static inline void
2728 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
2729                   struct mvpp2_tx_desc *desc)
2730 {
2731         struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu);
2732
2733         dma_addr_t buf_dma_addr =
2734                 mvpp2_txdesc_dma_addr_get(port, desc);
2735         size_t buf_sz =
2736                 mvpp2_txdesc_size_get(port, desc);
2737         if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr))
2738                 dma_unmap_single(port->dev->dev.parent, buf_dma_addr,
2739                                  buf_sz, DMA_TO_DEVICE);
2740         mvpp2_txq_desc_put(txq);
2741 }
2742
2743 /* Handle tx fragmentation processing */
2744 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
2745                                  struct mvpp2_tx_queue *aggr_txq,
2746                                  struct mvpp2_tx_queue *txq)
2747 {
2748         struct mvpp2_txq_pcpu *txq_pcpu = this_cpu_ptr(txq->pcpu);
2749         struct mvpp2_tx_desc *tx_desc;
2750         int i;
2751         dma_addr_t buf_dma_addr;
2752
2753         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2754                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2755                 void *addr = page_address(frag->page.p) + frag->page_offset;
2756
2757                 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2758                 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2759                 mvpp2_txdesc_size_set(port, tx_desc, frag->size);
2760
2761                 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr,
2762                                               frag->size, DMA_TO_DEVICE);
2763                 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) {
2764                         mvpp2_txq_desc_put(txq);
2765                         goto cleanup;
2766                 }
2767
2768                 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
2769
2770                 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
2771                         /* Last descriptor */
2772                         mvpp2_txdesc_cmd_set(port, tx_desc,
2773                                              MVPP2_TXD_L_DESC);
2774                         mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
2775                 } else {
2776                         /* Descriptor in the middle: Not First, Not Last */
2777                         mvpp2_txdesc_cmd_set(port, tx_desc, 0);
2778                         mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
2779                 }
2780         }
2781
2782         return 0;
2783 cleanup:
2784         /* Release all descriptors that were used to map fragments of
2785          * this packet, as well as the corresponding DMA mappings
2786          */
2787         for (i = i - 1; i >= 0; i--) {
2788                 tx_desc = txq->descs + i;
2789                 tx_desc_unmap_put(port, txq, tx_desc);
2790         }
2791
2792         return -ENOMEM;
2793 }
2794
2795 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb,
2796                                      struct net_device *dev,
2797                                      struct mvpp2_tx_queue *txq,
2798                                      struct mvpp2_tx_queue *aggr_txq,
2799                                      struct mvpp2_txq_pcpu *txq_pcpu,
2800                                      int hdr_sz)
2801 {
2802         struct mvpp2_port *port = netdev_priv(dev);
2803         struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2804         dma_addr_t addr;
2805
2806         mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2807         mvpp2_txdesc_size_set(port, tx_desc, hdr_sz);
2808
2809         addr = txq_pcpu->tso_headers_dma +
2810                txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
2811         mvpp2_txdesc_dma_addr_set(port, tx_desc, addr);
2812
2813         mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) |
2814                                             MVPP2_TXD_F_DESC |
2815                                             MVPP2_TXD_PADDING_DISABLE);
2816         mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
2817 }
2818
2819 static inline int mvpp2_tso_put_data(struct sk_buff *skb,
2820                                      struct net_device *dev, struct tso_t *tso,
2821                                      struct mvpp2_tx_queue *txq,
2822                                      struct mvpp2_tx_queue *aggr_txq,
2823                                      struct mvpp2_txq_pcpu *txq_pcpu,
2824                                      int sz, bool left, bool last)
2825 {
2826         struct mvpp2_port *port = netdev_priv(dev);
2827         struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2828         dma_addr_t buf_dma_addr;
2829
2830         mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2831         mvpp2_txdesc_size_set(port, tx_desc, sz);
2832
2833         buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz,
2834                                       DMA_TO_DEVICE);
2835         if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
2836                 mvpp2_txq_desc_put(txq);
2837                 return -ENOMEM;
2838         }
2839
2840         mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
2841
2842         if (!left) {
2843                 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC);
2844                 if (last) {
2845                         mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
2846                         return 0;
2847                 }
2848         } else {
2849                 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
2850         }
2851
2852         mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
2853         return 0;
2854 }
2855
2856 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev,
2857                         struct mvpp2_tx_queue *txq,
2858                         struct mvpp2_tx_queue *aggr_txq,
2859                         struct mvpp2_txq_pcpu *txq_pcpu)
2860 {
2861         struct mvpp2_port *port = netdev_priv(dev);
2862         struct tso_t tso;
2863         int hdr_sz = skb_transport_offset(skb) + tcp_hdrlen(skb);
2864         int i, len, descs = 0;
2865
2866         /* Check number of available descriptors */
2867         if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq,
2868                                       tso_count_descs(skb)) ||
2869             mvpp2_txq_reserved_desc_num_proc(port->priv, txq, txq_pcpu,
2870                                              tso_count_descs(skb)))
2871                 return 0;
2872
2873         tso_start(skb, &tso);
2874         len = skb->len - hdr_sz;
2875         while (len > 0) {
2876                 int left = min_t(int, skb_shinfo(skb)->gso_size, len);
2877                 char *hdr = txq_pcpu->tso_headers +
2878                             txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
2879
2880                 len -= left;
2881                 descs++;
2882
2883                 tso_build_hdr(skb, hdr, &tso, left, len == 0);
2884                 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz);
2885
2886                 while (left > 0) {
2887                         int sz = min_t(int, tso.size, left);
2888                         left -= sz;
2889                         descs++;
2890
2891                         if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq,
2892                                                txq_pcpu, sz, left, len == 0))
2893                                 goto release;
2894                         tso_build_data(skb, &tso, sz);
2895                 }
2896         }
2897
2898         return descs;
2899
2900 release:
2901         for (i = descs - 1; i >= 0; i--) {
2902                 struct mvpp2_tx_desc *tx_desc = txq->descs + i;
2903                 tx_desc_unmap_put(port, txq, tx_desc);
2904         }
2905         return 0;
2906 }
2907
2908 /* Main tx processing */
2909 static int mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
2910 {
2911         struct mvpp2_port *port = netdev_priv(dev);
2912         struct mvpp2_tx_queue *txq, *aggr_txq;
2913         struct mvpp2_txq_pcpu *txq_pcpu;
2914         struct mvpp2_tx_desc *tx_desc;
2915         dma_addr_t buf_dma_addr;
2916         int frags = 0;
2917         u16 txq_id;
2918         u32 tx_cmd;
2919
2920         txq_id = skb_get_queue_mapping(skb);
2921         txq = port->txqs[txq_id];
2922         txq_pcpu = this_cpu_ptr(txq->pcpu);
2923         aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
2924
2925         if (skb_is_gso(skb)) {
2926                 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu);
2927                 goto out;
2928         }
2929         frags = skb_shinfo(skb)->nr_frags + 1;
2930
2931         /* Check number of available descriptors */
2932         if (mvpp2_aggr_desc_num_check(port->priv, aggr_txq, frags) ||
2933             mvpp2_txq_reserved_desc_num_proc(port->priv, txq,
2934                                              txq_pcpu, frags)) {
2935                 frags = 0;
2936                 goto out;
2937         }
2938
2939         /* Get a descriptor for the first part of the packet */
2940         tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2941         mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2942         mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb));
2943
2944         buf_dma_addr = dma_map_single(dev->dev.parent, skb->data,
2945                                       skb_headlen(skb), DMA_TO_DEVICE);
2946         if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
2947                 mvpp2_txq_desc_put(txq);
2948                 frags = 0;
2949                 goto out;
2950         }
2951
2952         mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
2953
2954         tx_cmd = mvpp2_skb_tx_csum(port, skb);
2955
2956         if (frags == 1) {
2957                 /* First and Last descriptor */
2958                 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
2959                 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
2960                 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
2961         } else {
2962                 /* First but not Last */
2963                 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE;
2964                 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
2965                 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
2966
2967                 /* Continue with other skb fragments */
2968                 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {
2969                         tx_desc_unmap_put(port, txq, tx_desc);
2970                         frags = 0;
2971                 }
2972         }
2973
2974 out:
2975         if (frags > 0) {
2976                 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
2977                 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
2978
2979                 txq_pcpu->reserved_num -= frags;
2980                 txq_pcpu->count += frags;
2981                 aggr_txq->count += frags;
2982
2983                 /* Enable transmit */
2984                 wmb();
2985                 mvpp2_aggr_txq_pend_desc_add(port, frags);
2986
2987                 if (txq_pcpu->count >= txq_pcpu->stop_threshold)
2988                         netif_tx_stop_queue(nq);
2989
2990                 u64_stats_update_begin(&stats->syncp);
2991                 stats->tx_packets++;
2992                 stats->tx_bytes += skb->len;
2993                 u64_stats_update_end(&stats->syncp);
2994         } else {
2995                 dev->stats.tx_dropped++;
2996                 dev_kfree_skb_any(skb);
2997         }
2998
2999         /* Finalize TX processing */
3000         if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
3001                 mvpp2_txq_done(port, txq, txq_pcpu);
3002
3003         /* Set the timer in case not all frags were processed */
3004         if (!port->has_tx_irqs && txq_pcpu->count <= frags &&
3005             txq_pcpu->count > 0) {
3006                 struct mvpp2_port_pcpu *port_pcpu = this_cpu_ptr(port->pcpu);
3007
3008                 mvpp2_timer_set(port_pcpu);
3009         }
3010
3011         return NETDEV_TX_OK;
3012 }
3013
3014 static inline void mvpp2_cause_error(struct net_device *dev, int cause)
3015 {
3016         if (cause & MVPP2_CAUSE_FCS_ERR_MASK)
3017                 netdev_err(dev, "FCS error\n");
3018         if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK)
3019                 netdev_err(dev, "rx fifo overrun error\n");
3020         if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK)
3021                 netdev_err(dev, "tx fifo underrun error\n");
3022 }
3023
3024 static int mvpp2_poll(struct napi_struct *napi, int budget)
3025 {
3026         u32 cause_rx_tx, cause_rx, cause_tx, cause_misc;
3027         int rx_done = 0;
3028         struct mvpp2_port *port = netdev_priv(napi->dev);
3029         struct mvpp2_queue_vector *qv;
3030         int cpu = smp_processor_id();
3031
3032         qv = container_of(napi, struct mvpp2_queue_vector, napi);
3033
3034         /* Rx/Tx cause register
3035          *
3036          * Bits 0-15: each bit indicates received packets on the Rx queue
3037          * (bit 0 is for Rx queue 0).
3038          *
3039          * Bits 16-23: each bit indicates transmitted packets on the Tx queue
3040          * (bit 16 is for Tx queue 0).
3041          *
3042          * Each CPU has its own Rx/Tx cause register
3043          */
3044         cause_rx_tx = mvpp2_percpu_read_relaxed(port->priv, qv->sw_thread_id,
3045                                                 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
3046
3047         cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
3048         if (cause_misc) {
3049                 mvpp2_cause_error(port->dev, cause_misc);
3050
3051                 /* Clear the cause register */
3052                 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);
3053                 mvpp2_percpu_write(port->priv, cpu,
3054                                    MVPP2_ISR_RX_TX_CAUSE_REG(port->id),
3055                                    cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK);
3056         }
3057
3058         if (port->has_tx_irqs) {
3059                 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
3060                 if (cause_tx) {
3061                         cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET;
3062                         mvpp2_tx_done(port, cause_tx, qv->sw_thread_id);
3063                 }
3064         }
3065
3066         /* Process RX packets */
3067         cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK;
3068         cause_rx <<= qv->first_rxq;
3069         cause_rx |= qv->pending_cause_rx;
3070         while (cause_rx && budget > 0) {
3071                 int count;
3072                 struct mvpp2_rx_queue *rxq;
3073
3074                 rxq = mvpp2_get_rx_queue(port, cause_rx);
3075                 if (!rxq)
3076                         break;
3077
3078                 count = mvpp2_rx(port, napi, budget, rxq);
3079                 rx_done += count;
3080                 budget -= count;
3081                 if (budget > 0) {
3082                         /* Clear the bit associated to this Rx queue
3083                          * so that next iteration will continue from
3084                          * the next Rx queue.
3085                          */
3086                         cause_rx &= ~(1 << rxq->logic_rxq);
3087                 }
3088         }
3089
3090         if (budget > 0) {
3091                 cause_rx = 0;
3092                 napi_complete_done(napi, rx_done);
3093
3094                 mvpp2_qvec_interrupt_enable(qv);
3095         }
3096         qv->pending_cause_rx = cause_rx;
3097         return rx_done;
3098 }
3099
3100 static void mvpp22_mode_reconfigure(struct mvpp2_port *port)
3101 {
3102         u32 ctrl3;
3103
3104         /* comphy reconfiguration */
3105         mvpp22_comphy_init(port);
3106
3107         /* gop reconfiguration */
3108         mvpp22_gop_init(port);
3109
3110         /* Only GOP port 0 has an XLG MAC */
3111         if (port->gop_id == 0) {
3112                 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG);
3113                 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3114
3115                 if (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
3116                     port->phy_interface == PHY_INTERFACE_MODE_10GKR)
3117                         ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G;
3118                 else
3119                         ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
3120
3121                 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG);
3122         }
3123
3124         if (port->gop_id == 0 &&
3125             (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
3126              port->phy_interface == PHY_INTERFACE_MODE_10GKR))
3127                 mvpp2_xlg_max_rx_size_set(port);
3128         else
3129                 mvpp2_gmac_max_rx_size_set(port);
3130 }
3131
3132 /* Set hw internals when starting port */
3133 static void mvpp2_start_dev(struct mvpp2_port *port)
3134 {
3135         int i;
3136
3137         mvpp2_txp_max_tx_size_set(port);
3138
3139         for (i = 0; i < port->nqvecs; i++)
3140                 napi_enable(&port->qvecs[i].napi);
3141
3142         /* Enable interrupts on all CPUs */
3143         mvpp2_interrupts_enable(port);
3144
3145         if (port->priv->hw_version == MVPP22)
3146                 mvpp22_mode_reconfigure(port);
3147
3148         if (port->phylink) {
3149                 netif_carrier_off(port->dev);
3150                 phylink_start(port->phylink);
3151         } else {
3152                 /* Phylink isn't used as of now for ACPI, so the MAC has to be
3153                  * configured manually when the interface is started. This will
3154                  * be removed as soon as the phylink ACPI support lands in.
3155                  */
3156                 struct phylink_link_state state = {
3157                         .interface = port->phy_interface,
3158                 };
3159                 mvpp2_mac_config(port->dev, MLO_AN_INBAND, &state);
3160                 mvpp2_mac_link_up(port->dev, MLO_AN_INBAND, port->phy_interface,
3161                                   NULL);
3162         }
3163
3164         netif_tx_start_all_queues(port->dev);
3165 }
3166
3167 /* Set hw internals when stopping port */
3168 static void mvpp2_stop_dev(struct mvpp2_port *port)
3169 {
3170         int i;
3171
3172         /* Disable interrupts on all CPUs */
3173         mvpp2_interrupts_disable(port);
3174
3175         for (i = 0; i < port->nqvecs; i++)
3176                 napi_disable(&port->qvecs[i].napi);
3177
3178         if (port->phylink)
3179                 phylink_stop(port->phylink);
3180         phy_power_off(port->comphy);
3181 }
3182
3183 static int mvpp2_check_ringparam_valid(struct net_device *dev,
3184                                        struct ethtool_ringparam *ring)
3185 {
3186         u16 new_rx_pending = ring->rx_pending;
3187         u16 new_tx_pending = ring->tx_pending;
3188
3189         if (ring->rx_pending == 0 || ring->tx_pending == 0)
3190                 return -EINVAL;
3191
3192         if (ring->rx_pending > MVPP2_MAX_RXD_MAX)
3193                 new_rx_pending = MVPP2_MAX_RXD_MAX;
3194         else if (!IS_ALIGNED(ring->rx_pending, 16))
3195                 new_rx_pending = ALIGN(ring->rx_pending, 16);
3196
3197         if (ring->tx_pending > MVPP2_MAX_TXD_MAX)
3198                 new_tx_pending = MVPP2_MAX_TXD_MAX;
3199         else if (!IS_ALIGNED(ring->tx_pending, 32))
3200                 new_tx_pending = ALIGN(ring->tx_pending, 32);
3201
3202         /* The Tx ring size cannot be smaller than the minimum number of
3203          * descriptors needed for TSO.
3204          */
3205         if (new_tx_pending < MVPP2_MAX_SKB_DESCS)
3206                 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32);
3207
3208         if (ring->rx_pending != new_rx_pending) {
3209                 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n",
3210                             ring->rx_pending, new_rx_pending);
3211                 ring->rx_pending = new_rx_pending;
3212         }
3213
3214         if (ring->tx_pending != new_tx_pending) {
3215                 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n",
3216                             ring->tx_pending, new_tx_pending);
3217                 ring->tx_pending = new_tx_pending;
3218         }
3219
3220         return 0;
3221 }
3222
3223 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr)
3224 {
3225         u32 mac_addr_l, mac_addr_m, mac_addr_h;
3226
3227         mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
3228         mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE);
3229         mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH);
3230         addr[0] = (mac_addr_h >> 24) & 0xFF;
3231         addr[1] = (mac_addr_h >> 16) & 0xFF;
3232         addr[2] = (mac_addr_h >> 8) & 0xFF;
3233         addr[3] = mac_addr_h & 0xFF;
3234         addr[4] = mac_addr_m & 0xFF;
3235         addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF;
3236 }
3237
3238 static int mvpp2_irqs_init(struct mvpp2_port *port)
3239 {
3240         int err, i;
3241
3242         for (i = 0; i < port->nqvecs; i++) {
3243                 struct mvpp2_queue_vector *qv = port->qvecs + i;
3244
3245                 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE)
3246                         irq_set_status_flags(qv->irq, IRQ_NO_BALANCING);
3247
3248                 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv);
3249                 if (err)
3250                         goto err;
3251
3252                 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE)
3253                         irq_set_affinity_hint(qv->irq,
3254                                               cpumask_of(qv->sw_thread_id));
3255         }
3256
3257         return 0;
3258 err:
3259         for (i = 0; i < port->nqvecs; i++) {
3260                 struct mvpp2_queue_vector *qv = port->qvecs + i;
3261
3262                 irq_set_affinity_hint(qv->irq, NULL);
3263                 free_irq(qv->irq, qv);
3264         }
3265
3266         return err;
3267 }
3268
3269 static void mvpp2_irqs_deinit(struct mvpp2_port *port)
3270 {
3271         int i;
3272
3273         for (i = 0; i < port->nqvecs; i++) {
3274                 struct mvpp2_queue_vector *qv = port->qvecs + i;
3275
3276                 irq_set_affinity_hint(qv->irq, NULL);
3277                 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING);
3278                 free_irq(qv->irq, qv);
3279         }
3280 }
3281
3282 static bool mvpp22_rss_is_supported(void)
3283 {
3284         return queue_mode == MVPP2_QDIST_MULTI_MODE;
3285 }
3286
3287 static int mvpp2_open(struct net_device *dev)
3288 {
3289         struct mvpp2_port *port = netdev_priv(dev);
3290         struct mvpp2 *priv = port->priv;
3291         unsigned char mac_bcast[ETH_ALEN] = {
3292                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3293         bool valid = false;
3294         int err;
3295
3296         err = mvpp2_prs_mac_da_accept(port, mac_bcast, true);
3297         if (err) {
3298                 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
3299                 return err;
3300         }
3301         err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true);
3302         if (err) {
3303                 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n");
3304                 return err;
3305         }
3306         err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH);
3307         if (err) {
3308                 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n");
3309                 return err;
3310         }
3311         err = mvpp2_prs_def_flow(port);
3312         if (err) {
3313                 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
3314                 return err;
3315         }
3316
3317         /* Allocate the Rx/Tx queues */
3318         err = mvpp2_setup_rxqs(port);
3319         if (err) {
3320                 netdev_err(port->dev, "cannot allocate Rx queues\n");
3321                 return err;
3322         }
3323
3324         err = mvpp2_setup_txqs(port);
3325         if (err) {
3326                 netdev_err(port->dev, "cannot allocate Tx queues\n");
3327                 goto err_cleanup_rxqs;
3328         }
3329
3330         err = mvpp2_irqs_init(port);
3331         if (err) {
3332                 netdev_err(port->dev, "cannot init IRQs\n");
3333                 goto err_cleanup_txqs;
3334         }
3335
3336         /* Phylink isn't supported yet in ACPI mode */
3337         if (port->of_node) {
3338                 err = phylink_of_phy_connect(port->phylink, port->of_node, 0);
3339                 if (err) {
3340                         netdev_err(port->dev, "could not attach PHY (%d)\n",
3341                                    err);
3342                         goto err_free_irq;
3343                 }
3344
3345                 valid = true;
3346         }
3347
3348         if (priv->hw_version == MVPP22 && port->link_irq && !port->phylink) {
3349                 err = request_irq(port->link_irq, mvpp2_link_status_isr, 0,
3350                                   dev->name, port);
3351                 if (err) {
3352                         netdev_err(port->dev, "cannot request link IRQ %d\n",
3353                                    port->link_irq);
3354                         goto err_free_irq;
3355                 }
3356
3357                 mvpp22_gop_setup_irq(port);
3358
3359                 /* In default link is down */
3360                 netif_carrier_off(port->dev);
3361
3362                 valid = true;
3363         } else {
3364                 port->link_irq = 0;
3365         }
3366
3367         if (!valid) {
3368                 netdev_err(port->dev,
3369                            "invalid configuration: no dt or link IRQ");
3370                 goto err_free_irq;
3371         }
3372
3373         /* Unmask interrupts on all CPUs */
3374         on_each_cpu(mvpp2_interrupts_unmask, port, 1);
3375         mvpp2_shared_interrupt_mask_unmask(port, false);
3376
3377         mvpp2_start_dev(port);
3378
3379         /* Start hardware statistics gathering */
3380         queue_delayed_work(priv->stats_queue, &port->stats_work,
3381                            MVPP2_MIB_COUNTERS_STATS_DELAY);
3382
3383         return 0;
3384
3385 err_free_irq:
3386         mvpp2_irqs_deinit(port);
3387 err_cleanup_txqs:
3388         mvpp2_cleanup_txqs(port);
3389 err_cleanup_rxqs:
3390         mvpp2_cleanup_rxqs(port);
3391         return err;
3392 }
3393
3394 static int mvpp2_stop(struct net_device *dev)
3395 {
3396         struct mvpp2_port *port = netdev_priv(dev);
3397         struct mvpp2_port_pcpu *port_pcpu;
3398         int cpu;
3399
3400         mvpp2_stop_dev(port);
3401
3402         /* Mask interrupts on all CPUs */
3403         on_each_cpu(mvpp2_interrupts_mask, port, 1);
3404         mvpp2_shared_interrupt_mask_unmask(port, true);
3405
3406         if (port->phylink)
3407                 phylink_disconnect_phy(port->phylink);
3408         if (port->link_irq)
3409                 free_irq(port->link_irq, port);
3410
3411         mvpp2_irqs_deinit(port);
3412         if (!port->has_tx_irqs) {
3413                 for_each_present_cpu(cpu) {
3414                         port_pcpu = per_cpu_ptr(port->pcpu, cpu);
3415
3416                         hrtimer_cancel(&port_pcpu->tx_done_timer);
3417                         port_pcpu->timer_scheduled = false;
3418                         tasklet_kill(&port_pcpu->tx_done_tasklet);
3419                 }
3420         }
3421         mvpp2_cleanup_rxqs(port);
3422         mvpp2_cleanup_txqs(port);
3423
3424         cancel_delayed_work_sync(&port->stats_work);
3425
3426         return 0;
3427 }
3428
3429 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port,
3430                                         struct netdev_hw_addr_list *list)
3431 {
3432         struct netdev_hw_addr *ha;
3433         int ret;
3434
3435         netdev_hw_addr_list_for_each(ha, list) {
3436                 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true);
3437                 if (ret)
3438                         return ret;
3439         }
3440
3441         return 0;
3442 }
3443
3444 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable)
3445 {
3446         if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER))
3447                 mvpp2_prs_vid_enable_filtering(port);
3448         else
3449                 mvpp2_prs_vid_disable_filtering(port);
3450
3451         mvpp2_prs_mac_promisc_set(port->priv, port->id,
3452                                   MVPP2_PRS_L2_UNI_CAST, enable);
3453
3454         mvpp2_prs_mac_promisc_set(port->priv, port->id,
3455                                   MVPP2_PRS_L2_MULTI_CAST, enable);
3456 }
3457
3458 static void mvpp2_set_rx_mode(struct net_device *dev)
3459 {
3460         struct mvpp2_port *port = netdev_priv(dev);
3461
3462         /* Clear the whole UC and MC list */
3463         mvpp2_prs_mac_del_all(port);
3464
3465         if (dev->flags & IFF_PROMISC) {
3466                 mvpp2_set_rx_promisc(port, true);
3467                 return;
3468         }
3469
3470         mvpp2_set_rx_promisc(port, false);
3471
3472         if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX ||
3473             mvpp2_prs_mac_da_accept_list(port, &dev->uc))
3474                 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3475                                           MVPP2_PRS_L2_UNI_CAST, true);
3476
3477         if (dev->flags & IFF_ALLMULTI) {
3478                 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3479                                           MVPP2_PRS_L2_MULTI_CAST, true);
3480                 return;
3481         }
3482
3483         if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX ||
3484             mvpp2_prs_mac_da_accept_list(port, &dev->mc))
3485                 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3486                                           MVPP2_PRS_L2_MULTI_CAST, true);
3487 }
3488
3489 static int mvpp2_set_mac_address(struct net_device *dev, void *p)
3490 {
3491         const struct sockaddr *addr = p;
3492         int err;
3493
3494         if (!is_valid_ether_addr(addr->sa_data))
3495                 return -EADDRNOTAVAIL;
3496
3497         err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
3498         if (err) {
3499                 /* Reconfigure parser accept the original MAC address */
3500                 mvpp2_prs_update_mac_da(dev, dev->dev_addr);
3501                 netdev_err(dev, "failed to change MAC address\n");
3502         }
3503         return err;
3504 }
3505
3506 static int mvpp2_change_mtu(struct net_device *dev, int mtu)
3507 {
3508         struct mvpp2_port *port = netdev_priv(dev);
3509         int err;
3510
3511         if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) {
3512                 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu,
3513                             ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8));
3514                 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8);
3515         }
3516
3517         if (!netif_running(dev)) {
3518                 err = mvpp2_bm_update_mtu(dev, mtu);
3519                 if (!err) {
3520                         port->pkt_size =  MVPP2_RX_PKT_SIZE(mtu);
3521                         return 0;
3522                 }
3523
3524                 /* Reconfigure BM to the original MTU */
3525                 err = mvpp2_bm_update_mtu(dev, dev->mtu);
3526                 if (err)
3527                         goto log_error;
3528         }
3529
3530         mvpp2_stop_dev(port);
3531
3532         err = mvpp2_bm_update_mtu(dev, mtu);
3533         if (!err) {
3534                 port->pkt_size =  MVPP2_RX_PKT_SIZE(mtu);
3535                 goto out_start;
3536         }
3537
3538         /* Reconfigure BM to the original MTU */
3539         err = mvpp2_bm_update_mtu(dev, dev->mtu);
3540         if (err)
3541                 goto log_error;
3542
3543 out_start:
3544         mvpp2_start_dev(port);
3545         mvpp2_egress_enable(port);
3546         mvpp2_ingress_enable(port);
3547
3548         return 0;
3549 log_error:
3550         netdev_err(dev, "failed to change MTU\n");
3551         return err;
3552 }
3553
3554 static void
3555 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
3556 {
3557         struct mvpp2_port *port = netdev_priv(dev);
3558         unsigned int start;
3559         int cpu;
3560
3561         for_each_possible_cpu(cpu) {
3562                 struct mvpp2_pcpu_stats *cpu_stats;
3563                 u64 rx_packets;
3564                 u64 rx_bytes;
3565                 u64 tx_packets;
3566                 u64 tx_bytes;
3567
3568                 cpu_stats = per_cpu_ptr(port->stats, cpu);
3569                 do {
3570                         start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
3571                         rx_packets = cpu_stats->rx_packets;
3572                         rx_bytes   = cpu_stats->rx_bytes;
3573                         tx_packets = cpu_stats->tx_packets;
3574                         tx_bytes   = cpu_stats->tx_bytes;
3575                 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
3576
3577                 stats->rx_packets += rx_packets;
3578                 stats->rx_bytes   += rx_bytes;
3579                 stats->tx_packets += tx_packets;
3580                 stats->tx_bytes   += tx_bytes;
3581         }
3582
3583         stats->rx_errors        = dev->stats.rx_errors;
3584         stats->rx_dropped       = dev->stats.rx_dropped;
3585         stats->tx_dropped       = dev->stats.tx_dropped;
3586 }
3587
3588 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3589 {
3590         struct mvpp2_port *port = netdev_priv(dev);
3591
3592         if (!port->phylink)
3593                 return -ENOTSUPP;
3594
3595         return phylink_mii_ioctl(port->phylink, ifr, cmd);
3596 }
3597
3598 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
3599 {
3600         struct mvpp2_port *port = netdev_priv(dev);
3601         int ret;
3602
3603         ret = mvpp2_prs_vid_entry_add(port, vid);
3604         if (ret)
3605                 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n",
3606                            MVPP2_PRS_VLAN_FILT_MAX - 1);
3607         return ret;
3608 }
3609
3610 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
3611 {
3612         struct mvpp2_port *port = netdev_priv(dev);
3613
3614         mvpp2_prs_vid_entry_remove(port, vid);
3615         return 0;
3616 }
3617
3618 static int mvpp2_set_features(struct net_device *dev,
3619                               netdev_features_t features)
3620 {
3621         netdev_features_t changed = dev->features ^ features;
3622         struct mvpp2_port *port = netdev_priv(dev);
3623
3624         if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
3625                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) {
3626                         mvpp2_prs_vid_enable_filtering(port);
3627                 } else {
3628                         /* Invalidate all registered VID filters for this
3629                          * port
3630                          */
3631                         mvpp2_prs_vid_remove_all(port);
3632
3633                         mvpp2_prs_vid_disable_filtering(port);
3634                 }
3635         }
3636
3637         if (changed & NETIF_F_RXHASH) {
3638                 if (features & NETIF_F_RXHASH)
3639                         mvpp22_rss_enable(port);
3640                 else
3641                         mvpp22_rss_disable(port);
3642         }
3643
3644         return 0;
3645 }
3646
3647 /* Ethtool methods */
3648
3649 static int mvpp2_ethtool_nway_reset(struct net_device *dev)
3650 {
3651         struct mvpp2_port *port = netdev_priv(dev);
3652
3653         if (!port->phylink)
3654                 return -ENOTSUPP;
3655
3656         return phylink_ethtool_nway_reset(port->phylink);
3657 }
3658
3659 /* Set interrupt coalescing for ethtools */
3660 static int mvpp2_ethtool_set_coalesce(struct net_device *dev,
3661                                       struct ethtool_coalesce *c)
3662 {
3663         struct mvpp2_port *port = netdev_priv(dev);
3664         int queue;
3665
3666         for (queue = 0; queue < port->nrxqs; queue++) {
3667                 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
3668
3669                 rxq->time_coal = c->rx_coalesce_usecs;
3670                 rxq->pkts_coal = c->rx_max_coalesced_frames;
3671                 mvpp2_rx_pkts_coal_set(port, rxq);
3672                 mvpp2_rx_time_coal_set(port, rxq);
3673         }
3674
3675         if (port->has_tx_irqs) {
3676                 port->tx_time_coal = c->tx_coalesce_usecs;
3677                 mvpp2_tx_time_coal_set(port);
3678         }
3679
3680         for (queue = 0; queue < port->ntxqs; queue++) {
3681                 struct mvpp2_tx_queue *txq = port->txqs[queue];
3682
3683                 txq->done_pkts_coal = c->tx_max_coalesced_frames;
3684
3685                 if (port->has_tx_irqs)
3686                         mvpp2_tx_pkts_coal_set(port, txq);
3687         }
3688
3689         return 0;
3690 }
3691
3692 /* get coalescing for ethtools */
3693 static int mvpp2_ethtool_get_coalesce(struct net_device *dev,
3694                                       struct ethtool_coalesce *c)
3695 {
3696         struct mvpp2_port *port = netdev_priv(dev);
3697
3698         c->rx_coalesce_usecs       = port->rxqs[0]->time_coal;
3699         c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal;
3700         c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal;
3701         c->tx_coalesce_usecs       = port->tx_time_coal;
3702         return 0;
3703 }
3704
3705 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev,
3706                                       struct ethtool_drvinfo *drvinfo)
3707 {
3708         strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME,
3709                 sizeof(drvinfo->driver));
3710         strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION,
3711                 sizeof(drvinfo->version));
3712         strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
3713                 sizeof(drvinfo->bus_info));
3714 }
3715
3716 static void mvpp2_ethtool_get_ringparam(struct net_device *dev,
3717                                         struct ethtool_ringparam *ring)
3718 {
3719         struct mvpp2_port *port = netdev_priv(dev);
3720
3721         ring->rx_max_pending = MVPP2_MAX_RXD_MAX;
3722         ring->tx_max_pending = MVPP2_MAX_TXD_MAX;
3723         ring->rx_pending = port->rx_ring_size;
3724         ring->tx_pending = port->tx_ring_size;
3725 }
3726
3727 static int mvpp2_ethtool_set_ringparam(struct net_device *dev,
3728                                        struct ethtool_ringparam *ring)
3729 {
3730         struct mvpp2_port *port = netdev_priv(dev);
3731         u16 prev_rx_ring_size = port->rx_ring_size;
3732         u16 prev_tx_ring_size = port->tx_ring_size;
3733         int err;
3734
3735         err = mvpp2_check_ringparam_valid(dev, ring);
3736         if (err)
3737                 return err;
3738
3739         if (!netif_running(dev)) {
3740                 port->rx_ring_size = ring->rx_pending;
3741                 port->tx_ring_size = ring->tx_pending;
3742                 return 0;
3743         }
3744
3745         /* The interface is running, so we have to force a
3746          * reallocation of the queues
3747          */
3748         mvpp2_stop_dev(port);
3749         mvpp2_cleanup_rxqs(port);
3750         mvpp2_cleanup_txqs(port);
3751
3752         port->rx_ring_size = ring->rx_pending;
3753         port->tx_ring_size = ring->tx_pending;
3754
3755         err = mvpp2_setup_rxqs(port);
3756         if (err) {
3757                 /* Reallocate Rx queues with the original ring size */
3758                 port->rx_ring_size = prev_rx_ring_size;
3759                 ring->rx_pending = prev_rx_ring_size;
3760                 err = mvpp2_setup_rxqs(port);
3761                 if (err)
3762                         goto err_out;
3763         }
3764         err = mvpp2_setup_txqs(port);
3765         if (err) {
3766                 /* Reallocate Tx queues with the original ring size */
3767                 port->tx_ring_size = prev_tx_ring_size;
3768                 ring->tx_pending = prev_tx_ring_size;
3769                 err = mvpp2_setup_txqs(port);
3770                 if (err)
3771                         goto err_clean_rxqs;
3772         }
3773
3774         mvpp2_start_dev(port);
3775         mvpp2_egress_enable(port);
3776         mvpp2_ingress_enable(port);
3777
3778         return 0;
3779
3780 err_clean_rxqs:
3781         mvpp2_cleanup_rxqs(port);
3782 err_out:
3783         netdev_err(dev, "failed to change ring parameters");
3784         return err;
3785 }
3786
3787 static void mvpp2_ethtool_get_pause_param(struct net_device *dev,
3788                                           struct ethtool_pauseparam *pause)
3789 {
3790         struct mvpp2_port *port = netdev_priv(dev);
3791
3792         if (!port->phylink)
3793                 return;
3794
3795         phylink_ethtool_get_pauseparam(port->phylink, pause);
3796 }
3797
3798 static int mvpp2_ethtool_set_pause_param(struct net_device *dev,
3799                                          struct ethtool_pauseparam *pause)
3800 {
3801         struct mvpp2_port *port = netdev_priv(dev);
3802
3803         if (!port->phylink)
3804                 return -ENOTSUPP;
3805
3806         return phylink_ethtool_set_pauseparam(port->phylink, pause);
3807 }
3808
3809 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev,
3810                                             struct ethtool_link_ksettings *cmd)
3811 {
3812         struct mvpp2_port *port = netdev_priv(dev);
3813
3814         if (!port->phylink)
3815                 return -ENOTSUPP;
3816
3817         return phylink_ethtool_ksettings_get(port->phylink, cmd);
3818 }
3819
3820 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev,
3821                                             const struct ethtool_link_ksettings *cmd)
3822 {
3823         struct mvpp2_port *port = netdev_priv(dev);
3824
3825         if (!port->phylink)
3826                 return -ENOTSUPP;
3827
3828         return phylink_ethtool_ksettings_set(port->phylink, cmd);
3829 }
3830
3831 static int mvpp2_ethtool_get_rxnfc(struct net_device *dev,
3832                                    struct ethtool_rxnfc *info, u32 *rules)
3833 {
3834         struct mvpp2_port *port = netdev_priv(dev);
3835         int ret = 0;
3836
3837         if (!mvpp22_rss_is_supported())
3838                 return -EOPNOTSUPP;
3839
3840         switch (info->cmd) {
3841         case ETHTOOL_GRXFH:
3842                 ret = mvpp2_ethtool_rxfh_get(port, info);
3843                 break;
3844         case ETHTOOL_GRXRINGS:
3845                 info->data = port->nrxqs;
3846                 break;
3847         default:
3848                 return -ENOTSUPP;
3849         }
3850
3851         return ret;
3852 }
3853
3854 static int mvpp2_ethtool_set_rxnfc(struct net_device *dev,
3855                                    struct ethtool_rxnfc *info)
3856 {
3857         struct mvpp2_port *port = netdev_priv(dev);
3858         int ret = 0;
3859
3860         if (!mvpp22_rss_is_supported())
3861                 return -EOPNOTSUPP;
3862
3863         switch (info->cmd) {
3864         case ETHTOOL_SRXFH:
3865                 ret = mvpp2_ethtool_rxfh_set(port, info);
3866                 break;
3867         default:
3868                 return -EOPNOTSUPP;
3869         }
3870         return ret;
3871 }
3872
3873 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev)
3874 {
3875         return mvpp22_rss_is_supported() ? MVPP22_RSS_TABLE_ENTRIES : 0;
3876 }
3877
3878 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3879                                   u8 *hfunc)
3880 {
3881         struct mvpp2_port *port = netdev_priv(dev);
3882
3883         if (!mvpp22_rss_is_supported())
3884                 return -EOPNOTSUPP;
3885
3886         if (indir)
3887                 memcpy(indir, port->indir,
3888                        ARRAY_SIZE(port->indir) * sizeof(port->indir[0]));
3889
3890         if (hfunc)
3891                 *hfunc = ETH_RSS_HASH_CRC32;
3892
3893         return 0;
3894 }
3895
3896 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
3897                                   const u8 *key, const u8 hfunc)
3898 {
3899         struct mvpp2_port *port = netdev_priv(dev);
3900
3901         if (!mvpp22_rss_is_supported())
3902                 return -EOPNOTSUPP;
3903
3904         if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
3905                 return -EOPNOTSUPP;
3906
3907         if (key)
3908                 return -EOPNOTSUPP;
3909
3910         if (indir) {
3911                 memcpy(port->indir, indir,
3912                        ARRAY_SIZE(port->indir) * sizeof(port->indir[0]));
3913                 mvpp22_rss_fill_table(port, port->id);
3914         }
3915
3916         return 0;
3917 }
3918
3919 /* Device ops */
3920
3921 static const struct net_device_ops mvpp2_netdev_ops = {
3922         .ndo_open               = mvpp2_open,
3923         .ndo_stop               = mvpp2_stop,
3924         .ndo_start_xmit         = mvpp2_tx,
3925         .ndo_set_rx_mode        = mvpp2_set_rx_mode,
3926         .ndo_set_mac_address    = mvpp2_set_mac_address,
3927         .ndo_change_mtu         = mvpp2_change_mtu,
3928         .ndo_get_stats64        = mvpp2_get_stats64,
3929         .ndo_do_ioctl           = mvpp2_ioctl,
3930         .ndo_vlan_rx_add_vid    = mvpp2_vlan_rx_add_vid,
3931         .ndo_vlan_rx_kill_vid   = mvpp2_vlan_rx_kill_vid,
3932         .ndo_set_features       = mvpp2_set_features,
3933 };
3934
3935 static const struct ethtool_ops mvpp2_eth_tool_ops = {
3936         .nway_reset             = mvpp2_ethtool_nway_reset,
3937         .get_link               = ethtool_op_get_link,
3938         .set_coalesce           = mvpp2_ethtool_set_coalesce,
3939         .get_coalesce           = mvpp2_ethtool_get_coalesce,
3940         .get_drvinfo            = mvpp2_ethtool_get_drvinfo,
3941         .get_ringparam          = mvpp2_ethtool_get_ringparam,
3942         .set_ringparam          = mvpp2_ethtool_set_ringparam,
3943         .get_strings            = mvpp2_ethtool_get_strings,
3944         .get_ethtool_stats      = mvpp2_ethtool_get_stats,
3945         .get_sset_count         = mvpp2_ethtool_get_sset_count,
3946         .get_pauseparam         = mvpp2_ethtool_get_pause_param,
3947         .set_pauseparam         = mvpp2_ethtool_set_pause_param,
3948         .get_link_ksettings     = mvpp2_ethtool_get_link_ksettings,
3949         .set_link_ksettings     = mvpp2_ethtool_set_link_ksettings,
3950         .get_rxnfc              = mvpp2_ethtool_get_rxnfc,
3951         .set_rxnfc              = mvpp2_ethtool_set_rxnfc,
3952         .get_rxfh_indir_size    = mvpp2_ethtool_get_rxfh_indir_size,
3953         .get_rxfh               = mvpp2_ethtool_get_rxfh,
3954         .set_rxfh               = mvpp2_ethtool_set_rxfh,
3955
3956 };
3957
3958 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that
3959  * had a single IRQ defined per-port.
3960  */
3961 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port,
3962                                            struct device_node *port_node)
3963 {
3964         struct mvpp2_queue_vector *v = &port->qvecs[0];
3965
3966         v->first_rxq = 0;
3967         v->nrxqs = port->nrxqs;
3968         v->type = MVPP2_QUEUE_VECTOR_SHARED;
3969         v->sw_thread_id = 0;
3970         v->sw_thread_mask = *cpumask_bits(cpu_online_mask);
3971         v->port = port;
3972         v->irq = irq_of_parse_and_map(port_node, 0);
3973         if (v->irq <= 0)
3974                 return -EINVAL;
3975         netif_napi_add(port->dev, &v->napi, mvpp2_poll,
3976                        NAPI_POLL_WEIGHT);
3977
3978         port->nqvecs = 1;
3979
3980         return 0;
3981 }
3982
3983 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port,
3984                                           struct device_node *port_node)
3985 {
3986         struct mvpp2_queue_vector *v;
3987         int i, ret;
3988
3989         port->nqvecs = num_possible_cpus();
3990         if (queue_mode == MVPP2_QDIST_SINGLE_MODE)
3991                 port->nqvecs += 1;
3992
3993         for (i = 0; i < port->nqvecs; i++) {
3994                 char irqname[16];
3995
3996                 v = port->qvecs + i;
3997
3998                 v->port = port;
3999                 v->type = MVPP2_QUEUE_VECTOR_PRIVATE;
4000                 v->sw_thread_id = i;
4001                 v->sw_thread_mask = BIT(i);
4002
4003                 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i);
4004
4005                 if (queue_mode == MVPP2_QDIST_MULTI_MODE) {
4006                         v->first_rxq = i * MVPP2_DEFAULT_RXQ;
4007                         v->nrxqs = MVPP2_DEFAULT_RXQ;
4008                 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE &&
4009                            i == (port->nqvecs - 1)) {
4010                         v->first_rxq = 0;
4011                         v->nrxqs = port->nrxqs;
4012                         v->type = MVPP2_QUEUE_VECTOR_SHARED;
4013                         strncpy(irqname, "rx-shared", sizeof(irqname));
4014                 }
4015
4016                 if (port_node)
4017                         v->irq = of_irq_get_byname(port_node, irqname);
4018                 else
4019                         v->irq = fwnode_irq_get(port->fwnode, i);
4020                 if (v->irq <= 0) {
4021                         ret = -EINVAL;
4022                         goto err;
4023                 }
4024
4025                 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
4026                                NAPI_POLL_WEIGHT);
4027         }
4028
4029         return 0;
4030
4031 err:
4032         for (i = 0; i < port->nqvecs; i++)
4033                 irq_dispose_mapping(port->qvecs[i].irq);
4034         return ret;
4035 }
4036
4037 static int mvpp2_queue_vectors_init(struct mvpp2_port *port,
4038                                     struct device_node *port_node)
4039 {
4040         if (port->has_tx_irqs)
4041                 return mvpp2_multi_queue_vectors_init(port, port_node);
4042         else
4043                 return mvpp2_simple_queue_vectors_init(port, port_node);
4044 }
4045
4046 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port)
4047 {
4048         int i;
4049
4050         for (i = 0; i < port->nqvecs; i++)
4051                 irq_dispose_mapping(port->qvecs[i].irq);
4052 }
4053
4054 /* Configure Rx queue group interrupt for this port */
4055 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port)
4056 {
4057         struct mvpp2 *priv = port->priv;
4058         u32 val;
4059         int i;
4060
4061         if (priv->hw_version == MVPP21) {
4062                 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
4063                             port->nrxqs);
4064                 return;
4065         }
4066
4067         /* Handle the more complicated PPv2.2 case */
4068         for (i = 0; i < port->nqvecs; i++) {
4069                 struct mvpp2_queue_vector *qv = port->qvecs + i;
4070
4071                 if (!qv->nrxqs)
4072                         continue;
4073
4074                 val = qv->sw_thread_id;
4075                 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET;
4076                 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
4077
4078                 val = qv->first_rxq;
4079                 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET;
4080                 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
4081         }
4082 }
4083
4084 /* Initialize port HW */
4085 static int mvpp2_port_init(struct mvpp2_port *port)
4086 {
4087         struct device *dev = port->dev->dev.parent;
4088         struct mvpp2 *priv = port->priv;
4089         struct mvpp2_txq_pcpu *txq_pcpu;
4090         int queue, cpu, err;
4091
4092         /* Checks for hardware constraints */
4093         if (port->first_rxq + port->nrxqs >
4094             MVPP2_MAX_PORTS * priv->max_port_rxqs)
4095                 return -EINVAL;
4096
4097         if (port->nrxqs % MVPP2_DEFAULT_RXQ ||
4098             port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ)
4099                 return -EINVAL;
4100
4101         /* Disable port */
4102         mvpp2_egress_disable(port);
4103         mvpp2_port_disable(port);
4104
4105         port->tx_time_coal = MVPP2_TXDONE_COAL_USEC;
4106
4107         port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs),
4108                                   GFP_KERNEL);
4109         if (!port->txqs)
4110                 return -ENOMEM;
4111
4112         /* Associate physical Tx queues to this port and initialize.
4113          * The mapping is predefined.
4114          */
4115         for (queue = 0; queue < port->ntxqs; queue++) {
4116                 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
4117                 struct mvpp2_tx_queue *txq;
4118
4119                 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
4120                 if (!txq) {
4121                         err = -ENOMEM;
4122                         goto err_free_percpu;
4123                 }
4124
4125                 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu);
4126                 if (!txq->pcpu) {
4127                         err = -ENOMEM;
4128                         goto err_free_percpu;
4129                 }
4130
4131                 txq->id = queue_phy_id;
4132                 txq->log_id = queue;
4133                 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
4134                 for_each_present_cpu(cpu) {
4135                         txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
4136                         txq_pcpu->cpu = cpu;
4137                 }
4138
4139                 port->txqs[queue] = txq;
4140         }
4141
4142         port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs),
4143                                   GFP_KERNEL);
4144         if (!port->rxqs) {
4145                 err = -ENOMEM;
4146                 goto err_free_percpu;
4147         }
4148
4149         /* Allocate and initialize Rx queue for this port */
4150         for (queue = 0; queue < port->nrxqs; queue++) {
4151                 struct mvpp2_rx_queue *rxq;
4152
4153                 /* Map physical Rx queue to port's logical Rx queue */
4154                 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
4155                 if (!rxq) {
4156                         err = -ENOMEM;
4157                         goto err_free_percpu;
4158                 }
4159                 /* Map this Rx queue to a physical queue */
4160                 rxq->id = port->first_rxq + queue;
4161                 rxq->port = port->id;
4162                 rxq->logic_rxq = queue;
4163
4164                 port->rxqs[queue] = rxq;
4165         }
4166
4167         mvpp2_rx_irqs_setup(port);
4168
4169         /* Create Rx descriptor rings */
4170         for (queue = 0; queue < port->nrxqs; queue++) {
4171                 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
4172
4173                 rxq->size = port->rx_ring_size;
4174                 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
4175                 rxq->time_coal = MVPP2_RX_COAL_USEC;
4176         }
4177
4178         mvpp2_ingress_disable(port);
4179
4180         /* Port default configuration */
4181         mvpp2_defaults_set(port);
4182
4183         /* Port's classifier configuration */
4184         mvpp2_cls_oversize_rxq_set(port);
4185         mvpp2_cls_port_config(port);
4186
4187         if (mvpp22_rss_is_supported())
4188                 mvpp22_rss_port_init(port);
4189
4190         /* Provide an initial Rx packet size */
4191         port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu);
4192
4193         /* Initialize pools for swf */
4194         err = mvpp2_swf_bm_pool_init(port);
4195         if (err)
4196                 goto err_free_percpu;
4197
4198         return 0;
4199
4200 err_free_percpu:
4201         for (queue = 0; queue < port->ntxqs; queue++) {
4202                 if (!port->txqs[queue])
4203                         continue;
4204                 free_percpu(port->txqs[queue]->pcpu);
4205         }
4206         return err;
4207 }
4208
4209 /* Checks if the port DT description has the TX interrupts
4210  * described. On PPv2.1, there are no such interrupts. On PPv2.2,
4211  * there are available, but we need to keep support for old DTs.
4212  */
4213 static bool mvpp2_port_has_tx_irqs(struct mvpp2 *priv,
4214                                    struct device_node *port_node)
4215 {
4216         char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1",
4217                           "tx-cpu2", "tx-cpu3" };
4218         int ret, i;
4219
4220         if (priv->hw_version == MVPP21)
4221                 return false;
4222
4223         for (i = 0; i < 5; i++) {
4224                 ret = of_property_match_string(port_node, "interrupt-names",
4225                                                irqs[i]);
4226                 if (ret < 0)
4227                         return false;
4228         }
4229
4230         return true;
4231 }
4232
4233 static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv,
4234                                      struct fwnode_handle *fwnode,
4235                                      char **mac_from)
4236 {
4237         struct mvpp2_port *port = netdev_priv(dev);
4238         char hw_mac_addr[ETH_ALEN] = {0};
4239         char fw_mac_addr[ETH_ALEN];
4240
4241         if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) {
4242                 *mac_from = "firmware node";
4243                 ether_addr_copy(dev->dev_addr, fw_mac_addr);
4244                 return;
4245         }
4246
4247         if (priv->hw_version == MVPP21) {
4248                 mvpp21_get_mac_address(port, hw_mac_addr);
4249                 if (is_valid_ether_addr(hw_mac_addr)) {
4250                         *mac_from = "hardware";
4251                         ether_addr_copy(dev->dev_addr, hw_mac_addr);
4252                         return;
4253                 }
4254         }
4255
4256         *mac_from = "random";
4257         eth_hw_addr_random(dev);
4258 }
4259
4260 static void mvpp2_phylink_validate(struct net_device *dev,
4261                                    unsigned long *supported,
4262                                    struct phylink_link_state *state)
4263 {
4264         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
4265
4266         phylink_set(mask, Autoneg);
4267         phylink_set_port_modes(mask);
4268         phylink_set(mask, Pause);
4269         phylink_set(mask, Asym_Pause);
4270
4271         switch (state->interface) {
4272         case PHY_INTERFACE_MODE_10GKR:
4273                 phylink_set(mask, 10000baseCR_Full);
4274                 phylink_set(mask, 10000baseSR_Full);
4275                 phylink_set(mask, 10000baseLR_Full);
4276                 phylink_set(mask, 10000baseLRM_Full);
4277                 phylink_set(mask, 10000baseER_Full);
4278                 phylink_set(mask, 10000baseKR_Full);
4279                 /* Fall-through */
4280         default:
4281                 phylink_set(mask, 10baseT_Half);
4282                 phylink_set(mask, 10baseT_Full);
4283                 phylink_set(mask, 100baseT_Half);
4284                 phylink_set(mask, 100baseT_Full);
4285                 phylink_set(mask, 10000baseT_Full);
4286                 /* Fall-through */
4287         case PHY_INTERFACE_MODE_1000BASEX:
4288         case PHY_INTERFACE_MODE_2500BASEX:
4289                 phylink_set(mask, 1000baseT_Full);
4290                 phylink_set(mask, 1000baseX_Full);
4291                 phylink_set(mask, 2500baseX_Full);
4292         }
4293
4294         bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
4295         bitmap_and(state->advertising, state->advertising, mask,
4296                    __ETHTOOL_LINK_MODE_MASK_NBITS);
4297 }
4298
4299 static void mvpp22_xlg_link_state(struct mvpp2_port *port,
4300                                   struct phylink_link_state *state)
4301 {
4302         u32 val;
4303
4304         state->speed = SPEED_10000;
4305         state->duplex = 1;
4306         state->an_complete = 1;
4307
4308         val = readl(port->base + MVPP22_XLG_STATUS);
4309         state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP);
4310
4311         state->pause = 0;
4312         val = readl(port->base + MVPP22_XLG_CTRL0_REG);
4313         if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN)
4314                 state->pause |= MLO_PAUSE_TX;
4315         if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN)
4316                 state->pause |= MLO_PAUSE_RX;
4317 }
4318
4319 static void mvpp2_gmac_link_state(struct mvpp2_port *port,
4320                                   struct phylink_link_state *state)
4321 {
4322         u32 val;
4323
4324         val = readl(port->base + MVPP2_GMAC_STATUS0);
4325
4326         state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE);
4327         state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP);
4328         state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX);
4329
4330         switch (port->phy_interface) {
4331         case PHY_INTERFACE_MODE_1000BASEX:
4332                 state->speed = SPEED_1000;
4333                 break;
4334         case PHY_INTERFACE_MODE_2500BASEX:
4335                 state->speed = SPEED_2500;
4336                 break;
4337         default:
4338                 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
4339                         state->speed = SPEED_1000;
4340                 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
4341                         state->speed = SPEED_100;
4342                 else
4343                         state->speed = SPEED_10;
4344         }
4345
4346         state->pause = 0;
4347         if (val & MVPP2_GMAC_STATUS0_RX_PAUSE)
4348                 state->pause |= MLO_PAUSE_RX;
4349         if (val & MVPP2_GMAC_STATUS0_TX_PAUSE)
4350                 state->pause |= MLO_PAUSE_TX;
4351 }
4352
4353 static int mvpp2_phylink_mac_link_state(struct net_device *dev,
4354                                         struct phylink_link_state *state)
4355 {
4356         struct mvpp2_port *port = netdev_priv(dev);
4357
4358         if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
4359                 u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG);
4360                 mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
4361
4362                 if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) {
4363                         mvpp22_xlg_link_state(port, state);
4364                         return 1;
4365                 }
4366         }
4367
4368         mvpp2_gmac_link_state(port, state);
4369         return 1;
4370 }
4371
4372 static void mvpp2_mac_an_restart(struct net_device *dev)
4373 {
4374         struct mvpp2_port *port = netdev_priv(dev);
4375         u32 val;
4376
4377         if (port->phy_interface != PHY_INTERFACE_MODE_SGMII)
4378                 return;
4379
4380         val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4381         /* The RESTART_AN bit is cleared by the h/w after restarting the AN
4382          * process.
4383          */
4384         val |= MVPP2_GMAC_IN_BAND_RESTART_AN | MVPP2_GMAC_IN_BAND_AUTONEG;
4385         writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4386 }
4387
4388 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
4389                              const struct phylink_link_state *state)
4390 {
4391         u32 ctrl0, ctrl4;
4392
4393         ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG);
4394         ctrl4 = readl(port->base + MVPP22_XLG_CTRL4_REG);
4395
4396         if (state->pause & MLO_PAUSE_TX)
4397                 ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
4398         if (state->pause & MLO_PAUSE_RX)
4399                 ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
4400
4401         ctrl4 &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC;
4402         ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC |
4403                  MVPP22_XLG_CTRL4_EN_IDLE_CHECK;
4404
4405         writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG);
4406         writel(ctrl4, port->base + MVPP22_XLG_CTRL4_REG);
4407 }
4408
4409 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
4410                               const struct phylink_link_state *state)
4411 {
4412         u32 an, ctrl0, ctrl2, ctrl4;
4413
4414         an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4415         ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
4416         ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
4417         ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
4418
4419         /* Force link down */
4420         an &= ~MVPP2_GMAC_FORCE_LINK_PASS;
4421         an |= MVPP2_GMAC_FORCE_LINK_DOWN;
4422         writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4423
4424         /* Set the GMAC in a reset state */
4425         ctrl2 |= MVPP2_GMAC_PORT_RESET_MASK;
4426         writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
4427
4428         an &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED |
4429                 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN |
4430                 MVPP2_GMAC_FC_ADV_ASM_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG |
4431                 MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_AN_DUPLEX_EN |
4432                 MVPP2_GMAC_FORCE_LINK_DOWN);
4433         ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
4434         ctrl2 &= ~(MVPP2_GMAC_PORT_RESET_MASK | MVPP2_GMAC_PCS_ENABLE_MASK);
4435
4436         if (state->interface == PHY_INTERFACE_MODE_1000BASEX ||
4437             state->interface == PHY_INTERFACE_MODE_2500BASEX) {
4438                 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can
4439                  * they negotiate duplex: they are always operating with a fixed
4440                  * speed of 1000/2500Mbps in full duplex, so force 1000/2500
4441                  * speed and full duplex here.
4442                  */
4443                 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK;
4444                 an |= MVPP2_GMAC_CONFIG_GMII_SPEED |
4445                       MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4446         } else if (!phy_interface_mode_is_rgmii(state->interface)) {
4447                 an |= MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG;
4448         }
4449
4450         if (state->duplex)
4451                 an |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4452         if (phylink_test(state->advertising, Pause))
4453                 an |= MVPP2_GMAC_FC_ADV_EN;
4454         if (phylink_test(state->advertising, Asym_Pause))
4455                 an |= MVPP2_GMAC_FC_ADV_ASM_EN;
4456
4457         if (state->interface == PHY_INTERFACE_MODE_SGMII ||
4458             state->interface == PHY_INTERFACE_MODE_1000BASEX ||
4459             state->interface == PHY_INTERFACE_MODE_2500BASEX) {
4460                 an |= MVPP2_GMAC_IN_BAND_AUTONEG;
4461                 ctrl2 |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK;
4462
4463                 ctrl4 &= ~(MVPP22_CTRL4_EXT_PIN_GMII_SEL |
4464                            MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN);
4465                 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
4466                          MVPP22_CTRL4_DP_CLK_SEL |
4467                          MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
4468
4469                 if (state->pause & MLO_PAUSE_TX)
4470                         ctrl4 |= MVPP22_CTRL4_TX_FC_EN;
4471                 if (state->pause & MLO_PAUSE_RX)
4472                         ctrl4 |= MVPP22_CTRL4_RX_FC_EN;
4473         } else if (phy_interface_mode_is_rgmii(state->interface)) {
4474                 an |= MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS;
4475
4476                 if (state->speed == SPEED_1000)
4477                         an |= MVPP2_GMAC_CONFIG_GMII_SPEED;
4478                 else if (state->speed == SPEED_100)
4479                         an |= MVPP2_GMAC_CONFIG_MII_SPEED;
4480
4481                 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL;
4482                 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |
4483                          MVPP22_CTRL4_SYNC_BYPASS_DIS |
4484                          MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
4485         }
4486
4487         writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG);
4488         writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
4489         writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG);
4490         writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4491 }
4492
4493 static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
4494                              const struct phylink_link_state *state)
4495 {
4496         struct mvpp2_port *port = netdev_priv(dev);
4497
4498         /* Check for invalid configuration */
4499         if (state->interface == PHY_INTERFACE_MODE_10GKR && port->gop_id != 0) {
4500                 netdev_err(dev, "Invalid mode on %s\n", dev->name);
4501                 return;
4502         }
4503
4504         /* Make sure the port is disabled when reconfiguring the mode */
4505         mvpp2_port_disable(port);
4506
4507         if (port->priv->hw_version == MVPP22 &&
4508             port->phy_interface != state->interface) {
4509                 port->phy_interface = state->interface;
4510
4511                 /* Reconfigure the serdes lanes */
4512                 phy_power_off(port->comphy);
4513                 mvpp22_mode_reconfigure(port);
4514         }
4515
4516         /* mac (re)configuration */
4517         if (state->interface == PHY_INTERFACE_MODE_10GKR)
4518                 mvpp2_xlg_config(port, mode, state);
4519         else if (phy_interface_mode_is_rgmii(state->interface) ||
4520                  state->interface == PHY_INTERFACE_MODE_SGMII ||
4521                  state->interface == PHY_INTERFACE_MODE_1000BASEX ||
4522                  state->interface == PHY_INTERFACE_MODE_2500BASEX)
4523                 mvpp2_gmac_config(port, mode, state);
4524
4525         if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK)
4526                 mvpp2_port_loopback_set(port, state);
4527
4528         mvpp2_port_enable(port);
4529 }
4530
4531 static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode,
4532                               phy_interface_t interface, struct phy_device *phy)
4533 {
4534         struct mvpp2_port *port = netdev_priv(dev);
4535         u32 val;
4536
4537         if (!phylink_autoneg_inband(mode) &&
4538             interface != PHY_INTERFACE_MODE_10GKR) {
4539                 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4540                 val &= ~MVPP2_GMAC_FORCE_LINK_DOWN;
4541                 if (phy_interface_mode_is_rgmii(interface))
4542                         val |= MVPP2_GMAC_FORCE_LINK_PASS;
4543                 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4544         }
4545
4546         mvpp2_port_enable(port);
4547
4548         mvpp2_egress_enable(port);
4549         mvpp2_ingress_enable(port);
4550         netif_tx_wake_all_queues(dev);
4551 }
4552
4553 static void mvpp2_mac_link_down(struct net_device *dev, unsigned int mode,
4554                                 phy_interface_t interface)
4555 {
4556         struct mvpp2_port *port = netdev_priv(dev);
4557         u32 val;
4558
4559         if (!phylink_autoneg_inband(mode) &&
4560             interface != PHY_INTERFACE_MODE_10GKR) {
4561                 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4562                 val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
4563                 val |= MVPP2_GMAC_FORCE_LINK_DOWN;
4564                 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4565         }
4566
4567         netif_tx_stop_all_queues(dev);
4568         mvpp2_egress_disable(port);
4569         mvpp2_ingress_disable(port);
4570
4571         /* When using link interrupts to notify phylink of a MAC state change,
4572          * we do not want the port to be disabled (we want to receive further
4573          * interrupts, to be notified when the port will have a link later).
4574          */
4575         if (!port->has_phy)
4576                 return;
4577
4578         mvpp2_port_disable(port);
4579 }
4580
4581 static const struct phylink_mac_ops mvpp2_phylink_ops = {
4582         .validate = mvpp2_phylink_validate,
4583         .mac_link_state = mvpp2_phylink_mac_link_state,
4584         .mac_an_restart = mvpp2_mac_an_restart,
4585         .mac_config = mvpp2_mac_config,
4586         .mac_link_up = mvpp2_mac_link_up,
4587         .mac_link_down = mvpp2_mac_link_down,
4588 };
4589
4590 /* Ports initialization */
4591 static int mvpp2_port_probe(struct platform_device *pdev,
4592                             struct fwnode_handle *port_fwnode,
4593                             struct mvpp2 *priv)
4594 {
4595         struct phy *comphy = NULL;
4596         struct mvpp2_port *port;
4597         struct mvpp2_port_pcpu *port_pcpu;
4598         struct device_node *port_node = to_of_node(port_fwnode);
4599         struct net_device *dev;
4600         struct resource *res;
4601         struct phylink *phylink;
4602         char *mac_from = "";
4603         unsigned int ntxqs, nrxqs;
4604         bool has_tx_irqs;
4605         u32 id;
4606         int features;
4607         int phy_mode;
4608         int err, i, cpu;
4609
4610         if (port_node) {
4611                 has_tx_irqs = mvpp2_port_has_tx_irqs(priv, port_node);
4612         } else {
4613                 has_tx_irqs = true;
4614                 queue_mode = MVPP2_QDIST_MULTI_MODE;
4615         }
4616
4617         if (!has_tx_irqs)
4618                 queue_mode = MVPP2_QDIST_SINGLE_MODE;
4619
4620         ntxqs = MVPP2_MAX_TXQ;
4621         if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_MULTI_MODE)
4622                 nrxqs = MVPP2_DEFAULT_RXQ * num_possible_cpus();
4623         else
4624                 nrxqs = MVPP2_DEFAULT_RXQ;
4625
4626         dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs);
4627         if (!dev)
4628                 return -ENOMEM;
4629
4630         phy_mode = fwnode_get_phy_mode(port_fwnode);
4631         if (phy_mode < 0) {
4632                 dev_err(&pdev->dev, "incorrect phy mode\n");
4633                 err = phy_mode;
4634                 goto err_free_netdev;
4635         }
4636
4637         if (port_node) {
4638                 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL);
4639                 if (IS_ERR(comphy)) {
4640                         if (PTR_ERR(comphy) == -EPROBE_DEFER) {
4641                                 err = -EPROBE_DEFER;
4642                                 goto err_free_netdev;
4643                         }
4644                         comphy = NULL;
4645                 }
4646         }
4647
4648         if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) {
4649                 err = -EINVAL;
4650                 dev_err(&pdev->dev, "missing port-id value\n");
4651                 goto err_free_netdev;
4652         }
4653
4654         dev->tx_queue_len = MVPP2_MAX_TXD_MAX;
4655         dev->watchdog_timeo = 5 * HZ;
4656         dev->netdev_ops = &mvpp2_netdev_ops;
4657         dev->ethtool_ops = &mvpp2_eth_tool_ops;
4658
4659         port = netdev_priv(dev);
4660         port->dev = dev;
4661         port->fwnode = port_fwnode;
4662         port->has_phy = !!of_find_property(port_node, "phy", NULL);
4663         port->ntxqs = ntxqs;
4664         port->nrxqs = nrxqs;
4665         port->priv = priv;
4666         port->has_tx_irqs = has_tx_irqs;
4667
4668         err = mvpp2_queue_vectors_init(port, port_node);
4669         if (err)
4670                 goto err_free_netdev;
4671
4672         if (port_node)
4673                 port->link_irq = of_irq_get_byname(port_node, "link");
4674         else
4675                 port->link_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1);
4676         if (port->link_irq == -EPROBE_DEFER) {
4677                 err = -EPROBE_DEFER;
4678                 goto err_deinit_qvecs;
4679         }
4680         if (port->link_irq <= 0)
4681                 /* the link irq is optional */
4682                 port->link_irq = 0;
4683
4684         if (fwnode_property_read_bool(port_fwnode, "marvell,loopback"))
4685                 port->flags |= MVPP2_F_LOOPBACK;
4686
4687         port->id = id;
4688         if (priv->hw_version == MVPP21)
4689                 port->first_rxq = port->id * port->nrxqs;
4690         else
4691                 port->first_rxq = port->id * priv->max_port_rxqs;
4692
4693         port->of_node = port_node;
4694         port->phy_interface = phy_mode;
4695         port->comphy = comphy;
4696
4697         if (priv->hw_version == MVPP21) {
4698                 res = platform_get_resource(pdev, IORESOURCE_MEM, 2 + id);
4699                 port->base = devm_ioremap_resource(&pdev->dev, res);
4700                 if (IS_ERR(port->base)) {
4701                         err = PTR_ERR(port->base);
4702                         goto err_free_irq;
4703                 }
4704
4705                 port->stats_base = port->priv->lms_base +
4706                                    MVPP21_MIB_COUNTERS_OFFSET +
4707                                    port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ;
4708         } else {
4709                 if (fwnode_property_read_u32(port_fwnode, "gop-port-id",
4710                                              &port->gop_id)) {
4711                         err = -EINVAL;
4712                         dev_err(&pdev->dev, "missing gop-port-id value\n");
4713                         goto err_deinit_qvecs;
4714                 }
4715
4716                 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id);
4717                 port->stats_base = port->priv->iface_base +
4718                                    MVPP22_MIB_COUNTERS_OFFSET +
4719                                    port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ;
4720         }
4721
4722         /* Alloc per-cpu and ethtool stats */
4723         port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);
4724         if (!port->stats) {
4725                 err = -ENOMEM;
4726                 goto err_free_irq;
4727         }
4728
4729         port->ethtool_stats = devm_kcalloc(&pdev->dev,
4730                                            ARRAY_SIZE(mvpp2_ethtool_regs),
4731                                            sizeof(u64), GFP_KERNEL);
4732         if (!port->ethtool_stats) {
4733                 err = -ENOMEM;
4734                 goto err_free_stats;
4735         }
4736
4737         mutex_init(&port->gather_stats_lock);
4738         INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics);
4739
4740         mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from);
4741
4742         port->tx_ring_size = MVPP2_MAX_TXD_DFLT;
4743         port->rx_ring_size = MVPP2_MAX_RXD_DFLT;
4744         SET_NETDEV_DEV(dev, &pdev->dev);
4745
4746         err = mvpp2_port_init(port);
4747         if (err < 0) {
4748                 dev_err(&pdev->dev, "failed to init port %d\n", id);
4749                 goto err_free_stats;
4750         }
4751
4752         mvpp2_port_periodic_xon_disable(port);
4753
4754         mvpp2_port_reset(port);
4755
4756         port->pcpu = alloc_percpu(struct mvpp2_port_pcpu);
4757         if (!port->pcpu) {
4758                 err = -ENOMEM;
4759                 goto err_free_txq_pcpu;
4760         }
4761
4762         if (!port->has_tx_irqs) {
4763                 for_each_present_cpu(cpu) {
4764                         port_pcpu = per_cpu_ptr(port->pcpu, cpu);
4765
4766                         hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC,
4767                                      HRTIMER_MODE_REL_PINNED);
4768                         port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb;
4769                         port_pcpu->timer_scheduled = false;
4770
4771                         tasklet_init(&port_pcpu->tx_done_tasklet,
4772                                      mvpp2_tx_proc_cb,
4773                                      (unsigned long)dev);
4774                 }
4775         }
4776
4777         features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4778                    NETIF_F_TSO;
4779         dev->features = features | NETIF_F_RXCSUM;
4780         dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO |
4781                             NETIF_F_HW_VLAN_CTAG_FILTER;
4782
4783         if (mvpp22_rss_is_supported())
4784                 dev->hw_features |= NETIF_F_RXHASH;
4785
4786         if (port->pool_long->id == MVPP2_BM_JUMBO && port->id != 0) {
4787                 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
4788                 dev->hw_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
4789         }
4790
4791         dev->vlan_features |= features;
4792         dev->gso_max_segs = MVPP2_MAX_TSO_SEGS;
4793         dev->priv_flags |= IFF_UNICAST_FLT;
4794
4795         /* MTU range: 68 - 9704 */
4796         dev->min_mtu = ETH_MIN_MTU;
4797         /* 9704 == 9728 - 20 and rounding to 8 */
4798         dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE;
4799         dev->dev.of_node = port_node;
4800
4801         /* Phylink isn't used w/ ACPI as of now */
4802         if (port_node) {
4803                 phylink = phylink_create(dev, port_fwnode, phy_mode,
4804                                          &mvpp2_phylink_ops);
4805                 if (IS_ERR(phylink)) {
4806                         err = PTR_ERR(phylink);
4807                         goto err_free_port_pcpu;
4808                 }
4809                 port->phylink = phylink;
4810         } else {
4811                 port->phylink = NULL;
4812         }
4813
4814         err = register_netdev(dev);
4815         if (err < 0) {
4816                 dev_err(&pdev->dev, "failed to register netdev\n");
4817                 goto err_phylink;
4818         }
4819         netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
4820
4821         priv->port_list[priv->port_count++] = port;
4822
4823         return 0;
4824
4825 err_phylink:
4826         if (port->phylink)
4827                 phylink_destroy(port->phylink);
4828 err_free_port_pcpu:
4829         free_percpu(port->pcpu);
4830 err_free_txq_pcpu:
4831         for (i = 0; i < port->ntxqs; i++)
4832                 free_percpu(port->txqs[i]->pcpu);
4833 err_free_stats:
4834         free_percpu(port->stats);
4835 err_free_irq:
4836         if (port->link_irq)
4837                 irq_dispose_mapping(port->link_irq);
4838 err_deinit_qvecs:
4839         mvpp2_queue_vectors_deinit(port);
4840 err_free_netdev:
4841         free_netdev(dev);
4842         return err;
4843 }
4844
4845 /* Ports removal routine */
4846 static void mvpp2_port_remove(struct mvpp2_port *port)
4847 {
4848         int i;
4849
4850         unregister_netdev(port->dev);
4851         if (port->phylink)
4852                 phylink_destroy(port->phylink);
4853         free_percpu(port->pcpu);
4854         free_percpu(port->stats);
4855         for (i = 0; i < port->ntxqs; i++)
4856                 free_percpu(port->txqs[i]->pcpu);
4857         mvpp2_queue_vectors_deinit(port);
4858         if (port->link_irq)
4859                 irq_dispose_mapping(port->link_irq);
4860         free_netdev(port->dev);
4861 }
4862
4863 /* Initialize decoding windows */
4864 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
4865                                     struct mvpp2 *priv)
4866 {
4867         u32 win_enable;
4868         int i;
4869
4870         for (i = 0; i < 6; i++) {
4871                 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
4872                 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
4873
4874                 if (i < 4)
4875                         mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
4876         }
4877
4878         win_enable = 0;
4879
4880         for (i = 0; i < dram->num_cs; i++) {
4881                 const struct mbus_dram_window *cs = dram->cs + i;
4882
4883                 mvpp2_write(priv, MVPP2_WIN_BASE(i),
4884                             (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
4885                             dram->mbus_dram_target_id);
4886
4887                 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
4888                             (cs->size - 1) & 0xffff0000);
4889
4890                 win_enable |= (1 << i);
4891         }
4892
4893         mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
4894 }
4895
4896 /* Initialize Rx FIFO's */
4897 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
4898 {
4899         int port;
4900
4901         for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4902                 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4903                             MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
4904                 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4905                             MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
4906         }
4907
4908         mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
4909                     MVPP2_RX_FIFO_PORT_MIN_PKT);
4910         mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
4911 }
4912
4913 static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
4914 {
4915         int port;
4916
4917         /* The FIFO size parameters are set depending on the maximum speed a
4918          * given port can handle:
4919          * - Port 0: 10Gbps
4920          * - Port 1: 2.5Gbps
4921          * - Ports 2 and 3: 1Gbps
4922          */
4923
4924         mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0),
4925                     MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB);
4926         mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0),
4927                     MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB);
4928
4929         mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1),
4930                     MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB);
4931         mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1),
4932                     MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB);
4933
4934         for (port = 2; port < MVPP2_MAX_PORTS; port++) {
4935                 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
4936                             MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
4937                 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
4938                             MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
4939         }
4940
4941         mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
4942                     MVPP2_RX_FIFO_PORT_MIN_PKT);
4943         mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
4944 }
4945
4946 /* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G
4947  * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G,
4948  * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB.
4949  */
4950 static void mvpp22_tx_fifo_init(struct mvpp2 *priv)
4951 {
4952         int port, size, thrs;
4953
4954         for (port = 0; port < MVPP2_MAX_PORTS; port++) {
4955                 if (port == 0) {
4956                         size = MVPP22_TX_FIFO_DATA_SIZE_10KB;
4957                         thrs = MVPP2_TX_FIFO_THRESHOLD_10KB;
4958                 } else {
4959                         size = MVPP22_TX_FIFO_DATA_SIZE_3KB;
4960                         thrs = MVPP2_TX_FIFO_THRESHOLD_3KB;
4961                 }
4962                 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size);
4963                 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs);
4964         }
4965 }
4966
4967 static void mvpp2_axi_init(struct mvpp2 *priv)
4968 {
4969         u32 val, rdval, wrval;
4970
4971         mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
4972
4973         /* AXI Bridge Configuration */
4974
4975         rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
4976                 << MVPP22_AXI_ATTR_CACHE_OFFS;
4977         rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4978                 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4979
4980         wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
4981                 << MVPP22_AXI_ATTR_CACHE_OFFS;
4982         wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
4983                 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
4984
4985         /* BM */
4986         mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
4987         mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
4988
4989         /* Descriptors */
4990         mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
4991         mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
4992         mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
4993         mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
4994
4995         /* Buffer Data */
4996         mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
4997         mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
4998
4999         val = MVPP22_AXI_CODE_CACHE_NON_CACHE
5000                 << MVPP22_AXI_CODE_CACHE_OFFS;
5001         val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
5002                 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5003         mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
5004         mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
5005
5006         val = MVPP22_AXI_CODE_CACHE_RD_CACHE
5007                 << MVPP22_AXI_CODE_CACHE_OFFS;
5008         val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5009                 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5010
5011         mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
5012
5013         val = MVPP22_AXI_CODE_CACHE_WR_CACHE
5014                 << MVPP22_AXI_CODE_CACHE_OFFS;
5015         val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5016                 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5017
5018         mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
5019 }
5020
5021 /* Initialize network controller common part HW */
5022 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
5023 {
5024         const struct mbus_dram_target_info *dram_target_info;
5025         int err, i;
5026         u32 val;
5027
5028         /* MBUS windows configuration */
5029         dram_target_info = mv_mbus_dram_info();
5030         if (dram_target_info)
5031                 mvpp2_conf_mbus_windows(dram_target_info, priv);
5032
5033         if (priv->hw_version == MVPP22)
5034                 mvpp2_axi_init(priv);
5035
5036         /* Disable HW PHY polling */
5037         if (priv->hw_version == MVPP21) {
5038                 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5039                 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
5040                 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5041         } else {
5042                 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5043                 val &= ~MVPP22_SMI_POLLING_EN;
5044                 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5045         }
5046
5047         /* Allocate and initialize aggregated TXQs */
5048         priv->aggr_txqs = devm_kcalloc(&pdev->dev, num_present_cpus(),
5049                                        sizeof(*priv->aggr_txqs),
5050                                        GFP_KERNEL);
5051         if (!priv->aggr_txqs)
5052                 return -ENOMEM;
5053
5054         for_each_present_cpu(i) {
5055                 priv->aggr_txqs[i].id = i;
5056                 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
5057                 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv);
5058                 if (err < 0)
5059                         return err;
5060         }
5061
5062         /* Fifo Init */
5063         if (priv->hw_version == MVPP21) {
5064                 mvpp2_rx_fifo_init(priv);
5065         } else {
5066                 mvpp22_rx_fifo_init(priv);
5067                 mvpp22_tx_fifo_init(priv);
5068         }
5069
5070         if (priv->hw_version == MVPP21)
5071                 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
5072                        priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
5073
5074         /* Allow cache snoop when transmiting packets */
5075         mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
5076
5077         /* Buffer Manager initialization */
5078         err = mvpp2_bm_init(pdev, priv);
5079         if (err < 0)
5080                 return err;
5081
5082         /* Parser default initialization */
5083         err = mvpp2_prs_default_init(pdev, priv);
5084         if (err < 0)
5085                 return err;
5086
5087         /* Classifier default initialization */
5088         mvpp2_cls_init(priv);
5089
5090         return 0;
5091 }
5092
5093 static int mvpp2_probe(struct platform_device *pdev)
5094 {
5095         const struct acpi_device_id *acpi_id;
5096         struct fwnode_handle *fwnode = pdev->dev.fwnode;
5097         struct fwnode_handle *port_fwnode;
5098         struct mvpp2 *priv;
5099         struct resource *res;
5100         void __iomem *base;
5101         int i;
5102         int err;
5103
5104         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
5105         if (!priv)
5106                 return -ENOMEM;
5107
5108         if (has_acpi_companion(&pdev->dev)) {
5109                 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
5110                                             &pdev->dev);
5111                 priv->hw_version = (unsigned long)acpi_id->driver_data;
5112         } else {
5113                 priv->hw_version =
5114                         (unsigned long)of_device_get_match_data(&pdev->dev);
5115         }
5116
5117         /* multi queue mode isn't supported on PPV2.1, fallback to single
5118          * mode
5119          */
5120         if (priv->hw_version == MVPP21)
5121                 queue_mode = MVPP2_QDIST_SINGLE_MODE;
5122
5123         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5124         base = devm_ioremap_resource(&pdev->dev, res);
5125         if (IS_ERR(base))
5126                 return PTR_ERR(base);
5127
5128         if (priv->hw_version == MVPP21) {
5129                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
5130                 priv->lms_base = devm_ioremap_resource(&pdev->dev, res);
5131                 if (IS_ERR(priv->lms_base))
5132                         return PTR_ERR(priv->lms_base);
5133         } else {
5134                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
5135                 if (has_acpi_companion(&pdev->dev)) {
5136                         /* In case the MDIO memory region is declared in
5137                          * the ACPI, it can already appear as 'in-use'
5138                          * in the OS. Because it is overlapped by second
5139                          * region of the network controller, make
5140                          * sure it is released, before requesting it again.
5141                          * The care is taken by mvpp2 driver to avoid
5142                          * concurrent access to this memory region.
5143                          */
5144                         release_resource(res);
5145                 }
5146                 priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
5147                 if (IS_ERR(priv->iface_base))
5148                         return PTR_ERR(priv->iface_base);
5149         }
5150
5151         if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) {
5152                 priv->sysctrl_base =
5153                         syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
5154                                                         "marvell,system-controller");
5155                 if (IS_ERR(priv->sysctrl_base))
5156                         /* The system controller regmap is optional for dt
5157                          * compatibility reasons. When not provided, the
5158                          * configuration of the GoP relies on the
5159                          * firmware/bootloader.
5160                          */
5161                         priv->sysctrl_base = NULL;
5162         }
5163
5164         mvpp2_setup_bm_pool();
5165
5166         for (i = 0; i < MVPP2_MAX_THREADS; i++) {
5167                 u32 addr_space_sz;
5168
5169                 addr_space_sz = (priv->hw_version == MVPP21 ?
5170                                  MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ);
5171                 priv->swth_base[i] = base + i * addr_space_sz;
5172         }
5173
5174         if (priv->hw_version == MVPP21)
5175                 priv->max_port_rxqs = 8;
5176         else
5177                 priv->max_port_rxqs = 32;
5178
5179         if (dev_of_node(&pdev->dev)) {
5180                 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
5181                 if (IS_ERR(priv->pp_clk))
5182                         return PTR_ERR(priv->pp_clk);
5183                 err = clk_prepare_enable(priv->pp_clk);
5184                 if (err < 0)
5185                         return err;
5186
5187                 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
5188                 if (IS_ERR(priv->gop_clk)) {
5189                         err = PTR_ERR(priv->gop_clk);
5190                         goto err_pp_clk;
5191                 }
5192                 err = clk_prepare_enable(priv->gop_clk);
5193                 if (err < 0)
5194                         goto err_pp_clk;
5195
5196                 if (priv->hw_version == MVPP22) {
5197                         priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
5198                         if (IS_ERR(priv->mg_clk)) {
5199                                 err = PTR_ERR(priv->mg_clk);
5200                                 goto err_gop_clk;
5201                         }
5202
5203                         err = clk_prepare_enable(priv->mg_clk);
5204                         if (err < 0)
5205                                 goto err_gop_clk;
5206
5207                         priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk");
5208                         if (IS_ERR(priv->mg_core_clk)) {
5209                                 priv->mg_core_clk = NULL;
5210                         } else {
5211                                 err = clk_prepare_enable(priv->mg_core_clk);
5212                                 if (err < 0)
5213                                         goto err_mg_clk;
5214                         }
5215                 }
5216
5217                 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk");
5218                 if (IS_ERR(priv->axi_clk)) {
5219                         err = PTR_ERR(priv->axi_clk);
5220                         if (err == -EPROBE_DEFER)
5221                                 goto err_mg_core_clk;
5222                         priv->axi_clk = NULL;
5223                 } else {
5224                         err = clk_prepare_enable(priv->axi_clk);
5225                         if (err < 0)
5226                                 goto err_mg_core_clk;
5227                 }
5228
5229                 /* Get system's tclk rate */
5230                 priv->tclk = clk_get_rate(priv->pp_clk);
5231         } else if (device_property_read_u32(&pdev->dev, "clock-frequency",
5232                                             &priv->tclk)) {
5233                 dev_err(&pdev->dev, "missing clock-frequency value\n");
5234                 return -EINVAL;
5235         }
5236
5237         if (priv->hw_version == MVPP22) {
5238                 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
5239                 if (err)
5240                         goto err_axi_clk;
5241                 /* Sadly, the BM pools all share the same register to
5242                  * store the high 32 bits of their address. So they
5243                  * must all have the same high 32 bits, which forces
5244                  * us to restrict coherent memory to DMA_BIT_MASK(32).
5245                  */
5246                 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
5247                 if (err)
5248                         goto err_axi_clk;
5249         }
5250
5251         /* Initialize network controller */
5252         err = mvpp2_init(pdev, priv);
5253         if (err < 0) {
5254                 dev_err(&pdev->dev, "failed to initialize controller\n");
5255                 goto err_axi_clk;
5256         }
5257
5258         /* Initialize ports */
5259         fwnode_for_each_available_child_node(fwnode, port_fwnode) {
5260                 err = mvpp2_port_probe(pdev, port_fwnode, priv);
5261                 if (err < 0)
5262                         goto err_port_probe;
5263         }
5264
5265         if (priv->port_count == 0) {
5266                 dev_err(&pdev->dev, "no ports enabled\n");
5267                 err = -ENODEV;
5268                 goto err_axi_clk;
5269         }
5270
5271         /* Statistics must be gathered regularly because some of them (like
5272          * packets counters) are 32-bit registers and could overflow quite
5273          * quickly. For instance, a 10Gb link used at full bandwidth with the
5274          * smallest packets (64B) will overflow a 32-bit counter in less than
5275          * 30 seconds. Then, use a workqueue to fill 64-bit counters.
5276          */
5277         snprintf(priv->queue_name, sizeof(priv->queue_name),
5278                  "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev),
5279                  priv->port_count > 1 ? "+" : "");
5280         priv->stats_queue = create_singlethread_workqueue(priv->queue_name);
5281         if (!priv->stats_queue) {
5282                 err = -ENOMEM;
5283                 goto err_port_probe;
5284         }
5285
5286         mvpp2_dbgfs_init(priv, pdev->name);
5287
5288         platform_set_drvdata(pdev, priv);
5289         return 0;
5290
5291 err_port_probe:
5292         i = 0;
5293         fwnode_for_each_available_child_node(fwnode, port_fwnode) {
5294                 if (priv->port_list[i])
5295                         mvpp2_port_remove(priv->port_list[i]);
5296                 i++;
5297         }
5298 err_axi_clk:
5299         clk_disable_unprepare(priv->axi_clk);
5300
5301 err_mg_core_clk:
5302         if (priv->hw_version == MVPP22)
5303                 clk_disable_unprepare(priv->mg_core_clk);
5304 err_mg_clk:
5305         if (priv->hw_version == MVPP22)
5306                 clk_disable_unprepare(priv->mg_clk);
5307 err_gop_clk:
5308         clk_disable_unprepare(priv->gop_clk);
5309 err_pp_clk:
5310         clk_disable_unprepare(priv->pp_clk);
5311         return err;
5312 }
5313
5314 static int mvpp2_remove(struct platform_device *pdev)
5315 {
5316         struct mvpp2 *priv = platform_get_drvdata(pdev);
5317         struct fwnode_handle *fwnode = pdev->dev.fwnode;
5318         struct fwnode_handle *port_fwnode;
5319         int i = 0;
5320
5321         mvpp2_dbgfs_cleanup(priv);
5322
5323         flush_workqueue(priv->stats_queue);
5324         destroy_workqueue(priv->stats_queue);
5325
5326         fwnode_for_each_available_child_node(fwnode, port_fwnode) {
5327                 if (priv->port_list[i]) {
5328                         mutex_destroy(&priv->port_list[i]->gather_stats_lock);
5329                         mvpp2_port_remove(priv->port_list[i]);
5330                 }
5331                 i++;
5332         }
5333
5334         for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
5335                 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i];
5336
5337                 mvpp2_bm_pool_destroy(pdev, priv, bm_pool);
5338         }
5339
5340         for_each_present_cpu(i) {
5341                 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i];
5342
5343                 dma_free_coherent(&pdev->dev,
5344                                   MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
5345                                   aggr_txq->descs,
5346                                   aggr_txq->descs_dma);
5347         }
5348
5349         if (is_acpi_node(port_fwnode))
5350                 return 0;
5351
5352         clk_disable_unprepare(priv->axi_clk);
5353         clk_disable_unprepare(priv->mg_core_clk);
5354         clk_disable_unprepare(priv->mg_clk);
5355         clk_disable_unprepare(priv->pp_clk);
5356         clk_disable_unprepare(priv->gop_clk);
5357
5358         return 0;
5359 }
5360
5361 static const struct of_device_id mvpp2_match[] = {
5362         {
5363                 .compatible = "marvell,armada-375-pp2",
5364                 .data = (void *)MVPP21,
5365         },
5366         {
5367                 .compatible = "marvell,armada-7k-pp22",
5368                 .data = (void *)MVPP22,
5369         },
5370         { }
5371 };
5372 MODULE_DEVICE_TABLE(of, mvpp2_match);
5373
5374 static const struct acpi_device_id mvpp2_acpi_match[] = {
5375         { "MRVL0110", MVPP22 },
5376         { },
5377 };
5378 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match);
5379
5380 static struct platform_driver mvpp2_driver = {
5381         .probe = mvpp2_probe,
5382         .remove = mvpp2_remove,
5383         .driver = {
5384                 .name = MVPP2_DRIVER_NAME,
5385                 .of_match_table = mvpp2_match,
5386                 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match),
5387         },
5388 };
5389
5390 module_platform_driver(mvpp2_driver);
5391
5392 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
5393 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
5394 MODULE_LICENSE("GPL v2");