2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/cpu.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_vlan.h>
18 #include <linux/inetdevice.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mbus.h>
23 #include <linux/module.h>
24 #include <linux/netdevice.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_mdio.h>
29 #include <linux/of_net.h>
30 #include <linux/phy.h>
31 #include <linux/platform_device.h>
32 #include <linux/skbuff.h>
34 #include "mvneta_bm.h"
40 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
41 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0)
42 #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4
43 #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30
44 #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6
45 #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0
46 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
47 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
48 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
49 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
50 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
51 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
52 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
53 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
54 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
55 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
56 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
57 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
58 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
59 #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2))
60 #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3
61 #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8
62 #define MVNETA_PORT_RX_RESET 0x1cc0
63 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
64 #define MVNETA_PHY_ADDR 0x2000
65 #define MVNETA_PHY_ADDR_MASK 0x1f
66 #define MVNETA_MBUS_RETRY 0x2010
67 #define MVNETA_UNIT_INTR_CAUSE 0x2080
68 #define MVNETA_UNIT_CONTROL 0x20B0
69 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
70 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
71 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
72 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
73 #define MVNETA_BASE_ADDR_ENABLE 0x2290
74 #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294
75 #define MVNETA_PORT_CONFIG 0x2400
76 #define MVNETA_UNI_PROMISC_MODE BIT(0)
77 #define MVNETA_DEF_RXQ(q) ((q) << 1)
78 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
79 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
80 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
81 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
82 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
83 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
84 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
85 MVNETA_DEF_RXQ_ARP(q) | \
86 MVNETA_DEF_RXQ_TCP(q) | \
87 MVNETA_DEF_RXQ_UDP(q) | \
88 MVNETA_DEF_RXQ_BPDU(q) | \
89 MVNETA_TX_UNSET_ERR_SUM | \
90 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
91 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
92 #define MVNETA_MAC_ADDR_LOW 0x2414
93 #define MVNETA_MAC_ADDR_HIGH 0x2418
94 #define MVNETA_SDMA_CONFIG 0x241c
95 #define MVNETA_SDMA_BRST_SIZE_16 4
96 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
97 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
98 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
99 #define MVNETA_DESC_SWAP BIT(6)
100 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
101 #define MVNETA_PORT_STATUS 0x2444
102 #define MVNETA_TX_IN_PRGRS BIT(1)
103 #define MVNETA_TX_FIFO_EMPTY BIT(8)
104 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
105 #define MVNETA_SERDES_CFG 0x24A0
106 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
107 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
108 #define MVNETA_TYPE_PRIO 0x24bc
109 #define MVNETA_FORCE_UNI BIT(21)
110 #define MVNETA_TXQ_CMD_1 0x24e4
111 #define MVNETA_TXQ_CMD 0x2448
112 #define MVNETA_TXQ_DISABLE_SHIFT 8
113 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
114 #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484
115 #define MVNETA_OVERRUN_FRAME_COUNT 0x2488
116 #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
117 #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
118 #define MVNETA_ACC_MODE 0x2500
119 #define MVNETA_BM_ADDRESS 0x2504
120 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
121 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
122 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
123 #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq)
124 #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8)
125 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
127 /* Exception Interrupt Port/Queue Cause register
129 * Their behavior depend of the mapping done using the PCPX2Q
130 * registers. For a given CPU if the bit associated to a queue is not
131 * set, then for the register a read from this CPU will always return
132 * 0 and a write won't do anything
135 #define MVNETA_INTR_NEW_CAUSE 0x25a0
136 #define MVNETA_INTR_NEW_MASK 0x25a4
138 /* bits 0..7 = TXQ SENT, one bit per queue.
139 * bits 8..15 = RXQ OCCUP, one bit per queue.
140 * bits 16..23 = RXQ FREE, one bit per queue.
141 * bit 29 = OLD_REG_SUM, see old reg ?
142 * bit 30 = TX_ERR_SUM, one bit for 4 ports
143 * bit 31 = MISC_SUM, one bit for 4 ports
145 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
146 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
147 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
148 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
149 #define MVNETA_MISCINTR_INTR_MASK BIT(31)
151 #define MVNETA_INTR_OLD_CAUSE 0x25a8
152 #define MVNETA_INTR_OLD_MASK 0x25ac
154 /* Data Path Port/Queue Cause Register */
155 #define MVNETA_INTR_MISC_CAUSE 0x25b0
156 #define MVNETA_INTR_MISC_MASK 0x25b4
158 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
159 #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
160 #define MVNETA_CAUSE_PTP BIT(4)
162 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
163 #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
164 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
165 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
166 #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
167 #define MVNETA_CAUSE_PRBS_ERR BIT(12)
168 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
169 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
171 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
172 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
173 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
175 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
176 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
177 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
179 #define MVNETA_INTR_ENABLE 0x25b8
180 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
181 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff
183 #define MVNETA_RXQ_CMD 0x2680
184 #define MVNETA_RXQ_DISABLE_SHIFT 8
185 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
186 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
187 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
188 #define MVNETA_GMAC_CTRL_0 0x2c00
189 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
190 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
191 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
192 #define MVNETA_GMAC_CTRL_2 0x2c08
193 #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
194 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
195 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
196 #define MVNETA_GMAC2_PORT_RESET BIT(6)
197 #define MVNETA_GMAC_STATUS 0x2c10
198 #define MVNETA_GMAC_LINK_UP BIT(0)
199 #define MVNETA_GMAC_SPEED_1000 BIT(1)
200 #define MVNETA_GMAC_SPEED_100 BIT(2)
201 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
202 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
203 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
204 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
205 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
206 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
207 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
208 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
209 #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
210 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
211 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
212 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
213 #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
214 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
215 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
216 #define MVNETA_MIB_COUNTERS_BASE 0x3000
217 #define MVNETA_MIB_LATE_COLLISION 0x7c
218 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
219 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
220 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
221 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
222 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
223 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
224 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
225 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
226 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
227 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
228 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
229 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
230 #define MVNETA_PORT_TX_RESET 0x3cf0
231 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
232 #define MVNETA_TX_MTU 0x3e0c
233 #define MVNETA_TX_TOKEN_SIZE 0x3e14
234 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
235 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
236 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
238 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
240 /* Descriptor ring Macros */
241 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
242 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
244 /* Various constants */
247 #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */
248 #define MVNETA_RX_COAL_PKTS 32
249 #define MVNETA_RX_COAL_USEC 100
251 /* The two bytes Marvell header. Either contains a special value used
252 * by Marvell switches when a specific hardware mode is enabled (not
253 * supported by this driver) or is filled automatically by zeroes on
254 * the RX side. Those two bytes being at the front of the Ethernet
255 * header, they allow to have the IP header aligned on a 4 bytes
256 * boundary automatically: the hardware skips those two bytes on its
259 #define MVNETA_MH_SIZE 2
261 #define MVNETA_VLAN_TAG_LEN 4
263 #define MVNETA_TX_CSUM_DEF_SIZE 1600
264 #define MVNETA_TX_CSUM_MAX_SIZE 9800
265 #define MVNETA_ACC_MODE_EXT1 1
266 #define MVNETA_ACC_MODE_EXT2 2
268 #define MVNETA_MAX_DECODE_WIN 6
270 /* Timeout constants */
271 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
272 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
273 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
275 #define MVNETA_TX_MTU_MAX 0x3ffff
277 /* The RSS lookup table actually has 256 entries but we do not use
280 #define MVNETA_RSS_LU_TABLE_SIZE 1
282 /* TSO header size */
283 #define TSO_HEADER_SIZE 128
285 /* Max number of Rx descriptors */
286 #define MVNETA_MAX_RXD 128
288 /* Max number of Tx descriptors */
289 #define MVNETA_MAX_TXD 532
291 /* Max number of allowed TCP segments for software TSO */
292 #define MVNETA_MAX_TSO_SEGS 100
294 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
296 /* descriptor aligned size */
297 #define MVNETA_DESC_ALIGNED_SIZE 32
299 /* Number of bytes to be taken into account by HW when putting incoming data
300 * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet
301 * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers.
303 #define MVNETA_RX_PKT_OFFSET_CORRECTION 64
305 #define MVNETA_RX_PKT_SIZE(mtu) \
306 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
307 ETH_HLEN + ETH_FCS_LEN, \
310 #define IS_TSO_HEADER(txq, addr) \
311 ((addr >= txq->tso_hdrs_phys) && \
312 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
314 #define MVNETA_RX_GET_BM_POOL_ID(rxd) \
315 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
317 struct mvneta_statistic {
318 unsigned short offset;
320 const char name[ETH_GSTRING_LEN];
326 static const struct mvneta_statistic mvneta_statistics[] = {
327 { 0x3000, T_REG_64, "good_octets_received", },
328 { 0x3010, T_REG_32, "good_frames_received", },
329 { 0x3008, T_REG_32, "bad_octets_received", },
330 { 0x3014, T_REG_32, "bad_frames_received", },
331 { 0x3018, T_REG_32, "broadcast_frames_received", },
332 { 0x301c, T_REG_32, "multicast_frames_received", },
333 { 0x3050, T_REG_32, "unrec_mac_control_received", },
334 { 0x3058, T_REG_32, "good_fc_received", },
335 { 0x305c, T_REG_32, "bad_fc_received", },
336 { 0x3060, T_REG_32, "undersize_received", },
337 { 0x3064, T_REG_32, "fragments_received", },
338 { 0x3068, T_REG_32, "oversize_received", },
339 { 0x306c, T_REG_32, "jabber_received", },
340 { 0x3070, T_REG_32, "mac_receive_error", },
341 { 0x3074, T_REG_32, "bad_crc_event", },
342 { 0x3078, T_REG_32, "collision", },
343 { 0x307c, T_REG_32, "late_collision", },
344 { 0x2484, T_REG_32, "rx_discard", },
345 { 0x2488, T_REG_32, "rx_overrun", },
346 { 0x3020, T_REG_32, "frames_64_octets", },
347 { 0x3024, T_REG_32, "frames_65_to_127_octets", },
348 { 0x3028, T_REG_32, "frames_128_to_255_octets", },
349 { 0x302c, T_REG_32, "frames_256_to_511_octets", },
350 { 0x3030, T_REG_32, "frames_512_to_1023_octets", },
351 { 0x3034, T_REG_32, "frames_1024_to_max_octets", },
352 { 0x3038, T_REG_64, "good_octets_sent", },
353 { 0x3040, T_REG_32, "good_frames_sent", },
354 { 0x3044, T_REG_32, "excessive_collision", },
355 { 0x3048, T_REG_32, "multicast_frames_sent", },
356 { 0x304c, T_REG_32, "broadcast_frames_sent", },
357 { 0x3054, T_REG_32, "fc_sent", },
358 { 0x300c, T_REG_32, "internal_mac_transmit_err", },
361 struct mvneta_pcpu_stats {
362 struct u64_stats_sync syncp;
369 struct mvneta_pcpu_port {
370 /* Pointer to the shared port */
371 struct mvneta_port *pp;
373 /* Pointer to the CPU-local NAPI struct */
374 struct napi_struct napi;
376 /* Cause of the previous interrupt */
382 struct mvneta_pcpu_port __percpu *ports;
383 struct mvneta_pcpu_stats __percpu *stats;
386 unsigned int frag_size;
388 struct mvneta_rx_queue *rxqs;
389 struct mvneta_tx_queue *txqs;
390 struct net_device *dev;
391 struct hlist_node node_online;
392 struct hlist_node node_dead;
394 /* Protect the access to the percpu interrupt registers,
395 * ensuring that the configuration remains coherent.
401 struct napi_struct napi;
411 struct mii_bus *mii_bus;
412 phy_interface_t phy_interface;
413 struct device_node *phy_node;
417 unsigned int tx_csum_limit;
418 unsigned int use_inband_status:1;
420 struct mvneta_bm *bm_priv;
421 struct mvneta_bm_pool *pool_long;
422 struct mvneta_bm_pool *pool_short;
425 u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)];
427 u32 indir[MVNETA_RSS_LU_TABLE_SIZE];
429 /* Flags for special SoC configurations */
430 bool neta_armada3700;
431 u16 rx_offset_correction;
434 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
435 * layout of the transmit and reception DMA descriptors, and their
436 * layout is therefore defined by the hardware design
439 #define MVNETA_TX_L3_OFF_SHIFT 0
440 #define MVNETA_TX_IP_HLEN_SHIFT 8
441 #define MVNETA_TX_L4_UDP BIT(16)
442 #define MVNETA_TX_L3_IP6 BIT(17)
443 #define MVNETA_TXD_IP_CSUM BIT(18)
444 #define MVNETA_TXD_Z_PAD BIT(19)
445 #define MVNETA_TXD_L_DESC BIT(20)
446 #define MVNETA_TXD_F_DESC BIT(21)
447 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
448 MVNETA_TXD_L_DESC | \
450 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
451 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
453 #define MVNETA_RXD_ERR_CRC 0x0
454 #define MVNETA_RXD_BM_POOL_SHIFT 13
455 #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14))
456 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
457 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
458 #define MVNETA_RXD_ERR_LEN BIT(18)
459 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
460 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
461 #define MVNETA_RXD_L3_IP4 BIT(25)
462 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
463 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
465 #if defined(__LITTLE_ENDIAN)
466 struct mvneta_tx_desc {
467 u32 command; /* Options used by HW for packet transmitting.*/
468 u16 reserverd1; /* csum_l4 (for future use) */
469 u16 data_size; /* Data size of transmitted packet in bytes */
470 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
471 u32 reserved2; /* hw_cmd - (for future use, PMT) */
472 u32 reserved3[4]; /* Reserved - (for future use) */
475 struct mvneta_rx_desc {
476 u32 status; /* Info about received packet */
477 u16 reserved1; /* pnc_info - (for future use, PnC) */
478 u16 data_size; /* Size of received packet in bytes */
480 u32 buf_phys_addr; /* Physical address of the buffer */
481 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
483 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
484 u16 reserved3; /* prefetch_cmd, for future use */
485 u16 reserved4; /* csum_l4 - (for future use, PnC) */
487 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
488 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
491 struct mvneta_tx_desc {
492 u16 data_size; /* Data size of transmitted packet in bytes */
493 u16 reserverd1; /* csum_l4 (for future use) */
494 u32 command; /* Options used by HW for packet transmitting.*/
495 u32 reserved2; /* hw_cmd - (for future use, PMT) */
496 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
497 u32 reserved3[4]; /* Reserved - (for future use) */
500 struct mvneta_rx_desc {
501 u16 data_size; /* Size of received packet in bytes */
502 u16 reserved1; /* pnc_info - (for future use, PnC) */
503 u32 status; /* Info about received packet */
505 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
506 u32 buf_phys_addr; /* Physical address of the buffer */
508 u16 reserved4; /* csum_l4 - (for future use, PnC) */
509 u16 reserved3; /* prefetch_cmd, for future use */
510 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
512 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
513 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
517 struct mvneta_tx_queue {
518 /* Number of this TX queue, in the range 0-7 */
521 /* Number of TX DMA descriptors in the descriptor ring */
524 /* Number of currently used TX DMA descriptor in the
528 int tx_stop_threshold;
529 int tx_wake_threshold;
531 /* Array of transmitted skb */
532 struct sk_buff **tx_skb;
534 /* Index of last TX DMA descriptor that was inserted */
537 /* Index of the TX DMA descriptor to be cleaned up */
542 /* Virtual address of the TX DMA descriptors array */
543 struct mvneta_tx_desc *descs;
545 /* DMA address of the TX DMA descriptors array */
546 dma_addr_t descs_phys;
548 /* Index of the last TX DMA descriptor */
551 /* Index of the next TX DMA descriptor to process */
552 int next_desc_to_proc;
554 /* DMA buffers for TSO headers */
557 /* DMA address of TSO headers */
558 dma_addr_t tso_hdrs_phys;
560 /* Affinity mask for CPUs*/
561 cpumask_t affinity_mask;
564 struct mvneta_rx_queue {
565 /* rx queue number, in the range 0-7 */
568 /* num of rx descriptors in the rx descriptor ring */
571 /* counter of times when mvneta_refill() failed */
577 /* Virtual address of the RX buffer */
578 void **buf_virt_addr;
580 /* Virtual address of the RX DMA descriptors array */
581 struct mvneta_rx_desc *descs;
583 /* DMA address of the RX DMA descriptors array */
584 dma_addr_t descs_phys;
586 /* Index of the last RX DMA descriptor */
589 /* Index of the next RX DMA descriptor to process */
590 int next_desc_to_proc;
593 static enum cpuhp_state online_hpstate;
594 /* The hardware supports eight (8) rx queues, but we are only allowing
595 * the first one to be used. Therefore, let's just allocate one queue.
597 static int rxq_number = 8;
598 static int txq_number = 8;
602 static int rx_copybreak __read_mostly = 256;
604 /* HW BM need that each port be identify by a unique ID */
605 static int global_port_id;
607 #define MVNETA_DRIVER_NAME "mvneta"
608 #define MVNETA_DRIVER_VERSION "1.0"
610 /* Utility/helper methods */
612 /* Write helper method */
613 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
615 writel(data, pp->base + offset);
618 /* Read helper method */
619 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
621 return readl(pp->base + offset);
624 /* Increment txq get counter */
625 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
627 txq->txq_get_index++;
628 if (txq->txq_get_index == txq->size)
629 txq->txq_get_index = 0;
632 /* Increment txq put counter */
633 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
635 txq->txq_put_index++;
636 if (txq->txq_put_index == txq->size)
637 txq->txq_put_index = 0;
641 /* Clear all MIB counters */
642 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
647 /* Perform dummy reads from MIB counters */
648 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
649 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
650 dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT);
651 dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT);
654 /* Get System Network Statistics */
656 mvneta_get_stats64(struct net_device *dev,
657 struct rtnl_link_stats64 *stats)
659 struct mvneta_port *pp = netdev_priv(dev);
663 for_each_possible_cpu(cpu) {
664 struct mvneta_pcpu_stats *cpu_stats;
670 cpu_stats = per_cpu_ptr(pp->stats, cpu);
672 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
673 rx_packets = cpu_stats->rx_packets;
674 rx_bytes = cpu_stats->rx_bytes;
675 tx_packets = cpu_stats->tx_packets;
676 tx_bytes = cpu_stats->tx_bytes;
677 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
679 stats->rx_packets += rx_packets;
680 stats->rx_bytes += rx_bytes;
681 stats->tx_packets += tx_packets;
682 stats->tx_bytes += tx_bytes;
685 stats->rx_errors = dev->stats.rx_errors;
686 stats->rx_dropped = dev->stats.rx_dropped;
688 stats->tx_dropped = dev->stats.tx_dropped;
691 /* Rx descriptors helper methods */
693 /* Checks whether the RX descriptor having this status is both the first
694 * and the last descriptor for the RX packet. Each RX packet is currently
695 * received through a single RX descriptor, so not having each RX
696 * descriptor with its first and last bits set is an error
698 static int mvneta_rxq_desc_is_first_last(u32 status)
700 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
701 MVNETA_RXD_FIRST_LAST_DESC;
704 /* Add number of descriptors ready to receive new packets */
705 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
706 struct mvneta_rx_queue *rxq,
709 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
712 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
713 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
714 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
715 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
716 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
719 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
720 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
723 /* Get number of RX descriptors occupied by received packets */
724 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
725 struct mvneta_rx_queue *rxq)
729 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
730 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
733 /* Update num of rx desc called upon return from rx path or
734 * from mvneta_rxq_drop_pkts().
736 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
737 struct mvneta_rx_queue *rxq,
738 int rx_done, int rx_filled)
742 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
744 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
745 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
749 /* Only 255 descriptors can be added at once */
750 while ((rx_done > 0) || (rx_filled > 0)) {
751 if (rx_done <= 0xff) {
758 if (rx_filled <= 0xff) {
759 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
762 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
765 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
769 /* Get pointer to next RX descriptor to be processed by SW */
770 static struct mvneta_rx_desc *
771 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
773 int rx_desc = rxq->next_desc_to_proc;
775 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
776 prefetch(rxq->descs + rxq->next_desc_to_proc);
777 return rxq->descs + rx_desc;
780 /* Change maximum receive size of the port. */
781 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
785 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
786 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
787 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
788 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
789 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
793 /* Set rx queue offset */
794 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
795 struct mvneta_rx_queue *rxq,
800 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
801 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
804 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
805 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
809 /* Tx descriptors helper methods */
811 /* Update HW with number of TX descriptors to be sent */
812 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
813 struct mvneta_tx_queue *txq,
818 /* Only 255 descriptors can be added at once ; Assume caller
819 * process TX desriptors in quanta less than 256
822 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
825 /* Get pointer to next TX descriptor to be processed (send) by HW */
826 static struct mvneta_tx_desc *
827 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
829 int tx_desc = txq->next_desc_to_proc;
831 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
832 return txq->descs + tx_desc;
835 /* Release the last allocated TX descriptor. Useful to handle DMA
836 * mapping failures in the TX path.
838 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
840 if (txq->next_desc_to_proc == 0)
841 txq->next_desc_to_proc = txq->last_desc - 1;
843 txq->next_desc_to_proc--;
846 /* Set rxq buf size */
847 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
848 struct mvneta_rx_queue *rxq,
853 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
855 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
856 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
858 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
861 /* Disable buffer management (BM) */
862 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
863 struct mvneta_rx_queue *rxq)
867 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
868 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
869 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
872 /* Enable buffer management (BM) */
873 static void mvneta_rxq_bm_enable(struct mvneta_port *pp,
874 struct mvneta_rx_queue *rxq)
878 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
879 val |= MVNETA_RXQ_HW_BUF_ALLOC;
880 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
883 /* Notify HW about port's assignment of pool for bigger packets */
884 static void mvneta_rxq_long_pool_set(struct mvneta_port *pp,
885 struct mvneta_rx_queue *rxq)
889 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
890 val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK;
891 val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT);
893 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
896 /* Notify HW about port's assignment of pool for smaller packets */
897 static void mvneta_rxq_short_pool_set(struct mvneta_port *pp,
898 struct mvneta_rx_queue *rxq)
902 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
903 val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK;
904 val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT);
906 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
909 /* Set port's receive buffer size for assigned BM pool */
910 static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp,
916 if (!IS_ALIGNED(buf_size, 8)) {
917 dev_warn(pp->dev->dev.parent,
918 "illegal buf_size value %d, round to %d\n",
919 buf_size, ALIGN(buf_size, 8));
920 buf_size = ALIGN(buf_size, 8);
923 val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id));
924 val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK;
925 mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val);
928 /* Configure MBUS window in order to enable access BM internal SRAM */
929 static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize,
932 u32 win_enable, win_protect;
935 win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE);
937 if (pp->bm_win_id < 0) {
938 /* Find first not occupied window */
939 for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) {
940 if (win_enable & (1 << i)) {
945 if (i == MVNETA_MAX_DECODE_WIN)
951 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
952 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
955 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
957 mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) |
958 (attr << 8) | target);
960 mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000);
962 win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE);
963 win_protect |= 3 << (2 * i);
964 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
966 win_enable &= ~(1 << i);
967 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
972 static int mvneta_bm_port_mbus_init(struct mvneta_port *pp)
978 /* Get BM window information */
979 err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize,
986 /* Open NETA -> BM window */
987 err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize,
990 netdev_info(pp->dev, "fail to configure mbus window to BM\n");
996 /* Assign and initialize pools for port. In case of fail
997 * buffer manager will remain disabled for current port.
999 static int mvneta_bm_port_init(struct platform_device *pdev,
1000 struct mvneta_port *pp)
1002 struct device_node *dn = pdev->dev.of_node;
1003 u32 long_pool_id, short_pool_id;
1005 if (!pp->neta_armada3700) {
1008 ret = mvneta_bm_port_mbus_init(pp);
1013 if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) {
1014 netdev_info(pp->dev, "missing long pool id\n");
1018 /* Create port's long pool depending on mtu */
1019 pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id,
1020 MVNETA_BM_LONG, pp->id,
1021 MVNETA_RX_PKT_SIZE(pp->dev->mtu));
1022 if (!pp->pool_long) {
1023 netdev_info(pp->dev, "fail to obtain long pool for port\n");
1027 pp->pool_long->port_map |= 1 << pp->id;
1029 mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size,
1032 /* If short pool id is not defined, assume using single pool */
1033 if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id))
1034 short_pool_id = long_pool_id;
1036 /* Create port's short pool */
1037 pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id,
1038 MVNETA_BM_SHORT, pp->id,
1039 MVNETA_BM_SHORT_PKT_SIZE);
1040 if (!pp->pool_short) {
1041 netdev_info(pp->dev, "fail to obtain short pool for port\n");
1042 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1046 if (short_pool_id != long_pool_id) {
1047 pp->pool_short->port_map |= 1 << pp->id;
1048 mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size,
1049 pp->pool_short->id);
1055 /* Update settings of a pool for bigger packets */
1056 static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu)
1058 struct mvneta_bm_pool *bm_pool = pp->pool_long;
1059 struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool;
1062 /* Release all buffers from long pool */
1063 mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id);
1064 if (hwbm_pool->buf_num) {
1065 WARN(1, "cannot free all buffers in pool %d\n",
1070 bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu);
1071 bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size);
1072 hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
1073 SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size));
1075 /* Fill entire long pool */
1076 num = hwbm_pool_add(hwbm_pool, hwbm_pool->size, GFP_ATOMIC);
1077 if (num != hwbm_pool->size) {
1078 WARN(1, "pool %d: %d of %d allocated\n",
1079 bm_pool->id, num, hwbm_pool->size);
1082 mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id);
1087 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
1088 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id);
1091 mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1);
1092 netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n");
1095 /* Start the Ethernet port RX and TX activity */
1096 static void mvneta_port_up(struct mvneta_port *pp)
1101 /* Enable all initialized TXs. */
1103 for (queue = 0; queue < txq_number; queue++) {
1104 struct mvneta_tx_queue *txq = &pp->txqs[queue];
1105 if (txq->descs != NULL)
1106 q_map |= (1 << queue);
1108 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
1110 /* Enable all initialized RXQs. */
1111 for (queue = 0; queue < rxq_number; queue++) {
1112 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
1114 if (rxq->descs != NULL)
1115 q_map |= (1 << queue);
1117 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
1120 /* Stop the Ethernet port activity */
1121 static void mvneta_port_down(struct mvneta_port *pp)
1126 /* Stop Rx port activity. Check port Rx activity. */
1127 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
1129 /* Issue stop command for active channels only */
1131 mvreg_write(pp, MVNETA_RXQ_CMD,
1132 val << MVNETA_RXQ_DISABLE_SHIFT);
1134 /* Wait for all Rx activity to terminate. */
1137 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
1138 netdev_warn(pp->dev,
1139 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n",
1145 val = mvreg_read(pp, MVNETA_RXQ_CMD);
1146 } while (val & MVNETA_RXQ_ENABLE_MASK);
1148 /* Stop Tx port activity. Check port Tx activity. Issue stop
1149 * command for active channels only
1151 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
1154 mvreg_write(pp, MVNETA_TXQ_CMD,
1155 (val << MVNETA_TXQ_DISABLE_SHIFT));
1157 /* Wait for all Tx activity to terminate. */
1160 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
1161 netdev_warn(pp->dev,
1162 "TIMEOUT for TX stopped status=0x%08x\n",
1168 /* Check TX Command reg that all Txqs are stopped */
1169 val = mvreg_read(pp, MVNETA_TXQ_CMD);
1171 } while (val & MVNETA_TXQ_ENABLE_MASK);
1173 /* Double check to verify that TX FIFO is empty */
1176 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
1177 netdev_warn(pp->dev,
1178 "TX FIFO empty timeout status=0x%08x\n",
1184 val = mvreg_read(pp, MVNETA_PORT_STATUS);
1185 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
1186 (val & MVNETA_TX_IN_PRGRS));
1191 /* Enable the port by setting the port enable bit of the MAC control register */
1192 static void mvneta_port_enable(struct mvneta_port *pp)
1197 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1198 val |= MVNETA_GMAC0_PORT_ENABLE;
1199 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1202 /* Disable the port and wait for about 200 usec before retuning */
1203 static void mvneta_port_disable(struct mvneta_port *pp)
1207 /* Reset the Enable bit in the Serial Control Register */
1208 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
1209 val &= ~MVNETA_GMAC0_PORT_ENABLE;
1210 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
1215 /* Multicast tables methods */
1217 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
1218 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
1226 val = 0x1 | (queue << 1);
1227 val |= (val << 24) | (val << 16) | (val << 8);
1230 for (offset = 0; offset <= 0xc; offset += 4)
1231 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
1234 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
1235 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
1243 val = 0x1 | (queue << 1);
1244 val |= (val << 24) | (val << 16) | (val << 8);
1247 for (offset = 0; offset <= 0xfc; offset += 4)
1248 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
1252 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
1253 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
1259 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
1262 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
1263 val = 0x1 | (queue << 1);
1264 val |= (val << 24) | (val << 16) | (val << 8);
1267 for (offset = 0; offset <= 0xfc; offset += 4)
1268 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
1271 static void mvneta_set_autoneg(struct mvneta_port *pp, int enable)
1276 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1277 val &= ~(MVNETA_GMAC_FORCE_LINK_PASS |
1278 MVNETA_GMAC_FORCE_LINK_DOWN |
1279 MVNETA_GMAC_AN_FLOW_CTRL_EN);
1280 val |= MVNETA_GMAC_INBAND_AN_ENABLE |
1281 MVNETA_GMAC_AN_SPEED_EN |
1282 MVNETA_GMAC_AN_DUPLEX_EN;
1283 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1285 val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
1286 val |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
1287 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
1289 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
1290 val |= MVNETA_GMAC2_INBAND_AN_ENABLE;
1291 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
1293 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1294 val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE |
1295 MVNETA_GMAC_AN_SPEED_EN |
1296 MVNETA_GMAC_AN_DUPLEX_EN);
1297 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1299 val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
1300 val &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
1301 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
1303 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
1304 val &= ~MVNETA_GMAC2_INBAND_AN_ENABLE;
1305 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
1309 static void mvneta_percpu_unmask_interrupt(void *arg)
1311 struct mvneta_port *pp = arg;
1313 /* All the queue are unmasked, but actually only the ones
1314 * mapped to this CPU will be unmasked
1316 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1317 MVNETA_RX_INTR_MASK_ALL |
1318 MVNETA_TX_INTR_MASK_ALL |
1319 MVNETA_MISCINTR_INTR_MASK);
1322 static void mvneta_percpu_mask_interrupt(void *arg)
1324 struct mvneta_port *pp = arg;
1326 /* All the queue are masked, but actually only the ones
1327 * mapped to this CPU will be masked
1329 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1330 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
1331 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
1334 static void mvneta_percpu_clear_intr_cause(void *arg)
1336 struct mvneta_port *pp = arg;
1338 /* All the queue are cleared, but actually only the ones
1339 * mapped to this CPU will be cleared
1341 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
1342 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
1343 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
1346 /* This method sets defaults to the NETA port:
1347 * Clears interrupt Cause and Mask registers.
1348 * Clears all MAC tables.
1349 * Sets defaults to all registers.
1350 * Resets RX and TX descriptor rings.
1352 * This method can be called after mvneta_port_down() to return the port
1353 * settings to defaults.
1355 static void mvneta_defaults_set(struct mvneta_port *pp)
1360 int max_cpu = num_present_cpus();
1362 /* Clear all Cause registers */
1363 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
1365 /* Mask all interrupts */
1366 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
1367 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
1369 /* Enable MBUS Retry bit16 */
1370 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
1372 /* Set CPU queue access map. CPUs are assigned to the RX and
1373 * TX queues modulo their number. If there is only one TX
1374 * queue then it is assigned to the CPU associated to the
1377 for_each_present_cpu(cpu) {
1378 int rxq_map = 0, txq_map = 0;
1380 if (!pp->neta_armada3700) {
1381 for (rxq = 0; rxq < rxq_number; rxq++)
1382 if ((rxq % max_cpu) == cpu)
1383 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
1385 for (txq = 0; txq < txq_number; txq++)
1386 if ((txq % max_cpu) == cpu)
1387 txq_map |= MVNETA_CPU_TXQ_ACCESS(txq);
1389 /* With only one TX queue we configure a special case
1390 * which will allow to get all the irq on a single
1393 if (txq_number == 1)
1394 txq_map = (cpu == pp->rxq_def) ?
1395 MVNETA_CPU_TXQ_ACCESS(1) : 0;
1398 txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
1399 rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK;
1402 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
1405 /* Reset RX and TX DMAs */
1406 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
1407 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
1409 /* Disable Legacy WRR, Disable EJP, Release from reset */
1410 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
1411 for (queue = 0; queue < txq_number; queue++) {
1412 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
1413 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
1416 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
1417 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
1419 /* Set Port Acceleration Mode */
1421 /* HW buffer management + legacy parser */
1422 val = MVNETA_ACC_MODE_EXT2;
1424 /* SW buffer management + legacy parser */
1425 val = MVNETA_ACC_MODE_EXT1;
1426 mvreg_write(pp, MVNETA_ACC_MODE, val);
1429 mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr);
1431 /* Update val of portCfg register accordingly with all RxQueue types */
1432 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
1433 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
1436 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
1437 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
1439 /* Build PORT_SDMA_CONFIG_REG */
1442 /* Default burst size */
1443 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1444 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
1445 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
1447 #if defined(__BIG_ENDIAN)
1448 val |= MVNETA_DESC_SWAP;
1451 /* Assign port SDMA configuration */
1452 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
1454 /* Disable PHY polling in hardware, since we're using the
1455 * kernel phylib to do this.
1457 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
1458 val &= ~MVNETA_PHY_POLLING_ENABLE;
1459 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
1461 mvneta_set_autoneg(pp, pp->use_inband_status);
1462 mvneta_set_ucast_table(pp, -1);
1463 mvneta_set_special_mcast_table(pp, -1);
1464 mvneta_set_other_mcast_table(pp, -1);
1466 /* Set port interrupt enable register - default enable all */
1467 mvreg_write(pp, MVNETA_INTR_ENABLE,
1468 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1469 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
1471 mvneta_mib_counters_clear(pp);
1474 /* Set max sizes for tx queues */
1475 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
1481 mtu = max_tx_size * 8;
1482 if (mtu > MVNETA_TX_MTU_MAX)
1483 mtu = MVNETA_TX_MTU_MAX;
1486 val = mvreg_read(pp, MVNETA_TX_MTU);
1487 val &= ~MVNETA_TX_MTU_MAX;
1489 mvreg_write(pp, MVNETA_TX_MTU, val);
1491 /* TX token size and all TXQs token size must be larger that MTU */
1492 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1494 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
1497 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
1499 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1501 for (queue = 0; queue < txq_number; queue++) {
1502 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1504 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1507 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1509 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1514 /* Set unicast address */
1515 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1518 unsigned int unicast_reg;
1519 unsigned int tbl_offset;
1520 unsigned int reg_offset;
1522 /* Locate the Unicast table entry */
1523 last_nibble = (0xf & last_nibble);
1525 /* offset from unicast tbl base */
1526 tbl_offset = (last_nibble / 4) * 4;
1528 /* offset within the above reg */
1529 reg_offset = last_nibble % 4;
1531 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1534 /* Clear accepts frame bit at specified unicast DA tbl entry */
1535 unicast_reg &= ~(0xff << (8 * reg_offset));
1537 unicast_reg &= ~(0xff << (8 * reg_offset));
1538 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1541 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1544 /* Set mac address */
1545 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1552 mac_l = (addr[4] << 8) | (addr[5]);
1553 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1554 (addr[2] << 8) | (addr[3] << 0);
1556 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1557 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1560 /* Accept frames of this address */
1561 mvneta_set_ucast_addr(pp, addr[5], queue);
1564 /* Set the number of packets that will be received before RX interrupt
1565 * will be generated by HW.
1567 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1568 struct mvneta_rx_queue *rxq, u32 value)
1570 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1571 value | MVNETA_RXQ_NON_OCCUPIED(0));
1572 rxq->pkts_coal = value;
1575 /* Set the time delay in usec before RX interrupt will be generated by
1578 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1579 struct mvneta_rx_queue *rxq, u32 value)
1582 unsigned long clk_rate;
1584 clk_rate = clk_get_rate(pp->clk);
1585 val = (clk_rate / 1000000) * value;
1587 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1588 rxq->time_coal = value;
1591 /* Set threshold for TX_DONE pkts coalescing */
1592 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1593 struct mvneta_tx_queue *txq, u32 value)
1597 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1599 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1600 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1602 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1604 txq->done_pkts_coal = value;
1607 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1608 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1609 u32 phys_addr, void *virt_addr,
1610 struct mvneta_rx_queue *rxq)
1614 rx_desc->buf_phys_addr = phys_addr;
1615 i = rx_desc - rxq->descs;
1616 rxq->buf_virt_addr[i] = virt_addr;
1619 /* Decrement sent descriptors counter */
1620 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1621 struct mvneta_tx_queue *txq,
1626 /* Only 255 TX descriptors can be updated at once */
1627 while (sent_desc > 0xff) {
1628 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1629 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1630 sent_desc = sent_desc - 0xff;
1633 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1634 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1637 /* Get number of TX descriptors already sent by HW */
1638 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1639 struct mvneta_tx_queue *txq)
1644 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1645 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1646 MVNETA_TXQ_SENT_DESC_SHIFT;
1651 /* Get number of sent descriptors and decrement counter.
1652 * The number of sent descriptors is returned.
1654 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1655 struct mvneta_tx_queue *txq)
1659 /* Get number of sent descriptors */
1660 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1662 /* Decrement sent descriptors counter */
1664 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1669 /* Set TXQ descriptors fields relevant for CSUM calculation */
1670 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1671 int ip_hdr_len, int l4_proto)
1675 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1676 * G_L4_chk, L4_type; required only for checksum
1679 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1680 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1682 if (l3_proto == htons(ETH_P_IP))
1683 command |= MVNETA_TXD_IP_CSUM;
1685 command |= MVNETA_TX_L3_IP6;
1687 if (l4_proto == IPPROTO_TCP)
1688 command |= MVNETA_TX_L4_CSUM_FULL;
1689 else if (l4_proto == IPPROTO_UDP)
1690 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1692 command |= MVNETA_TX_L4_CSUM_NOT;
1698 /* Display more error info */
1699 static void mvneta_rx_error(struct mvneta_port *pp,
1700 struct mvneta_rx_desc *rx_desc)
1702 u32 status = rx_desc->status;
1704 if (!mvneta_rxq_desc_is_first_last(status)) {
1706 "bad rx status %08x (buffer oversize), size=%d\n",
1707 status, rx_desc->data_size);
1711 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1712 case MVNETA_RXD_ERR_CRC:
1713 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1714 status, rx_desc->data_size);
1716 case MVNETA_RXD_ERR_OVERRUN:
1717 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1718 status, rx_desc->data_size);
1720 case MVNETA_RXD_ERR_LEN:
1721 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1722 status, rx_desc->data_size);
1724 case MVNETA_RXD_ERR_RESOURCE:
1725 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1726 status, rx_desc->data_size);
1731 /* Handle RX checksum offload based on the descriptor's status */
1732 static void mvneta_rx_csum(struct mvneta_port *pp, u32 status,
1733 struct sk_buff *skb)
1735 if ((status & MVNETA_RXD_L3_IP4) &&
1736 (status & MVNETA_RXD_L4_CSUM_OK)) {
1738 skb->ip_summed = CHECKSUM_UNNECESSARY;
1742 skb->ip_summed = CHECKSUM_NONE;
1745 /* Return tx queue pointer (find last set bit) according to <cause> returned
1746 * form tx_done reg. <cause> must not be null. The return value is always a
1747 * valid queue for matching the first one found in <cause>.
1749 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1752 int queue = fls(cause) - 1;
1754 return &pp->txqs[queue];
1757 /* Free tx queue skbuffs */
1758 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1759 struct mvneta_tx_queue *txq, int num)
1763 for (i = 0; i < num; i++) {
1764 struct mvneta_tx_desc *tx_desc = txq->descs +
1766 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1768 mvneta_txq_inc_get(txq);
1770 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
1771 dma_unmap_single(pp->dev->dev.parent,
1772 tx_desc->buf_phys_addr,
1773 tx_desc->data_size, DMA_TO_DEVICE);
1776 dev_kfree_skb_any(skb);
1780 /* Handle end of transmission */
1781 static void mvneta_txq_done(struct mvneta_port *pp,
1782 struct mvneta_tx_queue *txq)
1784 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1787 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1791 mvneta_txq_bufs_free(pp, txq, tx_done);
1793 txq->count -= tx_done;
1795 if (netif_tx_queue_stopped(nq)) {
1796 if (txq->count <= txq->tx_wake_threshold)
1797 netif_tx_wake_queue(nq);
1801 void *mvneta_frag_alloc(unsigned int frag_size)
1803 if (likely(frag_size <= PAGE_SIZE))
1804 return netdev_alloc_frag(frag_size);
1806 return kmalloc(frag_size, GFP_ATOMIC);
1808 EXPORT_SYMBOL_GPL(mvneta_frag_alloc);
1810 void mvneta_frag_free(unsigned int frag_size, void *data)
1812 if (likely(frag_size <= PAGE_SIZE))
1813 skb_free_frag(data);
1817 EXPORT_SYMBOL_GPL(mvneta_frag_free);
1819 /* Refill processing for SW buffer management */
1820 static int mvneta_rx_refill(struct mvneta_port *pp,
1821 struct mvneta_rx_desc *rx_desc,
1822 struct mvneta_rx_queue *rxq)
1825 dma_addr_t phys_addr;
1828 data = mvneta_frag_alloc(pp->frag_size);
1832 phys_addr = dma_map_single(pp->dev->dev.parent, data,
1833 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1835 if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
1836 mvneta_frag_free(pp->frag_size, data);
1840 phys_addr += pp->rx_offset_correction;
1841 mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq);
1845 /* Handle tx checksum */
1846 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1848 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1850 __be16 l3_proto = vlan_get_protocol(skb);
1853 if (l3_proto == htons(ETH_P_IP)) {
1854 struct iphdr *ip4h = ip_hdr(skb);
1856 /* Calculate IPv4 checksum and L4 checksum */
1857 ip_hdr_len = ip4h->ihl;
1858 l4_proto = ip4h->protocol;
1859 } else if (l3_proto == htons(ETH_P_IPV6)) {
1860 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1862 /* Read l4_protocol from one of IPv6 extra headers */
1863 if (skb_network_header_len(skb) > 0)
1864 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1865 l4_proto = ip6h->nexthdr;
1867 return MVNETA_TX_L4_CSUM_NOT;
1869 return mvneta_txq_desc_csum(skb_network_offset(skb),
1870 l3_proto, ip_hdr_len, l4_proto);
1873 return MVNETA_TX_L4_CSUM_NOT;
1876 /* Drop packets received by the RXQ and free buffers */
1877 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1878 struct mvneta_rx_queue *rxq)
1882 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1884 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1887 for (i = 0; i < rx_done; i++) {
1888 struct mvneta_rx_desc *rx_desc =
1889 mvneta_rxq_next_desc_get(rxq);
1890 u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
1891 struct mvneta_bm_pool *bm_pool;
1893 bm_pool = &pp->bm_priv->bm_pools[pool_id];
1894 /* Return dropped buffer to the pool */
1895 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
1896 rx_desc->buf_phys_addr);
1901 for (i = 0; i < rxq->size; i++) {
1902 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1903 void *data = rxq->buf_virt_addr[i];
1905 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1906 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
1907 mvneta_frag_free(pp->frag_size, data);
1911 /* Main rx processing when using software buffer management */
1912 static int mvneta_rx_swbm(struct mvneta_port *pp, int rx_todo,
1913 struct mvneta_rx_queue *rxq)
1915 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
1916 struct net_device *dev = pp->dev;
1921 /* Get number of received packets */
1922 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1924 if (rx_todo > rx_done)
1929 /* Fairness NAPI loop */
1930 while (rx_done < rx_todo) {
1931 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1932 struct sk_buff *skb;
1933 unsigned char *data;
1934 dma_addr_t phys_addr;
1935 u32 rx_status, frag_size;
1936 int rx_bytes, err, index;
1939 rx_status = rx_desc->status;
1940 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
1941 index = rx_desc - rxq->descs;
1942 data = rxq->buf_virt_addr[index];
1943 phys_addr = rx_desc->buf_phys_addr;
1945 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1946 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1948 dev->stats.rx_errors++;
1949 mvneta_rx_error(pp, rx_desc);
1950 /* leave the descriptor untouched */
1954 if (rx_bytes <= rx_copybreak) {
1955 /* better copy a small frame and not unmap the DMA region */
1956 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
1958 goto err_drop_frame;
1960 dma_sync_single_range_for_cpu(dev->dev.parent,
1962 MVNETA_MH_SIZE + NET_SKB_PAD,
1965 memcpy(skb_put(skb, rx_bytes),
1966 data + MVNETA_MH_SIZE + NET_SKB_PAD,
1969 skb->protocol = eth_type_trans(skb, dev);
1970 mvneta_rx_csum(pp, rx_status, skb);
1971 napi_gro_receive(&port->napi, skb);
1974 rcvd_bytes += rx_bytes;
1976 /* leave the descriptor and buffer untouched */
1980 /* Refill processing */
1981 err = mvneta_rx_refill(pp, rx_desc, rxq);
1983 netdev_err(dev, "Linux processing - Can't refill\n");
1985 goto err_drop_frame;
1988 frag_size = pp->frag_size;
1990 skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
1992 /* After refill old buffer has to be unmapped regardless
1993 * the skb is successfully built or not.
1995 dma_unmap_single(dev->dev.parent, phys_addr,
1996 MVNETA_RX_BUF_SIZE(pp->pkt_size),
2000 goto err_drop_frame;
2003 rcvd_bytes += rx_bytes;
2005 /* Linux processing */
2006 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
2007 skb_put(skb, rx_bytes);
2009 skb->protocol = eth_type_trans(skb, dev);
2011 mvneta_rx_csum(pp, rx_status, skb);
2013 napi_gro_receive(&port->napi, skb);
2017 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2019 u64_stats_update_begin(&stats->syncp);
2020 stats->rx_packets += rcvd_pkts;
2021 stats->rx_bytes += rcvd_bytes;
2022 u64_stats_update_end(&stats->syncp);
2025 /* Update rxq management counters */
2026 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
2031 /* Main rx processing when using hardware buffer management */
2032 static int mvneta_rx_hwbm(struct mvneta_port *pp, int rx_todo,
2033 struct mvneta_rx_queue *rxq)
2035 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
2036 struct net_device *dev = pp->dev;
2041 /* Get number of received packets */
2042 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
2044 if (rx_todo > rx_done)
2049 /* Fairness NAPI loop */
2050 while (rx_done < rx_todo) {
2051 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
2052 struct mvneta_bm_pool *bm_pool = NULL;
2053 struct sk_buff *skb;
2054 unsigned char *data;
2055 dma_addr_t phys_addr;
2056 u32 rx_status, frag_size;
2061 rx_status = rx_desc->status;
2062 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
2063 data = (u8 *)(uintptr_t)rx_desc->buf_cookie;
2064 phys_addr = rx_desc->buf_phys_addr;
2065 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
2066 bm_pool = &pp->bm_priv->bm_pools[pool_id];
2068 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
2069 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
2070 err_drop_frame_ret_pool:
2071 /* Return the buffer to the pool */
2072 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2073 rx_desc->buf_phys_addr);
2075 dev->stats.rx_errors++;
2076 mvneta_rx_error(pp, rx_desc);
2077 /* leave the descriptor untouched */
2081 if (rx_bytes <= rx_copybreak) {
2082 /* better copy a small frame and not unmap the DMA region */
2083 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
2085 goto err_drop_frame_ret_pool;
2087 dma_sync_single_range_for_cpu(dev->dev.parent,
2088 rx_desc->buf_phys_addr,
2089 MVNETA_MH_SIZE + NET_SKB_PAD,
2092 memcpy(skb_put(skb, rx_bytes),
2093 data + MVNETA_MH_SIZE + NET_SKB_PAD,
2096 skb->protocol = eth_type_trans(skb, dev);
2097 mvneta_rx_csum(pp, rx_status, skb);
2098 napi_gro_receive(&port->napi, skb);
2101 rcvd_bytes += rx_bytes;
2103 /* Return the buffer to the pool */
2104 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
2105 rx_desc->buf_phys_addr);
2107 /* leave the descriptor and buffer untouched */
2111 /* Refill processing */
2112 err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC);
2114 netdev_err(dev, "Linux processing - Can't refill\n");
2116 goto err_drop_frame_ret_pool;
2119 frag_size = bm_pool->hwbm_pool.frag_size;
2121 skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
2123 /* After refill old buffer has to be unmapped regardless
2124 * the skb is successfully built or not.
2126 dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr,
2127 bm_pool->buf_size, DMA_FROM_DEVICE);
2129 goto err_drop_frame;
2132 rcvd_bytes += rx_bytes;
2134 /* Linux processing */
2135 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
2136 skb_put(skb, rx_bytes);
2138 skb->protocol = eth_type_trans(skb, dev);
2140 mvneta_rx_csum(pp, rx_status, skb);
2142 napi_gro_receive(&port->napi, skb);
2146 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2148 u64_stats_update_begin(&stats->syncp);
2149 stats->rx_packets += rcvd_pkts;
2150 stats->rx_bytes += rcvd_bytes;
2151 u64_stats_update_end(&stats->syncp);
2154 /* Update rxq management counters */
2155 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
2161 mvneta_tso_put_hdr(struct sk_buff *skb,
2162 struct mvneta_port *pp, struct mvneta_tx_queue *txq)
2164 struct mvneta_tx_desc *tx_desc;
2165 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2167 txq->tx_skb[txq->txq_put_index] = NULL;
2168 tx_desc = mvneta_txq_next_desc_get(txq);
2169 tx_desc->data_size = hdr_len;
2170 tx_desc->command = mvneta_skb_tx_csum(pp, skb);
2171 tx_desc->command |= MVNETA_TXD_F_DESC;
2172 tx_desc->buf_phys_addr = txq->tso_hdrs_phys +
2173 txq->txq_put_index * TSO_HEADER_SIZE;
2174 mvneta_txq_inc_put(txq);
2178 mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq,
2179 struct sk_buff *skb, char *data, int size,
2180 bool last_tcp, bool is_last)
2182 struct mvneta_tx_desc *tx_desc;
2184 tx_desc = mvneta_txq_next_desc_get(txq);
2185 tx_desc->data_size = size;
2186 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data,
2187 size, DMA_TO_DEVICE);
2188 if (unlikely(dma_mapping_error(dev->dev.parent,
2189 tx_desc->buf_phys_addr))) {
2190 mvneta_txq_desc_put(txq);
2194 tx_desc->command = 0;
2195 txq->tx_skb[txq->txq_put_index] = NULL;
2198 /* last descriptor in the TCP packet */
2199 tx_desc->command = MVNETA_TXD_L_DESC;
2201 /* last descriptor in SKB */
2203 txq->tx_skb[txq->txq_put_index] = skb;
2205 mvneta_txq_inc_put(txq);
2209 static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev,
2210 struct mvneta_tx_queue *txq)
2212 int total_len, data_left;
2214 struct mvneta_port *pp = netdev_priv(dev);
2216 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2219 /* Count needed descriptors */
2220 if ((txq->count + tso_count_descs(skb)) >= txq->size)
2223 if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) {
2224 pr_info("*** Is this even possible???!?!?\n");
2228 /* Initialize the TSO handler, and prepare the first payload */
2229 tso_start(skb, &tso);
2231 total_len = skb->len - hdr_len;
2232 while (total_len > 0) {
2235 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
2236 total_len -= data_left;
2239 /* prepare packet headers: MAC + IP + TCP */
2240 hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE;
2241 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
2243 mvneta_tso_put_hdr(skb, pp, txq);
2245 while (data_left > 0) {
2249 size = min_t(int, tso.size, data_left);
2251 if (mvneta_tso_put_data(dev, txq, skb,
2258 tso_build_data(skb, &tso, size);
2265 /* Release all used data descriptors; header descriptors must not
2268 for (i = desc_count - 1; i >= 0; i--) {
2269 struct mvneta_tx_desc *tx_desc = txq->descs + i;
2270 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
2271 dma_unmap_single(pp->dev->dev.parent,
2272 tx_desc->buf_phys_addr,
2275 mvneta_txq_desc_put(txq);
2280 /* Handle tx fragmentation processing */
2281 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
2282 struct mvneta_tx_queue *txq)
2284 struct mvneta_tx_desc *tx_desc;
2285 int i, nr_frags = skb_shinfo(skb)->nr_frags;
2287 for (i = 0; i < nr_frags; i++) {
2288 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2289 void *addr = page_address(frag->page.p) + frag->page_offset;
2291 tx_desc = mvneta_txq_next_desc_get(txq);
2292 tx_desc->data_size = frag->size;
2294 tx_desc->buf_phys_addr =
2295 dma_map_single(pp->dev->dev.parent, addr,
2296 tx_desc->data_size, DMA_TO_DEVICE);
2298 if (dma_mapping_error(pp->dev->dev.parent,
2299 tx_desc->buf_phys_addr)) {
2300 mvneta_txq_desc_put(txq);
2304 if (i == nr_frags - 1) {
2305 /* Last descriptor */
2306 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
2307 txq->tx_skb[txq->txq_put_index] = skb;
2309 /* Descriptor in the middle: Not First, Not Last */
2310 tx_desc->command = 0;
2311 txq->tx_skb[txq->txq_put_index] = NULL;
2313 mvneta_txq_inc_put(txq);
2319 /* Release all descriptors that were used to map fragments of
2320 * this packet, as well as the corresponding DMA mappings
2322 for (i = i - 1; i >= 0; i--) {
2323 tx_desc = txq->descs + i;
2324 dma_unmap_single(pp->dev->dev.parent,
2325 tx_desc->buf_phys_addr,
2328 mvneta_txq_desc_put(txq);
2334 /* Main tx processing */
2335 static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
2337 struct mvneta_port *pp = netdev_priv(dev);
2338 u16 txq_id = skb_get_queue_mapping(skb);
2339 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
2340 struct mvneta_tx_desc *tx_desc;
2345 if (!netif_running(dev))
2348 if (skb_is_gso(skb)) {
2349 frags = mvneta_tx_tso(skb, dev, txq);
2353 frags = skb_shinfo(skb)->nr_frags + 1;
2355 /* Get a descriptor for the first part of the packet */
2356 tx_desc = mvneta_txq_next_desc_get(txq);
2358 tx_cmd = mvneta_skb_tx_csum(pp, skb);
2360 tx_desc->data_size = skb_headlen(skb);
2362 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
2365 if (unlikely(dma_mapping_error(dev->dev.parent,
2366 tx_desc->buf_phys_addr))) {
2367 mvneta_txq_desc_put(txq);
2373 /* First and Last descriptor */
2374 tx_cmd |= MVNETA_TXD_FLZ_DESC;
2375 tx_desc->command = tx_cmd;
2376 txq->tx_skb[txq->txq_put_index] = skb;
2377 mvneta_txq_inc_put(txq);
2379 /* First but not Last */
2380 tx_cmd |= MVNETA_TXD_F_DESC;
2381 txq->tx_skb[txq->txq_put_index] = NULL;
2382 mvneta_txq_inc_put(txq);
2383 tx_desc->command = tx_cmd;
2384 /* Continue with other skb fragments */
2385 if (mvneta_tx_frag_process(pp, skb, txq)) {
2386 dma_unmap_single(dev->dev.parent,
2387 tx_desc->buf_phys_addr,
2390 mvneta_txq_desc_put(txq);
2398 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
2399 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
2401 txq->count += frags;
2402 mvneta_txq_pend_desc_add(pp, txq, frags);
2404 if (txq->count >= txq->tx_stop_threshold)
2405 netif_tx_stop_queue(nq);
2407 u64_stats_update_begin(&stats->syncp);
2408 stats->tx_packets++;
2409 stats->tx_bytes += len;
2410 u64_stats_update_end(&stats->syncp);
2412 dev->stats.tx_dropped++;
2413 dev_kfree_skb_any(skb);
2416 return NETDEV_TX_OK;
2420 /* Free tx resources, when resetting a port */
2421 static void mvneta_txq_done_force(struct mvneta_port *pp,
2422 struct mvneta_tx_queue *txq)
2425 int tx_done = txq->count;
2427 mvneta_txq_bufs_free(pp, txq, tx_done);
2431 txq->txq_put_index = 0;
2432 txq->txq_get_index = 0;
2435 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
2436 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
2438 static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
2440 struct mvneta_tx_queue *txq;
2441 struct netdev_queue *nq;
2443 while (cause_tx_done) {
2444 txq = mvneta_tx_done_policy(pp, cause_tx_done);
2446 nq = netdev_get_tx_queue(pp->dev, txq->id);
2447 __netif_tx_lock(nq, smp_processor_id());
2450 mvneta_txq_done(pp, txq);
2452 __netif_tx_unlock(nq);
2453 cause_tx_done &= ~((1 << txq->id));
2457 /* Compute crc8 of the specified address, using a unique algorithm ,
2458 * according to hw spec, different than generic crc8 algorithm
2460 static int mvneta_addr_crc(unsigned char *addr)
2465 for (i = 0; i < ETH_ALEN; i++) {
2468 crc = (crc ^ addr[i]) << 8;
2469 for (j = 7; j >= 0; j--) {
2470 if (crc & (0x100 << j))
2478 /* This method controls the net device special MAC multicast support.
2479 * The Special Multicast Table for MAC addresses supports MAC of the form
2480 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2481 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2482 * Table entries in the DA-Filter table. This method set the Special
2483 * Multicast Table appropriate entry.
2485 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
2486 unsigned char last_byte,
2489 unsigned int smc_table_reg;
2490 unsigned int tbl_offset;
2491 unsigned int reg_offset;
2493 /* Register offset from SMC table base */
2494 tbl_offset = (last_byte / 4);
2495 /* Entry offset within the above reg */
2496 reg_offset = last_byte % 4;
2498 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
2502 smc_table_reg &= ~(0xff << (8 * reg_offset));
2504 smc_table_reg &= ~(0xff << (8 * reg_offset));
2505 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2508 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
2512 /* This method controls the network device Other MAC multicast support.
2513 * The Other Multicast Table is used for multicast of another type.
2514 * A CRC-8 is used as an index to the Other Multicast Table entries
2515 * in the DA-Filter table.
2516 * The method gets the CRC-8 value from the calling routine and
2517 * sets the Other Multicast Table appropriate entry according to the
2520 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
2524 unsigned int omc_table_reg;
2525 unsigned int tbl_offset;
2526 unsigned int reg_offset;
2528 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
2529 reg_offset = crc8 % 4; /* Entry offset within the above reg */
2531 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
2534 /* Clear accepts frame bit at specified Other DA table entry */
2535 omc_table_reg &= ~(0xff << (8 * reg_offset));
2537 omc_table_reg &= ~(0xff << (8 * reg_offset));
2538 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
2541 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
2544 /* The network device supports multicast using two tables:
2545 * 1) Special Multicast Table for MAC addresses of the form
2546 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
2547 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2548 * Table entries in the DA-Filter table.
2549 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
2550 * is used as an index to the Other Multicast Table entries in the
2553 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
2556 unsigned char crc_result = 0;
2558 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
2559 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
2563 crc_result = mvneta_addr_crc(p_addr);
2565 if (pp->mcast_count[crc_result] == 0) {
2566 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
2571 pp->mcast_count[crc_result]--;
2572 if (pp->mcast_count[crc_result] != 0) {
2573 netdev_info(pp->dev,
2574 "After delete there are %d valid Mcast for crc8=0x%02x\n",
2575 pp->mcast_count[crc_result], crc_result);
2579 pp->mcast_count[crc_result]++;
2581 mvneta_set_other_mcast_addr(pp, crc_result, queue);
2586 /* Configure Fitering mode of Ethernet port */
2587 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
2590 u32 port_cfg_reg, val;
2592 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
2594 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
2596 /* Set / Clear UPM bit in port configuration register */
2598 /* Accept all Unicast addresses */
2599 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
2600 val |= MVNETA_FORCE_UNI;
2601 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
2602 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
2604 /* Reject all Unicast addresses */
2605 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
2606 val &= ~MVNETA_FORCE_UNI;
2609 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
2610 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
2613 /* register unicast and multicast addresses */
2614 static void mvneta_set_rx_mode(struct net_device *dev)
2616 struct mvneta_port *pp = netdev_priv(dev);
2617 struct netdev_hw_addr *ha;
2619 if (dev->flags & IFF_PROMISC) {
2620 /* Accept all: Multicast + Unicast */
2621 mvneta_rx_unicast_promisc_set(pp, 1);
2622 mvneta_set_ucast_table(pp, pp->rxq_def);
2623 mvneta_set_special_mcast_table(pp, pp->rxq_def);
2624 mvneta_set_other_mcast_table(pp, pp->rxq_def);
2626 /* Accept single Unicast */
2627 mvneta_rx_unicast_promisc_set(pp, 0);
2628 mvneta_set_ucast_table(pp, -1);
2629 mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def);
2631 if (dev->flags & IFF_ALLMULTI) {
2632 /* Accept all multicast */
2633 mvneta_set_special_mcast_table(pp, pp->rxq_def);
2634 mvneta_set_other_mcast_table(pp, pp->rxq_def);
2636 /* Accept only initialized multicast */
2637 mvneta_set_special_mcast_table(pp, -1);
2638 mvneta_set_other_mcast_table(pp, -1);
2640 if (!netdev_mc_empty(dev)) {
2641 netdev_for_each_mc_addr(ha, dev) {
2642 mvneta_mcast_addr_set(pp, ha->addr,
2650 /* Interrupt handling - the callback for request_irq() */
2651 static irqreturn_t mvneta_isr(int irq, void *dev_id)
2653 struct mvneta_port *pp = (struct mvneta_port *)dev_id;
2655 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2656 napi_schedule(&pp->napi);
2661 /* Interrupt handling - the callback for request_percpu_irq() */
2662 static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id)
2664 struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id;
2666 disable_percpu_irq(port->pp->dev->irq);
2667 napi_schedule(&port->napi);
2672 static int mvneta_fixed_link_update(struct mvneta_port *pp,
2673 struct phy_device *phy)
2675 struct fixed_phy_status status;
2676 struct fixed_phy_status changed = {};
2677 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
2679 status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
2680 if (gmac_stat & MVNETA_GMAC_SPEED_1000)
2681 status.speed = SPEED_1000;
2682 else if (gmac_stat & MVNETA_GMAC_SPEED_100)
2683 status.speed = SPEED_100;
2685 status.speed = SPEED_10;
2686 status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
2690 fixed_phy_update_state(phy, &status, &changed);
2695 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
2696 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
2697 * Bits 8 -15 of the cause Rx Tx register indicate that are received
2698 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
2699 * Each CPU has its own causeRxTx register
2701 static int mvneta_poll(struct napi_struct *napi, int budget)
2706 struct mvneta_port *pp = netdev_priv(napi->dev);
2707 struct net_device *ndev = pp->dev;
2708 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports);
2710 if (!netif_running(pp->dev)) {
2711 napi_complete(napi);
2715 /* Read cause register */
2716 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
2717 if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) {
2718 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
2720 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2721 if (pp->use_inband_status && (cause_misc &
2722 (MVNETA_CAUSE_PHY_STATUS_CHANGE |
2723 MVNETA_CAUSE_LINK_CHANGE |
2724 MVNETA_CAUSE_PSC_SYNC_CHANGE))) {
2725 mvneta_fixed_link_update(pp, ndev->phydev);
2729 /* Release Tx descriptors */
2730 if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
2731 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
2732 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
2735 /* For the case where the last mvneta_poll did not process all
2738 rx_queue = fls(((cause_rx_tx >> 8) & 0xff));
2740 cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx :
2744 rx_queue = rx_queue - 1;
2746 rx_done = mvneta_rx_hwbm(pp, budget, &pp->rxqs[rx_queue]);
2748 rx_done = mvneta_rx_swbm(pp, budget, &pp->rxqs[rx_queue]);
2755 napi_complete(napi);
2757 if (pp->neta_armada3700) {
2758 unsigned long flags;
2760 local_irq_save(flags);
2761 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2762 MVNETA_RX_INTR_MASK(rxq_number) |
2763 MVNETA_TX_INTR_MASK(txq_number) |
2764 MVNETA_MISCINTR_INTR_MASK);
2765 local_irq_restore(flags);
2767 enable_percpu_irq(pp->dev->irq, 0);
2771 if (pp->neta_armada3700)
2772 pp->cause_rx_tx = cause_rx_tx;
2774 port->cause_rx_tx = cause_rx_tx;
2779 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
2780 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2785 for (i = 0; i < num; i++) {
2786 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
2787 if (mvneta_rx_refill(pp, rxq->descs + i, rxq) != 0) {
2788 netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n",
2789 __func__, rxq->id, i, num);
2794 /* Add this number of RX descriptors as non occupied (ready to
2797 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
2802 /* Free all packets pending transmit from all TXQs and reset TX port */
2803 static void mvneta_tx_reset(struct mvneta_port *pp)
2807 /* free the skb's in the tx ring */
2808 for (queue = 0; queue < txq_number; queue++)
2809 mvneta_txq_done_force(pp, &pp->txqs[queue]);
2811 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
2812 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
2815 static void mvneta_rx_reset(struct mvneta_port *pp)
2817 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
2818 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
2821 /* Rx/Tx queue initialization/cleanup methods */
2823 /* Create a specified RX queue */
2824 static int mvneta_rxq_init(struct mvneta_port *pp,
2825 struct mvneta_rx_queue *rxq)
2828 rxq->size = pp->rx_ring_size;
2830 /* Allocate memory for RX descriptors */
2831 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2832 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2833 &rxq->descs_phys, GFP_KERNEL);
2834 if (rxq->descs == NULL)
2837 rxq->last_desc = rxq->size - 1;
2839 /* Set Rx descriptors queue starting address */
2840 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
2841 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
2844 mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD - pp->rx_offset_correction);
2846 /* Set coalescing pkts and time */
2847 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2848 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2851 /* Fill RXQ with buffers from RX pool */
2852 mvneta_rxq_buf_size_set(pp, rxq,
2853 MVNETA_RX_BUF_SIZE(pp->pkt_size));
2854 mvneta_rxq_bm_disable(pp, rxq);
2855 mvneta_rxq_fill(pp, rxq, rxq->size);
2857 mvneta_rxq_bm_enable(pp, rxq);
2858 mvneta_rxq_long_pool_set(pp, rxq);
2859 mvneta_rxq_short_pool_set(pp, rxq);
2860 mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size);
2866 /* Cleanup Rx queue */
2867 static void mvneta_rxq_deinit(struct mvneta_port *pp,
2868 struct mvneta_rx_queue *rxq)
2870 mvneta_rxq_drop_pkts(pp, rxq);
2873 dma_free_coherent(pp->dev->dev.parent,
2874 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2880 rxq->next_desc_to_proc = 0;
2881 rxq->descs_phys = 0;
2884 /* Create and initialize a tx queue */
2885 static int mvneta_txq_init(struct mvneta_port *pp,
2886 struct mvneta_tx_queue *txq)
2890 txq->size = pp->tx_ring_size;
2892 /* A queue must always have room for at least one skb.
2893 * Therefore, stop the queue when the free entries reaches
2894 * the maximum number of descriptors per skb.
2896 txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS;
2897 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2900 /* Allocate memory for TX descriptors */
2901 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2902 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2903 &txq->descs_phys, GFP_KERNEL);
2904 if (txq->descs == NULL)
2907 txq->last_desc = txq->size - 1;
2909 /* Set maximum bandwidth for enabled TXQs */
2910 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
2911 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
2913 /* Set Tx descriptors queue starting address */
2914 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
2915 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
2917 txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL);
2918 if (txq->tx_skb == NULL) {
2919 dma_free_coherent(pp->dev->dev.parent,
2920 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2921 txq->descs, txq->descs_phys);
2925 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2926 txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent,
2927 txq->size * TSO_HEADER_SIZE,
2928 &txq->tso_hdrs_phys, GFP_KERNEL);
2929 if (txq->tso_hdrs == NULL) {
2931 dma_free_coherent(pp->dev->dev.parent,
2932 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2933 txq->descs, txq->descs_phys);
2936 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2938 /* Setup XPS mapping */
2940 cpu = txq->id % num_present_cpus();
2942 cpu = pp->rxq_def % num_present_cpus();
2943 cpumask_set_cpu(cpu, &txq->affinity_mask);
2944 netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id);
2949 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2950 static void mvneta_txq_deinit(struct mvneta_port *pp,
2951 struct mvneta_tx_queue *txq)
2956 dma_free_coherent(pp->dev->dev.parent,
2957 txq->size * TSO_HEADER_SIZE,
2958 txq->tso_hdrs, txq->tso_hdrs_phys);
2960 dma_free_coherent(pp->dev->dev.parent,
2961 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2962 txq->descs, txq->descs_phys);
2966 txq->next_desc_to_proc = 0;
2967 txq->descs_phys = 0;
2969 /* Set minimum bandwidth for disabled TXQs */
2970 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
2971 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
2973 /* Set Tx descriptors queue starting address and size */
2974 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
2975 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
2978 /* Cleanup all Tx queues */
2979 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
2983 for (queue = 0; queue < txq_number; queue++)
2984 mvneta_txq_deinit(pp, &pp->txqs[queue]);
2987 /* Cleanup all Rx queues */
2988 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
2992 for (queue = 0; queue < txq_number; queue++)
2993 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
2997 /* Init all Rx queues */
2998 static int mvneta_setup_rxqs(struct mvneta_port *pp)
3002 for (queue = 0; queue < rxq_number; queue++) {
3003 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
3006 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
3008 mvneta_cleanup_rxqs(pp);
3016 /* Init all tx queues */
3017 static int mvneta_setup_txqs(struct mvneta_port *pp)
3021 for (queue = 0; queue < txq_number; queue++) {
3022 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
3024 netdev_err(pp->dev, "%s: can't create txq=%d\n",
3026 mvneta_cleanup_txqs(pp);
3034 static void mvneta_start_dev(struct mvneta_port *pp)
3037 struct net_device *ndev = pp->dev;
3039 mvneta_max_rx_size_set(pp, pp->pkt_size);
3040 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
3042 /* start the Rx/Tx activity */
3043 mvneta_port_enable(pp);
3045 if (!pp->neta_armada3700) {
3046 /* Enable polling on the port */
3047 for_each_online_cpu(cpu) {
3048 struct mvneta_pcpu_port *port =
3049 per_cpu_ptr(pp->ports, cpu);
3051 napi_enable(&port->napi);
3054 napi_enable(&pp->napi);
3057 /* Unmask interrupts. It has to be done from each CPU */
3058 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3060 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3061 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3062 MVNETA_CAUSE_LINK_CHANGE |
3063 MVNETA_CAUSE_PSC_SYNC_CHANGE);
3065 phy_start(ndev->phydev);
3066 netif_tx_start_all_queues(pp->dev);
3069 static void mvneta_stop_dev(struct mvneta_port *pp)
3072 struct net_device *ndev = pp->dev;
3074 phy_stop(ndev->phydev);
3076 if (!pp->neta_armada3700) {
3077 for_each_online_cpu(cpu) {
3078 struct mvneta_pcpu_port *port =
3079 per_cpu_ptr(pp->ports, cpu);
3081 napi_disable(&port->napi);
3084 napi_disable(&pp->napi);
3087 netif_carrier_off(pp->dev);
3089 mvneta_port_down(pp);
3090 netif_tx_stop_all_queues(pp->dev);
3092 /* Stop the port activity */
3093 mvneta_port_disable(pp);
3095 /* Clear all ethernet port interrupts */
3096 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
3098 /* Mask all ethernet port interrupts */
3099 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3101 mvneta_tx_reset(pp);
3102 mvneta_rx_reset(pp);
3105 static void mvneta_percpu_enable(void *arg)
3107 struct mvneta_port *pp = arg;
3109 enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE);
3112 static void mvneta_percpu_disable(void *arg)
3114 struct mvneta_port *pp = arg;
3116 disable_percpu_irq(pp->dev->irq);
3119 /* Change the device mtu */
3120 static int mvneta_change_mtu(struct net_device *dev, int mtu)
3122 struct mvneta_port *pp = netdev_priv(dev);
3125 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
3126 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
3127 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
3128 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
3133 if (!netif_running(dev)) {
3135 mvneta_bm_update_mtu(pp, mtu);
3137 netdev_update_features(dev);
3141 /* The interface is running, so we have to force a
3142 * reallocation of the queues
3144 mvneta_stop_dev(pp);
3145 on_each_cpu(mvneta_percpu_disable, pp, true);
3147 mvneta_cleanup_txqs(pp);
3148 mvneta_cleanup_rxqs(pp);
3151 mvneta_bm_update_mtu(pp, mtu);
3153 pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu);
3154 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
3155 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3157 ret = mvneta_setup_rxqs(pp);
3159 netdev_err(dev, "unable to setup rxqs after MTU change\n");
3163 ret = mvneta_setup_txqs(pp);
3165 netdev_err(dev, "unable to setup txqs after MTU change\n");
3169 on_each_cpu(mvneta_percpu_enable, pp, true);
3170 mvneta_start_dev(pp);
3173 netdev_update_features(dev);
3178 static netdev_features_t mvneta_fix_features(struct net_device *dev,
3179 netdev_features_t features)
3181 struct mvneta_port *pp = netdev_priv(dev);
3183 if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) {
3184 features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO);
3186 "Disable IP checksum for MTU greater than %dB\n",
3193 /* Get mac address */
3194 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
3196 u32 mac_addr_l, mac_addr_h;
3198 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
3199 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
3200 addr[0] = (mac_addr_h >> 24) & 0xFF;
3201 addr[1] = (mac_addr_h >> 16) & 0xFF;
3202 addr[2] = (mac_addr_h >> 8) & 0xFF;
3203 addr[3] = mac_addr_h & 0xFF;
3204 addr[4] = (mac_addr_l >> 8) & 0xFF;
3205 addr[5] = mac_addr_l & 0xFF;
3208 /* Handle setting mac address */
3209 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
3211 struct mvneta_port *pp = netdev_priv(dev);
3212 struct sockaddr *sockaddr = addr;
3215 ret = eth_prepare_mac_addr_change(dev, addr);
3218 /* Remove previous address table entry */
3219 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
3221 /* Set new addr in hw */
3222 mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def);
3224 eth_commit_mac_addr_change(dev, addr);
3228 static void mvneta_adjust_link(struct net_device *ndev)
3230 struct mvneta_port *pp = netdev_priv(ndev);
3231 struct phy_device *phydev = ndev->phydev;
3232 int status_change = 0;
3235 if ((pp->speed != phydev->speed) ||
3236 (pp->duplex != phydev->duplex)) {
3239 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3240 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
3241 MVNETA_GMAC_CONFIG_GMII_SPEED |
3242 MVNETA_GMAC_CONFIG_FULL_DUPLEX);
3245 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
3247 if (phydev->speed == SPEED_1000)
3248 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
3249 else if (phydev->speed == SPEED_100)
3250 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
3252 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
3254 pp->duplex = phydev->duplex;
3255 pp->speed = phydev->speed;
3259 if (phydev->link != pp->link) {
3260 if (!phydev->link) {
3265 pp->link = phydev->link;
3269 if (status_change) {
3271 if (!pp->use_inband_status) {
3272 u32 val = mvreg_read(pp,
3273 MVNETA_GMAC_AUTONEG_CONFIG);
3274 val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
3275 val |= MVNETA_GMAC_FORCE_LINK_PASS;
3276 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3281 if (!pp->use_inband_status) {
3282 u32 val = mvreg_read(pp,
3283 MVNETA_GMAC_AUTONEG_CONFIG);
3284 val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
3285 val |= MVNETA_GMAC_FORCE_LINK_DOWN;
3286 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
3289 mvneta_port_down(pp);
3291 phy_print_status(phydev);
3295 static int mvneta_mdio_probe(struct mvneta_port *pp)
3297 struct phy_device *phy_dev;
3299 phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
3302 netdev_err(pp->dev, "could not find the PHY\n");
3306 phy_dev->supported &= PHY_GBIT_FEATURES;
3307 phy_dev->advertising = phy_dev->supported;
3316 static void mvneta_mdio_remove(struct mvneta_port *pp)
3318 struct net_device *ndev = pp->dev;
3320 phy_disconnect(ndev->phydev);
3323 /* Electing a CPU must be done in an atomic way: it should be done
3324 * after or before the removal/insertion of a CPU and this function is
3327 static void mvneta_percpu_elect(struct mvneta_port *pp)
3329 int elected_cpu = 0, max_cpu, cpu, i = 0;
3331 /* Use the cpu associated to the rxq when it is online, in all
3332 * the other cases, use the cpu 0 which can't be offline.
3334 if (cpu_online(pp->rxq_def))
3335 elected_cpu = pp->rxq_def;
3337 max_cpu = num_present_cpus();
3339 for_each_online_cpu(cpu) {
3340 int rxq_map = 0, txq_map = 0;
3343 for (rxq = 0; rxq < rxq_number; rxq++)
3344 if ((rxq % max_cpu) == cpu)
3345 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq);
3347 if (cpu == elected_cpu)
3348 /* Map the default receive queue queue to the
3351 rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def);
3353 /* We update the TX queue map only if we have one
3354 * queue. In this case we associate the TX queue to
3355 * the CPU bound to the default RX queue
3357 if (txq_number == 1)
3358 txq_map = (cpu == elected_cpu) ?
3359 MVNETA_CPU_TXQ_ACCESS(1) : 0;
3361 txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) &
3362 MVNETA_CPU_TXQ_ACCESS_ALL_MASK;
3364 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map);
3366 /* Update the interrupt mask on each CPU according the
3369 smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
3376 static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node)
3379 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3381 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3384 spin_lock(&pp->lock);
3386 * Configuring the driver for a new CPU while the driver is
3387 * stopping is racy, so just avoid it.
3389 if (pp->is_stopped) {
3390 spin_unlock(&pp->lock);
3393 netif_tx_stop_all_queues(pp->dev);
3396 * We have to synchronise on tha napi of each CPU except the one
3397 * just being woken up
3399 for_each_online_cpu(other_cpu) {
3400 if (other_cpu != cpu) {
3401 struct mvneta_pcpu_port *other_port =
3402 per_cpu_ptr(pp->ports, other_cpu);
3404 napi_synchronize(&other_port->napi);
3408 /* Mask all ethernet port interrupts */
3409 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3410 napi_enable(&port->napi);
3413 * Enable per-CPU interrupts on the CPU that is
3416 mvneta_percpu_enable(pp);
3419 * Enable per-CPU interrupt on the one CPU we care
3422 mvneta_percpu_elect(pp);
3424 /* Unmask all ethernet port interrupts */
3425 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3426 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3427 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3428 MVNETA_CAUSE_LINK_CHANGE |
3429 MVNETA_CAUSE_PSC_SYNC_CHANGE);
3430 netif_tx_start_all_queues(pp->dev);
3431 spin_unlock(&pp->lock);
3435 static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node)
3437 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3439 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
3442 * Thanks to this lock we are sure that any pending cpu election is
3445 spin_lock(&pp->lock);
3446 /* Mask all ethernet port interrupts */
3447 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3448 spin_unlock(&pp->lock);
3450 napi_synchronize(&port->napi);
3451 napi_disable(&port->napi);
3452 /* Disable per-CPU interrupts on the CPU that is brought down. */
3453 mvneta_percpu_disable(pp);
3457 static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node)
3459 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port,
3462 /* Check if a new CPU must be elected now this on is down */
3463 spin_lock(&pp->lock);
3464 mvneta_percpu_elect(pp);
3465 spin_unlock(&pp->lock);
3466 /* Unmask all ethernet port interrupts */
3467 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
3468 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
3469 MVNETA_CAUSE_PHY_STATUS_CHANGE |
3470 MVNETA_CAUSE_LINK_CHANGE |
3471 MVNETA_CAUSE_PSC_SYNC_CHANGE);
3472 netif_tx_start_all_queues(pp->dev);
3476 static int mvneta_open(struct net_device *dev)
3478 struct mvneta_port *pp = netdev_priv(dev);
3481 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
3482 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
3483 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3485 ret = mvneta_setup_rxqs(pp);
3489 ret = mvneta_setup_txqs(pp);
3491 goto err_cleanup_rxqs;
3493 /* Connect to port interrupt line */
3494 if (pp->neta_armada3700)
3495 ret = request_irq(pp->dev->irq, mvneta_isr, 0,
3498 ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr,
3499 dev->name, pp->ports);
3501 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
3502 goto err_cleanup_txqs;
3505 if (!pp->neta_armada3700) {
3506 /* Enable per-CPU interrupt on all the CPU to handle our RX
3509 on_each_cpu(mvneta_percpu_enable, pp, true);
3511 pp->is_stopped = false;
3512 /* Register a CPU notifier to handle the case where our CPU
3513 * might be taken offline.
3515 ret = cpuhp_state_add_instance_nocalls(online_hpstate,
3520 ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3523 goto err_free_online_hp;
3526 /* In default link is down */
3527 netif_carrier_off(pp->dev);
3529 ret = mvneta_mdio_probe(pp);
3531 netdev_err(dev, "cannot probe MDIO bus\n");
3532 goto err_free_dead_hp;
3535 mvneta_start_dev(pp);
3540 if (!pp->neta_armada3700)
3541 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3544 if (!pp->neta_armada3700)
3545 cpuhp_state_remove_instance_nocalls(online_hpstate,
3548 if (pp->neta_armada3700) {
3549 free_irq(pp->dev->irq, pp);
3551 on_each_cpu(mvneta_percpu_disable, pp, true);
3552 free_percpu_irq(pp->dev->irq, pp->ports);
3555 mvneta_cleanup_txqs(pp);
3557 mvneta_cleanup_rxqs(pp);
3561 /* Stop the port, free port interrupt line */
3562 static int mvneta_stop(struct net_device *dev)
3564 struct mvneta_port *pp = netdev_priv(dev);
3566 if (!pp->neta_armada3700) {
3567 /* Inform that we are stopping so we don't want to setup the
3568 * driver for new CPUs in the notifiers. The code of the
3569 * notifier for CPU online is protected by the same spinlock,
3570 * so when we get the lock, the notifer work is done.
3572 spin_lock(&pp->lock);
3573 pp->is_stopped = true;
3574 spin_unlock(&pp->lock);
3576 mvneta_stop_dev(pp);
3577 mvneta_mdio_remove(pp);
3579 cpuhp_state_remove_instance_nocalls(online_hpstate,
3581 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD,
3583 on_each_cpu(mvneta_percpu_disable, pp, true);
3584 free_percpu_irq(dev->irq, pp->ports);
3586 mvneta_stop_dev(pp);
3587 mvneta_mdio_remove(pp);
3588 free_irq(dev->irq, pp);
3591 mvneta_cleanup_rxqs(pp);
3592 mvneta_cleanup_txqs(pp);
3597 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3602 return phy_mii_ioctl(dev->phydev, ifr, cmd);
3605 /* Ethtool methods */
3607 /* Set link ksettings (phy address, speed) for ethtools */
3609 mvneta_ethtool_set_link_ksettings(struct net_device *ndev,
3610 const struct ethtool_link_ksettings *cmd)
3612 struct mvneta_port *pp = netdev_priv(ndev);
3613 struct phy_device *phydev = ndev->phydev;
3618 if ((cmd->base.autoneg == AUTONEG_ENABLE) != pp->use_inband_status) {
3621 mvneta_set_autoneg(pp, cmd->base.autoneg == AUTONEG_ENABLE);
3623 if (cmd->base.autoneg == AUTONEG_DISABLE) {
3624 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
3625 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
3626 MVNETA_GMAC_CONFIG_GMII_SPEED |
3627 MVNETA_GMAC_CONFIG_FULL_DUPLEX);
3630 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
3632 if (phydev->speed == SPEED_1000)
3633 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
3634 else if (phydev->speed == SPEED_100)
3635 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
3637 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
3640 pp->use_inband_status = (cmd->base.autoneg == AUTONEG_ENABLE);
3641 netdev_info(pp->dev, "autoneg status set to %i\n",
3642 pp->use_inband_status);
3644 if (netif_running(ndev)) {
3645 mvneta_port_down(pp);
3650 return phy_ethtool_ksettings_set(ndev->phydev, cmd);
3653 /* Set interrupt coalescing for ethtools */
3654 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
3655 struct ethtool_coalesce *c)
3657 struct mvneta_port *pp = netdev_priv(dev);
3660 for (queue = 0; queue < rxq_number; queue++) {
3661 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
3662 rxq->time_coal = c->rx_coalesce_usecs;
3663 rxq->pkts_coal = c->rx_max_coalesced_frames;
3664 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
3665 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
3668 for (queue = 0; queue < txq_number; queue++) {
3669 struct mvneta_tx_queue *txq = &pp->txqs[queue];
3670 txq->done_pkts_coal = c->tx_max_coalesced_frames;
3671 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
3677 /* get coalescing for ethtools */
3678 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
3679 struct ethtool_coalesce *c)
3681 struct mvneta_port *pp = netdev_priv(dev);
3683 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
3684 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
3686 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
3691 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
3692 struct ethtool_drvinfo *drvinfo)
3694 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
3695 sizeof(drvinfo->driver));
3696 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
3697 sizeof(drvinfo->version));
3698 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
3699 sizeof(drvinfo->bus_info));
3703 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
3704 struct ethtool_ringparam *ring)
3706 struct mvneta_port *pp = netdev_priv(netdev);
3708 ring->rx_max_pending = MVNETA_MAX_RXD;
3709 ring->tx_max_pending = MVNETA_MAX_TXD;
3710 ring->rx_pending = pp->rx_ring_size;
3711 ring->tx_pending = pp->tx_ring_size;
3714 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
3715 struct ethtool_ringparam *ring)
3717 struct mvneta_port *pp = netdev_priv(dev);
3719 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
3721 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
3722 ring->rx_pending : MVNETA_MAX_RXD;
3724 pp->tx_ring_size = clamp_t(u16, ring->tx_pending,
3725 MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD);
3726 if (pp->tx_ring_size != ring->tx_pending)
3727 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
3728 pp->tx_ring_size, ring->tx_pending);
3730 if (netif_running(dev)) {
3732 if (mvneta_open(dev)) {
3734 "error on opening device after ring param change\n");
3742 static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset,
3745 if (sset == ETH_SS_STATS) {
3748 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
3749 memcpy(data + i * ETH_GSTRING_LEN,
3750 mvneta_statistics[i].name, ETH_GSTRING_LEN);
3754 static void mvneta_ethtool_update_stats(struct mvneta_port *pp)
3756 const struct mvneta_statistic *s;
3757 void __iomem *base = pp->base;
3762 for (i = 0, s = mvneta_statistics;
3763 s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics);
3767 val = readl_relaxed(base + s->offset);
3768 pp->ethtool_stats[i] += val;
3771 /* Docs say to read low 32-bit then high */
3772 low = readl_relaxed(base + s->offset);
3773 high = readl_relaxed(base + s->offset + 4);
3774 val64 = (u64)high << 32 | low;
3775 pp->ethtool_stats[i] += val64;
3781 static void mvneta_ethtool_get_stats(struct net_device *dev,
3782 struct ethtool_stats *stats, u64 *data)
3784 struct mvneta_port *pp = netdev_priv(dev);
3787 mvneta_ethtool_update_stats(pp);
3789 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++)
3790 *data++ = pp->ethtool_stats[i];
3793 static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset)
3795 if (sset == ETH_SS_STATS)
3796 return ARRAY_SIZE(mvneta_statistics);
3800 static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev)
3802 return MVNETA_RSS_LU_TABLE_SIZE;
3805 static int mvneta_ethtool_get_rxnfc(struct net_device *dev,
3806 struct ethtool_rxnfc *info,
3807 u32 *rules __always_unused)
3809 switch (info->cmd) {
3810 case ETHTOOL_GRXRINGS:
3811 info->data = rxq_number;
3820 static int mvneta_config_rss(struct mvneta_port *pp)
3825 netif_tx_stop_all_queues(pp->dev);
3827 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
3829 /* We have to synchronise on the napi of each CPU */
3830 for_each_online_cpu(cpu) {
3831 struct mvneta_pcpu_port *pcpu_port =
3832 per_cpu_ptr(pp->ports, cpu);
3834 napi_synchronize(&pcpu_port->napi);
3835 napi_disable(&pcpu_port->napi);
3838 pp->rxq_def = pp->indir[0];
3840 /* Update unicast mapping */
3841 mvneta_set_rx_mode(pp->dev);
3843 /* Update val of portCfg register accordingly with all RxQueue types */
3844 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def);
3845 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
3847 /* Update the elected CPU matching the new rxq_def */
3848 spin_lock(&pp->lock);
3849 mvneta_percpu_elect(pp);
3850 spin_unlock(&pp->lock);
3852 /* We have to synchronise on the napi of each CPU */
3853 for_each_online_cpu(cpu) {
3854 struct mvneta_pcpu_port *pcpu_port =
3855 per_cpu_ptr(pp->ports, cpu);
3857 napi_enable(&pcpu_port->napi);
3860 netif_tx_start_all_queues(pp->dev);
3865 static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
3866 const u8 *key, const u8 hfunc)
3868 struct mvneta_port *pp = netdev_priv(dev);
3870 /* Current code for Armada 3700 doesn't support RSS features yet */
3871 if (pp->neta_armada3700)
3874 /* We require at least one supported parameter to be changed
3875 * and no change in any of the unsupported parameters
3878 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3884 memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE);
3886 return mvneta_config_rss(pp);
3889 static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3892 struct mvneta_port *pp = netdev_priv(dev);
3894 /* Current code for Armada 3700 doesn't support RSS features yet */
3895 if (pp->neta_armada3700)
3899 *hfunc = ETH_RSS_HASH_TOP;
3904 memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE);
3909 static const struct net_device_ops mvneta_netdev_ops = {
3910 .ndo_open = mvneta_open,
3911 .ndo_stop = mvneta_stop,
3912 .ndo_start_xmit = mvneta_tx,
3913 .ndo_set_rx_mode = mvneta_set_rx_mode,
3914 .ndo_set_mac_address = mvneta_set_mac_addr,
3915 .ndo_change_mtu = mvneta_change_mtu,
3916 .ndo_fix_features = mvneta_fix_features,
3917 .ndo_get_stats64 = mvneta_get_stats64,
3918 .ndo_do_ioctl = mvneta_ioctl,
3921 const struct ethtool_ops mvneta_eth_tool_ops = {
3922 .nway_reset = phy_ethtool_nway_reset,
3923 .get_link = ethtool_op_get_link,
3924 .set_coalesce = mvneta_ethtool_set_coalesce,
3925 .get_coalesce = mvneta_ethtool_get_coalesce,
3926 .get_drvinfo = mvneta_ethtool_get_drvinfo,
3927 .get_ringparam = mvneta_ethtool_get_ringparam,
3928 .set_ringparam = mvneta_ethtool_set_ringparam,
3929 .get_strings = mvneta_ethtool_get_strings,
3930 .get_ethtool_stats = mvneta_ethtool_get_stats,
3931 .get_sset_count = mvneta_ethtool_get_sset_count,
3932 .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size,
3933 .get_rxnfc = mvneta_ethtool_get_rxnfc,
3934 .get_rxfh = mvneta_ethtool_get_rxfh,
3935 .set_rxfh = mvneta_ethtool_set_rxfh,
3936 .get_link_ksettings = phy_ethtool_get_link_ksettings,
3937 .set_link_ksettings = mvneta_ethtool_set_link_ksettings,
3941 static int mvneta_init(struct device *dev, struct mvneta_port *pp)
3946 mvneta_port_disable(pp);
3948 /* Set port default values */
3949 mvneta_defaults_set(pp);
3951 pp->txqs = devm_kcalloc(dev, txq_number, sizeof(struct mvneta_tx_queue),
3956 /* Initialize TX descriptor rings */
3957 for (queue = 0; queue < txq_number; queue++) {
3958 struct mvneta_tx_queue *txq = &pp->txqs[queue];
3960 txq->size = pp->tx_ring_size;
3961 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
3964 pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(struct mvneta_rx_queue),
3969 /* Create Rx descriptor rings */
3970 for (queue = 0; queue < rxq_number; queue++) {
3971 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
3973 rxq->size = pp->rx_ring_size;
3974 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
3975 rxq->time_coal = MVNETA_RX_COAL_USEC;
3976 rxq->buf_virt_addr = devm_kmalloc(pp->dev->dev.parent,
3977 rxq->size * sizeof(void *),
3979 if (!rxq->buf_virt_addr)
3986 /* platform glue : initialize decoding windows */
3987 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
3988 const struct mbus_dram_target_info *dram)
3994 for (i = 0; i < 6; i++) {
3995 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
3996 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
3999 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
4006 for (i = 0; i < dram->num_cs; i++) {
4007 const struct mbus_dram_window *cs = dram->cs + i;
4009 mvreg_write(pp, MVNETA_WIN_BASE(i),
4010 (cs->base & 0xffff0000) |
4011 (cs->mbus_attr << 8) |
4012 dram->mbus_dram_target_id);
4014 mvreg_write(pp, MVNETA_WIN_SIZE(i),
4015 (cs->size - 1) & 0xffff0000);
4017 win_enable &= ~(1 << i);
4018 win_protect |= 3 << (2 * i);
4021 /* For Armada3700 open default 4GB Mbus window, leaving
4022 * arbitration of target/attribute to a different layer
4025 mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000);
4026 win_enable &= ~BIT(0);
4030 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
4031 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect);
4034 /* Power up the port */
4035 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
4039 /* MAC Cause register should be cleared */
4040 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
4042 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
4044 /* Even though it might look weird, when we're configured in
4045 * SGMII or QSGMII mode, the RGMII bit needs to be set.
4048 case PHY_INTERFACE_MODE_QSGMII:
4049 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
4050 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
4052 case PHY_INTERFACE_MODE_SGMII:
4053 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
4054 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
4056 case PHY_INTERFACE_MODE_RGMII:
4057 case PHY_INTERFACE_MODE_RGMII_ID:
4058 ctrl |= MVNETA_GMAC2_PORT_RGMII;
4064 /* Cancel Port Reset */
4065 ctrl &= ~MVNETA_GMAC2_PORT_RESET;
4066 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
4068 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
4069 MVNETA_GMAC2_PORT_RESET) != 0)
4075 /* Device initialization routine */
4076 static int mvneta_probe(struct platform_device *pdev)
4078 const struct mbus_dram_target_info *dram_target_info;
4079 struct resource *res;
4080 struct device_node *dn = pdev->dev.of_node;
4081 struct device_node *phy_node;
4082 struct device_node *bm_node;
4083 struct mvneta_port *pp;
4084 struct net_device *dev;
4085 const char *dt_mac_addr;
4086 char hw_mac_addr[ETH_ALEN];
4087 const char *mac_from;
4088 const char *managed;
4094 dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
4098 dev->irq = irq_of_parse_and_map(dn, 0);
4099 if (dev->irq == 0) {
4101 goto err_free_netdev;
4104 phy_node = of_parse_phandle(dn, "phy", 0);
4106 if (!of_phy_is_fixed_link(dn)) {
4107 dev_err(&pdev->dev, "no PHY specified\n");
4112 err = of_phy_register_fixed_link(dn);
4114 dev_err(&pdev->dev, "cannot register fixed PHY\n");
4118 /* In the case of a fixed PHY, the DT node associated
4119 * to the PHY is the Ethernet MAC DT node.
4121 phy_node = of_node_get(dn);
4124 phy_mode = of_get_phy_mode(dn);
4126 dev_err(&pdev->dev, "incorrect phy-mode\n");
4128 goto err_put_phy_node;
4131 dev->tx_queue_len = MVNETA_MAX_TXD;
4132 dev->watchdog_timeo = 5 * HZ;
4133 dev->netdev_ops = &mvneta_netdev_ops;
4135 dev->ethtool_ops = &mvneta_eth_tool_ops;
4137 pp = netdev_priv(dev);
4138 spin_lock_init(&pp->lock);
4139 pp->phy_node = phy_node;
4140 pp->phy_interface = phy_mode;
4142 err = of_property_read_string(dn, "managed", &managed);
4143 pp->use_inband_status = (err == 0 &&
4144 strcmp(managed, "in-band-status") == 0);
4146 pp->rxq_def = rxq_def;
4148 /* Set RX packet offset correction for platforms, whose
4149 * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit
4150 * platforms and 0B for 32-bit ones.
4152 pp->rx_offset_correction =
4153 max(0, NET_SKB_PAD - MVNETA_RX_PKT_OFFSET_CORRECTION);
4155 pp->indir[0] = rxq_def;
4157 /* Get special SoC configurations */
4158 if (of_device_is_compatible(dn, "marvell,armada-3700-neta"))
4159 pp->neta_armada3700 = true;
4161 pp->clk = devm_clk_get(&pdev->dev, "core");
4162 if (IS_ERR(pp->clk))
4163 pp->clk = devm_clk_get(&pdev->dev, NULL);
4164 if (IS_ERR(pp->clk)) {
4165 err = PTR_ERR(pp->clk);
4166 goto err_put_phy_node;
4169 clk_prepare_enable(pp->clk);
4171 pp->clk_bus = devm_clk_get(&pdev->dev, "bus");
4172 if (!IS_ERR(pp->clk_bus))
4173 clk_prepare_enable(pp->clk_bus);
4175 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4176 pp->base = devm_ioremap_resource(&pdev->dev, res);
4177 if (IS_ERR(pp->base)) {
4178 err = PTR_ERR(pp->base);
4182 /* Alloc per-cpu port structure */
4183 pp->ports = alloc_percpu(struct mvneta_pcpu_port);
4189 /* Alloc per-cpu stats */
4190 pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats);
4193 goto err_free_ports;
4196 dt_mac_addr = of_get_mac_address(dn);
4198 mac_from = "device tree";
4199 memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN);
4201 mvneta_get_mac_addr(pp, hw_mac_addr);
4202 if (is_valid_ether_addr(hw_mac_addr)) {
4203 mac_from = "hardware";
4204 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
4206 mac_from = "random";
4207 eth_hw_addr_random(dev);
4211 if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) {
4212 if (tx_csum_limit < 0 ||
4213 tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) {
4214 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
4215 dev_info(&pdev->dev,
4216 "Wrong TX csum limit in DT, set to %dB\n",
4217 MVNETA_TX_CSUM_DEF_SIZE);
4219 } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) {
4220 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE;
4222 tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE;
4225 pp->tx_csum_limit = tx_csum_limit;
4227 dram_target_info = mv_mbus_dram_info();
4228 /* Armada3700 requires setting default configuration of Mbus
4229 * windows, however without using filled mbus_dram_target_info
4232 if (dram_target_info || pp->neta_armada3700)
4233 mvneta_conf_mbus_windows(pp, dram_target_info);
4235 pp->tx_ring_size = MVNETA_MAX_TXD;
4236 pp->rx_ring_size = MVNETA_MAX_RXD;
4239 SET_NETDEV_DEV(dev, &pdev->dev);
4241 pp->id = global_port_id++;
4243 /* Obtain access to BM resources if enabled and already initialized */
4244 bm_node = of_parse_phandle(dn, "buffer-manager", 0);
4245 if (bm_node && bm_node->data) {
4246 pp->bm_priv = bm_node->data;
4247 err = mvneta_bm_port_init(pdev, pp);
4249 dev_info(&pdev->dev, "use SW buffer management\n");
4253 of_node_put(bm_node);
4255 err = mvneta_init(&pdev->dev, pp);
4259 err = mvneta_port_power_up(pp, phy_mode);
4261 dev_err(&pdev->dev, "can't power up port\n");
4265 /* Armada3700 network controller does not support per-cpu
4266 * operation, so only single NAPI should be initialized.
4268 if (pp->neta_armada3700) {
4269 netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT);
4271 for_each_present_cpu(cpu) {
4272 struct mvneta_pcpu_port *port =
4273 per_cpu_ptr(pp->ports, cpu);
4275 netif_napi_add(dev, &port->napi, mvneta_poll,
4281 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
4282 dev->hw_features |= dev->features;
4283 dev->vlan_features |= dev->features;
4284 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
4285 dev->gso_max_segs = MVNETA_MAX_TSO_SEGS;
4287 /* MTU range: 68 - 9676 */
4288 dev->min_mtu = ETH_MIN_MTU;
4289 /* 9676 == 9700 - 20 and rounding to 8 */
4290 dev->max_mtu = 9676;
4292 err = register_netdev(dev);
4294 dev_err(&pdev->dev, "failed to register\n");
4295 goto err_free_stats;
4298 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
4301 platform_set_drvdata(pdev, pp->dev);
4303 if (pp->use_inband_status) {
4304 struct phy_device *phy = of_phy_find_device(dn);
4306 mvneta_fixed_link_update(pp, phy);
4308 put_device(&phy->mdio.dev);
4314 unregister_netdev(dev);
4316 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
4317 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
4321 free_percpu(pp->stats);
4323 free_percpu(pp->ports);
4325 clk_disable_unprepare(pp->clk_bus);
4326 clk_disable_unprepare(pp->clk);
4328 of_node_put(phy_node);
4329 if (of_phy_is_fixed_link(dn))
4330 of_phy_deregister_fixed_link(dn);
4332 irq_dispose_mapping(dev->irq);
4338 /* Device removal routine */
4339 static int mvneta_remove(struct platform_device *pdev)
4341 struct net_device *dev = platform_get_drvdata(pdev);
4342 struct device_node *dn = pdev->dev.of_node;
4343 struct mvneta_port *pp = netdev_priv(dev);
4345 unregister_netdev(dev);
4346 clk_disable_unprepare(pp->clk_bus);
4347 clk_disable_unprepare(pp->clk);
4348 free_percpu(pp->ports);
4349 free_percpu(pp->stats);
4350 if (of_phy_is_fixed_link(dn))
4351 of_phy_deregister_fixed_link(dn);
4352 irq_dispose_mapping(dev->irq);
4353 of_node_put(pp->phy_node);
4357 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id);
4358 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short,
4365 static const struct of_device_id mvneta_match[] = {
4366 { .compatible = "marvell,armada-370-neta" },
4367 { .compatible = "marvell,armada-xp-neta" },
4368 { .compatible = "marvell,armada-3700-neta" },
4371 MODULE_DEVICE_TABLE(of, mvneta_match);
4373 static struct platform_driver mvneta_driver = {
4374 .probe = mvneta_probe,
4375 .remove = mvneta_remove,
4377 .name = MVNETA_DRIVER_NAME,
4378 .of_match_table = mvneta_match,
4382 static int __init mvneta_driver_init(void)
4386 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvmeta:online",
4388 mvneta_cpu_down_prepare);
4391 online_hpstate = ret;
4392 ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead",
4393 NULL, mvneta_cpu_dead);
4397 ret = platform_driver_register(&mvneta_driver);
4403 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
4405 cpuhp_remove_multi_state(online_hpstate);
4409 module_init(mvneta_driver_init);
4411 static void __exit mvneta_driver_exit(void)
4413 platform_driver_unregister(&mvneta_driver);
4414 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD);
4415 cpuhp_remove_multi_state(online_hpstate);
4417 module_exit(mvneta_driver_exit);
4419 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
4420 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
4421 MODULE_LICENSE("GPL");
4423 module_param(rxq_number, int, S_IRUGO);
4424 module_param(txq_number, int, S_IRUGO);
4426 module_param(rxq_def, int, S_IRUGO);
4427 module_param(rx_copybreak, int, S_IRUGO | S_IWUSR);