1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
4 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
6 * Based on the 64360 driver from:
7 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
8 * Rabeeh Khoury <rabeeh@marvell.com>
10 * Copyright (C) 2003 PMC-Sierra, Inc.,
11 * written by Manish Lachwani
13 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
15 * Copyright (C) 2004-2006 MontaVista Software, Inc.
16 * Dale Farnsworth <dale@farnsworth.org>
18 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
19 * <sjhill@realitydiluted.com>
21 * Copyright (C) 2007-2008 Marvell Semiconductor
22 * Lennert Buytenhek <buytenh@marvell.com>
24 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
27 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29 #include <linux/init.h>
30 #include <linux/dma-mapping.h>
34 #include <linux/tcp.h>
35 #include <linux/udp.h>
36 #include <linux/etherdevice.h>
37 #include <linux/delay.h>
38 #include <linux/ethtool.h>
39 #include <linux/platform_device.h>
40 #include <linux/module.h>
41 #include <linux/kernel.h>
42 #include <linux/spinlock.h>
43 #include <linux/workqueue.h>
44 #include <linux/phy.h>
45 #include <linux/mv643xx_eth.h>
47 #include <linux/interrupt.h>
48 #include <linux/types.h>
49 #include <linux/slab.h>
50 #include <linux/clk.h>
52 #include <linux/of_irq.h>
53 #include <linux/of_net.h>
54 #include <linux/of_mdio.h>
56 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
57 static char mv643xx_eth_driver_version[] = "1.4";
61 * Registers shared between all ports.
63 #define PHY_ADDR 0x0000
64 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
65 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
66 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
67 #define WINDOW_BAR_ENABLE 0x0290
68 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
71 * Main per-port registers. These live at offset 0x0400 for
72 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
74 #define PORT_CONFIG 0x0000
75 #define UNICAST_PROMISCUOUS_MODE 0x00000001
76 #define PORT_CONFIG_EXT 0x0004
77 #define MAC_ADDR_LOW 0x0014
78 #define MAC_ADDR_HIGH 0x0018
79 #define SDMA_CONFIG 0x001c
80 #define TX_BURST_SIZE_16_64BIT 0x01000000
81 #define TX_BURST_SIZE_4_64BIT 0x00800000
82 #define BLM_TX_NO_SWAP 0x00000020
83 #define BLM_RX_NO_SWAP 0x00000010
84 #define RX_BURST_SIZE_16_64BIT 0x00000008
85 #define RX_BURST_SIZE_4_64BIT 0x00000004
86 #define PORT_SERIAL_CONTROL 0x003c
87 #define SET_MII_SPEED_TO_100 0x01000000
88 #define SET_GMII_SPEED_TO_1000 0x00800000
89 #define SET_FULL_DUPLEX_MODE 0x00200000
90 #define MAX_RX_PACKET_9700BYTE 0x000a0000
91 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
92 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
93 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
94 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
95 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
96 #define FORCE_LINK_PASS 0x00000002
97 #define SERIAL_PORT_ENABLE 0x00000001
98 #define PORT_STATUS 0x0044
99 #define TX_FIFO_EMPTY 0x00000400
100 #define TX_IN_PROGRESS 0x00000080
101 #define PORT_SPEED_MASK 0x00000030
102 #define PORT_SPEED_1000 0x00000010
103 #define PORT_SPEED_100 0x00000020
104 #define PORT_SPEED_10 0x00000000
105 #define FLOW_CONTROL_ENABLED 0x00000008
106 #define FULL_DUPLEX 0x00000004
107 #define LINK_UP 0x00000002
108 #define TXQ_COMMAND 0x0048
109 #define TXQ_FIX_PRIO_CONF 0x004c
110 #define PORT_SERIAL_CONTROL1 0x004c
111 #define CLK125_BYPASS_EN 0x00000010
112 #define TX_BW_RATE 0x0050
113 #define TX_BW_MTU 0x0058
114 #define TX_BW_BURST 0x005c
115 #define INT_CAUSE 0x0060
116 #define INT_TX_END 0x07f80000
117 #define INT_TX_END_0 0x00080000
118 #define INT_RX 0x000003fc
119 #define INT_RX_0 0x00000004
120 #define INT_EXT 0x00000002
121 #define INT_CAUSE_EXT 0x0064
122 #define INT_EXT_LINK_PHY 0x00110000
123 #define INT_EXT_TX 0x000000ff
124 #define INT_MASK 0x0068
125 #define INT_MASK_EXT 0x006c
126 #define TX_FIFO_URGENT_THRESHOLD 0x0074
127 #define RX_DISCARD_FRAME_CNT 0x0084
128 #define RX_OVERRUN_FRAME_CNT 0x0088
129 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
130 #define TX_BW_RATE_MOVED 0x00e0
131 #define TX_BW_MTU_MOVED 0x00e8
132 #define TX_BW_BURST_MOVED 0x00ec
133 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
134 #define RXQ_COMMAND 0x0280
135 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
136 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
137 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
138 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
141 * Misc per-port registers.
143 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
144 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
145 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
146 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
150 * SDMA configuration register default value.
152 #if defined(__BIG_ENDIAN)
153 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
154 (RX_BURST_SIZE_4_64BIT | \
155 TX_BURST_SIZE_4_64BIT)
156 #elif defined(__LITTLE_ENDIAN)
157 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
158 (RX_BURST_SIZE_4_64BIT | \
161 TX_BURST_SIZE_4_64BIT)
163 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
170 #define DEFAULT_RX_QUEUE_SIZE 128
171 #define DEFAULT_TX_QUEUE_SIZE 512
172 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
174 /* Max number of allowed TCP segments for software TSO */
175 #define MV643XX_MAX_TSO_SEGS 100
176 #define MV643XX_MAX_SKB_DESCS (MV643XX_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
178 #define IS_TSO_HEADER(txq, addr) \
179 ((addr >= txq->tso_hdrs_dma) && \
180 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
182 #define DESC_DMA_MAP_SINGLE 0
183 #define DESC_DMA_MAP_PAGE 1
188 #if defined(__BIG_ENDIAN)
190 u16 byte_cnt; /* Descriptor buffer byte count */
191 u16 buf_size; /* Buffer size */
192 u32 cmd_sts; /* Descriptor command status */
193 u32 next_desc_ptr; /* Next descriptor pointer */
194 u32 buf_ptr; /* Descriptor buffer pointer */
198 u16 byte_cnt; /* buffer byte count */
199 u16 l4i_chk; /* CPU provided TCP checksum */
200 u32 cmd_sts; /* Command/status field */
201 u32 next_desc_ptr; /* Pointer to next descriptor */
202 u32 buf_ptr; /* pointer to buffer for this descriptor*/
204 #elif defined(__LITTLE_ENDIAN)
206 u32 cmd_sts; /* Descriptor command status */
207 u16 buf_size; /* Buffer size */
208 u16 byte_cnt; /* Descriptor buffer byte count */
209 u32 buf_ptr; /* Descriptor buffer pointer */
210 u32 next_desc_ptr; /* Next descriptor pointer */
214 u32 cmd_sts; /* Command/status field */
215 u16 l4i_chk; /* CPU provided TCP checksum */
216 u16 byte_cnt; /* buffer byte count */
217 u32 buf_ptr; /* pointer to buffer for this descriptor*/
218 u32 next_desc_ptr; /* Pointer to next descriptor */
221 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
224 /* RX & TX descriptor command */
225 #define BUFFER_OWNED_BY_DMA 0x80000000
227 /* RX & TX descriptor status */
228 #define ERROR_SUMMARY 0x00000001
230 /* RX descriptor status */
231 #define LAYER_4_CHECKSUM_OK 0x40000000
232 #define RX_ENABLE_INTERRUPT 0x20000000
233 #define RX_FIRST_DESC 0x08000000
234 #define RX_LAST_DESC 0x04000000
235 #define RX_IP_HDR_OK 0x02000000
236 #define RX_PKT_IS_IPV4 0x01000000
237 #define RX_PKT_IS_ETHERNETV2 0x00800000
238 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
239 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
240 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
242 /* TX descriptor command */
243 #define TX_ENABLE_INTERRUPT 0x00800000
244 #define GEN_CRC 0x00400000
245 #define TX_FIRST_DESC 0x00200000
246 #define TX_LAST_DESC 0x00100000
247 #define ZERO_PADDING 0x00080000
248 #define GEN_IP_V4_CHECKSUM 0x00040000
249 #define GEN_TCP_UDP_CHECKSUM 0x00020000
250 #define UDP_FRAME 0x00010000
251 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
252 #define GEN_TCP_UDP_CHK_FULL 0x00000400
253 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
255 #define TX_IHL_SHIFT 11
258 /* global *******************************************************************/
259 struct mv643xx_eth_shared_private {
261 * Ethernet controller base address.
266 * Per-port MBUS window access register value.
271 * Hardware-specific parameters.
273 int extended_rx_coal_limit;
279 #define TX_BW_CONTROL_ABSENT 0
280 #define TX_BW_CONTROL_OLD_LAYOUT 1
281 #define TX_BW_CONTROL_NEW_LAYOUT 2
283 static int mv643xx_eth_open(struct net_device *dev);
284 static int mv643xx_eth_stop(struct net_device *dev);
287 /* per-port *****************************************************************/
288 struct mib_counters {
289 u64 good_octets_received;
290 u32 bad_octets_received;
291 u32 internal_mac_transmit_err;
292 u32 good_frames_received;
293 u32 bad_frames_received;
294 u32 broadcast_frames_received;
295 u32 multicast_frames_received;
296 u32 frames_64_octets;
297 u32 frames_65_to_127_octets;
298 u32 frames_128_to_255_octets;
299 u32 frames_256_to_511_octets;
300 u32 frames_512_to_1023_octets;
301 u32 frames_1024_to_max_octets;
302 u64 good_octets_sent;
303 u32 good_frames_sent;
304 u32 excessive_collision;
305 u32 multicast_frames_sent;
306 u32 broadcast_frames_sent;
307 u32 unrec_mac_control_received;
309 u32 good_fc_received;
311 u32 undersize_received;
312 u32 fragments_received;
313 u32 oversize_received;
315 u32 mac_receive_error;
319 /* Non MIB hardware counters */
333 struct rx_desc *rx_desc_area;
334 dma_addr_t rx_desc_dma;
335 int rx_desc_area_size;
336 struct sk_buff **rx_skb;
348 int tx_stop_threshold;
349 int tx_wake_threshold;
352 dma_addr_t tso_hdrs_dma;
354 struct tx_desc *tx_desc_area;
355 char *tx_desc_mapping; /* array to track the type of the dma mapping */
356 dma_addr_t tx_desc_dma;
357 int tx_desc_area_size;
359 struct sk_buff_head tx_skb;
361 unsigned long tx_packets;
362 unsigned long tx_bytes;
363 unsigned long tx_dropped;
366 struct mv643xx_eth_private {
367 struct mv643xx_eth_shared_private *shared;
371 struct net_device *dev;
373 struct timer_list mib_counters_timer;
374 spinlock_t mib_counters_lock;
375 struct mib_counters mib_counters;
377 struct work_struct tx_timeout_task;
379 struct napi_struct napi;
394 unsigned long rx_desc_sram_addr;
395 int rx_desc_sram_size;
397 struct timer_list rx_oom;
398 struct rx_queue rxq[8];
404 unsigned long tx_desc_sram_addr;
405 int tx_desc_sram_size;
407 struct tx_queue txq[8];
410 * Hardware-specific parameters.
417 /* port register accessors **************************************************/
418 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
420 return readl(mp->shared->base + offset);
423 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
425 return readl(mp->base + offset);
428 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
430 writel(data, mp->shared->base + offset);
433 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
435 writel(data, mp->base + offset);
439 /* rxq/txq helper functions *************************************************/
440 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
442 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
445 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
447 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
450 static void rxq_enable(struct rx_queue *rxq)
452 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
453 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
456 static void rxq_disable(struct rx_queue *rxq)
458 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
459 u8 mask = 1 << rxq->index;
461 wrlp(mp, RXQ_COMMAND, mask << 8);
462 while (rdlp(mp, RXQ_COMMAND) & mask)
466 static void txq_reset_hw_ptr(struct tx_queue *txq)
468 struct mv643xx_eth_private *mp = txq_to_mp(txq);
471 addr = (u32)txq->tx_desc_dma;
472 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
473 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
476 static void txq_enable(struct tx_queue *txq)
478 struct mv643xx_eth_private *mp = txq_to_mp(txq);
479 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
482 static void txq_disable(struct tx_queue *txq)
484 struct mv643xx_eth_private *mp = txq_to_mp(txq);
485 u8 mask = 1 << txq->index;
487 wrlp(mp, TXQ_COMMAND, mask << 8);
488 while (rdlp(mp, TXQ_COMMAND) & mask)
492 static void txq_maybe_wake(struct tx_queue *txq)
494 struct mv643xx_eth_private *mp = txq_to_mp(txq);
495 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
497 if (netif_tx_queue_stopped(nq)) {
498 __netif_tx_lock(nq, smp_processor_id());
499 if (txq->tx_desc_count <= txq->tx_wake_threshold)
500 netif_tx_wake_queue(nq);
501 __netif_tx_unlock(nq);
505 static int rxq_process(struct rx_queue *rxq, int budget)
507 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
508 struct net_device_stats *stats = &mp->dev->stats;
512 while (rx < budget && rxq->rx_desc_count) {
513 struct rx_desc *rx_desc;
514 unsigned int cmd_sts;
518 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
520 cmd_sts = rx_desc->cmd_sts;
521 if (cmd_sts & BUFFER_OWNED_BY_DMA)
525 skb = rxq->rx_skb[rxq->rx_curr_desc];
526 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
529 if (rxq->rx_curr_desc == rxq->rx_ring_size)
530 rxq->rx_curr_desc = 0;
532 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
533 rx_desc->buf_size, DMA_FROM_DEVICE);
534 rxq->rx_desc_count--;
537 mp->work_rx_refill |= 1 << rxq->index;
539 byte_cnt = rx_desc->byte_cnt;
544 * Note that the descriptor byte count includes 2 dummy
545 * bytes automatically inserted by the hardware at the
546 * start of the packet (which we don't count), and a 4
547 * byte CRC at the end of the packet (which we do count).
550 stats->rx_bytes += byte_cnt - 2;
553 * In case we received a packet without first / last bits
554 * on, or the error summary bit is set, the packet needs
557 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
558 != (RX_FIRST_DESC | RX_LAST_DESC))
562 * The -4 is for the CRC in the trailer of the
565 skb_put(skb, byte_cnt - 2 - 4);
567 if (cmd_sts & LAYER_4_CHECKSUM_OK)
568 skb->ip_summed = CHECKSUM_UNNECESSARY;
569 skb->protocol = eth_type_trans(skb, mp->dev);
571 napi_gro_receive(&mp->napi, skb);
578 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
579 (RX_FIRST_DESC | RX_LAST_DESC)) {
582 "received packet spanning multiple descriptors\n");
585 if (cmd_sts & ERROR_SUMMARY)
592 mp->work_rx &= ~(1 << rxq->index);
597 static int rxq_refill(struct rx_queue *rxq, int budget)
599 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
603 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
606 struct rx_desc *rx_desc;
609 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
617 skb_reserve(skb, SKB_DMA_REALIGN);
620 rxq->rx_desc_count++;
622 rx = rxq->rx_used_desc++;
623 if (rxq->rx_used_desc == rxq->rx_ring_size)
624 rxq->rx_used_desc = 0;
626 rx_desc = rxq->rx_desc_area + rx;
628 size = skb_end_pointer(skb) - skb->data;
629 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
632 rx_desc->buf_size = size;
633 rxq->rx_skb[rx] = skb;
635 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
639 * The hardware automatically prepends 2 bytes of
640 * dummy data to each received packet, so that the
641 * IP header ends up 16-byte aligned.
646 if (refilled < budget)
647 mp->work_rx_refill &= ~(1 << rxq->index);
654 /* tx ***********************************************************************/
655 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
659 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
660 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
662 if (skb_frag_size(fragp) <= 8 && skb_frag_off(fragp) & 7)
669 static inline __be16 sum16_as_be(__sum16 sum)
671 return (__force __be16)sum;
674 static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb,
675 u16 *l4i_chk, u32 *command, int length)
680 if (skb->ip_summed == CHECKSUM_PARTIAL) {
684 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
685 skb->protocol != htons(ETH_P_8021Q));
687 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
688 tag_bytes = hdr_len - ETH_HLEN;
690 if (length - hdr_len > mp->shared->tx_csum_limit ||
691 unlikely(tag_bytes & ~12)) {
692 ret = skb_checksum_help(skb);
699 cmd |= MAC_HDR_EXTRA_4_BYTES;
701 cmd |= MAC_HDR_EXTRA_8_BYTES;
703 cmd |= GEN_TCP_UDP_CHECKSUM | GEN_TCP_UDP_CHK_FULL |
705 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
707 /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL
708 * it seems we don't need to pass the initial checksum. */
709 switch (ip_hdr(skb)->protocol) {
718 WARN(1, "protocol not supported");
722 /* Errata BTS #50, IHL must be 5 if no HW checksum */
723 cmd |= 5 << TX_IHL_SHIFT;
730 txq_put_data_tso(struct net_device *dev, struct tx_queue *txq,
731 struct sk_buff *skb, char *data, int length,
732 bool last_tcp, bool is_last)
736 struct tx_desc *desc;
738 tx_index = txq->tx_curr_desc++;
739 if (txq->tx_curr_desc == txq->tx_ring_size)
740 txq->tx_curr_desc = 0;
741 desc = &txq->tx_desc_area[tx_index];
742 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
745 desc->byte_cnt = length;
747 if (length <= 8 && (uintptr_t)data & 0x7) {
748 /* Copy unaligned small data fragment to TSO header data area */
749 memcpy(txq->tso_hdrs + tx_index * TSO_HEADER_SIZE,
751 desc->buf_ptr = txq->tso_hdrs_dma
752 + tx_index * TSO_HEADER_SIZE;
754 /* Alignment is okay, map buffer and hand off to hardware */
755 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
756 desc->buf_ptr = dma_map_single(dev->dev.parent, data,
757 length, DMA_TO_DEVICE);
758 if (unlikely(dma_mapping_error(dev->dev.parent,
760 WARN(1, "dma_map_single failed!\n");
765 cmd_sts = BUFFER_OWNED_BY_DMA;
767 /* last descriptor in the TCP packet */
768 cmd_sts |= ZERO_PADDING | TX_LAST_DESC;
769 /* last descriptor in SKB */
771 cmd_sts |= TX_ENABLE_INTERRUPT;
773 desc->cmd_sts = cmd_sts;
778 txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length,
779 u32 *first_cmd_sts, bool first_desc)
781 struct mv643xx_eth_private *mp = txq_to_mp(txq);
782 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
784 struct tx_desc *desc;
790 tx_index = txq->tx_curr_desc;
791 desc = &txq->tx_desc_area[tx_index];
793 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_csum, length);
795 WARN(1, "failed to prepare checksum!");
797 /* Should we set this? Can't use the value from skb_tx_csum()
798 * as it's not the correct initial L4 checksum to use. */
801 desc->byte_cnt = hdr_len;
802 desc->buf_ptr = txq->tso_hdrs_dma +
803 txq->tx_curr_desc * TSO_HEADER_SIZE;
804 cmd_sts = cmd_csum | BUFFER_OWNED_BY_DMA | TX_FIRST_DESC |
807 /* Defer updating the first command descriptor until all
808 * following descriptors have been written.
811 *first_cmd_sts = cmd_sts;
813 desc->cmd_sts = cmd_sts;
816 if (txq->tx_curr_desc == txq->tx_ring_size)
817 txq->tx_curr_desc = 0;
820 static int txq_submit_tso(struct tx_queue *txq, struct sk_buff *skb,
821 struct net_device *dev)
823 struct mv643xx_eth_private *mp = txq_to_mp(txq);
824 int total_len, data_left, ret;
827 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
828 struct tx_desc *first_tx_desc;
829 u32 first_cmd_sts = 0;
831 /* Count needed descriptors */
832 if ((txq->tx_desc_count + tso_count_descs(skb)) >= txq->tx_ring_size) {
833 netdev_dbg(dev, "not enough descriptors for TSO!\n");
837 first_tx_desc = &txq->tx_desc_area[txq->tx_curr_desc];
839 /* Initialize the TSO handler, and prepare the first payload */
840 tso_start(skb, &tso);
842 total_len = skb->len - hdr_len;
843 while (total_len > 0) {
844 bool first_desc = (desc_count == 0);
847 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
848 total_len -= data_left;
851 /* prepare packet headers: MAC + IP + TCP */
852 hdr = txq->tso_hdrs + txq->tx_curr_desc * TSO_HEADER_SIZE;
853 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
854 txq_put_hdr_tso(skb, txq, data_left, &first_cmd_sts,
857 while (data_left > 0) {
861 size = min_t(int, tso.size, data_left);
862 ret = txq_put_data_tso(dev, txq, skb, tso.data, size,
868 tso_build_data(skb, &tso, size);
872 __skb_queue_tail(&txq->tx_skb, skb);
873 skb_tx_timestamp(skb);
875 /* ensure all other descriptors are written before first cmd_sts */
877 first_tx_desc->cmd_sts = first_cmd_sts;
879 /* clear TX_END status */
880 mp->work_tx_end &= ~(1 << txq->index);
882 /* ensure all descriptors are written before poking hardware */
885 txq->tx_desc_count += desc_count;
888 /* TODO: Release all used data descriptors; header descriptors must not
894 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
896 struct mv643xx_eth_private *mp = txq_to_mp(txq);
897 int nr_frags = skb_shinfo(skb)->nr_frags;
900 for (frag = 0; frag < nr_frags; frag++) {
901 skb_frag_t *this_frag;
903 struct tx_desc *desc;
905 this_frag = &skb_shinfo(skb)->frags[frag];
906 tx_index = txq->tx_curr_desc++;
907 if (txq->tx_curr_desc == txq->tx_ring_size)
908 txq->tx_curr_desc = 0;
909 desc = &txq->tx_desc_area[tx_index];
910 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_PAGE;
913 * The last fragment will generate an interrupt
914 * which will free the skb on TX completion.
916 if (frag == nr_frags - 1) {
917 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
918 ZERO_PADDING | TX_LAST_DESC |
921 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
925 desc->byte_cnt = skb_frag_size(this_frag);
926 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
927 this_frag, 0, desc->byte_cnt,
932 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb,
933 struct net_device *dev)
935 struct mv643xx_eth_private *mp = txq_to_mp(txq);
936 int nr_frags = skb_shinfo(skb)->nr_frags;
938 struct tx_desc *desc;
946 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
948 netdev_err(dev, "tx queue full?!\n");
952 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len);
955 cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
957 tx_index = txq->tx_curr_desc++;
958 if (txq->tx_curr_desc == txq->tx_ring_size)
959 txq->tx_curr_desc = 0;
960 desc = &txq->tx_desc_area[tx_index];
961 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
964 txq_submit_frag_skb(txq, skb);
965 length = skb_headlen(skb);
967 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
971 desc->l4i_chk = l4i_chk;
972 desc->byte_cnt = length;
973 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
974 length, DMA_TO_DEVICE);
976 __skb_queue_tail(&txq->tx_skb, skb);
978 skb_tx_timestamp(skb);
980 /* ensure all other descriptors are written before first cmd_sts */
982 desc->cmd_sts = cmd_sts;
984 /* clear TX_END status */
985 mp->work_tx_end &= ~(1 << txq->index);
987 /* ensure all descriptors are written before poking hardware */
991 txq->tx_desc_count += nr_frags + 1;
996 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
998 struct mv643xx_eth_private *mp = netdev_priv(dev);
999 int length, queue, ret;
1000 struct tx_queue *txq;
1001 struct netdev_queue *nq;
1003 queue = skb_get_queue_mapping(skb);
1004 txq = mp->txq + queue;
1005 nq = netdev_get_tx_queue(dev, queue);
1007 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
1008 netdev_printk(KERN_DEBUG, dev,
1009 "failed to linearize skb with tiny unaligned fragment\n");
1010 return NETDEV_TX_BUSY;
1015 if (skb_is_gso(skb))
1016 ret = txq_submit_tso(txq, skb, dev);
1018 ret = txq_submit_skb(txq, skb, dev);
1020 txq->tx_bytes += length;
1023 if (txq->tx_desc_count >= txq->tx_stop_threshold)
1024 netif_tx_stop_queue(nq);
1027 dev_kfree_skb_any(skb);
1030 return NETDEV_TX_OK;
1034 /* tx napi ******************************************************************/
1035 static void txq_kick(struct tx_queue *txq)
1037 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1038 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1042 __netif_tx_lock(nq, smp_processor_id());
1044 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1047 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1048 expected_ptr = (u32)txq->tx_desc_dma +
1049 txq->tx_curr_desc * sizeof(struct tx_desc);
1051 if (hw_desc_ptr != expected_ptr)
1055 __netif_tx_unlock(nq);
1057 mp->work_tx_end &= ~(1 << txq->index);
1060 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
1062 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1063 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1066 __netif_tx_lock_bh(nq);
1069 while (reclaimed < budget && txq->tx_desc_count > 0) {
1071 struct tx_desc *desc;
1075 tx_index = txq->tx_used_desc;
1076 desc = &txq->tx_desc_area[tx_index];
1077 desc_dma_map = txq->tx_desc_mapping[tx_index];
1079 cmd_sts = desc->cmd_sts;
1081 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1084 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1087 txq->tx_used_desc = tx_index + 1;
1088 if (txq->tx_used_desc == txq->tx_ring_size)
1089 txq->tx_used_desc = 0;
1092 txq->tx_desc_count--;
1094 if (!IS_TSO_HEADER(txq, desc->buf_ptr)) {
1096 if (desc_dma_map == DESC_DMA_MAP_PAGE)
1097 dma_unmap_page(mp->dev->dev.parent,
1102 dma_unmap_single(mp->dev->dev.parent,
1108 if (cmd_sts & TX_ENABLE_INTERRUPT) {
1109 struct sk_buff *skb = __skb_dequeue(&txq->tx_skb);
1112 dev_consume_skb_any(skb);
1115 if (cmd_sts & ERROR_SUMMARY) {
1116 netdev_info(mp->dev, "tx error\n");
1117 mp->dev->stats.tx_errors++;
1122 __netif_tx_unlock_bh(nq);
1124 if (reclaimed < budget)
1125 mp->work_tx &= ~(1 << txq->index);
1131 /* tx rate control **********************************************************/
1133 * Set total maximum TX rate (shared by all TX queues for this port)
1134 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1136 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1142 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1143 if (token_rate > 1023)
1146 mtu = (mp->dev->mtu + 255) >> 8;
1150 bucket_size = (burst + 255) >> 8;
1151 if (bucket_size > 65535)
1152 bucket_size = 65535;
1154 switch (mp->shared->tx_bw_control) {
1155 case TX_BW_CONTROL_OLD_LAYOUT:
1156 wrlp(mp, TX_BW_RATE, token_rate);
1157 wrlp(mp, TX_BW_MTU, mtu);
1158 wrlp(mp, TX_BW_BURST, bucket_size);
1160 case TX_BW_CONTROL_NEW_LAYOUT:
1161 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1162 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1163 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1168 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1170 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1174 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1175 if (token_rate > 1023)
1178 bucket_size = (burst + 255) >> 8;
1179 if (bucket_size > 65535)
1180 bucket_size = 65535;
1182 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1183 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1186 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1188 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1193 * Turn on fixed priority mode.
1196 switch (mp->shared->tx_bw_control) {
1197 case TX_BW_CONTROL_OLD_LAYOUT:
1198 off = TXQ_FIX_PRIO_CONF;
1200 case TX_BW_CONTROL_NEW_LAYOUT:
1201 off = TXQ_FIX_PRIO_CONF_MOVED;
1206 val = rdlp(mp, off);
1207 val |= 1 << txq->index;
1213 /* mii management interface *************************************************/
1214 static void mv643xx_eth_adjust_link(struct net_device *dev)
1216 struct mv643xx_eth_private *mp = netdev_priv(dev);
1217 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1218 u32 autoneg_disable = FORCE_LINK_PASS |
1219 DISABLE_AUTO_NEG_SPEED_GMII |
1220 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1221 DISABLE_AUTO_NEG_FOR_DUPLEX;
1223 if (dev->phydev->autoneg == AUTONEG_ENABLE) {
1224 /* enable auto negotiation */
1225 pscr &= ~autoneg_disable;
1229 pscr |= autoneg_disable;
1231 if (dev->phydev->speed == SPEED_1000) {
1232 /* force gigabit, half duplex not supported */
1233 pscr |= SET_GMII_SPEED_TO_1000;
1234 pscr |= SET_FULL_DUPLEX_MODE;
1238 pscr &= ~SET_GMII_SPEED_TO_1000;
1240 if (dev->phydev->speed == SPEED_100)
1241 pscr |= SET_MII_SPEED_TO_100;
1243 pscr &= ~SET_MII_SPEED_TO_100;
1245 if (dev->phydev->duplex == DUPLEX_FULL)
1246 pscr |= SET_FULL_DUPLEX_MODE;
1248 pscr &= ~SET_FULL_DUPLEX_MODE;
1251 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1254 /* statistics ***************************************************************/
1255 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1257 struct mv643xx_eth_private *mp = netdev_priv(dev);
1258 struct net_device_stats *stats = &dev->stats;
1259 unsigned long tx_packets = 0;
1260 unsigned long tx_bytes = 0;
1261 unsigned long tx_dropped = 0;
1264 for (i = 0; i < mp->txq_count; i++) {
1265 struct tx_queue *txq = mp->txq + i;
1267 tx_packets += txq->tx_packets;
1268 tx_bytes += txq->tx_bytes;
1269 tx_dropped += txq->tx_dropped;
1272 stats->tx_packets = tx_packets;
1273 stats->tx_bytes = tx_bytes;
1274 stats->tx_dropped = tx_dropped;
1279 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1281 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1284 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1288 for (i = 0; i < 0x80; i += 4)
1291 /* Clear non MIB hw counters also */
1292 rdlp(mp, RX_DISCARD_FRAME_CNT);
1293 rdlp(mp, RX_OVERRUN_FRAME_CNT);
1296 static void mib_counters_update(struct mv643xx_eth_private *mp)
1298 struct mib_counters *p = &mp->mib_counters;
1300 spin_lock_bh(&mp->mib_counters_lock);
1301 p->good_octets_received += mib_read(mp, 0x00);
1302 p->bad_octets_received += mib_read(mp, 0x08);
1303 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1304 p->good_frames_received += mib_read(mp, 0x10);
1305 p->bad_frames_received += mib_read(mp, 0x14);
1306 p->broadcast_frames_received += mib_read(mp, 0x18);
1307 p->multicast_frames_received += mib_read(mp, 0x1c);
1308 p->frames_64_octets += mib_read(mp, 0x20);
1309 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1310 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1311 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1312 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1313 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1314 p->good_octets_sent += mib_read(mp, 0x38);
1315 p->good_frames_sent += mib_read(mp, 0x40);
1316 p->excessive_collision += mib_read(mp, 0x44);
1317 p->multicast_frames_sent += mib_read(mp, 0x48);
1318 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1319 p->unrec_mac_control_received += mib_read(mp, 0x50);
1320 p->fc_sent += mib_read(mp, 0x54);
1321 p->good_fc_received += mib_read(mp, 0x58);
1322 p->bad_fc_received += mib_read(mp, 0x5c);
1323 p->undersize_received += mib_read(mp, 0x60);
1324 p->fragments_received += mib_read(mp, 0x64);
1325 p->oversize_received += mib_read(mp, 0x68);
1326 p->jabber_received += mib_read(mp, 0x6c);
1327 p->mac_receive_error += mib_read(mp, 0x70);
1328 p->bad_crc_event += mib_read(mp, 0x74);
1329 p->collision += mib_read(mp, 0x78);
1330 p->late_collision += mib_read(mp, 0x7c);
1331 /* Non MIB hardware counters */
1332 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1333 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1334 spin_unlock_bh(&mp->mib_counters_lock);
1337 static void mib_counters_timer_wrapper(struct timer_list *t)
1339 struct mv643xx_eth_private *mp = from_timer(mp, t, mib_counters_timer);
1340 mib_counters_update(mp);
1341 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1345 /* interrupt coalescing *****************************************************/
1347 * Hardware coalescing parameters are set in units of 64 t_clk
1350 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1352 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1354 * In the ->set*() methods, we round the computed register value
1355 * to the nearest integer.
1357 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1359 u32 val = rdlp(mp, SDMA_CONFIG);
1362 if (mp->shared->extended_rx_coal_limit)
1363 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1365 temp = (val & 0x003fff00) >> 8;
1368 temp += mp->t_clk / 2;
1369 do_div(temp, mp->t_clk);
1371 return (unsigned int)temp;
1374 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1379 temp = (u64)usec * mp->t_clk;
1381 do_div(temp, 64000000);
1383 val = rdlp(mp, SDMA_CONFIG);
1384 if (mp->shared->extended_rx_coal_limit) {
1388 val |= (temp & 0x8000) << 10;
1389 val |= (temp & 0x7fff) << 7;
1394 val |= (temp & 0x3fff) << 8;
1396 wrlp(mp, SDMA_CONFIG, val);
1399 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1403 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1405 temp += mp->t_clk / 2;
1406 do_div(temp, mp->t_clk);
1408 return (unsigned int)temp;
1411 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1415 temp = (u64)usec * mp->t_clk;
1417 do_div(temp, 64000000);
1422 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1426 /* ethtool ******************************************************************/
1427 struct mv643xx_eth_stats {
1428 char stat_string[ETH_GSTRING_LEN];
1435 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1436 offsetof(struct net_device, stats.m), -1 }
1438 #define MIBSTAT(m) \
1439 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1440 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1442 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1451 MIBSTAT(good_octets_received),
1452 MIBSTAT(bad_octets_received),
1453 MIBSTAT(internal_mac_transmit_err),
1454 MIBSTAT(good_frames_received),
1455 MIBSTAT(bad_frames_received),
1456 MIBSTAT(broadcast_frames_received),
1457 MIBSTAT(multicast_frames_received),
1458 MIBSTAT(frames_64_octets),
1459 MIBSTAT(frames_65_to_127_octets),
1460 MIBSTAT(frames_128_to_255_octets),
1461 MIBSTAT(frames_256_to_511_octets),
1462 MIBSTAT(frames_512_to_1023_octets),
1463 MIBSTAT(frames_1024_to_max_octets),
1464 MIBSTAT(good_octets_sent),
1465 MIBSTAT(good_frames_sent),
1466 MIBSTAT(excessive_collision),
1467 MIBSTAT(multicast_frames_sent),
1468 MIBSTAT(broadcast_frames_sent),
1469 MIBSTAT(unrec_mac_control_received),
1471 MIBSTAT(good_fc_received),
1472 MIBSTAT(bad_fc_received),
1473 MIBSTAT(undersize_received),
1474 MIBSTAT(fragments_received),
1475 MIBSTAT(oversize_received),
1476 MIBSTAT(jabber_received),
1477 MIBSTAT(mac_receive_error),
1478 MIBSTAT(bad_crc_event),
1480 MIBSTAT(late_collision),
1481 MIBSTAT(rx_discard),
1482 MIBSTAT(rx_overrun),
1486 mv643xx_eth_get_link_ksettings_phy(struct mv643xx_eth_private *mp,
1487 struct ethtool_link_ksettings *cmd)
1489 struct net_device *dev = mp->dev;
1491 phy_ethtool_ksettings_get(dev->phydev, cmd);
1494 * The MAC does not support 1000baseT_Half.
1496 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1497 cmd->link_modes.supported);
1498 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1499 cmd->link_modes.advertising);
1505 mv643xx_eth_get_link_ksettings_phyless(struct mv643xx_eth_private *mp,
1506 struct ethtool_link_ksettings *cmd)
1509 u32 supported, advertising;
1511 port_status = rdlp(mp, PORT_STATUS);
1513 supported = SUPPORTED_MII;
1514 advertising = ADVERTISED_MII;
1515 switch (port_status & PORT_SPEED_MASK) {
1517 cmd->base.speed = SPEED_10;
1519 case PORT_SPEED_100:
1520 cmd->base.speed = SPEED_100;
1522 case PORT_SPEED_1000:
1523 cmd->base.speed = SPEED_1000;
1526 cmd->base.speed = -1;
1529 cmd->base.duplex = (port_status & FULL_DUPLEX) ?
1530 DUPLEX_FULL : DUPLEX_HALF;
1531 cmd->base.port = PORT_MII;
1532 cmd->base.phy_address = 0;
1533 cmd->base.autoneg = AUTONEG_DISABLE;
1535 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1537 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1544 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1549 phy_ethtool_get_wol(dev->phydev, wol);
1553 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1560 err = phy_ethtool_set_wol(dev->phydev, wol);
1561 /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1562 * this debugging hint is useful to have.
1564 if (err == -EOPNOTSUPP)
1565 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1570 mv643xx_eth_get_link_ksettings(struct net_device *dev,
1571 struct ethtool_link_ksettings *cmd)
1573 struct mv643xx_eth_private *mp = netdev_priv(dev);
1576 return mv643xx_eth_get_link_ksettings_phy(mp, cmd);
1578 return mv643xx_eth_get_link_ksettings_phyless(mp, cmd);
1582 mv643xx_eth_set_link_ksettings(struct net_device *dev,
1583 const struct ethtool_link_ksettings *cmd)
1585 struct ethtool_link_ksettings c = *cmd;
1593 * The MAC does not support 1000baseT_Half.
1595 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1596 c.link_modes.advertising);
1597 advertising &= ~ADVERTISED_1000baseT_Half;
1598 ethtool_convert_legacy_u32_to_link_mode(c.link_modes.advertising,
1601 ret = phy_ethtool_ksettings_set(dev->phydev, &c);
1603 mv643xx_eth_adjust_link(dev);
1607 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1608 struct ethtool_drvinfo *drvinfo)
1610 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1611 sizeof(drvinfo->driver));
1612 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1613 sizeof(drvinfo->version));
1614 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1615 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1619 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1621 struct mv643xx_eth_private *mp = netdev_priv(dev);
1623 ec->rx_coalesce_usecs = get_rx_coal(mp);
1624 ec->tx_coalesce_usecs = get_tx_coal(mp);
1630 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1632 struct mv643xx_eth_private *mp = netdev_priv(dev);
1634 set_rx_coal(mp, ec->rx_coalesce_usecs);
1635 set_tx_coal(mp, ec->tx_coalesce_usecs);
1641 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1643 struct mv643xx_eth_private *mp = netdev_priv(dev);
1645 er->rx_max_pending = 4096;
1646 er->tx_max_pending = 4096;
1648 er->rx_pending = mp->rx_ring_size;
1649 er->tx_pending = mp->tx_ring_size;
1653 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1655 struct mv643xx_eth_private *mp = netdev_priv(dev);
1657 if (er->rx_mini_pending || er->rx_jumbo_pending)
1660 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1661 mp->tx_ring_size = clamp_t(unsigned int, er->tx_pending,
1662 MV643XX_MAX_SKB_DESCS * 2, 4096);
1663 if (mp->tx_ring_size != er->tx_pending)
1664 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
1665 mp->tx_ring_size, er->tx_pending);
1667 if (netif_running(dev)) {
1668 mv643xx_eth_stop(dev);
1669 if (mv643xx_eth_open(dev)) {
1671 "fatal error on re-opening device after ring param change\n");
1681 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1683 struct mv643xx_eth_private *mp = netdev_priv(dev);
1684 bool rx_csum = features & NETIF_F_RXCSUM;
1686 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1691 static void mv643xx_eth_get_strings(struct net_device *dev,
1692 uint32_t stringset, uint8_t *data)
1696 if (stringset == ETH_SS_STATS) {
1697 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1698 memcpy(data + i * ETH_GSTRING_LEN,
1699 mv643xx_eth_stats[i].stat_string,
1705 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1706 struct ethtool_stats *stats,
1709 struct mv643xx_eth_private *mp = netdev_priv(dev);
1712 mv643xx_eth_get_stats(dev);
1713 mib_counters_update(mp);
1715 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1716 const struct mv643xx_eth_stats *stat;
1719 stat = mv643xx_eth_stats + i;
1721 if (stat->netdev_off >= 0)
1722 p = ((void *)mp->dev) + stat->netdev_off;
1724 p = ((void *)mp) + stat->mp_off;
1726 data[i] = (stat->sizeof_stat == 8) ?
1727 *(uint64_t *)p : *(uint32_t *)p;
1731 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1733 if (sset == ETH_SS_STATS)
1734 return ARRAY_SIZE(mv643xx_eth_stats);
1739 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1740 .get_drvinfo = mv643xx_eth_get_drvinfo,
1741 .nway_reset = phy_ethtool_nway_reset,
1742 .get_link = ethtool_op_get_link,
1743 .get_coalesce = mv643xx_eth_get_coalesce,
1744 .set_coalesce = mv643xx_eth_set_coalesce,
1745 .get_ringparam = mv643xx_eth_get_ringparam,
1746 .set_ringparam = mv643xx_eth_set_ringparam,
1747 .get_strings = mv643xx_eth_get_strings,
1748 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1749 .get_sset_count = mv643xx_eth_get_sset_count,
1750 .get_ts_info = ethtool_op_get_ts_info,
1751 .get_wol = mv643xx_eth_get_wol,
1752 .set_wol = mv643xx_eth_set_wol,
1753 .get_link_ksettings = mv643xx_eth_get_link_ksettings,
1754 .set_link_ksettings = mv643xx_eth_set_link_ksettings,
1758 /* address handling *********************************************************/
1759 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1761 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1762 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1764 addr[0] = (mac_h >> 24) & 0xff;
1765 addr[1] = (mac_h >> 16) & 0xff;
1766 addr[2] = (mac_h >> 8) & 0xff;
1767 addr[3] = mac_h & 0xff;
1768 addr[4] = (mac_l >> 8) & 0xff;
1769 addr[5] = mac_l & 0xff;
1772 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1774 wrlp(mp, MAC_ADDR_HIGH,
1775 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1776 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1779 static u32 uc_addr_filter_mask(struct net_device *dev)
1781 struct netdev_hw_addr *ha;
1784 if (dev->flags & IFF_PROMISC)
1787 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1788 netdev_for_each_uc_addr(ha, dev) {
1789 if (memcmp(dev->dev_addr, ha->addr, 5))
1791 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1794 nibbles |= 1 << (ha->addr[5] & 0x0f);
1800 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1802 struct mv643xx_eth_private *mp = netdev_priv(dev);
1807 uc_addr_set(mp, dev->dev_addr);
1809 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1811 nibbles = uc_addr_filter_mask(dev);
1813 port_config |= UNICAST_PROMISCUOUS_MODE;
1817 for (i = 0; i < 16; i += 4) {
1818 int off = UNICAST_TABLE(mp->port_num) + i;
1835 wrlp(mp, PORT_CONFIG, port_config);
1838 static int addr_crc(unsigned char *addr)
1843 for (i = 0; i < 6; i++) {
1846 crc = (crc ^ addr[i]) << 8;
1847 for (j = 7; j >= 0; j--) {
1848 if (crc & (0x100 << j))
1856 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1858 struct mv643xx_eth_private *mp = netdev_priv(dev);
1861 struct netdev_hw_addr *ha;
1864 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI))
1867 /* Allocate both mc_spec and mc_other tables */
1868 mc_spec = kcalloc(128, sizeof(u32), GFP_ATOMIC);
1871 mc_other = &mc_spec[64];
1873 netdev_for_each_mc_addr(ha, dev) {
1878 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1883 entry = addr_crc(a);
1886 table[entry >> 2] |= 1 << (8 * (entry & 3));
1889 for (i = 0; i < 64; i++) {
1890 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1892 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1900 for (i = 0; i < 64; i++) {
1901 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1903 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1908 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1910 mv643xx_eth_program_unicast_filter(dev);
1911 mv643xx_eth_program_multicast_filter(dev);
1914 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1916 struct sockaddr *sa = addr;
1918 if (!is_valid_ether_addr(sa->sa_data))
1919 return -EADDRNOTAVAIL;
1921 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1923 netif_addr_lock_bh(dev);
1924 mv643xx_eth_program_unicast_filter(dev);
1925 netif_addr_unlock_bh(dev);
1931 /* rx/tx queue initialisation ***********************************************/
1932 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1934 struct rx_queue *rxq = mp->rxq + index;
1935 struct rx_desc *rx_desc;
1941 rxq->rx_ring_size = mp->rx_ring_size;
1943 rxq->rx_desc_count = 0;
1944 rxq->rx_curr_desc = 0;
1945 rxq->rx_used_desc = 0;
1947 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1949 if (index == 0 && size <= mp->rx_desc_sram_size) {
1950 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1951 mp->rx_desc_sram_size);
1952 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1954 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1955 size, &rxq->rx_desc_dma,
1959 if (rxq->rx_desc_area == NULL) {
1961 "can't allocate rx ring (%d bytes)\n", size);
1964 memset(rxq->rx_desc_area, 0, size);
1966 rxq->rx_desc_area_size = size;
1967 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1969 if (rxq->rx_skb == NULL)
1972 rx_desc = rxq->rx_desc_area;
1973 for (i = 0; i < rxq->rx_ring_size; i++) {
1977 if (nexti == rxq->rx_ring_size)
1980 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1981 nexti * sizeof(struct rx_desc);
1988 if (index == 0 && size <= mp->rx_desc_sram_size)
1989 iounmap(rxq->rx_desc_area);
1991 dma_free_coherent(mp->dev->dev.parent, size,
1999 static void rxq_deinit(struct rx_queue *rxq)
2001 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
2006 for (i = 0; i < rxq->rx_ring_size; i++) {
2007 if (rxq->rx_skb[i]) {
2008 dev_consume_skb_any(rxq->rx_skb[i]);
2009 rxq->rx_desc_count--;
2013 if (rxq->rx_desc_count) {
2014 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
2015 rxq->rx_desc_count);
2018 if (rxq->index == 0 &&
2019 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
2020 iounmap(rxq->rx_desc_area);
2022 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
2023 rxq->rx_desc_area, rxq->rx_desc_dma);
2028 static int txq_init(struct mv643xx_eth_private *mp, int index)
2030 struct tx_queue *txq = mp->txq + index;
2031 struct tx_desc *tx_desc;
2038 txq->tx_ring_size = mp->tx_ring_size;
2040 /* A queue must always have room for at least one skb.
2041 * Therefore, stop the queue when the free entries reaches
2042 * the maximum number of descriptors per skb.
2044 txq->tx_stop_threshold = txq->tx_ring_size - MV643XX_MAX_SKB_DESCS;
2045 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2047 txq->tx_desc_count = 0;
2048 txq->tx_curr_desc = 0;
2049 txq->tx_used_desc = 0;
2051 size = txq->tx_ring_size * sizeof(struct tx_desc);
2053 if (index == 0 && size <= mp->tx_desc_sram_size) {
2054 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2055 mp->tx_desc_sram_size);
2056 txq->tx_desc_dma = mp->tx_desc_sram_addr;
2058 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
2059 size, &txq->tx_desc_dma,
2063 if (txq->tx_desc_area == NULL) {
2065 "can't allocate tx ring (%d bytes)\n", size);
2068 memset(txq->tx_desc_area, 0, size);
2070 txq->tx_desc_area_size = size;
2072 tx_desc = txq->tx_desc_area;
2073 for (i = 0; i < txq->tx_ring_size; i++) {
2074 struct tx_desc *txd = tx_desc + i;
2078 if (nexti == txq->tx_ring_size)
2082 txd->next_desc_ptr = txq->tx_desc_dma +
2083 nexti * sizeof(struct tx_desc);
2086 txq->tx_desc_mapping = kcalloc(txq->tx_ring_size, sizeof(char),
2088 if (!txq->tx_desc_mapping) {
2090 goto err_free_desc_area;
2093 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2094 txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent,
2095 txq->tx_ring_size * TSO_HEADER_SIZE,
2096 &txq->tso_hdrs_dma, GFP_KERNEL);
2097 if (txq->tso_hdrs == NULL) {
2099 goto err_free_desc_mapping;
2101 skb_queue_head_init(&txq->tx_skb);
2105 err_free_desc_mapping:
2106 kfree(txq->tx_desc_mapping);
2108 if (index == 0 && size <= mp->tx_desc_sram_size)
2109 iounmap(txq->tx_desc_area);
2111 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2112 txq->tx_desc_area, txq->tx_desc_dma);
2116 static void txq_deinit(struct tx_queue *txq)
2118 struct mv643xx_eth_private *mp = txq_to_mp(txq);
2121 txq_reclaim(txq, txq->tx_ring_size, 1);
2123 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2125 if (txq->index == 0 &&
2126 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2127 iounmap(txq->tx_desc_area);
2129 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2130 txq->tx_desc_area, txq->tx_desc_dma);
2131 kfree(txq->tx_desc_mapping);
2134 dma_free_coherent(mp->dev->dev.parent,
2135 txq->tx_ring_size * TSO_HEADER_SIZE,
2136 txq->tso_hdrs, txq->tso_hdrs_dma);
2140 /* netdev ops and related ***************************************************/
2141 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2146 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
2151 if (int_cause & INT_EXT) {
2152 int_cause &= ~INT_EXT;
2153 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2157 wrlp(mp, INT_CAUSE, ~int_cause);
2158 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2159 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
2160 mp->work_rx |= (int_cause & INT_RX) >> 2;
2163 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2164 if (int_cause_ext) {
2165 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2166 if (int_cause_ext & INT_EXT_LINK_PHY)
2168 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2174 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2176 struct net_device *dev = (struct net_device *)dev_id;
2177 struct mv643xx_eth_private *mp = netdev_priv(dev);
2179 if (unlikely(!mv643xx_eth_collect_events(mp)))
2182 wrlp(mp, INT_MASK, 0);
2183 napi_schedule(&mp->napi);
2188 static void handle_link_event(struct mv643xx_eth_private *mp)
2190 struct net_device *dev = mp->dev;
2196 port_status = rdlp(mp, PORT_STATUS);
2197 if (!(port_status & LINK_UP)) {
2198 if (netif_carrier_ok(dev)) {
2201 netdev_info(dev, "link down\n");
2203 netif_carrier_off(dev);
2205 for (i = 0; i < mp->txq_count; i++) {
2206 struct tx_queue *txq = mp->txq + i;
2208 txq_reclaim(txq, txq->tx_ring_size, 1);
2209 txq_reset_hw_ptr(txq);
2215 switch (port_status & PORT_SPEED_MASK) {
2219 case PORT_SPEED_100:
2222 case PORT_SPEED_1000:
2229 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2230 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2232 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2233 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2235 if (!netif_carrier_ok(dev))
2236 netif_carrier_on(dev);
2239 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2241 struct mv643xx_eth_private *mp;
2244 mp = container_of(napi, struct mv643xx_eth_private, napi);
2246 if (unlikely(mp->oom)) {
2248 del_timer(&mp->rx_oom);
2252 while (work_done < budget) {
2257 if (mp->work_link) {
2259 handle_link_event(mp);
2264 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2265 if (likely(!mp->oom))
2266 queue_mask |= mp->work_rx_refill;
2269 if (mv643xx_eth_collect_events(mp))
2274 queue = fls(queue_mask) - 1;
2275 queue_mask = 1 << queue;
2277 work_tbd = budget - work_done;
2281 if (mp->work_tx_end & queue_mask) {
2282 txq_kick(mp->txq + queue);
2283 } else if (mp->work_tx & queue_mask) {
2284 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2285 txq_maybe_wake(mp->txq + queue);
2286 } else if (mp->work_rx & queue_mask) {
2287 work_done += rxq_process(mp->rxq + queue, work_tbd);
2288 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2289 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2295 if (work_done < budget) {
2297 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2298 napi_complete_done(napi, work_done);
2299 wrlp(mp, INT_MASK, mp->int_mask);
2305 static inline void oom_timer_wrapper(struct timer_list *t)
2307 struct mv643xx_eth_private *mp = from_timer(mp, t, rx_oom);
2309 napi_schedule(&mp->napi);
2312 static void port_start(struct mv643xx_eth_private *mp)
2314 struct net_device *dev = mp->dev;
2319 * Perform PHY reset, if there is a PHY.
2322 struct ethtool_link_ksettings cmd;
2324 mv643xx_eth_get_link_ksettings(dev, &cmd);
2325 phy_init_hw(dev->phydev);
2326 mv643xx_eth_set_link_ksettings(
2327 dev, (const struct ethtool_link_ksettings *)&cmd);
2328 phy_start(dev->phydev);
2332 * Configure basic link parameters.
2334 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2336 pscr |= SERIAL_PORT_ENABLE;
2337 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2339 pscr |= DO_NOT_FORCE_LINK_FAIL;
2341 pscr |= FORCE_LINK_PASS;
2342 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2345 * Configure TX path and queues.
2347 tx_set_rate(mp, 1000000000, 16777216);
2348 for (i = 0; i < mp->txq_count; i++) {
2349 struct tx_queue *txq = mp->txq + i;
2351 txq_reset_hw_ptr(txq);
2352 txq_set_rate(txq, 1000000000, 16777216);
2353 txq_set_fixed_prio_mode(txq);
2357 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2358 * frames to RX queue #0, and include the pseudo-header when
2359 * calculating receive checksums.
2361 mv643xx_eth_set_features(mp->dev, mp->dev->features);
2364 * Treat BPDUs as normal multicasts, and disable partition mode.
2366 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2369 * Add configured unicast addresses to address filter table.
2371 mv643xx_eth_program_unicast_filter(mp->dev);
2374 * Enable the receive queues.
2376 for (i = 0; i < mp->rxq_count; i++) {
2377 struct rx_queue *rxq = mp->rxq + i;
2380 addr = (u32)rxq->rx_desc_dma;
2381 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2382 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2388 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2393 * Reserve 2+14 bytes for an ethernet header (the hardware
2394 * automatically prepends 2 bytes of dummy data to each
2395 * received packet), 16 bytes for up to four VLAN tags, and
2396 * 4 bytes for the trailing FCS -- 36 bytes total.
2398 skb_size = mp->dev->mtu + 36;
2401 * Make sure that the skb size is a multiple of 8 bytes, as
2402 * the lower three bits of the receive descriptor's buffer
2403 * size field are ignored by the hardware.
2405 mp->skb_size = (skb_size + 7) & ~7;
2408 * If NET_SKB_PAD is smaller than a cache line,
2409 * netdev_alloc_skb() will cause skb->data to be misaligned
2410 * to a cache line boundary. If this is the case, include
2411 * some extra space to allow re-aligning the data area.
2413 mp->skb_size += SKB_DMA_REALIGN;
2416 static int mv643xx_eth_open(struct net_device *dev)
2418 struct mv643xx_eth_private *mp = netdev_priv(dev);
2422 wrlp(mp, INT_CAUSE, 0);
2423 wrlp(mp, INT_CAUSE_EXT, 0);
2424 rdlp(mp, INT_CAUSE_EXT);
2426 err = request_irq(dev->irq, mv643xx_eth_irq,
2427 IRQF_SHARED, dev->name, dev);
2429 netdev_err(dev, "can't assign irq\n");
2433 mv643xx_eth_recalc_skb_size(mp);
2435 napi_enable(&mp->napi);
2437 mp->int_mask = INT_EXT;
2439 for (i = 0; i < mp->rxq_count; i++) {
2440 err = rxq_init(mp, i);
2443 rxq_deinit(mp->rxq + i);
2447 rxq_refill(mp->rxq + i, INT_MAX);
2448 mp->int_mask |= INT_RX_0 << i;
2452 mp->rx_oom.expires = jiffies + (HZ / 10);
2453 add_timer(&mp->rx_oom);
2456 for (i = 0; i < mp->txq_count; i++) {
2457 err = txq_init(mp, i);
2460 txq_deinit(mp->txq + i);
2463 mp->int_mask |= INT_TX_END_0 << i;
2466 add_timer(&mp->mib_counters_timer);
2469 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2470 wrlp(mp, INT_MASK, mp->int_mask);
2476 for (i = 0; i < mp->rxq_count; i++)
2477 rxq_deinit(mp->rxq + i);
2479 free_irq(dev->irq, dev);
2484 static void port_reset(struct mv643xx_eth_private *mp)
2489 for (i = 0; i < mp->rxq_count; i++)
2490 rxq_disable(mp->rxq + i);
2491 for (i = 0; i < mp->txq_count; i++)
2492 txq_disable(mp->txq + i);
2495 u32 ps = rdlp(mp, PORT_STATUS);
2497 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2502 /* Reset the Enable bit in the Configuration Register */
2503 data = rdlp(mp, PORT_SERIAL_CONTROL);
2504 data &= ~(SERIAL_PORT_ENABLE |
2505 DO_NOT_FORCE_LINK_FAIL |
2507 wrlp(mp, PORT_SERIAL_CONTROL, data);
2510 static int mv643xx_eth_stop(struct net_device *dev)
2512 struct mv643xx_eth_private *mp = netdev_priv(dev);
2515 wrlp(mp, INT_MASK_EXT, 0x00000000);
2516 wrlp(mp, INT_MASK, 0x00000000);
2519 napi_disable(&mp->napi);
2521 del_timer_sync(&mp->rx_oom);
2523 netif_carrier_off(dev);
2525 phy_stop(dev->phydev);
2526 free_irq(dev->irq, dev);
2529 mv643xx_eth_get_stats(dev);
2530 mib_counters_update(mp);
2531 del_timer_sync(&mp->mib_counters_timer);
2533 for (i = 0; i < mp->rxq_count; i++)
2534 rxq_deinit(mp->rxq + i);
2535 for (i = 0; i < mp->txq_count; i++)
2536 txq_deinit(mp->txq + i);
2541 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2548 ret = phy_mii_ioctl(dev->phydev, ifr, cmd);
2550 mv643xx_eth_adjust_link(dev);
2554 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2556 struct mv643xx_eth_private *mp = netdev_priv(dev);
2559 mv643xx_eth_recalc_skb_size(mp);
2560 tx_set_rate(mp, 1000000000, 16777216);
2562 if (!netif_running(dev))
2566 * Stop and then re-open the interface. This will allocate RX
2567 * skbs of the new MTU.
2568 * There is a possible danger that the open will not succeed,
2569 * due to memory being full.
2571 mv643xx_eth_stop(dev);
2572 if (mv643xx_eth_open(dev)) {
2574 "fatal error on re-opening device after MTU change\n");
2580 static void tx_timeout_task(struct work_struct *ugly)
2582 struct mv643xx_eth_private *mp;
2584 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2585 if (netif_running(mp->dev)) {
2586 netif_tx_stop_all_queues(mp->dev);
2589 netif_tx_wake_all_queues(mp->dev);
2593 static void mv643xx_eth_tx_timeout(struct net_device *dev, unsigned int txqueue)
2595 struct mv643xx_eth_private *mp = netdev_priv(dev);
2597 netdev_info(dev, "tx timeout\n");
2599 schedule_work(&mp->tx_timeout_task);
2602 #ifdef CONFIG_NET_POLL_CONTROLLER
2603 static void mv643xx_eth_netpoll(struct net_device *dev)
2605 struct mv643xx_eth_private *mp = netdev_priv(dev);
2607 wrlp(mp, INT_MASK, 0x00000000);
2610 mv643xx_eth_irq(dev->irq, dev);
2612 wrlp(mp, INT_MASK, mp->int_mask);
2617 /* platform glue ************************************************************/
2619 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2620 const struct mbus_dram_target_info *dram)
2622 void __iomem *base = msp->base;
2627 for (i = 0; i < 6; i++) {
2628 writel(0, base + WINDOW_BASE(i));
2629 writel(0, base + WINDOW_SIZE(i));
2631 writel(0, base + WINDOW_REMAP_HIGH(i));
2637 for (i = 0; i < dram->num_cs; i++) {
2638 const struct mbus_dram_window *cs = dram->cs + i;
2640 writel((cs->base & 0xffff0000) |
2641 (cs->mbus_attr << 8) |
2642 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2643 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2645 win_enable &= ~(1 << i);
2646 win_protect |= 3 << (2 * i);
2649 writel(win_enable, base + WINDOW_BAR_ENABLE);
2650 msp->win_protect = win_protect;
2653 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2656 * Check whether we have a 14-bit coal limit field in bits
2657 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2658 * SDMA config register.
2660 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2661 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2662 msp->extended_rx_coal_limit = 1;
2664 msp->extended_rx_coal_limit = 0;
2667 * Check whether the MAC supports TX rate control, and if
2668 * yes, whether its associated registers are in the old or
2671 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2672 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2673 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2675 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2676 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2677 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2679 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2683 #if defined(CONFIG_OF)
2684 static const struct of_device_id mv643xx_eth_shared_ids[] = {
2685 { .compatible = "marvell,orion-eth", },
2686 { .compatible = "marvell,kirkwood-eth", },
2689 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids);
2692 #if defined(CONFIG_OF_IRQ) && !defined(CONFIG_MV64X60)
2693 #define mv643xx_eth_property(_np, _name, _v) \
2696 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \
2700 static struct platform_device *port_platdev[3];
2702 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
2703 struct device_node *pnp)
2705 struct platform_device *ppdev;
2706 struct mv643xx_eth_platform_data ppd;
2707 struct resource res;
2708 const char *mac_addr;
2712 memset(&ppd, 0, sizeof(ppd));
2715 memset(&res, 0, sizeof(res));
2716 if (of_irq_to_resource(pnp, 0, &res) <= 0) {
2717 dev_err(&pdev->dev, "missing interrupt on %pOFn\n", pnp);
2721 if (of_property_read_u32(pnp, "reg", &ppd.port_number)) {
2722 dev_err(&pdev->dev, "missing reg property on %pOFn\n", pnp);
2726 if (ppd.port_number >= 3) {
2727 dev_err(&pdev->dev, "invalid reg property on %pOFn\n", pnp);
2731 while (dev_num < 3 && port_platdev[dev_num])
2735 dev_err(&pdev->dev, "too many ports registered\n");
2739 mac_addr = of_get_mac_address(pnp);
2740 if (!IS_ERR(mac_addr))
2741 ether_addr_copy(ppd.mac_addr, mac_addr);
2743 mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size);
2744 mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr);
2745 mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size);
2746 mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size);
2747 mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr);
2748 mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size);
2750 ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0);
2751 if (!ppd.phy_node) {
2752 ppd.phy_addr = MV643XX_ETH_PHY_NONE;
2753 of_property_read_u32(pnp, "speed", &ppd.speed);
2754 of_property_read_u32(pnp, "duplex", &ppd.duplex);
2757 ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num);
2760 ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
2761 ppdev->dev.of_node = pnp;
2763 ret = platform_device_add_resources(ppdev, &res, 1);
2767 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
2771 ret = platform_device_add(ppdev);
2775 port_platdev[dev_num] = ppdev;
2780 platform_device_put(ppdev);
2784 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2786 struct mv643xx_eth_shared_platform_data *pd;
2787 struct device_node *pnp, *np = pdev->dev.of_node;
2790 /* bail out if not registered from DT */
2794 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
2797 pdev->dev.platform_data = pd;
2799 mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit);
2801 for_each_available_child_of_node(np, pnp) {
2802 ret = mv643xx_eth_shared_of_add_port(pdev, pnp);
2811 static void mv643xx_eth_shared_of_remove(void)
2815 for (n = 0; n < 3; n++) {
2816 platform_device_del(port_platdev[n]);
2817 port_platdev[n] = NULL;
2821 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2826 static inline void mv643xx_eth_shared_of_remove(void)
2831 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2833 static int mv643xx_eth_version_printed;
2834 struct mv643xx_eth_shared_platform_data *pd;
2835 struct mv643xx_eth_shared_private *msp;
2836 const struct mbus_dram_target_info *dram;
2837 struct resource *res;
2840 if (!mv643xx_eth_version_printed++)
2841 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2842 mv643xx_eth_driver_version);
2844 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2848 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
2851 platform_set_drvdata(pdev, msp);
2853 msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
2854 if (msp->base == NULL)
2857 msp->clk = devm_clk_get(&pdev->dev, NULL);
2858 if (!IS_ERR(msp->clk))
2859 clk_prepare_enable(msp->clk);
2862 * (Re-)program MBUS remapping windows if we are asked to.
2864 dram = mv_mbus_dram_info();
2866 mv643xx_eth_conf_mbus_windows(msp, dram);
2868 ret = mv643xx_eth_shared_of_probe(pdev);
2871 pd = dev_get_platdata(&pdev->dev);
2873 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2874 pd->tx_csum_limit : 9 * 1024;
2875 infer_hw_params(msp);
2880 if (!IS_ERR(msp->clk))
2881 clk_disable_unprepare(msp->clk);
2885 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2887 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2889 mv643xx_eth_shared_of_remove();
2890 if (!IS_ERR(msp->clk))
2891 clk_disable_unprepare(msp->clk);
2895 static struct platform_driver mv643xx_eth_shared_driver = {
2896 .probe = mv643xx_eth_shared_probe,
2897 .remove = mv643xx_eth_shared_remove,
2899 .name = MV643XX_ETH_SHARED_NAME,
2900 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids),
2904 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2906 int addr_shift = 5 * mp->port_num;
2909 data = rdl(mp, PHY_ADDR);
2910 data &= ~(0x1f << addr_shift);
2911 data |= (phy_addr & 0x1f) << addr_shift;
2912 wrl(mp, PHY_ADDR, data);
2915 static int phy_addr_get(struct mv643xx_eth_private *mp)
2919 data = rdl(mp, PHY_ADDR);
2921 return (data >> (5 * mp->port_num)) & 0x1f;
2924 static void set_params(struct mv643xx_eth_private *mp,
2925 struct mv643xx_eth_platform_data *pd)
2927 struct net_device *dev = mp->dev;
2928 unsigned int tx_ring_size;
2930 if (is_valid_ether_addr(pd->mac_addr))
2931 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2933 uc_addr_get(mp, dev->dev_addr);
2935 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2936 if (pd->rx_queue_size)
2937 mp->rx_ring_size = pd->rx_queue_size;
2938 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2939 mp->rx_desc_sram_size = pd->rx_sram_size;
2941 mp->rxq_count = pd->rx_queue_count ? : 1;
2943 tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2944 if (pd->tx_queue_size)
2945 tx_ring_size = pd->tx_queue_size;
2947 mp->tx_ring_size = clamp_t(unsigned int, tx_ring_size,
2948 MV643XX_MAX_SKB_DESCS * 2, 4096);
2949 if (mp->tx_ring_size != tx_ring_size)
2950 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
2951 mp->tx_ring_size, tx_ring_size);
2953 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2954 mp->tx_desc_sram_size = pd->tx_sram_size;
2956 mp->txq_count = pd->tx_queue_count ? : 1;
2959 static int get_phy_mode(struct mv643xx_eth_private *mp)
2961 struct device *dev = mp->dev->dev.parent;
2962 phy_interface_t iface;
2966 err = of_get_phy_mode(dev->of_node, &iface);
2968 /* Historical default if unspecified. We could also read/write
2969 * the interface state in the PSC1
2971 if (!dev->of_node || err)
2972 iface = PHY_INTERFACE_MODE_GMII;
2976 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2979 struct phy_device *phydev;
2983 char phy_id[MII_BUS_ID_SIZE + 3];
2985 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2986 start = phy_addr_get(mp) & 0x1f;
2989 start = phy_addr & 0x1f;
2993 /* Attempt to connect to the PHY using orion-mdio */
2994 phydev = ERR_PTR(-ENODEV);
2995 for (i = 0; i < num; i++) {
2996 int addr = (start + i) & 0x1f;
2998 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2999 "orion-mdio-mii", addr);
3001 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
3003 if (!IS_ERR(phydev)) {
3004 phy_addr_set(mp, addr);
3012 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
3014 struct net_device *dev = mp->dev;
3015 struct phy_device *phy = dev->phydev;
3018 phy->autoneg = AUTONEG_ENABLE;
3021 linkmode_copy(phy->advertising, phy->supported);
3022 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
3025 phy->autoneg = AUTONEG_DISABLE;
3026 linkmode_zero(phy->advertising);
3028 phy->duplex = duplex;
3030 phy_start_aneg(phy);
3033 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
3035 struct net_device *dev = mp->dev;
3038 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
3039 if (pscr & SERIAL_PORT_ENABLE) {
3040 pscr &= ~SERIAL_PORT_ENABLE;
3041 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
3044 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
3046 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
3047 if (speed == SPEED_1000)
3048 pscr |= SET_GMII_SPEED_TO_1000;
3049 else if (speed == SPEED_100)
3050 pscr |= SET_MII_SPEED_TO_100;
3052 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
3054 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
3055 if (duplex == DUPLEX_FULL)
3056 pscr |= SET_FULL_DUPLEX_MODE;
3059 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
3062 static const struct net_device_ops mv643xx_eth_netdev_ops = {
3063 .ndo_open = mv643xx_eth_open,
3064 .ndo_stop = mv643xx_eth_stop,
3065 .ndo_start_xmit = mv643xx_eth_xmit,
3066 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
3067 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
3068 .ndo_validate_addr = eth_validate_addr,
3069 .ndo_do_ioctl = mv643xx_eth_ioctl,
3070 .ndo_change_mtu = mv643xx_eth_change_mtu,
3071 .ndo_set_features = mv643xx_eth_set_features,
3072 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
3073 .ndo_get_stats = mv643xx_eth_get_stats,
3074 #ifdef CONFIG_NET_POLL_CONTROLLER
3075 .ndo_poll_controller = mv643xx_eth_netpoll,
3079 static int mv643xx_eth_probe(struct platform_device *pdev)
3081 struct mv643xx_eth_platform_data *pd;
3082 struct mv643xx_eth_private *mp;
3083 struct net_device *dev;
3084 struct phy_device *phydev = NULL;
3085 struct resource *res;
3088 pd = dev_get_platdata(&pdev->dev);
3090 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
3094 if (pd->shared == NULL) {
3095 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
3099 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
3103 SET_NETDEV_DEV(dev, &pdev->dev);
3104 mp = netdev_priv(dev);
3105 platform_set_drvdata(pdev, mp);
3107 mp->shared = platform_get_drvdata(pd->shared);
3108 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
3109 mp->port_num = pd->port_number;
3113 /* Kirkwood resets some registers on gated clocks. Especially
3114 * CLK125_BYPASS_EN must be cleared but is not available on
3115 * all other SoCs/System Controllers using this driver.
3117 if (of_device_is_compatible(pdev->dev.of_node,
3118 "marvell,kirkwood-eth-port"))
3119 wrlp(mp, PORT_SERIAL_CONTROL1,
3120 rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
3123 * Start with a default rate, and if there is a clock, allow
3124 * it to override the default.
3126 mp->t_clk = 133000000;
3127 mp->clk = devm_clk_get(&pdev->dev, NULL);
3128 if (!IS_ERR(mp->clk)) {
3129 clk_prepare_enable(mp->clk);
3130 mp->t_clk = clk_get_rate(mp->clk);
3131 } else if (!IS_ERR(mp->shared->clk)) {
3132 mp->t_clk = clk_get_rate(mp->shared->clk);
3136 netif_set_real_num_tx_queues(dev, mp->txq_count);
3137 netif_set_real_num_rx_queues(dev, mp->rxq_count);
3141 phydev = of_phy_connect(mp->dev, pd->phy_node,
3142 mv643xx_eth_adjust_link, 0,
3147 phy_addr_set(mp, phydev->mdio.addr);
3148 } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
3149 phydev = phy_scan(mp, pd->phy_addr);
3152 err = PTR_ERR(phydev);
3154 phy_init(mp, pd->speed, pd->duplex);
3156 if (err == -ENODEV) {
3157 err = -EPROBE_DEFER;
3163 dev->ethtool_ops = &mv643xx_eth_ethtool_ops;
3165 init_pscr(mp, pd->speed, pd->duplex);
3168 mib_counters_clear(mp);
3170 timer_setup(&mp->mib_counters_timer, mib_counters_timer_wrapper, 0);
3171 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
3173 spin_lock_init(&mp->mib_counters_lock);
3175 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
3177 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
3179 timer_setup(&mp->rx_oom, oom_timer_wrapper, 0);
3182 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
3184 dev->irq = res->start;
3186 dev->netdev_ops = &mv643xx_eth_netdev_ops;
3188 dev->watchdog_timeo = 2 * HZ;
3191 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3192 dev->vlan_features = dev->features;
3194 dev->features |= NETIF_F_RXCSUM;
3195 dev->hw_features = dev->features;
3197 dev->priv_flags |= IFF_UNICAST_FLT;
3198 dev->gso_max_segs = MV643XX_MAX_TSO_SEGS;
3200 /* MTU range: 64 - 9500 */
3202 dev->max_mtu = 9500;
3204 if (mp->shared->win_protect)
3205 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
3207 netif_carrier_off(dev);
3209 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
3211 set_rx_coal(mp, 250);
3214 err = register_netdev(dev);
3218 netdev_notice(dev, "port %d with MAC address %pM\n",
3219 mp->port_num, dev->dev_addr);
3221 if (mp->tx_desc_sram_size > 0)
3222 netdev_notice(dev, "configured with sram\n");
3227 if (!IS_ERR(mp->clk))
3228 clk_disable_unprepare(mp->clk);
3234 static int mv643xx_eth_remove(struct platform_device *pdev)
3236 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3237 struct net_device *dev = mp->dev;
3239 unregister_netdev(mp->dev);
3241 phy_disconnect(dev->phydev);
3242 cancel_work_sync(&mp->tx_timeout_task);
3244 if (!IS_ERR(mp->clk))
3245 clk_disable_unprepare(mp->clk);
3247 free_netdev(mp->dev);
3252 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3254 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3256 /* Mask all interrupts on ethernet port */
3257 wrlp(mp, INT_MASK, 0);
3260 if (netif_running(mp->dev))
3264 static struct platform_driver mv643xx_eth_driver = {
3265 .probe = mv643xx_eth_probe,
3266 .remove = mv643xx_eth_remove,
3267 .shutdown = mv643xx_eth_shutdown,
3269 .name = MV643XX_ETH_NAME,
3273 static struct platform_driver * const drivers[] = {
3274 &mv643xx_eth_shared_driver,
3275 &mv643xx_eth_driver,
3278 static int __init mv643xx_eth_init_module(void)
3280 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
3282 module_init(mv643xx_eth_init_module);
3284 static void __exit mv643xx_eth_cleanup_module(void)
3286 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
3288 module_exit(mv643xx_eth_cleanup_module);
3290 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3291 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3292 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3293 MODULE_LICENSE("GPL");
3294 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3295 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);