2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License
27 * as published by the Free Software Foundation; either version 2
28 * of the License, or (at your option) any later version.
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, see <http://www.gnu.org/licenses/>.
39 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41 #include <linux/init.h>
42 #include <linux/dma-mapping.h>
46 #include <linux/tcp.h>
47 #include <linux/udp.h>
48 #include <linux/etherdevice.h>
49 #include <linux/delay.h>
50 #include <linux/ethtool.h>
51 #include <linux/platform_device.h>
52 #include <linux/module.h>
53 #include <linux/kernel.h>
54 #include <linux/spinlock.h>
55 #include <linux/workqueue.h>
56 #include <linux/phy.h>
57 #include <linux/mv643xx_eth.h>
59 #include <linux/interrupt.h>
60 #include <linux/types.h>
61 #include <linux/slab.h>
62 #include <linux/clk.h>
64 #include <linux/of_irq.h>
65 #include <linux/of_net.h>
66 #include <linux/of_mdio.h>
68 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
69 static char mv643xx_eth_driver_version[] = "1.4";
73 * Registers shared between all ports.
75 #define PHY_ADDR 0x0000
76 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
77 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
78 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
79 #define WINDOW_BAR_ENABLE 0x0290
80 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
83 * Main per-port registers. These live at offset 0x0400 for
84 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
86 #define PORT_CONFIG 0x0000
87 #define UNICAST_PROMISCUOUS_MODE 0x00000001
88 #define PORT_CONFIG_EXT 0x0004
89 #define MAC_ADDR_LOW 0x0014
90 #define MAC_ADDR_HIGH 0x0018
91 #define SDMA_CONFIG 0x001c
92 #define TX_BURST_SIZE_16_64BIT 0x01000000
93 #define TX_BURST_SIZE_4_64BIT 0x00800000
94 #define BLM_TX_NO_SWAP 0x00000020
95 #define BLM_RX_NO_SWAP 0x00000010
96 #define RX_BURST_SIZE_16_64BIT 0x00000008
97 #define RX_BURST_SIZE_4_64BIT 0x00000004
98 #define PORT_SERIAL_CONTROL 0x003c
99 #define SET_MII_SPEED_TO_100 0x01000000
100 #define SET_GMII_SPEED_TO_1000 0x00800000
101 #define SET_FULL_DUPLEX_MODE 0x00200000
102 #define MAX_RX_PACKET_9700BYTE 0x000a0000
103 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
104 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
105 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
106 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
107 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
108 #define FORCE_LINK_PASS 0x00000002
109 #define SERIAL_PORT_ENABLE 0x00000001
110 #define PORT_STATUS 0x0044
111 #define TX_FIFO_EMPTY 0x00000400
112 #define TX_IN_PROGRESS 0x00000080
113 #define PORT_SPEED_MASK 0x00000030
114 #define PORT_SPEED_1000 0x00000010
115 #define PORT_SPEED_100 0x00000020
116 #define PORT_SPEED_10 0x00000000
117 #define FLOW_CONTROL_ENABLED 0x00000008
118 #define FULL_DUPLEX 0x00000004
119 #define LINK_UP 0x00000002
120 #define TXQ_COMMAND 0x0048
121 #define TXQ_FIX_PRIO_CONF 0x004c
122 #define PORT_SERIAL_CONTROL1 0x004c
123 #define CLK125_BYPASS_EN 0x00000010
124 #define TX_BW_RATE 0x0050
125 #define TX_BW_MTU 0x0058
126 #define TX_BW_BURST 0x005c
127 #define INT_CAUSE 0x0060
128 #define INT_TX_END 0x07f80000
129 #define INT_TX_END_0 0x00080000
130 #define INT_RX 0x000003fc
131 #define INT_RX_0 0x00000004
132 #define INT_EXT 0x00000002
133 #define INT_CAUSE_EXT 0x0064
134 #define INT_EXT_LINK_PHY 0x00110000
135 #define INT_EXT_TX 0x000000ff
136 #define INT_MASK 0x0068
137 #define INT_MASK_EXT 0x006c
138 #define TX_FIFO_URGENT_THRESHOLD 0x0074
139 #define RX_DISCARD_FRAME_CNT 0x0084
140 #define RX_OVERRUN_FRAME_CNT 0x0088
141 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
142 #define TX_BW_RATE_MOVED 0x00e0
143 #define TX_BW_MTU_MOVED 0x00e8
144 #define TX_BW_BURST_MOVED 0x00ec
145 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
146 #define RXQ_COMMAND 0x0280
147 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
148 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
149 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
150 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
153 * Misc per-port registers.
155 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
156 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
157 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
158 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
162 * SDMA configuration register default value.
164 #if defined(__BIG_ENDIAN)
165 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
166 (RX_BURST_SIZE_4_64BIT | \
167 TX_BURST_SIZE_4_64BIT)
168 #elif defined(__LITTLE_ENDIAN)
169 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
170 (RX_BURST_SIZE_4_64BIT | \
173 TX_BURST_SIZE_4_64BIT)
175 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
182 #define DEFAULT_RX_QUEUE_SIZE 128
183 #define DEFAULT_TX_QUEUE_SIZE 512
184 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
186 #define TSO_HEADER_SIZE 128
188 /* Max number of allowed TCP segments for software TSO */
189 #define MV643XX_MAX_TSO_SEGS 100
190 #define MV643XX_MAX_SKB_DESCS (MV643XX_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
192 #define IS_TSO_HEADER(txq, addr) \
193 ((addr >= txq->tso_hdrs_dma) && \
194 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
198 #if defined(__BIG_ENDIAN)
200 u16 byte_cnt; /* Descriptor buffer byte count */
201 u16 buf_size; /* Buffer size */
202 u32 cmd_sts; /* Descriptor command status */
203 u32 next_desc_ptr; /* Next descriptor pointer */
204 u32 buf_ptr; /* Descriptor buffer pointer */
208 u16 byte_cnt; /* buffer byte count */
209 u16 l4i_chk; /* CPU provided TCP checksum */
210 u32 cmd_sts; /* Command/status field */
211 u32 next_desc_ptr; /* Pointer to next descriptor */
212 u32 buf_ptr; /* pointer to buffer for this descriptor*/
214 #elif defined(__LITTLE_ENDIAN)
216 u32 cmd_sts; /* Descriptor command status */
217 u16 buf_size; /* Buffer size */
218 u16 byte_cnt; /* Descriptor buffer byte count */
219 u32 buf_ptr; /* Descriptor buffer pointer */
220 u32 next_desc_ptr; /* Next descriptor pointer */
224 u32 cmd_sts; /* Command/status field */
225 u16 l4i_chk; /* CPU provided TCP checksum */
226 u16 byte_cnt; /* buffer byte count */
227 u32 buf_ptr; /* pointer to buffer for this descriptor*/
228 u32 next_desc_ptr; /* Pointer to next descriptor */
231 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
234 /* RX & TX descriptor command */
235 #define BUFFER_OWNED_BY_DMA 0x80000000
237 /* RX & TX descriptor status */
238 #define ERROR_SUMMARY 0x00000001
240 /* RX descriptor status */
241 #define LAYER_4_CHECKSUM_OK 0x40000000
242 #define RX_ENABLE_INTERRUPT 0x20000000
243 #define RX_FIRST_DESC 0x08000000
244 #define RX_LAST_DESC 0x04000000
245 #define RX_IP_HDR_OK 0x02000000
246 #define RX_PKT_IS_IPV4 0x01000000
247 #define RX_PKT_IS_ETHERNETV2 0x00800000
248 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
249 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
250 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
252 /* TX descriptor command */
253 #define TX_ENABLE_INTERRUPT 0x00800000
254 #define GEN_CRC 0x00400000
255 #define TX_FIRST_DESC 0x00200000
256 #define TX_LAST_DESC 0x00100000
257 #define ZERO_PADDING 0x00080000
258 #define GEN_IP_V4_CHECKSUM 0x00040000
259 #define GEN_TCP_UDP_CHECKSUM 0x00020000
260 #define UDP_FRAME 0x00010000
261 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
262 #define GEN_TCP_UDP_CHK_FULL 0x00000400
263 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
265 #define TX_IHL_SHIFT 11
268 /* global *******************************************************************/
269 struct mv643xx_eth_shared_private {
271 * Ethernet controller base address.
276 * Per-port MBUS window access register value.
281 * Hardware-specific parameters.
283 int extended_rx_coal_limit;
289 #define TX_BW_CONTROL_ABSENT 0
290 #define TX_BW_CONTROL_OLD_LAYOUT 1
291 #define TX_BW_CONTROL_NEW_LAYOUT 2
293 static int mv643xx_eth_open(struct net_device *dev);
294 static int mv643xx_eth_stop(struct net_device *dev);
297 /* per-port *****************************************************************/
298 struct mib_counters {
299 u64 good_octets_received;
300 u32 bad_octets_received;
301 u32 internal_mac_transmit_err;
302 u32 good_frames_received;
303 u32 bad_frames_received;
304 u32 broadcast_frames_received;
305 u32 multicast_frames_received;
306 u32 frames_64_octets;
307 u32 frames_65_to_127_octets;
308 u32 frames_128_to_255_octets;
309 u32 frames_256_to_511_octets;
310 u32 frames_512_to_1023_octets;
311 u32 frames_1024_to_max_octets;
312 u64 good_octets_sent;
313 u32 good_frames_sent;
314 u32 excessive_collision;
315 u32 multicast_frames_sent;
316 u32 broadcast_frames_sent;
317 u32 unrec_mac_control_received;
319 u32 good_fc_received;
321 u32 undersize_received;
322 u32 fragments_received;
323 u32 oversize_received;
325 u32 mac_receive_error;
329 /* Non MIB hardware counters */
343 struct rx_desc *rx_desc_area;
344 dma_addr_t rx_desc_dma;
345 int rx_desc_area_size;
346 struct sk_buff **rx_skb;
358 int tx_stop_threshold;
359 int tx_wake_threshold;
362 dma_addr_t tso_hdrs_dma;
364 struct tx_desc *tx_desc_area;
365 dma_addr_t tx_desc_dma;
366 int tx_desc_area_size;
368 struct sk_buff_head tx_skb;
370 unsigned long tx_packets;
371 unsigned long tx_bytes;
372 unsigned long tx_dropped;
375 struct mv643xx_eth_private {
376 struct mv643xx_eth_shared_private *shared;
380 struct net_device *dev;
382 struct phy_device *phy;
384 struct timer_list mib_counters_timer;
385 spinlock_t mib_counters_lock;
386 struct mib_counters mib_counters;
388 struct work_struct tx_timeout_task;
390 struct napi_struct napi;
405 unsigned long rx_desc_sram_addr;
406 int rx_desc_sram_size;
408 struct timer_list rx_oom;
409 struct rx_queue rxq[8];
415 unsigned long tx_desc_sram_addr;
416 int tx_desc_sram_size;
418 struct tx_queue txq[8];
421 * Hardware-specific parameters.
428 /* port register accessors **************************************************/
429 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
431 return readl(mp->shared->base + offset);
434 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
436 return readl(mp->base + offset);
439 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
441 writel(data, mp->shared->base + offset);
444 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
446 writel(data, mp->base + offset);
450 /* rxq/txq helper functions *************************************************/
451 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
453 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
456 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
458 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
461 static void rxq_enable(struct rx_queue *rxq)
463 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
464 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
467 static void rxq_disable(struct rx_queue *rxq)
469 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
470 u8 mask = 1 << rxq->index;
472 wrlp(mp, RXQ_COMMAND, mask << 8);
473 while (rdlp(mp, RXQ_COMMAND) & mask)
477 static void txq_reset_hw_ptr(struct tx_queue *txq)
479 struct mv643xx_eth_private *mp = txq_to_mp(txq);
482 addr = (u32)txq->tx_desc_dma;
483 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
484 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
487 static void txq_enable(struct tx_queue *txq)
489 struct mv643xx_eth_private *mp = txq_to_mp(txq);
490 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
493 static void txq_disable(struct tx_queue *txq)
495 struct mv643xx_eth_private *mp = txq_to_mp(txq);
496 u8 mask = 1 << txq->index;
498 wrlp(mp, TXQ_COMMAND, mask << 8);
499 while (rdlp(mp, TXQ_COMMAND) & mask)
503 static void txq_maybe_wake(struct tx_queue *txq)
505 struct mv643xx_eth_private *mp = txq_to_mp(txq);
506 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
508 if (netif_tx_queue_stopped(nq)) {
509 __netif_tx_lock(nq, smp_processor_id());
510 if (txq->tx_desc_count <= txq->tx_wake_threshold)
511 netif_tx_wake_queue(nq);
512 __netif_tx_unlock(nq);
516 static int rxq_process(struct rx_queue *rxq, int budget)
518 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
519 struct net_device_stats *stats = &mp->dev->stats;
523 while (rx < budget && rxq->rx_desc_count) {
524 struct rx_desc *rx_desc;
525 unsigned int cmd_sts;
529 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
531 cmd_sts = rx_desc->cmd_sts;
532 if (cmd_sts & BUFFER_OWNED_BY_DMA)
536 skb = rxq->rx_skb[rxq->rx_curr_desc];
537 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
540 if (rxq->rx_curr_desc == rxq->rx_ring_size)
541 rxq->rx_curr_desc = 0;
543 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
544 rx_desc->buf_size, DMA_FROM_DEVICE);
545 rxq->rx_desc_count--;
548 mp->work_rx_refill |= 1 << rxq->index;
550 byte_cnt = rx_desc->byte_cnt;
555 * Note that the descriptor byte count includes 2 dummy
556 * bytes automatically inserted by the hardware at the
557 * start of the packet (which we don't count), and a 4
558 * byte CRC at the end of the packet (which we do count).
561 stats->rx_bytes += byte_cnt - 2;
564 * In case we received a packet without first / last bits
565 * on, or the error summary bit is set, the packet needs
568 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
569 != (RX_FIRST_DESC | RX_LAST_DESC))
573 * The -4 is for the CRC in the trailer of the
576 skb_put(skb, byte_cnt - 2 - 4);
578 if (cmd_sts & LAYER_4_CHECKSUM_OK)
579 skb->ip_summed = CHECKSUM_UNNECESSARY;
580 skb->protocol = eth_type_trans(skb, mp->dev);
582 napi_gro_receive(&mp->napi, skb);
589 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
590 (RX_FIRST_DESC | RX_LAST_DESC)) {
593 "received packet spanning multiple descriptors\n");
596 if (cmd_sts & ERROR_SUMMARY)
603 mp->work_rx &= ~(1 << rxq->index);
608 static int rxq_refill(struct rx_queue *rxq, int budget)
610 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
614 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
617 struct rx_desc *rx_desc;
620 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
628 skb_reserve(skb, SKB_DMA_REALIGN);
631 rxq->rx_desc_count++;
633 rx = rxq->rx_used_desc++;
634 if (rxq->rx_used_desc == rxq->rx_ring_size)
635 rxq->rx_used_desc = 0;
637 rx_desc = rxq->rx_desc_area + rx;
639 size = skb_end_pointer(skb) - skb->data;
640 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
643 rx_desc->buf_size = size;
644 rxq->rx_skb[rx] = skb;
646 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
650 * The hardware automatically prepends 2 bytes of
651 * dummy data to each received packet, so that the
652 * IP header ends up 16-byte aligned.
657 if (refilled < budget)
658 mp->work_rx_refill &= ~(1 << rxq->index);
665 /* tx ***********************************************************************/
666 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
670 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
671 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
673 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
680 static inline __be16 sum16_as_be(__sum16 sum)
682 return (__force __be16)sum;
685 static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb,
686 u16 *l4i_chk, u32 *command, int length)
691 if (skb->ip_summed == CHECKSUM_PARTIAL) {
695 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
696 skb->protocol != htons(ETH_P_8021Q));
698 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
699 tag_bytes = hdr_len - ETH_HLEN;
701 if (length - hdr_len > mp->shared->tx_csum_limit ||
702 unlikely(tag_bytes & ~12)) {
703 ret = skb_checksum_help(skb);
710 cmd |= MAC_HDR_EXTRA_4_BYTES;
712 cmd |= MAC_HDR_EXTRA_8_BYTES;
714 cmd |= GEN_TCP_UDP_CHECKSUM | GEN_TCP_UDP_CHK_FULL |
716 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
718 /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL
719 * it seems we don't need to pass the initial checksum. */
720 switch (ip_hdr(skb)->protocol) {
729 WARN(1, "protocol not supported");
733 /* Errata BTS #50, IHL must be 5 if no HW checksum */
734 cmd |= 5 << TX_IHL_SHIFT;
741 txq_put_data_tso(struct net_device *dev, struct tx_queue *txq,
742 struct sk_buff *skb, char *data, int length,
743 bool last_tcp, bool is_last)
747 struct tx_desc *desc;
749 tx_index = txq->tx_curr_desc++;
750 if (txq->tx_curr_desc == txq->tx_ring_size)
751 txq->tx_curr_desc = 0;
752 desc = &txq->tx_desc_area[tx_index];
755 desc->byte_cnt = length;
756 desc->buf_ptr = dma_map_single(dev->dev.parent, data,
757 length, DMA_TO_DEVICE);
758 if (unlikely(dma_mapping_error(dev->dev.parent, desc->buf_ptr))) {
759 WARN(1, "dma_map_single failed!\n");
763 cmd_sts = BUFFER_OWNED_BY_DMA;
765 /* last descriptor in the TCP packet */
766 cmd_sts |= ZERO_PADDING | TX_LAST_DESC;
767 /* last descriptor in SKB */
769 cmd_sts |= TX_ENABLE_INTERRUPT;
771 desc->cmd_sts = cmd_sts;
776 txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length)
778 struct mv643xx_eth_private *mp = txq_to_mp(txq);
779 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
781 struct tx_desc *desc;
786 tx_index = txq->tx_curr_desc;
787 desc = &txq->tx_desc_area[tx_index];
789 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_csum, length);
791 WARN(1, "failed to prepare checksum!");
793 /* Should we set this? Can't use the value from skb_tx_csum()
794 * as it's not the correct initial L4 checksum to use. */
797 desc->byte_cnt = hdr_len;
798 desc->buf_ptr = txq->tso_hdrs_dma +
799 txq->tx_curr_desc * TSO_HEADER_SIZE;
800 desc->cmd_sts = cmd_csum | BUFFER_OWNED_BY_DMA | TX_FIRST_DESC |
804 if (txq->tx_curr_desc == txq->tx_ring_size)
805 txq->tx_curr_desc = 0;
808 static int txq_submit_tso(struct tx_queue *txq, struct sk_buff *skb,
809 struct net_device *dev)
811 struct mv643xx_eth_private *mp = txq_to_mp(txq);
812 int total_len, data_left, ret;
815 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
817 /* Count needed descriptors */
818 if ((txq->tx_desc_count + tso_count_descs(skb)) >= txq->tx_ring_size) {
819 netdev_dbg(dev, "not enough descriptors for TSO!\n");
823 /* Initialize the TSO handler, and prepare the first payload */
824 tso_start(skb, &tso);
826 total_len = skb->len - hdr_len;
827 while (total_len > 0) {
830 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
831 total_len -= data_left;
834 /* prepare packet headers: MAC + IP + TCP */
835 hdr = txq->tso_hdrs + txq->tx_curr_desc * TSO_HEADER_SIZE;
836 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
837 txq_put_hdr_tso(skb, txq, data_left);
839 while (data_left > 0) {
843 size = min_t(int, tso.size, data_left);
844 ret = txq_put_data_tso(dev, txq, skb, tso.data, size,
850 tso_build_data(skb, &tso, size);
854 __skb_queue_tail(&txq->tx_skb, skb);
855 skb_tx_timestamp(skb);
857 /* clear TX_END status */
858 mp->work_tx_end &= ~(1 << txq->index);
860 /* ensure all descriptors are written before poking hardware */
863 txq->tx_desc_count += desc_count;
866 /* TODO: Release all used data descriptors; header descriptors must not
872 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
874 struct mv643xx_eth_private *mp = txq_to_mp(txq);
875 int nr_frags = skb_shinfo(skb)->nr_frags;
878 for (frag = 0; frag < nr_frags; frag++) {
879 skb_frag_t *this_frag;
881 struct tx_desc *desc;
884 this_frag = &skb_shinfo(skb)->frags[frag];
885 addr = page_address(this_frag->page.p) + this_frag->page_offset;
886 tx_index = txq->tx_curr_desc++;
887 if (txq->tx_curr_desc == txq->tx_ring_size)
888 txq->tx_curr_desc = 0;
889 desc = &txq->tx_desc_area[tx_index];
892 * The last fragment will generate an interrupt
893 * which will free the skb on TX completion.
895 if (frag == nr_frags - 1) {
896 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
897 ZERO_PADDING | TX_LAST_DESC |
900 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
904 desc->byte_cnt = skb_frag_size(this_frag);
905 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, addr,
906 desc->byte_cnt, DMA_TO_DEVICE);
910 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb,
911 struct net_device *dev)
913 struct mv643xx_eth_private *mp = txq_to_mp(txq);
914 int nr_frags = skb_shinfo(skb)->nr_frags;
916 struct tx_desc *desc;
924 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
926 netdev_err(dev, "tx queue full?!\n");
930 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len);
933 cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
935 tx_index = txq->tx_curr_desc++;
936 if (txq->tx_curr_desc == txq->tx_ring_size)
937 txq->tx_curr_desc = 0;
938 desc = &txq->tx_desc_area[tx_index];
941 txq_submit_frag_skb(txq, skb);
942 length = skb_headlen(skb);
944 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
948 desc->l4i_chk = l4i_chk;
949 desc->byte_cnt = length;
950 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
951 length, DMA_TO_DEVICE);
953 __skb_queue_tail(&txq->tx_skb, skb);
955 skb_tx_timestamp(skb);
957 /* ensure all other descriptors are written before first cmd_sts */
959 desc->cmd_sts = cmd_sts;
961 /* clear TX_END status */
962 mp->work_tx_end &= ~(1 << txq->index);
964 /* ensure all descriptors are written before poking hardware */
968 txq->tx_desc_count += nr_frags + 1;
973 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
975 struct mv643xx_eth_private *mp = netdev_priv(dev);
976 int length, queue, ret;
977 struct tx_queue *txq;
978 struct netdev_queue *nq;
980 queue = skb_get_queue_mapping(skb);
981 txq = mp->txq + queue;
982 nq = netdev_get_tx_queue(dev, queue);
984 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
985 netdev_printk(KERN_DEBUG, dev,
986 "failed to linearize skb with tiny unaligned fragment\n");
987 return NETDEV_TX_BUSY;
993 ret = txq_submit_tso(txq, skb, dev);
995 ret = txq_submit_skb(txq, skb, dev);
997 txq->tx_bytes += length;
1000 if (txq->tx_desc_count >= txq->tx_stop_threshold)
1001 netif_tx_stop_queue(nq);
1004 dev_kfree_skb_any(skb);
1007 return NETDEV_TX_OK;
1011 /* tx napi ******************************************************************/
1012 static void txq_kick(struct tx_queue *txq)
1014 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1015 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1019 __netif_tx_lock(nq, smp_processor_id());
1021 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1024 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1025 expected_ptr = (u32)txq->tx_desc_dma +
1026 txq->tx_curr_desc * sizeof(struct tx_desc);
1028 if (hw_desc_ptr != expected_ptr)
1032 __netif_tx_unlock(nq);
1034 mp->work_tx_end &= ~(1 << txq->index);
1037 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
1039 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1040 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1043 __netif_tx_lock_bh(nq);
1046 while (reclaimed < budget && txq->tx_desc_count > 0) {
1048 struct tx_desc *desc;
1051 tx_index = txq->tx_used_desc;
1052 desc = &txq->tx_desc_area[tx_index];
1053 cmd_sts = desc->cmd_sts;
1055 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1058 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1061 txq->tx_used_desc = tx_index + 1;
1062 if (txq->tx_used_desc == txq->tx_ring_size)
1063 txq->tx_used_desc = 0;
1066 txq->tx_desc_count--;
1068 if (!IS_TSO_HEADER(txq, desc->buf_ptr))
1069 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
1070 desc->byte_cnt, DMA_TO_DEVICE);
1072 if (cmd_sts & TX_ENABLE_INTERRUPT) {
1073 struct sk_buff *skb = __skb_dequeue(&txq->tx_skb);
1079 if (cmd_sts & ERROR_SUMMARY) {
1080 netdev_info(mp->dev, "tx error\n");
1081 mp->dev->stats.tx_errors++;
1086 __netif_tx_unlock_bh(nq);
1088 if (reclaimed < budget)
1089 mp->work_tx &= ~(1 << txq->index);
1095 /* tx rate control **********************************************************/
1097 * Set total maximum TX rate (shared by all TX queues for this port)
1098 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1100 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1106 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1107 if (token_rate > 1023)
1110 mtu = (mp->dev->mtu + 255) >> 8;
1114 bucket_size = (burst + 255) >> 8;
1115 if (bucket_size > 65535)
1116 bucket_size = 65535;
1118 switch (mp->shared->tx_bw_control) {
1119 case TX_BW_CONTROL_OLD_LAYOUT:
1120 wrlp(mp, TX_BW_RATE, token_rate);
1121 wrlp(mp, TX_BW_MTU, mtu);
1122 wrlp(mp, TX_BW_BURST, bucket_size);
1124 case TX_BW_CONTROL_NEW_LAYOUT:
1125 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1126 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1127 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1132 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1134 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1138 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1139 if (token_rate > 1023)
1142 bucket_size = (burst + 255) >> 8;
1143 if (bucket_size > 65535)
1144 bucket_size = 65535;
1146 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1147 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1150 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1152 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1157 * Turn on fixed priority mode.
1160 switch (mp->shared->tx_bw_control) {
1161 case TX_BW_CONTROL_OLD_LAYOUT:
1162 off = TXQ_FIX_PRIO_CONF;
1164 case TX_BW_CONTROL_NEW_LAYOUT:
1165 off = TXQ_FIX_PRIO_CONF_MOVED;
1170 val = rdlp(mp, off);
1171 val |= 1 << txq->index;
1177 /* mii management interface *************************************************/
1178 static void mv643xx_eth_adjust_link(struct net_device *dev)
1180 struct mv643xx_eth_private *mp = netdev_priv(dev);
1181 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1182 u32 autoneg_disable = FORCE_LINK_PASS |
1183 DISABLE_AUTO_NEG_SPEED_GMII |
1184 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1185 DISABLE_AUTO_NEG_FOR_DUPLEX;
1187 if (mp->phy->autoneg == AUTONEG_ENABLE) {
1188 /* enable auto negotiation */
1189 pscr &= ~autoneg_disable;
1193 pscr |= autoneg_disable;
1195 if (mp->phy->speed == SPEED_1000) {
1196 /* force gigabit, half duplex not supported */
1197 pscr |= SET_GMII_SPEED_TO_1000;
1198 pscr |= SET_FULL_DUPLEX_MODE;
1202 pscr &= ~SET_GMII_SPEED_TO_1000;
1204 if (mp->phy->speed == SPEED_100)
1205 pscr |= SET_MII_SPEED_TO_100;
1207 pscr &= ~SET_MII_SPEED_TO_100;
1209 if (mp->phy->duplex == DUPLEX_FULL)
1210 pscr |= SET_FULL_DUPLEX_MODE;
1212 pscr &= ~SET_FULL_DUPLEX_MODE;
1215 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1218 /* statistics ***************************************************************/
1219 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1221 struct mv643xx_eth_private *mp = netdev_priv(dev);
1222 struct net_device_stats *stats = &dev->stats;
1223 unsigned long tx_packets = 0;
1224 unsigned long tx_bytes = 0;
1225 unsigned long tx_dropped = 0;
1228 for (i = 0; i < mp->txq_count; i++) {
1229 struct tx_queue *txq = mp->txq + i;
1231 tx_packets += txq->tx_packets;
1232 tx_bytes += txq->tx_bytes;
1233 tx_dropped += txq->tx_dropped;
1236 stats->tx_packets = tx_packets;
1237 stats->tx_bytes = tx_bytes;
1238 stats->tx_dropped = tx_dropped;
1243 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1245 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1248 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1252 for (i = 0; i < 0x80; i += 4)
1255 /* Clear non MIB hw counters also */
1256 rdlp(mp, RX_DISCARD_FRAME_CNT);
1257 rdlp(mp, RX_OVERRUN_FRAME_CNT);
1260 static void mib_counters_update(struct mv643xx_eth_private *mp)
1262 struct mib_counters *p = &mp->mib_counters;
1264 spin_lock_bh(&mp->mib_counters_lock);
1265 p->good_octets_received += mib_read(mp, 0x00);
1266 p->bad_octets_received += mib_read(mp, 0x08);
1267 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1268 p->good_frames_received += mib_read(mp, 0x10);
1269 p->bad_frames_received += mib_read(mp, 0x14);
1270 p->broadcast_frames_received += mib_read(mp, 0x18);
1271 p->multicast_frames_received += mib_read(mp, 0x1c);
1272 p->frames_64_octets += mib_read(mp, 0x20);
1273 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1274 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1275 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1276 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1277 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1278 p->good_octets_sent += mib_read(mp, 0x38);
1279 p->good_frames_sent += mib_read(mp, 0x40);
1280 p->excessive_collision += mib_read(mp, 0x44);
1281 p->multicast_frames_sent += mib_read(mp, 0x48);
1282 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1283 p->unrec_mac_control_received += mib_read(mp, 0x50);
1284 p->fc_sent += mib_read(mp, 0x54);
1285 p->good_fc_received += mib_read(mp, 0x58);
1286 p->bad_fc_received += mib_read(mp, 0x5c);
1287 p->undersize_received += mib_read(mp, 0x60);
1288 p->fragments_received += mib_read(mp, 0x64);
1289 p->oversize_received += mib_read(mp, 0x68);
1290 p->jabber_received += mib_read(mp, 0x6c);
1291 p->mac_receive_error += mib_read(mp, 0x70);
1292 p->bad_crc_event += mib_read(mp, 0x74);
1293 p->collision += mib_read(mp, 0x78);
1294 p->late_collision += mib_read(mp, 0x7c);
1295 /* Non MIB hardware counters */
1296 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1297 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1298 spin_unlock_bh(&mp->mib_counters_lock);
1301 static void mib_counters_timer_wrapper(unsigned long _mp)
1303 struct mv643xx_eth_private *mp = (void *)_mp;
1304 mib_counters_update(mp);
1305 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1309 /* interrupt coalescing *****************************************************/
1311 * Hardware coalescing parameters are set in units of 64 t_clk
1314 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1316 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1318 * In the ->set*() methods, we round the computed register value
1319 * to the nearest integer.
1321 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1323 u32 val = rdlp(mp, SDMA_CONFIG);
1326 if (mp->shared->extended_rx_coal_limit)
1327 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1329 temp = (val & 0x003fff00) >> 8;
1332 do_div(temp, mp->t_clk);
1334 return (unsigned int)temp;
1337 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1342 temp = (u64)usec * mp->t_clk;
1344 do_div(temp, 64000000);
1346 val = rdlp(mp, SDMA_CONFIG);
1347 if (mp->shared->extended_rx_coal_limit) {
1351 val |= (temp & 0x8000) << 10;
1352 val |= (temp & 0x7fff) << 7;
1357 val |= (temp & 0x3fff) << 8;
1359 wrlp(mp, SDMA_CONFIG, val);
1362 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1366 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1368 do_div(temp, mp->t_clk);
1370 return (unsigned int)temp;
1373 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1377 temp = (u64)usec * mp->t_clk;
1379 do_div(temp, 64000000);
1384 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1388 /* ethtool ******************************************************************/
1389 struct mv643xx_eth_stats {
1390 char stat_string[ETH_GSTRING_LEN];
1397 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1398 offsetof(struct net_device, stats.m), -1 }
1400 #define MIBSTAT(m) \
1401 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1402 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1404 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1413 MIBSTAT(good_octets_received),
1414 MIBSTAT(bad_octets_received),
1415 MIBSTAT(internal_mac_transmit_err),
1416 MIBSTAT(good_frames_received),
1417 MIBSTAT(bad_frames_received),
1418 MIBSTAT(broadcast_frames_received),
1419 MIBSTAT(multicast_frames_received),
1420 MIBSTAT(frames_64_octets),
1421 MIBSTAT(frames_65_to_127_octets),
1422 MIBSTAT(frames_128_to_255_octets),
1423 MIBSTAT(frames_256_to_511_octets),
1424 MIBSTAT(frames_512_to_1023_octets),
1425 MIBSTAT(frames_1024_to_max_octets),
1426 MIBSTAT(good_octets_sent),
1427 MIBSTAT(good_frames_sent),
1428 MIBSTAT(excessive_collision),
1429 MIBSTAT(multicast_frames_sent),
1430 MIBSTAT(broadcast_frames_sent),
1431 MIBSTAT(unrec_mac_control_received),
1433 MIBSTAT(good_fc_received),
1434 MIBSTAT(bad_fc_received),
1435 MIBSTAT(undersize_received),
1436 MIBSTAT(fragments_received),
1437 MIBSTAT(oversize_received),
1438 MIBSTAT(jabber_received),
1439 MIBSTAT(mac_receive_error),
1440 MIBSTAT(bad_crc_event),
1442 MIBSTAT(late_collision),
1443 MIBSTAT(rx_discard),
1444 MIBSTAT(rx_overrun),
1448 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1449 struct ethtool_cmd *cmd)
1453 err = phy_read_status(mp->phy);
1455 err = phy_ethtool_gset(mp->phy, cmd);
1458 * The MAC does not support 1000baseT_Half.
1460 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1461 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1467 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1468 struct ethtool_cmd *cmd)
1472 port_status = rdlp(mp, PORT_STATUS);
1474 cmd->supported = SUPPORTED_MII;
1475 cmd->advertising = ADVERTISED_MII;
1476 switch (port_status & PORT_SPEED_MASK) {
1478 ethtool_cmd_speed_set(cmd, SPEED_10);
1480 case PORT_SPEED_100:
1481 ethtool_cmd_speed_set(cmd, SPEED_100);
1483 case PORT_SPEED_1000:
1484 ethtool_cmd_speed_set(cmd, SPEED_1000);
1490 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1491 cmd->port = PORT_MII;
1492 cmd->phy_address = 0;
1493 cmd->transceiver = XCVR_INTERNAL;
1494 cmd->autoneg = AUTONEG_DISABLE;
1502 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1504 struct mv643xx_eth_private *mp = netdev_priv(dev);
1508 phy_ethtool_get_wol(mp->phy, wol);
1512 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1514 struct mv643xx_eth_private *mp = netdev_priv(dev);
1517 if (mp->phy == NULL)
1520 err = phy_ethtool_set_wol(mp->phy, wol);
1521 /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1522 * this debugging hint is useful to have.
1524 if (err == -EOPNOTSUPP)
1525 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1530 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1532 struct mv643xx_eth_private *mp = netdev_priv(dev);
1534 if (mp->phy != NULL)
1535 return mv643xx_eth_get_settings_phy(mp, cmd);
1537 return mv643xx_eth_get_settings_phyless(mp, cmd);
1541 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1543 struct mv643xx_eth_private *mp = netdev_priv(dev);
1546 if (mp->phy == NULL)
1550 * The MAC does not support 1000baseT_Half.
1552 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1554 ret = phy_ethtool_sset(mp->phy, cmd);
1556 mv643xx_eth_adjust_link(dev);
1560 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1561 struct ethtool_drvinfo *drvinfo)
1563 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1564 sizeof(drvinfo->driver));
1565 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1566 sizeof(drvinfo->version));
1567 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1568 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1569 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1572 static int mv643xx_eth_nway_reset(struct net_device *dev)
1574 struct mv643xx_eth_private *mp = netdev_priv(dev);
1576 if (mp->phy == NULL)
1579 return genphy_restart_aneg(mp->phy);
1583 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1585 struct mv643xx_eth_private *mp = netdev_priv(dev);
1587 ec->rx_coalesce_usecs = get_rx_coal(mp);
1588 ec->tx_coalesce_usecs = get_tx_coal(mp);
1594 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1596 struct mv643xx_eth_private *mp = netdev_priv(dev);
1598 set_rx_coal(mp, ec->rx_coalesce_usecs);
1599 set_tx_coal(mp, ec->tx_coalesce_usecs);
1605 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1607 struct mv643xx_eth_private *mp = netdev_priv(dev);
1609 er->rx_max_pending = 4096;
1610 er->tx_max_pending = 4096;
1612 er->rx_pending = mp->rx_ring_size;
1613 er->tx_pending = mp->tx_ring_size;
1617 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1619 struct mv643xx_eth_private *mp = netdev_priv(dev);
1621 if (er->rx_mini_pending || er->rx_jumbo_pending)
1624 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1625 mp->tx_ring_size = clamp_t(unsigned int, er->tx_pending,
1626 MV643XX_MAX_SKB_DESCS * 2, 4096);
1627 if (mp->tx_ring_size != er->tx_pending)
1628 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
1629 mp->tx_ring_size, er->tx_pending);
1631 if (netif_running(dev)) {
1632 mv643xx_eth_stop(dev);
1633 if (mv643xx_eth_open(dev)) {
1635 "fatal error on re-opening device after ring param change\n");
1645 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1647 struct mv643xx_eth_private *mp = netdev_priv(dev);
1648 bool rx_csum = features & NETIF_F_RXCSUM;
1650 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1655 static void mv643xx_eth_get_strings(struct net_device *dev,
1656 uint32_t stringset, uint8_t *data)
1660 if (stringset == ETH_SS_STATS) {
1661 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1662 memcpy(data + i * ETH_GSTRING_LEN,
1663 mv643xx_eth_stats[i].stat_string,
1669 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1670 struct ethtool_stats *stats,
1673 struct mv643xx_eth_private *mp = netdev_priv(dev);
1676 mv643xx_eth_get_stats(dev);
1677 mib_counters_update(mp);
1679 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1680 const struct mv643xx_eth_stats *stat;
1683 stat = mv643xx_eth_stats + i;
1685 if (stat->netdev_off >= 0)
1686 p = ((void *)mp->dev) + stat->netdev_off;
1688 p = ((void *)mp) + stat->mp_off;
1690 data[i] = (stat->sizeof_stat == 8) ?
1691 *(uint64_t *)p : *(uint32_t *)p;
1695 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1697 if (sset == ETH_SS_STATS)
1698 return ARRAY_SIZE(mv643xx_eth_stats);
1703 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1704 .get_settings = mv643xx_eth_get_settings,
1705 .set_settings = mv643xx_eth_set_settings,
1706 .get_drvinfo = mv643xx_eth_get_drvinfo,
1707 .nway_reset = mv643xx_eth_nway_reset,
1708 .get_link = ethtool_op_get_link,
1709 .get_coalesce = mv643xx_eth_get_coalesce,
1710 .set_coalesce = mv643xx_eth_set_coalesce,
1711 .get_ringparam = mv643xx_eth_get_ringparam,
1712 .set_ringparam = mv643xx_eth_set_ringparam,
1713 .get_strings = mv643xx_eth_get_strings,
1714 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1715 .get_sset_count = mv643xx_eth_get_sset_count,
1716 .get_ts_info = ethtool_op_get_ts_info,
1717 .get_wol = mv643xx_eth_get_wol,
1718 .set_wol = mv643xx_eth_set_wol,
1722 /* address handling *********************************************************/
1723 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1725 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1726 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1728 addr[0] = (mac_h >> 24) & 0xff;
1729 addr[1] = (mac_h >> 16) & 0xff;
1730 addr[2] = (mac_h >> 8) & 0xff;
1731 addr[3] = mac_h & 0xff;
1732 addr[4] = (mac_l >> 8) & 0xff;
1733 addr[5] = mac_l & 0xff;
1736 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1738 wrlp(mp, MAC_ADDR_HIGH,
1739 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1740 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1743 static u32 uc_addr_filter_mask(struct net_device *dev)
1745 struct netdev_hw_addr *ha;
1748 if (dev->flags & IFF_PROMISC)
1751 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1752 netdev_for_each_uc_addr(ha, dev) {
1753 if (memcmp(dev->dev_addr, ha->addr, 5))
1755 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1758 nibbles |= 1 << (ha->addr[5] & 0x0f);
1764 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1766 struct mv643xx_eth_private *mp = netdev_priv(dev);
1771 uc_addr_set(mp, dev->dev_addr);
1773 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1775 nibbles = uc_addr_filter_mask(dev);
1777 port_config |= UNICAST_PROMISCUOUS_MODE;
1781 for (i = 0; i < 16; i += 4) {
1782 int off = UNICAST_TABLE(mp->port_num) + i;
1799 wrlp(mp, PORT_CONFIG, port_config);
1802 static int addr_crc(unsigned char *addr)
1807 for (i = 0; i < 6; i++) {
1810 crc = (crc ^ addr[i]) << 8;
1811 for (j = 7; j >= 0; j--) {
1812 if (crc & (0x100 << j))
1820 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1822 struct mv643xx_eth_private *mp = netdev_priv(dev);
1825 struct netdev_hw_addr *ha;
1828 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1833 port_num = mp->port_num;
1834 accept = 0x01010101;
1835 for (i = 0; i < 0x100; i += 4) {
1836 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1837 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1842 mc_spec = kmalloc(0x200, GFP_ATOMIC);
1843 if (mc_spec == NULL)
1845 mc_other = mc_spec + (0x100 >> 2);
1847 memset(mc_spec, 0, 0x100);
1848 memset(mc_other, 0, 0x100);
1850 netdev_for_each_mc_addr(ha, dev) {
1855 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1860 entry = addr_crc(a);
1863 table[entry >> 2] |= 1 << (8 * (entry & 3));
1866 for (i = 0; i < 0x100; i += 4) {
1867 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1868 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1874 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1876 mv643xx_eth_program_unicast_filter(dev);
1877 mv643xx_eth_program_multicast_filter(dev);
1880 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1882 struct sockaddr *sa = addr;
1884 if (!is_valid_ether_addr(sa->sa_data))
1885 return -EADDRNOTAVAIL;
1887 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1889 netif_addr_lock_bh(dev);
1890 mv643xx_eth_program_unicast_filter(dev);
1891 netif_addr_unlock_bh(dev);
1897 /* rx/tx queue initialisation ***********************************************/
1898 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1900 struct rx_queue *rxq = mp->rxq + index;
1901 struct rx_desc *rx_desc;
1907 rxq->rx_ring_size = mp->rx_ring_size;
1909 rxq->rx_desc_count = 0;
1910 rxq->rx_curr_desc = 0;
1911 rxq->rx_used_desc = 0;
1913 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1915 if (index == 0 && size <= mp->rx_desc_sram_size) {
1916 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1917 mp->rx_desc_sram_size);
1918 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1920 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1921 size, &rxq->rx_desc_dma,
1925 if (rxq->rx_desc_area == NULL) {
1927 "can't allocate rx ring (%d bytes)\n", size);
1930 memset(rxq->rx_desc_area, 0, size);
1932 rxq->rx_desc_area_size = size;
1933 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1935 if (rxq->rx_skb == NULL)
1938 rx_desc = rxq->rx_desc_area;
1939 for (i = 0; i < rxq->rx_ring_size; i++) {
1943 if (nexti == rxq->rx_ring_size)
1946 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1947 nexti * sizeof(struct rx_desc);
1954 if (index == 0 && size <= mp->rx_desc_sram_size)
1955 iounmap(rxq->rx_desc_area);
1957 dma_free_coherent(mp->dev->dev.parent, size,
1965 static void rxq_deinit(struct rx_queue *rxq)
1967 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1972 for (i = 0; i < rxq->rx_ring_size; i++) {
1973 if (rxq->rx_skb[i]) {
1974 dev_kfree_skb(rxq->rx_skb[i]);
1975 rxq->rx_desc_count--;
1979 if (rxq->rx_desc_count) {
1980 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
1981 rxq->rx_desc_count);
1984 if (rxq->index == 0 &&
1985 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1986 iounmap(rxq->rx_desc_area);
1988 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
1989 rxq->rx_desc_area, rxq->rx_desc_dma);
1994 static int txq_init(struct mv643xx_eth_private *mp, int index)
1996 struct tx_queue *txq = mp->txq + index;
1997 struct tx_desc *tx_desc;
2003 txq->tx_ring_size = mp->tx_ring_size;
2005 /* A queue must always have room for at least one skb.
2006 * Therefore, stop the queue when the free entries reaches
2007 * the maximum number of descriptors per skb.
2009 txq->tx_stop_threshold = txq->tx_ring_size - MV643XX_MAX_SKB_DESCS;
2010 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2012 txq->tx_desc_count = 0;
2013 txq->tx_curr_desc = 0;
2014 txq->tx_used_desc = 0;
2016 size = txq->tx_ring_size * sizeof(struct tx_desc);
2018 if (index == 0 && size <= mp->tx_desc_sram_size) {
2019 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2020 mp->tx_desc_sram_size);
2021 txq->tx_desc_dma = mp->tx_desc_sram_addr;
2023 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
2024 size, &txq->tx_desc_dma,
2028 if (txq->tx_desc_area == NULL) {
2030 "can't allocate tx ring (%d bytes)\n", size);
2033 memset(txq->tx_desc_area, 0, size);
2035 txq->tx_desc_area_size = size;
2037 tx_desc = txq->tx_desc_area;
2038 for (i = 0; i < txq->tx_ring_size; i++) {
2039 struct tx_desc *txd = tx_desc + i;
2043 if (nexti == txq->tx_ring_size)
2047 txd->next_desc_ptr = txq->tx_desc_dma +
2048 nexti * sizeof(struct tx_desc);
2051 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2052 txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent,
2053 txq->tx_ring_size * TSO_HEADER_SIZE,
2054 &txq->tso_hdrs_dma, GFP_KERNEL);
2055 if (txq->tso_hdrs == NULL) {
2056 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2057 txq->tx_desc_area, txq->tx_desc_dma);
2060 skb_queue_head_init(&txq->tx_skb);
2065 static void txq_deinit(struct tx_queue *txq)
2067 struct mv643xx_eth_private *mp = txq_to_mp(txq);
2070 txq_reclaim(txq, txq->tx_ring_size, 1);
2072 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2074 if (txq->index == 0 &&
2075 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2076 iounmap(txq->tx_desc_area);
2078 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2079 txq->tx_desc_area, txq->tx_desc_dma);
2081 dma_free_coherent(mp->dev->dev.parent,
2082 txq->tx_ring_size * TSO_HEADER_SIZE,
2083 txq->tso_hdrs, txq->tso_hdrs_dma);
2087 /* netdev ops and related ***************************************************/
2088 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2093 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
2098 if (int_cause & INT_EXT) {
2099 int_cause &= ~INT_EXT;
2100 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2104 wrlp(mp, INT_CAUSE, ~int_cause);
2105 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2106 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
2107 mp->work_rx |= (int_cause & INT_RX) >> 2;
2110 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2111 if (int_cause_ext) {
2112 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2113 if (int_cause_ext & INT_EXT_LINK_PHY)
2115 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2121 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2123 struct net_device *dev = (struct net_device *)dev_id;
2124 struct mv643xx_eth_private *mp = netdev_priv(dev);
2126 if (unlikely(!mv643xx_eth_collect_events(mp)))
2129 wrlp(mp, INT_MASK, 0);
2130 napi_schedule(&mp->napi);
2135 static void handle_link_event(struct mv643xx_eth_private *mp)
2137 struct net_device *dev = mp->dev;
2143 port_status = rdlp(mp, PORT_STATUS);
2144 if (!(port_status & LINK_UP)) {
2145 if (netif_carrier_ok(dev)) {
2148 netdev_info(dev, "link down\n");
2150 netif_carrier_off(dev);
2152 for (i = 0; i < mp->txq_count; i++) {
2153 struct tx_queue *txq = mp->txq + i;
2155 txq_reclaim(txq, txq->tx_ring_size, 1);
2156 txq_reset_hw_ptr(txq);
2162 switch (port_status & PORT_SPEED_MASK) {
2166 case PORT_SPEED_100:
2169 case PORT_SPEED_1000:
2176 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2177 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2179 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2180 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2182 if (!netif_carrier_ok(dev))
2183 netif_carrier_on(dev);
2186 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2188 struct mv643xx_eth_private *mp;
2191 mp = container_of(napi, struct mv643xx_eth_private, napi);
2193 if (unlikely(mp->oom)) {
2195 del_timer(&mp->rx_oom);
2199 while (work_done < budget) {
2204 if (mp->work_link) {
2206 handle_link_event(mp);
2211 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2212 if (likely(!mp->oom))
2213 queue_mask |= mp->work_rx_refill;
2216 if (mv643xx_eth_collect_events(mp))
2221 queue = fls(queue_mask) - 1;
2222 queue_mask = 1 << queue;
2224 work_tbd = budget - work_done;
2228 if (mp->work_tx_end & queue_mask) {
2229 txq_kick(mp->txq + queue);
2230 } else if (mp->work_tx & queue_mask) {
2231 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2232 txq_maybe_wake(mp->txq + queue);
2233 } else if (mp->work_rx & queue_mask) {
2234 work_done += rxq_process(mp->rxq + queue, work_tbd);
2235 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2236 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2242 if (work_done < budget) {
2244 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2245 napi_complete(napi);
2246 wrlp(mp, INT_MASK, mp->int_mask);
2252 static inline void oom_timer_wrapper(unsigned long data)
2254 struct mv643xx_eth_private *mp = (void *)data;
2256 napi_schedule(&mp->napi);
2259 static void port_start(struct mv643xx_eth_private *mp)
2265 * Perform PHY reset, if there is a PHY.
2267 if (mp->phy != NULL) {
2268 struct ethtool_cmd cmd;
2270 mv643xx_eth_get_settings(mp->dev, &cmd);
2271 phy_init_hw(mp->phy);
2272 mv643xx_eth_set_settings(mp->dev, &cmd);
2277 * Configure basic link parameters.
2279 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2281 pscr |= SERIAL_PORT_ENABLE;
2282 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2284 pscr |= DO_NOT_FORCE_LINK_FAIL;
2285 if (mp->phy == NULL)
2286 pscr |= FORCE_LINK_PASS;
2287 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2290 * Configure TX path and queues.
2292 tx_set_rate(mp, 1000000000, 16777216);
2293 for (i = 0; i < mp->txq_count; i++) {
2294 struct tx_queue *txq = mp->txq + i;
2296 txq_reset_hw_ptr(txq);
2297 txq_set_rate(txq, 1000000000, 16777216);
2298 txq_set_fixed_prio_mode(txq);
2302 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2303 * frames to RX queue #0, and include the pseudo-header when
2304 * calculating receive checksums.
2306 mv643xx_eth_set_features(mp->dev, mp->dev->features);
2309 * Treat BPDUs as normal multicasts, and disable partition mode.
2311 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2314 * Add configured unicast addresses to address filter table.
2316 mv643xx_eth_program_unicast_filter(mp->dev);
2319 * Enable the receive queues.
2321 for (i = 0; i < mp->rxq_count; i++) {
2322 struct rx_queue *rxq = mp->rxq + i;
2325 addr = (u32)rxq->rx_desc_dma;
2326 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2327 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2333 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2338 * Reserve 2+14 bytes for an ethernet header (the hardware
2339 * automatically prepends 2 bytes of dummy data to each
2340 * received packet), 16 bytes for up to four VLAN tags, and
2341 * 4 bytes for the trailing FCS -- 36 bytes total.
2343 skb_size = mp->dev->mtu + 36;
2346 * Make sure that the skb size is a multiple of 8 bytes, as
2347 * the lower three bits of the receive descriptor's buffer
2348 * size field are ignored by the hardware.
2350 mp->skb_size = (skb_size + 7) & ~7;
2353 * If NET_SKB_PAD is smaller than a cache line,
2354 * netdev_alloc_skb() will cause skb->data to be misaligned
2355 * to a cache line boundary. If this is the case, include
2356 * some extra space to allow re-aligning the data area.
2358 mp->skb_size += SKB_DMA_REALIGN;
2361 static int mv643xx_eth_open(struct net_device *dev)
2363 struct mv643xx_eth_private *mp = netdev_priv(dev);
2367 wrlp(mp, INT_CAUSE, 0);
2368 wrlp(mp, INT_CAUSE_EXT, 0);
2369 rdlp(mp, INT_CAUSE_EXT);
2371 err = request_irq(dev->irq, mv643xx_eth_irq,
2372 IRQF_SHARED, dev->name, dev);
2374 netdev_err(dev, "can't assign irq\n");
2378 mv643xx_eth_recalc_skb_size(mp);
2380 napi_enable(&mp->napi);
2382 mp->int_mask = INT_EXT;
2384 for (i = 0; i < mp->rxq_count; i++) {
2385 err = rxq_init(mp, i);
2388 rxq_deinit(mp->rxq + i);
2392 rxq_refill(mp->rxq + i, INT_MAX);
2393 mp->int_mask |= INT_RX_0 << i;
2397 mp->rx_oom.expires = jiffies + (HZ / 10);
2398 add_timer(&mp->rx_oom);
2401 for (i = 0; i < mp->txq_count; i++) {
2402 err = txq_init(mp, i);
2405 txq_deinit(mp->txq + i);
2408 mp->int_mask |= INT_TX_END_0 << i;
2411 add_timer(&mp->mib_counters_timer);
2414 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2415 wrlp(mp, INT_MASK, mp->int_mask);
2421 for (i = 0; i < mp->rxq_count; i++)
2422 rxq_deinit(mp->rxq + i);
2424 free_irq(dev->irq, dev);
2429 static void port_reset(struct mv643xx_eth_private *mp)
2434 for (i = 0; i < mp->rxq_count; i++)
2435 rxq_disable(mp->rxq + i);
2436 for (i = 0; i < mp->txq_count; i++)
2437 txq_disable(mp->txq + i);
2440 u32 ps = rdlp(mp, PORT_STATUS);
2442 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2447 /* Reset the Enable bit in the Configuration Register */
2448 data = rdlp(mp, PORT_SERIAL_CONTROL);
2449 data &= ~(SERIAL_PORT_ENABLE |
2450 DO_NOT_FORCE_LINK_FAIL |
2452 wrlp(mp, PORT_SERIAL_CONTROL, data);
2455 static int mv643xx_eth_stop(struct net_device *dev)
2457 struct mv643xx_eth_private *mp = netdev_priv(dev);
2460 wrlp(mp, INT_MASK_EXT, 0x00000000);
2461 wrlp(mp, INT_MASK, 0x00000000);
2464 napi_disable(&mp->napi);
2466 del_timer_sync(&mp->rx_oom);
2468 netif_carrier_off(dev);
2471 free_irq(dev->irq, dev);
2474 mv643xx_eth_get_stats(dev);
2475 mib_counters_update(mp);
2476 del_timer_sync(&mp->mib_counters_timer);
2478 for (i = 0; i < mp->rxq_count; i++)
2479 rxq_deinit(mp->rxq + i);
2480 for (i = 0; i < mp->txq_count; i++)
2481 txq_deinit(mp->txq + i);
2486 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2488 struct mv643xx_eth_private *mp = netdev_priv(dev);
2491 if (mp->phy == NULL)
2494 ret = phy_mii_ioctl(mp->phy, ifr, cmd);
2496 mv643xx_eth_adjust_link(dev);
2500 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2502 struct mv643xx_eth_private *mp = netdev_priv(dev);
2504 if (new_mtu < 64 || new_mtu > 9500)
2508 mv643xx_eth_recalc_skb_size(mp);
2509 tx_set_rate(mp, 1000000000, 16777216);
2511 if (!netif_running(dev))
2515 * Stop and then re-open the interface. This will allocate RX
2516 * skbs of the new MTU.
2517 * There is a possible danger that the open will not succeed,
2518 * due to memory being full.
2520 mv643xx_eth_stop(dev);
2521 if (mv643xx_eth_open(dev)) {
2523 "fatal error on re-opening device after MTU change\n");
2529 static void tx_timeout_task(struct work_struct *ugly)
2531 struct mv643xx_eth_private *mp;
2533 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2534 if (netif_running(mp->dev)) {
2535 netif_tx_stop_all_queues(mp->dev);
2538 netif_tx_wake_all_queues(mp->dev);
2542 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2544 struct mv643xx_eth_private *mp = netdev_priv(dev);
2546 netdev_info(dev, "tx timeout\n");
2548 schedule_work(&mp->tx_timeout_task);
2551 #ifdef CONFIG_NET_POLL_CONTROLLER
2552 static void mv643xx_eth_netpoll(struct net_device *dev)
2554 struct mv643xx_eth_private *mp = netdev_priv(dev);
2556 wrlp(mp, INT_MASK, 0x00000000);
2559 mv643xx_eth_irq(dev->irq, dev);
2561 wrlp(mp, INT_MASK, mp->int_mask);
2566 /* platform glue ************************************************************/
2568 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2569 const struct mbus_dram_target_info *dram)
2571 void __iomem *base = msp->base;
2576 for (i = 0; i < 6; i++) {
2577 writel(0, base + WINDOW_BASE(i));
2578 writel(0, base + WINDOW_SIZE(i));
2580 writel(0, base + WINDOW_REMAP_HIGH(i));
2586 for (i = 0; i < dram->num_cs; i++) {
2587 const struct mbus_dram_window *cs = dram->cs + i;
2589 writel((cs->base & 0xffff0000) |
2590 (cs->mbus_attr << 8) |
2591 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2592 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2594 win_enable &= ~(1 << i);
2595 win_protect |= 3 << (2 * i);
2598 writel(win_enable, base + WINDOW_BAR_ENABLE);
2599 msp->win_protect = win_protect;
2602 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2605 * Check whether we have a 14-bit coal limit field in bits
2606 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2607 * SDMA config register.
2609 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2610 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2611 msp->extended_rx_coal_limit = 1;
2613 msp->extended_rx_coal_limit = 0;
2616 * Check whether the MAC supports TX rate control, and if
2617 * yes, whether its associated registers are in the old or
2620 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2621 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2622 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2624 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2625 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2626 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2628 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2632 #if defined(CONFIG_OF)
2633 static const struct of_device_id mv643xx_eth_shared_ids[] = {
2634 { .compatible = "marvell,orion-eth", },
2635 { .compatible = "marvell,kirkwood-eth", },
2638 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids);
2641 #if defined(CONFIG_OF) && !defined(CONFIG_MV64X60)
2642 #define mv643xx_eth_property(_np, _name, _v) \
2645 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \
2649 static struct platform_device *port_platdev[3];
2651 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
2652 struct device_node *pnp)
2654 struct platform_device *ppdev;
2655 struct mv643xx_eth_platform_data ppd;
2656 struct resource res;
2657 const char *mac_addr;
2661 memset(&ppd, 0, sizeof(ppd));
2664 memset(&res, 0, sizeof(res));
2665 if (!of_irq_to_resource(pnp, 0, &res)) {
2666 dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name);
2670 if (of_property_read_u32(pnp, "reg", &ppd.port_number)) {
2671 dev_err(&pdev->dev, "missing reg property on %s\n", pnp->name);
2675 if (ppd.port_number >= 3) {
2676 dev_err(&pdev->dev, "invalid reg property on %s\n", pnp->name);
2680 while (dev_num < 3 && port_platdev[dev_num])
2684 dev_err(&pdev->dev, "too many ports registered\n");
2688 mac_addr = of_get_mac_address(pnp);
2690 memcpy(ppd.mac_addr, mac_addr, ETH_ALEN);
2692 mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size);
2693 mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr);
2694 mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size);
2695 mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size);
2696 mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr);
2697 mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size);
2699 ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0);
2700 if (!ppd.phy_node) {
2701 ppd.phy_addr = MV643XX_ETH_PHY_NONE;
2702 of_property_read_u32(pnp, "speed", &ppd.speed);
2703 of_property_read_u32(pnp, "duplex", &ppd.duplex);
2706 ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num);
2709 ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
2710 ppdev->dev.of_node = pnp;
2712 ret = platform_device_add_resources(ppdev, &res, 1);
2716 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
2720 ret = platform_device_add(ppdev);
2724 port_platdev[dev_num] = ppdev;
2729 platform_device_put(ppdev);
2733 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2735 struct mv643xx_eth_shared_platform_data *pd;
2736 struct device_node *pnp, *np = pdev->dev.of_node;
2739 /* bail out if not registered from DT */
2743 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
2746 pdev->dev.platform_data = pd;
2748 mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit);
2750 for_each_available_child_of_node(np, pnp) {
2751 ret = mv643xx_eth_shared_of_add_port(pdev, pnp);
2758 static void mv643xx_eth_shared_of_remove(void)
2762 for (n = 0; n < 3; n++) {
2763 platform_device_del(port_platdev[n]);
2764 port_platdev[n] = NULL;
2768 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2773 static inline void mv643xx_eth_shared_of_remove(void)
2778 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2780 static int mv643xx_eth_version_printed;
2781 struct mv643xx_eth_shared_platform_data *pd;
2782 struct mv643xx_eth_shared_private *msp;
2783 const struct mbus_dram_target_info *dram;
2784 struct resource *res;
2787 if (!mv643xx_eth_version_printed++)
2788 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2789 mv643xx_eth_driver_version);
2791 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2795 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
2798 platform_set_drvdata(pdev, msp);
2800 msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
2801 if (msp->base == NULL)
2804 msp->clk = devm_clk_get(&pdev->dev, NULL);
2805 if (!IS_ERR(msp->clk))
2806 clk_prepare_enable(msp->clk);
2809 * (Re-)program MBUS remapping windows if we are asked to.
2811 dram = mv_mbus_dram_info();
2813 mv643xx_eth_conf_mbus_windows(msp, dram);
2815 ret = mv643xx_eth_shared_of_probe(pdev);
2818 pd = dev_get_platdata(&pdev->dev);
2820 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2821 pd->tx_csum_limit : 9 * 1024;
2822 infer_hw_params(msp);
2827 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2829 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2831 mv643xx_eth_shared_of_remove();
2832 if (!IS_ERR(msp->clk))
2833 clk_disable_unprepare(msp->clk);
2837 static struct platform_driver mv643xx_eth_shared_driver = {
2838 .probe = mv643xx_eth_shared_probe,
2839 .remove = mv643xx_eth_shared_remove,
2841 .name = MV643XX_ETH_SHARED_NAME,
2842 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids),
2846 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2848 int addr_shift = 5 * mp->port_num;
2851 data = rdl(mp, PHY_ADDR);
2852 data &= ~(0x1f << addr_shift);
2853 data |= (phy_addr & 0x1f) << addr_shift;
2854 wrl(mp, PHY_ADDR, data);
2857 static int phy_addr_get(struct mv643xx_eth_private *mp)
2861 data = rdl(mp, PHY_ADDR);
2863 return (data >> (5 * mp->port_num)) & 0x1f;
2866 static void set_params(struct mv643xx_eth_private *mp,
2867 struct mv643xx_eth_platform_data *pd)
2869 struct net_device *dev = mp->dev;
2870 unsigned int tx_ring_size;
2872 if (is_valid_ether_addr(pd->mac_addr))
2873 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2875 uc_addr_get(mp, dev->dev_addr);
2877 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2878 if (pd->rx_queue_size)
2879 mp->rx_ring_size = pd->rx_queue_size;
2880 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2881 mp->rx_desc_sram_size = pd->rx_sram_size;
2883 mp->rxq_count = pd->rx_queue_count ? : 1;
2885 tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2886 if (pd->tx_queue_size)
2887 tx_ring_size = pd->tx_queue_size;
2889 mp->tx_ring_size = clamp_t(unsigned int, tx_ring_size,
2890 MV643XX_MAX_SKB_DESCS * 2, 4096);
2891 if (mp->tx_ring_size != tx_ring_size)
2892 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
2893 mp->tx_ring_size, tx_ring_size);
2895 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2896 mp->tx_desc_sram_size = pd->tx_sram_size;
2898 mp->txq_count = pd->tx_queue_count ? : 1;
2901 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2904 struct phy_device *phydev;
2908 char phy_id[MII_BUS_ID_SIZE + 3];
2910 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2911 start = phy_addr_get(mp) & 0x1f;
2914 start = phy_addr & 0x1f;
2918 /* Attempt to connect to the PHY using orion-mdio */
2919 phydev = ERR_PTR(-ENODEV);
2920 for (i = 0; i < num; i++) {
2921 int addr = (start + i) & 0x1f;
2923 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2924 "orion-mdio-mii", addr);
2926 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
2927 PHY_INTERFACE_MODE_GMII);
2928 if (!IS_ERR(phydev)) {
2929 phy_addr_set(mp, addr);
2937 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2939 struct phy_device *phy = mp->phy;
2942 phy->autoneg = AUTONEG_ENABLE;
2945 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2947 phy->autoneg = AUTONEG_DISABLE;
2948 phy->advertising = 0;
2950 phy->duplex = duplex;
2952 phy_start_aneg(phy);
2955 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2959 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2960 if (pscr & SERIAL_PORT_ENABLE) {
2961 pscr &= ~SERIAL_PORT_ENABLE;
2962 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2965 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2966 if (mp->phy == NULL) {
2967 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2968 if (speed == SPEED_1000)
2969 pscr |= SET_GMII_SPEED_TO_1000;
2970 else if (speed == SPEED_100)
2971 pscr |= SET_MII_SPEED_TO_100;
2973 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2975 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2976 if (duplex == DUPLEX_FULL)
2977 pscr |= SET_FULL_DUPLEX_MODE;
2980 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2983 static const struct net_device_ops mv643xx_eth_netdev_ops = {
2984 .ndo_open = mv643xx_eth_open,
2985 .ndo_stop = mv643xx_eth_stop,
2986 .ndo_start_xmit = mv643xx_eth_xmit,
2987 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2988 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2989 .ndo_validate_addr = eth_validate_addr,
2990 .ndo_do_ioctl = mv643xx_eth_ioctl,
2991 .ndo_change_mtu = mv643xx_eth_change_mtu,
2992 .ndo_set_features = mv643xx_eth_set_features,
2993 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2994 .ndo_get_stats = mv643xx_eth_get_stats,
2995 #ifdef CONFIG_NET_POLL_CONTROLLER
2996 .ndo_poll_controller = mv643xx_eth_netpoll,
3000 static int mv643xx_eth_probe(struct platform_device *pdev)
3002 struct mv643xx_eth_platform_data *pd;
3003 struct mv643xx_eth_private *mp;
3004 struct net_device *dev;
3005 struct resource *res;
3008 pd = dev_get_platdata(&pdev->dev);
3010 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
3014 if (pd->shared == NULL) {
3015 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
3019 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
3023 mp = netdev_priv(dev);
3024 platform_set_drvdata(pdev, mp);
3026 mp->shared = platform_get_drvdata(pd->shared);
3027 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
3028 mp->port_num = pd->port_number;
3032 /* Kirkwood resets some registers on gated clocks. Especially
3033 * CLK125_BYPASS_EN must be cleared but is not available on
3034 * all other SoCs/System Controllers using this driver.
3036 if (of_device_is_compatible(pdev->dev.of_node,
3037 "marvell,kirkwood-eth-port"))
3038 wrlp(mp, PORT_SERIAL_CONTROL1,
3039 rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
3042 * Start with a default rate, and if there is a clock, allow
3043 * it to override the default.
3045 mp->t_clk = 133000000;
3046 mp->clk = devm_clk_get(&pdev->dev, NULL);
3047 if (!IS_ERR(mp->clk)) {
3048 clk_prepare_enable(mp->clk);
3049 mp->t_clk = clk_get_rate(mp->clk);
3050 } else if (!IS_ERR(mp->shared->clk)) {
3051 mp->t_clk = clk_get_rate(mp->shared->clk);
3055 netif_set_real_num_tx_queues(dev, mp->txq_count);
3056 netif_set_real_num_rx_queues(dev, mp->rxq_count);
3060 mp->phy = of_phy_connect(mp->dev, pd->phy_node,
3061 mv643xx_eth_adjust_link, 0,
3062 PHY_INTERFACE_MODE_GMII);
3066 phy_addr_set(mp, mp->phy->addr);
3067 } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
3068 mp->phy = phy_scan(mp, pd->phy_addr);
3070 if (IS_ERR(mp->phy))
3071 err = PTR_ERR(mp->phy);
3073 phy_init(mp, pd->speed, pd->duplex);
3075 if (err == -ENODEV) {
3076 err = -EPROBE_DEFER;
3082 dev->ethtool_ops = &mv643xx_eth_ethtool_ops;
3084 init_pscr(mp, pd->speed, pd->duplex);
3087 mib_counters_clear(mp);
3089 init_timer(&mp->mib_counters_timer);
3090 mp->mib_counters_timer.data = (unsigned long)mp;
3091 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
3092 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
3094 spin_lock_init(&mp->mib_counters_lock);
3096 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
3098 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
3100 init_timer(&mp->rx_oom);
3101 mp->rx_oom.data = (unsigned long)mp;
3102 mp->rx_oom.function = oom_timer_wrapper;
3105 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
3107 dev->irq = res->start;
3109 dev->netdev_ops = &mv643xx_eth_netdev_ops;
3111 dev->watchdog_timeo = 2 * HZ;
3114 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3115 dev->vlan_features = dev->features;
3117 dev->features |= NETIF_F_RXCSUM;
3118 dev->hw_features = dev->features;
3120 dev->priv_flags |= IFF_UNICAST_FLT;
3121 dev->gso_max_segs = MV643XX_MAX_TSO_SEGS;
3123 SET_NETDEV_DEV(dev, &pdev->dev);
3125 if (mp->shared->win_protect)
3126 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
3128 netif_carrier_off(dev);
3130 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
3132 set_rx_coal(mp, 250);
3135 err = register_netdev(dev);
3139 netdev_notice(dev, "port %d with MAC address %pM\n",
3140 mp->port_num, dev->dev_addr);
3142 if (mp->tx_desc_sram_size > 0)
3143 netdev_notice(dev, "configured with sram\n");
3148 if (!IS_ERR(mp->clk))
3149 clk_disable_unprepare(mp->clk);
3155 static int mv643xx_eth_remove(struct platform_device *pdev)
3157 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3159 unregister_netdev(mp->dev);
3160 if (mp->phy != NULL)
3161 phy_disconnect(mp->phy);
3162 cancel_work_sync(&mp->tx_timeout_task);
3164 if (!IS_ERR(mp->clk))
3165 clk_disable_unprepare(mp->clk);
3167 free_netdev(mp->dev);
3172 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3174 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3176 /* Mask all interrupts on ethernet port */
3177 wrlp(mp, INT_MASK, 0);
3180 if (netif_running(mp->dev))
3184 static struct platform_driver mv643xx_eth_driver = {
3185 .probe = mv643xx_eth_probe,
3186 .remove = mv643xx_eth_remove,
3187 .shutdown = mv643xx_eth_shutdown,
3189 .name = MV643XX_ETH_NAME,
3193 static int __init mv643xx_eth_init_module(void)
3197 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3199 rc = platform_driver_register(&mv643xx_eth_driver);
3201 platform_driver_unregister(&mv643xx_eth_shared_driver);
3206 module_init(mv643xx_eth_init_module);
3208 static void __exit mv643xx_eth_cleanup_module(void)
3210 platform_driver_unregister(&mv643xx_eth_driver);
3211 platform_driver_unregister(&mv643xx_eth_shared_driver);
3213 module_exit(mv643xx_eth_cleanup_module);
3215 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3216 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3217 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3218 MODULE_LICENSE("GPL");
3219 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3220 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);