1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/export.h>
29 #include <linux/ptp_classify.h>
32 * The 82599 and the X540 do not have true 64bit nanosecond scale
33 * counter registers. Instead, SYSTIME is defined by a fixed point
34 * system which allows the user to define the scale counter increment
35 * value at every level change of the oscillator driving the SYSTIME
36 * value. For both devices the TIMINCA:IV field defines this
37 * increment. On the X540 device, 31 bits are provided. However on the
38 * 82599 only provides 24 bits. The time unit is determined by the
39 * clock frequency of the oscillator in combination with the TIMINCA
40 * register. When these devices link at 10Gb the oscillator has a
41 * period of 6.4ns. In order to convert the scale counter into
42 * nanoseconds the cyclecounter and timecounter structures are
43 * used. The SYSTIME registers need to be converted to ns values by use
44 * of only a right shift (division by power of 2). The following math
45 * determines the largest incvalue that will fit into the available
46 * bits in the TIMINCA register.
48 * PeriodWidth: Number of bits to store the clock period
49 * MaxWidth: The maximum width value of the TIMINCA register
50 * Period: The clock period for the oscillator
51 * round(): discard the fractional portion of the calculation
53 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
55 * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns
56 * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns
58 * The period also changes based on the link speed:
59 * At 10Gb link or no link, the period remains the same.
60 * At 1Gb link, the period is multiplied by 10. (64ns)
61 * At 100Mb link, the period is multiplied by 100. (640ns)
63 * The calculated value allows us to right shift the SYSTIME register
64 * value in order to quickly convert it into a nanosecond clock,
65 * while allowing for the maximum possible adjustment value.
67 * These diagrams are only for the 10Gb link period
70 * +--------------+ +--------------+
71 * X540 | 32 | | 1 | 3 | 28 |
72 * *--------------+ +--------------+
73 * \________ 36 bits ______/ fract
75 * +--------------+ +--------------+
76 * 82599 | 32 | | 8 | 3 | 21 |
77 * *--------------+ +--------------+
78 * \________ 43 bits ______/ fract
80 * The 36 bit X540 SYSTIME overflows every
81 * 2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
83 * The 43 bit 82599 SYSTIME overflows every
84 * 2^43 * 10^-9 / 3600 = 2.4 hours
86 #define IXGBE_INCVAL_10GB 0x66666666
87 #define IXGBE_INCVAL_1GB 0x40000000
88 #define IXGBE_INCVAL_100 0x50000000
90 #define IXGBE_INCVAL_SHIFT_10GB 28
91 #define IXGBE_INCVAL_SHIFT_1GB 24
92 #define IXGBE_INCVAL_SHIFT_100 21
94 #define IXGBE_INCVAL_SHIFT_82599 7
95 #define IXGBE_INCPER_SHIFT_82599 24
96 #define IXGBE_MAX_TIMEADJ_VALUE 0x7FFFFFFFFFFFFFFFULL
98 #define IXGBE_OVERFLOW_PERIOD (HZ * 30)
100 #ifndef NSECS_PER_SEC
101 #define NSECS_PER_SEC 1000000000ULL
104 static struct sock_filter ptp_filter[] = {
109 * ixgbe_ptp_setup_sdp
110 * @hw: the hardware private structure
112 * this function enables or disables the clock out feature on SDP0 for
113 * the X540 device. It will create a 1second periodic output that can
114 * be used as the PPS (via an interrupt).
116 * It calculates when the systime will be on an exact second, and then
117 * aligns the start of the PPS signal to that value. The shift is
118 * necessary because it can change based on the link speed.
120 static void ixgbe_ptp_setup_sdp(struct ixgbe_adapter *adapter)
122 struct ixgbe_hw *hw = &adapter->hw;
123 int shift = adapter->cc.shift;
124 u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
125 u64 ns = 0, clock_edge = 0;
127 if ((adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED) &&
128 (hw->mac.type == ixgbe_mac_X540)) {
130 /* disable the pin first */
131 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
132 IXGBE_WRITE_FLUSH(hw);
134 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
137 * enable the SDP0 pin as output, and connected to the
138 * native function for Timesync (ClockOut)
140 esdp |= (IXGBE_ESDP_SDP0_DIR |
141 IXGBE_ESDP_SDP0_NATIVE);
144 * enable the Clock Out feature on SDP0, and allow
145 * interrupts to occur when the pin changes
147 tsauxc = (IXGBE_TSAUXC_EN_CLK |
148 IXGBE_TSAUXC_SYNCLK |
149 IXGBE_TSAUXC_SDP0_INT);
151 /* clock period (or pulse length) */
152 clktiml = (u32)(NSECS_PER_SEC << shift);
153 clktimh = (u32)((NSECS_PER_SEC << shift) >> 32);
156 * Account for the cyclecounter wrap-around value by
157 * using the converted ns value of the current time to
158 * check for when the next aligned second would occur.
160 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
161 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
162 ns = timecounter_cyc2time(&adapter->tc, clock_edge);
164 div_u64_rem(ns, NSECS_PER_SEC, &rem);
165 clock_edge += ((NSECS_PER_SEC - (u64)rem) << shift);
167 /* specify the initial clock start time */
168 trgttiml = (u32)clock_edge;
169 trgttimh = (u32)(clock_edge >> 32);
171 IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
172 IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
173 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
174 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
176 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
177 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
179 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
182 IXGBE_WRITE_FLUSH(hw);
186 * ixgbe_ptp_read - read raw cycle counter (to be used by time counter)
187 * @cc: the cyclecounter structure
189 * this function reads the cyclecounter registers and is called by the
190 * cyclecounter structure used to construct a ns counter from the
191 * arbitrary fixed point registers
193 static cycle_t ixgbe_ptp_read(const struct cyclecounter *cc)
195 struct ixgbe_adapter *adapter =
196 container_of(cc, struct ixgbe_adapter, cc);
197 struct ixgbe_hw *hw = &adapter->hw;
200 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
201 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
208 * @ptp: the ptp clock structure
209 * @ppb: parts per billion adjustment from base
211 * adjust the frequency of the ptp cycle counter by the
212 * indicated ppb from the base frequency.
214 static int ixgbe_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
216 struct ixgbe_adapter *adapter =
217 container_of(ptp, struct ixgbe_adapter, ptp_caps);
218 struct ixgbe_hw *hw = &adapter->hw;
229 incval = ACCESS_ONCE(adapter->base_incval);
233 diff = div_u64(freq, 1000000000ULL);
235 incval = neg_adj ? (incval - diff) : (incval + diff);
237 switch (hw->mac.type) {
239 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
241 case ixgbe_mac_82599EB:
242 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
243 (1 << IXGBE_INCPER_SHIFT_82599) |
255 * @ptp: the ptp clock structure
256 * @delta: offset to adjust the cycle counter by
258 * adjust the timer by resetting the timecounter structure.
260 static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
262 struct ixgbe_adapter *adapter =
263 container_of(ptp, struct ixgbe_adapter, ptp_caps);
267 spin_lock_irqsave(&adapter->tmreg_lock, flags);
269 now = timecounter_read(&adapter->tc);
272 /* reset the timecounter */
273 timecounter_init(&adapter->tc,
277 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
279 ixgbe_ptp_setup_sdp(adapter);
286 * @ptp: the ptp clock structure
287 * @ts: timespec structure to hold the current time value
289 * read the timecounter and return the correct value on ns,
290 * after converting it into a struct timespec.
292 static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
294 struct ixgbe_adapter *adapter =
295 container_of(ptp, struct ixgbe_adapter, ptp_caps);
300 spin_lock_irqsave(&adapter->tmreg_lock, flags);
301 ns = timecounter_read(&adapter->tc);
302 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
304 ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
305 ts->tv_nsec = remainder;
312 * @ptp: the ptp clock structure
313 * @ts: the timespec containing the new time for the cycle counter
315 * reset the timecounter to use a new base value instead of the kernel
318 static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
319 const struct timespec *ts)
321 struct ixgbe_adapter *adapter =
322 container_of(ptp, struct ixgbe_adapter, ptp_caps);
326 ns = ts->tv_sec * 1000000000ULL;
329 /* reset the timecounter */
330 spin_lock_irqsave(&adapter->tmreg_lock, flags);
331 timecounter_init(&adapter->tc, &adapter->cc, ns);
332 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
334 ixgbe_ptp_setup_sdp(adapter);
340 * @ptp: the ptp clock structure
341 * @rq: the requested feature to change
342 * @on: whether to enable or disable the feature
344 * enable (or disable) ancillary features of the phc subsystem.
345 * our driver only supports the PPS feature on the X540
347 static int ixgbe_ptp_enable(struct ptp_clock_info *ptp,
348 struct ptp_clock_request *rq, int on)
350 struct ixgbe_adapter *adapter =
351 container_of(ptp, struct ixgbe_adapter, ptp_caps);
354 * When PPS is enabled, unmask the interrupt for the ClockOut
355 * feature, so that the interrupt handler can send the PPS
356 * event when the clock SDP triggers. Clear mask when PPS is
359 if (rq->type == PTP_CLK_REQ_PPS) {
360 switch (adapter->hw.mac.type) {
363 adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
365 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
367 ixgbe_ptp_setup_sdp(adapter);
378 * ixgbe_ptp_check_pps_event
379 * @adapter: the private adapter structure
380 * @eicr: the interrupt cause register value
382 * This function is called by the interrupt routine when checking for
383 * interrupts. It will check and handle a pps event.
385 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr)
387 struct ixgbe_hw *hw = &adapter->hw;
388 struct ptp_clock_event event;
390 event.type = PTP_CLOCK_PPS;
392 /* this check is necessary in case the interrupt was enabled via some
393 * alternative means (ex. debug_fs). Better to check here than
394 * everywhere that calls this function.
396 if (!adapter->ptp_clock)
399 switch (hw->mac.type) {
401 ptp_clock_event(adapter->ptp_clock, &event);
410 * ixgbe_ptp_overflow_check - delayed work to detect SYSTIME overflow
411 * @work: structure containing information about this work task
413 * this work function is scheduled to continue reading the timecounter
414 * in order to prevent missing when the system time registers wrap
415 * around. This needs to be run approximately twice a minute when no
416 * PTP activity is occurring.
418 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter)
420 unsigned long elapsed_jiffies = adapter->last_overflow_check - jiffies;
423 if ((adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED) &&
424 (elapsed_jiffies >= IXGBE_OVERFLOW_PERIOD)) {
425 ixgbe_ptp_gettime(&adapter->ptp_caps, &ts);
426 adapter->last_overflow_check = jiffies;
431 * ixgbe_ptp_match - determine if this skb matches a ptp packet
432 * @skb: pointer to the skb
433 * @hwtstamp: pointer to the hwtstamp_config to check
435 * Determine whether the skb should have been timestamped, assuming the
436 * hwtstamp was set via the hwtstamp ioctl. Returns non-zero when the packet
437 * should have a timestamp waiting in the registers, and 0 otherwise.
439 * V1 packets have to check the version type to determine whether they are
440 * correct. However, we can't directly access the data because it might be
441 * fragmented in the SKB, in paged memory. In order to work around this, we
442 * use skb_copy_bits which will properly copy the data whether it is in the
443 * paged memory fragments or not. We have to copy the IP header as well as the
446 static int ixgbe_ptp_match(struct sk_buff *skb, int rx_filter)
450 unsigned int type, offset;
452 if (rx_filter == HWTSTAMP_FILTER_NONE)
455 type = sk_run_filter(skb, ptp_filter);
457 if (likely(rx_filter == HWTSTAMP_FILTER_PTP_V2_EVENT))
458 return type & PTP_CLASS_V2;
460 /* For the remaining cases actually check message type */
462 case PTP_CLASS_V1_IPV4:
463 skb_copy_bits(skb, OFF_IHL, &iph, sizeof(iph));
464 offset = ETH_HLEN + (iph.ihl << 2) + UDP_HLEN + OFF_PTP_CONTROL;
466 case PTP_CLASS_V1_IPV6:
467 offset = OFF_PTP6 + OFF_PTP_CONTROL;
470 /* other cases invalid or handled above */
474 /* Make sure our buffer is long enough */
475 if (skb->len < offset)
478 skb_copy_bits(skb, offset, &msgtype, sizeof(msgtype));
481 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
482 return (msgtype == IXGBE_RXMTRL_V1_SYNC_MSG);
484 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
485 return (msgtype == IXGBE_RXMTRL_V1_DELAY_REQ_MSG);
493 * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp
494 * @q_vector: structure containing interrupt and ring information
495 * @skb: particular skb to send timestamp with
497 * if the timestamp is valid, we convert it into the timecounter ns
498 * value, then store that result into the shhwtstamps structure which
499 * is passed up the network stack
501 void ixgbe_ptp_tx_hwtstamp(struct ixgbe_q_vector *q_vector,
504 struct ixgbe_adapter *adapter;
506 struct skb_shared_hwtstamps shhwtstamps;
511 /* we cannot process timestamps on a ring without a q_vector */
512 if (!q_vector || !q_vector->adapter)
515 adapter = q_vector->adapter;
518 tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
519 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
520 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
523 * if TX timestamp is not valid, exit after clearing the
524 * timestamp registers
526 if (!(tsynctxctl & IXGBE_TSYNCTXCTL_VALID))
529 spin_lock_irqsave(&adapter->tmreg_lock, flags);
530 ns = timecounter_cyc2time(&adapter->tc, regval);
531 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
533 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
534 shhwtstamps.hwtstamp = ns_to_ktime(ns);
535 skb_tstamp_tx(skb, &shhwtstamps);
539 * ixgbe_ptp_rx_hwtstamp - utility function which checks for RX time stamp
540 * @q_vector: structure containing interrupt and ring information
541 * @rx_desc: the rx descriptor
542 * @skb: particular skb to send timestamp with
544 * if the timestamp is valid, we convert it into the timecounter ns
545 * value, then store that result into the shhwtstamps structure which
546 * is passed up the network stack
548 void ixgbe_ptp_rx_hwtstamp(struct ixgbe_q_vector *q_vector,
549 union ixgbe_adv_rx_desc *rx_desc,
552 struct ixgbe_adapter *adapter;
554 struct skb_shared_hwtstamps *shhwtstamps;
559 /* we cannot process timestamps on a ring without a q_vector */
560 if (!q_vector || !q_vector->adapter)
563 adapter = q_vector->adapter;
566 if (likely(!ixgbe_ptp_match(skb, adapter->rx_hwtstamp_filter)))
569 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
571 /* Check if we have a valid timestamp and make sure the skb should
572 * have been timestamped */
573 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID))
577 * Always read the registers, in order to clear a possible fault
578 * because of stagnant RX timestamp values for a packet that never
581 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
582 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
585 * If the timestamp bit is set in the packet's descriptor, we know the
586 * timestamp belongs to this packet. No other packet can be
587 * timestamped until the registers for timestamping have been read.
588 * Therefor only one packet with this bit can be in the queue at a
589 * time, and the rx timestamp values that were in the registers belong
592 * If nothing went wrong, then it should have a skb_shared_tx that we
593 * can turn into a skb_shared_hwtstamps.
595 if (unlikely(!ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
598 spin_lock_irqsave(&adapter->tmreg_lock, flags);
599 ns = timecounter_cyc2time(&adapter->tc, regval);
600 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
602 shhwtstamps = skb_hwtstamps(skb);
603 shhwtstamps->hwtstamp = ns_to_ktime(ns);
607 * ixgbe_ptp_hwtstamp_ioctl - control hardware time stamping
608 * @adapter: pointer to adapter struct
610 * @cmd: particular ioctl requested
612 * Outgoing time stamping can be enabled and disabled. Play nice and
613 * disable it when requested, although it shouldn't case any overhead
614 * when no packet needs it. At most one packet in the queue may be
615 * marked for time stamping, otherwise it would be impossible to tell
616 * for sure to which packet the hardware time stamp belongs.
618 * Incoming time stamping has to be configured via the hardware
619 * filters. Not all combinations are supported, in particular event
620 * type has to be specified. Matching the kind of event packet is
621 * not supported, with the exception of "all V2 events regardless of
624 * Since hardware always timestamps Path delay packets when timestamping V2
625 * packets, regardless of the type specified in the register, only use V2
626 * Event mode. This more accurately tells the user what the hardware is going
629 int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter,
630 struct ifreq *ifr, int cmd)
632 struct ixgbe_hw *hw = &adapter->hw;
633 struct hwtstamp_config config;
634 u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
635 u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
636 u32 tsync_rx_mtrl = PTP_EV_PORT << 16;
640 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
643 /* reserved for future extensions */
647 switch (config.tx_type) {
648 case HWTSTAMP_TX_OFF:
656 switch (config.rx_filter) {
657 case HWTSTAMP_FILTER_NONE:
661 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
662 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
663 tsync_rx_mtrl = IXGBE_RXMTRL_V1_SYNC_MSG;
665 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
666 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
667 tsync_rx_mtrl = IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
669 case HWTSTAMP_FILTER_PTP_V2_EVENT:
670 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
671 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
672 case HWTSTAMP_FILTER_PTP_V2_SYNC:
673 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
674 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
675 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
676 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
677 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
678 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
680 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
682 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
683 case HWTSTAMP_FILTER_ALL:
686 * register RXMTRL must be set in order to do V1 packets,
687 * therefore it is not possible to time stamp both V1 Sync and
688 * Delay_Req messages and hardware does not support
689 * timestamping all packets => return error
691 config.rx_filter = HWTSTAMP_FILTER_NONE;
695 if (hw->mac.type == ixgbe_mac_82598EB) {
696 if (tsync_rx_ctl | tsync_tx_ctl)
701 /* Store filter value for later use */
702 adapter->rx_hwtstamp_filter = config.rx_filter;
704 /* define ethertype filter for timestamping L2 packets */
706 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
707 (IXGBE_ETQF_FILTER_EN | /* enable filter */
708 IXGBE_ETQF_1588 | /* enable timestamping */
709 ETH_P_1588)); /* 1588 eth protocol type */
711 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
714 /* enable/disable TX */
715 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
716 regval &= ~IXGBE_TSYNCTXCTL_ENABLED;
717 regval |= tsync_tx_ctl;
718 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);
720 /* enable/disable RX */
721 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
722 regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);
723 regval |= tsync_rx_ctl;
724 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);
726 /* define which PTP packets are time stamped */
727 IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl);
729 IXGBE_WRITE_FLUSH(hw);
731 /* clear TX/RX time stamp registers, just to be sure */
732 regval = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
733 regval = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
735 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
740 * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw
741 * @adapter: pointer to the adapter structure
743 * This function should be called to set the proper values for the TIMINCA
744 * register and tell the cyclecounter structure what the tick rate of SYSTIME
745 * is. It does not directly modify SYSTIME registers or the timecounter
746 * structure. It should be called whenever a new TIMINCA value is necessary,
747 * such as during initialization or when the link speed changes.
749 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
751 struct ixgbe_hw *hw = &adapter->hw;
757 * Scale the NIC cycle counter by a large factor so that
758 * relatively small corrections to the frequency can be added
759 * or subtracted. The drawbacks of a large factor include
760 * (a) the clock register overflows more quickly, (b) the cycle
761 * counter structure must be able to convert the systime value
762 * to nanoseconds using only a multiplier and a right-shift,
763 * and (c) the value must fit within the timinca register space
764 * => math based on internal DMA clock rate and available bits
766 * Note that when there is no link, internal DMA clock is same as when
767 * link speed is 10Gb. Set the registers correctly even when link is
768 * down to preserve the clock setting
770 switch (adapter->link_speed) {
771 case IXGBE_LINK_SPEED_100_FULL:
772 incval = IXGBE_INCVAL_100;
773 shift = IXGBE_INCVAL_SHIFT_100;
775 case IXGBE_LINK_SPEED_1GB_FULL:
776 incval = IXGBE_INCVAL_1GB;
777 shift = IXGBE_INCVAL_SHIFT_1GB;
779 case IXGBE_LINK_SPEED_10GB_FULL:
781 incval = IXGBE_INCVAL_10GB;
782 shift = IXGBE_INCVAL_SHIFT_10GB;
787 * Modify the calculated values to fit within the correct
788 * number of bits specified by the hardware. The 82599 doesn't
789 * have the same space as the X540, so bitshift the calculated
792 switch (hw->mac.type) {
794 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
796 case ixgbe_mac_82599EB:
797 incval >>= IXGBE_INCVAL_SHIFT_82599;
798 shift -= IXGBE_INCVAL_SHIFT_82599;
799 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
800 (1 << IXGBE_INCPER_SHIFT_82599) |
804 /* other devices aren't supported */
808 /* update the base incval used to calculate frequency adjustment */
809 ACCESS_ONCE(adapter->base_incval) = incval;
812 /* need lock to prevent incorrect read while modifying cyclecounter */
813 spin_lock_irqsave(&adapter->tmreg_lock, flags);
815 memset(&adapter->cc, 0, sizeof(adapter->cc));
816 adapter->cc.read = ixgbe_ptp_read;
817 adapter->cc.mask = CLOCKSOURCE_MASK(64);
818 adapter->cc.shift = shift;
819 adapter->cc.mult = 1;
821 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
826 * @adapter: the ixgbe private board structure
828 * When the MAC resets, all timesync features are reset. This function should be
829 * called to re-enable the PTP clock structure. It will re-init the timecounter
830 * structure based on the kernel time as well as setup the cycle counter data.
832 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter)
834 struct ixgbe_hw *hw = &adapter->hw;
837 /* set SYSTIME registers to 0 just in case */
838 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x00000000);
839 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x00000000);
840 IXGBE_WRITE_FLUSH(hw);
842 ixgbe_ptp_start_cyclecounter(adapter);
844 spin_lock_irqsave(&adapter->tmreg_lock, flags);
846 /* reset the ns time counter */
847 timecounter_init(&adapter->tc, &adapter->cc,
848 ktime_to_ns(ktime_get_real()));
850 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
853 * Now that the shift has been calculated and the systime
854 * registers reset, (re-)enable the Clock out feature
856 ixgbe_ptp_setup_sdp(adapter);
861 * @adapter: the ixgbe private adapter structure
863 * This function performs the required steps for enabling ptp
864 * support. If ptp support has already been loaded it simply calls the
865 * cyclecounter init routine and exits.
867 void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
869 struct net_device *netdev = adapter->netdev;
871 switch (adapter->hw.mac.type) {
873 snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name);
874 adapter->ptp_caps.owner = THIS_MODULE;
875 adapter->ptp_caps.max_adj = 250000000;
876 adapter->ptp_caps.n_alarm = 0;
877 adapter->ptp_caps.n_ext_ts = 0;
878 adapter->ptp_caps.n_per_out = 0;
879 adapter->ptp_caps.pps = 1;
880 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
881 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
882 adapter->ptp_caps.gettime = ixgbe_ptp_gettime;
883 adapter->ptp_caps.settime = ixgbe_ptp_settime;
884 adapter->ptp_caps.enable = ixgbe_ptp_enable;
886 case ixgbe_mac_82599EB:
887 snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name);
888 adapter->ptp_caps.owner = THIS_MODULE;
889 adapter->ptp_caps.max_adj = 250000000;
890 adapter->ptp_caps.n_alarm = 0;
891 adapter->ptp_caps.n_ext_ts = 0;
892 adapter->ptp_caps.n_per_out = 0;
893 adapter->ptp_caps.pps = 0;
894 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
895 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
896 adapter->ptp_caps.gettime = ixgbe_ptp_gettime;
897 adapter->ptp_caps.settime = ixgbe_ptp_settime;
898 adapter->ptp_caps.enable = ixgbe_ptp_enable;
901 adapter->ptp_clock = NULL;
905 /* initialize the ptp filter */
906 if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter)))
907 e_dev_warn("ptp_filter_init failed\n");
909 spin_lock_init(&adapter->tmreg_lock);
911 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
912 &adapter->pdev->dev);
913 if (IS_ERR(adapter->ptp_clock)) {
914 adapter->ptp_clock = NULL;
915 e_dev_err("ptp_clock_register failed\n");
917 e_dev_info("registered PHC device on %s\n", netdev->name);
919 ixgbe_ptp_reset(adapter);
921 /* set the flag that PTP has been enabled */
922 adapter->flags2 |= IXGBE_FLAG2_PTP_ENABLED;
928 * ixgbe_ptp_stop - disable ptp device and stop the overflow check
929 * @adapter: pointer to adapter struct
931 * this function stops the ptp support, and cancels the delayed work.
933 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
935 /* stop the overflow check task */
936 adapter->flags2 &= ~(IXGBE_FLAG2_PTP_ENABLED |
937 IXGBE_FLAG2_PTP_PPS_ENABLED);
939 ixgbe_ptp_setup_sdp(adapter);
941 if (adapter->ptp_clock) {
942 ptp_clock_unregister(adapter->ptp_clock);
943 adapter->ptp_clock = NULL;
944 e_dev_info("removed PHC on %s\n",
945 adapter->netdev->name);