1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
5 #include <linux/ptp_classify.h>
6 #include <linux/clocksource.h>
9 * The 82599 and the X540 do not have true 64bit nanosecond scale
10 * counter registers. Instead, SYSTIME is defined by a fixed point
11 * system which allows the user to define the scale counter increment
12 * value at every level change of the oscillator driving the SYSTIME
13 * value. For both devices the TIMINCA:IV field defines this
14 * increment. On the X540 device, 31 bits are provided. However on the
15 * 82599 only provides 24 bits. The time unit is determined by the
16 * clock frequency of the oscillator in combination with the TIMINCA
17 * register. When these devices link at 10Gb the oscillator has a
18 * period of 6.4ns. In order to convert the scale counter into
19 * nanoseconds the cyclecounter and timecounter structures are
20 * used. The SYSTIME registers need to be converted to ns values by use
21 * of only a right shift (division by power of 2). The following math
22 * determines the largest incvalue that will fit into the available
23 * bits in the TIMINCA register.
25 * PeriodWidth: Number of bits to store the clock period
26 * MaxWidth: The maximum width value of the TIMINCA register
27 * Period: The clock period for the oscillator
28 * round(): discard the fractional portion of the calculation
30 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
32 * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns
33 * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns
35 * The period also changes based on the link speed:
36 * At 10Gb link or no link, the period remains the same.
37 * At 1Gb link, the period is multiplied by 10. (64ns)
38 * At 100Mb link, the period is multiplied by 100. (640ns)
40 * The calculated value allows us to right shift the SYSTIME register
41 * value in order to quickly convert it into a nanosecond clock,
42 * while allowing for the maximum possible adjustment value.
44 * These diagrams are only for the 10Gb link period
47 * +--------------+ +--------------+
48 * X540 | 32 | | 1 | 3 | 28 |
49 * *--------------+ +--------------+
50 * \________ 36 bits ______/ fract
52 * +--------------+ +--------------+
53 * 82599 | 32 | | 8 | 3 | 21 |
54 * *--------------+ +--------------+
55 * \________ 43 bits ______/ fract
57 * The 36 bit X540 SYSTIME overflows every
58 * 2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
60 * The 43 bit 82599 SYSTIME overflows every
61 * 2^43 * 10^-9 / 3600 = 2.4 hours
63 #define IXGBE_INCVAL_10GB 0x66666666
64 #define IXGBE_INCVAL_1GB 0x40000000
65 #define IXGBE_INCVAL_100 0x50000000
67 #define IXGBE_INCVAL_SHIFT_10GB 28
68 #define IXGBE_INCVAL_SHIFT_1GB 24
69 #define IXGBE_INCVAL_SHIFT_100 21
71 #define IXGBE_INCVAL_SHIFT_82599 7
72 #define IXGBE_INCPER_SHIFT_82599 24
74 #define IXGBE_OVERFLOW_PERIOD (HZ * 30)
75 #define IXGBE_PTP_TX_TIMEOUT (HZ)
77 /* We use our own definitions instead of NSEC_PER_SEC because we want to mark
78 * the value as a ULL to force precision when bit shifting.
80 #define NS_PER_SEC 1000000000ULL
81 #define NS_PER_HALF_SEC 500000000ULL
83 /* In contrast, the X550 controller has two registers, SYSTIMEH and SYSTIMEL
84 * which contain measurements of seconds and nanoseconds respectively. This
85 * matches the standard linux representation of time in the kernel. In addition,
86 * the X550 also has a SYSTIMER register which represents residue, or
87 * subnanosecond overflow adjustments. To control clock adjustment, the TIMINCA
88 * register is used, but it is unlike the X540 and 82599 devices. TIMINCA
89 * represents units of 2^-32 nanoseconds, and uses 31 bits for this, with the
90 * high bit representing whether the adjustent is positive or negative. Every
91 * clock cycle, the X550 will add 12.5 ns + TIMINCA which can result in a range
92 * of 12 to 13 nanoseconds adjustment. Unlike the 82599 and X540 devices, the
93 * X550's clock for purposes of SYSTIME generation is constant and not dependent
96 * SYSTIMEH SYSTIMEL SYSTIMER
97 * +--------------+ +--------------+ +-------------+
98 * X550 | 32 | | 32 | | 32 |
99 * *--------------+ +--------------+ +-------------+
100 * \____seconds___/ \_nanoseconds_/ \__2^-32 ns__/
102 * This results in a full 96 bits to represent the clock, with 32 bits for
103 * seconds, 32 bits for nanoseconds (largest value is 0d999999999 or just under
104 * 1 second) and an additional 32 bits to measure sub nanosecond adjustments for
105 * underflow of adjustments.
107 * The 32 bits of seconds for the X550 overflows every
108 * 2^32 / ( 365.25 * 24 * 60 * 60 ) = ~136 years.
110 * In order to adjust the clock frequency for the X550, the TIMINCA register is
111 * provided. This register represents a + or minus nearly 0.5 ns adjustment to
112 * the base frequency. It is measured in 2^-32 ns units, with the high bit being
113 * the sign bit. This register enables software to calculate frequency
114 * adjustments and apply them directly to the clock rate.
116 * The math for converting scaled_ppm into TIMINCA values is fairly
119 * TIMINCA value = ( Base_Frequency * scaled_ppm ) / 1000000ULL << 16
121 * To avoid overflow, we simply use mul_u64_u64_div_u64.
123 * This assumes that scaled_ppm is never high enough to create a value bigger
124 * than TIMINCA's 31 bits can store. This is ensured by the stack, and is
125 * measured in parts per billion. Calculating this value is also simple.
126 * Max ppb = ( Max Adjustment / Base Frequency ) / 1000000000ULL
128 * For the X550, the Max adjustment is +/- 0.5 ns, and the base frequency is
129 * 12.5 nanoseconds. This means that the Max ppb is 39999999
130 * Note: We subtract one in order to ensure no overflow, because the TIMINCA
131 * register can only hold slightly under 0.5 nanoseconds.
133 * Because TIMINCA is measured in 2^-32 ns units, we have to convert 12.5 ns
134 * into 2^-32 units, which is
136 * 12.5 * 2^32 = C80000000
138 * Some revisions of hardware have a faster base frequency than the registers
139 * were defined for. To fix this, we use a timecounter structure with the
140 * proper mult and shift to convert the cycles into nanoseconds of time.
142 #define IXGBE_X550_BASE_PERIOD 0xC80000000ULL
143 #define INCVALUE_MASK 0x7FFFFFFF
144 #define ISGN 0x80000000
147 * ixgbe_ptp_setup_sdp_X540
148 * @adapter: private adapter structure
150 * this function enables or disables the clock out feature on SDP0 for
151 * the X540 device. It will create a 1 second periodic output that can
152 * be used as the PPS (via an interrupt).
154 * It calculates when the system time will be on an exact second, and then
155 * aligns the start of the PPS signal to that value.
157 * This works by using the cycle counter shift and mult values in reverse, and
158 * assumes that the values we're shifting will not overflow.
160 static void ixgbe_ptp_setup_sdp_X540(struct ixgbe_adapter *adapter)
162 struct cyclecounter *cc = &adapter->hw_cc;
163 struct ixgbe_hw *hw = &adapter->hw;
164 u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
165 u64 ns = 0, clock_edge = 0, clock_period;
168 /* disable the pin first */
169 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
170 IXGBE_WRITE_FLUSH(hw);
172 if (!(adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED))
175 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
177 /* enable the SDP0 pin as output, and connected to the
178 * native function for Timesync (ClockOut)
180 esdp |= IXGBE_ESDP_SDP0_DIR |
181 IXGBE_ESDP_SDP0_NATIVE;
183 /* enable the Clock Out feature on SDP0, and allow
184 * interrupts to occur when the pin changes
186 tsauxc = (IXGBE_TSAUXC_EN_CLK |
187 IXGBE_TSAUXC_SYNCLK |
188 IXGBE_TSAUXC_SDP0_INT);
190 /* Determine the clock time period to use. This assumes that the
191 * cycle counter shift is small enough to avoid overflow.
193 clock_period = div_u64((NS_PER_HALF_SEC << cc->shift), cc->mult);
194 clktiml = (u32)(clock_period);
195 clktimh = (u32)(clock_period >> 32);
197 /* Read the current clock time, and save the cycle counter value */
198 spin_lock_irqsave(&adapter->tmreg_lock, flags);
199 ns = timecounter_read(&adapter->hw_tc);
200 clock_edge = adapter->hw_tc.cycle_last;
201 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
203 /* Figure out how many seconds to add in order to round up */
204 div_u64_rem(ns, NS_PER_SEC, &rem);
206 /* Figure out how many nanoseconds to add to round the clock edge up
207 * to the next full second
209 rem = (NS_PER_SEC - rem);
211 /* Adjust the clock edge to align with the next full second. */
212 clock_edge += div_u64(((u64)rem << cc->shift), cc->mult);
213 trgttiml = (u32)clock_edge;
214 trgttimh = (u32)(clock_edge >> 32);
216 IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
217 IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
218 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
219 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
221 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
222 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
224 IXGBE_WRITE_FLUSH(hw);
228 * ixgbe_ptp_setup_sdp_X550
229 * @adapter: private adapter structure
231 * Enable or disable a clock output signal on SDP 0 for X550 hardware.
233 * Use the target time feature to align the output signal on the next full
236 * This works by using the cycle counter shift and mult values in reverse, and
237 * assumes that the values we're shifting will not overflow.
239 static void ixgbe_ptp_setup_sdp_X550(struct ixgbe_adapter *adapter)
241 u32 esdp, tsauxc, freqout, trgttiml, trgttimh, rem, tssdp;
242 struct cyclecounter *cc = &adapter->hw_cc;
243 struct ixgbe_hw *hw = &adapter->hw;
244 u64 ns = 0, clock_edge = 0;
245 struct timespec64 ts;
248 /* disable the pin first */
249 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
250 IXGBE_WRITE_FLUSH(hw);
252 if (!(adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED))
255 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
257 /* enable the SDP0 pin as output, and connected to the
258 * native function for Timesync (ClockOut)
260 esdp |= IXGBE_ESDP_SDP0_DIR |
261 IXGBE_ESDP_SDP0_NATIVE;
263 /* enable the Clock Out feature on SDP0, and use Target Time 0 to
264 * enable generation of interrupts on the clock change.
266 #define IXGBE_TSAUXC_DIS_TS_CLEAR 0x40000000
267 tsauxc = (IXGBE_TSAUXC_EN_CLK | IXGBE_TSAUXC_ST0 |
268 IXGBE_TSAUXC_EN_TT0 | IXGBE_TSAUXC_SDP0_INT |
269 IXGBE_TSAUXC_DIS_TS_CLEAR);
271 tssdp = (IXGBE_TSSDP_TS_SDP0_EN |
272 IXGBE_TSSDP_TS_SDP0_CLK0);
274 /* Determine the clock time period to use. This assumes that the
275 * cycle counter shift is small enough to avoid overflowing a 32bit
278 freqout = div_u64(NS_PER_HALF_SEC << cc->shift, cc->mult);
280 /* Read the current clock time, and save the cycle counter value */
281 spin_lock_irqsave(&adapter->tmreg_lock, flags);
282 ns = timecounter_read(&adapter->hw_tc);
283 clock_edge = adapter->hw_tc.cycle_last;
284 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
286 /* Figure out how far past the next second we are */
287 div_u64_rem(ns, NS_PER_SEC, &rem);
289 /* Figure out how many nanoseconds to add to round the clock edge up
290 * to the next full second
292 rem = (NS_PER_SEC - rem);
294 /* Adjust the clock edge to align with the next full second. */
295 clock_edge += div_u64(((u64)rem << cc->shift), cc->mult);
297 /* X550 hardware stores the time in 32bits of 'billions of cycles' and
298 * 32bits of 'cycles'. There's no guarantee that cycles represents
299 * nanoseconds. However, we can use the math from a timespec64 to
300 * convert into the hardware representation.
302 * See ixgbe_ptp_read_X550() for more details.
304 ts = ns_to_timespec64(clock_edge);
305 trgttiml = (u32)ts.tv_nsec;
306 trgttimh = (u32)ts.tv_sec;
308 IXGBE_WRITE_REG(hw, IXGBE_FREQOUT0, freqout);
309 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
310 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
312 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
313 IXGBE_WRITE_REG(hw, IXGBE_TSSDP, tssdp);
314 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
316 IXGBE_WRITE_FLUSH(hw);
320 * ixgbe_ptp_read_X550 - read cycle counter value
321 * @cc: cyclecounter structure
323 * This function reads SYSTIME registers. It is called by the cyclecounter
324 * structure to convert from internal representation into nanoseconds. We need
325 * this for X550 since some skews do not have expected clock frequency and
326 * result of SYSTIME is 32bits of "billions of cycles" and 32 bits of
327 * "cycles", rather than seconds and nanoseconds.
329 static u64 ixgbe_ptp_read_X550(const struct cyclecounter *cc)
331 struct ixgbe_adapter *adapter =
332 container_of(cc, struct ixgbe_adapter, hw_cc);
333 struct ixgbe_hw *hw = &adapter->hw;
334 struct timespec64 ts;
336 /* storage is 32 bits of 'billions of cycles' and 32 bits of 'cycles'.
337 * Some revisions of hardware run at a higher frequency and so the
338 * cycles are not guaranteed to be nanoseconds. The timespec64 created
339 * here is used for its math/conversions but does not necessarily
340 * represent nominal time.
342 * It should be noted that this cyclecounter will overflow at a
343 * non-bitmask field since we have to convert our billions of cycles
344 * into an actual cycles count. This results in some possible weird
345 * situations at high cycle counter stamps. However given that 32 bits
346 * of "seconds" is ~138 years this isn't a problem. Even at the
347 * increased frequency of some revisions, this is still ~103 years.
348 * Since the SYSTIME values start at 0 and we never write them, it is
349 * highly unlikely for the cyclecounter to overflow in practice.
351 IXGBE_READ_REG(hw, IXGBE_SYSTIMR);
352 ts.tv_nsec = IXGBE_READ_REG(hw, IXGBE_SYSTIML);
353 ts.tv_sec = IXGBE_READ_REG(hw, IXGBE_SYSTIMH);
355 return (u64)timespec64_to_ns(&ts);
359 * ixgbe_ptp_read_82599 - read raw cycle counter (to be used by time counter)
360 * @cc: the cyclecounter structure
362 * this function reads the cyclecounter registers and is called by the
363 * cyclecounter structure used to construct a ns counter from the
364 * arbitrary fixed point registers
366 static u64 ixgbe_ptp_read_82599(const struct cyclecounter *cc)
368 struct ixgbe_adapter *adapter =
369 container_of(cc, struct ixgbe_adapter, hw_cc);
370 struct ixgbe_hw *hw = &adapter->hw;
373 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
374 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
380 * ixgbe_ptp_convert_to_hwtstamp - convert register value to hw timestamp
381 * @adapter: private adapter structure
382 * @hwtstamp: stack timestamp structure
383 * @timestamp: unsigned 64bit system time value
385 * We need to convert the adapter's RX/TXSTMP registers into a hwtstamp value
386 * which can be used by the stack's ptp functions.
388 * The lock is used to protect consistency of the cyclecounter and the SYSTIME
389 * registers. However, it does not need to protect against the Rx or Tx
390 * timestamp registers, as there can't be a new timestamp until the old one is
391 * unlatched by reading.
393 * In addition to the timestamp in hardware, some controllers need a software
394 * overflow cyclecounter, and this function takes this into account as well.
396 static void ixgbe_ptp_convert_to_hwtstamp(struct ixgbe_adapter *adapter,
397 struct skb_shared_hwtstamps *hwtstamp,
401 struct timespec64 systime;
404 memset(hwtstamp, 0, sizeof(*hwtstamp));
406 switch (adapter->hw.mac.type) {
407 /* X550 and later hardware supposedly represent time using a seconds
408 * and nanoseconds counter, instead of raw 64bits nanoseconds. We need
409 * to convert the timestamp into cycles before it can be fed to the
410 * cyclecounter. We need an actual cyclecounter because some revisions
411 * of hardware run at a higher frequency and thus the counter does
412 * not represent seconds/nanoseconds. Instead it can be thought of as
413 * cycles and billions of cycles.
416 case ixgbe_mac_X550EM_x:
417 case ixgbe_mac_x550em_a:
418 /* Upper 32 bits represent billions of cycles, lower 32 bits
419 * represent cycles. However, we use timespec64_to_ns for the
420 * correct math even though the units haven't been corrected
423 systime.tv_sec = timestamp >> 32;
424 systime.tv_nsec = timestamp & 0xFFFFFFFF;
426 timestamp = timespec64_to_ns(&systime);
432 spin_lock_irqsave(&adapter->tmreg_lock, flags);
433 ns = timecounter_cyc2time(&adapter->hw_tc, timestamp);
434 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
436 hwtstamp->hwtstamp = ns_to_ktime(ns);
440 * ixgbe_ptp_adjfine_82599
441 * @ptp: the ptp clock structure
442 * @scaled_ppm: scaled parts per million adjustment from base
444 * Adjust the frequency of the ptp cycle counter by the
445 * indicated scaled_ppm from the base frequency.
447 * Scaled parts per million is ppm with a 16-bit binary fractional field.
449 static int ixgbe_ptp_adjfine_82599(struct ptp_clock_info *ptp, long scaled_ppm)
451 struct ixgbe_adapter *adapter =
452 container_of(ptp, struct ixgbe_adapter, ptp_caps);
453 struct ixgbe_hw *hw = &adapter->hw;
457 incval = READ_ONCE(adapter->base_incval);
458 incval = adjust_by_scaled_ppm(incval, scaled_ppm);
460 switch (hw->mac.type) {
462 if (incval > 0xFFFFFFFFULL)
463 e_dev_warn("PTP scaled_ppm adjusted SYSTIME rate overflowed!\n");
464 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, (u32)incval);
466 case ixgbe_mac_82599EB:
467 if (incval > 0x00FFFFFFULL)
468 e_dev_warn("PTP scaled_ppm adjusted SYSTIME rate overflowed!\n");
469 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
470 BIT(IXGBE_INCPER_SHIFT_82599) |
471 ((u32)incval & 0x00FFFFFFUL));
481 * ixgbe_ptp_adjfine_X550
482 * @ptp: the ptp clock structure
483 * @scaled_ppm: scaled parts per million adjustment from base
485 * Adjust the frequency of the SYSTIME registers by the indicated scaled_ppm
486 * from base frequency.
488 * Scaled parts per million is ppm with a 16-bit binary fractional field.
490 static int ixgbe_ptp_adjfine_X550(struct ptp_clock_info *ptp, long scaled_ppm)
492 struct ixgbe_adapter *adapter =
493 container_of(ptp, struct ixgbe_adapter, ptp_caps);
494 struct ixgbe_hw *hw = &adapter->hw;
499 neg_adj = diff_by_scaled_ppm(IXGBE_X550_BASE_PERIOD, scaled_ppm, &rate);
501 /* warn if rate is too large */
502 if (rate >= INCVALUE_MASK)
503 e_dev_warn("PTP scaled_ppm adjusted SYSTIME rate overflowed!\n");
505 inca = rate & INCVALUE_MASK;
509 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, inca);
516 * @ptp: the ptp clock structure
517 * @delta: offset to adjust the cycle counter by
519 * adjust the timer by resetting the timecounter structure.
521 static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
523 struct ixgbe_adapter *adapter =
524 container_of(ptp, struct ixgbe_adapter, ptp_caps);
527 spin_lock_irqsave(&adapter->tmreg_lock, flags);
528 timecounter_adjtime(&adapter->hw_tc, delta);
529 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
531 if (adapter->ptp_setup_sdp)
532 adapter->ptp_setup_sdp(adapter);
539 * @ptp: the ptp clock structure
540 * @ts: timespec to hold the PHC timestamp
541 * @sts: structure to hold the system time before and after reading the PHC
543 * read the timecounter and return the correct value on ns,
544 * after converting it into a struct timespec.
546 static int ixgbe_ptp_gettimex(struct ptp_clock_info *ptp,
547 struct timespec64 *ts,
548 struct ptp_system_timestamp *sts)
550 struct ixgbe_adapter *adapter =
551 container_of(ptp, struct ixgbe_adapter, ptp_caps);
552 struct ixgbe_hw *hw = &adapter->hw;
556 spin_lock_irqsave(&adapter->tmreg_lock, flags);
558 switch (adapter->hw.mac.type) {
560 case ixgbe_mac_X550EM_x:
561 case ixgbe_mac_x550em_a:
562 /* Upper 32 bits represent billions of cycles, lower 32 bits
563 * represent cycles. However, we use timespec64_to_ns for the
564 * correct math even though the units haven't been corrected
567 ptp_read_system_prets(sts);
568 IXGBE_READ_REG(hw, IXGBE_SYSTIMR);
569 ptp_read_system_postts(sts);
570 ts->tv_nsec = IXGBE_READ_REG(hw, IXGBE_SYSTIML);
571 ts->tv_sec = IXGBE_READ_REG(hw, IXGBE_SYSTIMH);
572 stamp = timespec64_to_ns(ts);
575 ptp_read_system_prets(sts);
576 stamp = IXGBE_READ_REG(hw, IXGBE_SYSTIML);
577 ptp_read_system_postts(sts);
578 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
582 ns = timecounter_cyc2time(&adapter->hw_tc, stamp);
584 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
586 *ts = ns_to_timespec64(ns);
593 * @ptp: the ptp clock structure
594 * @ts: the timespec containing the new time for the cycle counter
596 * reset the timecounter to use a new base value instead of the kernel
599 static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
600 const struct timespec64 *ts)
602 struct ixgbe_adapter *adapter =
603 container_of(ptp, struct ixgbe_adapter, ptp_caps);
605 u64 ns = timespec64_to_ns(ts);
607 /* reset the timecounter */
608 spin_lock_irqsave(&adapter->tmreg_lock, flags);
609 timecounter_init(&adapter->hw_tc, &adapter->hw_cc, ns);
610 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
612 if (adapter->ptp_setup_sdp)
613 adapter->ptp_setup_sdp(adapter);
618 * ixgbe_ptp_feature_enable
619 * @ptp: the ptp clock structure
620 * @rq: the requested feature to change
621 * @on: whether to enable or disable the feature
623 * enable (or disable) ancillary features of the phc subsystem.
624 * our driver only supports the PPS feature on the X540
626 static int ixgbe_ptp_feature_enable(struct ptp_clock_info *ptp,
627 struct ptp_clock_request *rq, int on)
629 struct ixgbe_adapter *adapter =
630 container_of(ptp, struct ixgbe_adapter, ptp_caps);
633 * When PPS is enabled, unmask the interrupt for the ClockOut
634 * feature, so that the interrupt handler can send the PPS
635 * event when the clock SDP triggers. Clear mask when PPS is
638 if (rq->type != PTP_CLK_REQ_PPS || !adapter->ptp_setup_sdp)
642 adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
644 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
646 adapter->ptp_setup_sdp(adapter);
651 * ixgbe_ptp_check_pps_event
652 * @adapter: the private adapter structure
654 * This function is called by the interrupt routine when checking for
655 * interrupts. It will check and handle a pps event.
657 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter)
659 struct ixgbe_hw *hw = &adapter->hw;
660 struct ptp_clock_event event;
662 event.type = PTP_CLOCK_PPS;
664 /* this check is necessary in case the interrupt was enabled via some
665 * alternative means (ex. debug_fs). Better to check here than
666 * everywhere that calls this function.
668 if (!adapter->ptp_clock)
671 switch (hw->mac.type) {
673 ptp_clock_event(adapter->ptp_clock, &event);
681 * ixgbe_ptp_overflow_check - watchdog task to detect SYSTIME overflow
682 * @adapter: private adapter struct
684 * this watchdog task periodically reads the timecounter
685 * in order to prevent missing when the system time registers wrap
686 * around. This needs to be run approximately twice a minute.
688 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter)
690 bool timeout = time_is_before_jiffies(adapter->last_overflow_check +
691 IXGBE_OVERFLOW_PERIOD);
695 /* Update the timecounter */
696 spin_lock_irqsave(&adapter->tmreg_lock, flags);
697 timecounter_read(&adapter->hw_tc);
698 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
700 adapter->last_overflow_check = jiffies;
705 * ixgbe_ptp_rx_hang - detect error case when Rx timestamp registers latched
706 * @adapter: private network adapter structure
708 * this watchdog task is scheduled to detect error case where hardware has
709 * dropped an Rx packet that was timestamped when the ring is full. The
710 * particular error is rare but leaves the device in a state unable to timestamp
711 * any future packets.
713 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter)
715 struct ixgbe_hw *hw = &adapter->hw;
716 u32 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
717 struct ixgbe_ring *rx_ring;
718 unsigned long rx_event;
721 /* if we don't have a valid timestamp in the registers, just update the
722 * timeout counter and exit
724 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) {
725 adapter->last_rx_ptp_check = jiffies;
729 /* determine the most recent watchdog or rx_timestamp event */
730 rx_event = adapter->last_rx_ptp_check;
731 for (n = 0; n < adapter->num_rx_queues; n++) {
732 rx_ring = adapter->rx_ring[n];
733 if (time_after(rx_ring->last_rx_timestamp, rx_event))
734 rx_event = rx_ring->last_rx_timestamp;
737 /* only need to read the high RXSTMP register to clear the lock */
738 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
739 IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
740 adapter->last_rx_ptp_check = jiffies;
742 adapter->rx_hwtstamp_cleared++;
743 e_warn(drv, "clearing RX Timestamp hang\n");
748 * ixgbe_ptp_clear_tx_timestamp - utility function to clear Tx timestamp state
749 * @adapter: the private adapter structure
751 * This function should be called whenever the state related to a Tx timestamp
752 * needs to be cleared. This helps ensure that all related bits are reset for
753 * the next Tx timestamp event.
755 static void ixgbe_ptp_clear_tx_timestamp(struct ixgbe_adapter *adapter)
757 struct ixgbe_hw *hw = &adapter->hw;
759 IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
760 if (adapter->ptp_tx_skb) {
761 dev_kfree_skb_any(adapter->ptp_tx_skb);
762 adapter->ptp_tx_skb = NULL;
764 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
768 * ixgbe_ptp_tx_hang - detect error case where Tx timestamp never finishes
769 * @adapter: private network adapter structure
771 void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter)
773 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
774 IXGBE_PTP_TX_TIMEOUT);
776 if (!adapter->ptp_tx_skb)
779 if (!test_bit(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state))
782 /* If we haven't received a timestamp within the timeout, it is
783 * reasonable to assume that it will never occur, so we can unlock the
784 * timestamp bit when this occurs.
787 cancel_work_sync(&adapter->ptp_tx_work);
788 ixgbe_ptp_clear_tx_timestamp(adapter);
789 adapter->tx_hwtstamp_timeouts++;
790 e_warn(drv, "clearing Tx timestamp hang\n");
795 * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp
796 * @adapter: the private adapter struct
798 * if the timestamp is valid, we convert it into the timecounter ns
799 * value, then store that result into the shhwtstamps structure which
800 * is passed up the network stack
802 static void ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter *adapter)
804 struct sk_buff *skb = adapter->ptp_tx_skb;
805 struct ixgbe_hw *hw = &adapter->hw;
806 struct skb_shared_hwtstamps shhwtstamps;
809 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
810 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
811 ixgbe_ptp_convert_to_hwtstamp(adapter, &shhwtstamps, regval);
813 /* Handle cleanup of the ptp_tx_skb ourselves, and unlock the state
814 * bit prior to notifying the stack via skb_tstamp_tx(). This prevents
815 * well behaved applications from attempting to timestamp again prior
816 * to the lock bit being clear.
818 adapter->ptp_tx_skb = NULL;
819 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
821 /* Notify the stack and then free the skb after we've unlocked */
822 skb_tstamp_tx(skb, &shhwtstamps);
823 dev_kfree_skb_any(skb);
827 * ixgbe_ptp_tx_hwtstamp_work
828 * @work: pointer to the work struct
830 * This work item polls TSYNCTXCTL valid bit to determine when a Tx hardware
831 * timestamp has been taken for the current skb. It is necessary, because the
832 * descriptor's "done" bit does not correlate with the timestamp event.
834 static void ixgbe_ptp_tx_hwtstamp_work(struct work_struct *work)
836 struct ixgbe_adapter *adapter = container_of(work, struct ixgbe_adapter,
838 struct ixgbe_hw *hw = &adapter->hw;
839 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
840 IXGBE_PTP_TX_TIMEOUT);
843 /* we have to have a valid skb to poll for a timestamp */
844 if (!adapter->ptp_tx_skb) {
845 ixgbe_ptp_clear_tx_timestamp(adapter);
849 /* stop polling once we have a valid timestamp */
850 tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
851 if (tsynctxctl & IXGBE_TSYNCTXCTL_VALID) {
852 ixgbe_ptp_tx_hwtstamp(adapter);
857 ixgbe_ptp_clear_tx_timestamp(adapter);
858 adapter->tx_hwtstamp_timeouts++;
859 e_warn(drv, "clearing Tx Timestamp hang\n");
861 /* reschedule to keep checking if it's not available yet */
862 schedule_work(&adapter->ptp_tx_work);
867 * ixgbe_ptp_rx_pktstamp - utility function to get RX time stamp from buffer
868 * @q_vector: structure containing interrupt and ring information
871 * This function will be called by the Rx routine of the timestamp for this
872 * packet is stored in the buffer. The value is stored in little endian format
873 * starting at the end of the packet data.
875 void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *q_vector,
880 /* copy the bits out of the skb, and then trim the skb length */
881 skb_copy_bits(skb, skb->len - IXGBE_TS_HDR_LEN, ®val,
883 __pskb_trim(skb, skb->len - IXGBE_TS_HDR_LEN);
885 /* The timestamp is recorded in little endian format, and is stored at
886 * the end of the packet.
888 * DWORD: N N + 1 N + 2
889 * Field: End of Packet SYSTIMH SYSTIML
891 ixgbe_ptp_convert_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb),
892 le64_to_cpu(regval));
896 * ixgbe_ptp_rx_rgtstamp - utility function which checks for RX time stamp
897 * @q_vector: structure containing interrupt and ring information
898 * @skb: particular skb to send timestamp with
900 * if the timestamp is valid, we convert it into the timecounter ns
901 * value, then store that result into the shhwtstamps structure which
902 * is passed up the network stack
904 void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *q_vector,
907 struct ixgbe_adapter *adapter;
912 /* we cannot process timestamps on a ring without a q_vector */
913 if (!q_vector || !q_vector->adapter)
916 adapter = q_vector->adapter;
919 /* Read the tsyncrxctl register afterwards in order to prevent taking an
920 * I/O hit on every packet.
923 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
924 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID))
927 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
928 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
930 ixgbe_ptp_convert_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
934 * ixgbe_ptp_get_ts_config - get current hardware timestamping configuration
935 * @adapter: pointer to adapter structure
938 * This function returns the current timestamping settings. Rather than
939 * attempt to deconstruct registers to fill in the values, simply keep a copy
940 * of the old settings around, and return a copy when requested.
942 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
944 struct hwtstamp_config *config = &adapter->tstamp_config;
946 return copy_to_user(ifr->ifr_data, config,
947 sizeof(*config)) ? -EFAULT : 0;
951 * ixgbe_ptp_set_timestamp_mode - setup the hardware for the requested mode
952 * @adapter: the private ixgbe adapter structure
953 * @config: the hwtstamp configuration requested
955 * Outgoing time stamping can be enabled and disabled. Play nice and
956 * disable it when requested, although it shouldn't cause any overhead
957 * when no packet needs it. At most one packet in the queue may be
958 * marked for time stamping, otherwise it would be impossible to tell
959 * for sure to which packet the hardware time stamp belongs.
961 * Incoming time stamping has to be configured via the hardware
962 * filters. Not all combinations are supported, in particular event
963 * type has to be specified. Matching the kind of event packet is
964 * not supported, with the exception of "all V2 events regardless of
967 * Since hardware always timestamps Path delay packets when timestamping V2
968 * packets, regardless of the type specified in the register, only use V2
969 * Event mode. This more accurately tells the user what the hardware is going
972 * Note: this may modify the hwtstamp configuration towards a more general
973 * mode, if required to support the specifically requested mode.
975 static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter,
976 struct hwtstamp_config *config)
978 struct ixgbe_hw *hw = &adapter->hw;
979 u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
980 u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
981 u32 tsync_rx_mtrl = PTP_EV_PORT << 16;
985 switch (config->tx_type) {
986 case HWTSTAMP_TX_OFF:
995 switch (config->rx_filter) {
996 case HWTSTAMP_FILTER_NONE:
999 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1000 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1002 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1003 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
1004 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG;
1005 adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1006 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1008 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1009 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
1010 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
1011 adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1012 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1014 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1015 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1016 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1017 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1018 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1019 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1020 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1021 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1022 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1023 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
1025 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1026 adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1027 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1029 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1030 case HWTSTAMP_FILTER_NTP_ALL:
1031 case HWTSTAMP_FILTER_ALL:
1032 /* The X550 controller is capable of timestamping all packets,
1033 * which allows it to accept any filter.
1035 if (hw->mac.type >= ixgbe_mac_X550) {
1036 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_ALL;
1037 config->rx_filter = HWTSTAMP_FILTER_ALL;
1038 adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED;
1044 * register RXMTRL must be set in order to do V1 packets,
1045 * therefore it is not possible to time stamp both V1 Sync and
1046 * Delay_Req messages and hardware does not support
1047 * timestamping all packets => return error
1049 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1050 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1051 config->rx_filter = HWTSTAMP_FILTER_NONE;
1055 if (hw->mac.type == ixgbe_mac_82598EB) {
1056 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1057 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1058 if (tsync_rx_ctl | tsync_tx_ctl)
1063 /* Per-packet timestamping only works if the filter is set to all
1064 * packets. Since this is desired, always timestamp all packets as long
1065 * as any Rx filter was configured.
1067 switch (hw->mac.type) {
1068 case ixgbe_mac_X550:
1069 case ixgbe_mac_X550EM_x:
1070 case ixgbe_mac_x550em_a:
1071 /* enable timestamping all packets only if at least some
1072 * packets were requested. Otherwise, play nice and disable
1075 if (config->rx_filter == HWTSTAMP_FILTER_NONE)
1078 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED |
1079 IXGBE_TSYNCRXCTL_TYPE_ALL |
1080 IXGBE_TSYNCRXCTL_TSIP_UT_EN;
1081 config->rx_filter = HWTSTAMP_FILTER_ALL;
1082 adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED;
1083 adapter->flags &= ~IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER;
1090 /* define ethertype filter for timestamping L2 packets */
1092 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
1093 (IXGBE_ETQF_FILTER_EN | /* enable filter */
1094 IXGBE_ETQF_1588 | /* enable timestamping */
1095 ETH_P_1588)); /* 1588 eth protocol type */
1097 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
1099 /* enable/disable TX */
1100 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
1101 regval &= ~IXGBE_TSYNCTXCTL_ENABLED;
1102 regval |= tsync_tx_ctl;
1103 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);
1105 /* enable/disable RX */
1106 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
1107 regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);
1108 regval |= tsync_rx_ctl;
1109 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);
1111 /* define which PTP packets are time stamped */
1112 IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl);
1114 IXGBE_WRITE_FLUSH(hw);
1116 /* clear TX/RX time stamp registers, just to be sure */
1117 ixgbe_ptp_clear_tx_timestamp(adapter);
1118 IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
1124 * ixgbe_ptp_set_ts_config - user entry point for timestamp mode
1125 * @adapter: pointer to adapter struct
1128 * Set hardware to requested mode. If unsupported, return an error with no
1129 * changes. Otherwise, store the mode for future reference.
1131 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
1133 struct hwtstamp_config config;
1136 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1139 err = ixgbe_ptp_set_timestamp_mode(adapter, &config);
1143 /* save these settings for future reference */
1144 memcpy(&adapter->tstamp_config, &config,
1145 sizeof(adapter->tstamp_config));
1147 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1151 static void ixgbe_ptp_link_speed_adjust(struct ixgbe_adapter *adapter,
1152 u32 *shift, u32 *incval)
1155 * Scale the NIC cycle counter by a large factor so that
1156 * relatively small corrections to the frequency can be added
1157 * or subtracted. The drawbacks of a large factor include
1158 * (a) the clock register overflows more quickly, (b) the cycle
1159 * counter structure must be able to convert the systime value
1160 * to nanoseconds using only a multiplier and a right-shift,
1161 * and (c) the value must fit within the timinca register space
1162 * => math based on internal DMA clock rate and available bits
1164 * Note that when there is no link, internal DMA clock is same as when
1165 * link speed is 10Gb. Set the registers correctly even when link is
1166 * down to preserve the clock setting
1168 switch (adapter->link_speed) {
1169 case IXGBE_LINK_SPEED_100_FULL:
1170 *shift = IXGBE_INCVAL_SHIFT_100;
1171 *incval = IXGBE_INCVAL_100;
1173 case IXGBE_LINK_SPEED_1GB_FULL:
1174 *shift = IXGBE_INCVAL_SHIFT_1GB;
1175 *incval = IXGBE_INCVAL_1GB;
1177 case IXGBE_LINK_SPEED_10GB_FULL:
1179 *shift = IXGBE_INCVAL_SHIFT_10GB;
1180 *incval = IXGBE_INCVAL_10GB;
1186 * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw
1187 * @adapter: pointer to the adapter structure
1189 * This function should be called to set the proper values for the TIMINCA
1190 * register and tell the cyclecounter structure what the tick rate of SYSTIME
1191 * is. It does not directly modify SYSTIME registers or the timecounter
1192 * structure. It should be called whenever a new TIMINCA value is necessary,
1193 * such as during initialization or when the link speed changes.
1195 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
1197 struct ixgbe_hw *hw = &adapter->hw;
1198 struct cyclecounter cc;
1199 unsigned long flags;
1203 /* For some of the boards below this mask is technically incorrect.
1204 * The timestamp mask overflows at approximately 61bits. However the
1205 * particular hardware does not overflow on an even bitmask value.
1206 * Instead, it overflows due to conversion of upper 32bits billions of
1207 * cycles. Timecounters are not really intended for this purpose so
1208 * they do not properly function if the overflow point isn't 2^N-1.
1209 * However, the actual SYSTIME values in question take ~138 years to
1210 * overflow. In practice this means they won't actually overflow. A
1211 * proper fix to this problem would require modification of the
1212 * timecounter delta calculations.
1214 cc.mask = CLOCKSOURCE_MASK(64);
1218 switch (hw->mac.type) {
1219 case ixgbe_mac_X550EM_x:
1220 /* SYSTIME assumes X550EM_x board frequency is 300Mhz, and is
1221 * designed to represent seconds and nanoseconds when this is
1222 * the case. However, some revisions of hardware have a 400Mhz
1223 * clock and we have to compensate for this frequency
1224 * variation using corrected mult and shift values.
1226 fuse0 = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
1227 if (!(fuse0 & IXGBE_FUSES0_300MHZ)) {
1232 case ixgbe_mac_x550em_a:
1233 case ixgbe_mac_X550:
1234 cc.read = ixgbe_ptp_read_X550;
1236 case ixgbe_mac_X540:
1237 cc.read = ixgbe_ptp_read_82599;
1239 ixgbe_ptp_link_speed_adjust(adapter, &cc.shift, &incval);
1240 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
1242 case ixgbe_mac_82599EB:
1243 cc.read = ixgbe_ptp_read_82599;
1245 ixgbe_ptp_link_speed_adjust(adapter, &cc.shift, &incval);
1246 incval >>= IXGBE_INCVAL_SHIFT_82599;
1247 cc.shift -= IXGBE_INCVAL_SHIFT_82599;
1248 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
1249 BIT(IXGBE_INCPER_SHIFT_82599) | incval);
1252 /* other devices aren't supported */
1256 /* update the base incval used to calculate frequency adjustment */
1257 WRITE_ONCE(adapter->base_incval, incval);
1260 /* need lock to prevent incorrect read while modifying cyclecounter */
1261 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1262 memcpy(&adapter->hw_cc, &cc, sizeof(adapter->hw_cc));
1263 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1267 * ixgbe_ptp_init_systime - Initialize SYSTIME registers
1268 * @adapter: the ixgbe private board structure
1270 * Initialize and start the SYSTIME registers.
1272 static void ixgbe_ptp_init_systime(struct ixgbe_adapter *adapter)
1274 struct ixgbe_hw *hw = &adapter->hw;
1277 switch (hw->mac.type) {
1278 case ixgbe_mac_X550EM_x:
1279 case ixgbe_mac_x550em_a:
1280 case ixgbe_mac_X550:
1281 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
1283 /* Reset SYSTIME registers to 0 */
1284 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMR, 0);
1285 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0);
1286 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0);
1288 /* Reset interrupt settings */
1289 IXGBE_WRITE_REG(hw, IXGBE_TSIM, IXGBE_TSIM_TXTS);
1290 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_TIMESYNC);
1292 /* Activate the SYSTIME counter */
1293 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC,
1294 tsauxc & ~IXGBE_TSAUXC_DISABLE_SYSTIME);
1296 case ixgbe_mac_X540:
1297 case ixgbe_mac_82599EB:
1298 /* Reset SYSTIME registers to 0 */
1299 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0);
1300 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0);
1303 /* Other devices aren't supported */
1307 IXGBE_WRITE_FLUSH(hw);
1312 * @adapter: the ixgbe private board structure
1314 * When the MAC resets, all the hardware bits for timesync are reset. This
1315 * function is used to re-enable the device for PTP based on current settings.
1316 * We do lose the current clock time, so just reset the cyclecounter to the
1317 * system real clock time.
1319 * This function will maintain hwtstamp_config settings, and resets the SDP
1320 * output if it was enabled.
1322 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter)
1324 struct ixgbe_hw *hw = &adapter->hw;
1325 unsigned long flags;
1327 /* reset the hardware timestamping mode */
1328 ixgbe_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1330 /* 82598 does not support PTP */
1331 if (hw->mac.type == ixgbe_mac_82598EB)
1334 ixgbe_ptp_start_cyclecounter(adapter);
1336 ixgbe_ptp_init_systime(adapter);
1338 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1339 timecounter_init(&adapter->hw_tc, &adapter->hw_cc,
1340 ktime_to_ns(ktime_get_real()));
1341 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1343 adapter->last_overflow_check = jiffies;
1345 /* Now that the shift has been calculated and the systime
1346 * registers reset, (re-)enable the Clock out feature
1348 if (adapter->ptp_setup_sdp)
1349 adapter->ptp_setup_sdp(adapter);
1353 * ixgbe_ptp_create_clock
1354 * @adapter: the ixgbe private adapter structure
1356 * This function performs setup of the user entry point function table and
1357 * initializes the PTP clock device, which is used to access the clock-like
1358 * features of the PTP core. It will be called by ixgbe_ptp_init, and may
1359 * reuse a previously initialized clock (such as during a suspend/resume
1362 static long ixgbe_ptp_create_clock(struct ixgbe_adapter *adapter)
1364 struct net_device *netdev = adapter->netdev;
1367 /* do nothing if we already have a clock device */
1368 if (!IS_ERR_OR_NULL(adapter->ptp_clock))
1371 switch (adapter->hw.mac.type) {
1372 case ixgbe_mac_X540:
1373 snprintf(adapter->ptp_caps.name,
1374 sizeof(adapter->ptp_caps.name),
1375 "%s", netdev->name);
1376 adapter->ptp_caps.owner = THIS_MODULE;
1377 adapter->ptp_caps.max_adj = 250000000;
1378 adapter->ptp_caps.n_alarm = 0;
1379 adapter->ptp_caps.n_ext_ts = 0;
1380 adapter->ptp_caps.n_per_out = 0;
1381 adapter->ptp_caps.pps = 1;
1382 adapter->ptp_caps.adjfine = ixgbe_ptp_adjfine_82599;
1383 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1384 adapter->ptp_caps.gettimex64 = ixgbe_ptp_gettimex;
1385 adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1386 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1387 adapter->ptp_setup_sdp = ixgbe_ptp_setup_sdp_X540;
1389 case ixgbe_mac_82599EB:
1390 snprintf(adapter->ptp_caps.name,
1391 sizeof(adapter->ptp_caps.name),
1392 "%s", netdev->name);
1393 adapter->ptp_caps.owner = THIS_MODULE;
1394 adapter->ptp_caps.max_adj = 250000000;
1395 adapter->ptp_caps.n_alarm = 0;
1396 adapter->ptp_caps.n_ext_ts = 0;
1397 adapter->ptp_caps.n_per_out = 0;
1398 adapter->ptp_caps.pps = 0;
1399 adapter->ptp_caps.adjfine = ixgbe_ptp_adjfine_82599;
1400 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1401 adapter->ptp_caps.gettimex64 = ixgbe_ptp_gettimex;
1402 adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1403 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1405 case ixgbe_mac_X550:
1406 case ixgbe_mac_X550EM_x:
1407 case ixgbe_mac_x550em_a:
1408 snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name);
1409 adapter->ptp_caps.owner = THIS_MODULE;
1410 adapter->ptp_caps.max_adj = 30000000;
1411 adapter->ptp_caps.n_alarm = 0;
1412 adapter->ptp_caps.n_ext_ts = 0;
1413 adapter->ptp_caps.n_per_out = 0;
1414 adapter->ptp_caps.pps = 1;
1415 adapter->ptp_caps.adjfine = ixgbe_ptp_adjfine_X550;
1416 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1417 adapter->ptp_caps.gettimex64 = ixgbe_ptp_gettimex;
1418 adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1419 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1420 adapter->ptp_setup_sdp = ixgbe_ptp_setup_sdp_X550;
1423 adapter->ptp_clock = NULL;
1424 adapter->ptp_setup_sdp = NULL;
1428 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1429 &adapter->pdev->dev);
1430 if (IS_ERR(adapter->ptp_clock)) {
1431 err = PTR_ERR(adapter->ptp_clock);
1432 adapter->ptp_clock = NULL;
1433 e_dev_err("ptp_clock_register failed\n");
1435 } else if (adapter->ptp_clock)
1436 e_dev_info("registered PHC device on %s\n", netdev->name);
1438 /* set default timestamp mode to disabled here. We do this in
1439 * create_clock instead of init, because we don't want to override the
1440 * previous settings during a resume cycle.
1442 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1443 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1450 * @adapter: the ixgbe private adapter structure
1452 * This function performs the required steps for enabling PTP
1453 * support. If PTP support has already been loaded it simply calls the
1454 * cyclecounter init routine and exits.
1456 void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
1458 /* initialize the spin lock first since we can't control when a user
1459 * will call the entry functions once we have initialized the clock
1462 spin_lock_init(&adapter->tmreg_lock);
1464 /* obtain a PTP device, or re-use an existing device */
1465 if (ixgbe_ptp_create_clock(adapter))
1468 /* we have a clock so we can initialize work now */
1469 INIT_WORK(&adapter->ptp_tx_work, ixgbe_ptp_tx_hwtstamp_work);
1471 /* reset the PTP related hardware bits */
1472 ixgbe_ptp_reset(adapter);
1474 /* enter the IXGBE_PTP_RUNNING state */
1475 set_bit(__IXGBE_PTP_RUNNING, &adapter->state);
1481 * ixgbe_ptp_suspend - stop PTP work items
1482 * @adapter: pointer to adapter struct
1484 * this function suspends PTP activity, and prevents more PTP work from being
1485 * generated, but does not destroy the PTP clock device.
1487 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter)
1489 /* Leave the IXGBE_PTP_RUNNING state. */
1490 if (!test_and_clear_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1493 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
1494 if (adapter->ptp_setup_sdp)
1495 adapter->ptp_setup_sdp(adapter);
1497 /* ensure that we cancel any pending PTP Tx work item in progress */
1498 cancel_work_sync(&adapter->ptp_tx_work);
1499 ixgbe_ptp_clear_tx_timestamp(adapter);
1503 * ixgbe_ptp_stop - close the PTP device
1504 * @adapter: pointer to adapter struct
1506 * completely destroy the PTP device, should only be called when the device is
1507 * being fully closed.
1509 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
1511 /* first, suspend PTP activity */
1512 ixgbe_ptp_suspend(adapter);
1514 /* disable the PTP clock device */
1515 if (adapter->ptp_clock) {
1516 ptp_clock_unregister(adapter->ptp_clock);
1517 adapter->ptp_clock = NULL;
1518 e_dev_info("removed PHC on %s\n",
1519 adapter->netdev->name);