drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2014 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #include <linux/pci.h>
  30 #include <linux/delay.h>
  31 #include <linux/sched.h>
  32
  33 #include "ixgbe.h"
  34 #include "ixgbe_phy.h"
  35
  36 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  37 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  38 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  39 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  40 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  41 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  42 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  43 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  44 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  45 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  46 static bool ixgbe_get_i2c_data(u32 *i2cctl);
  47 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
  48 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
  49 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
  50 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
  51
  52 /**
  53  *  ixgbe_identify_phy_generic - Get physical layer module
  54  *  @hw: pointer to hardware structure
  55  *
  56  *  Determines the physical layer module found on the current adapter.
  57  **/
  58 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  59 {
  60         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  61         u32 phy_addr;
  62         u16 ext_ability = 0;
  63
  64         if (hw->phy.type == ixgbe_phy_unknown) {
  65                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
  66                         hw->phy.mdio.prtad = phy_addr;
  67                         if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
  68                                 ixgbe_get_phy_id(hw);
  69                                 hw->phy.type =
  70                                         ixgbe_get_phy_type_from_id(hw->phy.id);
  71
  72                                 if (hw->phy.type == ixgbe_phy_unknown) {
  73                                         hw->phy.ops.read_reg(hw,
  74                                                              MDIO_PMA_EXTABLE,
  75                                                              MDIO_MMD_PMAPMD,
  76                                                              &ext_ability);
  77                                         if (ext_ability &
  78                                             (MDIO_PMA_EXTABLE_10GBT |
  79                                              MDIO_PMA_EXTABLE_1000BT))
  80                                                 hw->phy.type =
  81                                                          ixgbe_phy_cu_unknown;
  82                                         else
  83                                                 hw->phy.type =
  84                                                          ixgbe_phy_generic;
  85                                 }
  86
  87                                 status = 0;
  88                                 break;
  89                         }
  90                 }
  91                 /* clear value if nothing found */
  92                 if (status != 0)
  93                         hw->phy.mdio.prtad = 0;
  94         } else {
  95                 status = 0;
  96         }
  97
  98         return status;
  99 }
 100
 101 /**
 102  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 103  * @hw: pointer to the hardware structure
 104  *
 105  * This function checks the MMNGC.MNG_VETO bit to see if there are
 106  * any constraints on link from manageability.  For MAC's that don't
 107  * have this bit just return false since the link can not be blocked
 108  * via this method.
 109  **/
 110 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 111 {
 112         u32 mmngc;
 113
 114         /* If we don't have this bit, it can't be blocking */
 115         if (hw->mac.type == ixgbe_mac_82598EB)
 116                 return false;
 117
 118         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 119         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 120                 hw_dbg(hw, "MNG_VETO bit detected.\n");
 121                 return true;
 122         }
 123
 124         return false;
 125 }
 126
 127 /**
 128  *  ixgbe_get_phy_id - Get the phy type
 129  *  @hw: pointer to hardware structure
 130  *
 131  **/
 132 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 133 {
 134         u32 status;
 135         u16 phy_id_high = 0;
 136         u16 phy_id_low = 0;
 137
 138         status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
 139                                       &phy_id_high);
 140
 141         if (status == 0) {
 142                 hw->phy.id = (u32)(phy_id_high << 16);
 143                 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
 144                                               &phy_id_low);
 145                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 146                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 147         }
 148         return status;
 149 }
 150
 151 /**
 152  *  ixgbe_get_phy_type_from_id - Get the phy type
 153  *  @hw: pointer to hardware structure
 154  *
 155  **/
 156 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 157 {
 158         enum ixgbe_phy_type phy_type;
 159
 160         switch (phy_id) {
 161         case TN1010_PHY_ID:
 162                 phy_type = ixgbe_phy_tn;
 163                 break;
 164         case X540_PHY_ID:
 165                 phy_type = ixgbe_phy_aq;
 166                 break;
 167         case QT2022_PHY_ID:
 168                 phy_type = ixgbe_phy_qt;
 169                 break;
 170         case ATH_PHY_ID:
 171                 phy_type = ixgbe_phy_nl;
 172                 break;
 173         default:
 174                 phy_type = ixgbe_phy_unknown;
 175                 break;
 176         }
 177
 178         return phy_type;
 179 }
 180
 181 /**
 182  *  ixgbe_reset_phy_generic - Performs a PHY reset
 183  *  @hw: pointer to hardware structure
 184  **/
 185 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 186 {
 187         u32 i;
 188         u16 ctrl = 0;
 189         s32 status = 0;
 190
 191         if (hw->phy.type == ixgbe_phy_unknown)
 192                 status = ixgbe_identify_phy_generic(hw);
 193
 194         if (status != 0 || hw->phy.type == ixgbe_phy_none)
 195                 goto out;
 196
 197         /* Don't reset PHY if it's shut down due to overtemp. */
 198         if (!hw->phy.reset_if_overtemp &&
 199             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 200                 goto out;
 201
 202         /* Blocked by MNG FW so bail */
 203         if (ixgbe_check_reset_blocked(hw))
 204                 goto out;
 205
 206         /*
 207          * Perform soft PHY reset to the PHY_XS.
 208          * This will cause a soft reset to the PHY
 209          */
 210         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 211                               MDIO_MMD_PHYXS,
 212                               MDIO_CTRL1_RESET);
 213
 214         /*
 215          * Poll for reset bit to self-clear indicating reset is complete.
 216          * Some PHYs could take up to 3 seconds to complete and need about
 217          * 1.7 usec delay after the reset is complete.
 218          */
 219         for (i = 0; i < 30; i++) {
 220                 msleep(100);
 221                 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 222                                      MDIO_MMD_PHYXS, &ctrl);
 223                 if (!(ctrl & MDIO_CTRL1_RESET)) {
 224                         udelay(2);
 225                         break;
 226                 }
 227         }
 228
 229         if (ctrl & MDIO_CTRL1_RESET) {
 230                 status = IXGBE_ERR_RESET_FAILED;
 231                 hw_dbg(hw, "PHY reset polling failed to complete.\n");
 232         }
 233
 234 out:
 235         return status;
 236 }
 237
 238 /**
 239  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 240  *  the SWFW lock
 241  *  @hw: pointer to hardware structure
 242  *  @reg_addr: 32 bit address of PHY register to read
 243  *  @phy_data: Pointer to read data from PHY register
 244  **/
 245 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 246                        u16 *phy_data)
 247 {
 248         u32 i, data, command;
 249
 250         /* Setup and write the address cycle command */
 251         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 252                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 253                    (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 254                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 255
 256         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 257
 258         /* Check every 10 usec to see if the address cycle completed.
 259          * The MDI Command bit will clear when the operation is
 260          * complete
 261          */
 262         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 263                 udelay(10);
 264
 265                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 266                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 267                                 break;
 268         }
 269
 270
 271         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 272                 hw_dbg(hw, "PHY address command did not complete.\n");
 273                 return IXGBE_ERR_PHY;
 274         }
 275
 276         /* Address cycle complete, setup and write the read
 277          * command
 278          */
 279         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 280                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 281                    (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 282                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 283
 284         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 285
 286         /* Check every 10 usec to see if the address cycle
 287          * completed. The MDI Command bit will clear when the
 288          * operation is complete
 289          */
 290         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 291                 udelay(10);
 292
 293                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 294                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 295                         break;
 296         }
 297
 298         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 299                 hw_dbg(hw, "PHY read command didn't complete\n");
 300                 return IXGBE_ERR_PHY;
 301         }
 302
 303         /* Read operation is complete.  Get the data
 304          * from MSRWD
 305          */
 306         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 307         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 308         *phy_data = (u16)(data);
 309
 310         return 0;
 311 }
 312
 313 /**
 314  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 315  *  using the SWFW lock - this function is needed in most cases
 316  *  @hw: pointer to hardware structure
 317  *  @reg_addr: 32 bit address of PHY register to read
 318  *  @phy_data: Pointer to read data from PHY register
 319  **/
 320 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 321                                u32 device_type, u16 *phy_data)
 322 {
 323         s32 status;
 324         u16 gssr;
 325
 326         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 327                 gssr = IXGBE_GSSR_PHY1_SM;
 328         else
 329                 gssr = IXGBE_GSSR_PHY0_SM;
 330
 331         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
 332                 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 333                                                 phy_data);
 334                 hw->mac.ops.release_swfw_sync(hw, gssr);
 335         } else {
 336                 status = IXGBE_ERR_SWFW_SYNC;
 337         }
 338
 339         return status;
 340 }
 341
 342 /**
 343  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 344  *  without SWFW lock
 345  *  @hw: pointer to hardware structure
 346  *  @reg_addr: 32 bit PHY register to write
 347  *  @device_type: 5 bit device type
 348  *  @phy_data: Data to write to the PHY register
 349  **/
 350 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 351                                 u32 device_type, u16 phy_data)
 352 {
 353         u32 i, command;
 354
 355         /* Put the data in the MDI single read and write data register*/
 356         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 357
 358         /* Setup and write the address cycle command */
 359         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 360                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 361                    (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 362                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 363
 364         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 365
 366         /*
 367          * Check every 10 usec to see if the address cycle completed.
 368          * The MDI Command bit will clear when the operation is
 369          * complete
 370          */
 371         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 372                 udelay(10);
 373
 374                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 375                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 376                         break;
 377         }
 378
 379         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 380                 hw_dbg(hw, "PHY address cmd didn't complete\n");
 381                 return IXGBE_ERR_PHY;
 382         }
 383
 384         /*
 385          * Address cycle complete, setup and write the write
 386          * command
 387          */
 388         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 389                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 390                    (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 391                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 392
 393         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 394
 395         /* Check every 10 usec to see if the address cycle
 396          * completed. The MDI Command bit will clear when the
 397          * operation is complete
 398          */
 399         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 400                 udelay(10);
 401
 402                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 403                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 404                         break;
 405         }
 406
 407         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 408                 hw_dbg(hw, "PHY write cmd didn't complete\n");
 409                 return IXGBE_ERR_PHY;
 410         }
 411
 412         return 0;
 413 }
 414
 415 /**
 416  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 417  *  using SWFW lock- this function is needed in most cases
 418  *  @hw: pointer to hardware structure
 419  *  @reg_addr: 32 bit PHY register to write
 420  *  @device_type: 5 bit device type
 421  *  @phy_data: Data to write to the PHY register
 422  **/
 423 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 424                                 u32 device_type, u16 phy_data)
 425 {
 426         s32 status;
 427         u16 gssr;
 428
 429         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 430                 gssr = IXGBE_GSSR_PHY1_SM;
 431         else
 432                 gssr = IXGBE_GSSR_PHY0_SM;
 433
 434         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
 435                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 436                                                  phy_data);
 437                 hw->mac.ops.release_swfw_sync(hw, gssr);
 438         } else {
 439                 status = IXGBE_ERR_SWFW_SYNC;
 440         }
 441
 442         return status;
 443 }
 444
 445 /**
 446  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 447  *  @hw: pointer to hardware structure
 448  *
 449  *  Restart autonegotiation and PHY and waits for completion.
 450  **/
 451 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 452 {
 453         s32 status = 0;
 454         u32 time_out;
 455         u32 max_time_out = 10;
 456         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 457         bool autoneg = false;
 458         ixgbe_link_speed speed;
 459
 460         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 461
 462         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 463                 /* Set or unset auto-negotiation 10G advertisement */
 464                 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
 465                                      MDIO_MMD_AN,
 466                                      &autoneg_reg);
 467
 468                 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
 469                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 470                         autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
 471
 472                 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
 473                                       MDIO_MMD_AN,
 474                                       autoneg_reg);
 475         }
 476
 477         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 478                 /* Set or unset auto-negotiation 1G advertisement */
 479                 hw->phy.ops.read_reg(hw,
 480                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 481                                      MDIO_MMD_AN,
 482                                      &autoneg_reg);
 483
 484                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 485                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 486                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 487
 488                 hw->phy.ops.write_reg(hw,
 489                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 490                                       MDIO_MMD_AN,
 491                                       autoneg_reg);
 492         }
 493
 494         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 495                 /* Set or unset auto-negotiation 100M advertisement */
 496                 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
 497                                      MDIO_MMD_AN,
 498                                      &autoneg_reg);
 499
 500                 autoneg_reg &= ~(ADVERTISE_100FULL |
 501                                  ADVERTISE_100HALF);
 502                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 503                         autoneg_reg |= ADVERTISE_100FULL;
 504
 505                 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
 506                                       MDIO_MMD_AN,
 507                                       autoneg_reg);
 508         }
 509
 510         /* Blocked by MNG FW so don't reset PHY */
 511         if (ixgbe_check_reset_blocked(hw))
 512                 return status;
 513
 514         /* Restart PHY autonegotiation and wait for completion */
 515         hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 516                              MDIO_MMD_AN, &autoneg_reg);
 517
 518         autoneg_reg |= MDIO_AN_CTRL1_RESTART;
 519
 520         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 521                               MDIO_MMD_AN, autoneg_reg);
 522
 523         /* Wait for autonegotiation to finish */
 524         for (time_out = 0; time_out < max_time_out; time_out++) {
 525                 udelay(10);
 526                 /* Restart PHY autonegotiation and wait for completion */
 527                 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
 528                                               MDIO_MMD_AN,
 529                                               &autoneg_reg);
 530
 531                 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
 532                 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
 533                         break;
 534                 }
 535         }
 536
 537         if (time_out == max_time_out) {
 538                 status = IXGBE_ERR_LINK_SETUP;
 539                 hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out\n");
 540         }
 541
 542         return status;
 543 }
 544
 545 /**
 546  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 547  *  @hw: pointer to hardware structure
 548  *  @speed: new link speed
 549  **/
 550 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 551                                        ixgbe_link_speed speed,
 552                                        bool autoneg_wait_to_complete)
 553 {
 554
 555         /*
 556          * Clear autoneg_advertised and set new values based on input link
 557          * speed.
 558          */
 559         hw->phy.autoneg_advertised = 0;
 560
 561         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 562                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 563
 564         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 565                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 566
 567         if (speed & IXGBE_LINK_SPEED_100_FULL)
 568                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 569
 570         /* Setup link based on the new speed settings */
 571         hw->phy.ops.setup_link(hw);
 572
 573         return 0;
 574 }
 575
 576 /**
 577  * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 578  * @hw: pointer to hardware structure
 579  * @speed: pointer to link speed
 580  * @autoneg: boolean auto-negotiation value
 581  *
 582  * Determines the link capabilities by reading the AUTOC register.
 583  */
 584 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 585                                                ixgbe_link_speed *speed,
 586                                                bool *autoneg)
 587 {
 588         s32 status = IXGBE_ERR_LINK_SETUP;
 589         u16 speed_ability;
 590
 591         *speed = 0;
 592         *autoneg = true;
 593
 594         status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
 595                                       &speed_ability);
 596
 597         if (status == 0) {
 598                 if (speed_ability & MDIO_SPEED_10G)
 599                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 600                 if (speed_ability & MDIO_PMA_SPEED_1000)
 601                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 602                 if (speed_ability & MDIO_PMA_SPEED_100)
 603                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 604         }
 605
 606         return status;
 607 }
 608
 609 /**
 610  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 611  *  @hw: pointer to hardware structure
 612  *
 613  *  Reads the VS1 register to determine if link is up and the current speed for
 614  *  the PHY.
 615  **/
 616 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 617                              bool *link_up)
 618 {
 619         s32 status = 0;
 620         u32 time_out;
 621         u32 max_time_out = 10;
 622         u16 phy_link = 0;
 623         u16 phy_speed = 0;
 624         u16 phy_data = 0;
 625
 626         /* Initialize speed and link to default case */
 627         *link_up = false;
 628         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 629
 630         /*
 631          * Check current speed and link status of the PHY register.
 632          * This is a vendor specific register and may have to
 633          * be changed for other copper PHYs.
 634          */
 635         for (time_out = 0; time_out < max_time_out; time_out++) {
 636                 udelay(10);
 637                 status = hw->phy.ops.read_reg(hw,
 638                                               MDIO_STAT1,
 639                                               MDIO_MMD_VEND1,
 640                                               &phy_data);
 641                 phy_link = phy_data &
 642                             IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 643                 phy_speed = phy_data &
 644                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 645                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 646                         *link_up = true;
 647                         if (phy_speed ==
 648                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 649                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 650                         break;
 651                 }
 652         }
 653
 654         return status;
 655 }
 656
 657 /**
 658  *      ixgbe_setup_phy_link_tnx - Set and restart autoneg
 659  *      @hw: pointer to hardware structure
 660  *
 661  *      Restart autonegotiation and PHY and waits for completion.
 662  **/
 663 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 664 {
 665         s32 status = 0;
 666         u32 time_out;
 667         u32 max_time_out = 10;
 668         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 669         bool autoneg = false;
 670         ixgbe_link_speed speed;
 671
 672         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 673
 674         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 675                 /* Set or unset auto-negotiation 10G advertisement */
 676                 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
 677                                      MDIO_MMD_AN,
 678                                      &autoneg_reg);
 679
 680                 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
 681                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 682                         autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
 683
 684                 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
 685                                       MDIO_MMD_AN,
 686                                       autoneg_reg);
 687         }
 688
 689         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 690                 /* Set or unset auto-negotiation 1G advertisement */
 691                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 692                                      MDIO_MMD_AN,
 693                                      &autoneg_reg);
 694
 695                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 696                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 697                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 698
 699                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 700                                       MDIO_MMD_AN,
 701                                       autoneg_reg);
 702         }
 703
 704         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 705                 /* Set or unset auto-negotiation 100M advertisement */
 706                 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
 707                                      MDIO_MMD_AN,
 708                                      &autoneg_reg);
 709
 710                 autoneg_reg &= ~(ADVERTISE_100FULL |
 711                                  ADVERTISE_100HALF);
 712                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 713                         autoneg_reg |= ADVERTISE_100FULL;
 714
 715                 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
 716                                       MDIO_MMD_AN,
 717                                       autoneg_reg);
 718         }
 719
 720         /* Blocked by MNG FW so don't reset PHY */
 721         if (ixgbe_check_reset_blocked(hw))
 722                 return status;
 723
 724         /* Restart PHY autonegotiation and wait for completion */
 725         hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 726                              MDIO_MMD_AN, &autoneg_reg);
 727
 728         autoneg_reg |= MDIO_AN_CTRL1_RESTART;
 729
 730         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 731                               MDIO_MMD_AN, autoneg_reg);
 732
 733         /* Wait for autonegotiation to finish */
 734         for (time_out = 0; time_out < max_time_out; time_out++) {
 735                 udelay(10);
 736                 /* Restart PHY autonegotiation and wait for completion */
 737                 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
 738                                               MDIO_MMD_AN,
 739                                               &autoneg_reg);
 740
 741                 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
 742                 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE)
 743                         break;
 744         }
 745
 746         if (time_out == max_time_out) {
 747                 status = IXGBE_ERR_LINK_SETUP;
 748                 hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out\n");
 749         }
 750
 751         return status;
 752 }
 753
 754 /**
 755  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 756  *  @hw: pointer to hardware structure
 757  *  @firmware_version: pointer to the PHY Firmware Version
 758  **/
 759 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 760                                        u16 *firmware_version)
 761 {
 762         s32 status = 0;
 763
 764         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 765                                       MDIO_MMD_VEND1,
 766                                       firmware_version);
 767
 768         return status;
 769 }
 770
 771 /**
 772  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
 773  *  @hw: pointer to hardware structure
 774  *  @firmware_version: pointer to the PHY Firmware Version
 775  **/
 776 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 777                                            u16 *firmware_version)
 778 {
 779         s32 status = 0;
 780
 781         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
 782                                       MDIO_MMD_VEND1,
 783                                       firmware_version);
 784
 785         return status;
 786 }
 787
 788 /**
 789  *  ixgbe_reset_phy_nl - Performs a PHY reset
 790  *  @hw: pointer to hardware structure
 791  **/
 792 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 793 {
 794         u16 phy_offset, control, eword, edata, block_crc;
 795         bool end_data = false;
 796         u16 list_offset, data_offset;
 797         u16 phy_data = 0;
 798         s32 ret_val = 0;
 799         u32 i;
 800
 801         /* Blocked by MNG FW so bail */
 802         if (ixgbe_check_reset_blocked(hw))
 803                 goto out;
 804
 805         hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
 806
 807         /* reset the PHY and poll for completion */
 808         hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 809                               (phy_data | MDIO_CTRL1_RESET));
 810
 811         for (i = 0; i < 100; i++) {
 812                 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 813                                      &phy_data);
 814                 if ((phy_data & MDIO_CTRL1_RESET) == 0)
 815                         break;
 816                 usleep_range(10000, 20000);
 817         }
 818
 819         if ((phy_data & MDIO_CTRL1_RESET) != 0) {
 820                 hw_dbg(hw, "PHY reset did not complete.\n");
 821                 ret_val = IXGBE_ERR_PHY;
 822                 goto out;
 823         }
 824
 825         /* Get init offsets */
 826         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 827                                                       &data_offset);
 828         if (ret_val != 0)
 829                 goto out;
 830
 831         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 832         data_offset++;
 833         while (!end_data) {
 834                 /*
 835                  * Read control word from PHY init contents offset
 836                  */
 837                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 838                 if (ret_val)
 839                         goto err_eeprom;
 840                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 841                            IXGBE_CONTROL_SHIFT_NL;
 842                 edata = eword & IXGBE_DATA_MASK_NL;
 843                 switch (control) {
 844                 case IXGBE_DELAY_NL:
 845                         data_offset++;
 846                         hw_dbg(hw, "DELAY: %d MS\n", edata);
 847                         usleep_range(edata * 1000, edata * 2000);
 848                         break;
 849                 case IXGBE_DATA_NL:
 850                         hw_dbg(hw, "DATA:\n");
 851                         data_offset++;
 852                         ret_val = hw->eeprom.ops.read(hw, data_offset++,
 853                                                       &phy_offset);
 854                         if (ret_val)
 855                                 goto err_eeprom;
 856                         for (i = 0; i < edata; i++) {
 857                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
 858                                                               &eword);
 859                                 if (ret_val)
 860                                         goto err_eeprom;
 861                                 hw->phy.ops.write_reg(hw, phy_offset,
 862                                                       MDIO_MMD_PMAPMD, eword);
 863                                 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
 864                                        phy_offset);
 865                                 data_offset++;
 866                                 phy_offset++;
 867                         }
 868                         break;
 869                 case IXGBE_CONTROL_NL:
 870                         data_offset++;
 871                         hw_dbg(hw, "CONTROL:\n");
 872                         if (edata == IXGBE_CONTROL_EOL_NL) {
 873                                 hw_dbg(hw, "EOL\n");
 874                                 end_data = true;
 875                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 876                                 hw_dbg(hw, "SOL\n");
 877                         } else {
 878                                 hw_dbg(hw, "Bad control value\n");
 879                                 ret_val = IXGBE_ERR_PHY;
 880                                 goto out;
 881                         }
 882                         break;
 883                 default:
 884                         hw_dbg(hw, "Bad control type\n");
 885                         ret_val = IXGBE_ERR_PHY;
 886                         goto out;
 887                 }
 888         }
 889
 890 out:
 891         return ret_val;
 892
 893 err_eeprom:
 894         hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
 895         return IXGBE_ERR_PHY;
 896 }
 897
 898 /**
 899  *  ixgbe_identify_module_generic - Identifies module type
 900  *  @hw: pointer to hardware structure
 901  *
 902  *  Determines HW type and calls appropriate function.
 903  **/
 904 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
 905 {
 906         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
 907
 908         switch (hw->mac.ops.get_media_type(hw)) {
 909         case ixgbe_media_type_fiber:
 910                 status = ixgbe_identify_sfp_module_generic(hw);
 911                 break;
 912         case ixgbe_media_type_fiber_qsfp:
 913                 status = ixgbe_identify_qsfp_module_generic(hw);
 914                 break;
 915         default:
 916                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 917                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 918                 break;
 919         }
 920
 921         return status;
 922 }
 923
 924 /**
 925  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
 926  *  @hw: pointer to hardware structure
 927 *
 928  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
 929  **/
 930 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
 931 {
 932         struct ixgbe_adapter *adapter = hw->back;
 933         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 934         u32 vendor_oui = 0;
 935         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
 936         u8 identifier = 0;
 937         u8 comp_codes_1g = 0;
 938         u8 comp_codes_10g = 0;
 939         u8 oui_bytes[3] = {0, 0, 0};
 940         u8 cable_tech = 0;
 941         u8 cable_spec = 0;
 942         u16 enforce_sfp = 0;
 943
 944         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
 945                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 946                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 947                 goto out;
 948         }
 949
 950         status = hw->phy.ops.read_i2c_eeprom(hw,
 951                                              IXGBE_SFF_IDENTIFIER,
 952                                              &identifier);
 953
 954         if (status != 0)
 955                 goto err_read_i2c_eeprom;
 956
 957         /* LAN ID is needed for sfp_type determination */
 958         hw->mac.ops.set_lan_id(hw);
 959
 960         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
 961                 hw->phy.type = ixgbe_phy_sfp_unsupported;
 962                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
 963         } else {
 964                 status = hw->phy.ops.read_i2c_eeprom(hw,
 965                                                      IXGBE_SFF_1GBE_COMP_CODES,
 966                                                      &comp_codes_1g);
 967
 968                 if (status != 0)
 969                         goto err_read_i2c_eeprom;
 970
 971                 status = hw->phy.ops.read_i2c_eeprom(hw,
 972                                                      IXGBE_SFF_10GBE_COMP_CODES,
 973                                                      &comp_codes_10g);
 974
 975                 if (status != 0)
 976                         goto err_read_i2c_eeprom;
 977                 status = hw->phy.ops.read_i2c_eeprom(hw,
 978                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
 979                                                      &cable_tech);
 980
 981                 if (status != 0)
 982                         goto err_read_i2c_eeprom;
 983
 984                  /* ID Module
 985                   * =========
 986                   * 0   SFP_DA_CU
 987                   * 1   SFP_SR
 988                   * 2   SFP_LR
 989                   * 3   SFP_DA_CORE0 - 82599-specific
 990                   * 4   SFP_DA_CORE1 - 82599-specific
 991                   * 5   SFP_SR/LR_CORE0 - 82599-specific
 992                   * 6   SFP_SR/LR_CORE1 - 82599-specific
 993                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
 994                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
 995                   * 9   SFP_1g_cu_CORE0 - 82599-specific
 996                   * 10  SFP_1g_cu_CORE1 - 82599-specific
 997                   * 11  SFP_1g_sx_CORE0 - 82599-specific
 998                   * 12  SFP_1g_sx_CORE1 - 82599-specific
 999                   */
1000                 if (hw->mac.type == ixgbe_mac_82598EB) {
1001                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1002                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1003                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1004                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1005                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1006                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1007                         else
1008                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1009                 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1010                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1011                                 if (hw->bus.lan_id == 0)
1012                                         hw->phy.sfp_type =
1013                                                      ixgbe_sfp_type_da_cu_core0;
1014                                 else
1015                                         hw->phy.sfp_type =
1016                                                      ixgbe_sfp_type_da_cu_core1;
1017                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1018                                 hw->phy.ops.read_i2c_eeprom(
1019                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1020                                                 &cable_spec);
1021                                 if (cable_spec &
1022                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1023                                         if (hw->bus.lan_id == 0)
1024                                                 hw->phy.sfp_type =
1025                                                 ixgbe_sfp_type_da_act_lmt_core0;
1026                                         else
1027                                                 hw->phy.sfp_type =
1028                                                 ixgbe_sfp_type_da_act_lmt_core1;
1029                                 } else {
1030                                         hw->phy.sfp_type =
1031                                                         ixgbe_sfp_type_unknown;
1032                                 }
1033                         } else if (comp_codes_10g &
1034                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1035                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1036                                 if (hw->bus.lan_id == 0)
1037                                         hw->phy.sfp_type =
1038                                                       ixgbe_sfp_type_srlr_core0;
1039                                 else
1040                                         hw->phy.sfp_type =
1041                                                       ixgbe_sfp_type_srlr_core1;
1042                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1043                                 if (hw->bus.lan_id == 0)
1044                                         hw->phy.sfp_type =
1045                                                 ixgbe_sfp_type_1g_cu_core0;
1046                                 else
1047                                         hw->phy.sfp_type =
1048                                                 ixgbe_sfp_type_1g_cu_core1;
1049                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1050                                 if (hw->bus.lan_id == 0)
1051                                         hw->phy.sfp_type =
1052                                                 ixgbe_sfp_type_1g_sx_core0;
1053                                 else
1054                                         hw->phy.sfp_type =
1055                                                 ixgbe_sfp_type_1g_sx_core1;
1056                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1057                                 if (hw->bus.lan_id == 0)
1058                                         hw->phy.sfp_type =
1059                                                 ixgbe_sfp_type_1g_lx_core0;
1060                                 else
1061                                         hw->phy.sfp_type =
1062                                                 ixgbe_sfp_type_1g_lx_core1;
1063                         } else {
1064                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1065                         }
1066                 }
1067
1068                 if (hw->phy.sfp_type != stored_sfp_type)
1069                         hw->phy.sfp_setup_needed = true;
1070
1071                 /* Determine if the SFP+ PHY is dual speed or not. */
1072                 hw->phy.multispeed_fiber = false;
1073                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1074                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1075                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1076                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1077                         hw->phy.multispeed_fiber = true;
1078
1079                 /* Determine PHY vendor */
1080                 if (hw->phy.type != ixgbe_phy_nl) {
1081                         hw->phy.id = identifier;
1082                         status = hw->phy.ops.read_i2c_eeprom(hw,
1083                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1084                                                     &oui_bytes[0]);
1085
1086                         if (status != 0)
1087                                 goto err_read_i2c_eeprom;
1088
1089                         status = hw->phy.ops.read_i2c_eeprom(hw,
1090                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1091                                                     &oui_bytes[1]);
1092
1093                         if (status != 0)
1094                                 goto err_read_i2c_eeprom;
1095
1096                         status = hw->phy.ops.read_i2c_eeprom(hw,
1097                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1098                                                     &oui_bytes[2]);
1099
1100                         if (status != 0)
1101                                 goto err_read_i2c_eeprom;
1102
1103                         vendor_oui =
1104                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1105                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1106                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1107
1108                         switch (vendor_oui) {
1109                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1110                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1111                                         hw->phy.type =
1112                                                     ixgbe_phy_sfp_passive_tyco;
1113                                 break;
1114                         case IXGBE_SFF_VENDOR_OUI_FTL:
1115                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1116                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1117                                 else
1118                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1119                                 break;
1120                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1121                                 hw->phy.type = ixgbe_phy_sfp_avago;
1122                                 break;
1123                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1124                                 hw->phy.type = ixgbe_phy_sfp_intel;
1125                                 break;
1126                         default:
1127                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1128                                         hw->phy.type =
1129                                                  ixgbe_phy_sfp_passive_unknown;
1130                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1131                                         hw->phy.type =
1132                                                 ixgbe_phy_sfp_active_unknown;
1133                                 else
1134                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1135                                 break;
1136                         }
1137                 }
1138
1139                 /* Allow any DA cable vendor */
1140                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1141                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1142                         status = 0;
1143                         goto out;
1144                 }
1145
1146                 /* Verify supported 1G SFP modules */
1147                 if (comp_codes_10g == 0 &&
1148                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1149                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1150                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1151                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1152                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1153                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1154                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1155                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1156                         goto out;
1157                 }
1158
1159                 /* Anything else 82598-based is supported */
1160                 if (hw->mac.type == ixgbe_mac_82598EB) {
1161                         status = 0;
1162                         goto out;
1163                 }
1164
1165                 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1166                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1167                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1168                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1169                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1170                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1171                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1172                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1173                         /* Make sure we're a supported PHY type */
1174                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1175                                 status = 0;
1176                         } else {
1177                                 if (hw->allow_unsupported_sfp) {
1178                                         e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics.  Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter.  Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1179                                         status = 0;
1180                                 } else {
1181                                         hw_dbg(hw,
1182                                                "SFP+ module not supported\n");
1183                                         hw->phy.type =
1184                                                 ixgbe_phy_sfp_unsupported;
1185                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1186                                 }
1187                         }
1188                 } else {
1189                         status = 0;
1190                 }
1191         }
1192
1193 out:
1194         return status;
1195
1196 err_read_i2c_eeprom:
1197         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1198         if (hw->phy.type != ixgbe_phy_nl) {
1199                 hw->phy.id = 0;
1200                 hw->phy.type = ixgbe_phy_unknown;
1201         }
1202         return IXGBE_ERR_SFP_NOT_PRESENT;
1203 }
1204
1205 /**
1206  * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1207  * @hw: pointer to hardware structure
1208  *
1209  * Searches for and identifies the QSFP module and assigns appropriate PHY type
1210  **/
1211 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1212 {
1213         struct ixgbe_adapter *adapter = hw->back;
1214         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1215         u32 vendor_oui = 0;
1216         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1217         u8 identifier = 0;
1218         u8 comp_codes_1g = 0;
1219         u8 comp_codes_10g = 0;
1220         u8 oui_bytes[3] = {0, 0, 0};
1221         u16 enforce_sfp = 0;
1222         u8 connector = 0;
1223         u8 cable_length = 0;
1224         u8 device_tech = 0;
1225         bool active_cable = false;
1226
1227         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1228                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1229                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1230                 goto out;
1231         }
1232
1233         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1234                                              &identifier);
1235
1236         if (status != 0)
1237                 goto err_read_i2c_eeprom;
1238
1239         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1240                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1241                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1242                 goto out;
1243         }
1244
1245         hw->phy.id = identifier;
1246
1247         /* LAN ID is needed for sfp_type determination */
1248         hw->mac.ops.set_lan_id(hw);
1249
1250         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1251                                              &comp_codes_10g);
1252
1253         if (status != 0)
1254                 goto err_read_i2c_eeprom;
1255
1256         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1257                                              &comp_codes_1g);
1258
1259         if (status != 0)
1260                 goto err_read_i2c_eeprom;
1261
1262         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1263                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1264                 if (hw->bus.lan_id == 0)
1265                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1266                 else
1267                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1268         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1269                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1270                 if (hw->bus.lan_id == 0)
1271                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1272                 else
1273                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1274         } else {
1275                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1276                         active_cable = true;
1277
1278                 if (!active_cable) {
1279                         /* check for active DA cables that pre-date
1280                          * SFF-8436 v3.6
1281                          */
1282                         hw->phy.ops.read_i2c_eeprom(hw,
1283                                         IXGBE_SFF_QSFP_CONNECTOR,
1284                                         &connector);
1285
1286                         hw->phy.ops.read_i2c_eeprom(hw,
1287                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1288                                         &cable_length);
1289
1290                         hw->phy.ops.read_i2c_eeprom(hw,
1291                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1292                                         &device_tech);
1293
1294                         if ((connector ==
1295                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1296                             (cable_length > 0) &&
1297                             ((device_tech >> 4) ==
1298                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1299                                 active_cable = true;
1300                 }
1301
1302                 if (active_cable) {
1303                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1304                         if (hw->bus.lan_id == 0)
1305                                 hw->phy.sfp_type =
1306                                                 ixgbe_sfp_type_da_act_lmt_core0;
1307                         else
1308                                 hw->phy.sfp_type =
1309                                                 ixgbe_sfp_type_da_act_lmt_core1;
1310                 } else {
1311                         /* unsupported module type */
1312                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1313                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1314                         goto out;
1315                 }
1316         }
1317
1318         if (hw->phy.sfp_type != stored_sfp_type)
1319                 hw->phy.sfp_setup_needed = true;
1320
1321         /* Determine if the QSFP+ PHY is dual speed or not. */
1322         hw->phy.multispeed_fiber = false;
1323         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1324              (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1325             ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1326              (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1327                 hw->phy.multispeed_fiber = true;
1328
1329         /* Determine PHY vendor for optical modules */
1330         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1331                               IXGBE_SFF_10GBASELR_CAPABLE)) {
1332                 status = hw->phy.ops.read_i2c_eeprom(hw,
1333                                         IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1334                                         &oui_bytes[0]);
1335
1336                 if (status != 0)
1337                         goto err_read_i2c_eeprom;
1338
1339                 status = hw->phy.ops.read_i2c_eeprom(hw,
1340                                         IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1341                                         &oui_bytes[1]);
1342
1343                 if (status != 0)
1344                         goto err_read_i2c_eeprom;
1345
1346                 status = hw->phy.ops.read_i2c_eeprom(hw,
1347                                         IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1348                                         &oui_bytes[2]);
1349
1350                 if (status != 0)
1351                         goto err_read_i2c_eeprom;
1352
1353                 vendor_oui =
1354                         ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1355                          (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1356                          (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1357
1358                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1359                         hw->phy.type = ixgbe_phy_qsfp_intel;
1360                 else
1361                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1362
1363                 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1364                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1365                         /* Make sure we're a supported PHY type */
1366                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1367                                 status = 0;
1368                         } else {
1369                                 if (hw->allow_unsupported_sfp == true) {
1370                                         e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1371                                         status = 0;
1372                                 } else {
1373                                         hw_dbg(hw,
1374                                                "QSFP module not supported\n");
1375                                         hw->phy.type =
1376                                                 ixgbe_phy_sfp_unsupported;
1377                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1378                                 }
1379                         }
1380                 } else {
1381                         status = 0;
1382                 }
1383         }
1384
1385 out:
1386         return status;
1387
1388 err_read_i2c_eeprom:
1389         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1390         hw->phy.id = 0;
1391         hw->phy.type = ixgbe_phy_unknown;
1392
1393         return IXGBE_ERR_SFP_NOT_PRESENT;
1394 }
1395
1396 /**
1397  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1398  *  @hw: pointer to hardware structure
1399  *  @list_offset: offset to the SFP ID list
1400  *  @data_offset: offset to the SFP data block
1401  *
1402  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1403  *  so it returns the offsets to the phy init sequence block.
1404  **/
1405 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1406                                         u16 *list_offset,
1407                                         u16 *data_offset)
1408 {
1409         u16 sfp_id;
1410         u16 sfp_type = hw->phy.sfp_type;
1411
1412         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1413                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1414
1415         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1416                 return IXGBE_ERR_SFP_NOT_PRESENT;
1417
1418         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1419             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1420                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1421
1422         /*
1423          * Limiting active cables and 1G Phys must be initialized as
1424          * SR modules
1425          */
1426         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1427             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1428             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1429             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1430                 sfp_type = ixgbe_sfp_type_srlr_core0;
1431         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1432                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1433                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1434                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1435                 sfp_type = ixgbe_sfp_type_srlr_core1;
1436
1437         /* Read offset to PHY init contents */
1438         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1439                 hw_err(hw, "eeprom read at %d failed\n",
1440                        IXGBE_PHY_INIT_OFFSET_NL);
1441                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1442         }
1443
1444         if ((!*list_offset) || (*list_offset == 0xFFFF))
1445                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1446
1447         /* Shift offset to first ID word */
1448         (*list_offset)++;
1449
1450         /*
1451          * Find the matching SFP ID in the EEPROM
1452          * and program the init sequence
1453          */
1454         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1455                 goto err_phy;
1456
1457         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1458                 if (sfp_id == sfp_type) {
1459                         (*list_offset)++;
1460                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1461                                 goto err_phy;
1462                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1463                                 hw_dbg(hw, "SFP+ module not supported\n");
1464                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1465                         } else {
1466                                 break;
1467                         }
1468                 } else {
1469                         (*list_offset) += 2;
1470                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1471                                 goto err_phy;
1472                 }
1473         }
1474
1475         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1476                 hw_dbg(hw, "No matching SFP+ module found\n");
1477                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1478         }
1479
1480         return 0;
1481
1482 err_phy:
1483         hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
1484         return IXGBE_ERR_PHY;
1485 }
1486
1487 /**
1488  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1489  *  @hw: pointer to hardware structure
1490  *  @byte_offset: EEPROM byte offset to read
1491  *  @eeprom_data: value read
1492  *
1493  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1494  **/
1495 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1496                                   u8 *eeprom_data)
1497 {
1498         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1499                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1500                                          eeprom_data);
1501 }
1502
1503 /**
1504  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1505  *  @hw: pointer to hardware structure
1506  *  @byte_offset: byte offset at address 0xA2
1507  *  @eeprom_data: value read
1508  *
1509  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1510  **/
1511 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1512                                    u8 *sff8472_data)
1513 {
1514         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1515                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1516                                          sff8472_data);
1517 }
1518
1519 /**
1520  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1521  *  @hw: pointer to hardware structure
1522  *  @byte_offset: EEPROM byte offset to write
1523  *  @eeprom_data: value to write
1524  *
1525  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1526  **/
1527 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1528                                    u8 eeprom_data)
1529 {
1530         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1531                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1532                                           eeprom_data);
1533 }
1534
1535 /**
1536  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1537  *  @hw: pointer to hardware structure
1538  *  @byte_offset: byte offset to read
1539  *  @data: value read
1540  *
1541  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1542  *  a specified device address.
1543  **/
1544 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1545                                 u8 dev_addr, u8 *data)
1546 {
1547         s32 status = 0;
1548         u32 max_retry = 10;
1549         u32 retry = 0;
1550         u16 swfw_mask = 0;
1551         bool nack = true;
1552         *data = 0;
1553
1554         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1555                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1556         else
1557                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1558
1559         do {
1560                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
1561                         status = IXGBE_ERR_SWFW_SYNC;
1562                         goto read_byte_out;
1563                 }
1564
1565                 ixgbe_i2c_start(hw);
1566
1567                 /* Device Address and write indication */
1568                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1569                 if (status != 0)
1570                         goto fail;
1571
1572                 status = ixgbe_get_i2c_ack(hw);
1573                 if (status != 0)
1574                         goto fail;
1575
1576                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1577                 if (status != 0)
1578                         goto fail;
1579
1580                 status = ixgbe_get_i2c_ack(hw);
1581                 if (status != 0)
1582                         goto fail;
1583
1584                 ixgbe_i2c_start(hw);
1585
1586                 /* Device Address and read indication */
1587                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1588                 if (status != 0)
1589                         goto fail;
1590
1591                 status = ixgbe_get_i2c_ack(hw);
1592                 if (status != 0)
1593                         goto fail;
1594
1595                 status = ixgbe_clock_in_i2c_byte(hw, data);
1596                 if (status != 0)
1597                         goto fail;
1598
1599                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1600                 if (status != 0)
1601                         goto fail;
1602
1603                 ixgbe_i2c_stop(hw);
1604                 break;
1605
1606 fail:
1607                 ixgbe_i2c_bus_clear(hw);
1608                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1609                 msleep(100);
1610                 retry++;
1611                 if (retry < max_retry)
1612                         hw_dbg(hw, "I2C byte read error - Retrying.\n");
1613                 else
1614                         hw_dbg(hw, "I2C byte read error.\n");
1615
1616         } while (retry < max_retry);
1617
1618         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1619
1620 read_byte_out:
1621         return status;
1622 }
1623
1624 /**
1625  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1626  *  @hw: pointer to hardware structure
1627  *  @byte_offset: byte offset to write
1628  *  @data: value to write
1629  *
1630  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1631  *  a specified device address.
1632  **/
1633 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1634                                  u8 dev_addr, u8 data)
1635 {
1636         s32 status = 0;
1637         u32 max_retry = 1;
1638         u32 retry = 0;
1639         u16 swfw_mask = 0;
1640
1641         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1642                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1643         else
1644                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1645
1646         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
1647                 status = IXGBE_ERR_SWFW_SYNC;
1648                 goto write_byte_out;
1649         }
1650
1651         do {
1652                 ixgbe_i2c_start(hw);
1653
1654                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1655                 if (status != 0)
1656                         goto fail;
1657
1658                 status = ixgbe_get_i2c_ack(hw);
1659                 if (status != 0)
1660                         goto fail;
1661
1662                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1663                 if (status != 0)
1664                         goto fail;
1665
1666                 status = ixgbe_get_i2c_ack(hw);
1667                 if (status != 0)
1668                         goto fail;
1669
1670                 status = ixgbe_clock_out_i2c_byte(hw, data);
1671                 if (status != 0)
1672                         goto fail;
1673
1674                 status = ixgbe_get_i2c_ack(hw);
1675                 if (status != 0)
1676                         goto fail;
1677
1678                 ixgbe_i2c_stop(hw);
1679                 break;
1680
1681 fail:
1682                 ixgbe_i2c_bus_clear(hw);
1683                 retry++;
1684                 if (retry < max_retry)
1685                         hw_dbg(hw, "I2C byte write error - Retrying.\n");
1686                 else
1687                         hw_dbg(hw, "I2C byte write error.\n");
1688         } while (retry < max_retry);
1689
1690         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1691
1692 write_byte_out:
1693         return status;
1694 }
1695
1696 /**
1697  *  ixgbe_i2c_start - Sets I2C start condition
1698  *  @hw: pointer to hardware structure
1699  *
1700  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1701  **/
1702 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1703 {
1704         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1705
1706         /* Start condition must begin with data and clock high */
1707         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1708         ixgbe_raise_i2c_clk(hw, &i2cctl);
1709
1710         /* Setup time for start condition (4.7us) */
1711         udelay(IXGBE_I2C_T_SU_STA);
1712
1713         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1714
1715         /* Hold time for start condition (4us) */
1716         udelay(IXGBE_I2C_T_HD_STA);
1717
1718         ixgbe_lower_i2c_clk(hw, &i2cctl);
1719
1720         /* Minimum low period of clock is 4.7 us */
1721         udelay(IXGBE_I2C_T_LOW);
1722
1723 }
1724
1725 /**
1726  *  ixgbe_i2c_stop - Sets I2C stop condition
1727  *  @hw: pointer to hardware structure
1728  *
1729  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1730  **/
1731 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1732 {
1733         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1734
1735         /* Stop condition must begin with data low and clock high */
1736         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1737         ixgbe_raise_i2c_clk(hw, &i2cctl);
1738
1739         /* Setup time for stop condition (4us) */
1740         udelay(IXGBE_I2C_T_SU_STO);
1741
1742         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1743
1744         /* bus free time between stop and start (4.7us)*/
1745         udelay(IXGBE_I2C_T_BUF);
1746 }
1747
1748 /**
1749  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1750  *  @hw: pointer to hardware structure
1751  *  @data: data byte to clock in
1752  *
1753  *  Clocks in one byte data via I2C data/clock
1754  **/
1755 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1756 {
1757         s32 i;
1758         bool bit = false;
1759
1760         for (i = 7; i >= 0; i--) {
1761                 ixgbe_clock_in_i2c_bit(hw, &bit);
1762                 *data |= bit << i;
1763         }
1764
1765         return 0;
1766 }
1767
1768 /**
1769  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1770  *  @hw: pointer to hardware structure
1771  *  @data: data byte clocked out
1772  *
1773  *  Clocks out one byte data via I2C data/clock
1774  **/
1775 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1776 {
1777         s32 status = 0;
1778         s32 i;
1779         u32 i2cctl;
1780         bool bit = false;
1781
1782         for (i = 7; i >= 0; i--) {
1783                 bit = (data >> i) & 0x1;
1784                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1785
1786                 if (status != 0)
1787                         break;
1788         }
1789
1790         /* Release SDA line (set high) */
1791         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1792         i2cctl |= IXGBE_I2C_DATA_OUT;
1793         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1794         IXGBE_WRITE_FLUSH(hw);
1795
1796         return status;
1797 }
1798
1799 /**
1800  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1801  *  @hw: pointer to hardware structure
1802  *
1803  *  Clocks in/out one bit via I2C data/clock
1804  **/
1805 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1806 {
1807         s32 status = 0;
1808         u32 i = 0;
1809         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1810         u32 timeout = 10;
1811         bool ack = true;
1812
1813         ixgbe_raise_i2c_clk(hw, &i2cctl);
1814
1815
1816         /* Minimum high period of clock is 4us */
1817         udelay(IXGBE_I2C_T_HIGH);
1818
1819         /* Poll for ACK.  Note that ACK in I2C spec is
1820          * transition from 1 to 0 */
1821         for (i = 0; i < timeout; i++) {
1822                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1823                 ack = ixgbe_get_i2c_data(&i2cctl);
1824
1825                 udelay(1);
1826                 if (ack == 0)
1827                         break;
1828         }
1829
1830         if (ack == 1) {
1831                 hw_dbg(hw, "I2C ack was not received.\n");
1832                 status = IXGBE_ERR_I2C;
1833         }
1834
1835         ixgbe_lower_i2c_clk(hw, &i2cctl);
1836
1837         /* Minimum low period of clock is 4.7 us */
1838         udelay(IXGBE_I2C_T_LOW);
1839
1840         return status;
1841 }
1842
1843 /**
1844  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1845  *  @hw: pointer to hardware structure
1846  *  @data: read data value
1847  *
1848  *  Clocks in one bit via I2C data/clock
1849  **/
1850 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1851 {
1852         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1853
1854         ixgbe_raise_i2c_clk(hw, &i2cctl);
1855
1856         /* Minimum high period of clock is 4us */
1857         udelay(IXGBE_I2C_T_HIGH);
1858
1859         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1860         *data = ixgbe_get_i2c_data(&i2cctl);
1861
1862         ixgbe_lower_i2c_clk(hw, &i2cctl);
1863
1864         /* Minimum low period of clock is 4.7 us */
1865         udelay(IXGBE_I2C_T_LOW);
1866
1867         return 0;
1868 }
1869
1870 /**
1871  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1872  *  @hw: pointer to hardware structure
1873  *  @data: data value to write
1874  *
1875  *  Clocks out one bit via I2C data/clock
1876  **/
1877 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1878 {
1879         s32 status;
1880         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1881
1882         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1883         if (status == 0) {
1884                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1885
1886                 /* Minimum high period of clock is 4us */
1887                 udelay(IXGBE_I2C_T_HIGH);
1888
1889                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1890
1891                 /* Minimum low period of clock is 4.7 us.
1892                  * This also takes care of the data hold time.
1893                  */
1894                 udelay(IXGBE_I2C_T_LOW);
1895         } else {
1896                 status = IXGBE_ERR_I2C;
1897                 hw_dbg(hw, "I2C data was not set to %X\n", data);
1898         }
1899
1900         return status;
1901 }
1902 /**
1903  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1904  *  @hw: pointer to hardware structure
1905  *  @i2cctl: Current value of I2CCTL register
1906  *
1907  *  Raises the I2C clock line '0'->'1'
1908  **/
1909 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1910 {
1911         u32 i = 0;
1912         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1913         u32 i2cctl_r = 0;
1914
1915         for (i = 0; i < timeout; i++) {
1916                 *i2cctl |= IXGBE_I2C_CLK_OUT;
1917                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1918                 IXGBE_WRITE_FLUSH(hw);
1919                 /* SCL rise time (1000ns) */
1920                 udelay(IXGBE_I2C_T_RISE);
1921
1922                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1923                 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1924                         break;
1925         }
1926 }
1927
1928 /**
1929  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1930  *  @hw: pointer to hardware structure
1931  *  @i2cctl: Current value of I2CCTL register
1932  *
1933  *  Lowers the I2C clock line '1'->'0'
1934  **/
1935 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1936 {
1937
1938         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1939
1940         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1941         IXGBE_WRITE_FLUSH(hw);
1942
1943         /* SCL fall time (300ns) */
1944         udelay(IXGBE_I2C_T_FALL);
1945 }
1946
1947 /**
1948  *  ixgbe_set_i2c_data - Sets the I2C data bit
1949  *  @hw: pointer to hardware structure
1950  *  @i2cctl: Current value of I2CCTL register
1951  *  @data: I2C data value (0 or 1) to set
1952  *
1953  *  Sets the I2C data bit
1954  **/
1955 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1956 {
1957         s32 status = 0;
1958
1959         if (data)
1960                 *i2cctl |= IXGBE_I2C_DATA_OUT;
1961         else
1962                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1963
1964         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1965         IXGBE_WRITE_FLUSH(hw);
1966
1967         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1968         udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1969
1970         /* Verify data was set correctly */
1971         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1972         if (data != ixgbe_get_i2c_data(i2cctl)) {
1973                 status = IXGBE_ERR_I2C;
1974                 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1975         }
1976
1977         return status;
1978 }
1979
1980 /**
1981  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1982  *  @hw: pointer to hardware structure
1983  *  @i2cctl: Current value of I2CCTL register
1984  *
1985  *  Returns the I2C data bit value
1986  **/
1987 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1988 {
1989         bool data;
1990
1991         if (*i2cctl & IXGBE_I2C_DATA_IN)
1992                 data = true;
1993         else
1994                 data = false;
1995
1996         return data;
1997 }
1998
1999 /**
2000  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2001  *  @hw: pointer to hardware structure
2002  *
2003  *  Clears the I2C bus by sending nine clock pulses.
2004  *  Used when data line is stuck low.
2005  **/
2006 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2007 {
2008         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2009         u32 i;
2010
2011         ixgbe_i2c_start(hw);
2012
2013         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2014
2015         for (i = 0; i < 9; i++) {
2016                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2017
2018                 /* Min high period of clock is 4us */
2019                 udelay(IXGBE_I2C_T_HIGH);
2020
2021                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2022
2023                 /* Min low period of clock is 4.7us*/
2024                 udelay(IXGBE_I2C_T_LOW);
2025         }
2026
2027         ixgbe_i2c_start(hw);
2028
2029         /* Put the i2c bus back to default state */
2030         ixgbe_i2c_stop(hw);
2031 }
2032
2033 /**
2034  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2035  *  @hw: pointer to hardware structure
2036  *
2037  *  Checks if the LASI temp alarm status was triggered due to overtemp
2038  **/
2039 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2040 {
2041         s32 status = 0;
2042         u16 phy_data = 0;
2043
2044         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2045                 goto out;
2046
2047         /* Check that the LASI temp alarm status was triggered */
2048         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2049                              MDIO_MMD_PMAPMD, &phy_data);
2050
2051         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2052                 goto out;
2053
2054         status = IXGBE_ERR_OVERTEMP;
2055 out:
2056         return status;
2057 }