1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
32 #include "ixgbe_common.h"
33 #include "ixgbe_phy.h"
35 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
36 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
37 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
38 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
39 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
40 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
41 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
42 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
43 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
45 static bool ixgbe_get_i2c_data(u32 *i2cctl);
46 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
47 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
48 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
51 * ixgbe_identify_phy_generic - Get physical layer module
52 * @hw: pointer to hardware structure
54 * Determines the physical layer module found on the current adapter.
56 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
58 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
62 if (hw->phy.type == ixgbe_phy_unknown) {
63 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
64 hw->phy.mdio.prtad = phy_addr;
65 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
68 ixgbe_get_phy_type_from_id(hw->phy.id);
70 if (hw->phy.type == ixgbe_phy_unknown) {
71 hw->phy.ops.read_reg(hw,
76 (MDIO_PMA_EXTABLE_10GBT |
77 MDIO_PMA_EXTABLE_1000BT))
89 /* clear value if nothing found */
91 hw->phy.mdio.prtad = 0;
100 * ixgbe_get_phy_id - Get the phy type
101 * @hw: pointer to hardware structure
104 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
110 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
114 hw->phy.id = (u32)(phy_id_high << 16);
115 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
117 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
118 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
124 * ixgbe_get_phy_type_from_id - Get the phy type
125 * @hw: pointer to hardware structure
128 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
130 enum ixgbe_phy_type phy_type;
134 phy_type = ixgbe_phy_tn;
137 phy_type = ixgbe_phy_aq;
140 phy_type = ixgbe_phy_qt;
143 phy_type = ixgbe_phy_nl;
146 phy_type = ixgbe_phy_unknown;
154 * ixgbe_reset_phy_generic - Performs a PHY reset
155 * @hw: pointer to hardware structure
157 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
163 if (hw->phy.type == ixgbe_phy_unknown)
164 status = ixgbe_identify_phy_generic(hw);
166 if (status != 0 || hw->phy.type == ixgbe_phy_none)
169 /* Don't reset PHY if it's shut down due to overtemp. */
170 if (!hw->phy.reset_if_overtemp &&
171 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
175 * Perform soft PHY reset to the PHY_XS.
176 * This will cause a soft reset to the PHY
178 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
183 * Poll for reset bit to self-clear indicating reset is complete.
184 * Some PHYs could take up to 3 seconds to complete and need about
185 * 1.7 usec delay after the reset is complete.
187 for (i = 0; i < 30; i++) {
189 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
190 MDIO_MMD_PHYXS, &ctrl);
191 if (!(ctrl & MDIO_CTRL1_RESET)) {
197 if (ctrl & MDIO_CTRL1_RESET) {
198 status = IXGBE_ERR_RESET_FAILED;
199 hw_dbg(hw, "PHY reset polling failed to complete.\n");
207 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
209 * @hw: pointer to hardware structure
210 * @reg_addr: 32 bit address of PHY register to read
211 * @phy_data: Pointer to read data from PHY register
213 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
216 u32 i, data, command;
218 /* Setup and write the address cycle command */
219 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
220 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
221 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
222 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
224 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
226 /* Check every 10 usec to see if the address cycle completed.
227 * The MDI Command bit will clear when the operation is
230 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
233 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
234 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
239 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
240 hw_dbg(hw, "PHY address command did not complete.\n");
241 return IXGBE_ERR_PHY;
244 /* Address cycle complete, setup and write the read
247 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
248 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
249 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
250 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
252 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
254 /* Check every 10 usec to see if the address cycle
255 * completed. The MDI Command bit will clear when the
256 * operation is complete
258 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
261 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
262 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
266 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
267 hw_dbg(hw, "PHY read command didn't complete\n");
268 return IXGBE_ERR_PHY;
271 /* Read operation is complete. Get the data
274 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
275 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
276 *phy_data = (u16)(data);
282 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
283 * using the SWFW lock - this function is needed in most cases
284 * @hw: pointer to hardware structure
285 * @reg_addr: 32 bit address of PHY register to read
286 * @phy_data: Pointer to read data from PHY register
288 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
289 u32 device_type, u16 *phy_data)
294 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
295 gssr = IXGBE_GSSR_PHY1_SM;
297 gssr = IXGBE_GSSR_PHY0_SM;
299 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
300 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
302 hw->mac.ops.release_swfw_sync(hw, gssr);
304 status = IXGBE_ERR_SWFW_SYNC;
311 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
313 * @hw: pointer to hardware structure
314 * @reg_addr: 32 bit PHY register to write
315 * @device_type: 5 bit device type
316 * @phy_data: Data to write to the PHY register
318 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
319 u32 device_type, u16 phy_data)
323 /* Put the data in the MDI single read and write data register*/
324 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
326 /* Setup and write the address cycle command */
327 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
328 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
329 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
330 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
332 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
335 * Check every 10 usec to see if the address cycle completed.
336 * The MDI Command bit will clear when the operation is
339 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
342 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
343 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
347 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
348 hw_dbg(hw, "PHY address cmd didn't complete\n");
349 return IXGBE_ERR_PHY;
353 * Address cycle complete, setup and write the write
356 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
357 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
358 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
359 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
361 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
363 /* Check every 10 usec to see if the address cycle
364 * completed. The MDI Command bit will clear when the
365 * operation is complete
367 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
370 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
371 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
375 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
376 hw_dbg(hw, "PHY write cmd didn't complete\n");
377 return IXGBE_ERR_PHY;
384 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
385 * using SWFW lock- this function is needed in most cases
386 * @hw: pointer to hardware structure
387 * @reg_addr: 32 bit PHY register to write
388 * @device_type: 5 bit device type
389 * @phy_data: Data to write to the PHY register
391 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
392 u32 device_type, u16 phy_data)
397 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
398 gssr = IXGBE_GSSR_PHY1_SM;
400 gssr = IXGBE_GSSR_PHY0_SM;
402 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
403 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
405 hw->mac.ops.release_swfw_sync(hw, gssr);
407 status = IXGBE_ERR_SWFW_SYNC;
414 * ixgbe_setup_phy_link_generic - Set and restart autoneg
415 * @hw: pointer to hardware structure
417 * Restart autonegotiation and PHY and waits for completion.
419 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
423 u32 max_time_out = 10;
424 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
425 bool autoneg = false;
426 ixgbe_link_speed speed;
428 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
430 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
431 /* Set or unset auto-negotiation 10G advertisement */
432 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
436 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
437 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
438 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
440 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
445 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
446 /* Set or unset auto-negotiation 1G advertisement */
447 hw->phy.ops.read_reg(hw,
448 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
452 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
453 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
454 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
456 hw->phy.ops.write_reg(hw,
457 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
462 if (speed & IXGBE_LINK_SPEED_100_FULL) {
463 /* Set or unset auto-negotiation 100M advertisement */
464 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
468 autoneg_reg &= ~(ADVERTISE_100FULL |
470 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
471 autoneg_reg |= ADVERTISE_100FULL;
473 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
478 /* Restart PHY autonegotiation and wait for completion */
479 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
480 MDIO_MMD_AN, &autoneg_reg);
482 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
484 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
485 MDIO_MMD_AN, autoneg_reg);
487 /* Wait for autonegotiation to finish */
488 for (time_out = 0; time_out < max_time_out; time_out++) {
490 /* Restart PHY autonegotiation and wait for completion */
491 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
495 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
496 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
501 if (time_out == max_time_out) {
502 status = IXGBE_ERR_LINK_SETUP;
503 hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out");
510 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
511 * @hw: pointer to hardware structure
512 * @speed: new link speed
514 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
515 ixgbe_link_speed speed,
516 bool autoneg_wait_to_complete)
520 * Clear autoneg_advertised and set new values based on input link
523 hw->phy.autoneg_advertised = 0;
525 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
526 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
528 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
529 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
531 if (speed & IXGBE_LINK_SPEED_100_FULL)
532 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
534 /* Setup link based on the new speed settings */
535 hw->phy.ops.setup_link(hw);
541 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
542 * @hw: pointer to hardware structure
543 * @speed: pointer to link speed
544 * @autoneg: boolean auto-negotiation value
546 * Determines the link capabilities by reading the AUTOC register.
548 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
549 ixgbe_link_speed *speed,
552 s32 status = IXGBE_ERR_LINK_SETUP;
558 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
562 if (speed_ability & MDIO_SPEED_10G)
563 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
564 if (speed_ability & MDIO_PMA_SPEED_1000)
565 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
566 if (speed_ability & MDIO_PMA_SPEED_100)
567 *speed |= IXGBE_LINK_SPEED_100_FULL;
574 * ixgbe_check_phy_link_tnx - Determine link and speed status
575 * @hw: pointer to hardware structure
577 * Reads the VS1 register to determine if link is up and the current speed for
580 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
585 u32 max_time_out = 10;
590 /* Initialize speed and link to default case */
592 *speed = IXGBE_LINK_SPEED_10GB_FULL;
595 * Check current speed and link status of the PHY register.
596 * This is a vendor specific register and may have to
597 * be changed for other copper PHYs.
599 for (time_out = 0; time_out < max_time_out; time_out++) {
601 status = hw->phy.ops.read_reg(hw,
605 phy_link = phy_data &
606 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
607 phy_speed = phy_data &
608 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
609 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
612 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
613 *speed = IXGBE_LINK_SPEED_1GB_FULL;
622 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
623 * @hw: pointer to hardware structure
625 * Restart autonegotiation and PHY and waits for completion.
627 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
631 u32 max_time_out = 10;
632 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
633 bool autoneg = false;
634 ixgbe_link_speed speed;
636 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
638 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
639 /* Set or unset auto-negotiation 10G advertisement */
640 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
644 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
645 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
646 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
648 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
653 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
654 /* Set or unset auto-negotiation 1G advertisement */
655 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
659 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
660 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
661 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
663 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
668 if (speed & IXGBE_LINK_SPEED_100_FULL) {
669 /* Set or unset auto-negotiation 100M advertisement */
670 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
674 autoneg_reg &= ~(ADVERTISE_100FULL |
676 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
677 autoneg_reg |= ADVERTISE_100FULL;
679 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
684 /* Restart PHY autonegotiation and wait for completion */
685 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
686 MDIO_MMD_AN, &autoneg_reg);
688 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
690 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
691 MDIO_MMD_AN, autoneg_reg);
693 /* Wait for autonegotiation to finish */
694 for (time_out = 0; time_out < max_time_out; time_out++) {
696 /* Restart PHY autonegotiation and wait for completion */
697 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
701 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
702 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE)
706 if (time_out == max_time_out) {
707 status = IXGBE_ERR_LINK_SETUP;
708 hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out");
715 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
716 * @hw: pointer to hardware structure
717 * @firmware_version: pointer to the PHY Firmware Version
719 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
720 u16 *firmware_version)
724 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
732 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
733 * @hw: pointer to hardware structure
734 * @firmware_version: pointer to the PHY Firmware Version
736 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
737 u16 *firmware_version)
741 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
749 * ixgbe_reset_phy_nl - Performs a PHY reset
750 * @hw: pointer to hardware structure
752 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
754 u16 phy_offset, control, eword, edata, block_crc;
755 bool end_data = false;
756 u16 list_offset, data_offset;
761 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
763 /* reset the PHY and poll for completion */
764 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
765 (phy_data | MDIO_CTRL1_RESET));
767 for (i = 0; i < 100; i++) {
768 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
770 if ((phy_data & MDIO_CTRL1_RESET) == 0)
772 usleep_range(10000, 20000);
775 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
776 hw_dbg(hw, "PHY reset did not complete.\n");
777 ret_val = IXGBE_ERR_PHY;
781 /* Get init offsets */
782 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
787 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
791 * Read control word from PHY init contents offset
793 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
796 control = (eword & IXGBE_CONTROL_MASK_NL) >>
797 IXGBE_CONTROL_SHIFT_NL;
798 edata = eword & IXGBE_DATA_MASK_NL;
802 hw_dbg(hw, "DELAY: %d MS\n", edata);
803 usleep_range(edata * 1000, edata * 2000);
806 hw_dbg(hw, "DATA:\n");
808 ret_val = hw->eeprom.ops.read(hw, data_offset++,
812 for (i = 0; i < edata; i++) {
813 ret_val = hw->eeprom.ops.read(hw, data_offset,
817 hw->phy.ops.write_reg(hw, phy_offset,
818 MDIO_MMD_PMAPMD, eword);
819 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
825 case IXGBE_CONTROL_NL:
827 hw_dbg(hw, "CONTROL:\n");
828 if (edata == IXGBE_CONTROL_EOL_NL) {
831 } else if (edata == IXGBE_CONTROL_SOL_NL) {
834 hw_dbg(hw, "Bad control value\n");
835 ret_val = IXGBE_ERR_PHY;
840 hw_dbg(hw, "Bad control type\n");
841 ret_val = IXGBE_ERR_PHY;
850 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
851 return IXGBE_ERR_PHY;
855 * ixgbe_identify_module_generic - Identifies module type
856 * @hw: pointer to hardware structure
858 * Determines HW type and calls appropriate function.
860 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
862 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
864 switch (hw->mac.ops.get_media_type(hw)) {
865 case ixgbe_media_type_fiber:
866 status = ixgbe_identify_sfp_module_generic(hw);
868 case ixgbe_media_type_fiber_qsfp:
869 status = ixgbe_identify_qsfp_module_generic(hw);
872 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
873 status = IXGBE_ERR_SFP_NOT_PRESENT;
881 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
882 * @hw: pointer to hardware structure
884 * Searches for and identifies the SFP module and assigns appropriate PHY type.
886 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
888 struct ixgbe_adapter *adapter = hw->back;
889 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
891 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
893 u8 comp_codes_1g = 0;
894 u8 comp_codes_10g = 0;
895 u8 oui_bytes[3] = {0, 0, 0};
900 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
901 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
902 status = IXGBE_ERR_SFP_NOT_PRESENT;
906 status = hw->phy.ops.read_i2c_eeprom(hw,
907 IXGBE_SFF_IDENTIFIER,
911 goto err_read_i2c_eeprom;
913 /* LAN ID is needed for sfp_type determination */
914 hw->mac.ops.set_lan_id(hw);
916 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
917 hw->phy.type = ixgbe_phy_sfp_unsupported;
918 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
920 status = hw->phy.ops.read_i2c_eeprom(hw,
921 IXGBE_SFF_1GBE_COMP_CODES,
925 goto err_read_i2c_eeprom;
927 status = hw->phy.ops.read_i2c_eeprom(hw,
928 IXGBE_SFF_10GBE_COMP_CODES,
932 goto err_read_i2c_eeprom;
933 status = hw->phy.ops.read_i2c_eeprom(hw,
934 IXGBE_SFF_CABLE_TECHNOLOGY,
938 goto err_read_i2c_eeprom;
945 * 3 SFP_DA_CORE0 - 82599-specific
946 * 4 SFP_DA_CORE1 - 82599-specific
947 * 5 SFP_SR/LR_CORE0 - 82599-specific
948 * 6 SFP_SR/LR_CORE1 - 82599-specific
949 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
950 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
951 * 9 SFP_1g_cu_CORE0 - 82599-specific
952 * 10 SFP_1g_cu_CORE1 - 82599-specific
953 * 11 SFP_1g_sx_CORE0 - 82599-specific
954 * 12 SFP_1g_sx_CORE1 - 82599-specific
956 if (hw->mac.type == ixgbe_mac_82598EB) {
957 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
958 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
959 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
960 hw->phy.sfp_type = ixgbe_sfp_type_sr;
961 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
962 hw->phy.sfp_type = ixgbe_sfp_type_lr;
964 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
965 } else if (hw->mac.type == ixgbe_mac_82599EB) {
966 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
967 if (hw->bus.lan_id == 0)
969 ixgbe_sfp_type_da_cu_core0;
972 ixgbe_sfp_type_da_cu_core1;
973 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
974 hw->phy.ops.read_i2c_eeprom(
975 hw, IXGBE_SFF_CABLE_SPEC_COMP,
978 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
979 if (hw->bus.lan_id == 0)
981 ixgbe_sfp_type_da_act_lmt_core0;
984 ixgbe_sfp_type_da_act_lmt_core1;
987 ixgbe_sfp_type_unknown;
989 } else if (comp_codes_10g &
990 (IXGBE_SFF_10GBASESR_CAPABLE |
991 IXGBE_SFF_10GBASELR_CAPABLE)) {
992 if (hw->bus.lan_id == 0)
994 ixgbe_sfp_type_srlr_core0;
997 ixgbe_sfp_type_srlr_core1;
998 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
999 if (hw->bus.lan_id == 0)
1001 ixgbe_sfp_type_1g_cu_core0;
1004 ixgbe_sfp_type_1g_cu_core1;
1005 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1006 if (hw->bus.lan_id == 0)
1008 ixgbe_sfp_type_1g_sx_core0;
1011 ixgbe_sfp_type_1g_sx_core1;
1012 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1013 if (hw->bus.lan_id == 0)
1015 ixgbe_sfp_type_1g_lx_core0;
1018 ixgbe_sfp_type_1g_lx_core1;
1020 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1024 if (hw->phy.sfp_type != stored_sfp_type)
1025 hw->phy.sfp_setup_needed = true;
1027 /* Determine if the SFP+ PHY is dual speed or not. */
1028 hw->phy.multispeed_fiber = false;
1029 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1030 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1031 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1032 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1033 hw->phy.multispeed_fiber = true;
1035 /* Determine PHY vendor */
1036 if (hw->phy.type != ixgbe_phy_nl) {
1037 hw->phy.id = identifier;
1038 status = hw->phy.ops.read_i2c_eeprom(hw,
1039 IXGBE_SFF_VENDOR_OUI_BYTE0,
1043 goto err_read_i2c_eeprom;
1045 status = hw->phy.ops.read_i2c_eeprom(hw,
1046 IXGBE_SFF_VENDOR_OUI_BYTE1,
1050 goto err_read_i2c_eeprom;
1052 status = hw->phy.ops.read_i2c_eeprom(hw,
1053 IXGBE_SFF_VENDOR_OUI_BYTE2,
1057 goto err_read_i2c_eeprom;
1060 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1061 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1062 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1064 switch (vendor_oui) {
1065 case IXGBE_SFF_VENDOR_OUI_TYCO:
1066 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1068 ixgbe_phy_sfp_passive_tyco;
1070 case IXGBE_SFF_VENDOR_OUI_FTL:
1071 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1072 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1074 hw->phy.type = ixgbe_phy_sfp_ftl;
1076 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1077 hw->phy.type = ixgbe_phy_sfp_avago;
1079 case IXGBE_SFF_VENDOR_OUI_INTEL:
1080 hw->phy.type = ixgbe_phy_sfp_intel;
1083 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1085 ixgbe_phy_sfp_passive_unknown;
1086 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1088 ixgbe_phy_sfp_active_unknown;
1090 hw->phy.type = ixgbe_phy_sfp_unknown;
1095 /* Allow any DA cable vendor */
1096 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1097 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1102 /* Verify supported 1G SFP modules */
1103 if (comp_codes_10g == 0 &&
1104 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1105 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1106 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1107 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1108 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1109 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1110 hw->phy.type = ixgbe_phy_sfp_unsupported;
1111 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1115 /* Anything else 82598-based is supported */
1116 if (hw->mac.type == ixgbe_mac_82598EB) {
1121 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1122 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1123 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1124 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1125 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1126 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1127 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1128 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1129 /* Make sure we're a supported PHY type */
1130 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1133 if (hw->allow_unsupported_sfp) {
1134 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.");
1138 "SFP+ module not supported\n");
1140 ixgbe_phy_sfp_unsupported;
1141 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1152 err_read_i2c_eeprom:
1153 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1154 if (hw->phy.type != ixgbe_phy_nl) {
1156 hw->phy.type = ixgbe_phy_unknown;
1158 return IXGBE_ERR_SFP_NOT_PRESENT;
1162 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1163 * @hw: pointer to hardware structure
1165 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1167 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1169 struct ixgbe_adapter *adapter = hw->back;
1170 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1172 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1174 u8 comp_codes_1g = 0;
1175 u8 comp_codes_10g = 0;
1176 u8 oui_bytes[3] = {0, 0, 0};
1177 u16 enforce_sfp = 0;
1179 u8 cable_length = 0;
1181 bool active_cable = false;
1183 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1184 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1185 status = IXGBE_ERR_SFP_NOT_PRESENT;
1189 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1193 goto err_read_i2c_eeprom;
1195 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1196 hw->phy.type = ixgbe_phy_sfp_unsupported;
1197 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1201 hw->phy.id = identifier;
1203 /* LAN ID is needed for sfp_type determination */
1204 hw->mac.ops.set_lan_id(hw);
1206 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1210 goto err_read_i2c_eeprom;
1212 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1216 goto err_read_i2c_eeprom;
1218 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1219 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1220 if (hw->bus.lan_id == 0)
1221 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1223 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1224 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1225 IXGBE_SFF_10GBASELR_CAPABLE)) {
1226 if (hw->bus.lan_id == 0)
1227 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1229 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1231 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1232 active_cable = true;
1234 if (!active_cable) {
1235 /* check for active DA cables that pre-date
1238 hw->phy.ops.read_i2c_eeprom(hw,
1239 IXGBE_SFF_QSFP_CONNECTOR,
1242 hw->phy.ops.read_i2c_eeprom(hw,
1243 IXGBE_SFF_QSFP_CABLE_LENGTH,
1246 hw->phy.ops.read_i2c_eeprom(hw,
1247 IXGBE_SFF_QSFP_DEVICE_TECH,
1251 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1252 (cable_length > 0) &&
1253 ((device_tech >> 4) ==
1254 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1255 active_cable = true;
1259 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1260 if (hw->bus.lan_id == 0)
1262 ixgbe_sfp_type_da_act_lmt_core0;
1265 ixgbe_sfp_type_da_act_lmt_core1;
1267 /* unsupported module type */
1268 hw->phy.type = ixgbe_phy_sfp_unsupported;
1269 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1274 if (hw->phy.sfp_type != stored_sfp_type)
1275 hw->phy.sfp_setup_needed = true;
1277 /* Determine if the QSFP+ PHY is dual speed or not. */
1278 hw->phy.multispeed_fiber = false;
1279 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1280 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1281 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1282 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1283 hw->phy.multispeed_fiber = true;
1285 /* Determine PHY vendor for optical modules */
1286 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1287 IXGBE_SFF_10GBASELR_CAPABLE)) {
1288 status = hw->phy.ops.read_i2c_eeprom(hw,
1289 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1293 goto err_read_i2c_eeprom;
1295 status = hw->phy.ops.read_i2c_eeprom(hw,
1296 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1300 goto err_read_i2c_eeprom;
1302 status = hw->phy.ops.read_i2c_eeprom(hw,
1303 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1307 goto err_read_i2c_eeprom;
1310 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1311 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1312 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1314 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1315 hw->phy.type = ixgbe_phy_qsfp_intel;
1317 hw->phy.type = ixgbe_phy_qsfp_unknown;
1319 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1320 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1321 /* Make sure we're a supported PHY type */
1322 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1325 if (hw->allow_unsupported_sfp == true) {
1326 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1330 "QSFP module not supported\n");
1332 ixgbe_phy_sfp_unsupported;
1333 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1344 err_read_i2c_eeprom:
1345 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1347 hw->phy.type = ixgbe_phy_unknown;
1349 return IXGBE_ERR_SFP_NOT_PRESENT;
1353 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1354 * @hw: pointer to hardware structure
1355 * @list_offset: offset to the SFP ID list
1356 * @data_offset: offset to the SFP data block
1358 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1359 * so it returns the offsets to the phy init sequence block.
1361 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1366 u16 sfp_type = hw->phy.sfp_type;
1368 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1369 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1371 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1372 return IXGBE_ERR_SFP_NOT_PRESENT;
1374 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1375 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1376 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1379 * Limiting active cables and 1G Phys must be initialized as
1382 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1383 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1384 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1385 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1386 sfp_type = ixgbe_sfp_type_srlr_core0;
1387 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1388 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1389 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1390 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1391 sfp_type = ixgbe_sfp_type_srlr_core1;
1393 /* Read offset to PHY init contents */
1394 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1395 hw_err(hw, "eeprom read at %d failed\n",
1396 IXGBE_PHY_INIT_OFFSET_NL);
1397 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1400 if ((!*list_offset) || (*list_offset == 0xFFFF))
1401 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1403 /* Shift offset to first ID word */
1407 * Find the matching SFP ID in the EEPROM
1408 * and program the init sequence
1410 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1413 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1414 if (sfp_id == sfp_type) {
1416 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1418 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1419 hw_dbg(hw, "SFP+ module not supported\n");
1420 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1425 (*list_offset) += 2;
1426 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1431 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1432 hw_dbg(hw, "No matching SFP+ module found\n");
1433 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1439 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
1440 return IXGBE_ERR_PHY;
1444 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1445 * @hw: pointer to hardware structure
1446 * @byte_offset: EEPROM byte offset to read
1447 * @eeprom_data: value read
1449 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1451 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1454 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1455 IXGBE_I2C_EEPROM_DEV_ADDR,
1460 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1461 * @hw: pointer to hardware structure
1462 * @byte_offset: byte offset at address 0xA2
1463 * @eeprom_data: value read
1465 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1467 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1470 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1471 IXGBE_I2C_EEPROM_DEV_ADDR2,
1476 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1477 * @hw: pointer to hardware structure
1478 * @byte_offset: EEPROM byte offset to write
1479 * @eeprom_data: value to write
1481 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1483 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1486 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1487 IXGBE_I2C_EEPROM_DEV_ADDR,
1492 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1493 * @hw: pointer to hardware structure
1494 * @byte_offset: byte offset to read
1497 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1498 * a specified device address.
1500 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1501 u8 dev_addr, u8 *data)
1510 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1511 swfw_mask = IXGBE_GSSR_PHY1_SM;
1513 swfw_mask = IXGBE_GSSR_PHY0_SM;
1516 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
1517 status = IXGBE_ERR_SWFW_SYNC;
1521 ixgbe_i2c_start(hw);
1523 /* Device Address and write indication */
1524 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1528 status = ixgbe_get_i2c_ack(hw);
1532 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1536 status = ixgbe_get_i2c_ack(hw);
1540 ixgbe_i2c_start(hw);
1542 /* Device Address and read indication */
1543 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1547 status = ixgbe_get_i2c_ack(hw);
1551 status = ixgbe_clock_in_i2c_byte(hw, data);
1555 status = ixgbe_clock_out_i2c_bit(hw, nack);
1563 ixgbe_i2c_bus_clear(hw);
1564 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1567 if (retry < max_retry)
1568 hw_dbg(hw, "I2C byte read error - Retrying.\n");
1570 hw_dbg(hw, "I2C byte read error.\n");
1572 } while (retry < max_retry);
1574 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1581 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1582 * @hw: pointer to hardware structure
1583 * @byte_offset: byte offset to write
1584 * @data: value to write
1586 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1587 * a specified device address.
1589 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1590 u8 dev_addr, u8 data)
1597 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1598 swfw_mask = IXGBE_GSSR_PHY1_SM;
1600 swfw_mask = IXGBE_GSSR_PHY0_SM;
1602 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
1603 status = IXGBE_ERR_SWFW_SYNC;
1604 goto write_byte_out;
1608 ixgbe_i2c_start(hw);
1610 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1614 status = ixgbe_get_i2c_ack(hw);
1618 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1622 status = ixgbe_get_i2c_ack(hw);
1626 status = ixgbe_clock_out_i2c_byte(hw, data);
1630 status = ixgbe_get_i2c_ack(hw);
1638 ixgbe_i2c_bus_clear(hw);
1640 if (retry < max_retry)
1641 hw_dbg(hw, "I2C byte write error - Retrying.\n");
1643 hw_dbg(hw, "I2C byte write error.\n");
1644 } while (retry < max_retry);
1646 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1653 * ixgbe_i2c_start - Sets I2C start condition
1654 * @hw: pointer to hardware structure
1656 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1658 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1660 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1662 /* Start condition must begin with data and clock high */
1663 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1664 ixgbe_raise_i2c_clk(hw, &i2cctl);
1666 /* Setup time for start condition (4.7us) */
1667 udelay(IXGBE_I2C_T_SU_STA);
1669 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1671 /* Hold time for start condition (4us) */
1672 udelay(IXGBE_I2C_T_HD_STA);
1674 ixgbe_lower_i2c_clk(hw, &i2cctl);
1676 /* Minimum low period of clock is 4.7 us */
1677 udelay(IXGBE_I2C_T_LOW);
1682 * ixgbe_i2c_stop - Sets I2C stop condition
1683 * @hw: pointer to hardware structure
1685 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1687 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1689 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1691 /* Stop condition must begin with data low and clock high */
1692 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1693 ixgbe_raise_i2c_clk(hw, &i2cctl);
1695 /* Setup time for stop condition (4us) */
1696 udelay(IXGBE_I2C_T_SU_STO);
1698 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1700 /* bus free time between stop and start (4.7us)*/
1701 udelay(IXGBE_I2C_T_BUF);
1705 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1706 * @hw: pointer to hardware structure
1707 * @data: data byte to clock in
1709 * Clocks in one byte data via I2C data/clock
1711 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1716 for (i = 7; i >= 0; i--) {
1717 ixgbe_clock_in_i2c_bit(hw, &bit);
1725 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1726 * @hw: pointer to hardware structure
1727 * @data: data byte clocked out
1729 * Clocks out one byte data via I2C data/clock
1731 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1738 for (i = 7; i >= 0; i--) {
1739 bit = (data >> i) & 0x1;
1740 status = ixgbe_clock_out_i2c_bit(hw, bit);
1746 /* Release SDA line (set high) */
1747 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1748 i2cctl |= IXGBE_I2C_DATA_OUT;
1749 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1750 IXGBE_WRITE_FLUSH(hw);
1756 * ixgbe_get_i2c_ack - Polls for I2C ACK
1757 * @hw: pointer to hardware structure
1759 * Clocks in/out one bit via I2C data/clock
1761 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1765 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1769 ixgbe_raise_i2c_clk(hw, &i2cctl);
1772 /* Minimum high period of clock is 4us */
1773 udelay(IXGBE_I2C_T_HIGH);
1775 /* Poll for ACK. Note that ACK in I2C spec is
1776 * transition from 1 to 0 */
1777 for (i = 0; i < timeout; i++) {
1778 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1779 ack = ixgbe_get_i2c_data(&i2cctl);
1787 hw_dbg(hw, "I2C ack was not received.\n");
1788 status = IXGBE_ERR_I2C;
1791 ixgbe_lower_i2c_clk(hw, &i2cctl);
1793 /* Minimum low period of clock is 4.7 us */
1794 udelay(IXGBE_I2C_T_LOW);
1800 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1801 * @hw: pointer to hardware structure
1802 * @data: read data value
1804 * Clocks in one bit via I2C data/clock
1806 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1808 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1810 ixgbe_raise_i2c_clk(hw, &i2cctl);
1812 /* Minimum high period of clock is 4us */
1813 udelay(IXGBE_I2C_T_HIGH);
1815 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1816 *data = ixgbe_get_i2c_data(&i2cctl);
1818 ixgbe_lower_i2c_clk(hw, &i2cctl);
1820 /* Minimum low period of clock is 4.7 us */
1821 udelay(IXGBE_I2C_T_LOW);
1827 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1828 * @hw: pointer to hardware structure
1829 * @data: data value to write
1831 * Clocks out one bit via I2C data/clock
1833 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1836 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1838 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1840 ixgbe_raise_i2c_clk(hw, &i2cctl);
1842 /* Minimum high period of clock is 4us */
1843 udelay(IXGBE_I2C_T_HIGH);
1845 ixgbe_lower_i2c_clk(hw, &i2cctl);
1847 /* Minimum low period of clock is 4.7 us.
1848 * This also takes care of the data hold time.
1850 udelay(IXGBE_I2C_T_LOW);
1852 status = IXGBE_ERR_I2C;
1853 hw_dbg(hw, "I2C data was not set to %X\n", data);
1859 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1860 * @hw: pointer to hardware structure
1861 * @i2cctl: Current value of I2CCTL register
1863 * Raises the I2C clock line '0'->'1'
1865 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1868 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1871 for (i = 0; i < timeout; i++) {
1872 *i2cctl |= IXGBE_I2C_CLK_OUT;
1873 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1874 IXGBE_WRITE_FLUSH(hw);
1875 /* SCL rise time (1000ns) */
1876 udelay(IXGBE_I2C_T_RISE);
1878 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1879 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1885 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1886 * @hw: pointer to hardware structure
1887 * @i2cctl: Current value of I2CCTL register
1889 * Lowers the I2C clock line '1'->'0'
1891 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1894 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1896 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1897 IXGBE_WRITE_FLUSH(hw);
1899 /* SCL fall time (300ns) */
1900 udelay(IXGBE_I2C_T_FALL);
1904 * ixgbe_set_i2c_data - Sets the I2C data bit
1905 * @hw: pointer to hardware structure
1906 * @i2cctl: Current value of I2CCTL register
1907 * @data: I2C data value (0 or 1) to set
1909 * Sets the I2C data bit
1911 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1916 *i2cctl |= IXGBE_I2C_DATA_OUT;
1918 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1920 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1921 IXGBE_WRITE_FLUSH(hw);
1923 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1924 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1926 /* Verify data was set correctly */
1927 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1928 if (data != ixgbe_get_i2c_data(i2cctl)) {
1929 status = IXGBE_ERR_I2C;
1930 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1937 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1938 * @hw: pointer to hardware structure
1939 * @i2cctl: Current value of I2CCTL register
1941 * Returns the I2C data bit value
1943 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1947 if (*i2cctl & IXGBE_I2C_DATA_IN)
1956 * ixgbe_i2c_bus_clear - Clears the I2C bus
1957 * @hw: pointer to hardware structure
1959 * Clears the I2C bus by sending nine clock pulses.
1960 * Used when data line is stuck low.
1962 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1964 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1967 ixgbe_i2c_start(hw);
1969 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1971 for (i = 0; i < 9; i++) {
1972 ixgbe_raise_i2c_clk(hw, &i2cctl);
1974 /* Min high period of clock is 4us */
1975 udelay(IXGBE_I2C_T_HIGH);
1977 ixgbe_lower_i2c_clk(hw, &i2cctl);
1979 /* Min low period of clock is 4.7us*/
1980 udelay(IXGBE_I2C_T_LOW);
1983 ixgbe_i2c_start(hw);
1985 /* Put the i2c bus back to default state */
1990 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1991 * @hw: pointer to hardware structure
1993 * Checks if the LASI temp alarm status was triggered due to overtemp
1995 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2000 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2003 /* Check that the LASI temp alarm status was triggered */
2004 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2005 MDIO_MMD_PMAPMD, &phy_data);
2007 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2010 status = IXGBE_ERR_OVERTEMP;