1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 /* ethtool support for ixgbe */
30 #include <linux/interrupt.h>
31 #include <linux/types.h>
32 #include <linux/module.h>
33 #include <linux/slab.h>
34 #include <linux/pci.h>
35 #include <linux/netdevice.h>
36 #include <linux/ethtool.h>
37 #include <linux/vmalloc.h>
38 #include <linux/highmem.h>
39 #include <linux/uaccess.h>
42 #include "ixgbe_phy.h"
45 #define IXGBE_ALL_RAR_ENTRIES 16
47 enum {NETDEV_STATS, IXGBE_STATS};
50 char stat_string[ETH_GSTRING_LEN];
56 #define IXGBE_STAT(m) IXGBE_STATS, \
57 sizeof(((struct ixgbe_adapter *)0)->m), \
58 offsetof(struct ixgbe_adapter, m)
59 #define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
60 sizeof(((struct rtnl_link_stats64 *)0)->m), \
61 offsetof(struct rtnl_link_stats64, m)
63 static const struct ixgbe_stats ixgbe_gstrings_stats[] = {
64 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
65 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
66 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
67 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
68 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
69 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
70 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
71 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
72 {"lsc_int", IXGBE_STAT(lsc_int)},
73 {"tx_busy", IXGBE_STAT(tx_busy)},
74 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
75 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
76 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
77 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
78 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
79 {"multicast", IXGBE_NETDEV_STAT(multicast)},
80 {"broadcast", IXGBE_STAT(stats.bprc)},
81 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
82 {"collisions", IXGBE_NETDEV_STAT(collisions)},
83 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
84 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
85 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
86 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
87 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
88 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
89 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
90 {"fdir_overflow", IXGBE_STAT(fdir_overflow)},
91 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
92 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
93 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
94 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
95 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
96 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
97 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
98 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
99 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
100 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
101 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
102 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
103 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
104 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
105 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
106 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
107 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
108 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
109 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
110 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
111 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
112 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
114 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
115 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
116 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
117 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
118 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)},
119 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)},
120 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
121 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
122 #endif /* IXGBE_FCOE */
125 /* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so
126 * we set the num_rx_queues to evaluate to num_tx_queues. This is
127 * used because we do not have a good way to get the max number of
128 * rx queues with CONFIG_RPS disabled.
130 #define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues
132 #define IXGBE_QUEUE_STATS_LEN ( \
133 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \
134 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
135 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
136 #define IXGBE_PB_STATS_LEN ( \
137 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
138 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
139 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
140 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
142 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
143 IXGBE_PB_STATS_LEN + \
144 IXGBE_QUEUE_STATS_LEN)
146 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
147 "Register test (offline)", "Eeprom test (offline)",
148 "Interrupt test (offline)", "Loopback test (offline)",
149 "Link test (on/offline)"
151 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
153 static int ixgbe_get_settings(struct net_device *netdev,
154 struct ethtool_cmd *ecmd)
156 struct ixgbe_adapter *adapter = netdev_priv(netdev);
157 struct ixgbe_hw *hw = &adapter->hw;
158 ixgbe_link_speed supported_link;
160 bool autoneg = false;
163 /* SFP type is needed for get_link_capabilities */
164 if (hw->phy.media_type & (ixgbe_media_type_fiber |
165 ixgbe_media_type_fiber_qsfp)) {
166 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
167 hw->phy.ops.identify_sfp(hw);
170 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg);
172 /* set the supported link speeds */
173 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
174 ecmd->supported |= SUPPORTED_10000baseT_Full;
175 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
176 ecmd->supported |= SUPPORTED_1000baseT_Full;
177 if (supported_link & IXGBE_LINK_SPEED_100_FULL)
178 ecmd->supported |= SUPPORTED_100baseT_Full;
180 /* set the advertised speeds */
181 if (hw->phy.autoneg_advertised) {
182 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
183 ecmd->advertising |= ADVERTISED_100baseT_Full;
184 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
185 ecmd->advertising |= ADVERTISED_10000baseT_Full;
186 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
187 ecmd->advertising |= ADVERTISED_1000baseT_Full;
189 /* default modes in case phy.autoneg_advertised isn't set */
190 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
191 ecmd->advertising |= ADVERTISED_10000baseT_Full;
192 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
193 ecmd->advertising |= ADVERTISED_1000baseT_Full;
194 if (supported_link & IXGBE_LINK_SPEED_100_FULL)
195 ecmd->advertising |= ADVERTISED_100baseT_Full;
197 if (hw->phy.multispeed_fiber && !autoneg) {
198 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
199 ecmd->advertising = ADVERTISED_10000baseT_Full;
204 ecmd->supported |= SUPPORTED_Autoneg;
205 ecmd->advertising |= ADVERTISED_Autoneg;
206 ecmd->autoneg = AUTONEG_ENABLE;
208 ecmd->autoneg = AUTONEG_DISABLE;
210 ecmd->transceiver = XCVR_EXTERNAL;
212 /* Determine the remaining settings based on the PHY type. */
213 switch (adapter->hw.phy.type) {
216 case ixgbe_phy_cu_unknown:
217 ecmd->supported |= SUPPORTED_TP;
218 ecmd->advertising |= ADVERTISED_TP;
219 ecmd->port = PORT_TP;
222 ecmd->supported |= SUPPORTED_FIBRE;
223 ecmd->advertising |= ADVERTISED_FIBRE;
224 ecmd->port = PORT_FIBRE;
227 case ixgbe_phy_sfp_passive_tyco:
228 case ixgbe_phy_sfp_passive_unknown:
229 case ixgbe_phy_sfp_ftl:
230 case ixgbe_phy_sfp_avago:
231 case ixgbe_phy_sfp_intel:
232 case ixgbe_phy_sfp_unknown:
233 /* SFP+ devices, further checking needed */
234 switch (adapter->hw.phy.sfp_type) {
235 case ixgbe_sfp_type_da_cu:
236 case ixgbe_sfp_type_da_cu_core0:
237 case ixgbe_sfp_type_da_cu_core1:
238 ecmd->supported |= SUPPORTED_FIBRE;
239 ecmd->advertising |= ADVERTISED_FIBRE;
240 ecmd->port = PORT_DA;
242 case ixgbe_sfp_type_sr:
243 case ixgbe_sfp_type_lr:
244 case ixgbe_sfp_type_srlr_core0:
245 case ixgbe_sfp_type_srlr_core1:
246 case ixgbe_sfp_type_1g_sx_core0:
247 case ixgbe_sfp_type_1g_sx_core1:
248 case ixgbe_sfp_type_1g_lx_core0:
249 case ixgbe_sfp_type_1g_lx_core1:
250 ecmd->supported |= SUPPORTED_FIBRE;
251 ecmd->advertising |= ADVERTISED_FIBRE;
252 ecmd->port = PORT_FIBRE;
254 case ixgbe_sfp_type_not_present:
255 ecmd->supported |= SUPPORTED_FIBRE;
256 ecmd->advertising |= ADVERTISED_FIBRE;
257 ecmd->port = PORT_NONE;
259 case ixgbe_sfp_type_1g_cu_core0:
260 case ixgbe_sfp_type_1g_cu_core1:
261 ecmd->supported |= SUPPORTED_TP;
262 ecmd->advertising |= ADVERTISED_TP;
263 ecmd->port = PORT_TP;
265 case ixgbe_sfp_type_unknown:
267 ecmd->supported |= SUPPORTED_FIBRE;
268 ecmd->advertising |= ADVERTISED_FIBRE;
269 ecmd->port = PORT_OTHER;
274 ecmd->supported |= SUPPORTED_FIBRE;
275 ecmd->advertising |= ADVERTISED_FIBRE;
276 ecmd->port = PORT_NONE;
278 case ixgbe_phy_unknown:
279 case ixgbe_phy_generic:
280 case ixgbe_phy_sfp_unsupported:
282 ecmd->supported |= SUPPORTED_FIBRE;
283 ecmd->advertising |= ADVERTISED_FIBRE;
284 ecmd->port = PORT_OTHER;
288 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
290 switch (link_speed) {
291 case IXGBE_LINK_SPEED_10GB_FULL:
292 ethtool_cmd_speed_set(ecmd, SPEED_10000);
294 case IXGBE_LINK_SPEED_1GB_FULL:
295 ethtool_cmd_speed_set(ecmd, SPEED_1000);
297 case IXGBE_LINK_SPEED_100_FULL:
298 ethtool_cmd_speed_set(ecmd, SPEED_100);
303 ecmd->duplex = DUPLEX_FULL;
305 ethtool_cmd_speed_set(ecmd, -1);
312 static int ixgbe_set_settings(struct net_device *netdev,
313 struct ethtool_cmd *ecmd)
315 struct ixgbe_adapter *adapter = netdev_priv(netdev);
316 struct ixgbe_hw *hw = &adapter->hw;
320 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
321 (hw->phy.multispeed_fiber)) {
323 * this function does not support duplex forcing, but can
324 * limit the advertising of the adapter to the specified speed
326 if (ecmd->advertising & ~ecmd->supported)
329 /* only allow one speed at a time if no autoneg */
330 if (!ecmd->autoneg && hw->phy.multispeed_fiber) {
331 if (ecmd->advertising ==
332 (ADVERTISED_10000baseT_Full |
333 ADVERTISED_1000baseT_Full))
337 old = hw->phy.autoneg_advertised;
339 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
340 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
342 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
343 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
345 if (ecmd->advertising & ADVERTISED_100baseT_Full)
346 advertised |= IXGBE_LINK_SPEED_100_FULL;
348 if (old == advertised)
350 /* this sets the link speed and restarts auto-neg */
351 hw->mac.autotry_restart = true;
352 err = hw->mac.ops.setup_link(hw, advertised, true);
354 e_info(probe, "setup link failed with code %d\n", err);
355 hw->mac.ops.setup_link(hw, old, true);
358 /* in this case we currently only support 10Gb/FULL */
359 u32 speed = ethtool_cmd_speed(ecmd);
360 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
361 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
362 (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
369 static void ixgbe_get_pauseparam(struct net_device *netdev,
370 struct ethtool_pauseparam *pause)
372 struct ixgbe_adapter *adapter = netdev_priv(netdev);
373 struct ixgbe_hw *hw = &adapter->hw;
375 if (ixgbe_device_supports_autoneg_fc(hw) &&
376 !hw->fc.disable_fc_autoneg)
381 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
383 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
385 } else if (hw->fc.current_mode == ixgbe_fc_full) {
391 static int ixgbe_set_pauseparam(struct net_device *netdev,
392 struct ethtool_pauseparam *pause)
394 struct ixgbe_adapter *adapter = netdev_priv(netdev);
395 struct ixgbe_hw *hw = &adapter->hw;
396 struct ixgbe_fc_info fc = hw->fc;
398 /* 82598 does no support link flow control with DCB enabled */
399 if ((hw->mac.type == ixgbe_mac_82598EB) &&
400 (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
403 /* some devices do not support autoneg of link flow control */
404 if ((pause->autoneg == AUTONEG_ENABLE) &&
405 !ixgbe_device_supports_autoneg_fc(hw))
408 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE);
410 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
411 fc.requested_mode = ixgbe_fc_full;
412 else if (pause->rx_pause && !pause->tx_pause)
413 fc.requested_mode = ixgbe_fc_rx_pause;
414 else if (!pause->rx_pause && pause->tx_pause)
415 fc.requested_mode = ixgbe_fc_tx_pause;
417 fc.requested_mode = ixgbe_fc_none;
419 /* if the thing changed then we'll update and use new autoneg */
420 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
422 if (netif_running(netdev))
423 ixgbe_reinit_locked(adapter);
425 ixgbe_reset(adapter);
431 static u32 ixgbe_get_msglevel(struct net_device *netdev)
433 struct ixgbe_adapter *adapter = netdev_priv(netdev);
434 return adapter->msg_enable;
437 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
439 struct ixgbe_adapter *adapter = netdev_priv(netdev);
440 adapter->msg_enable = data;
443 static int ixgbe_get_regs_len(struct net_device *netdev)
445 #define IXGBE_REGS_LEN 1139
446 return IXGBE_REGS_LEN * sizeof(u32);
449 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
451 static void ixgbe_get_regs(struct net_device *netdev,
452 struct ethtool_regs *regs, void *p)
454 struct ixgbe_adapter *adapter = netdev_priv(netdev);
455 struct ixgbe_hw *hw = &adapter->hw;
459 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
461 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
464 /* General Registers */
465 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
466 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
467 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
468 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
469 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
470 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
471 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
472 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
475 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
476 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
477 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
478 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
479 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
480 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
481 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
482 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
483 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
484 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
487 /* don't read EICR because it can clear interrupt causes, instead
488 * read EICS which is a shadow but doesn't clear EICR */
489 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
490 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
491 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
492 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
493 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
494 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
495 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
496 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
497 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
498 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
499 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
500 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
503 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
504 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
505 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
506 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
507 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
508 for (i = 0; i < 8; i++) {
509 switch (hw->mac.type) {
510 case ixgbe_mac_82598EB:
511 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
512 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
514 case ixgbe_mac_82599EB:
516 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
517 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
523 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
524 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
527 for (i = 0; i < 64; i++)
528 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
529 for (i = 0; i < 64; i++)
530 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
531 for (i = 0; i < 64; i++)
532 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
533 for (i = 0; i < 64; i++)
534 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
535 for (i = 0; i < 64; i++)
536 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
537 for (i = 0; i < 64; i++)
538 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
539 for (i = 0; i < 16; i++)
540 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
541 for (i = 0; i < 16; i++)
542 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
543 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
544 for (i = 0; i < 8; i++)
545 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
546 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
547 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
550 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
551 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
552 for (i = 0; i < 16; i++)
553 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
554 for (i = 0; i < 16; i++)
555 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
556 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
557 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
558 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
559 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
560 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
561 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
562 for (i = 0; i < 8; i++)
563 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
564 for (i = 0; i < 8; i++)
565 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
566 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
569 for (i = 0; i < 32; i++)
570 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
571 for (i = 0; i < 32; i++)
572 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
573 for (i = 0; i < 32; i++)
574 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
575 for (i = 0; i < 32; i++)
576 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
577 for (i = 0; i < 32; i++)
578 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
579 for (i = 0; i < 32; i++)
580 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
581 for (i = 0; i < 32; i++)
582 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
583 for (i = 0; i < 32; i++)
584 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
585 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
586 for (i = 0; i < 16; i++)
587 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
588 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
589 for (i = 0; i < 8; i++)
590 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
591 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
594 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
595 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
596 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
597 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
598 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
599 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
600 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
601 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
602 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
605 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); /* same as FCCFG */
606 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */
608 switch (hw->mac.type) {
609 case ixgbe_mac_82598EB:
610 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
611 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
612 for (i = 0; i < 8; i++)
614 IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
615 for (i = 0; i < 8; i++)
617 IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
618 for (i = 0; i < 8; i++)
620 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
621 for (i = 0; i < 8; i++)
623 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
625 case ixgbe_mac_82599EB:
627 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
628 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS);
629 for (i = 0; i < 8; i++)
631 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i));
632 for (i = 0; i < 8; i++)
634 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i));
635 for (i = 0; i < 8; i++)
637 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i));
638 for (i = 0; i < 8; i++)
640 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i));
646 for (i = 0; i < 8; i++)
648 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */
649 for (i = 0; i < 8; i++)
651 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */
654 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
655 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
656 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
657 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
658 for (i = 0; i < 8; i++)
659 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
660 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
661 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
662 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
663 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
664 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
665 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
666 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
667 for (i = 0; i < 8; i++)
668 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
669 for (i = 0; i < 8; i++)
670 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
671 for (i = 0; i < 8; i++)
672 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
673 for (i = 0; i < 8; i++)
674 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
675 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
676 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
677 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
678 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
679 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
680 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
681 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
682 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
683 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
684 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
685 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
686 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
687 for (i = 0; i < 8; i++)
688 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
689 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
690 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
691 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
692 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
693 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
694 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
695 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
696 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
697 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
698 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
699 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
700 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
701 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
702 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
703 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
704 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
705 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
706 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
707 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
708 for (i = 0; i < 16; i++)
709 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
710 for (i = 0; i < 16; i++)
711 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
712 for (i = 0; i < 16; i++)
713 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
714 for (i = 0; i < 16; i++)
715 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
718 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
719 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
720 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
721 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
722 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
723 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
724 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
725 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
726 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
727 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
728 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
729 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
730 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
731 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
732 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
733 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
734 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
735 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
736 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
737 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
738 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
739 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
740 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
741 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
742 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
743 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
744 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
745 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
746 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
747 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
748 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
749 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
750 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
753 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
754 for (i = 0; i < 8; i++)
755 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
756 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
757 for (i = 0; i < 4; i++)
758 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
759 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
760 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
761 for (i = 0; i < 8; i++)
762 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
763 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
764 for (i = 0; i < 4; i++)
765 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
766 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
767 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
768 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
769 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
770 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
771 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
772 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
773 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
774 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
775 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
776 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
777 for (i = 0; i < 8; i++)
778 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
779 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
780 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
781 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
782 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
783 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
784 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
785 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
786 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
787 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
789 /* 82599 X540 specific registers */
790 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);
792 /* 82599 X540 specific DCB registers */
793 regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
794 regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC);
795 for (i = 0; i < 4; i++)
796 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i));
797 regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM);
798 /* same as RTTQCNRM */
799 regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD);
800 /* same as RTTQCNRR */
802 /* X540 specific DCB registers */
803 regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR);
804 regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG);
807 static int ixgbe_get_eeprom_len(struct net_device *netdev)
809 struct ixgbe_adapter *adapter = netdev_priv(netdev);
810 return adapter->hw.eeprom.word_size * 2;
813 static int ixgbe_get_eeprom(struct net_device *netdev,
814 struct ethtool_eeprom *eeprom, u8 *bytes)
816 struct ixgbe_adapter *adapter = netdev_priv(netdev);
817 struct ixgbe_hw *hw = &adapter->hw;
819 int first_word, last_word, eeprom_len;
823 if (eeprom->len == 0)
826 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
828 first_word = eeprom->offset >> 1;
829 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
830 eeprom_len = last_word - first_word + 1;
832 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
836 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
839 /* Device's eeprom is always little-endian, word addressable */
840 for (i = 0; i < eeprom_len; i++)
841 le16_to_cpus(&eeprom_buff[i]);
843 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
849 static int ixgbe_set_eeprom(struct net_device *netdev,
850 struct ethtool_eeprom *eeprom, u8 *bytes)
852 struct ixgbe_adapter *adapter = netdev_priv(netdev);
853 struct ixgbe_hw *hw = &adapter->hw;
856 int max_len, first_word, last_word, ret_val = 0;
859 if (eeprom->len == 0)
862 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
865 max_len = hw->eeprom.word_size * 2;
867 first_word = eeprom->offset >> 1;
868 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
869 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
875 if (eeprom->offset & 1) {
877 * need read/modify/write of first changed EEPROM word
878 * only the second byte of the word is being modified
880 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]);
886 if ((eeprom->offset + eeprom->len) & 1) {
888 * need read/modify/write of last changed EEPROM word
889 * only the first byte of the word is being modified
891 ret_val = hw->eeprom.ops.read(hw, last_word,
892 &eeprom_buff[last_word - first_word]);
897 /* Device's eeprom is always little-endian, word addressable */
898 for (i = 0; i < last_word - first_word + 1; i++)
899 le16_to_cpus(&eeprom_buff[i]);
901 memcpy(ptr, bytes, eeprom->len);
903 for (i = 0; i < last_word - first_word + 1; i++)
904 cpu_to_le16s(&eeprom_buff[i]);
906 ret_val = hw->eeprom.ops.write_buffer(hw, first_word,
907 last_word - first_word + 1,
910 /* Update the checksum */
912 hw->eeprom.ops.update_checksum(hw);
919 static void ixgbe_get_drvinfo(struct net_device *netdev,
920 struct ethtool_drvinfo *drvinfo)
922 struct ixgbe_adapter *adapter = netdev_priv(netdev);
925 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
926 strlcpy(drvinfo->version, ixgbe_driver_version,
927 sizeof(drvinfo->version));
929 nvm_track_id = (adapter->eeprom_verh << 16) |
930 adapter->eeprom_verl;
931 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "0x%08x",
934 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
935 sizeof(drvinfo->bus_info));
936 drvinfo->n_stats = IXGBE_STATS_LEN;
937 drvinfo->testinfo_len = IXGBE_TEST_LEN;
938 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
941 static void ixgbe_get_ringparam(struct net_device *netdev,
942 struct ethtool_ringparam *ring)
944 struct ixgbe_adapter *adapter = netdev_priv(netdev);
945 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
946 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
948 ring->rx_max_pending = IXGBE_MAX_RXD;
949 ring->tx_max_pending = IXGBE_MAX_TXD;
950 ring->rx_pending = rx_ring->count;
951 ring->tx_pending = tx_ring->count;
954 static int ixgbe_set_ringparam(struct net_device *netdev,
955 struct ethtool_ringparam *ring)
957 struct ixgbe_adapter *adapter = netdev_priv(netdev);
958 struct ixgbe_ring *temp_ring;
960 u32 new_rx_count, new_tx_count;
962 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
965 new_tx_count = clamp_t(u32, ring->tx_pending,
966 IXGBE_MIN_TXD, IXGBE_MAX_TXD);
967 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
969 new_rx_count = clamp_t(u32, ring->rx_pending,
970 IXGBE_MIN_RXD, IXGBE_MAX_RXD);
971 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
973 if ((new_tx_count == adapter->tx_ring_count) &&
974 (new_rx_count == adapter->rx_ring_count)) {
979 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
980 usleep_range(1000, 2000);
982 if (!netif_running(adapter->netdev)) {
983 for (i = 0; i < adapter->num_tx_queues; i++)
984 adapter->tx_ring[i]->count = new_tx_count;
985 for (i = 0; i < adapter->num_rx_queues; i++)
986 adapter->rx_ring[i]->count = new_rx_count;
987 adapter->tx_ring_count = new_tx_count;
988 adapter->rx_ring_count = new_rx_count;
992 /* allocate temporary buffer to store rings in */
993 i = max_t(int, adapter->num_tx_queues, adapter->num_rx_queues);
994 temp_ring = vmalloc(i * sizeof(struct ixgbe_ring));
1001 ixgbe_down(adapter);
1004 * Setup new Tx resources and free the old Tx resources in that order.
1005 * We can then assign the new resources to the rings via a memcpy.
1006 * The advantage to this approach is that we are guaranteed to still
1007 * have resources even in the case of an allocation failure.
1009 if (new_tx_count != adapter->tx_ring_count) {
1010 for (i = 0; i < adapter->num_tx_queues; i++) {
1011 memcpy(&temp_ring[i], adapter->tx_ring[i],
1012 sizeof(struct ixgbe_ring));
1014 temp_ring[i].count = new_tx_count;
1015 err = ixgbe_setup_tx_resources(&temp_ring[i]);
1019 ixgbe_free_tx_resources(&temp_ring[i]);
1025 for (i = 0; i < adapter->num_tx_queues; i++) {
1026 ixgbe_free_tx_resources(adapter->tx_ring[i]);
1028 memcpy(adapter->tx_ring[i], &temp_ring[i],
1029 sizeof(struct ixgbe_ring));
1032 adapter->tx_ring_count = new_tx_count;
1035 /* Repeat the process for the Rx rings if needed */
1036 if (new_rx_count != adapter->rx_ring_count) {
1037 for (i = 0; i < adapter->num_rx_queues; i++) {
1038 memcpy(&temp_ring[i], adapter->rx_ring[i],
1039 sizeof(struct ixgbe_ring));
1041 temp_ring[i].count = new_rx_count;
1042 err = ixgbe_setup_rx_resources(&temp_ring[i]);
1046 ixgbe_free_rx_resources(&temp_ring[i]);
1053 for (i = 0; i < adapter->num_rx_queues; i++) {
1054 ixgbe_free_rx_resources(adapter->rx_ring[i]);
1056 memcpy(adapter->rx_ring[i], &temp_ring[i],
1057 sizeof(struct ixgbe_ring));
1060 adapter->rx_ring_count = new_rx_count;
1067 clear_bit(__IXGBE_RESETTING, &adapter->state);
1071 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
1075 return IXGBE_TEST_LEN;
1077 return IXGBE_STATS_LEN;
1083 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
1084 struct ethtool_stats *stats, u64 *data)
1086 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1087 struct rtnl_link_stats64 temp;
1088 const struct rtnl_link_stats64 *net_stats;
1090 struct ixgbe_ring *ring;
1094 ixgbe_update_stats(adapter);
1095 net_stats = dev_get_stats(netdev, &temp);
1096 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1097 switch (ixgbe_gstrings_stats[i].type) {
1099 p = (char *) net_stats +
1100 ixgbe_gstrings_stats[i].stat_offset;
1103 p = (char *) adapter +
1104 ixgbe_gstrings_stats[i].stat_offset;
1111 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
1112 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1114 for (j = 0; j < netdev->num_tx_queues; j++) {
1115 ring = adapter->tx_ring[j];
1120 #ifdef BP_EXTENDED_STATS
1130 start = u64_stats_fetch_begin_bh(&ring->syncp);
1131 data[i] = ring->stats.packets;
1132 data[i+1] = ring->stats.bytes;
1133 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1135 #ifdef BP_EXTENDED_STATS
1136 data[i] = ring->stats.yields;
1137 data[i+1] = ring->stats.misses;
1138 data[i+2] = ring->stats.cleaned;
1142 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
1143 ring = adapter->rx_ring[j];
1148 #ifdef BP_EXTENDED_STATS
1158 start = u64_stats_fetch_begin_bh(&ring->syncp);
1159 data[i] = ring->stats.packets;
1160 data[i+1] = ring->stats.bytes;
1161 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1163 #ifdef BP_EXTENDED_STATS
1164 data[i] = ring->stats.yields;
1165 data[i+1] = ring->stats.misses;
1166 data[i+2] = ring->stats.cleaned;
1171 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1172 data[i++] = adapter->stats.pxontxc[j];
1173 data[i++] = adapter->stats.pxofftxc[j];
1175 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1176 data[i++] = adapter->stats.pxonrxc[j];
1177 data[i++] = adapter->stats.pxoffrxc[j];
1181 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
1184 char *p = (char *)data;
1187 switch (stringset) {
1189 for (i = 0; i < IXGBE_TEST_LEN; i++) {
1190 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN);
1191 data += ETH_GSTRING_LEN;
1195 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1196 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1198 p += ETH_GSTRING_LEN;
1200 for (i = 0; i < netdev->num_tx_queues; i++) {
1201 sprintf(p, "tx_queue_%u_packets", i);
1202 p += ETH_GSTRING_LEN;
1203 sprintf(p, "tx_queue_%u_bytes", i);
1204 p += ETH_GSTRING_LEN;
1205 #ifdef BP_EXTENDED_STATS
1206 sprintf(p, "tx_queue_%u_bp_napi_yield", i);
1207 p += ETH_GSTRING_LEN;
1208 sprintf(p, "tx_queue_%u_bp_misses", i);
1209 p += ETH_GSTRING_LEN;
1210 sprintf(p, "tx_queue_%u_bp_cleaned", i);
1211 p += ETH_GSTRING_LEN;
1212 #endif /* BP_EXTENDED_STATS */
1214 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) {
1215 sprintf(p, "rx_queue_%u_packets", i);
1216 p += ETH_GSTRING_LEN;
1217 sprintf(p, "rx_queue_%u_bytes", i);
1218 p += ETH_GSTRING_LEN;
1219 #ifdef BP_EXTENDED_STATS
1220 sprintf(p, "rx_queue_%u_bp_poll_yield", i);
1221 p += ETH_GSTRING_LEN;
1222 sprintf(p, "rx_queue_%u_bp_misses", i);
1223 p += ETH_GSTRING_LEN;
1224 sprintf(p, "rx_queue_%u_bp_cleaned", i);
1225 p += ETH_GSTRING_LEN;
1226 #endif /* BP_EXTENDED_STATS */
1228 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1229 sprintf(p, "tx_pb_%u_pxon", i);
1230 p += ETH_GSTRING_LEN;
1231 sprintf(p, "tx_pb_%u_pxoff", i);
1232 p += ETH_GSTRING_LEN;
1234 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1235 sprintf(p, "rx_pb_%u_pxon", i);
1236 p += ETH_GSTRING_LEN;
1237 sprintf(p, "rx_pb_%u_pxoff", i);
1238 p += ETH_GSTRING_LEN;
1240 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1245 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1247 struct ixgbe_hw *hw = &adapter->hw;
1252 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1260 /* ethtool register test data */
1261 struct ixgbe_reg_test {
1269 /* In the hardware, registers are laid out either singly, in arrays
1270 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1271 * most tests take place on arrays or single registers (handled
1272 * as a single-element array) and special-case the tables.
1273 * Table tests are always pattern tests.
1275 * We also make provision for some required setup steps by specifying
1276 * registers to be written without any read-back testing.
1279 #define PATTERN_TEST 1
1280 #define SET_READ_TEST 2
1281 #define WRITE_NO_TEST 3
1282 #define TABLE32_TEST 4
1283 #define TABLE64_TEST_LO 5
1284 #define TABLE64_TEST_HI 6
1286 /* default 82599 register test */
1287 static const struct ixgbe_reg_test reg_test_82599[] = {
1288 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1289 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1290 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1291 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1292 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1293 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1294 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1295 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1296 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1297 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1298 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1299 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1300 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1301 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1302 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1303 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1304 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1305 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1306 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1310 /* default 82598 register test */
1311 static const struct ixgbe_reg_test reg_test_82598[] = {
1312 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1313 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1314 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1315 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1316 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1317 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1318 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1319 /* Enable all four RX queues before testing. */
1320 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1321 /* RDH is read-only for 82598, only test RDT. */
1322 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1323 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1324 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1325 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1326 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1327 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1328 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1329 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1330 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1331 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1332 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1333 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1334 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1338 static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1339 u32 mask, u32 write)
1341 u32 pat, val, before;
1342 static const u32 test_pattern[] = {
1343 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1345 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
1346 before = readl(adapter->hw.hw_addr + reg);
1347 writel((test_pattern[pat] & write),
1348 (adapter->hw.hw_addr + reg));
1349 val = readl(adapter->hw.hw_addr + reg);
1350 if (val != (test_pattern[pat] & write & mask)) {
1351 e_err(drv, "pattern test reg %04X failed: got "
1352 "0x%08X expected 0x%08X\n",
1353 reg, val, (test_pattern[pat] & write & mask));
1355 writel(before, adapter->hw.hw_addr + reg);
1358 writel(before, adapter->hw.hw_addr + reg);
1363 static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1364 u32 mask, u32 write)
1367 before = readl(adapter->hw.hw_addr + reg);
1368 writel((write & mask), (adapter->hw.hw_addr + reg));
1369 val = readl(adapter->hw.hw_addr + reg);
1370 if ((write & mask) != (val & mask)) {
1371 e_err(drv, "set/check reg %04X test failed: got 0x%08X "
1372 "expected 0x%08X\n", reg, (val & mask), (write & mask));
1374 writel(before, (adapter->hw.hw_addr + reg));
1377 writel(before, (adapter->hw.hw_addr + reg));
1381 #define REG_PATTERN_TEST(reg, mask, write) \
1383 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1388 #define REG_SET_AND_CHECK(reg, mask, write) \
1390 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1394 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1396 const struct ixgbe_reg_test *test;
1397 u32 value, before, after;
1400 switch (adapter->hw.mac.type) {
1401 case ixgbe_mac_82598EB:
1402 toggle = 0x7FFFF3FF;
1403 test = reg_test_82598;
1405 case ixgbe_mac_82599EB:
1406 case ixgbe_mac_X540:
1407 toggle = 0x7FFFF30F;
1408 test = reg_test_82599;
1417 * Because the status register is such a special case,
1418 * we handle it separately from the rest of the register
1419 * tests. Some bits are read-only, some toggle, and some
1420 * are writeable on newer MACs.
1422 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1423 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1424 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1425 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1426 if (value != after) {
1427 e_err(drv, "failed STATUS register test got: 0x%08X "
1428 "expected: 0x%08X\n", after, value);
1432 /* restore previous status */
1433 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1436 * Perform the remainder of the register test, looping through
1437 * the test table until we either fail or reach the null entry.
1440 for (i = 0; i < test->array_len; i++) {
1441 switch (test->test_type) {
1443 REG_PATTERN_TEST(test->reg + (i * 0x40),
1448 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1454 (adapter->hw.hw_addr + test->reg)
1458 REG_PATTERN_TEST(test->reg + (i * 4),
1462 case TABLE64_TEST_LO:
1463 REG_PATTERN_TEST(test->reg + (i * 8),
1467 case TABLE64_TEST_HI:
1468 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1481 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1483 struct ixgbe_hw *hw = &adapter->hw;
1484 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1491 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1493 struct net_device *netdev = (struct net_device *) data;
1494 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1496 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1501 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1503 struct net_device *netdev = adapter->netdev;
1504 u32 mask, i = 0, shared_int = true;
1505 u32 irq = adapter->pdev->irq;
1509 /* Hook up test interrupt handler just for this test */
1510 if (adapter->msix_entries) {
1511 /* NOTE: we don't test MSI-X interrupts here, yet */
1513 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1515 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
1520 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
1521 netdev->name, netdev)) {
1523 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
1524 netdev->name, netdev)) {
1528 e_info(hw, "testing %s interrupt\n", shared_int ?
1529 "shared" : "unshared");
1531 /* Disable all the interrupts */
1532 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1533 IXGBE_WRITE_FLUSH(&adapter->hw);
1534 usleep_range(10000, 20000);
1536 /* Test each interrupt */
1537 for (; i < 10; i++) {
1538 /* Interrupt to test */
1543 * Disable the interrupts to be reported in
1544 * the cause register and then force the same
1545 * interrupt and see if one gets posted. If
1546 * an interrupt was posted to the bus, the
1549 adapter->test_icr = 0;
1550 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1551 ~mask & 0x00007FFF);
1552 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1553 ~mask & 0x00007FFF);
1554 IXGBE_WRITE_FLUSH(&adapter->hw);
1555 usleep_range(10000, 20000);
1557 if (adapter->test_icr & mask) {
1564 * Enable the interrupt to be reported in the cause
1565 * register and then force the same interrupt and see
1566 * if one gets posted. If an interrupt was not posted
1567 * to the bus, the test failed.
1569 adapter->test_icr = 0;
1570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1571 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1572 IXGBE_WRITE_FLUSH(&adapter->hw);
1573 usleep_range(10000, 20000);
1575 if (!(adapter->test_icr &mask)) {
1582 * Disable the other interrupts to be reported in
1583 * the cause register and then force the other
1584 * interrupts and see if any get posted. If
1585 * an interrupt was posted to the bus, the
1588 adapter->test_icr = 0;
1589 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1590 ~mask & 0x00007FFF);
1591 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1592 ~mask & 0x00007FFF);
1593 IXGBE_WRITE_FLUSH(&adapter->hw);
1594 usleep_range(10000, 20000);
1596 if (adapter->test_icr) {
1603 /* Disable all the interrupts */
1604 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1605 IXGBE_WRITE_FLUSH(&adapter->hw);
1606 usleep_range(10000, 20000);
1608 /* Unhook test interrupt handler */
1609 free_irq(irq, netdev);
1614 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1616 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1617 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1618 struct ixgbe_hw *hw = &adapter->hw;
1621 /* shut down the DMA engines now so they can be reinitialized later */
1624 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1625 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1626 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1627 ixgbe_disable_rx_queue(adapter, rx_ring);
1630 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
1631 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1632 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1634 switch (hw->mac.type) {
1635 case ixgbe_mac_82599EB:
1636 case ixgbe_mac_X540:
1637 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1638 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1639 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1645 ixgbe_reset(adapter);
1647 ixgbe_free_tx_resources(&adapter->test_tx_ring);
1648 ixgbe_free_rx_resources(&adapter->test_rx_ring);
1651 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1653 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1654 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1659 /* Setup Tx descriptor ring and Tx buffers */
1660 tx_ring->count = IXGBE_DEFAULT_TXD;
1661 tx_ring->queue_index = 0;
1662 tx_ring->dev = &adapter->pdev->dev;
1663 tx_ring->netdev = adapter->netdev;
1664 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
1666 err = ixgbe_setup_tx_resources(tx_ring);
1670 switch (adapter->hw.mac.type) {
1671 case ixgbe_mac_82599EB:
1672 case ixgbe_mac_X540:
1673 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1674 reg_data |= IXGBE_DMATXCTL_TE;
1675 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1681 ixgbe_configure_tx_ring(adapter, tx_ring);
1683 /* Setup Rx Descriptor ring and Rx buffers */
1684 rx_ring->count = IXGBE_DEFAULT_RXD;
1685 rx_ring->queue_index = 0;
1686 rx_ring->dev = &adapter->pdev->dev;
1687 rx_ring->netdev = adapter->netdev;
1688 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
1690 err = ixgbe_setup_rx_resources(rx_ring);
1696 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1697 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1699 ixgbe_configure_rx_ring(adapter, rx_ring);
1701 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1702 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1707 ixgbe_free_desc_rings(adapter);
1711 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1713 struct ixgbe_hw *hw = &adapter->hw;
1717 /* Setup MAC loopback */
1718 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1719 reg_data |= IXGBE_HLREG0_LPBK;
1720 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
1722 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1723 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1724 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
1726 /* X540 needs to set the MACC.FLU bit to force link up */
1727 if (adapter->hw.mac.type == ixgbe_mac_X540) {
1728 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
1729 reg_data |= IXGBE_MACC_FLU;
1730 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
1732 if (hw->mac.orig_autoc) {
1733 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU;
1734 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
1739 IXGBE_WRITE_FLUSH(hw);
1740 usleep_range(10000, 20000);
1742 /* Disable Atlas Tx lanes; re-enabled in reset path */
1743 if (hw->mac.type == ixgbe_mac_82598EB) {
1746 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1747 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1748 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1750 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1751 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1752 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1754 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1755 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1756 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1758 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1759 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1760 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1766 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1770 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1771 reg_data &= ~IXGBE_HLREG0_LPBK;
1772 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1775 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1776 unsigned int frame_size)
1778 memset(skb->data, 0xFF, frame_size);
1780 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1);
1781 memset(&skb->data[frame_size + 10], 0xBE, 1);
1782 memset(&skb->data[frame_size + 12], 0xAF, 1);
1785 static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer,
1786 unsigned int frame_size)
1788 unsigned char *data;
1793 data = kmap(rx_buffer->page) + rx_buffer->page_offset;
1795 if (data[3] != 0xFF ||
1796 data[frame_size + 10] != 0xBE ||
1797 data[frame_size + 12] != 0xAF)
1800 kunmap(rx_buffer->page);
1805 static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
1806 struct ixgbe_ring *tx_ring,
1809 union ixgbe_adv_rx_desc *rx_desc;
1810 struct ixgbe_rx_buffer *rx_buffer;
1811 struct ixgbe_tx_buffer *tx_buffer;
1812 u16 rx_ntc, tx_ntc, count = 0;
1814 /* initialize next to clean and descriptor values */
1815 rx_ntc = rx_ring->next_to_clean;
1816 tx_ntc = tx_ring->next_to_clean;
1817 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
1819 while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) {
1820 /* check Rx buffer */
1821 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc];
1823 /* sync Rx buffer for CPU read */
1824 dma_sync_single_for_cpu(rx_ring->dev,
1826 ixgbe_rx_bufsz(rx_ring),
1829 /* verify contents of skb */
1830 if (ixgbe_check_lbtest_frame(rx_buffer, size))
1833 /* sync Rx buffer for device write */
1834 dma_sync_single_for_device(rx_ring->dev,
1836 ixgbe_rx_bufsz(rx_ring),
1839 /* unmap buffer on Tx side */
1840 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc];
1841 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
1843 /* increment Rx/Tx next to clean counters */
1845 if (rx_ntc == rx_ring->count)
1848 if (tx_ntc == tx_ring->count)
1851 /* fetch next descriptor */
1852 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
1855 netdev_tx_reset_queue(txring_txq(tx_ring));
1857 /* re-map buffers to ring, store next to clean values */
1858 ixgbe_alloc_rx_buffers(rx_ring, count);
1859 rx_ring->next_to_clean = rx_ntc;
1860 tx_ring->next_to_clean = tx_ntc;
1865 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1867 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1868 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1869 int i, j, lc, good_cnt, ret_val = 0;
1870 unsigned int size = 1024;
1871 netdev_tx_t tx_ret_val;
1872 struct sk_buff *skb;
1873 u32 flags_orig = adapter->flags;
1875 /* DCB can modify the frames on Tx */
1876 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
1878 /* allocate test skb */
1879 skb = alloc_skb(size, GFP_KERNEL);
1883 /* place data into test skb */
1884 ixgbe_create_lbtest_frame(skb, size);
1888 * Calculate the loop count based on the largest descriptor ring
1889 * The idea is to wrap the largest ring a number of times using 64
1890 * send/receive pairs during each loop
1893 if (rx_ring->count <= tx_ring->count)
1894 lc = ((tx_ring->count / 64) * 2) + 1;
1896 lc = ((rx_ring->count / 64) * 2) + 1;
1898 for (j = 0; j <= lc; j++) {
1899 /* reset count of good packets */
1902 /* place 64 packets on the transmit queue*/
1903 for (i = 0; i < 64; i++) {
1905 tx_ret_val = ixgbe_xmit_frame_ring(skb,
1908 if (tx_ret_val == NETDEV_TX_OK)
1912 if (good_cnt != 64) {
1917 /* allow 200 milliseconds for packets to go from Tx to Rx */
1920 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
1921 if (good_cnt != 64) {
1927 /* free the original skb */
1929 adapter->flags = flags_orig;
1934 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1936 *data = ixgbe_setup_desc_rings(adapter);
1939 *data = ixgbe_setup_loopback_test(adapter);
1942 *data = ixgbe_run_loopback_test(adapter);
1943 ixgbe_loopback_cleanup(adapter);
1946 ixgbe_free_desc_rings(adapter);
1951 static void ixgbe_diag_test(struct net_device *netdev,
1952 struct ethtool_test *eth_test, u64 *data)
1954 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1955 bool if_running = netif_running(netdev);
1957 set_bit(__IXGBE_TESTING, &adapter->state);
1958 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1959 struct ixgbe_hw *hw = &adapter->hw;
1961 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1963 for (i = 0; i < adapter->num_vfs; i++) {
1964 if (adapter->vfinfo[i].clear_to_send) {
1965 netdev_warn(netdev, "%s",
1966 "offline diagnostic is not "
1967 "supported when VFs are "
1973 eth_test->flags |= ETH_TEST_FL_FAILED;
1974 clear_bit(__IXGBE_TESTING,
1982 e_info(hw, "offline testing starting\n");
1984 /* Link test performed before hardware reset so autoneg doesn't
1985 * interfere with test result
1987 if (ixgbe_link_test(adapter, &data[4]))
1988 eth_test->flags |= ETH_TEST_FL_FAILED;
1991 /* indicate we're in test mode */
1994 ixgbe_reset(adapter);
1996 e_info(hw, "register testing starting\n");
1997 if (ixgbe_reg_test(adapter, &data[0]))
1998 eth_test->flags |= ETH_TEST_FL_FAILED;
2000 ixgbe_reset(adapter);
2001 e_info(hw, "eeprom testing starting\n");
2002 if (ixgbe_eeprom_test(adapter, &data[1]))
2003 eth_test->flags |= ETH_TEST_FL_FAILED;
2005 ixgbe_reset(adapter);
2006 e_info(hw, "interrupt testing starting\n");
2007 if (ixgbe_intr_test(adapter, &data[2]))
2008 eth_test->flags |= ETH_TEST_FL_FAILED;
2010 /* If SRIOV or VMDq is enabled then skip MAC
2011 * loopback diagnostic. */
2012 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
2013 IXGBE_FLAG_VMDQ_ENABLED)) {
2014 e_info(hw, "Skip MAC loopback diagnostic in VT "
2020 ixgbe_reset(adapter);
2021 e_info(hw, "loopback testing starting\n");
2022 if (ixgbe_loopback_test(adapter, &data[3]))
2023 eth_test->flags |= ETH_TEST_FL_FAILED;
2026 ixgbe_reset(adapter);
2028 /* clear testing bit and return adapter to previous state */
2029 clear_bit(__IXGBE_TESTING, &adapter->state);
2032 else if (hw->mac.ops.disable_tx_laser)
2033 hw->mac.ops.disable_tx_laser(hw);
2035 e_info(hw, "online testing starting\n");
2038 if (ixgbe_link_test(adapter, &data[4]))
2039 eth_test->flags |= ETH_TEST_FL_FAILED;
2041 /* Offline tests aren't run; pass by default */
2047 clear_bit(__IXGBE_TESTING, &adapter->state);
2051 msleep_interruptible(4 * 1000);
2054 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
2055 struct ethtool_wolinfo *wol)
2057 struct ixgbe_hw *hw = &adapter->hw;
2060 /* WOL not supported for all devices */
2061 if (!ixgbe_wol_supported(adapter, hw->device_id,
2062 hw->subsystem_device_id)) {
2070 static void ixgbe_get_wol(struct net_device *netdev,
2071 struct ethtool_wolinfo *wol)
2073 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2075 wol->supported = WAKE_UCAST | WAKE_MCAST |
2076 WAKE_BCAST | WAKE_MAGIC;
2079 if (ixgbe_wol_exclusion(adapter, wol) ||
2080 !device_can_wakeup(&adapter->pdev->dev))
2083 if (adapter->wol & IXGBE_WUFC_EX)
2084 wol->wolopts |= WAKE_UCAST;
2085 if (adapter->wol & IXGBE_WUFC_MC)
2086 wol->wolopts |= WAKE_MCAST;
2087 if (adapter->wol & IXGBE_WUFC_BC)
2088 wol->wolopts |= WAKE_BCAST;
2089 if (adapter->wol & IXGBE_WUFC_MAG)
2090 wol->wolopts |= WAKE_MAGIC;
2093 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2095 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2097 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
2100 if (ixgbe_wol_exclusion(adapter, wol))
2101 return wol->wolopts ? -EOPNOTSUPP : 0;
2105 if (wol->wolopts & WAKE_UCAST)
2106 adapter->wol |= IXGBE_WUFC_EX;
2107 if (wol->wolopts & WAKE_MCAST)
2108 adapter->wol |= IXGBE_WUFC_MC;
2109 if (wol->wolopts & WAKE_BCAST)
2110 adapter->wol |= IXGBE_WUFC_BC;
2111 if (wol->wolopts & WAKE_MAGIC)
2112 adapter->wol |= IXGBE_WUFC_MAG;
2114 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2119 static int ixgbe_nway_reset(struct net_device *netdev)
2121 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2123 if (netif_running(netdev))
2124 ixgbe_reinit_locked(adapter);
2129 static int ixgbe_set_phys_id(struct net_device *netdev,
2130 enum ethtool_phys_id_state state)
2132 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2133 struct ixgbe_hw *hw = &adapter->hw;
2136 case ETHTOOL_ID_ACTIVE:
2137 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2141 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
2144 case ETHTOOL_ID_OFF:
2145 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
2148 case ETHTOOL_ID_INACTIVE:
2149 /* Restore LED settings */
2150 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2157 static int ixgbe_get_coalesce(struct net_device *netdev,
2158 struct ethtool_coalesce *ec)
2160 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2162 /* only valid if in constant ITR mode */
2163 if (adapter->rx_itr_setting <= 1)
2164 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2166 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2168 /* if in mixed tx/rx queues per vector mode, report only rx settings */
2169 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2172 /* only valid if in constant ITR mode */
2173 if (adapter->tx_itr_setting <= 1)
2174 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2176 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2182 * this function must be called before setting the new value of
2185 static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter)
2187 struct net_device *netdev = adapter->netdev;
2189 /* nothing to do if LRO or RSC are not enabled */
2190 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) ||
2191 !(netdev->features & NETIF_F_LRO))
2194 /* check the feature flag value and enable RSC if necessary */
2195 if (adapter->rx_itr_setting == 1 ||
2196 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
2197 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
2198 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
2199 e_info(probe, "rx-usecs value high enough "
2200 "to re-enable RSC\n");
2203 /* if interrupt rate is too high then disable RSC */
2204 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2205 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2206 e_info(probe, "rx-usecs set too low, disabling RSC\n");
2212 static int ixgbe_set_coalesce(struct net_device *netdev,
2213 struct ethtool_coalesce *ec)
2215 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2216 struct ixgbe_q_vector *q_vector;
2218 u16 tx_itr_param, rx_itr_param, tx_itr_prev;
2219 bool need_reset = false;
2221 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) {
2222 /* reject Tx specific changes in case of mixed RxTx vectors */
2223 if (ec->tx_coalesce_usecs)
2225 tx_itr_prev = adapter->rx_itr_setting;
2227 tx_itr_prev = adapter->tx_itr_setting;
2230 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) ||
2231 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)))
2234 if (ec->rx_coalesce_usecs > 1)
2235 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2237 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2239 if (adapter->rx_itr_setting == 1)
2240 rx_itr_param = IXGBE_20K_ITR;
2242 rx_itr_param = adapter->rx_itr_setting;
2244 if (ec->tx_coalesce_usecs > 1)
2245 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2247 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2249 if (adapter->tx_itr_setting == 1)
2250 tx_itr_param = IXGBE_10K_ITR;
2252 tx_itr_param = adapter->tx_itr_setting;
2255 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2256 adapter->tx_itr_setting = adapter->rx_itr_setting;
2258 #if IS_ENABLED(CONFIG_BQL)
2259 /* detect ITR changes that require update of TXDCTL.WTHRESH */
2260 if ((adapter->tx_itr_setting != 1) &&
2261 (adapter->tx_itr_setting < IXGBE_100K_ITR)) {
2262 if ((tx_itr_prev == 1) ||
2263 (tx_itr_prev >= IXGBE_100K_ITR))
2266 if ((tx_itr_prev != 1) &&
2267 (tx_itr_prev < IXGBE_100K_ITR))
2271 /* check the old value and enable RSC if necessary */
2272 need_reset |= ixgbe_update_rsc(adapter);
2274 for (i = 0; i < adapter->num_q_vectors; i++) {
2275 q_vector = adapter->q_vector[i];
2276 if (q_vector->tx.count && !q_vector->rx.count)
2278 q_vector->itr = tx_itr_param;
2280 /* rx only or mixed */
2281 q_vector->itr = rx_itr_param;
2282 ixgbe_write_eitr(q_vector);
2286 * do reset here at the end to make sure EITR==0 case is handled
2287 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2288 * also locks in RSC enable/disable which requires reset
2291 ixgbe_do_reset(netdev);
2296 static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2297 struct ethtool_rxnfc *cmd)
2299 union ixgbe_atr_input *mask = &adapter->fdir_mask;
2300 struct ethtool_rx_flow_spec *fsp =
2301 (struct ethtool_rx_flow_spec *)&cmd->fs;
2302 struct hlist_node *node2;
2303 struct ixgbe_fdir_filter *rule = NULL;
2305 /* report total rule count */
2306 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2308 hlist_for_each_entry_safe(rule, node2,
2309 &adapter->fdir_filter_list, fdir_node) {
2310 if (fsp->location <= rule->sw_idx)
2314 if (!rule || fsp->location != rule->sw_idx)
2317 /* fill out the flow spec entry */
2319 /* set flow type field */
2320 switch (rule->filter.formatted.flow_type) {
2321 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2322 fsp->flow_type = TCP_V4_FLOW;
2324 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2325 fsp->flow_type = UDP_V4_FLOW;
2327 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2328 fsp->flow_type = SCTP_V4_FLOW;
2330 case IXGBE_ATR_FLOW_TYPE_IPV4:
2331 fsp->flow_type = IP_USER_FLOW;
2332 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2333 fsp->h_u.usr_ip4_spec.proto = 0;
2334 fsp->m_u.usr_ip4_spec.proto = 0;
2340 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2341 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2342 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2343 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2344 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2345 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2346 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2347 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2348 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2349 fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2350 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2351 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2352 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2353 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2354 fsp->flow_type |= FLOW_EXT;
2357 if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2358 fsp->ring_cookie = RX_CLS_FLOW_DISC;
2360 fsp->ring_cookie = rule->action;
2365 static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2366 struct ethtool_rxnfc *cmd,
2369 struct hlist_node *node2;
2370 struct ixgbe_fdir_filter *rule;
2373 /* report total rule count */
2374 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2376 hlist_for_each_entry_safe(rule, node2,
2377 &adapter->fdir_filter_list, fdir_node) {
2378 if (cnt == cmd->rule_cnt)
2380 rule_locs[cnt] = rule->sw_idx;
2384 cmd->rule_cnt = cnt;
2389 static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter,
2390 struct ethtool_rxnfc *cmd)
2394 /* Report default options for RSS on ixgbe */
2395 switch (cmd->flow_type) {
2397 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2399 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2400 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2402 case AH_ESP_V4_FLOW:
2406 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2409 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2411 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2412 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2414 case AH_ESP_V6_FLOW:
2418 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2427 static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2430 struct ixgbe_adapter *adapter = netdev_priv(dev);
2431 int ret = -EOPNOTSUPP;
2434 case ETHTOOL_GRXRINGS:
2435 cmd->data = adapter->num_rx_queues;
2438 case ETHTOOL_GRXCLSRLCNT:
2439 cmd->rule_cnt = adapter->fdir_filter_count;
2442 case ETHTOOL_GRXCLSRULE:
2443 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2445 case ETHTOOL_GRXCLSRLALL:
2446 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs);
2449 ret = ixgbe_get_rss_hash_opts(adapter, cmd);
2458 static int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2459 struct ixgbe_fdir_filter *input,
2462 struct ixgbe_hw *hw = &adapter->hw;
2463 struct hlist_node *node2;
2464 struct ixgbe_fdir_filter *rule, *parent;
2470 hlist_for_each_entry_safe(rule, node2,
2471 &adapter->fdir_filter_list, fdir_node) {
2472 /* hash found, or no matching entry */
2473 if (rule->sw_idx >= sw_idx)
2478 /* if there is an old rule occupying our place remove it */
2479 if (rule && (rule->sw_idx == sw_idx)) {
2480 if (!input || (rule->filter.formatted.bkt_hash !=
2481 input->filter.formatted.bkt_hash)) {
2482 err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2487 hlist_del(&rule->fdir_node);
2489 adapter->fdir_filter_count--;
2493 * If no input this was a delete, err should be 0 if a rule was
2494 * successfully found and removed from the list else -EINVAL
2499 /* initialize node and set software index */
2500 INIT_HLIST_NODE(&input->fdir_node);
2502 /* add filter to the list */
2504 hlist_add_after(&parent->fdir_node, &input->fdir_node);
2506 hlist_add_head(&input->fdir_node,
2507 &adapter->fdir_filter_list);
2510 adapter->fdir_filter_count++;
2515 static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2518 switch (fsp->flow_type & ~FLOW_EXT) {
2520 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2523 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2526 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2529 switch (fsp->h_u.usr_ip4_spec.proto) {
2531 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2534 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2537 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2540 if (!fsp->m_u.usr_ip4_spec.proto) {
2541 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2555 static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2556 struct ethtool_rxnfc *cmd)
2558 struct ethtool_rx_flow_spec *fsp =
2559 (struct ethtool_rx_flow_spec *)&cmd->fs;
2560 struct ixgbe_hw *hw = &adapter->hw;
2561 struct ixgbe_fdir_filter *input;
2562 union ixgbe_atr_input mask;
2565 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2569 * Don't allow programming if the action is a queue greater than
2570 * the number of online Rx queues.
2572 if ((fsp->ring_cookie != RX_CLS_FLOW_DISC) &&
2573 (fsp->ring_cookie >= adapter->num_rx_queues))
2576 /* Don't allow indexes to exist outside of available space */
2577 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2578 e_err(drv, "Location out of range\n");
2582 input = kzalloc(sizeof(*input), GFP_ATOMIC);
2586 memset(&mask, 0, sizeof(union ixgbe_atr_input));
2589 input->sw_idx = fsp->location;
2591 /* record flow type */
2592 if (!ixgbe_flowspec_to_flow_type(fsp,
2593 &input->filter.formatted.flow_type)) {
2594 e_err(drv, "Unrecognized flow type\n");
2598 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2599 IXGBE_ATR_L4TYPE_MASK;
2601 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2602 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2604 /* Copy input into formatted structures */
2605 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2606 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2607 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2608 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2609 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2610 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2611 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2612 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2614 if (fsp->flow_type & FLOW_EXT) {
2615 input->filter.formatted.vm_pool =
2616 (unsigned char)ntohl(fsp->h_ext.data[1]);
2617 mask.formatted.vm_pool =
2618 (unsigned char)ntohl(fsp->m_ext.data[1]);
2619 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2620 mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2621 input->filter.formatted.flex_bytes =
2622 fsp->h_ext.vlan_etype;
2623 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2626 /* determine if we need to drop or route the packet */
2627 if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2628 input->action = IXGBE_FDIR_DROP_QUEUE;
2630 input->action = fsp->ring_cookie;
2632 spin_lock(&adapter->fdir_perfect_lock);
2634 if (hlist_empty(&adapter->fdir_filter_list)) {
2635 /* save mask and program input mask into HW */
2636 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2637 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
2639 e_err(drv, "Error writing mask\n");
2640 goto err_out_w_lock;
2642 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
2643 e_err(drv, "Only one mask supported per port\n");
2644 goto err_out_w_lock;
2647 /* apply mask and compute/store hash */
2648 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
2650 /* program filters to filter memory */
2651 err = ixgbe_fdir_write_perfect_filter_82599(hw,
2652 &input->filter, input->sw_idx,
2653 (input->action == IXGBE_FDIR_DROP_QUEUE) ?
2654 IXGBE_FDIR_DROP_QUEUE :
2655 adapter->rx_ring[input->action]->reg_idx);
2657 goto err_out_w_lock;
2659 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
2661 spin_unlock(&adapter->fdir_perfect_lock);
2665 spin_unlock(&adapter->fdir_perfect_lock);
2671 static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2672 struct ethtool_rxnfc *cmd)
2674 struct ethtool_rx_flow_spec *fsp =
2675 (struct ethtool_rx_flow_spec *)&cmd->fs;
2678 spin_lock(&adapter->fdir_perfect_lock);
2679 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location);
2680 spin_unlock(&adapter->fdir_perfect_lock);
2685 #define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \
2686 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2687 static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter,
2688 struct ethtool_rxnfc *nfc)
2690 u32 flags2 = adapter->flags2;
2693 * RSS does not support anything other than hashing
2694 * to queues on src and dst IPs and ports
2696 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2697 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2700 switch (nfc->flow_type) {
2703 if (!(nfc->data & RXH_IP_SRC) ||
2704 !(nfc->data & RXH_IP_DST) ||
2705 !(nfc->data & RXH_L4_B_0_1) ||
2706 !(nfc->data & RXH_L4_B_2_3))
2710 if (!(nfc->data & RXH_IP_SRC) ||
2711 !(nfc->data & RXH_IP_DST))
2713 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2715 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2717 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2718 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2725 if (!(nfc->data & RXH_IP_SRC) ||
2726 !(nfc->data & RXH_IP_DST))
2728 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2730 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2732 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2733 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2739 case AH_ESP_V4_FLOW:
2743 case AH_ESP_V6_FLOW:
2747 if (!(nfc->data & RXH_IP_SRC) ||
2748 !(nfc->data & RXH_IP_DST) ||
2749 (nfc->data & RXH_L4_B_0_1) ||
2750 (nfc->data & RXH_L4_B_2_3))
2757 /* if we changed something we need to update flags */
2758 if (flags2 != adapter->flags2) {
2759 struct ixgbe_hw *hw = &adapter->hw;
2760 u32 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2762 if ((flags2 & UDP_RSS_FLAGS) &&
2763 !(adapter->flags2 & UDP_RSS_FLAGS))
2764 e_warn(drv, "enabling UDP RSS: fragmented packets"
2765 " may arrive out of order to the stack above\n");
2767 adapter->flags2 = flags2;
2769 /* Perform hash on these packet types */
2770 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2771 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2772 | IXGBE_MRQC_RSS_FIELD_IPV6
2773 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2775 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
2776 IXGBE_MRQC_RSS_FIELD_IPV6_UDP);
2778 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2779 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2781 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2782 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2784 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2790 static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2792 struct ixgbe_adapter *adapter = netdev_priv(dev);
2793 int ret = -EOPNOTSUPP;
2796 case ETHTOOL_SRXCLSRLINS:
2797 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
2799 case ETHTOOL_SRXCLSRLDEL:
2800 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
2803 ret = ixgbe_set_rss_hash_opt(adapter, cmd);
2812 static int ixgbe_get_ts_info(struct net_device *dev,
2813 struct ethtool_ts_info *info)
2815 struct ixgbe_adapter *adapter = netdev_priv(dev);
2817 switch (adapter->hw.mac.type) {
2818 case ixgbe_mac_X540:
2819 case ixgbe_mac_82599EB:
2820 info->so_timestamping =
2821 SOF_TIMESTAMPING_TX_SOFTWARE |
2822 SOF_TIMESTAMPING_RX_SOFTWARE |
2823 SOF_TIMESTAMPING_SOFTWARE |
2824 SOF_TIMESTAMPING_TX_HARDWARE |
2825 SOF_TIMESTAMPING_RX_HARDWARE |
2826 SOF_TIMESTAMPING_RAW_HARDWARE;
2828 if (adapter->ptp_clock)
2829 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2831 info->phc_index = -1;
2834 (1 << HWTSTAMP_TX_OFF) |
2835 (1 << HWTSTAMP_TX_ON);
2838 (1 << HWTSTAMP_FILTER_NONE) |
2839 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2840 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2841 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2842 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2843 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
2844 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2845 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2846 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
2847 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
2848 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
2849 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2852 return ethtool_op_get_ts_info(dev, info);
2858 static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter)
2860 unsigned int max_combined;
2861 u8 tcs = netdev_get_num_tc(adapter->netdev);
2863 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2864 /* We only support one q_vector without MSI-X */
2866 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2867 /* SR-IOV currently only allows one queue on the PF */
2869 } else if (tcs > 1) {
2870 /* For DCB report channels per traffic class */
2871 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2872 /* 8 TC w/ 4 queues per TC */
2874 } else if (tcs > 4) {
2875 /* 8 TC w/ 8 queues per TC */
2878 /* 4 TC w/ 16 queues per TC */
2881 } else if (adapter->atr_sample_rate) {
2882 /* support up to 64 queues with ATR */
2883 max_combined = IXGBE_MAX_FDIR_INDICES;
2885 /* support up to 16 queues with RSS */
2886 max_combined = IXGBE_MAX_RSS_INDICES;
2889 return max_combined;
2892 static void ixgbe_get_channels(struct net_device *dev,
2893 struct ethtool_channels *ch)
2895 struct ixgbe_adapter *adapter = netdev_priv(dev);
2897 /* report maximum channels */
2898 ch->max_combined = ixgbe_max_channels(adapter);
2900 /* report info for other vector */
2901 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2902 ch->max_other = NON_Q_VECTORS;
2903 ch->other_count = NON_Q_VECTORS;
2906 /* record RSS queues */
2907 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices;
2909 /* nothing else to report if RSS is disabled */
2910 if (ch->combined_count == 1)
2913 /* we do not support ATR queueing if SR-IOV is enabled */
2914 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
2917 /* same thing goes for being DCB enabled */
2918 if (netdev_get_num_tc(dev) > 1)
2921 /* if ATR is disabled we can exit */
2922 if (!adapter->atr_sample_rate)
2925 /* report flow director queues as maximum channels */
2926 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices;
2929 static int ixgbe_set_channels(struct net_device *dev,
2930 struct ethtool_channels *ch)
2932 struct ixgbe_adapter *adapter = netdev_priv(dev);
2933 unsigned int count = ch->combined_count;
2935 /* verify they are not requesting separate vectors */
2936 if (!count || ch->rx_count || ch->tx_count)
2939 /* verify other_count has not changed */
2940 if (ch->other_count != NON_Q_VECTORS)
2943 /* verify the number of channels does not exceed hardware limits */
2944 if (count > ixgbe_max_channels(adapter))
2947 /* update feature limits from largest to smallest supported values */
2948 adapter->ring_feature[RING_F_FDIR].limit = count;
2950 /* cap RSS limit at 16 */
2951 if (count > IXGBE_MAX_RSS_INDICES)
2952 count = IXGBE_MAX_RSS_INDICES;
2953 adapter->ring_feature[RING_F_RSS].limit = count;
2956 /* cap FCoE limit at 8 */
2957 if (count > IXGBE_FCRETA_SIZE)
2958 count = IXGBE_FCRETA_SIZE;
2959 adapter->ring_feature[RING_F_FCOE].limit = count;
2962 /* use setup TC to update any traffic class queue mapping */
2963 return ixgbe_setup_tc(dev, netdev_get_num_tc(dev));
2966 static int ixgbe_get_module_info(struct net_device *dev,
2967 struct ethtool_modinfo *modinfo)
2969 struct ixgbe_adapter *adapter = netdev_priv(dev);
2970 struct ixgbe_hw *hw = &adapter->hw;
2972 u8 sff8472_rev, addr_mode;
2973 bool page_swap = false;
2975 /* Check whether we support SFF-8472 or not */
2976 status = hw->phy.ops.read_i2c_eeprom(hw,
2977 IXGBE_SFF_SFF_8472_COMP,
2982 /* addressing mode is not supported */
2983 status = hw->phy.ops.read_i2c_eeprom(hw,
2984 IXGBE_SFF_SFF_8472_SWAP,
2989 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
2990 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
2994 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
2995 /* We have a SFP, but it does not support SFF-8472 */
2996 modinfo->type = ETH_MODULE_SFF_8079;
2997 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
2999 /* We have a SFP which supports a revision of SFF-8472. */
3000 modinfo->type = ETH_MODULE_SFF_8472;
3001 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3007 static int ixgbe_get_module_eeprom(struct net_device *dev,
3008 struct ethtool_eeprom *ee,
3011 struct ixgbe_adapter *adapter = netdev_priv(dev);
3012 struct ixgbe_hw *hw = &adapter->hw;
3013 u32 status = IXGBE_ERR_PHY_ADDR_INVALID;
3020 for (i = ee->offset; i < ee->offset + ee->len; i++) {
3021 /* I2C reads can take long time */
3022 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3025 if (i < ETH_MODULE_SFF_8079_LEN)
3026 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
3028 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
3033 data[i - ee->offset] = databyte;
3039 static const struct ethtool_ops ixgbe_ethtool_ops = {
3040 .get_settings = ixgbe_get_settings,
3041 .set_settings = ixgbe_set_settings,
3042 .get_drvinfo = ixgbe_get_drvinfo,
3043 .get_regs_len = ixgbe_get_regs_len,
3044 .get_regs = ixgbe_get_regs,
3045 .get_wol = ixgbe_get_wol,
3046 .set_wol = ixgbe_set_wol,
3047 .nway_reset = ixgbe_nway_reset,
3048 .get_link = ethtool_op_get_link,
3049 .get_eeprom_len = ixgbe_get_eeprom_len,
3050 .get_eeprom = ixgbe_get_eeprom,
3051 .set_eeprom = ixgbe_set_eeprom,
3052 .get_ringparam = ixgbe_get_ringparam,
3053 .set_ringparam = ixgbe_set_ringparam,
3054 .get_pauseparam = ixgbe_get_pauseparam,
3055 .set_pauseparam = ixgbe_set_pauseparam,
3056 .get_msglevel = ixgbe_get_msglevel,
3057 .set_msglevel = ixgbe_set_msglevel,
3058 .self_test = ixgbe_diag_test,
3059 .get_strings = ixgbe_get_strings,
3060 .set_phys_id = ixgbe_set_phys_id,
3061 .get_sset_count = ixgbe_get_sset_count,
3062 .get_ethtool_stats = ixgbe_get_ethtool_stats,
3063 .get_coalesce = ixgbe_get_coalesce,
3064 .set_coalesce = ixgbe_set_coalesce,
3065 .get_rxnfc = ixgbe_get_rxnfc,
3066 .set_rxnfc = ixgbe_set_rxnfc,
3067 .get_channels = ixgbe_get_channels,
3068 .set_channels = ixgbe_set_channels,
3069 .get_ts_info = ixgbe_get_ts_info,
3070 .get_module_info = ixgbe_get_module_info,
3071 .get_module_eeprom = ixgbe_get_module_eeprom,
3074 void ixgbe_set_ethtool_ops(struct net_device *netdev)
3076 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);