1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
32 #include <linux/bitops.h>
33 #include <linux/types.h>
34 #include <linux/pci.h>
35 #include <linux/netdevice.h>
36 #include <linux/cpumask.h>
37 #include <linux/aer.h>
38 #include <linux/if_vlan.h>
39 #include <linux/jiffies.h>
41 #include <linux/clocksource.h>
42 #include <linux/net_tstamp.h>
43 #include <linux/ptp_clock_kernel.h>
45 #include "ixgbe_type.h"
46 #include "ixgbe_common.h"
47 #include "ixgbe_dcb.h"
48 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
50 #include "ixgbe_fcoe.h"
51 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
52 #ifdef CONFIG_IXGBE_DCA
53 #include <linux/dca.h>
56 #include <net/busy_poll.h>
58 #ifdef CONFIG_NET_RX_BUSY_POLL
59 #define BP_EXTENDED_STATS
61 /* common prefix used by pr_<> macros */
63 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65 /* TX/RX descriptor defines */
66 #define IXGBE_DEFAULT_TXD 512
67 #define IXGBE_DEFAULT_TX_WORK 256
68 #define IXGBE_MAX_TXD 4096
69 #define IXGBE_MIN_TXD 64
71 #if (PAGE_SIZE < 8192)
72 #define IXGBE_DEFAULT_RXD 512
74 #define IXGBE_DEFAULT_RXD 128
76 #define IXGBE_MAX_RXD 4096
77 #define IXGBE_MIN_RXD 64
80 #define IXGBE_MIN_FCRTL 0x40
81 #define IXGBE_MAX_FCRTL 0x7FF80
82 #define IXGBE_MIN_FCRTH 0x600
83 #define IXGBE_MAX_FCRTH 0x7FFF0
84 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
85 #define IXGBE_MIN_FCPAUSE 0
86 #define IXGBE_MAX_FCPAUSE 0xFFFF
88 /* Supported Rx Buffer Sizes */
89 #define IXGBE_RXBUFFER_256 256 /* Used for skb receive header */
90 #define IXGBE_RXBUFFER_2K 2048
91 #define IXGBE_RXBUFFER_3K 3072
92 #define IXGBE_RXBUFFER_4K 4096
93 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
96 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
97 * reserve 64 more, and skb_shared_info adds an additional 320 bytes more,
98 * this adds up to 448 bytes of extra data.
100 * Since netdev_alloc_skb now allocates a page fragment we can use a value
101 * of 256 and the resultant skb will have a truesize of 960 or less.
103 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
105 /* How many Rx Buffers do we bundle into one write to the hardware ? */
106 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
108 enum ixgbe_tx_flags {
110 IXGBE_TX_FLAGS_HW_VLAN = 0x01,
111 IXGBE_TX_FLAGS_TSO = 0x02,
112 IXGBE_TX_FLAGS_TSTAMP = 0x04,
115 IXGBE_TX_FLAGS_CC = 0x08,
116 IXGBE_TX_FLAGS_IPV4 = 0x10,
117 IXGBE_TX_FLAGS_CSUM = 0x20,
119 /* software defined flags */
120 IXGBE_TX_FLAGS_SW_VLAN = 0x40,
121 IXGBE_TX_FLAGS_FCOE = 0x80,
125 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
126 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
127 #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
128 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
130 #define IXGBE_MAX_VF_MC_ENTRIES 30
131 #define IXGBE_MAX_VF_FUNCTIONS 64
132 #define IXGBE_MAX_VFTA_ENTRIES 128
133 #define MAX_EMULATION_MAC_ADDRS 16
134 #define IXGBE_MAX_PF_MACVLANS 15
135 #define VMDQ_P(p) ((p) + adapter->ring_feature[RING_F_VMDQ].offset)
136 #define IXGBE_82599_VF_DEVICE_ID 0x10ED
137 #define IXGBE_X540_VF_DEVICE_ID 0x1515
139 struct vf_data_storage {
140 unsigned char vf_mac_addresses[ETH_ALEN];
141 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
142 u16 num_vf_mc_hashes;
143 u16 default_vf_vlan_id;
147 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
160 u8 vf_macvlan[ETH_ALEN];
163 #define IXGBE_MAX_TXD_PWR 14
164 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
166 /* Tx Descriptors needed, worst case */
167 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
168 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
170 /* wrapper around a pointer to a socket buffer,
171 * so a DMA handle can be stored along with the buffer */
172 struct ixgbe_tx_buffer {
173 union ixgbe_adv_tx_desc *next_to_watch;
174 unsigned long time_stamp;
176 unsigned int bytecount;
177 unsigned short gso_segs;
179 DEFINE_DMA_UNMAP_ADDR(dma);
180 DEFINE_DMA_UNMAP_LEN(len);
184 struct ixgbe_rx_buffer {
188 unsigned int page_offset;
191 struct ixgbe_queue_stats {
194 #ifdef BP_EXTENDED_STATS
198 #endif /* BP_EXTENDED_STATS */
201 struct ixgbe_tx_queue_stats {
207 struct ixgbe_rx_queue_stats {
211 u64 alloc_rx_page_failed;
212 u64 alloc_rx_buff_failed;
216 enum ixgbe_ring_state_t {
217 __IXGBE_TX_FDIR_INIT_DONE,
218 __IXGBE_TX_XPS_INIT_DONE,
219 __IXGBE_TX_DETECT_HANG,
220 __IXGBE_HANG_CHECK_ARMED,
221 __IXGBE_RX_RSC_ENABLED,
222 __IXGBE_RX_CSUM_UDP_ZERO_ERR,
226 struct ixgbe_fwd_adapter {
227 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
228 struct net_device *netdev;
229 struct ixgbe_adapter *real_adapter;
230 unsigned int tx_base_queue;
231 unsigned int rx_base_queue;
235 #define check_for_tx_hang(ring) \
236 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
237 #define set_check_for_tx_hang(ring) \
238 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
239 #define clear_check_for_tx_hang(ring) \
240 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
241 #define ring_is_rsc_enabled(ring) \
242 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
243 #define set_ring_rsc_enabled(ring) \
244 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
245 #define clear_ring_rsc_enabled(ring) \
246 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
248 struct ixgbe_ring *next; /* pointer to next ring in q_vector */
249 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
250 struct net_device *netdev; /* netdev ring belongs to */
251 struct device *dev; /* device for DMA mapping */
252 struct ixgbe_fwd_adapter *l2_accel_priv;
253 void *desc; /* descriptor ring memory */
255 struct ixgbe_tx_buffer *tx_buffer_info;
256 struct ixgbe_rx_buffer *rx_buffer_info;
260 dma_addr_t dma; /* phys. address of descriptor ring */
261 unsigned int size; /* length in bytes */
263 u16 count; /* amount of descriptors */
265 u8 queue_index; /* needed for multiqueue queue management */
266 u8 reg_idx; /* holds the special value that gets
267 * the hardware register offset
268 * associated with this ring, which is
269 * different for DCB and RSS modes
283 struct ixgbe_queue_stats stats;
284 struct u64_stats_sync syncp;
286 struct ixgbe_tx_queue_stats tx_stats;
287 struct ixgbe_rx_queue_stats rx_stats;
289 } ____cacheline_internodealigned_in_smp;
291 enum ixgbe_ring_f_enum {
293 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
298 #endif /* IXGBE_FCOE */
300 RING_F_ARRAY_SIZE /* must be last in enum set */
303 #define IXGBE_MAX_RSS_INDICES 16
304 #define IXGBE_MAX_VMDQ_INDICES 64
305 #define IXGBE_MAX_FDIR_INDICES 63 /* based on q_vector limit */
306 #define IXGBE_MAX_FCOE_INDICES 8
307 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
308 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + 1)
309 #define IXGBE_MAX_L2A_QUEUES 4
310 #define IXGBE_MAX_L2A_QUEUES 4
311 #define IXGBE_BAD_L2A_QUEUE 3
312 #define IXGBE_MAX_MACVLANS 31
313 #define IXGBE_MAX_DCBMACVLANS 8
315 struct ixgbe_ring_feature {
316 u16 limit; /* upper limit on feature indices */
317 u16 indices; /* current value of indices */
318 u16 mask; /* Mask used for feature to ring mapping */
319 u16 offset; /* offset to start of feature */
320 } ____cacheline_internodealigned_in_smp;
322 #define IXGBE_82599_VMDQ_8Q_MASK 0x78
323 #define IXGBE_82599_VMDQ_4Q_MASK 0x7C
324 #define IXGBE_82599_VMDQ_2Q_MASK 0x7E
327 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
328 * this is twice the size of a half page we need to double the page order
329 * for FCoE enabled Rx queues.
331 static inline unsigned int ixgbe_rx_bufsz(struct ixgbe_ring *ring)
334 if (test_bit(__IXGBE_RX_FCOE, &ring->state))
335 return (PAGE_SIZE < 8192) ? IXGBE_RXBUFFER_4K :
338 return IXGBE_RXBUFFER_2K;
341 static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
344 if (test_bit(__IXGBE_RX_FCOE, &ring->state))
345 return (PAGE_SIZE < 8192) ? 1 : 0;
349 #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
351 struct ixgbe_ring_container {
352 struct ixgbe_ring *ring; /* pointer to linked list of rings */
353 unsigned int total_bytes; /* total bytes processed this int */
354 unsigned int total_packets; /* total packets processed this int */
355 u16 work_limit; /* total work allowed per interrupt */
356 u8 count; /* total number of rings in vector */
357 u8 itr; /* current ITR setting for ring */
360 /* iterator for handling rings in ring container */
361 #define ixgbe_for_each_ring(pos, head) \
362 for (pos = (head).ring; pos != NULL; pos = pos->next)
364 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
366 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
368 /* MAX_Q_VECTORS of these are allocated,
369 * but we only use one per queue-specific vector.
371 struct ixgbe_q_vector {
372 struct ixgbe_adapter *adapter;
373 #ifdef CONFIG_IXGBE_DCA
374 int cpu; /* CPU for DCA */
376 u16 v_idx; /* index of q_vector within array, also used for
377 * finding the bit in EICR and friends that
378 * represents the vector for this ring */
379 u16 itr; /* Interrupt throttle rate written to EITR */
380 struct ixgbe_ring_container rx, tx;
382 struct napi_struct napi;
383 cpumask_t affinity_mask;
385 struct rcu_head rcu; /* to avoid race with update stats on free */
386 char name[IFNAMSIZ + 9];
388 #ifdef CONFIG_NET_RX_BUSY_POLL
390 #endif /* CONFIG_NET_RX_BUSY_POLL */
392 /* for dynamic allocation of rings associated with this q_vector */
393 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
396 #ifdef CONFIG_NET_RX_BUSY_POLL
397 enum ixgbe_qv_state_t {
398 IXGBE_QV_STATE_IDLE = 0,
401 IXGBE_QV_STATE_DISABLE
404 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
406 /* reset state to idle */
407 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE);
410 /* called from the device poll routine to get ownership of a q_vector */
411 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector)
413 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE,
414 IXGBE_QV_STATE_NAPI);
415 #ifdef BP_EXTENDED_STATS
416 if (rc != IXGBE_QV_STATE_IDLE)
417 q_vector->tx.ring->stats.yields++;
420 return rc == IXGBE_QV_STATE_IDLE;
423 /* returns true is someone tried to get the qv while napi had it */
424 static inline void ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector)
426 WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_NAPI);
428 /* flush any outstanding Rx frames */
429 if (q_vector->napi.gro_list)
430 napi_gro_flush(&q_vector->napi, false);
432 /* reset state to idle */
433 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE);
436 /* called from ixgbe_low_latency_poll() */
437 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector)
439 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE,
440 IXGBE_QV_STATE_POLL);
441 #ifdef BP_EXTENDED_STATS
442 if (rc != IXGBE_QV_STATE_IDLE)
443 q_vector->tx.ring->stats.yields++;
445 return rc == IXGBE_QV_STATE_IDLE;
448 /* returns true if someone tried to get the qv while it was locked */
449 static inline void ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector)
451 WARN_ON(atomic_read(&q_vector->state) != IXGBE_QV_STATE_POLL);
453 /* reset state to idle */
454 atomic_set(&q_vector->state, IXGBE_QV_STATE_IDLE);
457 /* true if a socket is polling, even if it did not get the lock */
458 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector)
460 return atomic_read(&q_vector->state) == IXGBE_QV_STATE_POLL;
463 /* false if QV is currently owned */
464 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector)
466 int rc = atomic_cmpxchg(&q_vector->state, IXGBE_QV_STATE_IDLE,
467 IXGBE_QV_STATE_DISABLE);
469 return rc == IXGBE_QV_STATE_IDLE;
472 #else /* CONFIG_NET_RX_BUSY_POLL */
473 static inline void ixgbe_qv_init_lock(struct ixgbe_q_vector *q_vector)
477 static inline bool ixgbe_qv_lock_napi(struct ixgbe_q_vector *q_vector)
482 static inline bool ixgbe_qv_unlock_napi(struct ixgbe_q_vector *q_vector)
487 static inline bool ixgbe_qv_lock_poll(struct ixgbe_q_vector *q_vector)
492 static inline bool ixgbe_qv_unlock_poll(struct ixgbe_q_vector *q_vector)
497 static inline bool ixgbe_qv_busy_polling(struct ixgbe_q_vector *q_vector)
502 static inline bool ixgbe_qv_disable(struct ixgbe_q_vector *q_vector)
507 #endif /* CONFIG_NET_RX_BUSY_POLL */
509 #ifdef CONFIG_IXGBE_HWMON
511 #define IXGBE_HWMON_TYPE_LOC 0
512 #define IXGBE_HWMON_TYPE_TEMP 1
513 #define IXGBE_HWMON_TYPE_CAUTION 2
514 #define IXGBE_HWMON_TYPE_MAX 3
517 struct device_attribute dev_attr;
519 struct ixgbe_thermal_diode_data *sensor;
524 struct attribute_group group;
525 const struct attribute_group *groups[2];
526 struct attribute *attrs[IXGBE_MAX_SENSORS * 4 + 1];
527 struct hwmon_attr hwmon_list[IXGBE_MAX_SENSORS * 4];
528 unsigned int n_hwmon;
530 #endif /* CONFIG_IXGBE_HWMON */
533 * microsecond values for various ITR rates shifted by 2 to fit itr register
534 * with the first 3 bits reserved 0
536 #define IXGBE_MIN_RSC_ITR 24
537 #define IXGBE_100K_ITR 40
538 #define IXGBE_20K_ITR 200
539 #define IXGBE_10K_ITR 400
540 #define IXGBE_8K_ITR 500
542 /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
543 static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
544 const u32 stat_err_bits)
546 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
549 static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
551 u16 ntc = ring->next_to_clean;
552 u16 ntu = ring->next_to_use;
554 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
557 static inline void ixgbe_write_tail(struct ixgbe_ring *ring, u32 value)
559 writel(value, ring->tail);
562 #define IXGBE_RX_DESC(R, i) \
563 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
564 #define IXGBE_TX_DESC(R, i) \
565 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
566 #define IXGBE_TX_CTXTDESC(R, i) \
567 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
569 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
571 /* Use 3K as the baby jumbo frame size for FCoE */
572 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
573 #endif /* IXGBE_FCOE */
575 #define OTHER_VECTOR 1
576 #define NON_Q_VECTORS (OTHER_VECTOR)
578 #define MAX_MSIX_VECTORS_82599 64
579 #define MAX_Q_VECTORS_82599 64
580 #define MAX_MSIX_VECTORS_82598 18
581 #define MAX_Q_VECTORS_82598 16
583 struct ixgbe_mac_addr {
586 u16 state; /* bitmask */
588 #define IXGBE_MAC_STATE_DEFAULT 0x1
589 #define IXGBE_MAC_STATE_MODIFIED 0x2
590 #define IXGBE_MAC_STATE_IN_USE 0x4
592 #define MAX_Q_VECTORS MAX_Q_VECTORS_82599
593 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
595 #define MIN_MSIX_Q_VECTORS 1
596 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
598 /* default to trying for four seconds */
599 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
601 /* board specific private data structure */
602 struct ixgbe_adapter {
603 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
604 /* OS defined structs */
605 struct net_device *netdev;
606 struct pci_dev *pdev;
610 /* Some features need tri-state capability,
611 * thus the additional *_CAPABLE flags.
614 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 0)
615 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1)
616 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 2)
617 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 3)
618 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 4)
619 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 5)
620 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 6)
621 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 7)
622 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 8)
623 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 9)
624 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 10)
625 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 11)
626 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 12)
627 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 13)
628 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 14)
629 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 15)
630 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 16)
631 #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 17)
632 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 18)
633 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 19)
634 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 20)
635 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 21)
636 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 22)
637 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 23)
640 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1 << 0)
641 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
642 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
643 #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
644 #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
645 #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
646 #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
647 #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
648 #define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8)
649 #define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9)
650 #define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 10)
651 #define IXGBE_FLAG2_BRIDGE_MODE_VEB (u32)(1 << 11)
653 /* Tx fast path data */
658 /* Rx fast path data */
663 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
667 u32 tx_timeout_count;
670 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
671 int num_rx_pools; /* == num_rx_queues in 82598 */
672 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
673 u64 hw_csum_rx_error;
674 u64 hw_rx_no_dma_resources;
678 u32 alloc_rx_page_failed;
679 u32 alloc_rx_buff_failed;
681 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS];
684 struct ieee_pfc *ixgbe_ieee_pfc;
685 struct ieee_ets *ixgbe_ieee_ets;
686 struct ixgbe_dcb_config dcb_cfg;
687 struct ixgbe_dcb_config temp_dcb_cfg;
690 enum ixgbe_fc_mode last_lfc_mode;
692 int num_q_vectors; /* current number of q_vectors for device */
693 int max_q_vectors; /* true count of q_vectors for device */
694 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
695 struct msix_entry *msix_entries;
698 struct ixgbe_ring test_tx_ring;
699 struct ixgbe_ring test_rx_ring;
701 /* structs defined in ixgbe_hw.h */
704 struct ixgbe_hw_stats stats;
707 unsigned int tx_ring_count;
708 unsigned int rx_ring_count;
712 unsigned long link_check_timeout;
714 struct timer_list service_timer;
715 struct work_struct service_task;
717 struct hlist_head fdir_filter_list;
718 unsigned long fdir_overflow; /* number of times ATR was backed off */
719 union ixgbe_atr_input fdir_mask;
720 int fdir_filter_count;
723 spinlock_t fdir_perfect_lock;
726 struct ixgbe_fcoe fcoe;
727 #endif /* IXGBE_FCOE */
728 u8 __iomem *io_addr; /* Mainly for iounmap use */
740 struct ptp_clock *ptp_clock;
741 struct ptp_clock_info ptp_caps;
742 struct work_struct ptp_tx_work;
743 struct sk_buff *ptp_tx_skb;
744 struct hwtstamp_config tstamp_config;
745 unsigned long ptp_tx_start;
746 unsigned long last_overflow_check;
747 unsigned long last_rx_ptp_check;
748 unsigned long last_rx_timestamp;
749 spinlock_t tmreg_lock;
750 struct cyclecounter cc;
751 struct timecounter tc;
755 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
756 unsigned int num_vfs;
757 struct vf_data_storage *vfinfo;
758 int vf_rate_link_speed;
759 struct vf_macvlans vf_mvs;
760 struct vf_macvlans *mv_list;
762 u32 timer_event_accumulator;
764 struct ixgbe_mac_addr *mac_table;
765 struct kobject *info_kobj;
766 #ifdef CONFIG_IXGBE_HWMON
767 struct hwmon_buff *ixgbe_hwmon_buff;
768 #endif /* CONFIG_IXGBE_HWMON */
769 #ifdef CONFIG_DEBUG_FS
770 struct dentry *ixgbe_dbg_adapter;
771 #endif /*CONFIG_DEBUG_FS*/
774 unsigned long fwd_bitmask; /* Bitmask indicating in use pools */
777 struct ixgbe_fdir_filter {
778 struct hlist_node fdir_node;
779 union ixgbe_atr_input filter;
790 __IXGBE_SERVICE_SCHED,
791 __IXGBE_SERVICE_INITED,
794 __IXGBE_PTP_TX_IN_PROGRESS,
798 union { /* Union defining head/tail partner */
799 struct sk_buff *head;
800 struct sk_buff *tail;
806 #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
814 extern struct ixgbe_info ixgbe_82598_info;
815 extern struct ixgbe_info ixgbe_82599_info;
816 extern struct ixgbe_info ixgbe_X540_info;
817 #ifdef CONFIG_IXGBE_DCB
818 extern const struct dcbnl_rtnl_ops dcbnl_ops;
821 extern char ixgbe_driver_name[];
822 extern const char ixgbe_driver_version[];
824 extern char ixgbe_default_device_descr[];
825 #endif /* IXGBE_FCOE */
827 void ixgbe_up(struct ixgbe_adapter *adapter);
828 void ixgbe_down(struct ixgbe_adapter *adapter);
829 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
830 void ixgbe_reset(struct ixgbe_adapter *adapter);
831 void ixgbe_set_ethtool_ops(struct net_device *netdev);
832 int ixgbe_setup_rx_resources(struct ixgbe_ring *);
833 int ixgbe_setup_tx_resources(struct ixgbe_ring *);
834 void ixgbe_free_rx_resources(struct ixgbe_ring *);
835 void ixgbe_free_tx_resources(struct ixgbe_ring *);
836 void ixgbe_configure_rx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
837 void ixgbe_configure_tx_ring(struct ixgbe_adapter *, struct ixgbe_ring *);
838 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_ring *);
839 void ixgbe_update_stats(struct ixgbe_adapter *adapter);
840 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
841 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
843 #ifdef CONFIG_PCI_IOV
844 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter);
846 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
847 u8 *addr, u16 queue);
848 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
849 u8 *addr, u16 queue);
850 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
851 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, struct ixgbe_adapter *,
852 struct ixgbe_ring *);
853 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
854 struct ixgbe_tx_buffer *);
855 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
856 void ixgbe_write_eitr(struct ixgbe_q_vector *);
857 int ixgbe_poll(struct napi_struct *napi, int budget);
858 int ethtool_ioctl(struct ifreq *ifr);
859 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
860 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
861 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
862 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
863 union ixgbe_atr_hash_dword input,
864 union ixgbe_atr_hash_dword common,
866 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
867 union ixgbe_atr_input *input_mask);
868 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
869 union ixgbe_atr_input *input,
870 u16 soft_id, u8 queue);
871 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
872 union ixgbe_atr_input *input,
874 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
875 union ixgbe_atr_input *mask);
876 void ixgbe_set_rx_mode(struct net_device *netdev);
877 #ifdef CONFIG_IXGBE_DCB
878 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
880 int ixgbe_setup_tc(struct net_device *dev, u8 tc);
881 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
882 void ixgbe_do_reset(struct net_device *netdev);
883 #ifdef CONFIG_IXGBE_HWMON
884 void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
885 int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
886 #endif /* CONFIG_IXGBE_HWMON */
888 void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
889 int ixgbe_fso(struct ixgbe_ring *tx_ring, struct ixgbe_tx_buffer *first,
891 int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
892 union ixgbe_adv_rx_desc *rx_desc, struct sk_buff *skb);
893 int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
894 struct scatterlist *sgl, unsigned int sgc);
895 int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
896 struct scatterlist *sgl, unsigned int sgc);
897 int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
898 int ixgbe_setup_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
899 void ixgbe_free_fcoe_ddp_resources(struct ixgbe_adapter *adapter);
900 int ixgbe_fcoe_enable(struct net_device *netdev);
901 int ixgbe_fcoe_disable(struct net_device *netdev);
902 #ifdef CONFIG_IXGBE_DCB
903 u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
904 u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
905 #endif /* CONFIG_IXGBE_DCB */
906 int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
907 int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
908 struct netdev_fcoe_hbainfo *info);
909 u8 ixgbe_fcoe_get_tc(struct ixgbe_adapter *adapter);
910 #endif /* IXGBE_FCOE */
911 #ifdef CONFIG_DEBUG_FS
912 void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter);
913 void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter);
914 void ixgbe_dbg_init(void);
915 void ixgbe_dbg_exit(void);
917 static inline void ixgbe_dbg_adapter_init(struct ixgbe_adapter *adapter) {}
918 static inline void ixgbe_dbg_adapter_exit(struct ixgbe_adapter *adapter) {}
919 static inline void ixgbe_dbg_init(void) {}
920 static inline void ixgbe_dbg_exit(void) {}
921 #endif /* CONFIG_DEBUG_FS */
922 static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
924 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
927 void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
928 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter);
929 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
930 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
931 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter);
932 void ixgbe_ptp_rx_hwtstamp(struct ixgbe_adapter *adapter, struct sk_buff *skb);
933 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
934 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr);
935 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
936 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter);
937 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr);
938 #ifdef CONFIG_PCI_IOV
939 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter);
942 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
943 struct ixgbe_adapter *adapter,
944 struct ixgbe_ring *tx_ring);
945 #endif /* _IXGBE_H_ */