1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018 Intel Corporation */
4 #include <linux/bitfield.h>
8 * igc_check_reset_block - Check if PHY reset is blocked
9 * @hw: pointer to the HW structure
11 * Read the PHY management control register and check whether a PHY reset
12 * is blocked. If a reset is not blocked return 0, otherwise
13 * return IGC_ERR_BLK_PHY_RESET (12).
15 s32 igc_check_reset_block(struct igc_hw *hw)
19 manc = rd32(IGC_MANC);
21 return (manc & IGC_MANC_BLK_PHY_RST_ON_IDE) ?
22 IGC_ERR_BLK_PHY_RESET : 0;
26 * igc_get_phy_id - Retrieve the PHY ID and revision
27 * @hw: pointer to the HW structure
29 * Reads the PHY registers and stores the PHY ID and possibly the PHY
30 * revision in the hardware structure.
32 s32 igc_get_phy_id(struct igc_hw *hw)
34 struct igc_phy_info *phy = &hw->phy;
38 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
42 phy->id = (u32)(phy_id << 16);
43 usleep_range(200, 500);
44 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
48 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
49 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
56 * igc_phy_has_link - Polls PHY for link
57 * @hw: pointer to the HW structure
58 * @iterations: number of times to poll for link
59 * @usec_interval: delay between polling attempts
60 * @success: pointer to whether polling was successful or not
62 * Polls the PHY status register for link, 'iterations' number of times.
64 s32 igc_phy_has_link(struct igc_hw *hw, u32 iterations,
65 u32 usec_interval, bool *success)
70 for (i = 0; i < iterations; i++) {
71 /* Some PHYs require the PHY_STATUS register to be read
72 * twice due to the link bit being sticky. No harm doing
73 * it across the board.
75 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
76 if (ret_val && usec_interval > 0) {
77 /* If the first read fails, another entity may have
78 * ownership of the resources, wait and try again to
79 * see if they have relinquished the resources yet.
81 if (usec_interval >= 1000)
82 mdelay(usec_interval / 1000);
84 udelay(usec_interval);
86 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
89 if (phy_status & MII_SR_LINK_STATUS)
91 if (usec_interval >= 1000)
92 mdelay(usec_interval / 1000);
94 udelay(usec_interval);
97 *success = (i < iterations) ? true : false;
103 * igc_power_up_phy_copper - Restore copper link in case of PHY power down
104 * @hw: pointer to the HW structure
106 * In the case of a PHY power down to save power, or to turn off link during a
107 * driver unload, restore the link to previous settings.
109 void igc_power_up_phy_copper(struct igc_hw *hw)
113 /* The PHY will retain its settings across a power down/up cycle */
114 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
115 mii_reg &= ~MII_CR_POWER_DOWN;
116 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
120 * igc_power_down_phy_copper - Power down copper PHY
121 * @hw: pointer to the HW structure
123 * Power down PHY to save power when interface is down and wake on lan
126 void igc_power_down_phy_copper(struct igc_hw *hw)
130 /* The PHY will retain its settings across a power down/up cycle */
131 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
132 mii_reg |= MII_CR_POWER_DOWN;
133 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
134 usleep_range(1000, 2000);
138 * igc_check_downshift - Checks whether a downshift in speed occurred
139 * @hw: pointer to the HW structure
141 * A downshift is detected by querying the PHY link health.
143 void igc_check_downshift(struct igc_hw *hw)
145 struct igc_phy_info *phy = &hw->phy;
147 /* speed downshift not supported */
148 phy->speed_downgraded = false;
152 * igc_phy_hw_reset - PHY hardware reset
153 * @hw: pointer to the HW structure
155 * Verify the reset block is not blocking us from resetting. Acquire
156 * semaphore (if necessary) and read/set/write the device control reset
157 * bit in the PHY. Wait the appropriate delay time for the device to
158 * reset and release the semaphore (if necessary).
160 s32 igc_phy_hw_reset(struct igc_hw *hw)
162 struct igc_phy_info *phy = &hw->phy;
163 u32 phpm = 0, timeout = 10000;
167 ret_val = igc_check_reset_block(hw);
173 ret_val = phy->ops.acquire(hw);
177 phpm = rd32(IGC_I225_PHPM);
179 ctrl = rd32(IGC_CTRL);
180 wr32(IGC_CTRL, ctrl | IGC_CTRL_PHY_RST);
183 udelay(phy->reset_delay_us);
185 wr32(IGC_CTRL, ctrl);
188 /* SW should guarantee 100us for the completion of the PHY reset */
189 usleep_range(100, 150);
191 phpm = rd32(IGC_I225_PHPM);
194 } while (!(phpm & IGC_PHY_RST_COMP) && timeout);
197 hw_dbg("Timeout is expired after a phy reset\n");
199 usleep_range(100, 150);
201 phy->ops.release(hw);
208 * igc_phy_setup_autoneg - Configure PHY for auto-negotiation
209 * @hw: pointer to the HW structure
211 * Reads the MII auto-neg advertisement register and/or the 1000T control
212 * register and if the PHY is already setup for auto-negotiation, then
213 * return successful. Otherwise, setup advertisement and flow control to
214 * the appropriate values for the wanted auto-negotiation.
216 static s32 igc_phy_setup_autoneg(struct igc_hw *hw)
218 struct igc_phy_info *phy = &hw->phy;
219 u16 aneg_multigbt_an_ctrl = 0;
220 u16 mii_1000t_ctrl_reg = 0;
221 u16 mii_autoneg_adv_reg;
224 phy->autoneg_advertised &= phy->autoneg_mask;
226 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
227 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
231 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
232 /* Read the MII 1000Base-T Control Register (Address 9). */
233 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
234 &mii_1000t_ctrl_reg);
239 if (phy->autoneg_mask & ADVERTISE_2500_FULL) {
240 /* Read the MULTI GBT AN Control Register - reg 7.32 */
241 ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<
243 ANEG_MULTIGBT_AN_CTRL,
244 &aneg_multigbt_an_ctrl);
250 /* Need to parse both autoneg_advertised and fc and set up
251 * the appropriate PHY registers. First we will parse for
252 * autoneg_advertised software override. Since we can advertise
253 * a plethora of combinations, we need to check each bit
257 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
258 * Advertisement Register (Address 4) and the 1000 mb speed bits in
259 * the 1000Base-T Control Register (Address 9).
261 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
262 NWAY_AR_100TX_HD_CAPS |
263 NWAY_AR_10T_FD_CAPS |
264 NWAY_AR_10T_HD_CAPS);
265 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
267 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
269 /* Do we want to advertise 10 Mb Half Duplex? */
270 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
271 hw_dbg("Advertise 10mb Half duplex\n");
272 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
275 /* Do we want to advertise 10 Mb Full Duplex? */
276 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
277 hw_dbg("Advertise 10mb Full duplex\n");
278 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
281 /* Do we want to advertise 100 Mb Half Duplex? */
282 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
283 hw_dbg("Advertise 100mb Half duplex\n");
284 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
287 /* Do we want to advertise 100 Mb Full Duplex? */
288 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
289 hw_dbg("Advertise 100mb Full duplex\n");
290 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
293 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
294 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
295 hw_dbg("Advertise 1000mb Half duplex request denied!\n");
297 /* Do we want to advertise 1000 Mb Full Duplex? */
298 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
299 hw_dbg("Advertise 1000mb Full duplex\n");
300 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
303 /* We do not allow the Phy to advertise 2500 Mb Half Duplex */
304 if (phy->autoneg_advertised & ADVERTISE_2500_HALF)
305 hw_dbg("Advertise 2500mb Half duplex request denied!\n");
307 /* Do we want to advertise 2500 Mb Full Duplex? */
308 if (phy->autoneg_advertised & ADVERTISE_2500_FULL) {
309 hw_dbg("Advertise 2500mb Full duplex\n");
310 aneg_multigbt_an_ctrl |= CR_2500T_FD_CAPS;
312 aneg_multigbt_an_ctrl &= ~CR_2500T_FD_CAPS;
315 /* Check for a software override of the flow control settings, and
316 * setup the PHY advertisement registers accordingly. If
317 * auto-negotiation is enabled, then software will have to set the
318 * "PAUSE" bits to the correct value in the Auto-Negotiation
319 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
322 * The possible values of the "fc" parameter are:
323 * 0: Flow control is completely disabled
324 * 1: Rx flow control is enabled (we can receive pause frames
325 * but not send pause frames).
326 * 2: Tx flow control is enabled (we can send pause frames
327 * but we do not support receiving pause frames).
328 * 3: Both Rx and Tx flow control (symmetric) are enabled.
329 * other: No software override. The flow control configuration
330 * in the EEPROM is used.
332 switch (hw->fc.current_mode) {
334 /* Flow control (Rx & Tx) is completely disabled by a
335 * software over-ride.
337 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
339 case igc_fc_rx_pause:
340 /* Rx Flow control is enabled, and Tx Flow control is
341 * disabled, by a software over-ride.
343 * Since there really isn't a way to advertise that we are
344 * capable of Rx Pause ONLY, we will advertise that we
345 * support both symmetric and asymmetric Rx PAUSE. Later
346 * (in igc_config_fc_after_link_up) we will disable the
347 * hw's ability to send PAUSE frames.
349 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
351 case igc_fc_tx_pause:
352 /* Tx Flow control is enabled, and Rx Flow control is
353 * disabled, by a software over-ride.
355 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
356 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
359 /* Flow control (both Rx and Tx) is enabled by a software
362 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
365 hw_dbg("Flow control param set incorrectly\n");
366 return -IGC_ERR_CONFIG;
369 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
373 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
375 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
376 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
379 if (phy->autoneg_mask & ADVERTISE_2500_FULL)
380 ret_val = phy->ops.write_reg(hw,
381 (STANDARD_AN_REG_MASK <<
383 ANEG_MULTIGBT_AN_CTRL,
384 aneg_multigbt_an_ctrl);
390 * igc_wait_autoneg - Wait for auto-neg completion
391 * @hw: pointer to the HW structure
393 * Waits for auto-negotiation to complete or for the auto-negotiation time
394 * limit to expire, which ever happens first.
396 static s32 igc_wait_autoneg(struct igc_hw *hw)
401 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
402 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
403 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
406 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
409 if (phy_status & MII_SR_AUTONEG_COMPLETE)
414 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
421 * igc_copper_link_autoneg - Setup/Enable autoneg for copper link
422 * @hw: pointer to the HW structure
424 * Performs initial bounds checking on autoneg advertisement parameter, then
425 * configure to advertise the full capability. Setup the PHY to autoneg
426 * and restart the negotiation process between the link partner. If
427 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
429 static s32 igc_copper_link_autoneg(struct igc_hw *hw)
431 struct igc_phy_info *phy = &hw->phy;
435 /* Perform some bounds checking on the autoneg advertisement
438 phy->autoneg_advertised &= phy->autoneg_mask;
440 /* If autoneg_advertised is zero, we assume it was not defaulted
441 * by the calling code so we set to advertise full capability.
443 if (phy->autoneg_advertised == 0)
444 phy->autoneg_advertised = phy->autoneg_mask;
446 hw_dbg("Reconfiguring auto-neg advertisement params\n");
447 ret_val = igc_phy_setup_autoneg(hw);
449 hw_dbg("Error Setting up Auto-Negotiation\n");
452 hw_dbg("Restarting Auto-Neg\n");
454 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
455 * the Auto Neg Restart bit in the PHY control register.
457 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
461 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
462 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
466 /* Does the user want to wait for Auto-Neg to complete here, or
467 * check at a later time (for example, callback routine).
469 if (phy->autoneg_wait_to_complete) {
470 ret_val = igc_wait_autoneg(hw);
472 hw_dbg("Error while waiting for autoneg to complete\n");
477 hw->mac.get_link_status = true;
484 * igc_setup_copper_link - Configure copper link settings
485 * @hw: pointer to the HW structure
487 * Calls the appropriate function to configure the link for auto-neg or forced
488 * speed and duplex. Then we check for link, once link is established calls
489 * to configure collision distance and flow control are called. If link is
490 * not established, we return -IGC_ERR_PHY (-2).
492 s32 igc_setup_copper_link(struct igc_hw *hw)
497 if (hw->mac.autoneg) {
498 /* Setup autoneg and flow control advertisement and perform
501 ret_val = igc_copper_link_autoneg(hw);
505 /* PHY will be set to 10H, 10F, 100H or 100F
506 * depending on user settings.
508 hw_dbg("Forcing Speed and Duplex\n");
509 ret_val = hw->phy.ops.force_speed_duplex(hw);
511 hw_dbg("Error Forcing Speed and Duplex\n");
516 /* Check link status. Wait up to 100 microseconds for link to become
519 ret_val = igc_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
524 hw_dbg("Valid link established!!!\n");
525 igc_config_collision_dist(hw);
526 ret_val = igc_config_fc_after_link_up(hw);
528 hw_dbg("Unable to establish link!!!\n");
536 * igc_read_phy_reg_mdic - Read MDI control register
537 * @hw: pointer to the HW structure
538 * @offset: register offset to be read
539 * @data: pointer to the read data
541 * Reads the MDI control register in the PHY at offset and stores the
542 * information read to data.
544 static s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data)
546 struct igc_phy_info *phy = &hw->phy;
550 if (offset > MAX_PHY_REG_ADDRESS) {
551 hw_dbg("PHY Address %d is out of range\n", offset);
552 ret_val = -IGC_ERR_PARAM;
556 /* Set up Op-code, Phy Address, and register offset in the MDI
557 * Control register. The MAC will take care of interfacing with the
558 * PHY to retrieve the desired data.
560 mdic = ((offset << IGC_MDIC_REG_SHIFT) |
561 (phy->addr << IGC_MDIC_PHY_SHIFT) |
564 wr32(IGC_MDIC, mdic);
566 /* Poll the ready bit to see if the MDI read completed
567 * Increasing the time out as testing showed failures with
570 for (i = 0; i < IGC_GEN_POLL_TIMEOUT; i++) {
572 mdic = rd32(IGC_MDIC);
573 if (mdic & IGC_MDIC_READY)
576 if (!(mdic & IGC_MDIC_READY)) {
577 hw_dbg("MDI Read did not complete\n");
578 ret_val = -IGC_ERR_PHY;
581 if (mdic & IGC_MDIC_ERROR) {
582 hw_dbg("MDI Error\n");
583 ret_val = -IGC_ERR_PHY;
593 * igc_write_phy_reg_mdic - Write MDI control register
594 * @hw: pointer to the HW structure
595 * @offset: register offset to write to
596 * @data: data to write to register at offset
598 * Writes data to MDI control register in the PHY at offset.
600 static s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data)
602 struct igc_phy_info *phy = &hw->phy;
606 if (offset > MAX_PHY_REG_ADDRESS) {
607 hw_dbg("PHY Address %d is out of range\n", offset);
608 ret_val = -IGC_ERR_PARAM;
612 /* Set up Op-code, Phy Address, and register offset in the MDI
613 * Control register. The MAC will take care of interfacing with the
614 * PHY to write the desired data.
616 mdic = (((u32)data) |
617 (offset << IGC_MDIC_REG_SHIFT) |
618 (phy->addr << IGC_MDIC_PHY_SHIFT) |
619 (IGC_MDIC_OP_WRITE));
621 wr32(IGC_MDIC, mdic);
623 /* Poll the ready bit to see if the MDI read completed
624 * Increasing the time out as testing showed failures with
627 for (i = 0; i < IGC_GEN_POLL_TIMEOUT; i++) {
629 mdic = rd32(IGC_MDIC);
630 if (mdic & IGC_MDIC_READY)
633 if (!(mdic & IGC_MDIC_READY)) {
634 hw_dbg("MDI Write did not complete\n");
635 ret_val = -IGC_ERR_PHY;
638 if (mdic & IGC_MDIC_ERROR) {
639 hw_dbg("MDI Error\n");
640 ret_val = -IGC_ERR_PHY;
649 * __igc_access_xmdio_reg - Read/write XMDIO register
650 * @hw: pointer to the HW structure
651 * @address: XMDIO address to program
652 * @dev_addr: device address to program
653 * @data: pointer to value to read/write from/to the XMDIO address
654 * @read: boolean flag to indicate read or write
656 static s32 __igc_access_xmdio_reg(struct igc_hw *hw, u16 address,
657 u8 dev_addr, u16 *data, bool read)
661 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);
665 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);
669 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |
675 ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data);
677 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);
681 /* Recalibrate the device back to 0 */
682 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);
690 * igc_read_xmdio_reg - Read XMDIO register
691 * @hw: pointer to the HW structure
692 * @addr: XMDIO address to program
693 * @dev_addr: device address to program
694 * @data: value to be read from the EMI address
696 static s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr,
697 u8 dev_addr, u16 *data)
699 return __igc_access_xmdio_reg(hw, addr, dev_addr, data, true);
703 * igc_write_xmdio_reg - Write XMDIO register
704 * @hw: pointer to the HW structure
705 * @addr: XMDIO address to program
706 * @dev_addr: device address to program
707 * @data: value to be written to the XMDIO address
709 static s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr,
710 u8 dev_addr, u16 data)
712 return __igc_access_xmdio_reg(hw, addr, dev_addr, &data, false);
716 * igc_write_phy_reg_gpy - Write GPY PHY register
717 * @hw: pointer to the HW structure
718 * @offset: register offset to write to
719 * @data: data to write at register offset
721 * Acquires semaphore, if necessary, then writes the data to PHY register
722 * at the offset. Release any acquired semaphores before exiting.
724 s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data)
726 u8 dev_addr = FIELD_GET(GPY_MMD_MASK, offset);
729 offset = offset & GPY_REG_MASK;
732 ret_val = hw->phy.ops.acquire(hw);
735 ret_val = igc_write_phy_reg_mdic(hw, offset, data);
736 hw->phy.ops.release(hw);
738 ret_val = igc_write_xmdio_reg(hw, (u16)offset, dev_addr,
746 * igc_read_phy_reg_gpy - Read GPY PHY register
747 * @hw: pointer to the HW structure
748 * @offset: lower half is register offset to read to
749 * upper half is MMD to use.
750 * @data: data to read at register offset
752 * Acquires semaphore, if necessary, then reads the data in the PHY register
753 * at the offset. Release any acquired semaphores before exiting.
755 s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data)
757 u8 dev_addr = FIELD_GET(GPY_MMD_MASK, offset);
760 offset = offset & GPY_REG_MASK;
763 ret_val = hw->phy.ops.acquire(hw);
766 ret_val = igc_read_phy_reg_mdic(hw, offset, data);
767 hw->phy.ops.release(hw);
769 ret_val = igc_read_xmdio_reg(hw, (u16)offset, dev_addr,
777 * igc_read_phy_fw_version - Read gPHY firmware version
778 * @hw: pointer to the HW structure
780 u16 igc_read_phy_fw_version(struct igc_hw *hw)
782 struct igc_phy_info *phy = &hw->phy;
783 u16 gphy_version = 0;
786 /* NVM image version is reported as firmware version for i225 device */
787 ret_val = phy->ops.read_reg(hw, IGC_GPHY_VERSION, &gphy_version);
789 hw_dbg("igc_phy: read wrong gphy version\n");