1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018 Intel Corporation */
7 #include <linux/kobject.h>
9 #include <linux/netdevice.h>
10 #include <linux/vmalloc.h>
11 #include <linux/ethtool.h>
12 #include <linux/sctp.h>
13 #include <linux/ptp_clock_kernel.h>
14 #include <linux/timecounter.h>
15 #include <linux/net_tstamp.h>
19 void igc_ethtool_set_ops(struct net_device *);
21 /* Transmit and receive queues */
22 #define IGC_MAX_RX_QUEUES 4
23 #define IGC_MAX_TX_QUEUES 4
25 #define MAX_Q_VECTORS 8
26 #define MAX_STD_JUMBO_FRAME_SIZE 9216
28 #define MAX_ETYPE_FILTER 8
29 #define IGC_RETA_SIZE 128
33 #define IGC_N_PEROUT 2
36 enum igc_mac_filter_type {
37 IGC_MAC_FILTER_TYPE_DST = 0,
38 IGC_MAC_FILTER_TYPE_SRC
41 struct igc_tx_queue_stats {
48 struct igc_rx_queue_stats {
56 struct igc_rx_packet_stats {
57 u64 ipv4_packets; /* IPv4 headers processed */
58 u64 ipv4e_packets; /* IPv4E headers with extensions processed */
59 u64 ipv6_packets; /* IPv6 headers processed */
60 u64 ipv6e_packets; /* IPv6E headers with extensions processed */
61 u64 tcp_packets; /* TCP headers processed */
62 u64 udp_packets; /* UDP headers processed */
63 u64 sctp_packets; /* SCTP headers processed */
64 u64 nfs_packets; /* NFS headers processe */
68 struct igc_ring_container {
69 struct igc_ring *ring; /* pointer to linked list of rings */
70 unsigned int total_bytes; /* total bytes processed this int */
71 unsigned int total_packets; /* total packets processed this int */
72 u16 work_limit; /* total work allowed per interrupt */
73 u8 count; /* total number of rings in vector */
74 u8 itr; /* current ITR setting for ring */
78 struct igc_q_vector *q_vector; /* backlink to q_vector */
79 struct net_device *netdev; /* back pointer to net_device */
80 struct device *dev; /* device for dma mapping */
81 union { /* array of buffer info structs */
82 struct igc_tx_buffer *tx_buffer_info;
83 struct igc_rx_buffer *rx_buffer_info;
85 void *desc; /* descriptor ring memory */
86 unsigned long flags; /* ring specific flags */
87 void __iomem *tail; /* pointer to ring tail register */
88 dma_addr_t dma; /* phys address of the ring */
89 unsigned int size; /* length of desc. ring in bytes */
91 u16 count; /* number of desc. in the ring */
92 u8 queue_index; /* logical index of the ring*/
93 u8 reg_idx; /* physical index of the ring */
94 bool launchtime_enable; /* true if LaunchTime is enabled */
99 /* everything past this point are written often */
107 struct igc_tx_queue_stats tx_stats;
108 struct u64_stats_sync tx_syncp;
109 struct u64_stats_sync tx_syncp2;
113 struct igc_rx_queue_stats rx_stats;
114 struct igc_rx_packet_stats pkt_stats;
115 struct u64_stats_sync rx_syncp;
120 struct xdp_rxq_info xdp_rxq;
121 struct xsk_buff_pool *xsk_pool;
122 } ____cacheline_internodealigned_in_smp;
124 /* Board specific private data structure */
126 struct net_device *netdev;
128 struct ethtool_eee eee;
133 unsigned int num_q_vectors;
135 struct msix_entry *msix_entries;
139 u32 tx_timeout_count;
141 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];
145 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];
147 struct timer_list watchdog_timer;
148 struct timer_list dma_err_timer;
149 struct timer_list phy_info_timer;
159 /* Interrupt Throttle Rate */
163 struct work_struct reset_task;
164 struct work_struct watchdog_task;
165 struct work_struct dma_err_task;
168 u8 tx_timeout_factor;
177 /* OS defined structs */
178 struct pci_dev *pdev;
179 /* lock for statistics */
180 spinlock_t stats64_lock;
181 struct rtnl_link_stats64 stats64;
183 /* structs defined in igc_hw.h */
185 struct igc_hw_stats stats;
187 struct igc_q_vector *q_vector[MAX_Q_VECTORS];
188 u32 eims_enable_mask;
194 u32 tx_hwtstamp_timeouts;
195 u32 tx_hwtstamp_skipped;
196 u32 rx_hwtstamp_cleared;
199 u32 rss_indir_tbl_init;
201 /* Any access to elements in nfc_rule_list is protected by the
204 struct mutex nfc_rule_lock;
205 struct list_head nfc_rule_list;
206 unsigned int nfc_rule_count;
208 u8 rss_indir_tbl[IGC_RETA_SIZE];
210 unsigned long link_check_timeout;
215 struct ptp_clock *ptp_clock;
216 struct ptp_clock_info ptp_caps;
217 struct work_struct ptp_tx_work;
218 struct sk_buff *ptp_tx_skb;
219 struct hwtstamp_config tstamp_config;
220 unsigned long ptp_tx_start;
221 unsigned int ptp_flags;
222 /* System time value lock */
223 spinlock_t tmreg_lock;
224 struct cyclecounter cc;
225 struct timecounter tc;
226 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */
227 ktime_t ptp_reset_start; /* Reset time in clock mono */
231 struct bpf_prog *xdp_prog;
233 bool pps_sys_wrap_on;
235 struct ptp_pin_desc sdp_config[IGC_N_SDP];
237 struct timespec64 start;
238 struct timespec64 period;
239 } perout[IGC_N_PEROUT];
242 void igc_up(struct igc_adapter *adapter);
243 void igc_down(struct igc_adapter *adapter);
244 int igc_open(struct net_device *netdev);
245 int igc_close(struct net_device *netdev);
246 int igc_setup_tx_resources(struct igc_ring *ring);
247 int igc_setup_rx_resources(struct igc_ring *ring);
248 void igc_free_tx_resources(struct igc_ring *ring);
249 void igc_free_rx_resources(struct igc_ring *ring);
250 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);
251 void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
252 const u32 max_rss_queues);
253 int igc_reinit_queues(struct igc_adapter *adapter);
254 void igc_write_rss_indir_tbl(struct igc_adapter *adapter);
255 bool igc_has_link(struct igc_adapter *adapter);
256 void igc_reset(struct igc_adapter *adapter);
257 int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx);
258 void igc_update_stats(struct igc_adapter *adapter);
259 void igc_disable_rx_ring(struct igc_ring *ring);
260 void igc_enable_rx_ring(struct igc_ring *ring);
261 void igc_disable_tx_ring(struct igc_ring *ring);
262 void igc_enable_tx_ring(struct igc_ring *ring);
263 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags);
265 /* igc_dump declarations */
266 void igc_rings_dump(struct igc_adapter *adapter);
267 void igc_regs_dump(struct igc_adapter *adapter);
269 extern char igc_driver_name[];
271 #define IGC_REGS_LEN 740
273 /* flags controlling PTP/1588 function */
274 #define IGC_PTP_ENABLED BIT(0)
276 /* Flags definitions */
277 #define IGC_FLAG_HAS_MSI BIT(0)
278 #define IGC_FLAG_QUEUE_PAIRS BIT(3)
279 #define IGC_FLAG_DMAC BIT(4)
280 #define IGC_FLAG_PTP BIT(8)
281 #define IGC_FLAG_WOL_SUPPORTED BIT(8)
282 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9)
283 #define IGC_FLAG_MEDIA_RESET BIT(10)
284 #define IGC_FLAG_MAS_ENABLE BIT(12)
285 #define IGC_FLAG_HAS_MSIX BIT(13)
286 #define IGC_FLAG_EEE BIT(14)
287 #define IGC_FLAG_VLAN_PROMISC BIT(15)
288 #define IGC_FLAG_RX_LEGACY BIT(16)
289 #define IGC_FLAG_TSN_QBV_ENABLED BIT(17)
291 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
292 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
294 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002
295 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
296 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
298 /* Interrupt defines */
299 #define IGC_START_ITR 648 /* ~6000 ints/sec */
300 #define IGC_4K_ITR 980
301 #define IGC_20K_ITR 196
302 #define IGC_70K_ITR 56
304 #define IGC_DEFAULT_ITR 3 /* dynamic */
305 #define IGC_MAX_ITR_USECS 10000
306 #define IGC_MIN_ITR_USECS 10
307 #define NON_Q_VECTORS 1
308 #define MAX_MSIX_ENTRIES 10
310 /* TX/RX descriptor defines */
311 #define IGC_DEFAULT_TXD 256
312 #define IGC_DEFAULT_TX_WORK 128
313 #define IGC_MIN_TXD 80
314 #define IGC_MAX_TXD 4096
316 #define IGC_DEFAULT_RXD 256
317 #define IGC_MIN_RXD 80
318 #define IGC_MAX_RXD 4096
320 /* Supported Rx Buffer Sizes */
321 #define IGC_RXBUFFER_256 256
322 #define IGC_RXBUFFER_2048 2048
323 #define IGC_RXBUFFER_3072 3072
325 #define AUTO_ALL_MODES 0
326 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256
328 /* Transmit and receive latency (for PTP timestamps) */
329 #define IGC_I225_TX_LATENCY_10 240
330 #define IGC_I225_TX_LATENCY_100 58
331 #define IGC_I225_TX_LATENCY_1000 80
332 #define IGC_I225_TX_LATENCY_2500 1325
333 #define IGC_I225_RX_LATENCY_10 6450
334 #define IGC_I225_RX_LATENCY_100 185
335 #define IGC_I225_RX_LATENCY_1000 300
336 #define IGC_I225_RX_LATENCY_2500 1485
338 /* RX and TX descriptor control thresholds.
339 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
340 * descriptors available in its onboard memory.
341 * Setting this to 0 disables RX descriptor prefetch.
342 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
343 * available in host memory.
344 * If PTHRESH is 0, this should also be 0.
345 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
346 * descriptors until either it has this many to write back, or the
349 #define IGC_RX_PTHRESH 8
350 #define IGC_RX_HTHRESH 8
351 #define IGC_TX_PTHRESH 8
352 #define IGC_TX_HTHRESH 1
353 #define IGC_RX_WTHRESH 4
354 #define IGC_TX_WTHRESH 16
356 #define IGC_RX_DMA_ATTR \
357 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
359 #define IGC_TS_HDR_LEN 16
361 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
363 #if (PAGE_SIZE < 8192)
364 #define IGC_MAX_FRAME_BUILD_SKB \
365 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN)
367 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)
370 /* How many Rx Buffers do we bundle into one write to the hardware ? */
371 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */
374 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000
375 #define IGC_TX_FLAGS_VLAN_SHIFT 16
377 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */
378 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,
379 const u32 stat_err_bits)
381 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
388 __IGC_PTP_TX_IN_PROGRESS,
393 IGC_TX_FLAGS_VLAN = 0x01,
394 IGC_TX_FLAGS_TSO = 0x02,
395 IGC_TX_FLAGS_TSTAMP = 0x04,
398 IGC_TX_FLAGS_IPV4 = 0x10,
399 IGC_TX_FLAGS_CSUM = 0x20,
406 /* The largest size we can write to the descriptor is 65535. In order to
407 * maintain a power of two alignment we have to limit ourselves to 32K.
409 #define IGC_MAX_TXD_PWR 15
410 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR)
412 /* Tx Descriptors needed, worst case */
413 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)
414 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
416 enum igc_tx_buffer_type {
417 IGC_TX_BUFFER_TYPE_SKB,
418 IGC_TX_BUFFER_TYPE_XDP,
419 IGC_TX_BUFFER_TYPE_XSK,
422 /* wrapper around a pointer to a socket buffer,
423 * so a DMA handle can be stored along with the buffer
425 struct igc_tx_buffer {
426 union igc_adv_tx_desc *next_to_watch;
427 unsigned long time_stamp;
428 enum igc_tx_buffer_type type;
431 struct xdp_frame *xdpf;
433 unsigned int bytecount;
437 DEFINE_DMA_UNMAP_ADDR(dma);
438 DEFINE_DMA_UNMAP_LEN(len);
442 struct igc_rx_buffer {
447 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
454 struct xdp_buff *xdp;
458 struct igc_q_vector {
459 struct igc_adapter *adapter; /* backlink */
460 void __iomem *itr_register;
461 u32 eims_value; /* EIMS mask value */
466 struct igc_ring_container rx, tx;
468 struct napi_struct napi;
470 struct rcu_head rcu; /* to avoid race with update stats on free */
471 char name[IFNAMSIZ + 9];
472 struct net_device poll_dev;
474 /* for dynamic allocation of rings associated with this q_vector */
475 struct igc_ring ring[] ____cacheline_internodealigned_in_smp;
478 enum igc_filter_match_flags {
479 IGC_FILTER_FLAG_ETHER_TYPE = 0x1,
480 IGC_FILTER_FLAG_VLAN_TCI = 0x2,
481 IGC_FILTER_FLAG_SRC_MAC_ADDR = 0x4,
482 IGC_FILTER_FLAG_DST_MAC_ADDR = 0x8,
485 struct igc_nfc_filter {
489 u8 src_addr[ETH_ALEN];
490 u8 dst_addr[ETH_ALEN];
493 struct igc_nfc_rule {
494 struct list_head list;
495 struct igc_nfc_filter filter;
500 /* IGC supports a total of 32 NFC rules: 16 MAC address based,, 8 VLAN priority
501 * based, and 8 ethertype based.
503 #define IGC_MAX_RXNFC_RULES 32
505 /* igc_desc_unused - calculate if we have unused descriptors */
506 static inline u16 igc_desc_unused(const struct igc_ring *ring)
508 u16 ntc = ring->next_to_clean;
509 u16 ntu = ring->next_to_use;
511 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
514 static inline s32 igc_get_phy_info(struct igc_hw *hw)
516 if (hw->phy.ops.get_phy_info)
517 return hw->phy.ops.get_phy_info(hw);
522 static inline s32 igc_reset_phy(struct igc_hw *hw)
524 if (hw->phy.ops.reset)
525 return hw->phy.ops.reset(hw);
530 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring)
532 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
535 enum igc_ring_flags_t {
536 IGC_RING_FLAG_RX_3K_BUFFER,
537 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED,
538 IGC_RING_FLAG_RX_SCTP_CSUM,
539 IGC_RING_FLAG_RX_LB_VLAN_BSWAP,
540 IGC_RING_FLAG_TX_CTX_IDX,
541 IGC_RING_FLAG_TX_DETECT_HANG,
542 IGC_RING_FLAG_AF_XDP_ZC,
545 #define ring_uses_large_buffer(ring) \
546 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
547 #define set_ring_uses_large_buffer(ring) \
548 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
549 #define clear_ring_uses_large_buffer(ring) \
550 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
552 #define ring_uses_build_skb(ring) \
553 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
555 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring)
557 #if (PAGE_SIZE < 8192)
558 if (ring_uses_large_buffer(ring))
559 return IGC_RXBUFFER_3072;
561 if (ring_uses_build_skb(ring))
562 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN;
564 return IGC_RXBUFFER_2048;
567 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring)
569 #if (PAGE_SIZE < 8192)
570 if (ring_uses_large_buffer(ring))
576 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
578 if (hw->phy.ops.read_reg)
579 return hw->phy.ops.read_reg(hw, offset, data);
584 void igc_reinit_locked(struct igc_adapter *);
585 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
587 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
588 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
590 void igc_ptp_init(struct igc_adapter *adapter);
591 void igc_ptp_reset(struct igc_adapter *adapter);
592 void igc_ptp_suspend(struct igc_adapter *adapter);
593 void igc_ptp_stop(struct igc_adapter *adapter);
594 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf);
595 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
596 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
597 void igc_ptp_tx_hang(struct igc_adapter *adapter);
598 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts);
600 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))
602 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)
604 #define IGC_RX_DESC(R, i) \
605 (&(((union igc_adv_rx_desc *)((R)->desc))[i]))
606 #define IGC_TX_DESC(R, i) \
607 (&(((union igc_adv_tx_desc *)((R)->desc))[i]))
608 #define IGC_TX_CTXTDESC(R, i) \
609 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i]))