1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> */
4 #include <linux/module.h>
5 #include <linux/device.h>
7 #include <linux/ptp_classify.h>
11 #define INCVALUE_MASK 0x7fffffff
12 #define ISGN 0x80000000
14 /* The 82580 timesync updates the system timer every 8ns by 8ns,
15 * and this update value cannot be reprogrammed.
17 * Neither the 82576 nor the 82580 offer registers wide enough to hold
18 * nanoseconds time values for very long. For the 82580, SYSTIM always
19 * counts nanoseconds, but the upper 24 bits are not available. The
20 * frequency is adjusted by changing the 32 bit fractional nanoseconds
23 * For the 82576, the SYSTIM register time unit is affect by the
24 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
25 * field are needed to provide the nominal 16 nanosecond period,
26 * leaving 19 bits for fractional nanoseconds.
28 * We scale the NIC clock cycle by a large factor so that relatively
29 * small clock corrections can be added or subtracted at each clock
30 * tick. The drawbacks of a large factor are a) that the clock
31 * register overflows more quickly (not such a big deal) and b) that
32 * the increment per tick has to fit into 24 bits. As a result we
33 * need to use a shift of 19 so we can fit a value of 16 into the
38 * +--------------+ +---+---+------+
39 * 82576 | 32 | | 8 | 5 | 19 |
40 * +--------------+ +---+---+------+
41 * \________ 45 bits _______/ fract
43 * +----------+---+ +--------------+
44 * 82580 | 24 | 8 | | 32 |
45 * +----------+---+ +--------------+
46 * reserved \______ 40 bits _____/
49 * The 45 bit 82576 SYSTIM overflows every
50 * 2^45 * 10^-9 / 3600 = 9.77 hours.
52 * The 40 bit 82580 SYSTIM overflows every
53 * 2^40 * 10^-9 / 60 = 18.3 minutes.
55 * SYSTIM is converted to real time using a timecounter. As
56 * timecounter_cyc2time() allows old timestamps, the timecounter needs
57 * to be updated at least once per half of the SYSTIM interval.
58 * Scheduling of delayed work is not very accurate, and also the NIC
59 * clock can be adjusted to run up to 6% faster and the system clock
60 * up to 10% slower, so we aim for 6 minutes to be sure the actual
61 * interval in the NIC time is shorter than 9.16 minutes.
64 #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 6)
65 #define IGB_PTP_TX_TIMEOUT (HZ * 15)
66 #define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT)
67 #define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
68 #define INCVALUE_82576 (16u << IGB_82576_TSYNC_SHIFT)
69 #define IGB_NBITS_82580 40
71 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
73 /* SYSTIM read access for the 82576 */
74 static u64 igb_ptp_read_82576(const struct cyclecounter *cc)
76 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
77 struct e1000_hw *hw = &igb->hw;
81 lo = rd32(E1000_SYSTIML);
82 hi = rd32(E1000_SYSTIMH);
84 val = ((u64) hi) << 32;
90 /* SYSTIM read access for the 82580 */
91 static u64 igb_ptp_read_82580(const struct cyclecounter *cc)
93 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
94 struct e1000_hw *hw = &igb->hw;
98 /* The timestamp latches on lowest register read. For the 82580
99 * the lowest register is SYSTIMR instead of SYSTIML. However we only
100 * need to provide nanosecond resolution, so we just ignore it.
103 lo = rd32(E1000_SYSTIML);
104 hi = rd32(E1000_SYSTIMH);
106 val = ((u64) hi) << 32;
112 /* SYSTIM read access for I210/I211 */
113 static void igb_ptp_read_i210(struct igb_adapter *adapter,
114 struct timespec64 *ts)
116 struct e1000_hw *hw = &adapter->hw;
119 /* The timestamp latches on lowest register read. For I210/I211, the
120 * lowest register is SYSTIMR. Since we only need to provide nanosecond
121 * resolution, we can ignore it.
124 nsec = rd32(E1000_SYSTIML);
125 sec = rd32(E1000_SYSTIMH);
131 static void igb_ptp_write_i210(struct igb_adapter *adapter,
132 const struct timespec64 *ts)
134 struct e1000_hw *hw = &adapter->hw;
136 /* Writing the SYSTIMR register is not necessary as it only provides
137 * sub-nanosecond resolution.
139 wr32(E1000_SYSTIML, ts->tv_nsec);
140 wr32(E1000_SYSTIMH, (u32)ts->tv_sec);
144 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
145 * @adapter: board private structure
146 * @hwtstamps: timestamp structure to update
147 * @systim: unsigned 64bit system time value.
149 * We need to convert the system time value stored in the RX/TXSTMP registers
150 * into a hwtstamp which can be used by the upper level timestamping functions.
152 * The 'tmreg_lock' spinlock is used to protect the consistency of the
153 * system time value. This is needed because reading the 64 bit time
154 * value involves reading two (or three) 32 bit registers. The first
155 * read latches the value. Ditto for writing.
157 * In addition, here have extended the system time with an overflow
158 * counter in software.
160 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
161 struct skb_shared_hwtstamps *hwtstamps,
167 switch (adapter->hw.mac.type) {
172 spin_lock_irqsave(&adapter->tmreg_lock, flags);
174 ns = timecounter_cyc2time(&adapter->tc, systim);
176 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
178 memset(hwtstamps, 0, sizeof(*hwtstamps));
179 hwtstamps->hwtstamp = ns_to_ktime(ns);
183 memset(hwtstamps, 0, sizeof(*hwtstamps));
184 /* Upper 32 bits contain s, lower 32 bits contain ns. */
185 hwtstamps->hwtstamp = ktime_set(systim >> 32,
186 systim & 0xFFFFFFFF);
193 /* PTP clock operations */
194 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb)
196 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
198 struct e1000_hw *hw = &igb->hw;
209 rate = div_u64(rate, 1953125);
211 incvalue = 16 << IGB_82576_TSYNC_SHIFT;
218 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
223 static int igb_ptp_adjfine_82580(struct ptp_clock_info *ptp, long scaled_ppm)
225 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
227 struct e1000_hw *hw = &igb->hw;
232 if (scaled_ppm < 0) {
234 scaled_ppm = -scaled_ppm;
238 rate = div_u64(rate, 15625);
240 inca = rate & INCVALUE_MASK;
244 wr32(E1000_TIMINCA, inca);
249 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
251 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
255 spin_lock_irqsave(&igb->tmreg_lock, flags);
256 timecounter_adjtime(&igb->tc, delta);
257 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
262 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
264 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
267 struct timespec64 now, then = ns_to_timespec64(delta);
269 spin_lock_irqsave(&igb->tmreg_lock, flags);
271 igb_ptp_read_i210(igb, &now);
272 now = timespec64_add(now, then);
273 igb_ptp_write_i210(igb, (const struct timespec64 *)&now);
275 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
280 static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp,
281 struct timespec64 *ts)
283 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
288 spin_lock_irqsave(&igb->tmreg_lock, flags);
290 ns = timecounter_read(&igb->tc);
292 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
294 *ts = ns_to_timespec64(ns);
299 static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp,
300 struct timespec64 *ts)
302 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
306 spin_lock_irqsave(&igb->tmreg_lock, flags);
308 igb_ptp_read_i210(igb, ts);
310 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
315 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
316 const struct timespec64 *ts)
318 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
323 ns = timespec64_to_ns(ts);
325 spin_lock_irqsave(&igb->tmreg_lock, flags);
327 timecounter_init(&igb->tc, &igb->cc, ns);
329 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
334 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
335 const struct timespec64 *ts)
337 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
341 spin_lock_irqsave(&igb->tmreg_lock, flags);
343 igb_ptp_write_i210(igb, ts);
345 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
350 static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
352 u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
353 static const u32 mask[IGB_N_SDP] = {
356 E1000_CTRL_EXT_SDP2_DIR,
357 E1000_CTRL_EXT_SDP3_DIR,
366 static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin)
368 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
369 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
371 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
372 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
374 static const u32 ts_sdp_en[IGB_N_SDP] = {
375 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
377 struct e1000_hw *hw = &igb->hw;
378 u32 ctrl, ctrl_ext, tssdp = 0;
380 ctrl = rd32(E1000_CTRL);
381 ctrl_ext = rd32(E1000_CTRL_EXT);
382 tssdp = rd32(E1000_TSSDP);
384 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext);
386 /* Make sure this pin is not enabled as an output. */
387 tssdp &= ~ts_sdp_en[pin];
390 tssdp &= ~AUX1_SEL_SDP3;
391 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN;
393 tssdp &= ~AUX0_SEL_SDP3;
394 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN;
397 wr32(E1000_TSSDP, tssdp);
398 wr32(E1000_CTRL, ctrl);
399 wr32(E1000_CTRL_EXT, ctrl_ext);
402 static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq)
404 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
405 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
407 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
408 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
410 static const u32 ts_sdp_en[IGB_N_SDP] = {
411 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
413 static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = {
414 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0,
415 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0,
417 static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = {
418 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1,
419 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1,
421 static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = {
422 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0,
423 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0,
425 static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = {
426 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
427 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
429 static const u32 ts_sdp_sel_clr[IGB_N_SDP] = {
430 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
431 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
433 struct e1000_hw *hw = &igb->hw;
434 u32 ctrl, ctrl_ext, tssdp = 0;
436 ctrl = rd32(E1000_CTRL);
437 ctrl_ext = rd32(E1000_CTRL_EXT);
438 tssdp = rd32(E1000_TSSDP);
440 igb_pin_direction(pin, 0, &ctrl, &ctrl_ext);
442 /* Make sure this pin is not enabled as an input. */
443 if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin])
444 tssdp &= ~AUX0_TS_SDP_EN;
446 if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin])
447 tssdp &= ~AUX1_TS_SDP_EN;
449 tssdp &= ~ts_sdp_sel_clr[pin];
452 tssdp |= ts_sdp_sel_fc1[pin];
454 tssdp |= ts_sdp_sel_fc0[pin];
457 tssdp |= ts_sdp_sel_tt1[pin];
459 tssdp |= ts_sdp_sel_tt0[pin];
461 tssdp |= ts_sdp_en[pin];
463 wr32(E1000_TSSDP, tssdp);
464 wr32(E1000_CTRL, ctrl);
465 wr32(E1000_CTRL_EXT, ctrl_ext);
468 static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp,
469 struct ptp_clock_request *rq, int on)
471 struct igb_adapter *igb =
472 container_of(ptp, struct igb_adapter, ptp_caps);
473 struct e1000_hw *hw = &igb->hw;
474 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
476 struct timespec64 ts;
477 int use_freq = 0, pin = -1;
481 case PTP_CLK_REQ_EXTTS:
483 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS,
488 if (rq->extts.index == 1) {
489 tsauxc_mask = TSAUXC_EN_TS1;
490 tsim_mask = TSINTR_AUTT1;
492 tsauxc_mask = TSAUXC_EN_TS0;
493 tsim_mask = TSINTR_AUTT0;
495 spin_lock_irqsave(&igb->tmreg_lock, flags);
496 tsauxc = rd32(E1000_TSAUXC);
497 tsim = rd32(E1000_TSIM);
499 igb_pin_extts(igb, rq->extts.index, pin);
500 tsauxc |= tsauxc_mask;
503 tsauxc &= ~tsauxc_mask;
506 wr32(E1000_TSAUXC, tsauxc);
507 wr32(E1000_TSIM, tsim);
508 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
511 case PTP_CLK_REQ_PEROUT:
513 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT,
518 ts.tv_sec = rq->perout.period.sec;
519 ts.tv_nsec = rq->perout.period.nsec;
520 ns = timespec64_to_ns(&ts);
522 if (on && ((ns <= 70000000LL) || (ns == 125000000LL) ||
523 (ns == 250000000LL) || (ns == 500000000LL))) {
528 ts = ns_to_timespec64(ns);
529 if (rq->perout.index == 1) {
531 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1;
534 tsauxc_mask = TSAUXC_EN_TT1;
535 tsim_mask = TSINTR_TT1;
537 trgttiml = E1000_TRGTTIML1;
538 trgttimh = E1000_TRGTTIMH1;
539 freqout = E1000_FREQOUT1;
542 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0;
545 tsauxc_mask = TSAUXC_EN_TT0;
546 tsim_mask = TSINTR_TT0;
548 trgttiml = E1000_TRGTTIML0;
549 trgttimh = E1000_TRGTTIMH0;
550 freqout = E1000_FREQOUT0;
552 spin_lock_irqsave(&igb->tmreg_lock, flags);
553 tsauxc = rd32(E1000_TSAUXC);
554 tsim = rd32(E1000_TSIM);
555 if (rq->perout.index == 1) {
556 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1);
559 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0);
563 int i = rq->perout.index;
564 igb_pin_perout(igb, i, pin, use_freq);
565 igb->perout[i].start.tv_sec = rq->perout.start.sec;
566 igb->perout[i].start.tv_nsec = rq->perout.start.nsec;
567 igb->perout[i].period.tv_sec = ts.tv_sec;
568 igb->perout[i].period.tv_nsec = ts.tv_nsec;
569 wr32(trgttimh, rq->perout.start.sec);
570 wr32(trgttiml, rq->perout.start.nsec);
573 tsauxc |= tsauxc_mask;
576 wr32(E1000_TSAUXC, tsauxc);
577 wr32(E1000_TSIM, tsim);
578 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
581 case PTP_CLK_REQ_PPS:
582 spin_lock_irqsave(&igb->tmreg_lock, flags);
583 tsim = rd32(E1000_TSIM);
585 tsim |= TSINTR_SYS_WRAP;
587 tsim &= ~TSINTR_SYS_WRAP;
588 igb->pps_sys_wrap_on = !!on;
589 wr32(E1000_TSIM, tsim);
590 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
597 static int igb_ptp_feature_enable(struct ptp_clock_info *ptp,
598 struct ptp_clock_request *rq, int on)
603 static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
604 enum ptp_pin_function func, unsigned int chan)
619 * @work: pointer to work struct
621 * This work function polls the TSYNCTXCTL valid bit to determine when a
622 * timestamp has been taken for the current stored skb.
624 static void igb_ptp_tx_work(struct work_struct *work)
626 struct igb_adapter *adapter = container_of(work, struct igb_adapter,
628 struct e1000_hw *hw = &adapter->hw;
631 if (!adapter->ptp_tx_skb)
634 if (time_is_before_jiffies(adapter->ptp_tx_start +
635 IGB_PTP_TX_TIMEOUT)) {
636 dev_kfree_skb_any(adapter->ptp_tx_skb);
637 adapter->ptp_tx_skb = NULL;
638 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
639 adapter->tx_hwtstamp_timeouts++;
640 /* Clear the tx valid bit in TSYNCTXCTL register to enable
644 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
648 tsynctxctl = rd32(E1000_TSYNCTXCTL);
649 if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
650 igb_ptp_tx_hwtstamp(adapter);
652 /* reschedule to check later */
653 schedule_work(&adapter->ptp_tx_work);
656 static void igb_ptp_overflow_check(struct work_struct *work)
658 struct igb_adapter *igb =
659 container_of(work, struct igb_adapter, ptp_overflow_work.work);
660 struct timespec64 ts;
662 igb->ptp_caps.gettime64(&igb->ptp_caps, &ts);
664 pr_debug("igb overflow check at %lld.%09lu\n",
665 (long long) ts.tv_sec, ts.tv_nsec);
667 schedule_delayed_work(&igb->ptp_overflow_work,
668 IGB_SYSTIM_OVERFLOW_PERIOD);
672 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
673 * @adapter: private network adapter structure
675 * This watchdog task is scheduled to detect error case where hardware has
676 * dropped an Rx packet that was timestamped when the ring is full. The
677 * particular error is rare but leaves the device in a state unable to timestamp
678 * any future packets.
680 void igb_ptp_rx_hang(struct igb_adapter *adapter)
682 struct e1000_hw *hw = &adapter->hw;
683 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL);
684 unsigned long rx_event;
686 /* Other hardware uses per-packet timestamps */
687 if (hw->mac.type != e1000_82576)
690 /* If we don't have a valid timestamp in the registers, just update the
691 * timeout counter and exit
693 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
694 adapter->last_rx_ptp_check = jiffies;
698 /* Determine the most recent watchdog or rx_timestamp event */
699 rx_event = adapter->last_rx_ptp_check;
700 if (time_after(adapter->last_rx_timestamp, rx_event))
701 rx_event = adapter->last_rx_timestamp;
703 /* Only need to read the high RXSTMP register to clear the lock */
704 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
706 adapter->last_rx_ptp_check = jiffies;
707 adapter->rx_hwtstamp_cleared++;
708 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n");
713 * igb_ptp_tx_hang - detect error case where Tx timestamp never finishes
714 * @adapter: private network adapter structure
716 void igb_ptp_tx_hang(struct igb_adapter *adapter)
718 struct e1000_hw *hw = &adapter->hw;
719 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
722 if (!adapter->ptp_tx_skb)
725 if (!test_bit(__IGB_PTP_TX_IN_PROGRESS, &adapter->state))
728 /* If we haven't received a timestamp within the timeout, it is
729 * reasonable to assume that it will never occur, so we can unlock the
730 * timestamp bit when this occurs.
733 cancel_work_sync(&adapter->ptp_tx_work);
734 dev_kfree_skb_any(adapter->ptp_tx_skb);
735 adapter->ptp_tx_skb = NULL;
736 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
737 adapter->tx_hwtstamp_timeouts++;
738 /* Clear the tx valid bit in TSYNCTXCTL register to enable
742 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
747 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
748 * @adapter: Board private structure.
750 * If we were asked to do hardware stamping and such a time stamp is
751 * available, then it must have been for this skb here because we only
752 * allow only one such packet into the queue.
754 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
756 struct sk_buff *skb = adapter->ptp_tx_skb;
757 struct e1000_hw *hw = &adapter->hw;
758 struct skb_shared_hwtstamps shhwtstamps;
762 regval = rd32(E1000_TXSTMPL);
763 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
765 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
766 /* adjust timestamp for the TX latency based on link speed */
767 if (adapter->hw.mac.type == e1000_i210) {
768 switch (adapter->link_speed) {
770 adjust = IGB_I210_TX_LATENCY_10;
773 adjust = IGB_I210_TX_LATENCY_100;
776 adjust = IGB_I210_TX_LATENCY_1000;
781 shhwtstamps.hwtstamp =
782 ktime_add_ns(shhwtstamps.hwtstamp, adjust);
784 /* Clear the lock early before calling skb_tstamp_tx so that
785 * applications are not woken up before the lock bit is clear. We use
786 * a copy of the skb pointer to ensure other threads can't change it
787 * while we're notifying the stack.
789 adapter->ptp_tx_skb = NULL;
790 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
792 /* Notify the stack and free the skb after we've unlocked */
793 skb_tstamp_tx(skb, &shhwtstamps);
794 dev_kfree_skb_any(skb);
798 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
799 * @q_vector: Pointer to interrupt specific structure
800 * @va: Pointer to address containing Rx buffer
801 * @skb: Buffer containing timestamp and packet
803 * This function is meant to retrieve a timestamp from the first buffer of an
804 * incoming frame. The value is stored in little endian format starting on
807 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va,
810 __le64 *regval = (__le64 *)va;
811 struct igb_adapter *adapter = q_vector->adapter;
814 /* The timestamp is recorded in little endian format.
816 * Field: Reserved Reserved SYSTIML SYSTIMH
818 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb),
819 le64_to_cpu(regval[1]));
821 /* adjust timestamp for the RX latency based on link speed */
822 if (adapter->hw.mac.type == e1000_i210) {
823 switch (adapter->link_speed) {
825 adjust = IGB_I210_RX_LATENCY_10;
828 adjust = IGB_I210_RX_LATENCY_100;
831 adjust = IGB_I210_RX_LATENCY_1000;
835 skb_hwtstamps(skb)->hwtstamp =
836 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
840 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
841 * @q_vector: Pointer to interrupt specific structure
842 * @skb: Buffer containing timestamp and packet
844 * This function is meant to retrieve a timestamp from the internal registers
845 * of the adapter and store it in the skb.
847 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
850 struct igb_adapter *adapter = q_vector->adapter;
851 struct e1000_hw *hw = &adapter->hw;
855 /* If this bit is set, then the RX registers contain the time stamp. No
856 * other packet will be time stamped until we read these registers, so
857 * read the registers to make them available again. Because only one
858 * packet can be time stamped at a time, we know that the register
859 * values must belong to this one here and therefore we don't need to
860 * compare any of the additional attributes stored for it.
862 * If nothing went wrong, then it should have a shared tx_flags that we
863 * can turn into a skb_shared_hwtstamps.
865 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
868 regval = rd32(E1000_RXSTMPL);
869 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
871 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
873 /* adjust timestamp for the RX latency based on link speed */
874 if (adapter->hw.mac.type == e1000_i210) {
875 switch (adapter->link_speed) {
877 adjust = IGB_I210_RX_LATENCY_10;
880 adjust = IGB_I210_RX_LATENCY_100;
883 adjust = IGB_I210_RX_LATENCY_1000;
887 skb_hwtstamps(skb)->hwtstamp =
888 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
890 /* Update the last_rx_timestamp timer in order to enable watchdog check
891 * for error case of latched timestamp on a dropped packet.
893 adapter->last_rx_timestamp = jiffies;
897 * igb_ptp_get_ts_config - get hardware time stamping config
901 * Get the hwtstamp_config settings to return to the user. Rather than attempt
902 * to deconstruct the settings from the registers, just return a shadow copy
903 * of the last known settings.
905 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
907 struct igb_adapter *adapter = netdev_priv(netdev);
908 struct hwtstamp_config *config = &adapter->tstamp_config;
910 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
915 * igb_ptp_set_timestamp_mode - setup hardware for timestamping
916 * @adapter: networking device structure
917 * @config: hwtstamp configuration
919 * Outgoing time stamping can be enabled and disabled. Play nice and
920 * disable it when requested, although it shouldn't case any overhead
921 * when no packet needs it. At most one packet in the queue may be
922 * marked for time stamping, otherwise it would be impossible to tell
923 * for sure to which packet the hardware time stamp belongs.
925 * Incoming time stamping has to be configured via the hardware
926 * filters. Not all combinations are supported, in particular event
927 * type has to be specified. Matching the kind of event packet is
928 * not supported, with the exception of "all V2 events regardless of
931 static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter,
932 struct hwtstamp_config *config)
934 struct e1000_hw *hw = &adapter->hw;
935 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
936 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
937 u32 tsync_rx_cfg = 0;
942 /* reserved for future extensions */
946 switch (config->tx_type) {
947 case HWTSTAMP_TX_OFF:
955 switch (config->rx_filter) {
956 case HWTSTAMP_FILTER_NONE:
959 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
960 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
961 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
964 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
965 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
966 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
969 case HWTSTAMP_FILTER_PTP_V2_EVENT:
970 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
971 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
972 case HWTSTAMP_FILTER_PTP_V2_SYNC:
973 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
974 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
975 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
976 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
977 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
978 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
979 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
983 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
984 case HWTSTAMP_FILTER_NTP_ALL:
985 case HWTSTAMP_FILTER_ALL:
986 /* 82576 cannot timestamp all packets, which it needs to do to
987 * support both V1 Sync and Delay_Req messages
989 if (hw->mac.type != e1000_82576) {
990 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
991 config->rx_filter = HWTSTAMP_FILTER_ALL;
996 config->rx_filter = HWTSTAMP_FILTER_NONE;
1000 if (hw->mac.type == e1000_82575) {
1001 if (tsync_rx_ctl | tsync_tx_ctl)
1006 /* Per-packet timestamping only works if all packets are
1007 * timestamped, so enable timestamping in all packets as
1008 * long as one Rx filter was configured.
1010 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
1011 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
1012 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
1013 config->rx_filter = HWTSTAMP_FILTER_ALL;
1017 if ((hw->mac.type == e1000_i210) ||
1018 (hw->mac.type == e1000_i211)) {
1019 regval = rd32(E1000_RXPBS);
1020 regval |= E1000_RXPBS_CFG_TS_EN;
1021 wr32(E1000_RXPBS, regval);
1025 /* enable/disable TX */
1026 regval = rd32(E1000_TSYNCTXCTL);
1027 regval &= ~E1000_TSYNCTXCTL_ENABLED;
1028 regval |= tsync_tx_ctl;
1029 wr32(E1000_TSYNCTXCTL, regval);
1031 /* enable/disable RX */
1032 regval = rd32(E1000_TSYNCRXCTL);
1033 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
1034 regval |= tsync_rx_ctl;
1035 wr32(E1000_TSYNCRXCTL, regval);
1037 /* define which PTP packets are time stamped */
1038 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
1040 /* define ethertype filter for timestamped packets */
1042 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588),
1043 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
1044 E1000_ETQF_1588 | /* enable timestamping */
1045 ETH_P_1588)); /* 1588 eth protocol type */
1047 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 0);
1049 /* L4 Queue Filter[3]: filter by destination port and protocol */
1051 u32 ftqf = (IPPROTO_UDP /* UDP */
1052 | E1000_FTQF_VF_BP /* VF not compared */
1053 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
1054 | E1000_FTQF_MASK); /* mask all inputs */
1055 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
1057 wr32(E1000_IMIR(3), htons(PTP_EV_PORT));
1058 wr32(E1000_IMIREXT(3),
1059 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
1060 if (hw->mac.type == e1000_82576) {
1061 /* enable source port check */
1062 wr32(E1000_SPQF(3), htons(PTP_EV_PORT));
1063 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
1065 wr32(E1000_FTQF(3), ftqf);
1067 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
1071 /* clear TX/RX time stamp registers, just to be sure */
1072 regval = rd32(E1000_TXSTMPL);
1073 regval = rd32(E1000_TXSTMPH);
1074 regval = rd32(E1000_RXSTMPL);
1075 regval = rd32(E1000_RXSTMPH);
1081 * igb_ptp_set_ts_config - set hardware time stamping config
1086 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
1088 struct igb_adapter *adapter = netdev_priv(netdev);
1089 struct hwtstamp_config config;
1092 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1095 err = igb_ptp_set_timestamp_mode(adapter, &config);
1099 /* save these settings for future reference */
1100 memcpy(&adapter->tstamp_config, &config,
1101 sizeof(adapter->tstamp_config));
1103 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1108 * igb_ptp_init - Initialize PTP functionality
1109 * @adapter: Board private structure
1111 * This function is called at device probe to initialize the PTP
1114 void igb_ptp_init(struct igb_adapter *adapter)
1116 struct e1000_hw *hw = &adapter->hw;
1117 struct net_device *netdev = adapter->netdev;
1120 switch (hw->mac.type) {
1122 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1123 adapter->ptp_caps.owner = THIS_MODULE;
1124 adapter->ptp_caps.max_adj = 999999881;
1125 adapter->ptp_caps.n_ext_ts = 0;
1126 adapter->ptp_caps.pps = 0;
1127 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;
1128 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1129 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1130 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1131 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1132 adapter->cc.read = igb_ptp_read_82576;
1133 adapter->cc.mask = CYCLECOUNTER_MASK(64);
1134 adapter->cc.mult = 1;
1135 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
1136 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1141 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1142 adapter->ptp_caps.owner = THIS_MODULE;
1143 adapter->ptp_caps.max_adj = 62499999;
1144 adapter->ptp_caps.n_ext_ts = 0;
1145 adapter->ptp_caps.pps = 0;
1146 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580;
1147 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1148 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1149 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1150 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1151 adapter->cc.read = igb_ptp_read_82580;
1152 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580);
1153 adapter->cc.mult = 1;
1154 adapter->cc.shift = 0;
1155 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1159 for (i = 0; i < IGB_N_SDP; i++) {
1160 struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
1162 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
1164 ppd->func = PTP_PF_NONE;
1166 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1167 adapter->ptp_caps.owner = THIS_MODULE;
1168 adapter->ptp_caps.max_adj = 62499999;
1169 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;
1170 adapter->ptp_caps.n_per_out = IGB_N_PEROUT;
1171 adapter->ptp_caps.n_pins = IGB_N_SDP;
1172 adapter->ptp_caps.pps = 1;
1173 adapter->ptp_caps.pin_config = adapter->sdp_config;
1174 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580;
1175 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
1176 adapter->ptp_caps.gettime64 = igb_ptp_gettime_i210;
1177 adapter->ptp_caps.settime64 = igb_ptp_settime_i210;
1178 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210;
1179 adapter->ptp_caps.verify = igb_ptp_verify_pin;
1182 adapter->ptp_clock = NULL;
1186 spin_lock_init(&adapter->tmreg_lock);
1187 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
1189 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1190 INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
1191 igb_ptp_overflow_check);
1193 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1194 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1196 igb_ptp_reset(adapter);
1198 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1199 &adapter->pdev->dev);
1200 if (IS_ERR(adapter->ptp_clock)) {
1201 adapter->ptp_clock = NULL;
1202 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
1203 } else if (adapter->ptp_clock) {
1204 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
1205 adapter->netdev->name);
1206 adapter->ptp_flags |= IGB_PTP_ENABLED;
1211 * igb_ptp_suspend - Disable PTP work items and prepare for suspend
1212 * @adapter: Board private structure
1214 * This function stops the overflow check work and PTP Tx timestamp work, and
1215 * will prepare the device for OS suspend.
1217 void igb_ptp_suspend(struct igb_adapter *adapter)
1219 if (!(adapter->ptp_flags & IGB_PTP_ENABLED))
1222 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1223 cancel_delayed_work_sync(&adapter->ptp_overflow_work);
1225 cancel_work_sync(&adapter->ptp_tx_work);
1226 if (adapter->ptp_tx_skb) {
1227 dev_kfree_skb_any(adapter->ptp_tx_skb);
1228 adapter->ptp_tx_skb = NULL;
1229 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
1234 * igb_ptp_stop - Disable PTP device and stop the overflow check.
1235 * @adapter: Board private structure.
1237 * This function stops the PTP support and cancels the delayed work.
1239 void igb_ptp_stop(struct igb_adapter *adapter)
1241 igb_ptp_suspend(adapter);
1243 if (adapter->ptp_clock) {
1244 ptp_clock_unregister(adapter->ptp_clock);
1245 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
1246 adapter->netdev->name);
1247 adapter->ptp_flags &= ~IGB_PTP_ENABLED;
1252 * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
1253 * @adapter: Board private structure.
1255 * This function handles the reset work required to re-enable the PTP device.
1257 void igb_ptp_reset(struct igb_adapter *adapter)
1259 struct e1000_hw *hw = &adapter->hw;
1260 unsigned long flags;
1262 /* reset the tstamp_config */
1263 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1265 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1267 switch (adapter->hw.mac.type) {
1269 /* Dial the nominal frequency. */
1270 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1277 wr32(E1000_TSAUXC, 0x0);
1278 wr32(E1000_TSSDP, 0x0);
1281 (adapter->pps_sys_wrap_on ? TSINTR_SYS_WRAP : 0));
1282 wr32(E1000_IMS, E1000_IMS_TS);
1285 /* No work to do. */
1289 /* Re-initialize the timer. */
1290 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1291 struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1293 igb_ptp_write_i210(adapter, &ts);
1295 timecounter_init(&adapter->tc, &adapter->cc,
1296 ktime_to_ns(ktime_get_real()));
1299 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1303 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1304 schedule_delayed_work(&adapter->ptp_overflow_work,
1305 IGB_SYSTIM_OVERFLOW_PERIOD);