drivers/net/ethernet/intel/igb/igb_main.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Intel(R) Gigabit Ethernet Linux driver
   3  * Copyright(c) 2007-2014 Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, see <http://www.gnu.org/licenses/>.
  16  *
  17  * The full GNU General Public License is included in this distribution in
  18  * the file called "COPYING".
  19  *
  20  * Contact Information:
  21  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  23  */
  24
  25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  26
  27 #include <linux/module.h>
  28 #include <linux/types.h>
  29 #include <linux/init.h>
  30 #include <linux/bitops.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/pagemap.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/ipv6.h>
  35 #include <linux/slab.h>
  36 #include <net/checksum.h>
  37 #include <net/ip6_checksum.h>
  38 #include <net/pkt_sched.h>
  39 #include <linux/net_tstamp.h>
  40 #include <linux/mii.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if.h>
  43 #include <linux/if_vlan.h>
  44 #include <linux/pci.h>
  45 #include <linux/pci-aspm.h>
  46 #include <linux/delay.h>
  47 #include <linux/interrupt.h>
  48 #include <linux/ip.h>
  49 #include <linux/tcp.h>
  50 #include <linux/sctp.h>
  51 #include <linux/if_ether.h>
  52 #include <linux/aer.h>
  53 #include <linux/prefetch.h>
  54 #include <linux/pm_runtime.h>
  55 #include <linux/etherdevice.h>
  56 #ifdef CONFIG_IGB_DCA
  57 #include <linux/dca.h>
  58 #endif
  59 #include <linux/i2c.h>
  60 #include "igb.h"
  61
  62 #define MAJ 5
  63 #define MIN 4
  64 #define BUILD 0
  65 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  66 __stringify(BUILD) "-k"
  67
  68 enum queue_mode {
  69         QUEUE_MODE_STRICT_PRIORITY,
  70         QUEUE_MODE_STREAM_RESERVATION,
  71 };
  72
  73 enum tx_queue_prio {
  74         TX_QUEUE_PRIO_HIGH,
  75         TX_QUEUE_PRIO_LOW,
  76 };
  77
  78 char igb_driver_name[] = "igb";
  79 char igb_driver_version[] = DRV_VERSION;
  80 static const char igb_driver_string[] =
  81                                 "Intel(R) Gigabit Ethernet Network Driver";
  82 static const char igb_copyright[] =
  83                                 "Copyright (c) 2007-2014 Intel Corporation.";
  84
  85 static const struct e1000_info *igb_info_tbl[] = {
  86         [board_82575] = &e1000_82575_info,
  87 };
  88
  89 static const struct pci_device_id igb_pci_tbl[] = {
  90         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
  91         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
  92         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
  93         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
  94         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
  95         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
  96         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
  97         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
  98         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
  99         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
 100         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
 101         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
 102         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
 103         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
 104         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
 105         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
 106         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
 107         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
 108         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
 109         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
 110         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
 111         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
 112         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
 113         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
 114         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
 115         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
 116         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
 117         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
 118         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
 119         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
 120         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
 121         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
 122         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
 123         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
 124         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
 125         /* required last entry */
 126         {0, }
 127 };
 128
 129 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
 130
 131 static int igb_setup_all_tx_resources(struct igb_adapter *);
 132 static int igb_setup_all_rx_resources(struct igb_adapter *);
 133 static void igb_free_all_tx_resources(struct igb_adapter *);
 134 static void igb_free_all_rx_resources(struct igb_adapter *);
 135 static void igb_setup_mrqc(struct igb_adapter *);
 136 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
 137 static void igb_remove(struct pci_dev *pdev);
 138 static int igb_sw_init(struct igb_adapter *);
 139 int igb_open(struct net_device *);
 140 int igb_close(struct net_device *);
 141 static void igb_configure(struct igb_adapter *);
 142 static void igb_configure_tx(struct igb_adapter *);
 143 static void igb_configure_rx(struct igb_adapter *);
 144 static void igb_clean_all_tx_rings(struct igb_adapter *);
 145 static void igb_clean_all_rx_rings(struct igb_adapter *);
 146 static void igb_clean_tx_ring(struct igb_ring *);
 147 static void igb_clean_rx_ring(struct igb_ring *);
 148 static void igb_set_rx_mode(struct net_device *);
 149 static void igb_update_phy_info(struct timer_list *);
 150 static void igb_watchdog(struct timer_list *);
 151 static void igb_watchdog_task(struct work_struct *);
 152 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
 153 static void igb_get_stats64(struct net_device *dev,
 154                             struct rtnl_link_stats64 *stats);
 155 static int igb_change_mtu(struct net_device *, int);
 156 static int igb_set_mac(struct net_device *, void *);
 157 static void igb_set_uta(struct igb_adapter *adapter, bool set);
 158 static irqreturn_t igb_intr(int irq, void *);
 159 static irqreturn_t igb_intr_msi(int irq, void *);
 160 static irqreturn_t igb_msix_other(int irq, void *);
 161 static irqreturn_t igb_msix_ring(int irq, void *);
 162 #ifdef CONFIG_IGB_DCA
 163 static void igb_update_dca(struct igb_q_vector *);
 164 static void igb_setup_dca(struct igb_adapter *);
 165 #endif /* CONFIG_IGB_DCA */
 166 static int igb_poll(struct napi_struct *, int);
 167 static bool igb_clean_tx_irq(struct igb_q_vector *, int);
 168 static int igb_clean_rx_irq(struct igb_q_vector *, int);
 169 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 170 static void igb_tx_timeout(struct net_device *);
 171 static void igb_reset_task(struct work_struct *);
 172 static void igb_vlan_mode(struct net_device *netdev,
 173                           netdev_features_t features);
 174 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
 175 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
 176 static void igb_restore_vlan(struct igb_adapter *);
 177 static void igb_rar_set_index(struct igb_adapter *, u32);
 178 static void igb_ping_all_vfs(struct igb_adapter *);
 179 static void igb_msg_task(struct igb_adapter *);
 180 static void igb_vmm_control(struct igb_adapter *);
 181 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
 182 static void igb_flush_mac_table(struct igb_adapter *);
 183 static int igb_available_rars(struct igb_adapter *, u8);
 184 static void igb_set_default_mac_filter(struct igb_adapter *);
 185 static int igb_uc_sync(struct net_device *, const unsigned char *);
 186 static int igb_uc_unsync(struct net_device *, const unsigned char *);
 187 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 188 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
 189 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
 190                                int vf, u16 vlan, u8 qos, __be16 vlan_proto);
 191 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
 192 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
 193                                    bool setting);
 194 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf,
 195                                 bool setting);
 196 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
 197                                  struct ifla_vf_info *ivi);
 198 static void igb_check_vf_rate_limit(struct igb_adapter *);
 199 static void igb_nfc_filter_exit(struct igb_adapter *adapter);
 200 static void igb_nfc_filter_restore(struct igb_adapter *adapter);
 201
 202 #ifdef CONFIG_PCI_IOV
 203 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
 204 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
 205 static int igb_disable_sriov(struct pci_dev *dev);
 206 static int igb_pci_disable_sriov(struct pci_dev *dev);
 207 #endif
 208
 209 static int igb_suspend(struct device *);
 210 static int igb_resume(struct device *);
 211 static int igb_runtime_suspend(struct device *dev);
 212 static int igb_runtime_resume(struct device *dev);
 213 static int igb_runtime_idle(struct device *dev);
 214 static const struct dev_pm_ops igb_pm_ops = {
 215         SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
 216         SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
 217                         igb_runtime_idle)
 218 };
 219 static void igb_shutdown(struct pci_dev *);
 220 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
 221 #ifdef CONFIG_IGB_DCA
 222 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 223 static struct notifier_block dca_notifier = {
 224         .notifier_call  = igb_notify_dca,
 225         .next           = NULL,
 226         .priority       = 0
 227 };
 228 #endif
 229 #ifdef CONFIG_NET_POLL_CONTROLLER
 230 /* for netdump / net console */
 231 static void igb_netpoll(struct net_device *);
 232 #endif
 233 #ifdef CONFIG_PCI_IOV
 234 static unsigned int max_vfs;
 235 module_param(max_vfs, uint, 0);
 236 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
 237 #endif /* CONFIG_PCI_IOV */
 238
 239 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 240                      pci_channel_state_t);
 241 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 242 static void igb_io_resume(struct pci_dev *);
 243
 244 static const struct pci_error_handlers igb_err_handler = {
 245         .error_detected = igb_io_error_detected,
 246         .slot_reset = igb_io_slot_reset,
 247         .resume = igb_io_resume,
 248 };
 249
 250 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
 251
 252 static struct pci_driver igb_driver = {
 253         .name     = igb_driver_name,
 254         .id_table = igb_pci_tbl,
 255         .probe    = igb_probe,
 256         .remove   = igb_remove,
 257 #ifdef CONFIG_PM
 258         .driver.pm = &igb_pm_ops,
 259 #endif
 260         .shutdown = igb_shutdown,
 261         .sriov_configure = igb_pci_sriov_configure,
 262         .err_handler = &igb_err_handler
 263 };
 264
 265 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 266 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 267 MODULE_LICENSE("GPL");
 268 MODULE_VERSION(DRV_VERSION);
 269
 270 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
 271 static int debug = -1;
 272 module_param(debug, int, 0);
 273 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
 274
 275 struct igb_reg_info {
 276         u32 ofs;
 277         char *name;
 278 };
 279
 280 static const struct igb_reg_info igb_reg_info_tbl[] = {
 281
 282         /* General Registers */
 283         {E1000_CTRL, "CTRL"},
 284         {E1000_STATUS, "STATUS"},
 285         {E1000_CTRL_EXT, "CTRL_EXT"},
 286
 287         /* Interrupt Registers */
 288         {E1000_ICR, "ICR"},
 289
 290         /* RX Registers */
 291         {E1000_RCTL, "RCTL"},
 292         {E1000_RDLEN(0), "RDLEN"},
 293         {E1000_RDH(0), "RDH"},
 294         {E1000_RDT(0), "RDT"},
 295         {E1000_RXDCTL(0), "RXDCTL"},
 296         {E1000_RDBAL(0), "RDBAL"},
 297         {E1000_RDBAH(0), "RDBAH"},
 298
 299         /* TX Registers */
 300         {E1000_TCTL, "TCTL"},
 301         {E1000_TDBAL(0), "TDBAL"},
 302         {E1000_TDBAH(0), "TDBAH"},
 303         {E1000_TDLEN(0), "TDLEN"},
 304         {E1000_TDH(0), "TDH"},
 305         {E1000_TDT(0), "TDT"},
 306         {E1000_TXDCTL(0), "TXDCTL"},
 307         {E1000_TDFH, "TDFH"},
 308         {E1000_TDFT, "TDFT"},
 309         {E1000_TDFHS, "TDFHS"},
 310         {E1000_TDFPC, "TDFPC"},
 311
 312         /* List Terminator */
 313         {}
 314 };
 315
 316 /* igb_regdump - register printout routine */
 317 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
 318 {
 319         int n = 0;
 320         char rname[16];
 321         u32 regs[8];
 322
 323         switch (reginfo->ofs) {
 324         case E1000_RDLEN(0):
 325                 for (n = 0; n < 4; n++)
 326                         regs[n] = rd32(E1000_RDLEN(n));
 327                 break;
 328         case E1000_RDH(0):
 329                 for (n = 0; n < 4; n++)
 330                         regs[n] = rd32(E1000_RDH(n));
 331                 break;
 332         case E1000_RDT(0):
 333                 for (n = 0; n < 4; n++)
 334                         regs[n] = rd32(E1000_RDT(n));
 335                 break;
 336         case E1000_RXDCTL(0):
 337                 for (n = 0; n < 4; n++)
 338                         regs[n] = rd32(E1000_RXDCTL(n));
 339                 break;
 340         case E1000_RDBAL(0):
 341                 for (n = 0; n < 4; n++)
 342                         regs[n] = rd32(E1000_RDBAL(n));
 343                 break;
 344         case E1000_RDBAH(0):
 345                 for (n = 0; n < 4; n++)
 346                         regs[n] = rd32(E1000_RDBAH(n));
 347                 break;
 348         case E1000_TDBAL(0):
 349                 for (n = 0; n < 4; n++)
 350                         regs[n] = rd32(E1000_RDBAL(n));
 351                 break;
 352         case E1000_TDBAH(0):
 353                 for (n = 0; n < 4; n++)
 354                         regs[n] = rd32(E1000_TDBAH(n));
 355                 break;
 356         case E1000_TDLEN(0):
 357                 for (n = 0; n < 4; n++)
 358                         regs[n] = rd32(E1000_TDLEN(n));
 359                 break;
 360         case E1000_TDH(0):
 361                 for (n = 0; n < 4; n++)
 362                         regs[n] = rd32(E1000_TDH(n));
 363                 break;
 364         case E1000_TDT(0):
 365                 for (n = 0; n < 4; n++)
 366                         regs[n] = rd32(E1000_TDT(n));
 367                 break;
 368         case E1000_TXDCTL(0):
 369                 for (n = 0; n < 4; n++)
 370                         regs[n] = rd32(E1000_TXDCTL(n));
 371                 break;
 372         default:
 373                 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
 374                 return;
 375         }
 376
 377         snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
 378         pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
 379                 regs[2], regs[3]);
 380 }
 381
 382 /* igb_dump - Print registers, Tx-rings and Rx-rings */
 383 static void igb_dump(struct igb_adapter *adapter)
 384 {
 385         struct net_device *netdev = adapter->netdev;
 386         struct e1000_hw *hw = &adapter->hw;
 387         struct igb_reg_info *reginfo;
 388         struct igb_ring *tx_ring;
 389         union e1000_adv_tx_desc *tx_desc;
 390         struct my_u0 { u64 a; u64 b; } *u0;
 391         struct igb_ring *rx_ring;
 392         union e1000_adv_rx_desc *rx_desc;
 393         u32 staterr;
 394         u16 i, n;
 395
 396         if (!netif_msg_hw(adapter))
 397                 return;
 398
 399         /* Print netdevice Info */
 400         if (netdev) {
 401                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 402                 pr_info("Device Name     state            trans_start\n");
 403                 pr_info("%-15s %016lX %016lX\n", netdev->name,
 404                         netdev->state, dev_trans_start(netdev));
 405         }
 406
 407         /* Print Registers */
 408         dev_info(&adapter->pdev->dev, "Register Dump\n");
 409         pr_info(" Register Name   Value\n");
 410         for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
 411              reginfo->name; reginfo++) {
 412                 igb_regdump(hw, reginfo);
 413         }
 414
 415         /* Print TX Ring Summary */
 416         if (!netdev || !netif_running(netdev))
 417                 goto exit;
 418
 419         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 420         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 421         for (n = 0; n < adapter->num_tx_queues; n++) {
 422                 struct igb_tx_buffer *buffer_info;
 423                 tx_ring = adapter->tx_ring[n];
 424                 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 425                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
 426                         n, tx_ring->next_to_use, tx_ring->next_to_clean,
 427                         (u64)dma_unmap_addr(buffer_info, dma),
 428                         dma_unmap_len(buffer_info, len),
 429                         buffer_info->next_to_watch,
 430                         (u64)buffer_info->time_stamp);
 431         }
 432
 433         /* Print TX Rings */
 434         if (!netif_msg_tx_done(adapter))
 435                 goto rx_ring_summary;
 436
 437         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 438
 439         /* Transmit Descriptor Formats
 440          *
 441          * Advanced Transmit Descriptor
 442          *   +--------------------------------------------------------------+
 443          * 0 |         Buffer Address [63:0]                                |
 444          *   +--------------------------------------------------------------+
 445          * 8 | PAYLEN  | PORTS  |CC|IDX | STA | DCMD  |DTYP|MAC|RSV| DTALEN |
 446          *   +--------------------------------------------------------------+
 447          *   63      46 45    40 39 38 36 35 32 31   24             15       0
 448          */
 449
 450         for (n = 0; n < adapter->num_tx_queues; n++) {
 451                 tx_ring = adapter->tx_ring[n];
 452                 pr_info("------------------------------------\n");
 453                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 454                 pr_info("------------------------------------\n");
 455                 pr_info("T [desc]     [address 63:0  ] [PlPOCIStDDM Ln] [bi->dma       ] leng  ntw timestamp        bi->skb\n");
 456
 457                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 458                         const char *next_desc;
 459                         struct igb_tx_buffer *buffer_info;
 460                         tx_desc = IGB_TX_DESC(tx_ring, i);
 461                         buffer_info = &tx_ring->tx_buffer_info[i];
 462                         u0 = (struct my_u0 *)tx_desc;
 463                         if (i == tx_ring->next_to_use &&
 464                             i == tx_ring->next_to_clean)
 465                                 next_desc = " NTC/U";
 466                         else if (i == tx_ring->next_to_use)
 467                                 next_desc = " NTU";
 468                         else if (i == tx_ring->next_to_clean)
 469                                 next_desc = " NTC";
 470                         else
 471                                 next_desc = "";
 472
 473                         pr_info("T [0x%03X]    %016llX %016llX %016llX %04X  %p %016llX %p%s\n",
 474                                 i, le64_to_cpu(u0->a),
 475                                 le64_to_cpu(u0->b),
 476                                 (u64)dma_unmap_addr(buffer_info, dma),
 477                                 dma_unmap_len(buffer_info, len),
 478                                 buffer_info->next_to_watch,
 479                                 (u64)buffer_info->time_stamp,
 480                                 buffer_info->skb, next_desc);
 481
 482                         if (netif_msg_pktdata(adapter) && buffer_info->skb)
 483                                 print_hex_dump(KERN_INFO, "",
 484                                         DUMP_PREFIX_ADDRESS,
 485                                         16, 1, buffer_info->skb->data,
 486                                         dma_unmap_len(buffer_info, len),
 487                                         true);
 488                 }
 489         }
 490
 491         /* Print RX Rings Summary */
 492 rx_ring_summary:
 493         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 494         pr_info("Queue [NTU] [NTC]\n");
 495         for (n = 0; n < adapter->num_rx_queues; n++) {
 496                 rx_ring = adapter->rx_ring[n];
 497                 pr_info(" %5d %5X %5X\n",
 498                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 499         }
 500
 501         /* Print RX Rings */
 502         if (!netif_msg_rx_status(adapter))
 503                 goto exit;
 504
 505         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 506
 507         /* Advanced Receive Descriptor (Read) Format
 508          *    63                                           1        0
 509          *    +-----------------------------------------------------+
 510          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 511          *    +----------------------------------------------+------+
 512          *  8 |       Header Buffer Address [63:1]           |  DD  |
 513          *    +-----------------------------------------------------+
 514          *
 515          *
 516          * Advanced Receive Descriptor (Write-Back) Format
 517          *
 518          *   63       48 47    32 31  30      21 20 17 16   4 3     0
 519          *   +------------------------------------------------------+
 520          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 521          *   | Checksum   Ident  |   |           |    | Type | Type |
 522          *   +------------------------------------------------------+
 523          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 524          *   +------------------------------------------------------+
 525          *   63       48 47    32 31            20 19               0
 526          */
 527
 528         for (n = 0; n < adapter->num_rx_queues; n++) {
 529                 rx_ring = adapter->rx_ring[n];
 530                 pr_info("------------------------------------\n");
 531                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 532                 pr_info("------------------------------------\n");
 533                 pr_info("R  [desc]      [ PktBuf     A0] [  HeadBuf   DD] [bi->dma       ] [bi->skb] <-- Adv Rx Read format\n");
 534                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
 535
 536                 for (i = 0; i < rx_ring->count; i++) {
 537                         const char *next_desc;
 538                         struct igb_rx_buffer *buffer_info;
 539                         buffer_info = &rx_ring->rx_buffer_info[i];
 540                         rx_desc = IGB_RX_DESC(rx_ring, i);
 541                         u0 = (struct my_u0 *)rx_desc;
 542                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 543
 544                         if (i == rx_ring->next_to_use)
 545                                 next_desc = " NTU";
 546                         else if (i == rx_ring->next_to_clean)
 547                                 next_desc = " NTC";
 548                         else
 549                                 next_desc = "";
 550
 551                         if (staterr & E1000_RXD_STAT_DD) {
 552                                 /* Descriptor Done */
 553                                 pr_info("%s[0x%03X]     %016llX %016llX ---------------- %s\n",
 554                                         "RWB", i,
 555                                         le64_to_cpu(u0->a),
 556                                         le64_to_cpu(u0->b),
 557                                         next_desc);
 558                         } else {
 559                                 pr_info("%s[0x%03X]     %016llX %016llX %016llX %s\n",
 560                                         "R  ", i,
 561                                         le64_to_cpu(u0->a),
 562                                         le64_to_cpu(u0->b),
 563                                         (u64)buffer_info->dma,
 564                                         next_desc);
 565
 566                                 if (netif_msg_pktdata(adapter) &&
 567                                     buffer_info->dma && buffer_info->page) {
 568                                         print_hex_dump(KERN_INFO, "",
 569                                           DUMP_PREFIX_ADDRESS,
 570                                           16, 1,
 571                                           page_address(buffer_info->page) +
 572                                                       buffer_info->page_offset,
 573                                           igb_rx_bufsz(rx_ring), true);
 574                                 }
 575                         }
 576                 }
 577         }
 578
 579 exit:
 580         return;
 581 }
 582
 583 /**
 584  *  igb_get_i2c_data - Reads the I2C SDA data bit
 585  *  @hw: pointer to hardware structure
 586  *  @i2cctl: Current value of I2CCTL register
 587  *
 588  *  Returns the I2C data bit value
 589  **/
 590 static int igb_get_i2c_data(void *data)
 591 {
 592         struct igb_adapter *adapter = (struct igb_adapter *)data;
 593         struct e1000_hw *hw = &adapter->hw;
 594         s32 i2cctl = rd32(E1000_I2CPARAMS);
 595
 596         return !!(i2cctl & E1000_I2C_DATA_IN);
 597 }
 598
 599 /**
 600  *  igb_set_i2c_data - Sets the I2C data bit
 601  *  @data: pointer to hardware structure
 602  *  @state: I2C data value (0 or 1) to set
 603  *
 604  *  Sets the I2C data bit
 605  **/
 606 static void igb_set_i2c_data(void *data, int state)
 607 {
 608         struct igb_adapter *adapter = (struct igb_adapter *)data;
 609         struct e1000_hw *hw = &adapter->hw;
 610         s32 i2cctl = rd32(E1000_I2CPARAMS);
 611
 612         if (state)
 613                 i2cctl |= E1000_I2C_DATA_OUT;
 614         else
 615                 i2cctl &= ~E1000_I2C_DATA_OUT;
 616
 617         i2cctl &= ~E1000_I2C_DATA_OE_N;
 618         i2cctl |= E1000_I2C_CLK_OE_N;
 619         wr32(E1000_I2CPARAMS, i2cctl);
 620         wrfl();
 621
 622 }
 623
 624 /**
 625  *  igb_set_i2c_clk - Sets the I2C SCL clock
 626  *  @data: pointer to hardware structure
 627  *  @state: state to set clock
 628  *
 629  *  Sets the I2C clock line to state
 630  **/
 631 static void igb_set_i2c_clk(void *data, int state)
 632 {
 633         struct igb_adapter *adapter = (struct igb_adapter *)data;
 634         struct e1000_hw *hw = &adapter->hw;
 635         s32 i2cctl = rd32(E1000_I2CPARAMS);
 636
 637         if (state) {
 638                 i2cctl |= E1000_I2C_CLK_OUT;
 639                 i2cctl &= ~E1000_I2C_CLK_OE_N;
 640         } else {
 641                 i2cctl &= ~E1000_I2C_CLK_OUT;
 642                 i2cctl &= ~E1000_I2C_CLK_OE_N;
 643         }
 644         wr32(E1000_I2CPARAMS, i2cctl);
 645         wrfl();
 646 }
 647
 648 /**
 649  *  igb_get_i2c_clk - Gets the I2C SCL clock state
 650  *  @data: pointer to hardware structure
 651  *
 652  *  Gets the I2C clock state
 653  **/
 654 static int igb_get_i2c_clk(void *data)
 655 {
 656         struct igb_adapter *adapter = (struct igb_adapter *)data;
 657         struct e1000_hw *hw = &adapter->hw;
 658         s32 i2cctl = rd32(E1000_I2CPARAMS);
 659
 660         return !!(i2cctl & E1000_I2C_CLK_IN);
 661 }
 662
 663 static const struct i2c_algo_bit_data igb_i2c_algo = {
 664         .setsda         = igb_set_i2c_data,
 665         .setscl         = igb_set_i2c_clk,
 666         .getsda         = igb_get_i2c_data,
 667         .getscl         = igb_get_i2c_clk,
 668         .udelay         = 5,
 669         .timeout        = 20,
 670 };
 671
 672 /**
 673  *  igb_get_hw_dev - return device
 674  *  @hw: pointer to hardware structure
 675  *
 676  *  used by hardware layer to print debugging information
 677  **/
 678 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
 679 {
 680         struct igb_adapter *adapter = hw->back;
 681         return adapter->netdev;
 682 }
 683
 684 /**
 685  *  igb_init_module - Driver Registration Routine
 686  *
 687  *  igb_init_module is the first routine called when the driver is
 688  *  loaded. All it does is register with the PCI subsystem.
 689  **/
 690 static int __init igb_init_module(void)
 691 {
 692         int ret;
 693
 694         pr_info("%s - version %s\n",
 695                igb_driver_string, igb_driver_version);
 696         pr_info("%s\n", igb_copyright);
 697
 698 #ifdef CONFIG_IGB_DCA
 699         dca_register_notify(&dca_notifier);
 700 #endif
 701         ret = pci_register_driver(&igb_driver);
 702         return ret;
 703 }
 704
 705 module_init(igb_init_module);
 706
 707 /**
 708  *  igb_exit_module - Driver Exit Cleanup Routine
 709  *
 710  *  igb_exit_module is called just before the driver is removed
 711  *  from memory.
 712  **/
 713 static void __exit igb_exit_module(void)
 714 {
 715 #ifdef CONFIG_IGB_DCA
 716         dca_unregister_notify(&dca_notifier);
 717 #endif
 718         pci_unregister_driver(&igb_driver);
 719 }
 720
 721 module_exit(igb_exit_module);
 722
 723 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 724 /**
 725  *  igb_cache_ring_register - Descriptor ring to register mapping
 726  *  @adapter: board private structure to initialize
 727  *
 728  *  Once we know the feature-set enabled for the device, we'll cache
 729  *  the register offset the descriptor ring is assigned to.
 730  **/
 731 static void igb_cache_ring_register(struct igb_adapter *adapter)
 732 {
 733         int i = 0, j = 0;
 734         u32 rbase_offset = adapter->vfs_allocated_count;
 735
 736         switch (adapter->hw.mac.type) {
 737         case e1000_82576:
 738                 /* The queues are allocated for virtualization such that VF 0
 739                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 740                  * In order to avoid collision we start at the first free queue
 741                  * and continue consuming queues in the same sequence
 742                  */
 743                 if (adapter->vfs_allocated_count) {
 744                         for (; i < adapter->rss_queues; i++)
 745                                 adapter->rx_ring[i]->reg_idx = rbase_offset +
 746                                                                Q_IDX_82576(i);
 747                 }
 748                 /* Fall through */
 749         case e1000_82575:
 750         case e1000_82580:
 751         case e1000_i350:
 752         case e1000_i354:
 753         case e1000_i210:
 754         case e1000_i211:
 755                 /* Fall through */
 756         default:
 757                 for (; i < adapter->num_rx_queues; i++)
 758                         adapter->rx_ring[i]->reg_idx = rbase_offset + i;
 759                 for (; j < adapter->num_tx_queues; j++)
 760                         adapter->tx_ring[j]->reg_idx = rbase_offset + j;
 761                 break;
 762         }
 763 }
 764
 765 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
 766 {
 767         struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
 768         u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr);
 769         u32 value = 0;
 770
 771         if (E1000_REMOVED(hw_addr))
 772                 return ~value;
 773
 774         value = readl(&hw_addr[reg]);
 775
 776         /* reads should not return all F's */
 777         if (!(~value) && (!reg || !(~readl(hw_addr)))) {
 778                 struct net_device *netdev = igb->netdev;
 779                 hw->hw_addr = NULL;
 780                 netdev_err(netdev, "PCIe link lost\n");
 781         }
 782
 783         return value;
 784 }
 785
 786 /**
 787  *  igb_write_ivar - configure ivar for given MSI-X vector
 788  *  @hw: pointer to the HW structure
 789  *  @msix_vector: vector number we are allocating to a given ring
 790  *  @index: row index of IVAR register to write within IVAR table
 791  *  @offset: column offset of in IVAR, should be multiple of 8
 792  *
 793  *  This function is intended to handle the writing of the IVAR register
 794  *  for adapters 82576 and newer.  The IVAR table consists of 2 columns,
 795  *  each containing an cause allocation for an Rx and Tx ring, and a
 796  *  variable number of rows depending on the number of queues supported.
 797  **/
 798 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
 799                            int index, int offset)
 800 {
 801         u32 ivar = array_rd32(E1000_IVAR0, index);
 802
 803         /* clear any bits that are currently set */
 804         ivar &= ~((u32)0xFF << offset);
 805
 806         /* write vector and valid bit */
 807         ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
 808
 809         array_wr32(E1000_IVAR0, index, ivar);
 810 }
 811
 812 #define IGB_N0_QUEUE -1
 813 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
 814 {
 815         struct igb_adapter *adapter = q_vector->adapter;
 816         struct e1000_hw *hw = &adapter->hw;
 817         int rx_queue = IGB_N0_QUEUE;
 818         int tx_queue = IGB_N0_QUEUE;
 819         u32 msixbm = 0;
 820
 821         if (q_vector->rx.ring)
 822                 rx_queue = q_vector->rx.ring->reg_idx;
 823         if (q_vector->tx.ring)
 824                 tx_queue = q_vector->tx.ring->reg_idx;
 825
 826         switch (hw->mac.type) {
 827         case e1000_82575:
 828                 /* The 82575 assigns vectors using a bitmask, which matches the
 829                  * bitmask for the EICR/EIMS/EIMC registers.  To assign one
 830                  * or more queues to a vector, we write the appropriate bits
 831                  * into the MSIXBM register for that vector.
 832                  */
 833                 if (rx_queue > IGB_N0_QUEUE)
 834                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 835                 if (tx_queue > IGB_N0_QUEUE)
 836                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 837                 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
 838                         msixbm |= E1000_EIMS_OTHER;
 839                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 840                 q_vector->eims_value = msixbm;
 841                 break;
 842         case e1000_82576:
 843                 /* 82576 uses a table that essentially consists of 2 columns
 844                  * with 8 rows.  The ordering is column-major so we use the
 845                  * lower 3 bits as the row index, and the 4th bit as the
 846                  * column offset.
 847                  */
 848                 if (rx_queue > IGB_N0_QUEUE)
 849                         igb_write_ivar(hw, msix_vector,
 850                                        rx_queue & 0x7,
 851                                        (rx_queue & 0x8) << 1);
 852                 if (tx_queue > IGB_N0_QUEUE)
 853                         igb_write_ivar(hw, msix_vector,
 854                                        tx_queue & 0x7,
 855                                        ((tx_queue & 0x8) << 1) + 8);
 856                 q_vector->eims_value = BIT(msix_vector);
 857                 break;
 858         case e1000_82580:
 859         case e1000_i350:
 860         case e1000_i354:
 861         case e1000_i210:
 862         case e1000_i211:
 863                 /* On 82580 and newer adapters the scheme is similar to 82576
 864                  * however instead of ordering column-major we have things
 865                  * ordered row-major.  So we traverse the table by using
 866                  * bit 0 as the column offset, and the remaining bits as the
 867                  * row index.
 868                  */
 869                 if (rx_queue > IGB_N0_QUEUE)
 870                         igb_write_ivar(hw, msix_vector,
 871                                        rx_queue >> 1,
 872                                        (rx_queue & 0x1) << 4);
 873                 if (tx_queue > IGB_N0_QUEUE)
 874                         igb_write_ivar(hw, msix_vector,
 875                                        tx_queue >> 1,
 876                                        ((tx_queue & 0x1) << 4) + 8);
 877                 q_vector->eims_value = BIT(msix_vector);
 878                 break;
 879         default:
 880                 BUG();
 881                 break;
 882         }
 883
 884         /* add q_vector eims value to global eims_enable_mask */
 885         adapter->eims_enable_mask |= q_vector->eims_value;
 886
 887         /* configure q_vector to set itr on first interrupt */
 888         q_vector->set_itr = 1;
 889 }
 890
 891 /**
 892  *  igb_configure_msix - Configure MSI-X hardware
 893  *  @adapter: board private structure to initialize
 894  *
 895  *  igb_configure_msix sets up the hardware to properly
 896  *  generate MSI-X interrupts.
 897  **/
 898 static void igb_configure_msix(struct igb_adapter *adapter)
 899 {
 900         u32 tmp;
 901         int i, vector = 0;
 902         struct e1000_hw *hw = &adapter->hw;
 903
 904         adapter->eims_enable_mask = 0;
 905
 906         /* set vector for other causes, i.e. link changes */
 907         switch (hw->mac.type) {
 908         case e1000_82575:
 909                 tmp = rd32(E1000_CTRL_EXT);
 910                 /* enable MSI-X PBA support*/
 911                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 912
 913                 /* Auto-Mask interrupts upon ICR read. */
 914                 tmp |= E1000_CTRL_EXT_EIAME;
 915                 tmp |= E1000_CTRL_EXT_IRCA;
 916
 917                 wr32(E1000_CTRL_EXT, tmp);
 918
 919                 /* enable msix_other interrupt */
 920                 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
 921                 adapter->eims_other = E1000_EIMS_OTHER;
 922
 923                 break;
 924
 925         case e1000_82576:
 926         case e1000_82580:
 927         case e1000_i350:
 928         case e1000_i354:
 929         case e1000_i210:
 930         case e1000_i211:
 931                 /* Turn on MSI-X capability first, or our settings
 932                  * won't stick.  And it will take days to debug.
 933                  */
 934                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 935                      E1000_GPIE_PBA | E1000_GPIE_EIAME |
 936                      E1000_GPIE_NSICR);
 937
 938                 /* enable msix_other interrupt */
 939                 adapter->eims_other = BIT(vector);
 940                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 941
 942                 wr32(E1000_IVAR_MISC, tmp);
 943                 break;
 944         default:
 945                 /* do nothing, since nothing else supports MSI-X */
 946                 break;
 947         } /* switch (hw->mac.type) */
 948
 949         adapter->eims_enable_mask |= adapter->eims_other;
 950
 951         for (i = 0; i < adapter->num_q_vectors; i++)
 952                 igb_assign_vector(adapter->q_vector[i], vector++);
 953
 954         wrfl();
 955 }
 956
 957 /**
 958  *  igb_request_msix - Initialize MSI-X interrupts
 959  *  @adapter: board private structure to initialize
 960  *
 961  *  igb_request_msix allocates MSI-X vectors and requests interrupts from the
 962  *  kernel.
 963  **/
 964 static int igb_request_msix(struct igb_adapter *adapter)
 965 {
 966         struct net_device *netdev = adapter->netdev;
 967         int i, err = 0, vector = 0, free_vector = 0;
 968
 969         err = request_irq(adapter->msix_entries[vector].vector,
 970                           igb_msix_other, 0, netdev->name, adapter);
 971         if (err)
 972                 goto err_out;
 973
 974         for (i = 0; i < adapter->num_q_vectors; i++) {
 975                 struct igb_q_vector *q_vector = adapter->q_vector[i];
 976
 977                 vector++;
 978
 979                 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
 980
 981                 if (q_vector->rx.ring && q_vector->tx.ring)
 982                         sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
 983                                 q_vector->rx.ring->queue_index);
 984                 else if (q_vector->tx.ring)
 985                         sprintf(q_vector->name, "%s-tx-%u", netdev->name,
 986                                 q_vector->tx.ring->queue_index);
 987                 else if (q_vector->rx.ring)
 988                         sprintf(q_vector->name, "%s-rx-%u", netdev->name,
 989                                 q_vector->rx.ring->queue_index);
 990                 else
 991                         sprintf(q_vector->name, "%s-unused", netdev->name);
 992
 993                 err = request_irq(adapter->msix_entries[vector].vector,
 994                                   igb_msix_ring, 0, q_vector->name,
 995                                   q_vector);
 996                 if (err)
 997                         goto err_free;
 998         }
 999
1000         igb_configure_msix(adapter);
1001         return 0;
1002
1003 err_free:
1004         /* free already assigned IRQs */
1005         free_irq(adapter->msix_entries[free_vector++].vector, adapter);
1006
1007         vector--;
1008         for (i = 0; i < vector; i++) {
1009                 free_irq(adapter->msix_entries[free_vector++].vector,
1010                          adapter->q_vector[i]);
1011         }
1012 err_out:
1013         return err;
1014 }
1015
1016 /**
1017  *  igb_free_q_vector - Free memory allocated for specific interrupt vector
1018  *  @adapter: board private structure to initialize
1019  *  @v_idx: Index of vector to be freed
1020  *
1021  *  This function frees the memory allocated to the q_vector.
1022  **/
1023 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1024 {
1025         struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1026
1027         adapter->q_vector[v_idx] = NULL;
1028
1029         /* igb_get_stats64() might access the rings on this vector,
1030          * we must wait a grace period before freeing it.
1031          */
1032         if (q_vector)
1033                 kfree_rcu(q_vector, rcu);
1034 }
1035
1036 /**
1037  *  igb_reset_q_vector - Reset config for interrupt vector
1038  *  @adapter: board private structure to initialize
1039  *  @v_idx: Index of vector to be reset
1040  *
1041  *  If NAPI is enabled it will delete any references to the
1042  *  NAPI struct. This is preparation for igb_free_q_vector.
1043  **/
1044 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1045 {
1046         struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1047
1048         /* Coming from igb_set_interrupt_capability, the vectors are not yet
1049          * allocated. So, q_vector is NULL so we should stop here.
1050          */
1051         if (!q_vector)
1052                 return;
1053
1054         if (q_vector->tx.ring)
1055                 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1056
1057         if (q_vector->rx.ring)
1058                 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1059
1060         netif_napi_del(&q_vector->napi);
1061
1062 }
1063
1064 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1065 {
1066         int v_idx = adapter->num_q_vectors;
1067
1068         if (adapter->flags & IGB_FLAG_HAS_MSIX)
1069                 pci_disable_msix(adapter->pdev);
1070         else if (adapter->flags & IGB_FLAG_HAS_MSI)
1071                 pci_disable_msi(adapter->pdev);
1072
1073         while (v_idx--)
1074                 igb_reset_q_vector(adapter, v_idx);
1075 }
1076
1077 /**
1078  *  igb_free_q_vectors - Free memory allocated for interrupt vectors
1079  *  @adapter: board private structure to initialize
1080  *
1081  *  This function frees the memory allocated to the q_vectors.  In addition if
1082  *  NAPI is enabled it will delete any references to the NAPI struct prior
1083  *  to freeing the q_vector.
1084  **/
1085 static void igb_free_q_vectors(struct igb_adapter *adapter)
1086 {
1087         int v_idx = adapter->num_q_vectors;
1088
1089         adapter->num_tx_queues = 0;
1090         adapter->num_rx_queues = 0;
1091         adapter->num_q_vectors = 0;
1092
1093         while (v_idx--) {
1094                 igb_reset_q_vector(adapter, v_idx);
1095                 igb_free_q_vector(adapter, v_idx);
1096         }
1097 }
1098
1099 /**
1100  *  igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1101  *  @adapter: board private structure to initialize
1102  *
1103  *  This function resets the device so that it has 0 Rx queues, Tx queues, and
1104  *  MSI-X interrupts allocated.
1105  */
1106 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1107 {
1108         igb_free_q_vectors(adapter);
1109         igb_reset_interrupt_capability(adapter);
1110 }
1111
1112 /**
1113  *  igb_set_interrupt_capability - set MSI or MSI-X if supported
1114  *  @adapter: board private structure to initialize
1115  *  @msix: boolean value of MSIX capability
1116  *
1117  *  Attempt to configure interrupts using the best available
1118  *  capabilities of the hardware and kernel.
1119  **/
1120 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1121 {
1122         int err;
1123         int numvecs, i;
1124
1125         if (!msix)
1126                 goto msi_only;
1127         adapter->flags |= IGB_FLAG_HAS_MSIX;
1128
1129         /* Number of supported queues. */
1130         adapter->num_rx_queues = adapter->rss_queues;
1131         if (adapter->vfs_allocated_count)
1132                 adapter->num_tx_queues = 1;
1133         else
1134                 adapter->num_tx_queues = adapter->rss_queues;
1135
1136         /* start with one vector for every Rx queue */
1137         numvecs = adapter->num_rx_queues;
1138
1139         /* if Tx handler is separate add 1 for every Tx queue */
1140         if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1141                 numvecs += adapter->num_tx_queues;
1142
1143         /* store the number of vectors reserved for queues */
1144         adapter->num_q_vectors = numvecs;
1145
1146         /* add 1 vector for link status interrupts */
1147         numvecs++;
1148         for (i = 0; i < numvecs; i++)
1149                 adapter->msix_entries[i].entry = i;
1150
1151         err = pci_enable_msix_range(adapter->pdev,
1152                                     adapter->msix_entries,
1153                                     numvecs,
1154                                     numvecs);
1155         if (err > 0)
1156                 return;
1157
1158         igb_reset_interrupt_capability(adapter);
1159
1160         /* If we can't do MSI-X, try MSI */
1161 msi_only:
1162         adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1163 #ifdef CONFIG_PCI_IOV
1164         /* disable SR-IOV for non MSI-X configurations */
1165         if (adapter->vf_data) {
1166                 struct e1000_hw *hw = &adapter->hw;
1167                 /* disable iov and allow time for transactions to clear */
1168                 pci_disable_sriov(adapter->pdev);
1169                 msleep(500);
1170
1171                 kfree(adapter->vf_mac_list);
1172                 adapter->vf_mac_list = NULL;
1173                 kfree(adapter->vf_data);
1174                 adapter->vf_data = NULL;
1175                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1176                 wrfl();
1177                 msleep(100);
1178                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1179         }
1180 #endif
1181         adapter->vfs_allocated_count = 0;
1182         adapter->rss_queues = 1;
1183         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1184         adapter->num_rx_queues = 1;
1185         adapter->num_tx_queues = 1;
1186         adapter->num_q_vectors = 1;
1187         if (!pci_enable_msi(adapter->pdev))
1188                 adapter->flags |= IGB_FLAG_HAS_MSI;
1189 }
1190
1191 static void igb_add_ring(struct igb_ring *ring,
1192                          struct igb_ring_container *head)
1193 {
1194         head->ring = ring;
1195         head->count++;
1196 }
1197
1198 /**
1199  *  igb_alloc_q_vector - Allocate memory for a single interrupt vector
1200  *  @adapter: board private structure to initialize
1201  *  @v_count: q_vectors allocated on adapter, used for ring interleaving
1202  *  @v_idx: index of vector in adapter struct
1203  *  @txr_count: total number of Tx rings to allocate
1204  *  @txr_idx: index of first Tx ring to allocate
1205  *  @rxr_count: total number of Rx rings to allocate
1206  *  @rxr_idx: index of first Rx ring to allocate
1207  *
1208  *  We allocate one q_vector.  If allocation fails we return -ENOMEM.
1209  **/
1210 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1211                               int v_count, int v_idx,
1212                               int txr_count, int txr_idx,
1213                               int rxr_count, int rxr_idx)
1214 {
1215         struct igb_q_vector *q_vector;
1216         struct igb_ring *ring;
1217         int ring_count, size;
1218
1219         /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1220         if (txr_count > 1 || rxr_count > 1)
1221                 return -ENOMEM;
1222
1223         ring_count = txr_count + rxr_count;
1224         size = sizeof(struct igb_q_vector) +
1225                (sizeof(struct igb_ring) * ring_count);
1226
1227         /* allocate q_vector and rings */
1228         q_vector = adapter->q_vector[v_idx];
1229         if (!q_vector) {
1230                 q_vector = kzalloc(size, GFP_KERNEL);
1231         } else if (size > ksize(q_vector)) {
1232                 kfree_rcu(q_vector, rcu);
1233                 q_vector = kzalloc(size, GFP_KERNEL);
1234         } else {
1235                 memset(q_vector, 0, size);
1236         }
1237         if (!q_vector)
1238                 return -ENOMEM;
1239
1240         /* initialize NAPI */
1241         netif_napi_add(adapter->netdev, &q_vector->napi,
1242                        igb_poll, 64);
1243
1244         /* tie q_vector and adapter together */
1245         adapter->q_vector[v_idx] = q_vector;
1246         q_vector->adapter = adapter;
1247
1248         /* initialize work limits */
1249         q_vector->tx.work_limit = adapter->tx_work_limit;
1250
1251         /* initialize ITR configuration */
1252         q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
1253         q_vector->itr_val = IGB_START_ITR;
1254
1255         /* initialize pointer to rings */
1256         ring = q_vector->ring;
1257
1258         /* intialize ITR */
1259         if (rxr_count) {
1260                 /* rx or rx/tx vector */
1261                 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1262                         q_vector->itr_val = adapter->rx_itr_setting;
1263         } else {
1264                 /* tx only vector */
1265                 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1266                         q_vector->itr_val = adapter->tx_itr_setting;
1267         }
1268
1269         if (txr_count) {
1270                 /* assign generic ring traits */
1271                 ring->dev = &adapter->pdev->dev;
1272                 ring->netdev = adapter->netdev;
1273
1274                 /* configure backlink on ring */
1275                 ring->q_vector = q_vector;
1276
1277                 /* update q_vector Tx values */
1278                 igb_add_ring(ring, &q_vector->tx);
1279
1280                 /* For 82575, context index must be unique per ring. */
1281                 if (adapter->hw.mac.type == e1000_82575)
1282                         set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1283
1284                 /* apply Tx specific ring traits */
1285                 ring->count = adapter->tx_ring_count;
1286                 ring->queue_index = txr_idx;
1287
1288                 ring->cbs_enable = false;
1289                 ring->idleslope = 0;
1290                 ring->sendslope = 0;
1291                 ring->hicredit = 0;
1292                 ring->locredit = 0;
1293
1294                 u64_stats_init(&ring->tx_syncp);
1295                 u64_stats_init(&ring->tx_syncp2);
1296
1297                 /* assign ring to adapter */
1298                 adapter->tx_ring[txr_idx] = ring;
1299
1300                 /* push pointer to next ring */
1301                 ring++;
1302         }
1303
1304         if (rxr_count) {
1305                 /* assign generic ring traits */
1306                 ring->dev = &adapter->pdev->dev;
1307                 ring->netdev = adapter->netdev;
1308
1309                 /* configure backlink on ring */
1310                 ring->q_vector = q_vector;
1311
1312                 /* update q_vector Rx values */
1313                 igb_add_ring(ring, &q_vector->rx);
1314
1315                 /* set flag indicating ring supports SCTP checksum offload */
1316                 if (adapter->hw.mac.type >= e1000_82576)
1317                         set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1318
1319                 /* On i350, i354, i210, and i211, loopback VLAN packets
1320                  * have the tag byte-swapped.
1321                  */
1322                 if (adapter->hw.mac.type >= e1000_i350)
1323                         set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1324
1325                 /* apply Rx specific ring traits */
1326                 ring->count = adapter->rx_ring_count;
1327                 ring->queue_index = rxr_idx;
1328
1329                 u64_stats_init(&ring->rx_syncp);
1330
1331                 /* assign ring to adapter */
1332                 adapter->rx_ring[rxr_idx] = ring;
1333         }
1334
1335         return 0;
1336 }
1337
1338
1339 /**
1340  *  igb_alloc_q_vectors - Allocate memory for interrupt vectors
1341  *  @adapter: board private structure to initialize
1342  *
1343  *  We allocate one q_vector per queue interrupt.  If allocation fails we
1344  *  return -ENOMEM.
1345  **/
1346 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1347 {
1348         int q_vectors = adapter->num_q_vectors;
1349         int rxr_remaining = adapter->num_rx_queues;
1350         int txr_remaining = adapter->num_tx_queues;
1351         int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1352         int err;
1353
1354         if (q_vectors >= (rxr_remaining + txr_remaining)) {
1355                 for (; rxr_remaining; v_idx++) {
1356                         err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1357                                                  0, 0, 1, rxr_idx);
1358
1359                         if (err)
1360                                 goto err_out;
1361
1362                         /* update counts and index */
1363                         rxr_remaining--;
1364                         rxr_idx++;
1365                 }
1366         }
1367
1368         for (; v_idx < q_vectors; v_idx++) {
1369                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1370                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1371
1372                 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1373                                          tqpv, txr_idx, rqpv, rxr_idx);
1374
1375                 if (err)
1376                         goto err_out;
1377
1378                 /* update counts and index */
1379                 rxr_remaining -= rqpv;
1380                 txr_remaining -= tqpv;
1381                 rxr_idx++;
1382                 txr_idx++;
1383         }
1384
1385         return 0;
1386
1387 err_out:
1388         adapter->num_tx_queues = 0;
1389         adapter->num_rx_queues = 0;
1390         adapter->num_q_vectors = 0;
1391
1392         while (v_idx--)
1393                 igb_free_q_vector(adapter, v_idx);
1394
1395         return -ENOMEM;
1396 }
1397
1398 /**
1399  *  igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1400  *  @adapter: board private structure to initialize
1401  *  @msix: boolean value of MSIX capability
1402  *
1403  *  This function initializes the interrupts and allocates all of the queues.
1404  **/
1405 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1406 {
1407         struct pci_dev *pdev = adapter->pdev;
1408         int err;
1409
1410         igb_set_interrupt_capability(adapter, msix);
1411
1412         err = igb_alloc_q_vectors(adapter);
1413         if (err) {
1414                 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1415                 goto err_alloc_q_vectors;
1416         }
1417
1418         igb_cache_ring_register(adapter);
1419
1420         return 0;
1421
1422 err_alloc_q_vectors:
1423         igb_reset_interrupt_capability(adapter);
1424         return err;
1425 }
1426
1427 /**
1428  *  igb_request_irq - initialize interrupts
1429  *  @adapter: board private structure to initialize
1430  *
1431  *  Attempts to configure interrupts using the best available
1432  *  capabilities of the hardware and kernel.
1433  **/
1434 static int igb_request_irq(struct igb_adapter *adapter)
1435 {
1436         struct net_device *netdev = adapter->netdev;
1437         struct pci_dev *pdev = adapter->pdev;
1438         int err = 0;
1439
1440         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1441                 err = igb_request_msix(adapter);
1442                 if (!err)
1443                         goto request_done;
1444                 /* fall back to MSI */
1445                 igb_free_all_tx_resources(adapter);
1446                 igb_free_all_rx_resources(adapter);
1447
1448                 igb_clear_interrupt_scheme(adapter);
1449                 err = igb_init_interrupt_scheme(adapter, false);
1450                 if (err)
1451                         goto request_done;
1452
1453                 igb_setup_all_tx_resources(adapter);
1454                 igb_setup_all_rx_resources(adapter);
1455                 igb_configure(adapter);
1456         }
1457
1458         igb_assign_vector(adapter->q_vector[0], 0);
1459
1460         if (adapter->flags & IGB_FLAG_HAS_MSI) {
1461                 err = request_irq(pdev->irq, igb_intr_msi, 0,
1462                                   netdev->name, adapter);
1463                 if (!err)
1464                         goto request_done;
1465
1466                 /* fall back to legacy interrupts */
1467                 igb_reset_interrupt_capability(adapter);
1468                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1469         }
1470
1471         err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1472                           netdev->name, adapter);
1473
1474         if (err)
1475                 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1476                         err);
1477
1478 request_done:
1479         return err;
1480 }
1481
1482 static void igb_free_irq(struct igb_adapter *adapter)
1483 {
1484         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1485                 int vector = 0, i;
1486
1487                 free_irq(adapter->msix_entries[vector++].vector, adapter);
1488
1489                 for (i = 0; i < adapter->num_q_vectors; i++)
1490                         free_irq(adapter->msix_entries[vector++].vector,
1491                                  adapter->q_vector[i]);
1492         } else {
1493                 free_irq(adapter->pdev->irq, adapter);
1494         }
1495 }
1496
1497 /**
1498  *  igb_irq_disable - Mask off interrupt generation on the NIC
1499  *  @adapter: board private structure
1500  **/
1501 static void igb_irq_disable(struct igb_adapter *adapter)
1502 {
1503         struct e1000_hw *hw = &adapter->hw;
1504
1505         /* we need to be careful when disabling interrupts.  The VFs are also
1506          * mapped into these registers and so clearing the bits can cause
1507          * issues on the VF drivers so we only need to clear what we set
1508          */
1509         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1510                 u32 regval = rd32(E1000_EIAM);
1511
1512                 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1513                 wr32(E1000_EIMC, adapter->eims_enable_mask);
1514                 regval = rd32(E1000_EIAC);
1515                 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1516         }
1517
1518         wr32(E1000_IAM, 0);
1519         wr32(E1000_IMC, ~0);
1520         wrfl();
1521         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1522                 int i;
1523
1524                 for (i = 0; i < adapter->num_q_vectors; i++)
1525                         synchronize_irq(adapter->msix_entries[i].vector);
1526         } else {
1527                 synchronize_irq(adapter->pdev->irq);
1528         }
1529 }
1530
1531 /**
1532  *  igb_irq_enable - Enable default interrupt generation settings
1533  *  @adapter: board private structure
1534  **/
1535 static void igb_irq_enable(struct igb_adapter *adapter)
1536 {
1537         struct e1000_hw *hw = &adapter->hw;
1538
1539         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1540                 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1541                 u32 regval = rd32(E1000_EIAC);
1542
1543                 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1544                 regval = rd32(E1000_EIAM);
1545                 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1546                 wr32(E1000_EIMS, adapter->eims_enable_mask);
1547                 if (adapter->vfs_allocated_count) {
1548                         wr32(E1000_MBVFIMR, 0xFF);
1549                         ims |= E1000_IMS_VMMB;
1550                 }
1551                 wr32(E1000_IMS, ims);
1552         } else {
1553                 wr32(E1000_IMS, IMS_ENABLE_MASK |
1554                                 E1000_IMS_DRSTA);
1555                 wr32(E1000_IAM, IMS_ENABLE_MASK |
1556                                 E1000_IMS_DRSTA);
1557         }
1558 }
1559
1560 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1561 {
1562         struct e1000_hw *hw = &adapter->hw;
1563         u16 pf_id = adapter->vfs_allocated_count;
1564         u16 vid = adapter->hw.mng_cookie.vlan_id;
1565         u16 old_vid = adapter->mng_vlan_id;
1566
1567         if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1568                 /* add VID to filter table */
1569                 igb_vfta_set(hw, vid, pf_id, true, true);
1570                 adapter->mng_vlan_id = vid;
1571         } else {
1572                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1573         }
1574
1575         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1576             (vid != old_vid) &&
1577             !test_bit(old_vid, adapter->active_vlans)) {
1578                 /* remove VID from filter table */
1579                 igb_vfta_set(hw, vid, pf_id, false, true);
1580         }
1581 }
1582
1583 /**
1584  *  igb_release_hw_control - release control of the h/w to f/w
1585  *  @adapter: address of board private structure
1586  *
1587  *  igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1588  *  For ASF and Pass Through versions of f/w this means that the
1589  *  driver is no longer loaded.
1590  **/
1591 static void igb_release_hw_control(struct igb_adapter *adapter)
1592 {
1593         struct e1000_hw *hw = &adapter->hw;
1594         u32 ctrl_ext;
1595
1596         /* Let firmware take over control of h/w */
1597         ctrl_ext = rd32(E1000_CTRL_EXT);
1598         wr32(E1000_CTRL_EXT,
1599                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1600 }
1601
1602 /**
1603  *  igb_get_hw_control - get control of the h/w from f/w
1604  *  @adapter: address of board private structure
1605  *
1606  *  igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1607  *  For ASF and Pass Through versions of f/w this means that
1608  *  the driver is loaded.
1609  **/
1610 static void igb_get_hw_control(struct igb_adapter *adapter)
1611 {
1612         struct e1000_hw *hw = &adapter->hw;
1613         u32 ctrl_ext;
1614
1615         /* Let firmware know the driver has taken over */
1616         ctrl_ext = rd32(E1000_CTRL_EXT);
1617         wr32(E1000_CTRL_EXT,
1618                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1619 }
1620
1621 static void enable_fqtss(struct igb_adapter *adapter, bool enable)
1622 {
1623         struct net_device *netdev = adapter->netdev;
1624         struct e1000_hw *hw = &adapter->hw;
1625
1626         WARN_ON(hw->mac.type != e1000_i210);
1627
1628         if (enable)
1629                 adapter->flags |= IGB_FLAG_FQTSS;
1630         else
1631                 adapter->flags &= ~IGB_FLAG_FQTSS;
1632
1633         if (netif_running(netdev))
1634                 schedule_work(&adapter->reset_task);
1635 }
1636
1637 static bool is_fqtss_enabled(struct igb_adapter *adapter)
1638 {
1639         return (adapter->flags & IGB_FLAG_FQTSS) ? true : false;
1640 }
1641
1642 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue,
1643                                    enum tx_queue_prio prio)
1644 {
1645         u32 val;
1646
1647         WARN_ON(hw->mac.type != e1000_i210);
1648         WARN_ON(queue < 0 || queue > 4);
1649
1650         val = rd32(E1000_I210_TXDCTL(queue));
1651
1652         if (prio == TX_QUEUE_PRIO_HIGH)
1653                 val |= E1000_TXDCTL_PRIORITY;
1654         else
1655                 val &= ~E1000_TXDCTL_PRIORITY;
1656
1657         wr32(E1000_I210_TXDCTL(queue), val);
1658 }
1659
1660 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode)
1661 {
1662         u32 val;
1663
1664         WARN_ON(hw->mac.type != e1000_i210);
1665         WARN_ON(queue < 0 || queue > 1);
1666
1667         val = rd32(E1000_I210_TQAVCC(queue));
1668
1669         if (mode == QUEUE_MODE_STREAM_RESERVATION)
1670                 val |= E1000_TQAVCC_QUEUEMODE;
1671         else
1672                 val &= ~E1000_TQAVCC_QUEUEMODE;
1673
1674         wr32(E1000_I210_TQAVCC(queue), val);
1675 }
1676
1677 /**
1678  *  igb_configure_cbs - Configure Credit-Based Shaper (CBS)
1679  *  @adapter: pointer to adapter struct
1680  *  @queue: queue number
1681  *  @enable: true = enable CBS, false = disable CBS
1682  *  @idleslope: idleSlope in kbps
1683  *  @sendslope: sendSlope in kbps
1684  *  @hicredit: hiCredit in bytes
1685  *  @locredit: loCredit in bytes
1686  *
1687  *  Configure CBS for a given hardware queue. When disabling, idleslope,
1688  *  sendslope, hicredit, locredit arguments are ignored. Returns 0 if
1689  *  success. Negative otherwise.
1690  **/
1691 static void igb_configure_cbs(struct igb_adapter *adapter, int queue,
1692                               bool enable, int idleslope, int sendslope,
1693                               int hicredit, int locredit)
1694 {
1695         struct net_device *netdev = adapter->netdev;
1696         struct e1000_hw *hw = &adapter->hw;
1697         u32 tqavcc;
1698         u16 value;
1699
1700         WARN_ON(hw->mac.type != e1000_i210);
1701         WARN_ON(queue < 0 || queue > 1);
1702
1703         if (enable || queue == 0) {
1704                 /* i210 does not allow the queue 0 to be in the Strict
1705                  * Priority mode while the Qav mode is enabled, so,
1706                  * instead of disabling strict priority mode, we give
1707                  * queue 0 the maximum of credits possible.
1708                  *
1709                  * See section 8.12.19 of the i210 datasheet, "Note:
1710                  * Queue0 QueueMode must be set to 1b when
1711                  * TransmitMode is set to Qav."
1712                  */
1713                 if (queue == 0 && !enable) {
1714                         /* max "linkspeed" idleslope in kbps */
1715                         idleslope = 1000000;
1716                         hicredit = ETH_FRAME_LEN;
1717                 }
1718
1719                 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH);
1720                 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION);
1721
1722                 /* According to i210 datasheet section 7.2.7.7, we should set
1723                  * the 'idleSlope' field from TQAVCC register following the
1724                  * equation:
1725                  *
1726                  * For 100 Mbps link speed:
1727                  *
1728                  *     value = BW * 0x7735 * 0.2                          (E1)
1729                  *
1730                  * For 1000Mbps link speed:
1731                  *
1732                  *     value = BW * 0x7735 * 2                            (E2)
1733                  *
1734                  * E1 and E2 can be merged into one equation as shown below.
1735                  * Note that 'link-speed' is in Mbps.
1736                  *
1737                  *     value = BW * 0x7735 * 2 * link-speed
1738                  *                           --------------               (E3)
1739                  *                                1000
1740                  *
1741                  * 'BW' is the percentage bandwidth out of full link speed
1742                  * which can be found with the following equation. Note that
1743                  * idleSlope here is the parameter from this function which
1744                  * is in kbps.
1745                  *
1746                  *     BW =     idleSlope
1747                  *          -----------------                             (E4)
1748                  *          link-speed * 1000
1749                  *
1750                  * That said, we can come up with a generic equation to
1751                  * calculate the value we should set it TQAVCC register by
1752                  * replacing 'BW' in E3 by E4. The resulting equation is:
1753                  *
1754                  * value =     idleSlope     * 0x7735 * 2 * link-speed
1755                  *         -----------------            --------------    (E5)
1756                  *         link-speed * 1000                 1000
1757                  *
1758                  * 'link-speed' is present in both sides of the fraction so
1759                  * it is canceled out. The final equation is the following:
1760                  *
1761                  *     value = idleSlope * 61034
1762                  *             -----------------                          (E6)
1763                  *                  1000000
1764                  *
1765                  * NOTE: For i210, given the above, we can see that idleslope
1766                  *       is represented in 16.38431 kbps units by the value at
1767                  *       the TQAVCC register (1Gbps / 61034), which reduces
1768                  *       the granularity for idleslope increments.
1769                  *       For instance, if you want to configure a 2576kbps
1770                  *       idleslope, the value to be written on the register
1771                  *       would have to be 157.23. If rounded down, you end
1772                  *       up with less bandwidth available than originally
1773                  *       required (~2572 kbps). If rounded up, you end up
1774                  *       with a higher bandwidth (~2589 kbps). Below the
1775                  *       approach we take is to always round up the
1776                  *       calculated value, so the resulting bandwidth might
1777                  *       be slightly higher for some configurations.
1778                  */
1779                 value = DIV_ROUND_UP_ULL(idleslope * 61034ULL, 1000000);
1780
1781                 tqavcc = rd32(E1000_I210_TQAVCC(queue));
1782                 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1783                 tqavcc |= value;
1784                 wr32(E1000_I210_TQAVCC(queue), tqavcc);
1785
1786                 wr32(E1000_I210_TQAVHC(queue), 0x80000000 + hicredit * 0x7735);
1787         } else {
1788                 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW);
1789                 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY);
1790
1791                 /* Set idleSlope to zero. */
1792                 tqavcc = rd32(E1000_I210_TQAVCC(queue));
1793                 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1794                 wr32(E1000_I210_TQAVCC(queue), tqavcc);
1795
1796                 /* Set hiCredit to zero. */
1797                 wr32(E1000_I210_TQAVHC(queue), 0);
1798         }
1799
1800         /* XXX: In i210 controller the sendSlope and loCredit parameters from
1801          * CBS are not configurable by software so we don't do any 'controller
1802          * configuration' in respect to these parameters.
1803          */
1804
1805         netdev_dbg(netdev, "CBS %s: queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n",
1806                    (enable) ? "enabled" : "disabled", queue,
1807                    idleslope, sendslope, hicredit, locredit);
1808 }
1809
1810 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue,
1811                                bool enable, int idleslope, int sendslope,
1812                                int hicredit, int locredit)
1813 {
1814         struct igb_ring *ring;
1815
1816         if (queue < 0 || queue > adapter->num_tx_queues)
1817                 return -EINVAL;
1818
1819         ring = adapter->tx_ring[queue];
1820
1821         ring->cbs_enable = enable;
1822         ring->idleslope = idleslope;
1823         ring->sendslope = sendslope;
1824         ring->hicredit = hicredit;
1825         ring->locredit = locredit;
1826
1827         return 0;
1828 }
1829
1830 static bool is_any_cbs_enabled(struct igb_adapter *adapter)
1831 {
1832         struct igb_ring *ring;
1833         int i;
1834
1835         for (i = 0; i < adapter->num_tx_queues; i++) {
1836                 ring = adapter->tx_ring[i];
1837
1838                 if (ring->cbs_enable)
1839                         return true;
1840         }
1841
1842         return false;
1843 }
1844
1845 static void igb_setup_tx_mode(struct igb_adapter *adapter)
1846 {
1847         struct net_device *netdev = adapter->netdev;
1848         struct e1000_hw *hw = &adapter->hw;
1849         u32 val;
1850
1851         /* Only i210 controller supports changing the transmission mode. */
1852         if (hw->mac.type != e1000_i210)
1853                 return;
1854
1855         if (is_fqtss_enabled(adapter)) {
1856                 int i, max_queue;
1857
1858                 /* Configure TQAVCTRL register: set transmit mode to 'Qav',
1859                  * set data fetch arbitration to 'round robin' and set data
1860                  * transfer arbitration to 'credit shaper algorithm.
1861                  */
1862                 val = rd32(E1000_I210_TQAVCTRL);
1863                 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_DATATRANARB;
1864                 val &= ~E1000_TQAVCTRL_DATAFETCHARB;
1865                 wr32(E1000_I210_TQAVCTRL, val);
1866
1867                 /* Configure Tx and Rx packet buffers sizes as described in
1868                  * i210 datasheet section 7.2.7.7.
1869                  */
1870                 val = rd32(E1000_TXPBS);
1871                 val &= ~I210_TXPBSIZE_MASK;
1872                 val |= I210_TXPBSIZE_PB0_8KB | I210_TXPBSIZE_PB1_8KB |
1873                         I210_TXPBSIZE_PB2_4KB | I210_TXPBSIZE_PB3_4KB;
1874                 wr32(E1000_TXPBS, val);
1875
1876                 val = rd32(E1000_RXPBS);
1877                 val &= ~I210_RXPBSIZE_MASK;
1878                 val |= I210_RXPBSIZE_PB_32KB;
1879                 wr32(E1000_RXPBS, val);
1880
1881                 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ
1882                  * register should not exceed the buffer size programmed in
1883                  * TXPBS. The smallest buffer size programmed in TXPBS is 4kB
1884                  * so according to the datasheet we should set MAX_TPKT_SIZE to
1885                  * 4kB / 64.
1886                  *
1887                  * However, when we do so, no frame from queue 2 and 3 are
1888                  * transmitted.  It seems the MAX_TPKT_SIZE should not be great
1889                  * or _equal_ to the buffer size programmed in TXPBS. For this
1890                  * reason, we set set MAX_ TPKT_SIZE to (4kB - 1) / 64.
1891                  */
1892                 val = (4096 - 1) / 64;
1893                 wr32(E1000_I210_DTXMXPKTSZ, val);
1894
1895                 /* Since FQTSS mode is enabled, apply any CBS configuration
1896                  * previously set. If no previous CBS configuration has been
1897                  * done, then the initial configuration is applied, which means
1898                  * CBS is disabled.
1899                  */
1900                 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ?
1901                             adapter->num_tx_queues : I210_SR_QUEUES_NUM;
1902
1903                 for (i = 0; i < max_queue; i++) {
1904                         struct igb_ring *ring = adapter->tx_ring[i];
1905
1906                         igb_configure_cbs(adapter, i, ring->cbs_enable,
1907                                           ring->idleslope, ring->sendslope,
1908                                           ring->hicredit, ring->locredit);
1909                 }
1910         } else {
1911                 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
1912                 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
1913                 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT);
1914
1915                 val = rd32(E1000_I210_TQAVCTRL);
1916                 /* According to Section 8.12.21, the other flags we've set when
1917                  * enabling FQTSS are not relevant when disabling FQTSS so we
1918                  * don't set they here.
1919                  */
1920                 val &= ~E1000_TQAVCTRL_XMIT_MODE;
1921                 wr32(E1000_I210_TQAVCTRL, val);
1922         }
1923
1924         netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ?
1925                    "enabled" : "disabled");
1926 }
1927
1928 /**
1929  *  igb_configure - configure the hardware for RX and TX
1930  *  @adapter: private board structure
1931  **/
1932 static void igb_configure(struct igb_adapter *adapter)
1933 {
1934         struct net_device *netdev = adapter->netdev;
1935         int i;
1936
1937         igb_get_hw_control(adapter);
1938         igb_set_rx_mode(netdev);
1939         igb_setup_tx_mode(adapter);
1940
1941         igb_restore_vlan(adapter);
1942
1943         igb_setup_tctl(adapter);
1944         igb_setup_mrqc(adapter);
1945         igb_setup_rctl(adapter);
1946
1947         igb_nfc_filter_restore(adapter);
1948         igb_configure_tx(adapter);
1949         igb_configure_rx(adapter);
1950
1951         igb_rx_fifo_flush_82575(&adapter->hw);
1952
1953         /* call igb_desc_unused which always leaves
1954          * at least 1 descriptor unused to make sure
1955          * next_to_use != next_to_clean
1956          */
1957         for (i = 0; i < adapter->num_rx_queues; i++) {
1958                 struct igb_ring *ring = adapter->rx_ring[i];
1959                 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1960         }
1961 }
1962
1963 /**
1964  *  igb_power_up_link - Power up the phy/serdes link
1965  *  @adapter: address of board private structure
1966  **/
1967 void igb_power_up_link(struct igb_adapter *adapter)
1968 {
1969         igb_reset_phy(&adapter->hw);
1970
1971         if (adapter->hw.phy.media_type == e1000_media_type_copper)
1972                 igb_power_up_phy_copper(&adapter->hw);
1973         else
1974                 igb_power_up_serdes_link_82575(&adapter->hw);
1975
1976         igb_setup_link(&adapter->hw);
1977 }
1978
1979 /**
1980  *  igb_power_down_link - Power down the phy/serdes link
1981  *  @adapter: address of board private structure
1982  */
1983 static void igb_power_down_link(struct igb_adapter *adapter)
1984 {
1985         if (adapter->hw.phy.media_type == e1000_media_type_copper)
1986                 igb_power_down_phy_copper_82575(&adapter->hw);
1987         else
1988                 igb_shutdown_serdes_link_82575(&adapter->hw);
1989 }
1990
1991 /**
1992  * Detect and switch function for Media Auto Sense
1993  * @adapter: address of the board private structure
1994  **/
1995 static void igb_check_swap_media(struct igb_adapter *adapter)
1996 {
1997         struct e1000_hw *hw = &adapter->hw;
1998         u32 ctrl_ext, connsw;
1999         bool swap_now = false;
2000
2001         ctrl_ext = rd32(E1000_CTRL_EXT);
2002         connsw = rd32(E1000_CONNSW);
2003
2004         /* need to live swap if current media is copper and we have fiber/serdes
2005          * to go to.
2006          */
2007
2008         if ((hw->phy.media_type == e1000_media_type_copper) &&
2009             (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
2010                 swap_now = true;
2011         } else if (!(connsw & E1000_CONNSW_SERDESD)) {
2012                 /* copper signal takes time to appear */
2013                 if (adapter->copper_tries < 4) {
2014                         adapter->copper_tries++;
2015                         connsw |= E1000_CONNSW_AUTOSENSE_CONF;
2016                         wr32(E1000_CONNSW, connsw);
2017                         return;
2018                 } else {
2019                         adapter->copper_tries = 0;
2020                         if ((connsw & E1000_CONNSW_PHYSD) &&
2021                             (!(connsw & E1000_CONNSW_PHY_PDN))) {
2022                                 swap_now = true;
2023                                 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
2024                                 wr32(E1000_CONNSW, connsw);
2025                         }
2026                 }
2027         }
2028
2029         if (!swap_now)
2030                 return;
2031
2032         switch (hw->phy.media_type) {
2033         case e1000_media_type_copper:
2034                 netdev_info(adapter->netdev,
2035                         "MAS: changing media to fiber/serdes\n");
2036                 ctrl_ext |=
2037                         E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2038                 adapter->flags |= IGB_FLAG_MEDIA_RESET;
2039                 adapter->copper_tries = 0;
2040                 break;
2041         case e1000_media_type_internal_serdes:
2042         case e1000_media_type_fiber:
2043                 netdev_info(adapter->netdev,
2044                         "MAS: changing media to copper\n");
2045                 ctrl_ext &=
2046                         ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2047                 adapter->flags |= IGB_FLAG_MEDIA_RESET;
2048                 break;
2049         default:
2050                 /* shouldn't get here during regular operation */
2051                 netdev_err(adapter->netdev,
2052                         "AMS: Invalid media type found, returning\n");
2053                 break;
2054         }
2055         wr32(E1000_CTRL_EXT, ctrl_ext);
2056 }
2057
2058 /**
2059  *  igb_up - Open the interface and prepare it to handle traffic
2060  *  @adapter: board private structure
2061  **/
2062 int igb_up(struct igb_adapter *adapter)
2063 {
2064         struct e1000_hw *hw = &adapter->hw;
2065         int i;
2066
2067         /* hardware has been reset, we need to reload some things */
2068         igb_configure(adapter);
2069
2070         clear_bit(__IGB_DOWN, &adapter->state);
2071
2072         for (i = 0; i < adapter->num_q_vectors; i++)
2073                 napi_enable(&(adapter->q_vector[i]->napi));
2074
2075         if (adapter->flags & IGB_FLAG_HAS_MSIX)
2076                 igb_configure_msix(adapter);
2077         else
2078                 igb_assign_vector(adapter->q_vector[0], 0);
2079
2080         /* Clear any pending interrupts. */
2081         rd32(E1000_ICR);
2082         igb_irq_enable(adapter);
2083
2084         /* notify VFs that reset has been completed */
2085         if (adapter->vfs_allocated_count) {
2086                 u32 reg_data = rd32(E1000_CTRL_EXT);
2087
2088                 reg_data |= E1000_CTRL_EXT_PFRSTD;
2089                 wr32(E1000_CTRL_EXT, reg_data);
2090         }
2091
2092         netif_tx_start_all_queues(adapter->netdev);
2093
2094         /* start the watchdog. */
2095         hw->mac.get_link_status = 1;
2096         schedule_work(&adapter->watchdog_task);
2097
2098         if ((adapter->flags & IGB_FLAG_EEE) &&
2099             (!hw->dev_spec._82575.eee_disable))
2100                 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
2101
2102         return 0;
2103 }
2104
2105 void igb_down(struct igb_adapter *adapter)
2106 {
2107         struct net_device *netdev = adapter->netdev;
2108         struct e1000_hw *hw = &adapter->hw;
2109         u32 tctl, rctl;
2110         int i;
2111
2112         /* signal that we're down so the interrupt handler does not
2113          * reschedule our watchdog timer
2114          */
2115         set_bit(__IGB_DOWN, &adapter->state);
2116
2117         /* disable receives in the hardware */
2118         rctl = rd32(E1000_RCTL);
2119         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2120         /* flush and sleep below */
2121
2122         igb_nfc_filter_exit(adapter);
2123
2124         netif_carrier_off(netdev);
2125         netif_tx_stop_all_queues(netdev);
2126
2127         /* disable transmits in the hardware */
2128         tctl = rd32(E1000_TCTL);
2129         tctl &= ~E1000_TCTL_EN;
2130         wr32(E1000_TCTL, tctl);
2131         /* flush both disables and wait for them to finish */
2132         wrfl();
2133         usleep_range(10000, 11000);
2134
2135         igb_irq_disable(adapter);
2136
2137         adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
2138
2139         for (i = 0; i < adapter->num_q_vectors; i++) {
2140                 if (adapter->q_vector[i]) {
2141                         napi_synchronize(&adapter->q_vector[i]->napi);
2142                         napi_disable(&adapter->q_vector[i]->napi);
2143                 }
2144         }
2145
2146         del_timer_sync(&adapter->watchdog_timer);
2147         del_timer_sync(&adapter->phy_info_timer);
2148
2149         /* record the stats before reset*/
2150         spin_lock(&adapter->stats64_lock);
2151         igb_update_stats(adapter);
2152         spin_unlock(&adapter->stats64_lock);
2153
2154         adapter->link_speed = 0;
2155         adapter->link_duplex = 0;
2156
2157         if (!pci_channel_offline(adapter->pdev))
2158                 igb_reset(adapter);
2159
2160         /* clear VLAN promisc flag so VFTA will be updated if necessary */
2161         adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
2162
2163         igb_clean_all_tx_rings(adapter);
2164         igb_clean_all_rx_rings(adapter);
2165 #ifdef CONFIG_IGB_DCA
2166
2167         /* since we reset the hardware DCA settings were cleared */
2168         igb_setup_dca(adapter);
2169 #endif
2170 }
2171
2172 void igb_reinit_locked(struct igb_adapter *adapter)
2173 {
2174         WARN_ON(in_interrupt());
2175         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2176                 usleep_range(1000, 2000);
2177         igb_down(adapter);
2178         igb_up(adapter);
2179         clear_bit(__IGB_RESETTING, &adapter->state);
2180 }
2181
2182 /** igb_enable_mas - Media Autosense re-enable after swap
2183  *
2184  * @adapter: adapter struct
2185  **/
2186 static void igb_enable_mas(struct igb_adapter *adapter)
2187 {
2188         struct e1000_hw *hw = &adapter->hw;
2189         u32 connsw = rd32(E1000_CONNSW);
2190
2191         /* configure for SerDes media detect */
2192         if ((hw->phy.media_type == e1000_media_type_copper) &&
2193             (!(connsw & E1000_CONNSW_SERDESD))) {
2194                 connsw |= E1000_CONNSW_ENRGSRC;
2195                 connsw |= E1000_CONNSW_AUTOSENSE_EN;
2196                 wr32(E1000_CONNSW, connsw);
2197                 wrfl();
2198         }
2199 }
2200
2201 void igb_reset(struct igb_adapter *adapter)
2202 {
2203         struct pci_dev *pdev = adapter->pdev;
2204         struct e1000_hw *hw = &adapter->hw;
2205         struct e1000_mac_info *mac = &hw->mac;
2206         struct e1000_fc_info *fc = &hw->fc;
2207         u32 pba, hwm;
2208
2209         /* Repartition Pba for greater than 9k mtu
2210          * To take effect CTRL.RST is required.
2211          */
2212         switch (mac->type) {
2213         case e1000_i350:
2214         case e1000_i354:
2215         case e1000_82580:
2216                 pba = rd32(E1000_RXPBS);
2217                 pba = igb_rxpbs_adjust_82580(pba);
2218                 break;
2219         case e1000_82576:
2220                 pba = rd32(E1000_RXPBS);
2221                 pba &= E1000_RXPBS_SIZE_MASK_82576;
2222                 break;
2223         case e1000_82575:
2224         case e1000_i210:
2225         case e1000_i211:
2226         default:
2227                 pba = E1000_PBA_34K;
2228                 break;
2229         }
2230
2231         if (mac->type == e1000_82575) {
2232                 u32 min_rx_space, min_tx_space, needed_tx_space;
2233
2234                 /* write Rx PBA so that hardware can report correct Tx PBA */
2235                 wr32(E1000_PBA, pba);
2236
2237                 /* To maintain wire speed transmits, the Tx FIFO should be
2238                  * large enough to accommodate two full transmit packets,
2239                  * rounded up to the next 1KB and expressed in KB.  Likewise,
2240                  * the Rx FIFO should be large enough to accommodate at least
2241                  * one full receive packet and is similarly rounded up and
2242                  * expressed in KB.
2243                  */
2244                 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
2245
2246                 /* The Tx FIFO also stores 16 bytes of information about the Tx
2247                  * but don't include Ethernet FCS because hardware appends it.
2248                  * We only need to round down to the nearest 512 byte block
2249                  * count since the value we care about is 2 frames, not 1.
2250                  */
2251                 min_tx_space = adapter->max_frame_size;
2252                 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
2253                 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
2254
2255                 /* upper 16 bits has Tx packet buffer allocation size in KB */
2256                 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
2257
2258                 /* If current Tx allocation is less than the min Tx FIFO size,
2259                  * and the min Tx FIFO size is less than the current Rx FIFO
2260                  * allocation, take space away from current Rx allocation.
2261                  */
2262                 if (needed_tx_space < pba) {
2263                         pba -= needed_tx_space;
2264
2265                         /* if short on Rx space, Rx wins and must trump Tx
2266                          * adjustment
2267                          */
2268                         if (pba < min_rx_space)
2269                                 pba = min_rx_space;
2270                 }
2271
2272                 /* adjust PBA for jumbo frames */
2273                 wr32(E1000_PBA, pba);
2274         }
2275
2276         /* flow control settings
2277          * The high water mark must be low enough to fit one full frame
2278          * after transmitting the pause frame.  As such we must have enough
2279          * space to allow for us to complete our current transmit and then
2280          * receive the frame that is in progress from the link partner.
2281          * Set it to:
2282          * - the full Rx FIFO size minus one full Tx plus one full Rx frame
2283          */
2284         hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
2285
2286         fc->high_water = hwm & 0xFFFFFFF0;      /* 16-byte granularity */
2287         fc->low_water = fc->high_water - 16;
2288         fc->pause_time = 0xFFFF;
2289         fc->send_xon = 1;
2290         fc->current_mode = fc->requested_mode;
2291
2292         /* disable receive for all VFs and wait one second */
2293         if (adapter->vfs_allocated_count) {
2294                 int i;
2295
2296                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
2297                         adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
2298
2299                 /* ping all the active vfs to let them know we are going down */
2300                 igb_ping_all_vfs(adapter);
2301
2302                 /* disable transmits and receives */
2303                 wr32(E1000_VFRE, 0);
2304                 wr32(E1000_VFTE, 0);
2305         }
2306
2307         /* Allow time for pending master requests to run */
2308         hw->mac.ops.reset_hw(hw);
2309         wr32(E1000_WUC, 0);
2310
2311         if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
2312                 /* need to resetup here after media swap */
2313                 adapter->ei.get_invariants(hw);
2314                 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
2315         }
2316         if ((mac->type == e1000_82575) &&
2317             (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
2318                 igb_enable_mas(adapter);
2319         }
2320         if (hw->mac.ops.init_hw(hw))
2321                 dev_err(&pdev->dev, "Hardware Error\n");
2322
2323         /* RAR registers were cleared during init_hw, clear mac table */
2324         igb_flush_mac_table(adapter);
2325         __dev_uc_unsync(adapter->netdev, NULL);
2326
2327         /* Recover default RAR entry */
2328         igb_set_default_mac_filter(adapter);
2329
2330         /* Flow control settings reset on hardware reset, so guarantee flow
2331          * control is off when forcing speed.
2332          */
2333         if (!hw->mac.autoneg)
2334                 igb_force_mac_fc(hw);
2335
2336         igb_init_dmac(adapter, pba);
2337 #ifdef CONFIG_IGB_HWMON
2338         /* Re-initialize the thermal sensor on i350 devices. */
2339         if (!test_bit(__IGB_DOWN, &adapter->state)) {
2340                 if (mac->type == e1000_i350 && hw->bus.func == 0) {
2341                         /* If present, re-initialize the external thermal sensor
2342                          * interface.
2343                          */
2344                         if (adapter->ets)
2345                                 mac->ops.init_thermal_sensor_thresh(hw);
2346                 }
2347         }
2348 #endif
2349         /* Re-establish EEE setting */
2350         if (hw->phy.media_type == e1000_media_type_copper) {
2351                 switch (mac->type) {
2352                 case e1000_i350:
2353                 case e1000_i210:
2354                 case e1000_i211:
2355                         igb_set_eee_i350(hw, true, true);
2356                         break;
2357                 case e1000_i354:
2358                         igb_set_eee_i354(hw, true, true);
2359                         break;
2360                 default:
2361                         break;
2362                 }
2363         }
2364         if (!netif_running(adapter->netdev))
2365                 igb_power_down_link(adapter);
2366
2367         igb_update_mng_vlan(adapter);
2368
2369         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2370         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2371
2372         /* Re-enable PTP, where applicable. */
2373         if (adapter->ptp_flags & IGB_PTP_ENABLED)
2374                 igb_ptp_reset(adapter);
2375
2376         igb_get_phy_info(hw);
2377 }
2378
2379 static netdev_features_t igb_fix_features(struct net_device *netdev,
2380         netdev_features_t features)
2381 {
2382         /* Since there is no support for separate Rx/Tx vlan accel
2383          * enable/disable make sure Tx flag is always in same state as Rx.
2384          */
2385         if (features & NETIF_F_HW_VLAN_CTAG_RX)
2386                 features |= NETIF_F_HW_VLAN_CTAG_TX;
2387         else
2388                 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2389
2390         return features;
2391 }
2392
2393 static int igb_set_features(struct net_device *netdev,
2394         netdev_features_t features)
2395 {
2396         netdev_features_t changed = netdev->features ^ features;
2397         struct igb_adapter *adapter = netdev_priv(netdev);
2398
2399         if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2400                 igb_vlan_mode(netdev, features);
2401
2402         if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
2403                 return 0;
2404
2405         if (!(features & NETIF_F_NTUPLE)) {
2406                 struct hlist_node *node2;
2407                 struct igb_nfc_filter *rule;
2408
2409                 spin_lock(&adapter->nfc_lock);
2410                 hlist_for_each_entry_safe(rule, node2,
2411                                           &adapter->nfc_filter_list, nfc_node) {
2412                         igb_erase_filter(adapter, rule);
2413                         hlist_del(&rule->nfc_node);
2414                         kfree(rule);
2415                 }
2416                 spin_unlock(&adapter->nfc_lock);
2417                 adapter->nfc_filter_count = 0;
2418         }
2419
2420         netdev->features = features;
2421
2422         if (netif_running(netdev))
2423                 igb_reinit_locked(adapter);
2424         else
2425                 igb_reset(adapter);
2426
2427         return 0;
2428 }
2429
2430 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2431                            struct net_device *dev,
2432                            const unsigned char *addr, u16 vid,
2433                            u16 flags)
2434 {
2435         /* guarantee we can provide a unique filter for the unicast address */
2436         if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2437                 struct igb_adapter *adapter = netdev_priv(dev);
2438                 int vfn = adapter->vfs_allocated_count;
2439
2440                 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn))
2441                         return -ENOMEM;
2442         }
2443
2444         return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2445 }
2446
2447 #define IGB_MAX_MAC_HDR_LEN     127
2448 #define IGB_MAX_NETWORK_HDR_LEN 511
2449
2450 static netdev_features_t
2451 igb_features_check(struct sk_buff *skb, struct net_device *dev,
2452                    netdev_features_t features)
2453 {
2454         unsigned int network_hdr_len, mac_hdr_len;
2455
2456         /* Make certain the headers can be described by a context descriptor */
2457         mac_hdr_len = skb_network_header(skb) - skb->data;
2458         if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN))
2459                 return features & ~(NETIF_F_HW_CSUM |
2460                                     NETIF_F_SCTP_CRC |
2461                                     NETIF_F_HW_VLAN_CTAG_TX |
2462                                     NETIF_F_TSO |
2463                                     NETIF_F_TSO6);
2464
2465         network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
2466         if (unlikely(network_hdr_len >  IGB_MAX_NETWORK_HDR_LEN))
2467                 return features & ~(NETIF_F_HW_CSUM |
2468                                     NETIF_F_SCTP_CRC |
2469                                     NETIF_F_TSO |
2470                                     NETIF_F_TSO6);
2471
2472         /* We can only support IPV4 TSO in tunnels if we can mangle the
2473          * inner IP ID field, so strip TSO if MANGLEID is not supported.
2474          */
2475         if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
2476                 features &= ~NETIF_F_TSO;
2477
2478         return features;
2479 }
2480
2481 static int igb_offload_cbs(struct igb_adapter *adapter,
2482                            struct tc_cbs_qopt_offload *qopt)
2483 {
2484         struct e1000_hw *hw = &adapter->hw;
2485         int err;
2486
2487         /* CBS offloading is only supported by i210 controller. */
2488         if (hw->mac.type != e1000_i210)
2489                 return -EOPNOTSUPP;
2490
2491         /* CBS offloading is only supported by queue 0 and queue 1. */
2492         if (qopt->queue < 0 || qopt->queue > 1)
2493                 return -EINVAL;
2494
2495         err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable,
2496                                   qopt->idleslope, qopt->sendslope,
2497                                   qopt->hicredit, qopt->locredit);
2498         if (err)
2499                 return err;
2500
2501         if (is_fqtss_enabled(adapter)) {
2502                 igb_configure_cbs(adapter, qopt->queue, qopt->enable,
2503                                   qopt->idleslope, qopt->sendslope,
2504                                   qopt->hicredit, qopt->locredit);
2505
2506                 if (!is_any_cbs_enabled(adapter))
2507                         enable_fqtss(adapter, false);
2508
2509         } else {
2510                 enable_fqtss(adapter, true);
2511         }
2512
2513         return 0;
2514 }
2515
2516 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type,
2517                         void *type_data)
2518 {
2519         struct igb_adapter *adapter = netdev_priv(dev);
2520
2521         switch (type) {
2522         case TC_SETUP_QDISC_CBS:
2523                 return igb_offload_cbs(adapter, type_data);
2524
2525         default:
2526                 return -EOPNOTSUPP;
2527         }
2528 }
2529
2530 static const struct net_device_ops igb_netdev_ops = {
2531         .ndo_open               = igb_open,
2532         .ndo_stop               = igb_close,
2533         .ndo_start_xmit         = igb_xmit_frame,
2534         .ndo_get_stats64        = igb_get_stats64,
2535         .ndo_set_rx_mode        = igb_set_rx_mode,
2536         .ndo_set_mac_address    = igb_set_mac,
2537         .ndo_change_mtu         = igb_change_mtu,
2538         .ndo_do_ioctl           = igb_ioctl,
2539         .ndo_tx_timeout         = igb_tx_timeout,
2540         .ndo_validate_addr      = eth_validate_addr,
2541         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
2542         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
2543         .ndo_set_vf_mac         = igb_ndo_set_vf_mac,
2544         .ndo_set_vf_vlan        = igb_ndo_set_vf_vlan,
2545         .ndo_set_vf_rate        = igb_ndo_set_vf_bw,
2546         .ndo_set_vf_spoofchk    = igb_ndo_set_vf_spoofchk,
2547         .ndo_set_vf_trust       = igb_ndo_set_vf_trust,
2548         .ndo_get_vf_config      = igb_ndo_get_vf_config,
2549 #ifdef CONFIG_NET_POLL_CONTROLLER
2550         .ndo_poll_controller    = igb_netpoll,
2551 #endif
2552         .ndo_fix_features       = igb_fix_features,
2553         .ndo_set_features       = igb_set_features,
2554         .ndo_fdb_add            = igb_ndo_fdb_add,
2555         .ndo_features_check     = igb_features_check,
2556         .ndo_setup_tc           = igb_setup_tc,
2557 };
2558
2559 /**
2560  * igb_set_fw_version - Configure version string for ethtool
2561  * @adapter: adapter struct
2562  **/
2563 void igb_set_fw_version(struct igb_adapter *adapter)
2564 {
2565         struct e1000_hw *hw = &adapter->hw;
2566         struct e1000_fw_version fw;
2567
2568         igb_get_fw_version(hw, &fw);
2569
2570         switch (hw->mac.type) {
2571         case e1000_i210:
2572         case e1000_i211:
2573                 if (!(igb_get_flash_presence_i210(hw))) {
2574                         snprintf(adapter->fw_version,
2575                                  sizeof(adapter->fw_version),
2576                                  "%2d.%2d-%d",
2577                                  fw.invm_major, fw.invm_minor,
2578                                  fw.invm_img_type);
2579                         break;
2580                 }
2581                 /* fall through */
2582         default:
2583                 /* if option is rom valid, display its version too */
2584                 if (fw.or_valid) {
2585                         snprintf(adapter->fw_version,
2586                                  sizeof(adapter->fw_version),
2587                                  "%d.%d, 0x%08x, %d.%d.%d",
2588                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2589                                  fw.or_major, fw.or_build, fw.or_patch);
2590                 /* no option rom */
2591                 } else if (fw.etrack_id != 0X0000) {
2592                         snprintf(adapter->fw_version,
2593                             sizeof(adapter->fw_version),
2594                             "%d.%d, 0x%08x",
2595                             fw.eep_major, fw.eep_minor, fw.etrack_id);
2596                 } else {
2597                 snprintf(adapter->fw_version,
2598                     sizeof(adapter->fw_version),
2599                     "%d.%d.%d",
2600                     fw.eep_major, fw.eep_minor, fw.eep_build);
2601                 }
2602                 break;
2603         }
2604 }
2605
2606 /**
2607  * igb_init_mas - init Media Autosense feature if enabled in the NVM
2608  *
2609  * @adapter: adapter struct
2610  **/
2611 static void igb_init_mas(struct igb_adapter *adapter)
2612 {
2613         struct e1000_hw *hw = &adapter->hw;
2614         u16 eeprom_data;
2615
2616         hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2617         switch (hw->bus.func) {
2618         case E1000_FUNC_0:
2619                 if (eeprom_data & IGB_MAS_ENABLE_0) {
2620                         adapter->flags |= IGB_FLAG_MAS_ENABLE;
2621                         netdev_info(adapter->netdev,
2622                                 "MAS: Enabling Media Autosense for port %d\n",
2623                                 hw->bus.func);
2624                 }
2625                 break;
2626         case E1000_FUNC_1:
2627                 if (eeprom_data & IGB_MAS_ENABLE_1) {
2628                         adapter->flags |= IGB_FLAG_MAS_ENABLE;
2629                         netdev_info(adapter->netdev,
2630                                 "MAS: Enabling Media Autosense for port %d\n",
2631                                 hw->bus.func);
2632                 }
2633                 break;
2634         case E1000_FUNC_2:
2635                 if (eeprom_data & IGB_MAS_ENABLE_2) {
2636                         adapter->flags |= IGB_FLAG_MAS_ENABLE;
2637                         netdev_info(adapter->netdev,
2638                                 "MAS: Enabling Media Autosense for port %d\n",
2639                                 hw->bus.func);
2640                 }
2641                 break;
2642         case E1000_FUNC_3:
2643                 if (eeprom_data & IGB_MAS_ENABLE_3) {
2644                         adapter->flags |= IGB_FLAG_MAS_ENABLE;
2645                         netdev_info(adapter->netdev,
2646                                 "MAS: Enabling Media Autosense for port %d\n",
2647                                 hw->bus.func);
2648                 }
2649                 break;
2650         default:
2651                 /* Shouldn't get here */
2652                 netdev_err(adapter->netdev,
2653                         "MAS: Invalid port configuration, returning\n");
2654                 break;
2655         }
2656 }
2657
2658 /**
2659  *  igb_init_i2c - Init I2C interface
2660  *  @adapter: pointer to adapter structure
2661  **/
2662 static s32 igb_init_i2c(struct igb_adapter *adapter)
2663 {
2664         s32 status = 0;
2665
2666         /* I2C interface supported on i350 devices */
2667         if (adapter->hw.mac.type != e1000_i350)
2668                 return 0;
2669
2670         /* Initialize the i2c bus which is controlled by the registers.
2671          * This bus will use the i2c_algo_bit structue that implements
2672          * the protocol through toggling of the 4 bits in the register.
2673          */
2674         adapter->i2c_adap.owner = THIS_MODULE;
2675         adapter->i2c_algo = igb_i2c_algo;
2676         adapter->i2c_algo.data = adapter;
2677         adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2678         adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2679         strlcpy(adapter->i2c_adap.name, "igb BB",
2680                 sizeof(adapter->i2c_adap.name));
2681         status = i2c_bit_add_bus(&adapter->i2c_adap);
2682         return status;
2683 }
2684
2685 /**
2686  *  igb_probe - Device Initialization Routine
2687  *  @pdev: PCI device information struct
2688  *  @ent: entry in igb_pci_tbl
2689  *
2690  *  Returns 0 on success, negative on failure
2691  *
2692  *  igb_probe initializes an adapter identified by a pci_dev structure.
2693  *  The OS initialization, configuring of the adapter private structure,
2694  *  and a hardware reset occur.
2695  **/
2696 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2697 {
2698         struct net_device *netdev;
2699         struct igb_adapter *adapter;
2700         struct e1000_hw *hw;
2701         u16 eeprom_data = 0;
2702         s32 ret_val;
2703         static int global_quad_port_a; /* global quad port a indication */
2704         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2705         int err, pci_using_dac;
2706         u8 part_str[E1000_PBANUM_LENGTH];
2707
2708         /* Catch broken hardware that put the wrong VF device ID in
2709          * the PCIe SR-IOV capability.
2710          */
2711         if (pdev->is_virtfn) {
2712                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
2713                         pci_name(pdev), pdev->vendor, pdev->device);
2714                 return -EINVAL;
2715         }
2716
2717         err = pci_enable_device_mem(pdev);
2718         if (err)
2719                 return err;
2720
2721         pci_using_dac = 0;
2722         err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2723         if (!err) {
2724                 pci_using_dac = 1;
2725         } else {
2726                 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2727                 if (err) {
2728                         dev_err(&pdev->dev,
2729                                 "No usable DMA configuration, aborting\n");
2730                         goto err_dma;
2731                 }
2732         }
2733
2734         err = pci_request_mem_regions(pdev, igb_driver_name);
2735         if (err)
2736                 goto err_pci_reg;
2737
2738         pci_enable_pcie_error_reporting(pdev);
2739
2740         pci_set_master(pdev);
2741         pci_save_state(pdev);
2742
2743         err = -ENOMEM;
2744         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2745                                    IGB_MAX_TX_QUEUES);
2746         if (!netdev)
2747                 goto err_alloc_etherdev;
2748
2749         SET_NETDEV_DEV(netdev, &pdev->dev);
2750
2751         pci_set_drvdata(pdev, netdev);
2752         adapter = netdev_priv(netdev);
2753         adapter->netdev = netdev;
2754         adapter->pdev = pdev;
2755         hw = &adapter->hw;
2756         hw->back = adapter;
2757         adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2758
2759         err = -EIO;
2760         adapter->io_addr = pci_iomap(pdev, 0, 0);
2761         if (!adapter->io_addr)
2762                 goto err_ioremap;
2763         /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
2764         hw->hw_addr = adapter->io_addr;
2765
2766         netdev->netdev_ops = &igb_netdev_ops;
2767         igb_set_ethtool_ops(netdev);
2768         netdev->watchdog_timeo = 5 * HZ;
2769
2770         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2771
2772         netdev->mem_start = pci_resource_start(pdev, 0);
2773         netdev->mem_end = pci_resource_end(pdev, 0);
2774
2775         /* PCI config space info */
2776         hw->vendor_id = pdev->vendor;
2777         hw->device_id = pdev->device;
2778         hw->revision_id = pdev->revision;
2779         hw->subsystem_vendor_id = pdev->subsystem_vendor;
2780         hw->subsystem_device_id = pdev->subsystem_device;
2781
2782         /* Copy the default MAC, PHY and NVM function pointers */
2783         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2784         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2785         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2786         /* Initialize skew-specific constants */
2787         err = ei->get_invariants(hw);
2788         if (err)
2789                 goto err_sw_init;
2790
2791         /* setup the private structure */
2792         err = igb_sw_init(adapter);
2793         if (err)
2794                 goto err_sw_init;
2795
2796         igb_get_bus_info_pcie(hw);
2797
2798         hw->phy.autoneg_wait_to_complete = false;
2799
2800         /* Copper options */
2801         if (hw->phy.media_type == e1000_media_type_copper) {
2802                 hw->phy.mdix = AUTO_ALL_MODES;
2803                 hw->phy.disable_polarity_correction = false;
2804                 hw->phy.ms_type = e1000_ms_hw_default;
2805         }
2806
2807         if (igb_check_reset_block(hw))
2808                 dev_info(&pdev->dev,
2809                         "PHY reset is blocked due to SOL/IDER session.\n");
2810
2811         /* features is initialized to 0 in allocation, it might have bits
2812          * set by igb_sw_init so we should use an or instead of an
2813          * assignment.
2814          */
2815         netdev->features |= NETIF_F_SG |
2816                             NETIF_F_TSO |
2817                             NETIF_F_TSO6 |
2818                             NETIF_F_RXHASH |
2819                             NETIF_F_RXCSUM |
2820                             NETIF_F_HW_CSUM;
2821
2822         if (hw->mac.type >= e1000_82576)
2823                 netdev->features |= NETIF_F_SCTP_CRC;
2824
2825 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
2826                                   NETIF_F_GSO_GRE_CSUM | \
2827                                   NETIF_F_GSO_IPXIP4 | \
2828                                   NETIF_F_GSO_IPXIP6 | \
2829                                   NETIF_F_GSO_UDP_TUNNEL | \
2830                                   NETIF_F_GSO_UDP_TUNNEL_CSUM)
2831
2832         netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES;
2833         netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES;
2834
2835         /* copy netdev features into list of user selectable features */
2836         netdev->hw_features |= netdev->features |
2837                                NETIF_F_HW_VLAN_CTAG_RX |
2838                                NETIF_F_HW_VLAN_CTAG_TX |
2839                                NETIF_F_RXALL;
2840
2841         if (hw->mac.type >= e1000_i350)
2842                 netdev->hw_features |= NETIF_F_NTUPLE;
2843
2844         if (pci_using_dac)
2845                 netdev->features |= NETIF_F_HIGHDMA;
2846
2847         netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
2848         netdev->mpls_features |= NETIF_F_HW_CSUM;
2849         netdev->hw_enc_features |= netdev->vlan_features;
2850
2851         /* set this bit last since it cannot be part of vlan_features */
2852         netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
2853                             NETIF_F_HW_VLAN_CTAG_RX |
2854                             NETIF_F_HW_VLAN_CTAG_TX;
2855
2856         netdev->priv_flags |= IFF_SUPP_NOFCS;
2857
2858         netdev->priv_flags |= IFF_UNICAST_FLT;
2859
2860         /* MTU range: 68 - 9216 */
2861         netdev->min_mtu = ETH_MIN_MTU;
2862         netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE;
2863
2864         adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2865
2866         /* before reading the NVM, reset the controller to put the device in a
2867          * known good starting state
2868          */
2869         hw->mac.ops.reset_hw(hw);
2870
2871         /* make sure the NVM is good , i211/i210 parts can have special NVM
2872          * that doesn't contain a checksum
2873          */
2874         switch (hw->mac.type) {
2875         case e1000_i210:
2876         case e1000_i211:
2877                 if (igb_get_flash_presence_i210(hw)) {
2878                         if (hw->nvm.ops.validate(hw) < 0) {
2879                                 dev_err(&pdev->dev,
2880                                         "The NVM Checksum Is Not Valid\n");
2881                                 err = -EIO;
2882                                 goto err_eeprom;
2883                         }
2884                 }
2885                 break;
2886         default:
2887                 if (hw->nvm.ops.validate(hw) < 0) {
2888                         dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2889                         err = -EIO;
2890                         goto err_eeprom;
2891                 }
2892                 break;
2893         }
2894
2895         if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {
2896                 /* copy the MAC address out of the NVM */
2897                 if (hw->mac.ops.read_mac_addr(hw))
2898                         dev_err(&pdev->dev, "NVM Read Error\n");
2899         }
2900
2901         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2902
2903         if (!is_valid_ether_addr(netdev->dev_addr)) {
2904                 dev_err(&pdev->dev, "Invalid MAC Address\n");
2905                 err = -EIO;
2906                 goto err_eeprom;
2907         }
2908
2909         igb_set_default_mac_filter(adapter);
2910
2911         /* get firmware version for ethtool -i */
2912         igb_set_fw_version(adapter);
2913
2914         /* configure RXPBSIZE and TXPBSIZE */
2915         if (hw->mac.type == e1000_i210) {
2916                 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2917                 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2918         }
2919
2920         timer_setup(&adapter->watchdog_timer, igb_watchdog, 0);
2921         timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0);
2922
2923         INIT_WORK(&adapter->reset_task, igb_reset_task);
2924         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2925
2926         /* Initialize link properties that are user-changeable */
2927         adapter->fc_autoneg = true;
2928         hw->mac.autoneg = true;
2929         hw->phy.autoneg_advertised = 0x2f;
2930
2931         hw->fc.requested_mode = e1000_fc_default;
2932         hw->fc.current_mode = e1000_fc_default;
2933
2934         igb_validate_mdi_setting(hw);
2935
2936         /* By default, support wake on port A */
2937         if (hw->bus.func == 0)
2938                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2939
2940         /* Check the NVM for wake support on non-port A ports */
2941         if (hw->mac.type >= e1000_82580)
2942                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2943                                  NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2944                                  &eeprom_data);
2945         else if (hw->bus.func == 1)
2946                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2947
2948         if (eeprom_data & IGB_EEPROM_APME)
2949                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2950
2951         /* now that we have the eeprom settings, apply the special cases where
2952          * the eeprom may be wrong or the board simply won't support wake on
2953          * lan on a particular port
2954          */
2955         switch (pdev->device) {
2956         case E1000_DEV_ID_82575GB_QUAD_COPPER:
2957                 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2958                 break;
2959         case E1000_DEV_ID_82575EB_FIBER_SERDES:
2960         case E1000_DEV_ID_82576_FIBER:
2961         case E1000_DEV_ID_82576_SERDES:
2962                 /* Wake events only supported on port A for dual fiber
2963                  * regardless of eeprom setting
2964                  */
2965                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2966                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2967                 break;
2968         case E1000_DEV_ID_82576_QUAD_COPPER:
2969         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2970                 /* if quad port adapter, disable WoL on all but port A */
2971                 if (global_quad_port_a != 0)
2972                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2973                 else
2974                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2975                 /* Reset for multiple quad port adapters */
2976                 if (++global_quad_port_a == 4)
2977                         global_quad_port_a = 0;
2978                 break;
2979         default:
2980                 /* If the device can't wake, don't set software support */
2981                 if (!device_can_wakeup(&adapter->pdev->dev))
2982                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2983         }
2984
2985         /* initialize the wol settings based on the eeprom settings */
2986         if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2987                 adapter->wol |= E1000_WUFC_MAG;
2988
2989         /* Some vendors want WoL disabled by default, but still supported */
2990         if ((hw->mac.type == e1000_i350) &&
2991             (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2992                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2993                 adapter->wol = 0;
2994         }
2995
2996         /* Some vendors want the ability to Use the EEPROM setting as
2997          * enable/disable only, and not for capability
2998          */
2999         if (((hw->mac.type == e1000_i350) ||
3000              (hw->mac.type == e1000_i354)) &&
3001             (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) {
3002                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3003                 adapter->wol = 0;
3004         }
3005         if (hw->mac.type == e1000_i350) {
3006                 if (((pdev->subsystem_device == 0x5001) ||
3007                      (pdev->subsystem_device == 0x5002)) &&
3008                                 (hw->bus.func == 0)) {
3009                         adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3010                         adapter->wol = 0;
3011                 }
3012                 if (pdev->subsystem_device == 0x1F52)
3013                         adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3014         }
3015
3016         device_set_wakeup_enable(&adapter->pdev->dev,
3017                                  adapter->flags & IGB_FLAG_WOL_SUPPORTED);
3018
3019         /* reset the hardware with the new settings */
3020         igb_reset(adapter);
3021
3022         /* Init the I2C interface */
3023         err = igb_init_i2c(adapter);
3024         if (err) {
3025                 dev_err(&pdev->dev, "failed to init i2c interface\n");
3026                 goto err_eeprom;
3027         }
3028
3029         /* let the f/w know that the h/w is now under the control of the
3030          * driver.
3031          */
3032         igb_get_hw_control(adapter);
3033
3034         strcpy(netdev->name, "eth%d");
3035         err = register_netdev(netdev);
3036         if (err)
3037                 goto err_register;
3038
3039         /* carrier off reporting is important to ethtool even BEFORE open */
3040         netif_carrier_off(netdev);
3041
3042 #ifdef CONFIG_IGB_DCA
3043         if (dca_add_requester(&pdev->dev) == 0) {
3044                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
3045                 dev_info(&pdev->dev, "DCA enabled\n");
3046                 igb_setup_dca(adapter);
3047         }
3048
3049 #endif
3050 #ifdef CONFIG_IGB_HWMON
3051         /* Initialize the thermal sensor on i350 devices. */
3052         if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
3053                 u16 ets_word;
3054
3055                 /* Read the NVM to determine if this i350 device supports an
3056                  * external thermal sensor.
3057                  */
3058                 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
3059                 if (ets_word != 0x0000 && ets_word != 0xFFFF)
3060                         adapter->ets = true;
3061                 else
3062                         adapter->ets = false;
3063                 if (igb_sysfs_init(adapter))
3064                         dev_err(&pdev->dev,
3065                                 "failed to allocate sysfs resources\n");
3066         } else {
3067                 adapter->ets = false;
3068         }
3069 #endif
3070         /* Check if Media Autosense is enabled */
3071         adapter->ei = *ei;
3072         if (hw->dev_spec._82575.mas_capable)
3073                 igb_init_mas(adapter);
3074
3075         /* do hw tstamp init after resetting */
3076         igb_ptp_init(adapter);
3077
3078         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
3079         /* print bus type/speed/width info, not applicable to i354 */
3080         if (hw->mac.type != e1000_i354) {
3081                 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
3082                          netdev->name,
3083                          ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
3084                           (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
3085                            "unknown"),
3086                          ((hw->bus.width == e1000_bus_width_pcie_x4) ?
3087                           "Width x4" :
3088                           (hw->bus.width == e1000_bus_width_pcie_x2) ?
3089                           "Width x2" :
3090                           (hw->bus.width == e1000_bus_width_pcie_x1) ?
3091                           "Width x1" : "unknown"), netdev->dev_addr);
3092         }
3093
3094         if ((hw->mac.type >= e1000_i210 ||
3095              igb_get_flash_presence_i210(hw))) {
3096                 ret_val = igb_read_part_string(hw, part_str,
3097                                                E1000_PBANUM_LENGTH);
3098         } else {
3099                 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
3100         }
3101
3102         if (ret_val)
3103                 strcpy(part_str, "Unknown");
3104         dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
3105         dev_info(&pdev->dev,
3106                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
3107                 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
3108                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
3109                 adapter->num_rx_queues, adapter->num_tx_queues);
3110         if (hw->phy.media_type == e1000_media_type_copper) {
3111                 switch (hw->mac.type) {
3112                 case e1000_i350:
3113                 case e1000_i210:
3114                 case e1000_i211:
3115                         /* Enable EEE for internal copper PHY devices */
3116                         err = igb_set_eee_i350(hw, true, true);
3117                         if ((!err) &&
3118                             (!hw->dev_spec._82575.eee_disable)) {
3119                                 adapter->eee_advert =
3120                                         MDIO_EEE_100TX | MDIO_EEE_1000T;
3121                                 adapter->flags |= IGB_FLAG_EEE;
3122                         }
3123                         break;
3124                 case e1000_i354:
3125                         if ((rd32(E1000_CTRL_EXT) &
3126                             E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3127                                 err = igb_set_eee_i354(hw, true, true);
3128                                 if ((!err) &&
3129                                         (!hw->dev_spec._82575.eee_disable)) {
3130                                         adapter->eee_advert =
3131                                            MDIO_EEE_100TX | MDIO_EEE_1000T;
3132                                         adapter->flags |= IGB_FLAG_EEE;
3133                                 }
3134                         }
3135                         break;
3136                 default:
3137                         break;
3138                 }
3139         }
3140         pm_runtime_put_noidle(&pdev->dev);
3141         return 0;
3142
3143 err_register:
3144         igb_release_hw_control(adapter);
3145         memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
3146 err_eeprom:
3147         if (!igb_check_reset_block(hw))
3148                 igb_reset_phy(hw);
3149
3150         if (hw->flash_address)
3151                 iounmap(hw->flash_address);
3152 err_sw_init:
3153         kfree(adapter->mac_table);
3154         kfree(adapter->shadow_vfta);
3155         igb_clear_interrupt_scheme(adapter);
3156 #ifdef CONFIG_PCI_IOV
3157         igb_disable_sriov(pdev);
3158 #endif
3159         pci_iounmap(pdev, adapter->io_addr);
3160 err_ioremap:
3161         free_netdev(netdev);
3162 err_alloc_etherdev:
3163         pci_release_mem_regions(pdev);
3164 err_pci_reg:
3165 err_dma:
3166         pci_disable_device(pdev);
3167         return err;
3168 }
3169
3170 #ifdef CONFIG_PCI_IOV
3171 static int igb_disable_sriov(struct pci_dev *pdev)
3172 {
3173         struct net_device *netdev = pci_get_drvdata(pdev);
3174         struct igb_adapter *adapter = netdev_priv(netdev);
3175         struct e1000_hw *hw = &adapter->hw;
3176
3177         /* reclaim resources allocated to VFs */
3178         if (adapter->vf_data) {
3179                 /* disable iov and allow time for transactions to clear */
3180                 if (pci_vfs_assigned(pdev)) {
3181                         dev_warn(&pdev->dev,
3182                                  "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
3183                         return -EPERM;
3184                 } else {
3185                         pci_disable_sriov(pdev);
3186                         msleep(500);
3187                 }
3188
3189                 kfree(adapter->vf_mac_list);
3190                 adapter->vf_mac_list = NULL;
3191                 kfree(adapter->vf_data);
3192                 adapter->vf_data = NULL;
3193                 adapter->vfs_allocated_count = 0;
3194                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
3195                 wrfl();
3196                 msleep(100);
3197                 dev_info(&pdev->dev, "IOV Disabled\n");
3198
3199                 /* Re-enable DMA Coalescing flag since IOV is turned off */
3200                 adapter->flags |= IGB_FLAG_DMAC;
3201         }
3202
3203         return 0;
3204 }
3205
3206 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
3207 {
3208         struct net_device *netdev = pci_get_drvdata(pdev);
3209         struct igb_adapter *adapter = netdev_priv(netdev);
3210         int old_vfs = pci_num_vf(pdev);
3211         struct vf_mac_filter *mac_list;
3212         int err = 0;
3213         int num_vf_mac_filters, i;
3214
3215         if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
3216                 err = -EPERM;
3217                 goto out;
3218         }
3219         if (!num_vfs)
3220                 goto out;
3221
3222         if (old_vfs) {
3223                 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
3224                          old_vfs, max_vfs);
3225                 adapter->vfs_allocated_count = old_vfs;
3226         } else
3227                 adapter->vfs_allocated_count = num_vfs;
3228
3229         adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
3230                                 sizeof(struct vf_data_storage), GFP_KERNEL);
3231
3232         /* if allocation failed then we do not support SR-IOV */
3233         if (!adapter->vf_data) {
3234                 adapter->vfs_allocated_count = 0;
3235                 err = -ENOMEM;
3236                 goto out;
3237         }
3238
3239         /* Due to the limited number of RAR entries calculate potential
3240          * number of MAC filters available for the VFs. Reserve entries
3241          * for PF default MAC, PF MAC filters and at least one RAR entry
3242          * for each VF for VF MAC.
3243          */
3244         num_vf_mac_filters = adapter->hw.mac.rar_entry_count -
3245                              (1 + IGB_PF_MAC_FILTERS_RESERVED +
3246                               adapter->vfs_allocated_count);
3247
3248         adapter->vf_mac_list = kcalloc(num_vf_mac_filters,
3249                                        sizeof(struct vf_mac_filter),
3250                                        GFP_KERNEL);
3251
3252         mac_list = adapter->vf_mac_list;
3253         INIT_LIST_HEAD(&adapter->vf_macs.l);
3254
3255         if (adapter->vf_mac_list) {
3256                 /* Initialize list of VF MAC filters */
3257                 for (i = 0; i < num_vf_mac_filters; i++) {
3258                         mac_list->vf = -1;
3259                         mac_list->free = true;
3260                         list_add(&mac_list->l, &adapter->vf_macs.l);
3261                         mac_list++;
3262                 }
3263         } else {
3264                 /* If we could not allocate memory for the VF MAC filters
3265                  * we can continue without this feature but warn user.
3266                  */
3267                 dev_err(&pdev->dev,
3268                         "Unable to allocate memory for VF MAC filter list\n");
3269         }
3270
3271         /* only call pci_enable_sriov() if no VFs are allocated already */
3272         if (!old_vfs) {
3273                 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
3274                 if (err)
3275                         goto err_out;
3276         }
3277         dev_info(&pdev->dev, "%d VFs allocated\n",
3278                  adapter->vfs_allocated_count);
3279         for (i = 0; i < adapter->vfs_allocated_count; i++)
3280                 igb_vf_configure(adapter, i);
3281
3282         /* DMA Coalescing is not supported in IOV mode. */
3283         adapter->flags &= ~IGB_FLAG_DMAC;
3284         goto out;
3285
3286 err_out:
3287         kfree(adapter->vf_mac_list);
3288         adapter->vf_mac_list = NULL;
3289         kfree(adapter->vf_data);
3290         adapter->vf_data = NULL;
3291         adapter->vfs_allocated_count = 0;
3292 out:
3293         return err;
3294 }
3295
3296 #endif
3297 /**
3298  *  igb_remove_i2c - Cleanup  I2C interface
3299  *  @adapter: pointer to adapter structure
3300  **/
3301 static void igb_remove_i2c(struct igb_adapter *adapter)
3302 {
3303         /* free the adapter bus structure */
3304         i2c_del_adapter(&adapter->i2c_adap);
3305 }
3306
3307 /**
3308  *  igb_remove - Device Removal Routine
3309  *  @pdev: PCI device information struct
3310  *
3311  *  igb_remove is called by the PCI subsystem to alert the driver
3312  *  that it should release a PCI device.  The could be caused by a
3313  *  Hot-Plug event, or because the driver is going to be removed from
3314  *  memory.
3315  **/
3316 static void igb_remove(struct pci_dev *pdev)
3317 {
3318         struct net_device *netdev = pci_get_drvdata(pdev);
3319         struct igb_adapter *adapter = netdev_priv(netdev);
3320         struct e1000_hw *hw = &adapter->hw;
3321
3322         pm_runtime_get_noresume(&pdev->dev);
3323 #ifdef CONFIG_IGB_HWMON
3324         igb_sysfs_exit(adapter);
3325 #endif
3326         igb_remove_i2c(adapter);
3327         igb_ptp_stop(adapter);
3328         /* The watchdog timer may be rescheduled, so explicitly
3329          * disable watchdog from being rescheduled.
3330          */
3331         set_bit(__IGB_DOWN, &adapter->state);
3332         del_timer_sync(&adapter->watchdog_timer);
3333         del_timer_sync(&adapter->phy_info_timer);
3334
3335         cancel_work_sync(&adapter->reset_task);
3336         cancel_work_sync(&adapter->watchdog_task);
3337
3338 #ifdef CONFIG_IGB_DCA
3339         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3340                 dev_info(&pdev->dev, "DCA disabled\n");
3341                 dca_remove_requester(&pdev->dev);
3342                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3343                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3344         }
3345 #endif
3346
3347         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
3348          * would have already happened in close and is redundant.
3349          */
3350         igb_release_hw_control(adapter);
3351
3352 #ifdef CONFIG_PCI_IOV
3353         igb_disable_sriov(pdev);
3354 #endif
3355
3356         unregister_netdev(netdev);
3357
3358         igb_clear_interrupt_scheme(adapter);
3359
3360         pci_iounmap(pdev, adapter->io_addr);
3361         if (hw->flash_address)
3362                 iounmap(hw->flash_address);
3363         pci_release_mem_regions(pdev);
3364
3365         kfree(adapter->mac_table);
3366         kfree(adapter->shadow_vfta);
3367         free_netdev(netdev);
3368
3369         pci_disable_pcie_error_reporting(pdev);
3370
3371         pci_disable_device(pdev);
3372 }
3373
3374 /**
3375  *  igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
3376  *  @adapter: board private structure to initialize
3377  *
3378  *  This function initializes the vf specific data storage and then attempts to
3379  *  allocate the VFs.  The reason for ordering it this way is because it is much
3380  *  mor expensive time wise to disable SR-IOV than it is to allocate and free
3381  *  the memory for the VFs.
3382  **/
3383 static void igb_probe_vfs(struct igb_adapter *adapter)
3384 {
3385 #ifdef CONFIG_PCI_IOV
3386         struct pci_dev *pdev = adapter->pdev;
3387         struct e1000_hw *hw = &adapter->hw;
3388
3389         /* Virtualization features not supported on i210 family. */
3390         if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
3391                 return;
3392
3393         /* Of the below we really only want the effect of getting
3394          * IGB_FLAG_HAS_MSIX set (if available), without which
3395          * igb_enable_sriov() has no effect.
3396          */
3397         igb_set_interrupt_capability(adapter, true);
3398         igb_reset_interrupt_capability(adapter);
3399
3400         pci_sriov_set_totalvfs(pdev, 7);
3401         igb_enable_sriov(pdev, max_vfs);
3402
3403 #endif /* CONFIG_PCI_IOV */
3404 }
3405
3406 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter)
3407 {
3408         struct e1000_hw *hw = &adapter->hw;
3409         unsigned int max_rss_queues;
3410
3411         /* Determine the maximum number of RSS queues supported. */
3412         switch (hw->mac.type) {
3413         case e1000_i211:
3414                 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
3415                 break;
3416         case e1000_82575:
3417         case e1000_i210:
3418                 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
3419                 break;
3420         case e1000_i350:
3421                 /* I350 cannot do RSS and SR-IOV at the same time */
3422                 if (!!adapter->vfs_allocated_count) {
3423                         max_rss_queues = 1;
3424                         break;
3425                 }
3426                 /* fall through */
3427         case e1000_82576:
3428                 if (!!adapter->vfs_allocated_count) {
3429                         max_rss_queues = 2;
3430                         break;
3431                 }
3432                 /* fall through */
3433         case e1000_82580:
3434         case e1000_i354:
3435         default:
3436                 max_rss_queues = IGB_MAX_RX_QUEUES;
3437                 break;
3438         }
3439
3440         return max_rss_queues;
3441 }
3442
3443 static void igb_init_queue_configuration(struct igb_adapter *adapter)
3444 {
3445         u32 max_rss_queues;
3446
3447         max_rss_queues = igb_get_max_rss_queues(adapter);
3448         adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
3449
3450         igb_set_flag_queue_pairs(adapter, max_rss_queues);
3451 }
3452
3453 void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
3454                               const u32 max_rss_queues)
3455 {
3456         struct e1000_hw *hw = &adapter->hw;
3457
3458         /* Determine if we need to pair queues. */
3459         switch (hw->mac.type) {
3460         case e1000_82575:
3461         case e1000_i211:
3462                 /* Device supports enough interrupts without queue pairing. */
3463                 break;
3464         case e1000_82576:
3465         case e1000_82580:
3466         case e1000_i350:
3467         case e1000_i354:
3468         case e1000_i210:
3469         default:
3470                 /* If rss_queues > half of max_rss_queues, pair the queues in
3471                  * order to conserve interrupts due to limited supply.
3472                  */
3473                 if (adapter->rss_queues > (max_rss_queues / 2))
3474                         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
3475                 else
3476                         adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
3477                 break;
3478         }
3479 }
3480
3481 /**
3482  *  igb_sw_init - Initialize general software structures (struct igb_adapter)
3483  *  @adapter: board private structure to initialize
3484  *
3485  *  igb_sw_init initializes the Adapter private data structure.
3486  *  Fields are initialized based on PCI device information and
3487  *  OS network device settings (MTU size).
3488  **/
3489 static int igb_sw_init(struct igb_adapter *adapter)
3490 {
3491         struct e1000_hw *hw = &adapter->hw;
3492         struct net_device *netdev = adapter->netdev;
3493         struct pci_dev *pdev = adapter->pdev;
3494
3495         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
3496
3497         /* set default ring sizes */
3498         adapter->tx_ring_count = IGB_DEFAULT_TXD;
3499         adapter->rx_ring_count = IGB_DEFAULT_RXD;
3500
3501         /* set default ITR values */
3502         adapter->rx_itr_setting = IGB_DEFAULT_ITR;
3503         adapter->tx_itr_setting = IGB_DEFAULT_ITR;
3504
3505         /* set default work limits */
3506         adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
3507
3508         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
3509                                   VLAN_HLEN;
3510         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
3511
3512         spin_lock_init(&adapter->nfc_lock);
3513         spin_lock_init(&adapter->stats64_lock);
3514 #ifdef CONFIG_PCI_IOV
3515         switch (hw->mac.type) {
3516         case e1000_82576:
3517         case e1000_i350:
3518                 if (max_vfs > 7) {
3519                         dev_warn(&pdev->dev,
3520                                  "Maximum of 7 VFs per PF, using max\n");
3521                         max_vfs = adapter->vfs_allocated_count = 7;
3522                 } else
3523                         adapter->vfs_allocated_count = max_vfs;
3524                 if (adapter->vfs_allocated_count)
3525                         dev_warn(&pdev->dev,
3526                                  "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
3527                 break;
3528         default:
3529                 break;
3530         }
3531 #endif /* CONFIG_PCI_IOV */
3532
3533         /* Assume MSI-X interrupts, will be checked during IRQ allocation */
3534         adapter->flags |= IGB_FLAG_HAS_MSIX;
3535
3536         adapter->mac_table = kzalloc(sizeof(struct igb_mac_addr) *
3537                                      hw->mac.rar_entry_count, GFP_ATOMIC);
3538         if (!adapter->mac_table)
3539                 return -ENOMEM;
3540
3541         igb_probe_vfs(adapter);
3542
3543         igb_init_queue_configuration(adapter);
3544
3545         /* Setup and initialize a copy of the hw vlan table array */
3546         adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
3547                                        GFP_ATOMIC);
3548         if (!adapter->shadow_vfta)
3549                 return -ENOMEM;
3550
3551         /* This call may decrease the number of queues */
3552         if (igb_init_interrupt_scheme(adapter, true)) {
3553                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3554                 return -ENOMEM;
3555         }
3556
3557         /* Explicitly disable IRQ since the NIC can be in any state. */
3558         igb_irq_disable(adapter);
3559
3560         if (hw->mac.type >= e1000_i350)
3561                 adapter->flags &= ~IGB_FLAG_DMAC;
3562
3563         set_bit(__IGB_DOWN, &adapter->state);
3564         return 0;
3565 }
3566
3567 /**
3568  *  igb_open - Called when a network interface is made active
3569  *  @netdev: network interface device structure
3570  *
3571  *  Returns 0 on success, negative value on failure
3572  *
3573  *  The open entry point is called when a network interface is made
3574  *  active by the system (IFF_UP).  At this point all resources needed
3575  *  for transmit and receive operations are allocated, the interrupt
3576  *  handler is registered with the OS, the watchdog timer is started,
3577  *  and the stack is notified that the interface is ready.
3578  **/
3579 static int __igb_open(struct net_device *netdev, bool resuming)
3580 {
3581         struct igb_adapter *adapter = netdev_priv(netdev);
3582         struct e1000_hw *hw = &adapter->hw;
3583         struct pci_dev *pdev = adapter->pdev;
3584         int err;
3585         int i;
3586
3587         /* disallow open during test */
3588         if (test_bit(__IGB_TESTING, &adapter->state)) {
3589                 WARN_ON(resuming);
3590                 return -EBUSY;
3591         }
3592
3593         if (!resuming)
3594                 pm_runtime_get_sync(&pdev->dev);
3595
3596         netif_carrier_off(netdev);
3597
3598         /* allocate transmit descriptors */
3599         err = igb_setup_all_tx_resources(adapter);
3600         if (err)
3601                 goto err_setup_tx;
3602
3603         /* allocate receive descriptors */
3604         err = igb_setup_all_rx_resources(adapter);
3605         if (err)
3606                 goto err_setup_rx;
3607
3608         igb_power_up_link(adapter);
3609
3610         /* before we allocate an interrupt, we must be ready to handle it.
3611          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3612          * as soon as we call pci_request_irq, so we have to setup our
3613          * clean_rx handler before we do so.
3614          */
3615         igb_configure(adapter);
3616
3617         err = igb_request_irq(adapter);
3618         if (err)
3619                 goto err_req_irq;
3620
3621         /* Notify the stack of the actual queue counts. */
3622         err = netif_set_real_num_tx_queues(adapter->netdev,
3623                                            adapter->num_tx_queues);
3624         if (err)
3625                 goto err_set_queues;
3626
3627         err = netif_set_real_num_rx_queues(adapter->netdev,
3628                                            adapter->num_rx_queues);
3629         if (err)
3630                 goto err_set_queues;
3631
3632         /* From here on the code is the same as igb_up() */
3633         clear_bit(__IGB_DOWN, &adapter->state);
3634
3635         for (i = 0; i < adapter->num_q_vectors; i++)
3636                 napi_enable(&(adapter->q_vector[i]->napi));
3637
3638         /* Clear any pending interrupts. */
3639         rd32(E1000_ICR);
3640
3641         igb_irq_enable(adapter);
3642
3643         /* notify VFs that reset has been completed */
3644         if (adapter->vfs_allocated_count) {
3645                 u32 reg_data = rd32(E1000_CTRL_EXT);
3646
3647                 reg_data |= E1000_CTRL_EXT_PFRSTD;
3648                 wr32(E1000_CTRL_EXT, reg_data);
3649         }
3650
3651         netif_tx_start_all_queues(netdev);
3652
3653         if (!resuming)
3654                 pm_runtime_put(&pdev->dev);
3655
3656         /* start the watchdog. */
3657         hw->mac.get_link_status = 1;
3658         schedule_work(&adapter->watchdog_task);
3659
3660         return 0;
3661
3662 err_set_queues:
3663         igb_free_irq(adapter);
3664 err_req_irq:
3665         igb_release_hw_control(adapter);
3666         igb_power_down_link(adapter);
3667         igb_free_all_rx_resources(adapter);
3668 err_setup_rx:
3669         igb_free_all_tx_resources(adapter);
3670 err_setup_tx:
3671         igb_reset(adapter);
3672         if (!resuming)
3673                 pm_runtime_put(&pdev->dev);
3674
3675         return err;
3676 }
3677
3678 int igb_open(struct net_device *netdev)
3679 {
3680         return __igb_open(netdev, false);
3681 }
3682
3683 /**
3684  *  igb_close - Disables a network interface
3685  *  @netdev: network interface device structure
3686  *
3687  *  Returns 0, this is not allowed to fail
3688  *
3689  *  The close entry point is called when an interface is de-activated
3690  *  by the OS.  The hardware is still under the driver's control, but
3691  *  needs to be disabled.  A global MAC reset is issued to stop the
3692  *  hardware, and all transmit and receive resources are freed.
3693  **/
3694 static int __igb_close(struct net_device *netdev, bool suspending)
3695 {
3696         struct igb_adapter *adapter = netdev_priv(netdev);
3697         struct pci_dev *pdev = adapter->pdev;
3698
3699         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3700
3701         if (!suspending)
3702                 pm_runtime_get_sync(&pdev->dev);
3703
3704         igb_down(adapter);
3705         igb_free_irq(adapter);
3706
3707         igb_free_all_tx_resources(adapter);
3708         igb_free_all_rx_resources(adapter);
3709
3710         if (!suspending)
3711                 pm_runtime_put_sync(&pdev->dev);
3712         return 0;
3713 }
3714
3715 int igb_close(struct net_device *netdev)
3716 {
3717         if (netif_device_present(netdev) || netdev->dismantle)
3718                 return __igb_close(netdev, false);
3719         return 0;
3720 }
3721
3722 /**
3723  *  igb_setup_tx_resources - allocate Tx resources (Descriptors)
3724  *  @tx_ring: tx descriptor ring (for a specific queue) to setup
3725  *
3726  *  Return 0 on success, negative on failure
3727  **/
3728 int igb_setup_tx_resources(struct igb_ring *tx_ring)
3729 {
3730         struct device *dev = tx_ring->dev;
3731         int size;
3732
3733         size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3734
3735         tx_ring->tx_buffer_info = vmalloc(size);
3736         if (!tx_ring->tx_buffer_info)
3737                 goto err;
3738
3739         /* round up to nearest 4K */
3740         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
3741         tx_ring->size = ALIGN(tx_ring->size, 4096);
3742
3743         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3744                                            &tx_ring->dma, GFP_KERNEL);
3745         if (!tx_ring->desc)
3746                 goto err;
3747
3748         tx_ring->next_to_use = 0;
3749         tx_ring->next_to_clean = 0;
3750
3751         return 0;
3752
3753 err:
3754         vfree(tx_ring->tx_buffer_info);
3755         tx_ring->tx_buffer_info = NULL;
3756         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
3757         return -ENOMEM;
3758 }
3759
3760 /**
3761  *  igb_setup_all_tx_resources - wrapper to allocate Tx resources
3762  *                               (Descriptors) for all queues
3763  *  @adapter: board private structure
3764  *
3765  *  Return 0 on success, negative on failure
3766  **/
3767 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3768 {
3769         struct pci_dev *pdev = adapter->pdev;
3770         int i, err = 0;
3771
3772         for (i = 0; i < adapter->num_tx_queues; i++) {
3773                 err = igb_setup_tx_resources(adapter->tx_ring[i]);
3774                 if (err) {
3775                         dev_err(&pdev->dev,
3776                                 "Allocation for Tx Queue %u failed\n", i);
3777                         for (i--; i >= 0; i--)
3778                                 igb_free_tx_resources(adapter->tx_ring[i]);
3779                         break;
3780                 }
3781         }
3782
3783         return err;
3784 }
3785
3786 /**
3787  *  igb_setup_tctl - configure the transmit control registers
3788  *  @adapter: Board private structure
3789  **/
3790 void igb_setup_tctl(struct igb_adapter *adapter)
3791 {
3792         struct e1000_hw *hw = &adapter->hw;
3793         u32 tctl;
3794
3795         /* disable queue 0 which is enabled by default on 82575 and 82576 */
3796         wr32(E1000_TXDCTL(0), 0);
3797
3798         /* Program the Transmit Control Register */
3799         tctl = rd32(E1000_TCTL);
3800         tctl &= ~E1000_TCTL_CT;
3801         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3802                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3803
3804         igb_config_collision_dist(hw);
3805
3806         /* Enable transmits */
3807         tctl |= E1000_TCTL_EN;
3808
3809         wr32(E1000_TCTL, tctl);
3810 }
3811
3812 /**
3813  *  igb_configure_tx_ring - Configure transmit ring after Reset
3814  *  @adapter: board private structure
3815  *  @ring: tx ring to configure
3816  *
3817  *  Configure a transmit ring after a reset.
3818  **/
3819 void igb_configure_tx_ring(struct igb_adapter *adapter,
3820                            struct igb_ring *ring)
3821 {
3822         struct e1000_hw *hw = &adapter->hw;
3823         u32 txdctl = 0;
3824         u64 tdba = ring->dma;
3825         int reg_idx = ring->reg_idx;
3826
3827         /* disable the queue */
3828         wr32(E1000_TXDCTL(reg_idx), 0);
3829         wrfl();
3830         mdelay(10);
3831
3832         wr32(E1000_TDLEN(reg_idx),
3833              ring->count * sizeof(union e1000_adv_tx_desc));
3834         wr32(E1000_TDBAL(reg_idx),
3835              tdba & 0x00000000ffffffffULL);
3836         wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3837
3838         ring->tail = adapter->io_addr + E1000_TDT(reg_idx);
3839         wr32(E1000_TDH(reg_idx), 0);
3840         writel(0, ring->tail);
3841
3842         txdctl |= IGB_TX_PTHRESH;
3843         txdctl |= IGB_TX_HTHRESH << 8;
3844         txdctl |= IGB_TX_WTHRESH << 16;
3845
3846         /* reinitialize tx_buffer_info */
3847         memset(ring->tx_buffer_info, 0,
3848                sizeof(struct igb_tx_buffer) * ring->count);
3849
3850         txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3851         wr32(E1000_TXDCTL(reg_idx), txdctl);
3852 }
3853
3854 /**
3855  *  igb_configure_tx - Configure transmit Unit after Reset
3856  *  @adapter: board private structure
3857  *
3858  *  Configure the Tx unit of the MAC after a reset.
3859  **/
3860 static void igb_configure_tx(struct igb_adapter *adapter)
3861 {
3862         int i;
3863
3864         for (i = 0; i < adapter->num_tx_queues; i++)
3865                 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
3866 }
3867
3868 /**
3869  *  igb_setup_rx_resources - allocate Rx resources (Descriptors)
3870  *  @rx_ring: Rx descriptor ring (for a specific queue) to setup
3871  *
3872  *  Returns 0 on success, negative on failure
3873  **/
3874 int igb_setup_rx_resources(struct igb_ring *rx_ring)
3875 {
3876         struct device *dev = rx_ring->dev;
3877         int size;
3878
3879         size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3880
3881         rx_ring->rx_buffer_info = vmalloc(size);
3882         if (!rx_ring->rx_buffer_info)
3883                 goto err;
3884
3885         /* Round up to nearest 4K */
3886         rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3887         rx_ring->size = ALIGN(rx_ring->size, 4096);
3888
3889         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3890                                            &rx_ring->dma, GFP_KERNEL);
3891         if (!rx_ring->desc)
3892                 goto err;
3893
3894         rx_ring->next_to_alloc = 0;
3895         rx_ring->next_to_clean = 0;
3896         rx_ring->next_to_use = 0;
3897
3898         return 0;
3899
3900 err:
3901         vfree(rx_ring->rx_buffer_info);
3902         rx_ring->rx_buffer_info = NULL;
3903         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3904         return -ENOMEM;
3905 }
3906
3907 /**
3908  *  igb_setup_all_rx_resources - wrapper to allocate Rx resources
3909  *                               (Descriptors) for all queues
3910  *  @adapter: board private structure
3911  *
3912  *  Return 0 on success, negative on failure
3913  **/
3914 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3915 {
3916         struct pci_dev *pdev = adapter->pdev;
3917         int i, err = 0;
3918
3919         for (i = 0; i < adapter->num_rx_queues; i++) {
3920                 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3921                 if (err) {
3922                         dev_err(&pdev->dev,
3923                                 "Allocation for Rx Queue %u failed\n", i);
3924                         for (i--; i >= 0; i--)
3925                                 igb_free_rx_resources(adapter->rx_ring[i]);
3926                         break;
3927                 }
3928         }
3929
3930         return err;
3931 }
3932
3933 /**
3934  *  igb_setup_mrqc - configure the multiple receive queue control registers
3935  *  @adapter: Board private structure
3936  **/
3937 static void igb_setup_mrqc(struct igb_adapter *adapter)
3938 {
3939         struct e1000_hw *hw = &adapter->hw;
3940         u32 mrqc, rxcsum;
3941         u32 j, num_rx_queues;
3942         u32 rss_key[10];
3943
3944         netdev_rss_key_fill(rss_key, sizeof(rss_key));
3945         for (j = 0; j < 10; j++)
3946                 wr32(E1000_RSSRK(j), rss_key[j]);
3947
3948         num_rx_queues = adapter->rss_queues;
3949
3950         switch (hw->mac.type) {
3951         case e1000_82576:
3952                 /* 82576 supports 2 RSS queues for SR-IOV */
3953                 if (adapter->vfs_allocated_count)
3954                         num_rx_queues = 2;
3955                 break;
3956         default:
3957                 break;
3958         }
3959
3960         if (adapter->rss_indir_tbl_init != num_rx_queues) {
3961                 for (j = 0; j < IGB_RETA_SIZE; j++)
3962                         adapter->rss_indir_tbl[j] =
3963                         (j * num_rx_queues) / IGB_RETA_SIZE;
3964                 adapter->rss_indir_tbl_init = num_rx_queues;
3965         }
3966         igb_write_rss_indir_tbl(adapter);
3967
3968         /* Disable raw packet checksumming so that RSS hash is placed in
3969          * descriptor on writeback.  No need to enable TCP/UDP/IP checksum
3970          * offloads as they are enabled by default
3971          */
3972         rxcsum = rd32(E1000_RXCSUM);
3973         rxcsum |= E1000_RXCSUM_PCSD;
3974
3975         if (adapter->hw.mac.type >= e1000_82576)
3976                 /* Enable Receive Checksum Offload for SCTP */
3977                 rxcsum |= E1000_RXCSUM_CRCOFL;
3978
3979         /* Don't need to set TUOFL or IPOFL, they default to 1 */
3980         wr32(E1000_RXCSUM, rxcsum);
3981
3982         /* Generate RSS hash based on packet types, TCP/UDP
3983          * port numbers and/or IPv4/v6 src and dst addresses
3984          */
3985         mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3986                E1000_MRQC_RSS_FIELD_IPV4_TCP |
3987                E1000_MRQC_RSS_FIELD_IPV6 |
3988                E1000_MRQC_RSS_FIELD_IPV6_TCP |
3989                E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3990
3991         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3992                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3993         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3994                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3995
3996         /* If VMDq is enabled then we set the appropriate mode for that, else
3997          * we default to RSS so that an RSS hash is calculated per packet even
3998          * if we are only using one queue
3999          */
4000         if (adapter->vfs_allocated_count) {
4001                 if (hw->mac.type > e1000_82575) {
4002                         /* Set the default pool for the PF's first queue */
4003                         u32 vtctl = rd32(E1000_VT_CTL);
4004
4005                         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
4006                                    E1000_VT_CTL_DISABLE_DEF_POOL);
4007                         vtctl |= adapter->vfs_allocated_count <<
4008                                 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
4009                         wr32(E1000_VT_CTL, vtctl);
4010                 }
4011                 if (adapter->rss_queues > 1)
4012                         mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ;
4013                 else
4014                         mrqc |= E1000_MRQC_ENABLE_VMDQ;
4015         } else {
4016                 if (hw->mac.type != e1000_i211)
4017                         mrqc |= E1000_MRQC_ENABLE_RSS_MQ;
4018         }
4019         igb_vmm_control(adapter);
4020
4021         wr32(E1000_MRQC, mrqc);
4022 }
4023
4024 /**
4025  *  igb_setup_rctl - configure the receive control registers
4026  *  @adapter: Board private structure
4027  **/
4028 void igb_setup_rctl(struct igb_adapter *adapter)
4029 {
4030         struct e1000_hw *hw = &adapter->hw;
4031         u32 rctl;
4032
4033         rctl = rd32(E1000_RCTL);
4034
4035         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4036         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
4037
4038         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
4039                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
4040
4041         /* enable stripping of CRC. It's unlikely this will break BMC
4042          * redirection as it did with e1000. Newer features require
4043          * that the HW strips the CRC.
4044          */
4045         rctl |= E1000_RCTL_SECRC;
4046
4047         /* disable store bad packets and clear size bits. */
4048         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
4049
4050         /* enable LPE to allow for reception of jumbo frames */
4051         rctl |= E1000_RCTL_LPE;
4052
4053         /* disable queue 0 to prevent tail write w/o re-config */
4054         wr32(E1000_RXDCTL(0), 0);
4055
4056         /* Attention!!!  For SR-IOV PF driver operations you must enable
4057          * queue drop for all VF and PF queues to prevent head of line blocking
4058          * if an un-trusted VF does not provide descriptors to hardware.
4059          */
4060         if (adapter->vfs_allocated_count) {
4061                 /* set all queue drop enable bits */
4062                 wr32(E1000_QDE, ALL_QUEUES);
4063         }
4064
4065         /* This is useful for sniffing bad packets. */
4066         if (adapter->netdev->features & NETIF_F_RXALL) {
4067                 /* UPE and MPE will be handled by normal PROMISC logic
4068                  * in e1000e_set_rx_mode
4069                  */
4070                 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
4071                          E1000_RCTL_BAM | /* RX All Bcast Pkts */
4072                          E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
4073
4074                 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
4075                           E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
4076                 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
4077                  * and that breaks VLANs.
4078                  */
4079         }
4080
4081         wr32(E1000_RCTL, rctl);
4082 }
4083
4084 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
4085                                    int vfn)
4086 {
4087         struct e1000_hw *hw = &adapter->hw;
4088         u32 vmolr;
4089
4090         if (size > MAX_JUMBO_FRAME_SIZE)
4091                 size = MAX_JUMBO_FRAME_SIZE;
4092
4093         vmolr = rd32(E1000_VMOLR(vfn));
4094         vmolr &= ~E1000_VMOLR_RLPML_MASK;
4095         vmolr |= size | E1000_VMOLR_LPE;
4096         wr32(E1000_VMOLR(vfn), vmolr);
4097
4098         return 0;
4099 }
4100
4101 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter,
4102                                          int vfn, bool enable)
4103 {
4104         struct e1000_hw *hw = &adapter->hw;
4105         u32 val, reg;
4106
4107         if (hw->mac.type < e1000_82576)
4108                 return;
4109
4110         if (hw->mac.type == e1000_i350)
4111                 reg = E1000_DVMOLR(vfn);
4112         else
4113                 reg = E1000_VMOLR(vfn);
4114
4115         val = rd32(reg);
4116         if (enable)
4117                 val |= E1000_VMOLR_STRVLAN;
4118         else
4119                 val &= ~(E1000_VMOLR_STRVLAN);
4120         wr32(reg, val);
4121 }
4122
4123 static inline void igb_set_vmolr(struct igb_adapter *adapter,
4124                                  int vfn, bool aupe)
4125 {
4126         struct e1000_hw *hw = &adapter->hw;
4127         u32 vmolr;
4128
4129         /* This register exists only on 82576 and newer so if we are older then
4130          * we should exit and do nothing
4131          */
4132         if (hw->mac.type < e1000_82576)
4133                 return;
4134
4135         vmolr = rd32(E1000_VMOLR(vfn));
4136         if (aupe)
4137                 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
4138         else
4139                 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
4140
4141         /* clear all bits that might not be set */
4142         vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
4143
4144         if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
4145                 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
4146         /* for VMDq only allow the VFs and pool 0 to accept broadcast and
4147          * multicast packets
4148          */
4149         if (vfn <= adapter->vfs_allocated_count)
4150                 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
4151
4152         wr32(E1000_VMOLR(vfn), vmolr);
4153 }
4154
4155 /**
4156  *  igb_configure_rx_ring - Configure a receive ring after Reset
4157  *  @adapter: board private structure
4158  *  @ring: receive ring to be configured
4159  *
4160  *  Configure the Rx unit of the MAC after a reset.
4161  **/
4162 void igb_configure_rx_ring(struct igb_adapter *adapter,
4163                            struct igb_ring *ring)
4164 {
4165         struct e1000_hw *hw = &adapter->hw;
4166         union e1000_adv_rx_desc *rx_desc;
4167         u64 rdba = ring->dma;
4168         int reg_idx = ring->reg_idx;
4169         u32 srrctl = 0, rxdctl = 0;
4170
4171         /* disable the queue */
4172         wr32(E1000_RXDCTL(reg_idx), 0);
4173
4174         /* Set DMA base address registers */
4175         wr32(E1000_RDBAL(reg_idx),
4176              rdba & 0x00000000ffffffffULL);
4177         wr32(E1000_RDBAH(reg_idx), rdba >> 32);
4178         wr32(E1000_RDLEN(reg_idx),
4179              ring->count * sizeof(union e1000_adv_rx_desc));
4180
4181         /* initialize head and tail */
4182         ring->tail = adapter->io_addr + E1000_RDT(reg_idx);
4183         wr32(E1000_RDH(reg_idx), 0);
4184         writel(0, ring->tail);
4185
4186         /* set descriptor configuration */
4187         srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
4188         if (ring_uses_large_buffer(ring))
4189                 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4190         else
4191                 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4192         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
4193         if (hw->mac.type >= e1000_82580)
4194                 srrctl |= E1000_SRRCTL_TIMESTAMP;
4195         /* Only set Drop Enable if we are supporting multiple queues */
4196         if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
4197                 srrctl |= E1000_SRRCTL_DROP_EN;
4198
4199         wr32(E1000_SRRCTL(reg_idx), srrctl);
4200
4201         /* set filtering for VMDQ pools */
4202         igb_set_vmolr(adapter, reg_idx & 0x7, true);
4203
4204         rxdctl |= IGB_RX_PTHRESH;
4205         rxdctl |= IGB_RX_HTHRESH << 8;
4206         rxdctl |= IGB_RX_WTHRESH << 16;
4207
4208         /* initialize rx_buffer_info */
4209         memset(ring->rx_buffer_info, 0,
4210                sizeof(struct igb_rx_buffer) * ring->count);
4211
4212         /* initialize Rx descriptor 0 */
4213         rx_desc = IGB_RX_DESC(ring, 0);
4214         rx_desc->wb.upper.length = 0;
4215
4216         /* enable receive descriptor fetching */
4217         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
4218         wr32(E1000_RXDCTL(reg_idx), rxdctl);
4219 }
4220
4221 static void igb_set_rx_buffer_len(struct igb_adapter *adapter,
4222                                   struct igb_ring *rx_ring)
4223 {
4224         /* set build_skb and buffer size flags */
4225         clear_ring_build_skb_enabled(rx_ring);
4226         clear_ring_uses_large_buffer(rx_ring);
4227
4228         if (adapter->flags & IGB_FLAG_RX_LEGACY)
4229                 return;
4230
4231         set_ring_build_skb_enabled(rx_ring);
4232
4233 #if (PAGE_SIZE < 8192)
4234         if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
4235                 return;
4236
4237         set_ring_uses_large_buffer(rx_ring);
4238 #endif
4239 }
4240
4241 /**
4242  *  igb_configure_rx - Configure receive Unit after Reset
4243  *  @adapter: board private structure
4244  *
4245  *  Configure the Rx unit of the MAC after a reset.
4246  **/
4247 static void igb_configure_rx(struct igb_adapter *adapter)
4248 {
4249         int i;
4250
4251         /* set the correct pool for the PF default MAC address in entry 0 */
4252         igb_set_default_mac_filter(adapter);
4253
4254         /* Setup the HW Rx Head and Tail Descriptor Pointers and
4255          * the Base and Length of the Rx Descriptor Ring
4256          */
4257         for (i = 0; i < adapter->num_rx_queues; i++) {
4258                 struct igb_ring *rx_ring = adapter->rx_ring[i];
4259
4260                 igb_set_rx_buffer_len(adapter, rx_ring);
4261                 igb_configure_rx_ring(adapter, rx_ring);
4262         }
4263 }
4264
4265 /**
4266  *  igb_free_tx_resources - Free Tx Resources per Queue
4267  *  @tx_ring: Tx descriptor ring for a specific queue
4268  *
4269  *  Free all transmit software resources
4270  **/
4271 void igb_free_tx_resources(struct igb_ring *tx_ring)
4272 {
4273         igb_clean_tx_ring(tx_ring);
4274
4275         vfree(tx_ring->tx_buffer_info);
4276         tx_ring->tx_buffer_info = NULL;
4277
4278         /* if not set, then don't free */
4279         if (!tx_ring->desc)
4280                 return;
4281
4282         dma_free_coherent(tx_ring->dev, tx_ring->size,
4283                           tx_ring->desc, tx_ring->dma);
4284
4285         tx_ring->desc = NULL;
4286 }
4287
4288 /**
4289  *  igb_free_all_tx_resources - Free Tx Resources for All Queues
4290  *  @adapter: board private structure
4291  *
4292  *  Free all transmit software resources
4293  **/
4294 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
4295 {
4296         int i;
4297
4298         for (i = 0; i < adapter->num_tx_queues; i++)
4299                 if (adapter->tx_ring[i])
4300                         igb_free_tx_resources(adapter->tx_ring[i]);
4301 }
4302
4303 /**
4304  *  igb_clean_tx_ring - Free Tx Buffers
4305  *  @tx_ring: ring to be cleaned
4306  **/
4307 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
4308 {
4309         u16 i = tx_ring->next_to_clean;
4310         struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
4311
4312         while (i != tx_ring->next_to_use) {
4313                 union e1000_adv_tx_desc *eop_desc, *tx_desc;
4314
4315                 /* Free all the Tx ring sk_buffs */
4316                 dev_kfree_skb_any(tx_buffer->skb);
4317
4318                 /* unmap skb header data */
4319                 dma_unmap_single(tx_ring->dev,
4320                                  dma_unmap_addr(tx_buffer, dma),
4321                                  dma_unmap_len(tx_buffer, len),
4322                                  DMA_TO_DEVICE);
4323
4324                 /* check for eop_desc to determine the end of the packet */
4325                 eop_desc = tx_buffer->next_to_watch;
4326                 tx_desc = IGB_TX_DESC(tx_ring, i);
4327
4328                 /* unmap remaining buffers */
4329                 while (tx_desc != eop_desc) {
4330                         tx_buffer++;
4331                         tx_desc++;
4332                         i++;
4333                         if (unlikely(i == tx_ring->count)) {
4334                                 i = 0;
4335                                 tx_buffer = tx_ring->tx_buffer_info;
4336                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
4337                         }
4338
4339                         /* unmap any remaining paged data */
4340                         if (dma_unmap_len(tx_buffer, len))
4341                                 dma_unmap_page(tx_ring->dev,
4342                                                dma_unmap_addr(tx_buffer, dma),
4343                                                dma_unmap_len(tx_buffer, len),
4344                                                DMA_TO_DEVICE);
4345                 }
4346
4347                 /* move us one more past the eop_desc for start of next pkt */
4348                 tx_buffer++;
4349                 i++;
4350                 if (unlikely(i == tx_ring->count)) {
4351                         i = 0;
4352                         tx_buffer = tx_ring->tx_buffer_info;
4353                 }
4354         }
4355
4356         /* reset BQL for queue */
4357         netdev_tx_reset_queue(txring_txq(tx_ring));
4358
4359         /* reset next_to_use and next_to_clean */
4360         tx_ring->next_to_use = 0;
4361         tx_ring->next_to_clean = 0;
4362 }
4363
4364 /**
4365  *  igb_clean_all_tx_rings - Free Tx Buffers for all queues
4366  *  @adapter: board private structure
4367  **/
4368 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
4369 {
4370         int i;
4371
4372         for (i = 0; i < adapter->num_tx_queues; i++)
4373                 if (adapter->tx_ring[i])
4374                         igb_clean_tx_ring(adapter->tx_ring[i]);
4375 }
4376
4377 /**
4378  *  igb_free_rx_resources - Free Rx Resources
4379  *  @rx_ring: ring to clean the resources from
4380  *
4381  *  Free all receive software resources
4382  **/
4383 void igb_free_rx_resources(struct igb_ring *rx_ring)
4384 {
4385         igb_clean_rx_ring(rx_ring);
4386
4387         vfree(rx_ring->rx_buffer_info);
4388         rx_ring->rx_buffer_info = NULL;
4389
4390         /* if not set, then don't free */
4391         if (!rx_ring->desc)
4392                 return;
4393
4394         dma_free_coherent(rx_ring->dev, rx_ring->size,
4395                           rx_ring->desc, rx_ring->dma);
4396
4397         rx_ring->desc = NULL;
4398 }
4399
4400 /**
4401  *  igb_free_all_rx_resources - Free Rx Resources for All Queues
4402  *  @adapter: board private structure
4403  *
4404  *  Free all receive software resources
4405  **/
4406 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
4407 {
4408         int i;
4409
4410         for (i = 0; i < adapter->num_rx_queues; i++)
4411                 if (adapter->rx_ring[i])
4412                         igb_free_rx_resources(adapter->rx_ring[i]);
4413 }
4414
4415 /**
4416  *  igb_clean_rx_ring - Free Rx Buffers per Queue
4417  *  @rx_ring: ring to free buffers from
4418  **/
4419 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
4420 {
4421         u16 i = rx_ring->next_to_clean;
4422
4423         if (rx_ring->skb)
4424                 dev_kfree_skb(rx_ring->skb);
4425         rx_ring->skb = NULL;
4426
4427         /* Free all the Rx ring sk_buffs */
4428         while (i != rx_ring->next_to_alloc) {
4429                 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
4430
4431                 /* Invalidate cache lines that may have been written to by
4432                  * device so that we avoid corrupting memory.
4433                  */
4434                 dma_sync_single_range_for_cpu(rx_ring->dev,
4435                                               buffer_info->dma,
4436                                               buffer_info->page_offset,
4437                                               igb_rx_bufsz(rx_ring),
4438                                               DMA_FROM_DEVICE);
4439
4440                 /* free resources associated with mapping */
4441                 dma_unmap_page_attrs(rx_ring->dev,
4442                                      buffer_info->dma,
4443                                      igb_rx_pg_size(rx_ring),
4444                                      DMA_FROM_DEVICE,
4445                                      IGB_RX_DMA_ATTR);
4446                 __page_frag_cache_drain(buffer_info->page,
4447                                         buffer_info->pagecnt_bias);
4448
4449                 i++;
4450                 if (i == rx_ring->count)
4451                         i = 0;
4452         }
4453
4454         rx_ring->next_to_alloc = 0;
4455         rx_ring->next_to_clean = 0;
4456         rx_ring->next_to_use = 0;
4457 }
4458
4459 /**
4460  *  igb_clean_all_rx_rings - Free Rx Buffers for all queues
4461  *  @adapter: board private structure
4462  **/
4463 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
4464 {
4465         int i;
4466
4467         for (i = 0; i < adapter->num_rx_queues; i++)
4468                 if (adapter->rx_ring[i])
4469                         igb_clean_rx_ring(adapter->rx_ring[i]);
4470 }
4471
4472 /**
4473  *  igb_set_mac - Change the Ethernet Address of the NIC
4474  *  @netdev: network interface device structure
4475  *  @p: pointer to an address structure
4476  *
4477  *  Returns 0 on success, negative on failure
4478  **/
4479 static int igb_set_mac(struct net_device *netdev, void *p)
4480 {
4481         struct igb_adapter *adapter = netdev_priv(netdev);
4482         struct e1000_hw *hw = &adapter->hw;
4483         struct sockaddr *addr = p;
4484
4485         if (!is_valid_ether_addr(addr->sa_data))
4486                 return -EADDRNOTAVAIL;
4487
4488         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4489         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
4490
4491         /* set the correct pool for the new PF MAC address in entry 0 */
4492         igb_set_default_mac_filter(adapter);
4493
4494         return 0;
4495 }
4496
4497 /**
4498  *  igb_write_mc_addr_list - write multicast addresses to MTA
4499  *  @netdev: network interface device structure
4500  *
4501  *  Writes multicast address list to the MTA hash table.
4502  *  Returns: -ENOMEM on failure
4503  *           0 on no addresses written
4504  *           X on writing X addresses to MTA
4505  **/
4506 static int igb_write_mc_addr_list(struct net_device *netdev)
4507 {
4508         struct igb_adapter *adapter = netdev_priv(netdev);
4509         struct e1000_hw *hw = &adapter->hw;
4510         struct netdev_hw_addr *ha;
4511         u8  *mta_list;
4512         int i;
4513
4514         if (netdev_mc_empty(netdev)) {
4515                 /* nothing to program, so clear mc list */
4516                 igb_update_mc_addr_list(hw, NULL, 0);
4517                 igb_restore_vf_multicasts(adapter);
4518                 return 0;
4519         }
4520
4521         mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
4522         if (!mta_list)
4523                 return -ENOMEM;
4524
4525         /* The shared function expects a packed array of only addresses. */
4526         i = 0;
4527         netdev_for_each_mc_addr(ha, netdev)
4528                 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
4529
4530         igb_update_mc_addr_list(hw, mta_list, i);
4531         kfree(mta_list);
4532
4533         return netdev_mc_count(netdev);
4534 }
4535
4536 static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
4537 {
4538         struct e1000_hw *hw = &adapter->hw;
4539         u32 i, pf_id;
4540
4541         switch (hw->mac.type) {
4542         case e1000_i210:
4543         case e1000_i211:
4544         case e1000_i350:
4545                 /* VLAN filtering needed for VLAN prio filter */
4546                 if (adapter->netdev->features & NETIF_F_NTUPLE)
4547                         break;
4548                 /* fall through */
4549         case e1000_82576:
4550         case e1000_82580:
4551         case e1000_i354:
4552                 /* VLAN filtering needed for pool filtering */
4553                 if (adapter->vfs_allocated_count)
4554                         break;
4555                 /* fall through */
4556         default:
4557                 return 1;
4558         }
4559
4560         /* We are already in VLAN promisc, nothing to do */
4561         if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
4562                 return 0;
4563
4564         if (!adapter->vfs_allocated_count)
4565                 goto set_vfta;
4566
4567         /* Add PF to all active pools */
4568         pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4569
4570         for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4571                 u32 vlvf = rd32(E1000_VLVF(i));
4572
4573                 vlvf |= BIT(pf_id);
4574                 wr32(E1000_VLVF(i), vlvf);
4575         }
4576
4577 set_vfta:
4578         /* Set all bits in the VLAN filter table array */
4579         for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
4580                 hw->mac.ops.write_vfta(hw, i, ~0U);
4581
4582         /* Set flag so we don't redo unnecessary work */
4583         adapter->flags |= IGB_FLAG_VLAN_PROMISC;
4584
4585         return 0;
4586 }
4587
4588 #define VFTA_BLOCK_SIZE 8
4589 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
4590 {
4591         struct e1000_hw *hw = &adapter->hw;
4592         u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4593         u32 vid_start = vfta_offset * 32;
4594         u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4595         u32 i, vid, word, bits, pf_id;
4596
4597         /* guarantee that we don't scrub out management VLAN */
4598         vid = adapter->mng_vlan_id;
4599         if (vid >= vid_start && vid < vid_end)
4600                 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
4601
4602         if (!adapter->vfs_allocated_count)
4603                 goto set_vfta;
4604
4605         pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4606
4607         for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4608                 u32 vlvf = rd32(E1000_VLVF(i));
4609
4610                 /* pull VLAN ID from VLVF */
4611                 vid = vlvf & VLAN_VID_MASK;
4612
4613                 /* only concern ourselves with a certain range */
4614                 if (vid < vid_start || vid >= vid_end)
4615                         continue;
4616
4617                 if (vlvf & E1000_VLVF_VLANID_ENABLE) {
4618                         /* record VLAN ID in VFTA */
4619                         vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
4620
4621                         /* if PF is part of this then continue */
4622                         if (test_bit(vid, adapter->active_vlans))
4623                                 continue;
4624                 }
4625
4626                 /* remove PF from the pool */
4627                 bits = ~BIT(pf_id);
4628                 bits &= rd32(E1000_VLVF(i));
4629                 wr32(E1000_VLVF(i), bits);
4630         }
4631
4632 set_vfta:
4633         /* extract values from active_vlans and write back to VFTA */
4634         for (i = VFTA_BLOCK_SIZE; i--;) {
4635                 vid = (vfta_offset + i) * 32;
4636                 word = vid / BITS_PER_LONG;
4637                 bits = vid % BITS_PER_LONG;
4638
4639                 vfta[i] |= adapter->active_vlans[word] >> bits;
4640
4641                 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
4642         }
4643 }
4644
4645 static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
4646 {
4647         u32 i;
4648
4649         /* We are not in VLAN promisc, nothing to do */
4650         if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
4651                 return;
4652
4653         /* Set flag so we don't redo unnecessary work */
4654         adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
4655
4656         for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
4657                 igb_scrub_vfta(adapter, i);
4658 }
4659
4660 /**
4661  *  igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
4662  *  @netdev: network interface device structure
4663  *
4664  *  The set_rx_mode entry point is called whenever the unicast or multicast
4665  *  address lists or the network interface flags are updated.  This routine is
4666  *  responsible for configuring the hardware for proper unicast, multicast,
4667  *  promiscuous mode, and all-multi behavior.
4668  **/
4669 static void igb_set_rx_mode(struct net_device *netdev)
4670 {
4671         struct igb_adapter *adapter = netdev_priv(netdev);
4672         struct e1000_hw *hw = &adapter->hw;
4673         unsigned int vfn = adapter->vfs_allocated_count;
4674         u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE;
4675         int count;
4676
4677         /* Check for Promiscuous and All Multicast modes */
4678         if (netdev->flags & IFF_PROMISC) {
4679                 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
4680                 vmolr |= E1000_VMOLR_MPME;
4681
4682                 /* enable use of UTA filter to force packets to default pool */
4683                 if (hw->mac.type == e1000_82576)
4684                         vmolr |= E1000_VMOLR_ROPE;
4685         } else {
4686                 if (netdev->flags & IFF_ALLMULTI) {
4687                         rctl |= E1000_RCTL_MPE;
4688                         vmolr |= E1000_VMOLR_MPME;
4689                 } else {
4690                         /* Write addresses to the MTA, if the attempt fails
4691                          * then we should just turn on promiscuous mode so
4692                          * that we can at least receive multicast traffic
4693                          */
4694                         count = igb_write_mc_addr_list(netdev);
4695                         if (count < 0) {
4696                                 rctl |= E1000_RCTL_MPE;
4697                                 vmolr |= E1000_VMOLR_MPME;
4698                         } else if (count) {
4699                                 vmolr |= E1000_VMOLR_ROMPE;
4700                         }
4701                 }
4702         }
4703
4704         /* Write addresses to available RAR registers, if there is not
4705          * sufficient space to store all the addresses then enable
4706          * unicast promiscuous mode
4707          */
4708         if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) {
4709                 rctl |= E1000_RCTL_UPE;
4710                 vmolr |= E1000_VMOLR_ROPE;
4711         }
4712
4713         /* enable VLAN filtering by default */
4714         rctl |= E1000_RCTL_VFE;
4715
4716         /* disable VLAN filtering for modes that require it */
4717         if ((netdev->flags & IFF_PROMISC) ||
4718             (netdev->features & NETIF_F_RXALL)) {
4719                 /* if we fail to set all rules then just clear VFE */
4720                 if (igb_vlan_promisc_enable(adapter))
4721                         rctl &= ~E1000_RCTL_VFE;
4722         } else {
4723                 igb_vlan_promisc_disable(adapter);
4724         }
4725
4726         /* update state of unicast, multicast, and VLAN filtering modes */
4727         rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
4728                                      E1000_RCTL_VFE);
4729         wr32(E1000_RCTL, rctl);
4730
4731 #if (PAGE_SIZE < 8192)
4732         if (!adapter->vfs_allocated_count) {
4733                 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
4734                         rlpml = IGB_MAX_FRAME_BUILD_SKB;
4735         }
4736 #endif
4737         wr32(E1000_RLPML, rlpml);
4738
4739         /* In order to support SR-IOV and eventually VMDq it is necessary to set
4740          * the VMOLR to enable the appropriate modes.  Without this workaround
4741          * we will have issues with VLAN tag stripping not being done for frames
4742          * that are only arriving because we are the default pool
4743          */
4744         if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
4745                 return;
4746
4747         /* set UTA to appropriate mode */
4748         igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE));
4749
4750         vmolr |= rd32(E1000_VMOLR(vfn)) &
4751                  ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
4752
4753         /* enable Rx jumbo frames, restrict as needed to support build_skb */
4754         vmolr &= ~E1000_VMOLR_RLPML_MASK;
4755 #if (PAGE_SIZE < 8192)
4756         if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
4757                 vmolr |= IGB_MAX_FRAME_BUILD_SKB;
4758         else
4759 #endif
4760                 vmolr |= MAX_JUMBO_FRAME_SIZE;
4761         vmolr |= E1000_VMOLR_LPE;
4762
4763         wr32(E1000_VMOLR(vfn), vmolr);
4764
4765         igb_restore_vf_multicasts(adapter);
4766 }
4767
4768 static void igb_check_wvbr(struct igb_adapter *adapter)
4769 {
4770         struct e1000_hw *hw = &adapter->hw;
4771         u32 wvbr = 0;
4772
4773         switch (hw->mac.type) {
4774         case e1000_82576:
4775         case e1000_i350:
4776                 wvbr = rd32(E1000_WVBR);
4777                 if (!wvbr)
4778                         return;
4779                 break;
4780         default:
4781                 break;
4782         }
4783
4784         adapter->wvbr |= wvbr;
4785 }
4786
4787 #define IGB_STAGGERED_QUEUE_OFFSET 8
4788
4789 static void igb_spoof_check(struct igb_adapter *adapter)
4790 {
4791         int j;
4792
4793         if (!adapter->wvbr)
4794                 return;
4795
4796         for (j = 0; j < adapter->vfs_allocated_count; j++) {
4797                 if (adapter->wvbr & BIT(j) ||
4798                     adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) {
4799                         dev_warn(&adapter->pdev->dev,
4800                                 "Spoof event(s) detected on VF %d\n", j);
4801                         adapter->wvbr &=
4802                                 ~(BIT(j) |
4803                                   BIT(j + IGB_STAGGERED_QUEUE_OFFSET));
4804                 }
4805         }
4806 }
4807
4808 /* Need to wait a few seconds after link up to get diagnostic information from
4809  * the phy
4810  */
4811 static void igb_update_phy_info(struct timer_list *t)
4812 {
4813         struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer);
4814         igb_get_phy_info(&adapter->hw);
4815 }
4816
4817 /**
4818  *  igb_has_link - check shared code for link and determine up/down
4819  *  @adapter: pointer to driver private info
4820  **/
4821 bool igb_has_link(struct igb_adapter *adapter)
4822 {
4823         struct e1000_hw *hw = &adapter->hw;
4824         bool link_active = false;
4825
4826         /* get_link_status is set on LSC (link status) interrupt or
4827          * rx sequence error interrupt.  get_link_status will stay
4828          * false until the e1000_check_for_link establishes link
4829          * for copper adapters ONLY
4830          */
4831         switch (hw->phy.media_type) {
4832         case e1000_media_type_copper:
4833                 if (!hw->mac.get_link_status)
4834                         return true;
4835         case e1000_media_type_internal_serdes:
4836                 hw->mac.ops.check_for_link(hw);
4837                 link_active = !hw->mac.get_link_status;
4838                 break;
4839         default:
4840         case e1000_media_type_unknown:
4841                 break;
4842         }
4843
4844         if (((hw->mac.type == e1000_i210) ||
4845              (hw->mac.type == e1000_i211)) &&
4846              (hw->phy.id == I210_I_PHY_ID)) {
4847                 if (!netif_carrier_ok(adapter->netdev)) {
4848                         adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4849                 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4850                         adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4851                         adapter->link_check_timeout = jiffies;
4852                 }
4853         }
4854
4855         return link_active;
4856 }
4857
4858 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4859 {
4860         bool ret = false;
4861         u32 ctrl_ext, thstat;
4862
4863         /* check for thermal sensor event on i350 copper only */
4864         if (hw->mac.type == e1000_i350) {
4865                 thstat = rd32(E1000_THSTAT);
4866                 ctrl_ext = rd32(E1000_CTRL_EXT);
4867
4868                 if ((hw->phy.media_type == e1000_media_type_copper) &&
4869                     !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
4870                         ret = !!(thstat & event);
4871         }
4872
4873         return ret;
4874 }
4875
4876 /**
4877  *  igb_check_lvmmc - check for malformed packets received
4878  *  and indicated in LVMMC register
4879  *  @adapter: pointer to adapter
4880  **/
4881 static void igb_check_lvmmc(struct igb_adapter *adapter)
4882 {
4883         struct e1000_hw *hw = &adapter->hw;
4884         u32 lvmmc;
4885
4886         lvmmc = rd32(E1000_LVMMC);
4887         if (lvmmc) {
4888                 if (unlikely(net_ratelimit())) {
4889                         netdev_warn(adapter->netdev,
4890                                     "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4891                                     lvmmc);
4892                 }
4893         }
4894 }
4895
4896 /**
4897  *  igb_watchdog - Timer Call-back
4898  *  @data: pointer to adapter cast into an unsigned long
4899  **/
4900 static void igb_watchdog(struct timer_list *t)
4901 {
4902         struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer);
4903         /* Do the rest outside of interrupt context */
4904         schedule_work(&adapter->watchdog_task);
4905 }
4906
4907 static void igb_watchdog_task(struct work_struct *work)
4908 {
4909         struct igb_adapter *adapter = container_of(work,
4910                                                    struct igb_adapter,
4911                                                    watchdog_task);
4912         struct e1000_hw *hw = &adapter->hw;
4913         struct e1000_phy_info *phy = &hw->phy;
4914         struct net_device *netdev = adapter->netdev;
4915         u32 link;
4916         int i;
4917         u32 connsw;
4918         u16 phy_data, retry_count = 20;
4919
4920         link = igb_has_link(adapter);
4921
4922         if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4923                 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4924                         adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4925                 else
4926                         link = false;
4927         }
4928
4929         /* Force link down if we have fiber to swap to */
4930         if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4931                 if (hw->phy.media_type == e1000_media_type_copper) {
4932                         connsw = rd32(E1000_CONNSW);
4933                         if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4934                                 link = 0;
4935                 }
4936         }
4937         if (link) {
4938                 /* Perform a reset if the media type changed. */
4939                 if (hw->dev_spec._82575.media_changed) {
4940                         hw->dev_spec._82575.media_changed = false;
4941                         adapter->flags |= IGB_FLAG_MEDIA_RESET;
4942                         igb_reset(adapter);
4943                 }
4944                 /* Cancel scheduled suspend requests. */
4945                 pm_runtime_resume(netdev->dev.parent);
4946
4947                 if (!netif_carrier_ok(netdev)) {
4948                         u32 ctrl;
4949
4950                         hw->mac.ops.get_speed_and_duplex(hw,
4951                                                          &adapter->link_speed,
4952                                                          &adapter->link_duplex);
4953
4954                         ctrl = rd32(E1000_CTRL);
4955                         /* Links status message must follow this format */
4956                         netdev_info(netdev,
4957                                "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4958                                netdev->name,
4959                                adapter->link_speed,
4960                                adapter->link_duplex == FULL_DUPLEX ?
4961                                "Full" : "Half",
4962                                (ctrl & E1000_CTRL_TFCE) &&
4963                                (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4964                                (ctrl & E1000_CTRL_RFCE) ?  "RX" :
4965                                (ctrl & E1000_CTRL_TFCE) ?  "TX" : "None");
4966
4967                         /* disable EEE if enabled */
4968                         if ((adapter->flags & IGB_FLAG_EEE) &&
4969                                 (adapter->link_duplex == HALF_DUPLEX)) {
4970                                 dev_info(&adapter->pdev->dev,
4971                                 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4972                                 adapter->hw.dev_spec._82575.eee_disable = true;
4973                                 adapter->flags &= ~IGB_FLAG_EEE;
4974                         }
4975
4976                         /* check if SmartSpeed worked */
4977                         igb_check_downshift(hw);
4978                         if (phy->speed_downgraded)
4979                                 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4980
4981                         /* check for thermal sensor event */
4982                         if (igb_thermal_sensor_event(hw,
4983                             E1000_THSTAT_LINK_THROTTLE))
4984                                 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
4985
4986                         /* adjust timeout factor according to speed/duplex */
4987                         adapter->tx_timeout_factor = 1;
4988                         switch (adapter->link_speed) {
4989                         case SPEED_10:
4990                                 adapter->tx_timeout_factor = 14;
4991                                 break;
4992                         case SPEED_100:
4993                                 /* maybe add some timeout factor ? */
4994                                 break;
4995                         }
4996
4997                         if (adapter->link_speed != SPEED_1000)
4998                                 goto no_wait;
4999
5000                         /* wait for Remote receiver status OK */
5001 retry_read_status:
5002                         if (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
5003                                               &phy_data)) {
5004                                 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
5005                                     retry_count) {
5006                                         msleep(100);
5007                                         retry_count--;
5008                                         goto retry_read_status;
5009                                 } else if (!retry_count) {
5010                                         dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
5011                                 }
5012                         } else {
5013                                 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
5014                         }
5015 no_wait:
5016                         netif_carrier_on(netdev);
5017
5018                         igb_ping_all_vfs(adapter);
5019                         igb_check_vf_rate_limit(adapter);
5020
5021                         /* link state has changed, schedule phy info update */
5022                         if (!test_bit(__IGB_DOWN, &adapter->state))
5023                                 mod_timer(&adapter->phy_info_timer,
5024                                           round_jiffies(jiffies + 2 * HZ));
5025                 }
5026         } else {
5027                 if (netif_carrier_ok(netdev)) {
5028                         adapter->link_speed = 0;
5029                         adapter->link_duplex = 0;
5030
5031                         /* check for thermal sensor event */
5032                         if (igb_thermal_sensor_event(hw,
5033                             E1000_THSTAT_PWR_DOWN)) {
5034                                 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
5035                         }
5036
5037                         /* Links status message must follow this format */
5038                         netdev_info(netdev, "igb: %s NIC Link is Down\n",
5039                                netdev->name);
5040                         netif_carrier_off(netdev);
5041
5042                         igb_ping_all_vfs(adapter);
5043
5044                         /* link state has changed, schedule phy info update */
5045                         if (!test_bit(__IGB_DOWN, &adapter->state))
5046                                 mod_timer(&adapter->phy_info_timer,
5047                                           round_jiffies(jiffies + 2 * HZ));
5048
5049                         /* link is down, time to check for alternate media */
5050                         if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5051                                 igb_check_swap_media(adapter);
5052                                 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5053                                         schedule_work(&adapter->reset_task);
5054                                         /* return immediately */
5055                                         return;
5056                                 }
5057                         }
5058                         pm_schedule_suspend(netdev->dev.parent,
5059                                             MSEC_PER_SEC * 5);
5060
5061                 /* also check for alternate media here */
5062                 } else if (!netif_carrier_ok(netdev) &&
5063                            (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
5064                         igb_check_swap_media(adapter);
5065                         if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5066                                 schedule_work(&adapter->reset_task);
5067                                 /* return immediately */
5068                                 return;
5069                         }
5070                 }
5071         }
5072
5073         spin_lock(&adapter->stats64_lock);
5074         igb_update_stats(adapter);
5075         spin_unlock(&adapter->stats64_lock);
5076
5077         for (i = 0; i < adapter->num_tx_queues; i++) {
5078                 struct igb_ring *tx_ring = adapter->tx_ring[i];
5079                 if (!netif_carrier_ok(netdev)) {
5080                         /* We've lost link, so the controller stops DMA,
5081                          * but we've got queued Tx work that's never going
5082                          * to get done, so reset controller to flush Tx.
5083                          * (Do the reset outside of interrupt context).
5084                          */
5085                         if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
5086                                 adapter->tx_timeout_count++;
5087                                 schedule_work(&adapter->reset_task);
5088                                 /* return immediately since reset is imminent */
5089                                 return;
5090                         }
5091                 }
5092
5093                 /* Force detection of hung controller every watchdog period */
5094                 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
5095         }
5096
5097         /* Cause software interrupt to ensure Rx ring is cleaned */
5098         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
5099                 u32 eics = 0;
5100
5101                 for (i = 0; i < adapter->num_q_vectors; i++)
5102                         eics |= adapter->q_vector[i]->eims_value;
5103                 wr32(E1000_EICS, eics);
5104         } else {
5105                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
5106         }
5107
5108         igb_spoof_check(adapter);
5109         igb_ptp_rx_hang(adapter);
5110         igb_ptp_tx_hang(adapter);
5111
5112         /* Check LVMMC register on i350/i354 only */
5113         if ((adapter->hw.mac.type == e1000_i350) ||
5114             (adapter->hw.mac.type == e1000_i354))
5115                 igb_check_lvmmc(adapter);
5116
5117         /* Reset the timer */
5118         if (!test_bit(__IGB_DOWN, &adapter->state)) {
5119                 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
5120                         mod_timer(&adapter->watchdog_timer,
5121                                   round_jiffies(jiffies +  HZ));
5122                 else
5123                         mod_timer(&adapter->watchdog_timer,
5124                                   round_jiffies(jiffies + 2 * HZ));
5125         }
5126 }
5127
5128 enum latency_range {
5129         lowest_latency = 0,
5130         low_latency = 1,
5131         bulk_latency = 2,
5132         latency_invalid = 255
5133 };
5134
5135 /**
5136  *  igb_update_ring_itr - update the dynamic ITR value based on packet size
5137  *  @q_vector: pointer to q_vector
5138  *
5139  *  Stores a new ITR value based on strictly on packet size.  This
5140  *  algorithm is less sophisticated than that used in igb_update_itr,
5141  *  due to the difficulty of synchronizing statistics across multiple
5142  *  receive rings.  The divisors and thresholds used by this function
5143  *  were determined based on theoretical maximum wire speed and testing
5144  *  data, in order to minimize response time while increasing bulk
5145  *  throughput.
5146  *  This functionality is controlled by ethtool's coalescing settings.
5147  *  NOTE:  This function is called only when operating in a multiqueue
5148  *         receive environment.
5149  **/
5150 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
5151 {
5152         int new_val = q_vector->itr_val;
5153         int avg_wire_size = 0;
5154         struct igb_adapter *adapter = q_vector->adapter;
5155         unsigned int packets;
5156
5157         /* For non-gigabit speeds, just fix the interrupt rate at 4000
5158          * ints/sec - ITR timer value of 120 ticks.
5159          */
5160         if (adapter->link_speed != SPEED_1000) {
5161                 new_val = IGB_4K_ITR;
5162                 goto set_itr_val;
5163         }
5164
5165         packets = q_vector->rx.total_packets;
5166         if (packets)
5167                 avg_wire_size = q_vector->rx.total_bytes / packets;
5168
5169         packets = q_vector->tx.total_packets;
5170         if (packets)
5171                 avg_wire_size = max_t(u32, avg_wire_size,
5172                                       q_vector->tx.total_bytes / packets);
5173
5174         /* if avg_wire_size isn't set no work was done */
5175         if (!avg_wire_size)
5176                 goto clear_counts;
5177
5178         /* Add 24 bytes to size to account for CRC, preamble, and gap */
5179         avg_wire_size += 24;
5180
5181         /* Don't starve jumbo frames */
5182         avg_wire_size = min(avg_wire_size, 3000);
5183
5184         /* Give a little boost to mid-size frames */
5185         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
5186                 new_val = avg_wire_size / 3;
5187         else
5188                 new_val = avg_wire_size / 2;
5189
5190         /* conservative mode (itr 3) eliminates the lowest_latency setting */
5191         if (new_val < IGB_20K_ITR &&
5192             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5193              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5194                 new_val = IGB_20K_ITR;
5195
5196 set_itr_val:
5197         if (new_val != q_vector->itr_val) {
5198                 q_vector->itr_val = new_val;
5199                 q_vector->set_itr = 1;
5200         }
5201 clear_counts:
5202         q_vector->rx.total_bytes = 0;
5203         q_vector->rx.total_packets = 0;
5204         q_vector->tx.total_bytes = 0;
5205         q_vector->tx.total_packets = 0;
5206 }
5207
5208 /**
5209  *  igb_update_itr - update the dynamic ITR value based on statistics
5210  *  @q_vector: pointer to q_vector
5211  *  @ring_container: ring info to update the itr for
5212  *
5213  *  Stores a new ITR value based on packets and byte
5214  *  counts during the last interrupt.  The advantage of per interrupt
5215  *  computation is faster updates and more accurate ITR for the current
5216  *  traffic pattern.  Constants in this function were computed
5217  *  based on theoretical maximum wire speed and thresholds were set based
5218  *  on testing data as well as attempting to minimize response time
5219  *  while increasing bulk throughput.
5220  *  This functionality is controlled by ethtool's coalescing settings.
5221  *  NOTE:  These calculations are only valid when operating in a single-
5222  *         queue environment.
5223  **/
5224 static void igb_update_itr(struct igb_q_vector *q_vector,
5225                            struct igb_ring_container *ring_container)
5226 {
5227         unsigned int packets = ring_container->total_packets;
5228         unsigned int bytes = ring_container->total_bytes;
5229         u8 itrval = ring_container->itr;
5230
5231         /* no packets, exit with status unchanged */
5232         if (packets == 0)
5233                 return;
5234
5235         switch (itrval) {
5236         case lowest_latency:
5237                 /* handle TSO and jumbo frames */
5238                 if (bytes/packets > 8000)
5239                         itrval = bulk_latency;
5240                 else if ((packets < 5) && (bytes > 512))
5241                         itrval = low_latency;
5242                 break;
5243         case low_latency:  /* 50 usec aka 20000 ints/s */
5244                 if (bytes > 10000) {
5245                         /* this if handles the TSO accounting */
5246                         if (bytes/packets > 8000)
5247                                 itrval = bulk_latency;
5248                         else if ((packets < 10) || ((bytes/packets) > 1200))
5249                                 itrval = bulk_latency;
5250                         else if ((packets > 35))
5251                                 itrval = lowest_latency;
5252                 } else if (bytes/packets > 2000) {
5253                         itrval = bulk_latency;
5254                 } else if (packets <= 2 && bytes < 512) {
5255                         itrval = lowest_latency;
5256                 }
5257                 break;
5258         case bulk_latency: /* 250 usec aka 4000 ints/s */
5259                 if (bytes > 25000) {
5260                         if (packets > 35)
5261                                 itrval = low_latency;
5262                 } else if (bytes < 1500) {
5263                         itrval = low_latency;
5264                 }
5265                 break;
5266         }
5267
5268         /* clear work counters since we have the values we need */
5269         ring_container->total_bytes = 0;
5270         ring_container->total_packets = 0;
5271
5272         /* write updated itr to ring container */
5273         ring_container->itr = itrval;
5274 }
5275
5276 static void igb_set_itr(struct igb_q_vector *q_vector)
5277 {
5278         struct igb_adapter *adapter = q_vector->adapter;
5279         u32 new_itr = q_vector->itr_val;
5280         u8 current_itr = 0;
5281
5282         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
5283         if (adapter->link_speed != SPEED_1000) {
5284                 current_itr = 0;
5285                 new_itr = IGB_4K_ITR;
5286                 goto set_itr_now;
5287         }
5288
5289         igb_update_itr(q_vector, &q_vector->tx);
5290         igb_update_itr(q_vector, &q_vector->rx);
5291
5292         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
5293
5294         /* conservative mode (itr 3) eliminates the lowest_latency setting */
5295         if (current_itr == lowest_latency &&
5296             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5297              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5298                 current_itr = low_latency;
5299
5300         switch (current_itr) {
5301         /* counts and packets in update_itr are dependent on these numbers */
5302         case lowest_latency:
5303                 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
5304                 break;
5305         case low_latency:
5306                 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
5307                 break;
5308         case bulk_latency:
5309                 new_itr = IGB_4K_ITR;  /* 4,000 ints/sec */
5310                 break;
5311         default:
5312                 break;
5313         }
5314
5315 set_itr_now:
5316         if (new_itr != q_vector->itr_val) {
5317                 /* this attempts to bias the interrupt rate towards Bulk
5318                  * by adding intermediate steps when interrupt rate is
5319                  * increasing
5320                  */
5321                 new_itr = new_itr > q_vector->itr_val ?
5322                           max((new_itr * q_vector->itr_val) /
5323                           (new_itr + (q_vector->itr_val >> 2)),
5324                           new_itr) : new_itr;
5325                 /* Don't write the value here; it resets the adapter's
5326                  * internal timer, and causes us to delay far longer than
5327                  * we should between interrupts.  Instead, we write the ITR
5328                  * value at the beginning of the next interrupt so the timing
5329                  * ends up being correct.
5330                  */
5331                 q_vector->itr_val = new_itr;
5332                 q_vector->set_itr = 1;
5333         }
5334 }
5335
5336 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
5337                             u32 type_tucmd, u32 mss_l4len_idx)
5338 {
5339         struct e1000_adv_tx_context_desc *context_desc;
5340         u16 i = tx_ring->next_to_use;
5341
5342         context_desc = IGB_TX_CTXTDESC(tx_ring, i);
5343
5344         i++;
5345         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
5346
5347         /* set bits to identify this as an advanced context descriptor */
5348         type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
5349
5350         /* For 82575, context index must be unique per ring. */
5351         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
5352                 mss_l4len_idx |= tx_ring->reg_idx << 4;
5353
5354         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
5355         context_desc->seqnum_seed       = 0;
5356         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
5357         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
5358 }
5359
5360 static int igb_tso(struct igb_ring *tx_ring,
5361                    struct igb_tx_buffer *first,
5362                    u8 *hdr_len)
5363 {
5364         u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
5365         struct sk_buff *skb = first->skb;
5366         union {
5367                 struct iphdr *v4;
5368                 struct ipv6hdr *v6;
5369                 unsigned char *hdr;
5370         } ip;
5371         union {
5372                 struct tcphdr *tcp;
5373                 unsigned char *hdr;
5374         } l4;
5375         u32 paylen, l4_offset;
5376         int err;
5377
5378         if (skb->ip_summed != CHECKSUM_PARTIAL)
5379                 return 0;
5380
5381         if (!skb_is_gso(skb))
5382                 return 0;
5383
5384         err = skb_cow_head(skb, 0);
5385         if (err < 0)
5386                 return err;
5387
5388         ip.hdr = skb_network_header(skb);
5389         l4.hdr = skb_checksum_start(skb);
5390
5391         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5392         type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
5393
5394         /* initialize outer IP header fields */
5395         if (ip.v4->version == 4) {
5396                 unsigned char *csum_start = skb_checksum_start(skb);
5397                 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
5398
5399                 /* IP header will have to cancel out any data that
5400                  * is not a part of the outer IP header
5401                  */
5402                 ip.v4->check = csum_fold(csum_partial(trans_start,
5403                                                       csum_start - trans_start,
5404                                                       0));
5405                 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
5406
5407                 ip.v4->tot_len = 0;
5408                 first->tx_flags |= IGB_TX_FLAGS_TSO |
5409                                    IGB_TX_FLAGS_CSUM |
5410                                    IGB_TX_FLAGS_IPV4;
5411         } else {
5412                 ip.v6->payload_len = 0;
5413                 first->tx_flags |= IGB_TX_FLAGS_TSO |
5414                                    IGB_TX_FLAGS_CSUM;
5415         }
5416
5417         /* determine offset of inner transport header */
5418         l4_offset = l4.hdr - skb->data;
5419
5420         /* compute length of segmentation header */
5421         *hdr_len = (l4.tcp->doff * 4) + l4_offset;
5422
5423         /* remove payload length from inner checksum */
5424         paylen = skb->len - l4_offset;
5425         csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
5426
5427         /* update gso size and bytecount with header size */
5428         first->gso_segs = skb_shinfo(skb)->gso_segs;
5429         first->bytecount += (first->gso_segs - 1) * *hdr_len;
5430
5431         /* MSS L4LEN IDX */
5432         mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT;
5433         mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
5434
5435         /* VLAN MACLEN IPLEN */
5436         vlan_macip_lens = l4.hdr - ip.hdr;
5437         vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT;
5438         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
5439
5440         igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
5441
5442         return 1;
5443 }
5444
5445 static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb)
5446 {
5447         unsigned int offset = 0;
5448
5449         ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
5450
5451         return offset == skb_checksum_start_offset(skb);
5452 }
5453
5454 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
5455 {
5456         struct sk_buff *skb = first->skb;
5457         u32 vlan_macip_lens = 0;
5458         u32 type_tucmd = 0;
5459
5460         if (skb->ip_summed != CHECKSUM_PARTIAL) {
5461 csum_failed:
5462                 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
5463                         return;
5464                 goto no_csum;
5465         }
5466
5467         switch (skb->csum_offset) {
5468         case offsetof(struct tcphdr, check):
5469                 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
5470                 /* fall through */
5471         case offsetof(struct udphdr, check):
5472                 break;
5473         case offsetof(struct sctphdr, checksum):
5474                 /* validate that this is actually an SCTP request */
5475                 if (((first->protocol == htons(ETH_P_IP)) &&
5476                      (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
5477                     ((first->protocol == htons(ETH_P_IPV6)) &&
5478                      igb_ipv6_csum_is_sctp(skb))) {
5479                         type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP;
5480                         break;
5481                 }
5482         default:
5483                 skb_checksum_help(skb);
5484                 goto csum_failed;
5485         }
5486
5487         /* update TX checksum flag */
5488         first->tx_flags |= IGB_TX_FLAGS_CSUM;
5489         vlan_macip_lens = skb_checksum_start_offset(skb) -
5490                           skb_network_offset(skb);
5491 no_csum:
5492         vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
5493         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
5494
5495         igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, 0);
5496 }
5497
5498 #define IGB_SET_FLAG(_input, _flag, _result) \
5499         ((_flag <= _result) ? \
5500          ((u32)(_input & _flag) * (_result / _flag)) : \
5501          ((u32)(_input & _flag) / (_flag / _result)))
5502
5503 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
5504 {
5505         /* set type for advanced descriptor with frame checksum insertion */
5506         u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
5507                        E1000_ADVTXD_DCMD_DEXT |
5508                        E1000_ADVTXD_DCMD_IFCS;
5509
5510         /* set HW vlan bit if vlan is present */
5511         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
5512                                  (E1000_ADVTXD_DCMD_VLE));
5513
5514         /* set segmentation bits for TSO */
5515         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
5516                                  (E1000_ADVTXD_DCMD_TSE));
5517
5518         /* set timestamp bit if present */
5519         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
5520                                  (E1000_ADVTXD_MAC_TSTAMP));
5521
5522         /* insert frame checksum */
5523         cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
5524
5525         return cmd_type;
5526 }
5527
5528 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
5529                                  union e1000_adv_tx_desc *tx_desc,
5530                                  u32 tx_flags, unsigned int paylen)
5531 {
5532         u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
5533
5534         /* 82575 requires a unique index per ring */
5535         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
5536                 olinfo_status |= tx_ring->reg_idx << 4;
5537
5538         /* insert L4 checksum */
5539         olinfo_status |= IGB_SET_FLAG(tx_flags,
5540                                       IGB_TX_FLAGS_CSUM,
5541                                       (E1000_TXD_POPTS_TXSM << 8));
5542
5543         /* insert IPv4 checksum */
5544         olinfo_status |= IGB_SET_FLAG(tx_flags,
5545                                       IGB_TX_FLAGS_IPV4,
5546                                       (E1000_TXD_POPTS_IXSM << 8));
5547
5548         tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5549 }
5550
5551 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
5552 {
5553         struct net_device *netdev = tx_ring->netdev;
5554
5555         netif_stop_subqueue(netdev, tx_ring->queue_index);
5556
5557         /* Herbert's original patch had:
5558          *  smp_mb__after_netif_stop_queue();
5559          * but since that doesn't exist yet, just open code it.
5560          */
5561         smp_mb();
5562
5563         /* We need to check again in a case another CPU has just
5564          * made room available.
5565          */
5566         if (igb_desc_unused(tx_ring) < size)
5567                 return -EBUSY;
5568
5569         /* A reprieve! */
5570         netif_wake_subqueue(netdev, tx_ring->queue_index);
5571
5572         u64_stats_update_begin(&tx_ring->tx_syncp2);
5573         tx_ring->tx_stats.restart_queue2++;
5574         u64_stats_update_end(&tx_ring->tx_syncp2);
5575
5576         return 0;
5577 }
5578
5579 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
5580 {
5581         if (igb_desc_unused(tx_ring) >= size)
5582                 return 0;
5583         return __igb_maybe_stop_tx(tx_ring, size);
5584 }
5585
5586 static int igb_tx_map(struct igb_ring *tx_ring,
5587                       struct igb_tx_buffer *first,
5588                       const u8 hdr_len)
5589 {
5590         struct sk_buff *skb = first->skb;
5591         struct igb_tx_buffer *tx_buffer;
5592         union e1000_adv_tx_desc *tx_desc;
5593         struct skb_frag_struct *frag;
5594         dma_addr_t dma;
5595         unsigned int data_len, size;
5596         u32 tx_flags = first->tx_flags;
5597         u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
5598         u16 i = tx_ring->next_to_use;
5599
5600         tx_desc = IGB_TX_DESC(tx_ring, i);
5601
5602         igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
5603
5604         size = skb_headlen(skb);
5605         data_len = skb->data_len;
5606
5607         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
5608
5609         tx_buffer = first;
5610
5611         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
5612                 if (dma_mapping_error(tx_ring->dev, dma))
5613                         goto dma_error;
5614
5615                 /* record length, and DMA address */
5616                 dma_unmap_len_set(tx_buffer, len, size);
5617                 dma_unmap_addr_set(tx_buffer, dma, dma);
5618
5619                 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5620
5621                 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
5622                         tx_desc->read.cmd_type_len =
5623                                 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
5624
5625                         i++;
5626                         tx_desc++;
5627                         if (i == tx_ring->count) {
5628                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
5629                                 i = 0;
5630                         }
5631                         tx_desc->read.olinfo_status = 0;
5632
5633                         dma += IGB_MAX_DATA_PER_TXD;
5634                         size -= IGB_MAX_DATA_PER_TXD;
5635
5636                         tx_desc->read.buffer_addr = cpu_to_le64(dma);
5637                 }
5638
5639                 if (likely(!data_len))
5640                         break;
5641
5642                 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
5643
5644                 i++;
5645                 tx_desc++;
5646                 if (i == tx_ring->count) {
5647                         tx_desc = IGB_TX_DESC(tx_ring, 0);
5648                         i = 0;
5649                 }
5650                 tx_desc->read.olinfo_status = 0;
5651
5652                 size = skb_frag_size(frag);
5653                 data_len -= size;
5654
5655                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
5656                                        size, DMA_TO_DEVICE);
5657
5658                 tx_buffer = &tx_ring->tx_buffer_info[i];
5659         }
5660
5661         /* write last descriptor with RS and EOP bits */
5662         cmd_type |= size | IGB_TXD_DCMD;
5663         tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
5664
5665         netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
5666
5667         /* set the timestamp */
5668         first->time_stamp = jiffies;
5669
5670         /* Force memory writes to complete before letting h/w know there
5671          * are new descriptors to fetch.  (Only applicable for weak-ordered
5672          * memory model archs, such as IA-64).
5673          *
5674          * We also need this memory barrier to make certain all of the
5675          * status bits have been updated before next_to_watch is written.
5676          */
5677         wmb();
5678
5679         /* set next_to_watch value indicating a packet is present */
5680         first->next_to_watch = tx_desc;
5681
5682         i++;
5683         if (i == tx_ring->count)
5684                 i = 0;
5685
5686         tx_ring->next_to_use = i;
5687
5688         /* Make sure there is space in the ring for the next send. */
5689         igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
5690
5691         if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
5692                 writel(i, tx_ring->tail);
5693
5694                 /* we need this if more than one processor can write to our tail
5695                  * at a time, it synchronizes IO on IA64/Altix systems
5696                  */
5697                 mmiowb();
5698         }
5699         return 0;
5700
5701 dma_error:
5702         dev_err(tx_ring->dev, "TX DMA map failed\n");
5703         tx_buffer = &tx_ring->tx_buffer_info[i];
5704
5705         /* clear dma mappings for failed tx_buffer_info map */
5706         while (tx_buffer != first) {
5707                 if (dma_unmap_len(tx_buffer, len))
5708                         dma_unmap_page(tx_ring->dev,
5709                                        dma_unmap_addr(tx_buffer, dma),
5710                                        dma_unmap_len(tx_buffer, len),
5711                                        DMA_TO_DEVICE);
5712                 dma_unmap_len_set(tx_buffer, len, 0);
5713
5714                 if (i-- == 0)
5715                         i += tx_ring->count;
5716                 tx_buffer = &tx_ring->tx_buffer_info[i];
5717         }
5718
5719         if (dma_unmap_len(tx_buffer, len))
5720                 dma_unmap_single(tx_ring->dev,
5721                                  dma_unmap_addr(tx_buffer, dma),
5722                                  dma_unmap_len(tx_buffer, len),
5723                                  DMA_TO_DEVICE);
5724         dma_unmap_len_set(tx_buffer, len, 0);
5725
5726         dev_kfree_skb_any(tx_buffer->skb);
5727         tx_buffer->skb = NULL;
5728
5729         tx_ring->next_to_use = i;
5730
5731         return -1;
5732 }
5733
5734 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
5735                                 struct igb_ring *tx_ring)
5736 {
5737         struct igb_tx_buffer *first;
5738         int tso;
5739         u32 tx_flags = 0;
5740         unsigned short f;
5741         u16 count = TXD_USE_COUNT(skb_headlen(skb));
5742         __be16 protocol = vlan_get_protocol(skb);
5743         u8 hdr_len = 0;
5744
5745         /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
5746          *       + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
5747          *       + 2 desc gap to keep tail from touching head,
5748          *       + 1 desc for context descriptor,
5749          * otherwise try next time
5750          */
5751         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5752                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5753
5754         if (igb_maybe_stop_tx(tx_ring, count + 3)) {
5755                 /* this is a hard error */
5756                 return NETDEV_TX_BUSY;
5757         }
5758
5759         /* record the location of the first descriptor for this packet */
5760         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5761         first->skb = skb;
5762         first->bytecount = skb->len;
5763         first->gso_segs = 1;
5764
5765         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5766                 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
5767
5768                 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
5769                     !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5770                                            &adapter->state)) {
5771                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5772                         tx_flags |= IGB_TX_FLAGS_TSTAMP;
5773
5774                         adapter->ptp_tx_skb = skb_get(skb);
5775                         adapter->ptp_tx_start = jiffies;
5776                         if (adapter->hw.mac.type == e1000_82576)
5777                                 schedule_work(&adapter->ptp_tx_work);
5778                 } else {
5779                         adapter->tx_hwtstamp_skipped++;
5780                 }
5781         }
5782
5783         skb_tx_timestamp(skb);
5784
5785         if (skb_vlan_tag_present(skb)) {
5786                 tx_flags |= IGB_TX_FLAGS_VLAN;
5787                 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5788         }
5789
5790         /* record initial flags and protocol */
5791         first->tx_flags = tx_flags;
5792         first->protocol = protocol;
5793
5794         tso = igb_tso(tx_ring, first, &hdr_len);
5795         if (tso < 0)
5796                 goto out_drop;
5797         else if (!tso)
5798                 igb_tx_csum(tx_ring, first);
5799
5800         if (igb_tx_map(tx_ring, first, hdr_len))
5801                 goto cleanup_tx_tstamp;
5802
5803         return NETDEV_TX_OK;
5804
5805 out_drop:
5806         dev_kfree_skb_any(first->skb);
5807         first->skb = NULL;
5808 cleanup_tx_tstamp:
5809         if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) {
5810                 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
5811
5812                 dev_kfree_skb_any(adapter->ptp_tx_skb);
5813                 adapter->ptp_tx_skb = NULL;
5814                 if (adapter->hw.mac.type == e1000_82576)
5815                         cancel_work_sync(&adapter->ptp_tx_work);
5816                 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
5817         }
5818
5819         return NETDEV_TX_OK;
5820 }
5821
5822 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5823                                                     struct sk_buff *skb)
5824 {
5825         unsigned int r_idx = skb->queue_mapping;
5826
5827         if (r_idx >= adapter->num_tx_queues)
5828                 r_idx = r_idx % adapter->num_tx_queues;
5829
5830         return adapter->tx_ring[r_idx];
5831 }
5832
5833 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5834                                   struct net_device *netdev)
5835 {
5836         struct igb_adapter *adapter = netdev_priv(netdev);
5837
5838         /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
5839          * in order to meet this minimum size requirement.
5840          */
5841         if (skb_put_padto(skb, 17))
5842                 return NETDEV_TX_OK;
5843
5844         return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
5845 }
5846
5847 /**
5848  *  igb_tx_timeout - Respond to a Tx Hang
5849  *  @netdev: network interface device structure
5850  **/
5851 static void igb_tx_timeout(struct net_device *netdev)
5852 {
5853         struct igb_adapter *adapter = netdev_priv(netdev);
5854         struct e1000_hw *hw = &adapter->hw;
5855
5856         /* Do the reset outside of interrupt context */
5857         adapter->tx_timeout_count++;
5858
5859         if (hw->mac.type >= e1000_82580)
5860                 hw->dev_spec._82575.global_device_reset = true;
5861
5862         schedule_work(&adapter->reset_task);
5863         wr32(E1000_EICS,
5864              (adapter->eims_enable_mask & ~adapter->eims_other));
5865 }
5866
5867 static void igb_reset_task(struct work_struct *work)
5868 {
5869         struct igb_adapter *adapter;
5870         adapter = container_of(work, struct igb_adapter, reset_task);
5871
5872         igb_dump(adapter);
5873         netdev_err(adapter->netdev, "Reset adapter\n");
5874         igb_reinit_locked(adapter);
5875 }
5876
5877 /**
5878  *  igb_get_stats64 - Get System Network Statistics
5879  *  @netdev: network interface device structure
5880  *  @stats: rtnl_link_stats64 pointer
5881  **/
5882 static void igb_get_stats64(struct net_device *netdev,
5883                             struct rtnl_link_stats64 *stats)
5884 {
5885         struct igb_adapter *adapter = netdev_priv(netdev);
5886
5887         spin_lock(&adapter->stats64_lock);
5888         igb_update_stats(adapter);
5889         memcpy(stats, &adapter->stats64, sizeof(*stats));
5890         spin_unlock(&adapter->stats64_lock);
5891 }
5892
5893 /**
5894  *  igb_change_mtu - Change the Maximum Transfer Unit
5895  *  @netdev: network interface device structure
5896  *  @new_mtu: new value for maximum frame size
5897  *
5898  *  Returns 0 on success, negative on failure
5899  **/
5900 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5901 {
5902         struct igb_adapter *adapter = netdev_priv(netdev);
5903         struct pci_dev *pdev = adapter->pdev;
5904         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5905
5906         /* adjust max frame to be at least the size of a standard frame */
5907         if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5908                 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5909
5910         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
5911                 usleep_range(1000, 2000);
5912
5913         /* igb_down has a dependency on max_frame_size */
5914         adapter->max_frame_size = max_frame;
5915
5916         if (netif_running(netdev))
5917                 igb_down(adapter);
5918
5919         dev_info(&pdev->dev, "changing MTU from %d to %d\n",
5920                  netdev->mtu, new_mtu);
5921         netdev->mtu = new_mtu;
5922
5923         if (netif_running(netdev))
5924                 igb_up(adapter);
5925         else
5926                 igb_reset(adapter);
5927
5928         clear_bit(__IGB_RESETTING, &adapter->state);
5929
5930         return 0;
5931 }
5932
5933 /**
5934  *  igb_update_stats - Update the board statistics counters
5935  *  @adapter: board private structure
5936  **/
5937 void igb_update_stats(struct igb_adapter *adapter)
5938 {
5939         struct rtnl_link_stats64 *net_stats = &adapter->stats64;
5940         struct e1000_hw *hw = &adapter->hw;
5941         struct pci_dev *pdev = adapter->pdev;
5942         u32 reg, mpc;
5943         int i;
5944         u64 bytes, packets;
5945         unsigned int start;
5946         u64 _bytes, _packets;
5947
5948         /* Prevent stats update while adapter is being reset, or if the pci
5949          * connection is down.
5950          */
5951         if (adapter->link_speed == 0)
5952                 return;
5953         if (pci_channel_offline(pdev))
5954                 return;
5955
5956         bytes = 0;
5957         packets = 0;
5958
5959         rcu_read_lock();
5960         for (i = 0; i < adapter->num_rx_queues; i++) {
5961                 struct igb_ring *ring = adapter->rx_ring[i];
5962                 u32 rqdpc = rd32(E1000_RQDPC(i));
5963                 if (hw->mac.type >= e1000_i210)
5964                         wr32(E1000_RQDPC(i), 0);
5965
5966                 if (rqdpc) {
5967                         ring->rx_stats.drops += rqdpc;
5968                         net_stats->rx_fifo_errors += rqdpc;
5969                 }
5970
5971                 do {
5972                         start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
5973                         _bytes = ring->rx_stats.bytes;
5974                         _packets = ring->rx_stats.packets;
5975                 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
5976                 bytes += _bytes;
5977                 packets += _packets;
5978         }
5979
5980         net_stats->rx_bytes = bytes;
5981         net_stats->rx_packets = packets;
5982
5983         bytes = 0;
5984         packets = 0;
5985         for (i = 0; i < adapter->num_tx_queues; i++) {
5986                 struct igb_ring *ring = adapter->tx_ring[i];
5987                 do {
5988                         start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
5989                         _bytes = ring->tx_stats.bytes;
5990                         _packets = ring->tx_stats.packets;
5991                 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
5992                 bytes += _bytes;
5993                 packets += _packets;
5994         }
5995         net_stats->tx_bytes = bytes;
5996         net_stats->tx_packets = packets;
5997         rcu_read_unlock();
5998
5999         /* read stats registers */
6000         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
6001         adapter->stats.gprc += rd32(E1000_GPRC);
6002         adapter->stats.gorc += rd32(E1000_GORCL);
6003         rd32(E1000_GORCH); /* clear GORCL */
6004         adapter->stats.bprc += rd32(E1000_BPRC);
6005         adapter->stats.mprc += rd32(E1000_MPRC);
6006         adapter->stats.roc += rd32(E1000_ROC);
6007
6008         adapter->stats.prc64 += rd32(E1000_PRC64);
6009         adapter->stats.prc127 += rd32(E1000_PRC127);
6010         adapter->stats.prc255 += rd32(E1000_PRC255);
6011         adapter->stats.prc511 += rd32(E1000_PRC511);
6012         adapter->stats.prc1023 += rd32(E1000_PRC1023);
6013         adapter->stats.prc1522 += rd32(E1000_PRC1522);
6014         adapter->stats.symerrs += rd32(E1000_SYMERRS);
6015         adapter->stats.sec += rd32(E1000_SEC);
6016
6017         mpc = rd32(E1000_MPC);
6018         adapter->stats.mpc += mpc;
6019         net_stats->rx_fifo_errors += mpc;
6020         adapter->stats.scc += rd32(E1000_SCC);
6021         adapter->stats.ecol += rd32(E1000_ECOL);
6022         adapter->stats.mcc += rd32(E1000_MCC);
6023         adapter->stats.latecol += rd32(E1000_LATECOL);
6024         adapter->stats.dc += rd32(E1000_DC);
6025         adapter->stats.rlec += rd32(E1000_RLEC);
6026         adapter->stats.xonrxc += rd32(E1000_XONRXC);
6027         adapter->stats.xontxc += rd32(E1000_XONTXC);
6028         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
6029         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
6030         adapter->stats.fcruc += rd32(E1000_FCRUC);
6031         adapter->stats.gptc += rd32(E1000_GPTC);
6032         adapter->stats.gotc += rd32(E1000_GOTCL);
6033         rd32(E1000_GOTCH); /* clear GOTCL */
6034         adapter->stats.rnbc += rd32(E1000_RNBC);
6035         adapter->stats.ruc += rd32(E1000_RUC);
6036         adapter->stats.rfc += rd32(E1000_RFC);
6037         adapter->stats.rjc += rd32(E1000_RJC);
6038         adapter->stats.tor += rd32(E1000_TORH);
6039         adapter->stats.tot += rd32(E1000_TOTH);
6040         adapter->stats.tpr += rd32(E1000_TPR);
6041
6042         adapter->stats.ptc64 += rd32(E1000_PTC64);
6043         adapter->stats.ptc127 += rd32(E1000_PTC127);
6044         adapter->stats.ptc255 += rd32(E1000_PTC255);
6045         adapter->stats.ptc511 += rd32(E1000_PTC511);
6046         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
6047         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
6048
6049         adapter->stats.mptc += rd32(E1000_MPTC);
6050         adapter->stats.bptc += rd32(E1000_BPTC);
6051
6052         adapter->stats.tpt += rd32(E1000_TPT);
6053         adapter->stats.colc += rd32(E1000_COLC);
6054
6055         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
6056         /* read internal phy specific stats */
6057         reg = rd32(E1000_CTRL_EXT);
6058         if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
6059                 adapter->stats.rxerrc += rd32(E1000_RXERRC);
6060
6061                 /* this stat has invalid values on i210/i211 */
6062                 if ((hw->mac.type != e1000_i210) &&
6063                     (hw->mac.type != e1000_i211))
6064                         adapter->stats.tncrs += rd32(E1000_TNCRS);
6065         }
6066
6067         adapter->stats.tsctc += rd32(E1000_TSCTC);
6068         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
6069
6070         adapter->stats.iac += rd32(E1000_IAC);
6071         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
6072         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
6073         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
6074         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
6075         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
6076         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
6077         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
6078         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
6079
6080         /* Fill out the OS statistics structure */
6081         net_stats->multicast = adapter->stats.mprc;
6082         net_stats->collisions = adapter->stats.colc;
6083
6084         /* Rx Errors */
6085
6086         /* RLEC on some newer hardware can be incorrect so build
6087          * our own version based on RUC and ROC
6088          */
6089         net_stats->rx_errors = adapter->stats.rxerrc +
6090                 adapter->stats.crcerrs + adapter->stats.algnerrc +
6091                 adapter->stats.ruc + adapter->stats.roc +
6092                 adapter->stats.cexterr;
6093         net_stats->rx_length_errors = adapter->stats.ruc +
6094                                       adapter->stats.roc;
6095         net_stats->rx_crc_errors = adapter->stats.crcerrs;
6096         net_stats->rx_frame_errors = adapter->stats.algnerrc;
6097         net_stats->rx_missed_errors = adapter->stats.mpc;
6098
6099         /* Tx Errors */
6100         net_stats->tx_errors = adapter->stats.ecol +
6101                                adapter->stats.latecol;
6102         net_stats->tx_aborted_errors = adapter->stats.ecol;
6103         net_stats->tx_window_errors = adapter->stats.latecol;
6104         net_stats->tx_carrier_errors = adapter->stats.tncrs;
6105
6106         /* Tx Dropped needs to be maintained elsewhere */
6107
6108         /* Management Stats */
6109         adapter->stats.mgptc += rd32(E1000_MGTPTC);
6110         adapter->stats.mgprc += rd32(E1000_MGTPRC);
6111         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
6112
6113         /* OS2BMC Stats */
6114         reg = rd32(E1000_MANC);
6115         if (reg & E1000_MANC_EN_BMC2OS) {
6116                 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
6117                 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
6118                 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
6119                 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
6120         }
6121 }
6122
6123 static void igb_tsync_interrupt(struct igb_adapter *adapter)
6124 {
6125         struct e1000_hw *hw = &adapter->hw;
6126         struct ptp_clock_event event;
6127         struct timespec64 ts;
6128         u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
6129
6130         if (tsicr & TSINTR_SYS_WRAP) {
6131                 event.type = PTP_CLOCK_PPS;
6132                 if (adapter->ptp_caps.pps)
6133                         ptp_clock_event(adapter->ptp_clock, &event);
6134                 ack |= TSINTR_SYS_WRAP;
6135         }
6136
6137         if (tsicr & E1000_TSICR_TXTS) {
6138                 /* retrieve hardware timestamp */
6139                 schedule_work(&adapter->ptp_tx_work);
6140                 ack |= E1000_TSICR_TXTS;
6141         }
6142
6143         if (tsicr & TSINTR_TT0) {
6144                 spin_lock(&adapter->tmreg_lock);
6145                 ts = timespec64_add(adapter->perout[0].start,
6146                                     adapter->perout[0].period);
6147                 /* u32 conversion of tv_sec is safe until y2106 */
6148                 wr32(E1000_TRGTTIML0, ts.tv_nsec);
6149                 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
6150                 tsauxc = rd32(E1000_TSAUXC);
6151                 tsauxc |= TSAUXC_EN_TT0;
6152                 wr32(E1000_TSAUXC, tsauxc);
6153                 adapter->perout[0].start = ts;
6154                 spin_unlock(&adapter->tmreg_lock);
6155                 ack |= TSINTR_TT0;
6156         }
6157
6158         if (tsicr & TSINTR_TT1) {
6159                 spin_lock(&adapter->tmreg_lock);
6160                 ts = timespec64_add(adapter->perout[1].start,
6161                                     adapter->perout[1].period);
6162                 wr32(E1000_TRGTTIML1, ts.tv_nsec);
6163                 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
6164                 tsauxc = rd32(E1000_TSAUXC);
6165                 tsauxc |= TSAUXC_EN_TT1;
6166                 wr32(E1000_TSAUXC, tsauxc);
6167                 adapter->perout[1].start = ts;
6168                 spin_unlock(&adapter->tmreg_lock);
6169                 ack |= TSINTR_TT1;
6170         }
6171
6172         if (tsicr & TSINTR_AUTT0) {
6173                 nsec = rd32(E1000_AUXSTMPL0);
6174                 sec  = rd32(E1000_AUXSTMPH0);
6175                 event.type = PTP_CLOCK_EXTTS;
6176                 event.index = 0;
6177                 event.timestamp = sec * 1000000000ULL + nsec;
6178                 ptp_clock_event(adapter->ptp_clock, &event);
6179                 ack |= TSINTR_AUTT0;
6180         }
6181
6182         if (tsicr & TSINTR_AUTT1) {
6183                 nsec = rd32(E1000_AUXSTMPL1);
6184                 sec  = rd32(E1000_AUXSTMPH1);
6185                 event.type = PTP_CLOCK_EXTTS;
6186                 event.index = 1;
6187                 event.timestamp = sec * 1000000000ULL + nsec;
6188                 ptp_clock_event(adapter->ptp_clock, &event);
6189                 ack |= TSINTR_AUTT1;
6190         }
6191
6192         /* acknowledge the interrupts */
6193         wr32(E1000_TSICR, ack);
6194 }
6195
6196 static irqreturn_t igb_msix_other(int irq, void *data)
6197 {
6198         struct igb_adapter *adapter = data;
6199         struct e1000_hw *hw = &adapter->hw;
6200         u32 icr = rd32(E1000_ICR);
6201         /* reading ICR causes bit 31 of EICR to be cleared */
6202
6203         if (icr & E1000_ICR_DRSTA)
6204                 schedule_work(&adapter->reset_task);
6205
6206         if (icr & E1000_ICR_DOUTSYNC) {
6207                 /* HW is reporting DMA is out of sync */
6208                 adapter->stats.doosync++;
6209                 /* The DMA Out of Sync is also indication of a spoof event
6210                  * in IOV mode. Check the Wrong VM Behavior register to
6211                  * see if it is really a spoof event.
6212                  */
6213                 igb_check_wvbr(adapter);
6214         }
6215
6216         /* Check for a mailbox event */
6217         if (icr & E1000_ICR_VMMB)
6218                 igb_msg_task(adapter);
6219
6220         if (icr & E1000_ICR_LSC) {
6221                 hw->mac.get_link_status = 1;
6222                 /* guard against interrupt when we're going down */
6223                 if (!test_bit(__IGB_DOWN, &adapter->state))
6224                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
6225         }
6226
6227         if (icr & E1000_ICR_TS)
6228                 igb_tsync_interrupt(adapter);
6229
6230         wr32(E1000_EIMS, adapter->eims_other);
6231
6232         return IRQ_HANDLED;
6233 }
6234
6235 static void igb_write_itr(struct igb_q_vector *q_vector)
6236 {
6237         struct igb_adapter *adapter = q_vector->adapter;
6238         u32 itr_val = q_vector->itr_val & 0x7FFC;
6239
6240         if (!q_vector->set_itr)
6241                 return;
6242
6243         if (!itr_val)
6244                 itr_val = 0x4;
6245
6246         if (adapter->hw.mac.type == e1000_82575)
6247                 itr_val |= itr_val << 16;
6248         else
6249                 itr_val |= E1000_EITR_CNT_IGNR;
6250
6251         writel(itr_val, q_vector->itr_register);
6252         q_vector->set_itr = 0;
6253 }
6254
6255 static irqreturn_t igb_msix_ring(int irq, void *data)
6256 {
6257         struct igb_q_vector *q_vector = data;
6258
6259         /* Write the ITR value calculated from the previous interrupt. */
6260         igb_write_itr(q_vector);
6261
6262         napi_schedule(&q_vector->napi);
6263
6264         return IRQ_HANDLED;
6265 }
6266
6267 #ifdef CONFIG_IGB_DCA
6268 static void igb_update_tx_dca(struct igb_adapter *adapter,
6269                               struct igb_ring *tx_ring,
6270                               int cpu)
6271 {
6272         struct e1000_hw *hw = &adapter->hw;
6273         u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
6274
6275         if (hw->mac.type != e1000_82575)
6276                 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
6277
6278         /* We can enable relaxed ordering for reads, but not writes when
6279          * DCA is enabled.  This is due to a known issue in some chipsets
6280          * which will cause the DCA tag to be cleared.
6281          */
6282         txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
6283                   E1000_DCA_TXCTRL_DATA_RRO_EN |
6284                   E1000_DCA_TXCTRL_DESC_DCA_EN;
6285
6286         wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
6287 }
6288
6289 static void igb_update_rx_dca(struct igb_adapter *adapter,
6290                               struct igb_ring *rx_ring,
6291                               int cpu)
6292 {
6293         struct e1000_hw *hw = &adapter->hw;
6294         u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
6295
6296         if (hw->mac.type != e1000_82575)
6297                 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
6298
6299         /* We can enable relaxed ordering for reads, but not writes when
6300          * DCA is enabled.  This is due to a known issue in some chipsets
6301          * which will cause the DCA tag to be cleared.
6302          */
6303         rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
6304                   E1000_DCA_RXCTRL_DESC_DCA_EN;
6305
6306         wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
6307 }
6308
6309 static void igb_update_dca(struct igb_q_vector *q_vector)
6310 {
6311         struct igb_adapter *adapter = q_vector->adapter;
6312         int cpu = get_cpu();
6313
6314         if (q_vector->cpu == cpu)
6315                 goto out_no_update;
6316
6317         if (q_vector->tx.ring)
6318                 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
6319
6320         if (q_vector->rx.ring)
6321                 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
6322
6323         q_vector->cpu = cpu;
6324 out_no_update:
6325         put_cpu();
6326 }
6327
6328 static void igb_setup_dca(struct igb_adapter *adapter)
6329 {
6330         struct e1000_hw *hw = &adapter->hw;
6331         int i;
6332
6333         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
6334                 return;
6335
6336         /* Always use CB2 mode, difference is masked in the CB driver. */
6337         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
6338
6339         for (i = 0; i < adapter->num_q_vectors; i++) {
6340                 adapter->q_vector[i]->cpu = -1;
6341                 igb_update_dca(adapter->q_vector[i]);
6342         }
6343 }
6344
6345 static int __igb_notify_dca(struct device *dev, void *data)
6346 {
6347         struct net_device *netdev = dev_get_drvdata(dev);
6348         struct igb_adapter *adapter = netdev_priv(netdev);
6349         struct pci_dev *pdev = adapter->pdev;
6350         struct e1000_hw *hw = &adapter->hw;
6351         unsigned long event = *(unsigned long *)data;
6352
6353         switch (event) {
6354         case DCA_PROVIDER_ADD:
6355                 /* if already enabled, don't do it again */
6356                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
6357                         break;
6358                 if (dca_add_requester(dev) == 0) {
6359                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
6360                         dev_info(&pdev->dev, "DCA enabled\n");
6361                         igb_setup_dca(adapter);
6362                         break;
6363                 }
6364                 /* Fall Through since DCA is disabled. */
6365         case DCA_PROVIDER_REMOVE:
6366                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
6367                         /* without this a class_device is left
6368                          * hanging around in the sysfs model
6369                          */
6370                         dca_remove_requester(dev);
6371                         dev_info(&pdev->dev, "DCA disabled\n");
6372                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
6373                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
6374                 }
6375                 break;
6376         }
6377
6378         return 0;
6379 }
6380
6381 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
6382                           void *p)
6383 {
6384         int ret_val;
6385
6386         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
6387                                          __igb_notify_dca);
6388
6389         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6390 }
6391 #endif /* CONFIG_IGB_DCA */
6392
6393 #ifdef CONFIG_PCI_IOV
6394 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
6395 {
6396         unsigned char mac_addr[ETH_ALEN];
6397
6398         eth_zero_addr(mac_addr);
6399         igb_set_vf_mac(adapter, vf, mac_addr);
6400
6401         /* By default spoof check is enabled for all VFs */
6402         adapter->vf_data[vf].spoofchk_enabled = true;
6403
6404         /* By default VFs are not trusted */
6405         adapter->vf_data[vf].trusted = false;
6406
6407         return 0;
6408 }
6409
6410 #endif
6411 static void igb_ping_all_vfs(struct igb_adapter *adapter)
6412 {
6413         struct e1000_hw *hw = &adapter->hw;
6414         u32 ping;
6415         int i;
6416
6417         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
6418                 ping = E1000_PF_CONTROL_MSG;
6419                 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
6420                         ping |= E1000_VT_MSGTYPE_CTS;
6421                 igb_write_mbx(hw, &ping, 1, i);
6422         }
6423 }
6424
6425 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
6426 {
6427         struct e1000_hw *hw = &adapter->hw;
6428         u32 vmolr = rd32(E1000_VMOLR(vf));
6429         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6430
6431         vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
6432                             IGB_VF_FLAG_MULTI_PROMISC);
6433         vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
6434
6435         if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
6436                 vmolr |= E1000_VMOLR_MPME;
6437                 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
6438                 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
6439         } else {
6440                 /* if we have hashes and we are clearing a multicast promisc
6441                  * flag we need to write the hashes to the MTA as this step
6442                  * was previously skipped
6443                  */
6444                 if (vf_data->num_vf_mc_hashes > 30) {
6445                         vmolr |= E1000_VMOLR_MPME;
6446                 } else if (vf_data->num_vf_mc_hashes) {
6447                         int j;
6448
6449                         vmolr |= E1000_VMOLR_ROMPE;
6450                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
6451                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
6452                 }
6453         }
6454
6455         wr32(E1000_VMOLR(vf), vmolr);
6456
6457         /* there are flags left unprocessed, likely not supported */
6458         if (*msgbuf & E1000_VT_MSGINFO_MASK)
6459                 return -EINVAL;
6460
6461         return 0;
6462 }
6463
6464 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
6465                                   u32 *msgbuf, u32 vf)
6466 {
6467         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
6468         u16 *hash_list = (u16 *)&msgbuf[1];
6469         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6470         int i;
6471
6472         /* salt away the number of multicast addresses assigned
6473          * to this VF for later use to restore when the PF multi cast
6474          * list changes
6475          */
6476         vf_data->num_vf_mc_hashes = n;
6477
6478         /* only up to 30 hash values supported */
6479         if (n > 30)
6480                 n = 30;
6481
6482         /* store the hashes for later use */
6483         for (i = 0; i < n; i++)
6484                 vf_data->vf_mc_hashes[i] = hash_list[i];
6485
6486         /* Flush and reset the mta with the new values */
6487         igb_set_rx_mode(adapter->netdev);
6488
6489         return 0;
6490 }
6491
6492 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
6493 {
6494         struct e1000_hw *hw = &adapter->hw;
6495         struct vf_data_storage *vf_data;
6496         int i, j;
6497
6498         for (i = 0; i < adapter->vfs_allocated_count; i++) {
6499                 u32 vmolr = rd32(E1000_VMOLR(i));
6500
6501                 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
6502
6503                 vf_data = &adapter->vf_data[i];
6504
6505                 if ((vf_data->num_vf_mc_hashes > 30) ||
6506                     (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
6507                         vmolr |= E1000_VMOLR_MPME;
6508                 } else if (vf_data->num_vf_mc_hashes) {
6509                         vmolr |= E1000_VMOLR_ROMPE;
6510                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
6511                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
6512                 }
6513                 wr32(E1000_VMOLR(i), vmolr);
6514         }
6515 }
6516
6517 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
6518 {
6519         struct e1000_hw *hw = &adapter->hw;
6520         u32 pool_mask, vlvf_mask, i;
6521
6522         /* create mask for VF and other pools */
6523         pool_mask = E1000_VLVF_POOLSEL_MASK;
6524         vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf);
6525
6526         /* drop PF from pool bits */
6527         pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT +
6528                              adapter->vfs_allocated_count);
6529
6530         /* Find the vlan filter for this id */
6531         for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
6532                 u32 vlvf = rd32(E1000_VLVF(i));
6533                 u32 vfta_mask, vid, vfta;
6534
6535                 /* remove the vf from the pool */
6536                 if (!(vlvf & vlvf_mask))
6537                         continue;
6538
6539                 /* clear out bit from VLVF */
6540                 vlvf ^= vlvf_mask;
6541
6542                 /* if other pools are present, just remove ourselves */
6543                 if (vlvf & pool_mask)
6544                         goto update_vlvfb;
6545
6546                 /* if PF is present, leave VFTA */
6547                 if (vlvf & E1000_VLVF_POOLSEL_MASK)
6548                         goto update_vlvf;
6549
6550                 vid = vlvf & E1000_VLVF_VLANID_MASK;
6551                 vfta_mask = BIT(vid % 32);
6552
6553                 /* clear bit from VFTA */
6554                 vfta = adapter->shadow_vfta[vid / 32];
6555                 if (vfta & vfta_mask)
6556                         hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
6557 update_vlvf:
6558                 /* clear pool selection enable */
6559                 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
6560                         vlvf &= E1000_VLVF_POOLSEL_MASK;
6561                 else
6562                         vlvf = 0;
6563 update_vlvfb:
6564                 /* clear pool bits */
6565                 wr32(E1000_VLVF(i), vlvf);
6566         }
6567 }
6568
6569 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
6570 {
6571         u32 vlvf;
6572         int idx;
6573
6574         /* short cut the special case */
6575         if (vlan == 0)
6576                 return 0;
6577
6578         /* Search for the VLAN id in the VLVF entries */
6579         for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
6580                 vlvf = rd32(E1000_VLVF(idx));
6581                 if ((vlvf & VLAN_VID_MASK) == vlan)
6582                         break;
6583         }
6584
6585         return idx;
6586 }
6587
6588 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
6589 {
6590         struct e1000_hw *hw = &adapter->hw;
6591         u32 bits, pf_id;
6592         int idx;
6593
6594         idx = igb_find_vlvf_entry(hw, vid);
6595         if (!idx)
6596                 return;
6597
6598         /* See if any other pools are set for this VLAN filter
6599          * entry other than the PF.
6600          */
6601         pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
6602         bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK;
6603         bits &= rd32(E1000_VLVF(idx));
6604
6605         /* Disable the filter so this falls into the default pool. */
6606         if (!bits) {
6607                 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
6608                         wr32(E1000_VLVF(idx), BIT(pf_id));
6609                 else
6610                         wr32(E1000_VLVF(idx), 0);
6611         }
6612 }
6613
6614 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
6615                            bool add, u32 vf)
6616 {
6617         int pf_id = adapter->vfs_allocated_count;
6618         struct e1000_hw *hw = &adapter->hw;
6619         int err;
6620
6621         /* If VLAN overlaps with one the PF is currently monitoring make
6622          * sure that we are able to allocate a VLVF entry.  This may be
6623          * redundant but it guarantees PF will maintain visibility to
6624          * the VLAN.
6625          */
6626         if (add && test_bit(vid, adapter->active_vlans)) {
6627                 err = igb_vfta_set(hw, vid, pf_id, true, false);
6628                 if (err)
6629                         return err;
6630         }
6631
6632         err = igb_vfta_set(hw, vid, vf, add, false);
6633
6634         if (add && !err)
6635                 return err;
6636
6637         /* If we failed to add the VF VLAN or we are removing the VF VLAN
6638          * we may need to drop the PF pool bit in order to allow us to free
6639          * up the VLVF resources.
6640          */
6641         if (test_bit(vid, adapter->active_vlans) ||
6642             (adapter->flags & IGB_FLAG_VLAN_PROMISC))
6643                 igb_update_pf_vlvf(adapter, vid);
6644
6645         return err;
6646 }
6647
6648 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
6649 {
6650         struct e1000_hw *hw = &adapter->hw;
6651
6652         if (vid)
6653                 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
6654         else
6655                 wr32(E1000_VMVIR(vf), 0);
6656 }
6657
6658 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
6659                                 u16 vlan, u8 qos)
6660 {
6661         int err;
6662
6663         err = igb_set_vf_vlan(adapter, vlan, true, vf);
6664         if (err)
6665                 return err;
6666
6667         igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
6668         igb_set_vmolr(adapter, vf, !vlan);
6669
6670         /* revoke access to previous VLAN */
6671         if (vlan != adapter->vf_data[vf].pf_vlan)
6672                 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6673                                 false, vf);
6674
6675         adapter->vf_data[vf].pf_vlan = vlan;
6676         adapter->vf_data[vf].pf_qos = qos;
6677         igb_set_vf_vlan_strip(adapter, vf, true);
6678         dev_info(&adapter->pdev->dev,
6679                  "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
6680         if (test_bit(__IGB_DOWN, &adapter->state)) {
6681                 dev_warn(&adapter->pdev->dev,
6682                          "The VF VLAN has been set, but the PF device is not up.\n");
6683                 dev_warn(&adapter->pdev->dev,
6684                          "Bring the PF device up before attempting to use the VF device.\n");
6685         }
6686
6687         return err;
6688 }
6689
6690 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
6691 {
6692         /* Restore tagless access via VLAN 0 */
6693         igb_set_vf_vlan(adapter, 0, true, vf);
6694
6695         igb_set_vmvir(adapter, 0, vf);
6696         igb_set_vmolr(adapter, vf, true);
6697
6698         /* Remove any PF assigned VLAN */
6699         if (adapter->vf_data[vf].pf_vlan)
6700                 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6701                                 false, vf);
6702
6703         adapter->vf_data[vf].pf_vlan = 0;
6704         adapter->vf_data[vf].pf_qos = 0;
6705         igb_set_vf_vlan_strip(adapter, vf, false);
6706
6707         return 0;
6708 }
6709
6710 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf,
6711                                u16 vlan, u8 qos, __be16 vlan_proto)
6712 {
6713         struct igb_adapter *adapter = netdev_priv(netdev);
6714
6715         if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
6716                 return -EINVAL;
6717
6718         if (vlan_proto != htons(ETH_P_8021Q))
6719                 return -EPROTONOSUPPORT;
6720
6721         return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
6722                                igb_disable_port_vlan(adapter, vf);
6723 }
6724
6725 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
6726 {
6727         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
6728         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6729         int ret;
6730
6731         if (adapter->vf_data[vf].pf_vlan)
6732                 return -1;
6733
6734         /* VLAN 0 is a special case, don't allow it to be removed */
6735         if (!vid && !add)
6736                 return 0;
6737
6738         ret = igb_set_vf_vlan(adapter, vid, !!add, vf);
6739         if (!ret)
6740                 igb_set_vf_vlan_strip(adapter, vf, !!vid);
6741         return ret;
6742 }
6743
6744 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
6745 {
6746         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6747
6748         /* clear flags - except flag that indicates PF has set the MAC */
6749         vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
6750         vf_data->last_nack = jiffies;
6751
6752         /* reset vlans for device */
6753         igb_clear_vf_vfta(adapter, vf);
6754         igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
6755         igb_set_vmvir(adapter, vf_data->pf_vlan |
6756                                (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
6757         igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
6758         igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan));
6759
6760         /* reset multicast table array for vf */
6761         adapter->vf_data[vf].num_vf_mc_hashes = 0;
6762
6763         /* Flush and reset the mta with the new values */
6764         igb_set_rx_mode(adapter->netdev);
6765 }
6766
6767 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6768 {
6769         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6770
6771         /* clear mac address as we were hotplug removed/added */
6772         if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
6773                 eth_zero_addr(vf_mac);
6774
6775         /* process remaining reset events */
6776         igb_vf_reset(adapter, vf);
6777 }
6778
6779 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
6780 {
6781         struct e1000_hw *hw = &adapter->hw;
6782         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6783         u32 reg, msgbuf[3];
6784         u8 *addr = (u8 *)(&msgbuf[1]);
6785
6786         /* process all the same items cleared in a function level reset */
6787         igb_vf_reset(adapter, vf);
6788
6789         /* set vf mac address */
6790         igb_set_vf_mac(adapter, vf, vf_mac);
6791
6792         /* enable transmit and receive for vf */
6793         reg = rd32(E1000_VFTE);
6794         wr32(E1000_VFTE, reg | BIT(vf));
6795         reg = rd32(E1000_VFRE);
6796         wr32(E1000_VFRE, reg | BIT(vf));
6797
6798         adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
6799
6800         /* reply to reset with ack and vf mac address */
6801         if (!is_zero_ether_addr(vf_mac)) {
6802                 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6803                 memcpy(addr, vf_mac, ETH_ALEN);
6804         } else {
6805                 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6806         }
6807         igb_write_mbx(hw, msgbuf, 3, vf);
6808 }
6809
6810 static void igb_flush_mac_table(struct igb_adapter *adapter)
6811 {
6812         struct e1000_hw *hw = &adapter->hw;
6813         int i;
6814
6815         for (i = 0; i < hw->mac.rar_entry_count; i++) {
6816                 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE;
6817                 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
6818                 adapter->mac_table[i].queue = 0;
6819                 igb_rar_set_index(adapter, i);
6820         }
6821 }
6822
6823 static int igb_available_rars(struct igb_adapter *adapter, u8 queue)
6824 {
6825         struct e1000_hw *hw = &adapter->hw;
6826         /* do not count rar entries reserved for VFs MAC addresses */
6827         int rar_entries = hw->mac.rar_entry_count -
6828                           adapter->vfs_allocated_count;
6829         int i, count = 0;
6830
6831         for (i = 0; i < rar_entries; i++) {
6832                 /* do not count default entries */
6833                 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT)
6834                         continue;
6835
6836                 /* do not count "in use" entries for different queues */
6837                 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) &&
6838                     (adapter->mac_table[i].queue != queue))
6839                         continue;
6840
6841                 count++;
6842         }
6843
6844         return count;
6845 }
6846
6847 /* Set default MAC address for the PF in the first RAR entry */
6848 static void igb_set_default_mac_filter(struct igb_adapter *adapter)
6849 {
6850         struct igb_mac_addr *mac_table = &adapter->mac_table[0];
6851
6852         ether_addr_copy(mac_table->addr, adapter->hw.mac.addr);
6853         mac_table->queue = adapter->vfs_allocated_count;
6854         mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
6855
6856         igb_rar_set_index(adapter, 0);
6857 }
6858
6859 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr,
6860                               const u8 queue)
6861 {
6862         struct e1000_hw *hw = &adapter->hw;
6863         int rar_entries = hw->mac.rar_entry_count -
6864                           adapter->vfs_allocated_count;
6865         int i;
6866
6867         if (is_zero_ether_addr(addr))
6868                 return -EINVAL;
6869
6870         /* Search for the first empty entry in the MAC table.
6871          * Do not touch entries at the end of the table reserved for the VF MAC
6872          * addresses.
6873          */
6874         for (i = 0; i < rar_entries; i++) {
6875                 if (adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)
6876                         continue;
6877
6878                 ether_addr_copy(adapter->mac_table[i].addr, addr);
6879                 adapter->mac_table[i].queue = queue;
6880                 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE;
6881
6882                 igb_rar_set_index(adapter, i);
6883                 return i;
6884         }
6885
6886         return -ENOSPC;
6887 }
6888
6889 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr,
6890                               const u8 queue)
6891 {
6892         struct e1000_hw *hw = &adapter->hw;
6893         int rar_entries = hw->mac.rar_entry_count -
6894                           adapter->vfs_allocated_count;
6895         int i;
6896
6897         if (is_zero_ether_addr(addr))
6898                 return -EINVAL;
6899
6900         /* Search for matching entry in the MAC table based on given address
6901          * and queue. Do not touch entries at the end of the table reserved
6902          * for the VF MAC addresses.
6903          */
6904         for (i = 0; i < rar_entries; i++) {
6905                 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE))
6906                         continue;
6907                 if (adapter->mac_table[i].queue != queue)
6908                         continue;
6909                 if (!ether_addr_equal(adapter->mac_table[i].addr, addr))
6910                         continue;
6911
6912                 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE;
6913                 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
6914                 adapter->mac_table[i].queue = 0;
6915
6916                 igb_rar_set_index(adapter, i);
6917                 return 0;
6918         }
6919
6920         return -ENOENT;
6921 }
6922
6923 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr)
6924 {
6925         struct igb_adapter *adapter = netdev_priv(netdev);
6926         int ret;
6927
6928         ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count);
6929
6930         return min_t(int, ret, 0);
6931 }
6932
6933 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr)
6934 {
6935         struct igb_adapter *adapter = netdev_priv(netdev);
6936
6937         igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count);
6938
6939         return 0;
6940 }
6941
6942 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf,
6943                                  const u32 info, const u8 *addr)
6944 {
6945         struct pci_dev *pdev = adapter->pdev;
6946         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6947         struct list_head *pos;
6948         struct vf_mac_filter *entry = NULL;
6949         int ret = 0;
6950
6951         switch (info) {
6952         case E1000_VF_MAC_FILTER_CLR:
6953                 /* remove all unicast MAC filters related to the current VF */
6954                 list_for_each(pos, &adapter->vf_macs.l) {
6955                         entry = list_entry(pos, struct vf_mac_filter, l);
6956                         if (entry->vf == vf) {
6957                                 entry->vf = -1;
6958                                 entry->free = true;
6959                                 igb_del_mac_filter(adapter, entry->vf_mac, vf);
6960                         }
6961                 }
6962                 break;
6963         case E1000_VF_MAC_FILTER_ADD:
6964                 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
6965                     !vf_data->trusted) {
6966                         dev_warn(&pdev->dev,
6967                                  "VF %d requested MAC filter but is administratively denied\n",
6968                                  vf);
6969                         return -EINVAL;
6970                 }
6971                 if (!is_valid_ether_addr(addr)) {
6972                         dev_warn(&pdev->dev,
6973                                  "VF %d attempted to set invalid MAC filter\n",
6974                                  vf);
6975                         return -EINVAL;
6976                 }
6977
6978                 /* try to find empty slot in the list */
6979                 list_for_each(pos, &adapter->vf_macs.l) {
6980                         entry = list_entry(pos, struct vf_mac_filter, l);
6981                         if (entry->free)
6982                                 break;
6983                 }
6984
6985                 if (entry && entry->free) {
6986                         entry->free = false;
6987                         entry->vf = vf;
6988                         ether_addr_copy(entry->vf_mac, addr);
6989
6990                         ret = igb_add_mac_filter(adapter, addr, vf);
6991                         ret = min_t(int, ret, 0);
6992                 } else {
6993                         ret = -ENOSPC;
6994                 }
6995
6996                 if (ret == -ENOSPC)
6997                         dev_warn(&pdev->dev,
6998                                  "VF %d has requested MAC filter but there is no space for it\n",
6999                                  vf);
7000                 break;
7001         default:
7002                 ret = -EINVAL;
7003                 break;
7004         }
7005
7006         return ret;
7007 }
7008
7009 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
7010 {
7011         struct pci_dev *pdev = adapter->pdev;
7012         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7013         u32 info = msg[0] & E1000_VT_MSGINFO_MASK;
7014
7015         /* The VF MAC Address is stored in a packed array of bytes
7016          * starting at the second 32 bit word of the msg array
7017          */
7018         unsigned char *addr = (unsigned char *)&msg[1];
7019         int ret = 0;
7020
7021         if (!info) {
7022                 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7023                     !vf_data->trusted) {
7024                         dev_warn(&pdev->dev,
7025                                  "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
7026                                  vf);
7027                         return -EINVAL;
7028                 }
7029
7030                 if (!is_valid_ether_addr(addr)) {
7031                         dev_warn(&pdev->dev,
7032                                  "VF %d attempted to set invalid MAC\n",
7033                                  vf);
7034                         return -EINVAL;
7035                 }
7036
7037                 ret = igb_set_vf_mac(adapter, vf, addr);
7038         } else {
7039                 ret = igb_set_vf_mac_filter(adapter, vf, info, addr);
7040         }
7041
7042         return ret;
7043 }
7044
7045 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
7046 {
7047         struct e1000_hw *hw = &adapter->hw;
7048         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7049         u32 msg = E1000_VT_MSGTYPE_NACK;
7050
7051         /* if device isn't clear to send it shouldn't be reading either */
7052         if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
7053             time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
7054                 igb_write_mbx(hw, &msg, 1, vf);
7055                 vf_data->last_nack = jiffies;
7056         }
7057 }
7058
7059 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
7060 {
7061         struct pci_dev *pdev = adapter->pdev;
7062         u32 msgbuf[E1000_VFMAILBOX_SIZE];
7063         struct e1000_hw *hw = &adapter->hw;
7064         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7065         s32 retval;
7066
7067         retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false);
7068
7069         if (retval) {
7070                 /* if receive failed revoke VF CTS stats and restart init */
7071                 dev_err(&pdev->dev, "Error receiving message from VF\n");
7072                 vf_data->flags &= ~IGB_VF_FLAG_CTS;
7073                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7074                         goto unlock;
7075                 goto out;
7076         }
7077
7078         /* this is a message we already processed, do nothing */
7079         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
7080                 goto unlock;
7081
7082         /* until the vf completes a reset it should not be
7083          * allowed to start any configuration.
7084          */
7085         if (msgbuf[0] == E1000_VF_RESET) {
7086                 /* unlocks mailbox */
7087                 igb_vf_reset_msg(adapter, vf);
7088                 return;
7089         }
7090
7091         if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
7092                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7093                         goto unlock;
7094                 retval = -1;
7095                 goto out;
7096         }
7097
7098         switch ((msgbuf[0] & 0xFFFF)) {
7099         case E1000_VF_SET_MAC_ADDR:
7100                 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
7101                 break;
7102         case E1000_VF_SET_PROMISC:
7103                 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
7104                 break;
7105         case E1000_VF_SET_MULTICAST:
7106                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
7107                 break;
7108         case E1000_VF_SET_LPE:
7109                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
7110                 break;
7111         case E1000_VF_SET_VLAN:
7112                 retval = -1;
7113                 if (vf_data->pf_vlan)
7114                         dev_warn(&pdev->dev,
7115                                  "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
7116                                  vf);
7117                 else
7118                         retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
7119                 break;
7120         default:
7121                 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
7122                 retval = -1;
7123                 break;
7124         }
7125
7126         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
7127 out:
7128         /* notify the VF of the results of what it sent us */
7129         if (retval)
7130                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
7131         else
7132                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
7133
7134         /* unlocks mailbox */
7135         igb_write_mbx(hw, msgbuf, 1, vf);
7136         return;
7137
7138 unlock:
7139         igb_unlock_mbx(hw, vf);
7140 }
7141
7142 static void igb_msg_task(struct igb_adapter *adapter)
7143 {
7144         struct e1000_hw *hw = &adapter->hw;
7145         u32 vf;
7146
7147         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
7148                 /* process any reset requests */
7149                 if (!igb_check_for_rst(hw, vf))
7150                         igb_vf_reset_event(adapter, vf);
7151
7152                 /* process any messages pending */
7153                 if (!igb_check_for_msg(hw, vf))
7154                         igb_rcv_msg_from_vf(adapter, vf);
7155
7156                 /* process any acks */
7157                 if (!igb_check_for_ack(hw, vf))
7158                         igb_rcv_ack_from_vf(adapter, vf);
7159         }
7160 }
7161
7162 /**
7163  *  igb_set_uta - Set unicast filter table address
7164  *  @adapter: board private structure
7165  *  @set: boolean indicating if we are setting or clearing bits
7166  *
7167  *  The unicast table address is a register array of 32-bit registers.
7168  *  The table is meant to be used in a way similar to how the MTA is used
7169  *  however due to certain limitations in the hardware it is necessary to
7170  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
7171  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
7172  **/
7173 static void igb_set_uta(struct igb_adapter *adapter, bool set)
7174 {
7175         struct e1000_hw *hw = &adapter->hw;
7176         u32 uta = set ? ~0 : 0;
7177         int i;
7178
7179         /* we only need to do this if VMDq is enabled */
7180         if (!adapter->vfs_allocated_count)
7181                 return;
7182
7183         for (i = hw->mac.uta_reg_count; i--;)
7184                 array_wr32(E1000_UTA, i, uta);
7185 }
7186
7187 /**
7188  *  igb_intr_msi - Interrupt Handler
7189  *  @irq: interrupt number
7190  *  @data: pointer to a network interface device structure
7191  **/
7192 static irqreturn_t igb_intr_msi(int irq, void *data)
7193 {
7194         struct igb_adapter *adapter = data;
7195         struct igb_q_vector *q_vector = adapter->q_vector[0];
7196         struct e1000_hw *hw = &adapter->hw;
7197         /* read ICR disables interrupts using IAM */
7198         u32 icr = rd32(E1000_ICR);
7199
7200         igb_write_itr(q_vector);
7201
7202         if (icr & E1000_ICR_DRSTA)
7203                 schedule_work(&adapter->reset_task);
7204
7205         if (icr & E1000_ICR_DOUTSYNC) {
7206                 /* HW is reporting DMA is out of sync */
7207                 adapter->stats.doosync++;
7208         }
7209
7210         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
7211                 hw->mac.get_link_status = 1;
7212                 if (!test_bit(__IGB_DOWN, &adapter->state))
7213                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
7214         }
7215
7216         if (icr & E1000_ICR_TS)
7217                 igb_tsync_interrupt(adapter);
7218
7219         napi_schedule(&q_vector->napi);
7220
7221         return IRQ_HANDLED;
7222 }
7223
7224 /**
7225  *  igb_intr - Legacy Interrupt Handler
7226  *  @irq: interrupt number
7227  *  @data: pointer to a network interface device structure
7228  **/
7229 static irqreturn_t igb_intr(int irq, void *data)
7230 {
7231         struct igb_adapter *adapter = data;
7232         struct igb_q_vector *q_vector = adapter->q_vector[0];
7233         struct e1000_hw *hw = &adapter->hw;
7234         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
7235          * need for the IMC write
7236          */
7237         u32 icr = rd32(E1000_ICR);
7238
7239         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
7240          * not set, then the adapter didn't send an interrupt
7241          */
7242         if (!(icr & E1000_ICR_INT_ASSERTED))
7243                 return IRQ_NONE;
7244
7245         igb_write_itr(q_vector);
7246
7247         if (icr & E1000_ICR_DRSTA)
7248                 schedule_work(&adapter->reset_task);
7249
7250         if (icr & E1000_ICR_DOUTSYNC) {
7251                 /* HW is reporting DMA is out of sync */
7252                 adapter->stats.doosync++;
7253         }
7254
7255         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
7256                 hw->mac.get_link_status = 1;
7257                 /* guard against interrupt when we're going down */
7258                 if (!test_bit(__IGB_DOWN, &adapter->state))
7259                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
7260         }
7261
7262         if (icr & E1000_ICR_TS)
7263                 igb_tsync_interrupt(adapter);
7264
7265         napi_schedule(&q_vector->napi);
7266
7267         return IRQ_HANDLED;
7268 }
7269
7270 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
7271 {
7272         struct igb_adapter *adapter = q_vector->adapter;
7273         struct e1000_hw *hw = &adapter->hw;
7274
7275         if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
7276             (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
7277                 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
7278                         igb_set_itr(q_vector);
7279                 else
7280                         igb_update_ring_itr(q_vector);
7281         }
7282
7283         if (!test_bit(__IGB_DOWN, &adapter->state)) {
7284                 if (adapter->flags & IGB_FLAG_HAS_MSIX)
7285                         wr32(E1000_EIMS, q_vector->eims_value);
7286                 else
7287                         igb_irq_enable(adapter);
7288         }
7289 }
7290
7291 /**
7292  *  igb_poll - NAPI Rx polling callback
7293  *  @napi: napi polling structure
7294  *  @budget: count of how many packets we should handle
7295  **/
7296 static int igb_poll(struct napi_struct *napi, int budget)
7297 {
7298         struct igb_q_vector *q_vector = container_of(napi,
7299                                                      struct igb_q_vector,
7300                                                      napi);
7301         bool clean_complete = true;
7302         int work_done = 0;
7303
7304 #ifdef CONFIG_IGB_DCA
7305         if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
7306                 igb_update_dca(q_vector);
7307 #endif
7308         if (q_vector->tx.ring)
7309                 clean_complete = igb_clean_tx_irq(q_vector, budget);
7310
7311         if (q_vector->rx.ring) {
7312                 int cleaned = igb_clean_rx_irq(q_vector, budget);
7313
7314                 work_done += cleaned;
7315                 if (cleaned >= budget)
7316                         clean_complete = false;
7317         }
7318
7319         /* If all work not completed, return budget and keep polling */
7320         if (!clean_complete)
7321                 return budget;
7322
7323         /* If not enough Rx work done, exit the polling mode */
7324         napi_complete_done(napi, work_done);
7325         igb_ring_irq_enable(q_vector);
7326
7327         return 0;
7328 }
7329
7330 /**
7331  *  igb_clean_tx_irq - Reclaim resources after transmit completes
7332  *  @q_vector: pointer to q_vector containing needed info
7333  *  @napi_budget: Used to determine if we are in netpoll
7334  *
7335  *  returns true if ring is completely cleaned
7336  **/
7337 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget)
7338 {
7339         struct igb_adapter *adapter = q_vector->adapter;
7340         struct igb_ring *tx_ring = q_vector->tx.ring;
7341         struct igb_tx_buffer *tx_buffer;
7342         union e1000_adv_tx_desc *tx_desc;
7343         unsigned int total_bytes = 0, total_packets = 0;
7344         unsigned int budget = q_vector->tx.work_limit;
7345         unsigned int i = tx_ring->next_to_clean;
7346
7347         if (test_bit(__IGB_DOWN, &adapter->state))
7348                 return true;
7349
7350         tx_buffer = &tx_ring->tx_buffer_info[i];
7351         tx_desc = IGB_TX_DESC(tx_ring, i);
7352         i -= tx_ring->count;
7353
7354         do {
7355                 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
7356
7357                 /* if next_to_watch is not set then there is no work pending */
7358                 if (!eop_desc)
7359                         break;
7360
7361                 /* prevent any other reads prior to eop_desc */
7362                 smp_rmb();
7363
7364                 /* if DD is not set pending work has not been completed */
7365                 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
7366                         break;
7367
7368                 /* clear next_to_watch to prevent false hangs */
7369                 tx_buffer->next_to_watch = NULL;
7370
7371                 /* update the statistics for this packet */
7372                 total_bytes += tx_buffer->bytecount;
7373                 total_packets += tx_buffer->gso_segs;
7374
7375                 /* free the skb */
7376                 napi_consume_skb(tx_buffer->skb, napi_budget);
7377
7378                 /* unmap skb header data */
7379                 dma_unmap_single(tx_ring->dev,
7380                                  dma_unmap_addr(tx_buffer, dma),
7381                                  dma_unmap_len(tx_buffer, len),
7382                                  DMA_TO_DEVICE);
7383
7384                 /* clear tx_buffer data */
7385                 dma_unmap_len_set(tx_buffer, len, 0);
7386
7387                 /* clear last DMA location and unmap remaining buffers */
7388                 while (tx_desc != eop_desc) {
7389                         tx_buffer++;
7390                         tx_desc++;
7391                         i++;
7392                         if (unlikely(!i)) {
7393                                 i -= tx_ring->count;
7394                                 tx_buffer = tx_ring->tx_buffer_info;
7395                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
7396                         }
7397
7398                         /* unmap any remaining paged data */
7399                         if (dma_unmap_len(tx_buffer, len)) {
7400                                 dma_unmap_page(tx_ring->dev,
7401                                                dma_unmap_addr(tx_buffer, dma),
7402                                                dma_unmap_len(tx_buffer, len),
7403                                                DMA_TO_DEVICE);
7404                                 dma_unmap_len_set(tx_buffer, len, 0);
7405                         }
7406                 }
7407
7408                 /* move us one more past the eop_desc for start of next pkt */
7409                 tx_buffer++;
7410                 tx_desc++;
7411                 i++;
7412                 if (unlikely(!i)) {
7413                         i -= tx_ring->count;
7414                         tx_buffer = tx_ring->tx_buffer_info;
7415                         tx_desc = IGB_TX_DESC(tx_ring, 0);
7416                 }
7417
7418                 /* issue prefetch for next Tx descriptor */
7419                 prefetch(tx_desc);
7420
7421                 /* update budget accounting */
7422                 budget--;
7423         } while (likely(budget));
7424
7425         netdev_tx_completed_queue(txring_txq(tx_ring),
7426                                   total_packets, total_bytes);
7427         i += tx_ring->count;
7428         tx_ring->next_to_clean = i;
7429         u64_stats_update_begin(&tx_ring->tx_syncp);
7430         tx_ring->tx_stats.bytes += total_bytes;
7431         tx_ring->tx_stats.packets += total_packets;
7432         u64_stats_update_end(&tx_ring->tx_syncp);
7433         q_vector->tx.total_bytes += total_bytes;
7434         q_vector->tx.total_packets += total_packets;
7435
7436         if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
7437                 struct e1000_hw *hw = &adapter->hw;
7438
7439                 /* Detect a transmit hang in hardware, this serializes the
7440                  * check with the clearing of time_stamp and movement of i
7441                  */
7442                 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
7443                 if (tx_buffer->next_to_watch &&
7444                     time_after(jiffies, tx_buffer->time_stamp +
7445                                (adapter->tx_timeout_factor * HZ)) &&
7446                     !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
7447
7448                         /* detected Tx unit hang */
7449                         dev_err(tx_ring->dev,
7450                                 "Detected Tx Unit Hang\n"
7451                                 "  Tx Queue             <%d>\n"
7452                                 "  TDH                  <%x>\n"
7453                                 "  TDT                  <%x>\n"
7454                                 "  next_to_use          <%x>\n"
7455                                 "  next_to_clean        <%x>\n"
7456                                 "buffer_info[next_to_clean]\n"
7457                                 "  time_stamp           <%lx>\n"
7458                                 "  next_to_watch        <%p>\n"
7459                                 "  jiffies              <%lx>\n"
7460                                 "  desc.status          <%x>\n",
7461                                 tx_ring->queue_index,
7462                                 rd32(E1000_TDH(tx_ring->reg_idx)),
7463                                 readl(tx_ring->tail),
7464                                 tx_ring->next_to_use,
7465                                 tx_ring->next_to_clean,
7466                                 tx_buffer->time_stamp,
7467                                 tx_buffer->next_to_watch,
7468                                 jiffies,
7469                                 tx_buffer->next_to_watch->wb.status);
7470                         netif_stop_subqueue(tx_ring->netdev,
7471                                             tx_ring->queue_index);
7472
7473                         /* we are about to reset, no point in enabling stuff */
7474                         return true;
7475                 }
7476         }
7477
7478 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
7479         if (unlikely(total_packets &&
7480             netif_carrier_ok(tx_ring->netdev) &&
7481             igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
7482                 /* Make sure that anybody stopping the queue after this
7483                  * sees the new next_to_clean.
7484                  */
7485                 smp_mb();
7486                 if (__netif_subqueue_stopped(tx_ring->netdev,
7487                                              tx_ring->queue_index) &&
7488                     !(test_bit(__IGB_DOWN, &adapter->state))) {
7489                         netif_wake_subqueue(tx_ring->netdev,
7490                                             tx_ring->queue_index);
7491
7492                         u64_stats_update_begin(&tx_ring->tx_syncp);
7493                         tx_ring->tx_stats.restart_queue++;
7494                         u64_stats_update_end(&tx_ring->tx_syncp);
7495                 }
7496         }
7497
7498         return !!budget;
7499 }
7500
7501 /**
7502  *  igb_reuse_rx_page - page flip buffer and store it back on the ring
7503  *  @rx_ring: rx descriptor ring to store buffers on
7504  *  @old_buff: donor buffer to have page reused
7505  *
7506  *  Synchronizes page for reuse by the adapter
7507  **/
7508 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
7509                               struct igb_rx_buffer *old_buff)
7510 {
7511         struct igb_rx_buffer *new_buff;
7512         u16 nta = rx_ring->next_to_alloc;
7513
7514         new_buff = &rx_ring->rx_buffer_info[nta];
7515
7516         /* update, and store next to alloc */
7517         nta++;
7518         rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
7519
7520         /* Transfer page from old buffer to new buffer.
7521          * Move each member individually to avoid possible store
7522          * forwarding stalls.
7523          */
7524         new_buff->dma           = old_buff->dma;
7525         new_buff->page          = old_buff->page;
7526         new_buff->page_offset   = old_buff->page_offset;
7527         new_buff->pagecnt_bias  = old_buff->pagecnt_bias;
7528 }
7529
7530 static inline bool igb_page_is_reserved(struct page *page)
7531 {
7532         return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
7533 }
7534
7535 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer)
7536 {
7537         unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
7538         struct page *page = rx_buffer->page;
7539
7540         /* avoid re-using remote pages */
7541         if (unlikely(igb_page_is_reserved(page)))
7542                 return false;
7543
7544 #if (PAGE_SIZE < 8192)
7545         /* if we are only owner of page we can reuse it */
7546         if (unlikely((page_ref_count(page) - pagecnt_bias) > 1))
7547                 return false;
7548 #else
7549 #define IGB_LAST_OFFSET \
7550         (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048)
7551
7552         if (rx_buffer->page_offset > IGB_LAST_OFFSET)
7553                 return false;
7554 #endif
7555
7556         /* If we have drained the page fragment pool we need to update
7557          * the pagecnt_bias and page count so that we fully restock the
7558          * number of references the driver holds.
7559          */
7560         if (unlikely(!pagecnt_bias)) {
7561                 page_ref_add(page, USHRT_MAX);
7562                 rx_buffer->pagecnt_bias = USHRT_MAX;
7563         }
7564
7565         return true;
7566 }
7567
7568 /**
7569  *  igb_add_rx_frag - Add contents of Rx buffer to sk_buff
7570  *  @rx_ring: rx descriptor ring to transact packets on
7571  *  @rx_buffer: buffer containing page to add
7572  *  @skb: sk_buff to place the data into
7573  *  @size: size of buffer to be added
7574  *
7575  *  This function will add the data contained in rx_buffer->page to the skb.
7576  **/
7577 static void igb_add_rx_frag(struct igb_ring *rx_ring,
7578                             struct igb_rx_buffer *rx_buffer,
7579                             struct sk_buff *skb,
7580                             unsigned int size)
7581 {
7582 #if (PAGE_SIZE < 8192)
7583         unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
7584 #else
7585         unsigned int truesize = ring_uses_build_skb(rx_ring) ?
7586                                 SKB_DATA_ALIGN(IGB_SKB_PAD + size) :
7587                                 SKB_DATA_ALIGN(size);
7588 #endif
7589         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
7590                         rx_buffer->page_offset, size, truesize);
7591 #if (PAGE_SIZE < 8192)
7592         rx_buffer->page_offset ^= truesize;
7593 #else
7594         rx_buffer->page_offset += truesize;
7595 #endif
7596 }
7597
7598 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring,
7599                                          struct igb_rx_buffer *rx_buffer,
7600                                          union e1000_adv_rx_desc *rx_desc,
7601                                          unsigned int size)
7602 {
7603         void *va = page_address(rx_buffer->page) + rx_buffer->page_offset;
7604 #if (PAGE_SIZE < 8192)
7605         unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
7606 #else
7607         unsigned int truesize = SKB_DATA_ALIGN(size);
7608 #endif
7609         unsigned int headlen;
7610         struct sk_buff *skb;
7611
7612         /* prefetch first cache line of first page */
7613         prefetch(va);
7614 #if L1_CACHE_BYTES < 128
7615         prefetch(va + L1_CACHE_BYTES);
7616 #endif
7617
7618         /* allocate a skb to store the frags */
7619         skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
7620         if (unlikely(!skb))
7621                 return NULL;
7622
7623         if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
7624                 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
7625                 va += IGB_TS_HDR_LEN;
7626                 size -= IGB_TS_HDR_LEN;
7627         }
7628
7629         /* Determine available headroom for copy */
7630         headlen = size;
7631         if (headlen > IGB_RX_HDR_LEN)
7632                 headlen = eth_get_headlen(va, IGB_RX_HDR_LEN);
7633
7634         /* align pull length to size of long to optimize memcpy performance */
7635         memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long)));
7636
7637         /* update all of the pointers */
7638         size -= headlen;
7639         if (size) {
7640                 skb_add_rx_frag(skb, 0, rx_buffer->page,
7641                                 (va + headlen) - page_address(rx_buffer->page),
7642                                 size, truesize);
7643 #if (PAGE_SIZE < 8192)
7644                 rx_buffer->page_offset ^= truesize;
7645 #else
7646                 rx_buffer->page_offset += truesize;
7647 #endif
7648         } else {
7649                 rx_buffer->pagecnt_bias++;
7650         }
7651
7652         return skb;
7653 }
7654
7655 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring,
7656                                      struct igb_rx_buffer *rx_buffer,
7657                                      union e1000_adv_rx_desc *rx_desc,
7658                                      unsigned int size)
7659 {
7660         void *va = page_address(rx_buffer->page) + rx_buffer->page_offset;
7661 #if (PAGE_SIZE < 8192)
7662         unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
7663 #else
7664         unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
7665                                 SKB_DATA_ALIGN(IGB_SKB_PAD + size);
7666 #endif
7667         struct sk_buff *skb;
7668
7669         /* prefetch first cache line of first page */
7670         prefetch(va);
7671 #if L1_CACHE_BYTES < 128
7672         prefetch(va + L1_CACHE_BYTES);
7673 #endif
7674
7675         /* build an skb around the page buffer */
7676         skb = build_skb(va - IGB_SKB_PAD, truesize);
7677         if (unlikely(!skb))
7678                 return NULL;
7679
7680         /* update pointers within the skb to store the data */
7681         skb_reserve(skb, IGB_SKB_PAD);
7682         __skb_put(skb, size);
7683
7684         /* pull timestamp out of packet data */
7685         if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
7686                 igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb);
7687                 __skb_pull(skb, IGB_TS_HDR_LEN);
7688         }
7689
7690         /* update buffer offset */
7691 #if (PAGE_SIZE < 8192)
7692         rx_buffer->page_offset ^= truesize;
7693 #else
7694         rx_buffer->page_offset += truesize;
7695 #endif
7696
7697         return skb;
7698 }
7699
7700 static inline void igb_rx_checksum(struct igb_ring *ring,
7701                                    union e1000_adv_rx_desc *rx_desc,
7702                                    struct sk_buff *skb)
7703 {
7704         skb_checksum_none_assert(skb);
7705
7706         /* Ignore Checksum bit is set */
7707         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
7708                 return;
7709
7710         /* Rx checksum disabled via ethtool */
7711         if (!(ring->netdev->features & NETIF_F_RXCSUM))
7712                 return;
7713
7714         /* TCP/UDP checksum error bit is set */
7715         if (igb_test_staterr(rx_desc,
7716                              E1000_RXDEXT_STATERR_TCPE |
7717                              E1000_RXDEXT_STATERR_IPE)) {
7718                 /* work around errata with sctp packets where the TCPE aka
7719                  * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
7720                  * packets, (aka let the stack check the crc32c)
7721                  */
7722                 if (!((skb->len == 60) &&
7723                       test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
7724                         u64_stats_update_begin(&ring->rx_syncp);
7725                         ring->rx_stats.csum_err++;
7726                         u64_stats_update_end(&ring->rx_syncp);
7727                 }
7728                 /* let the stack verify checksum errors */
7729                 return;
7730         }
7731         /* It must be a TCP or UDP packet with a valid checksum */
7732         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
7733                                       E1000_RXD_STAT_UDPCS))
7734                 skb->ip_summed = CHECKSUM_UNNECESSARY;
7735
7736         dev_dbg(ring->dev, "cksum success: bits %08X\n",
7737                 le32_to_cpu(rx_desc->wb.upper.status_error));
7738 }
7739
7740 static inline void igb_rx_hash(struct igb_ring *ring,
7741                                union e1000_adv_rx_desc *rx_desc,
7742                                struct sk_buff *skb)
7743 {
7744         if (ring->netdev->features & NETIF_F_RXHASH)
7745                 skb_set_hash(skb,
7746                              le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
7747                              PKT_HASH_TYPE_L3);
7748 }
7749
7750 /**
7751  *  igb_is_non_eop - process handling of non-EOP buffers
7752  *  @rx_ring: Rx ring being processed
7753  *  @rx_desc: Rx descriptor for current buffer
7754  *  @skb: current socket buffer containing buffer in progress
7755  *
7756  *  This function updates next to clean.  If the buffer is an EOP buffer
7757  *  this function exits returning false, otherwise it will place the
7758  *  sk_buff in the next buffer to be chained and return true indicating
7759  *  that this is in fact a non-EOP buffer.
7760  **/
7761 static bool igb_is_non_eop(struct igb_ring *rx_ring,
7762                            union e1000_adv_rx_desc *rx_desc)
7763 {
7764         u32 ntc = rx_ring->next_to_clean + 1;
7765
7766         /* fetch, update, and store next to clean */
7767         ntc = (ntc < rx_ring->count) ? ntc : 0;
7768         rx_ring->next_to_clean = ntc;
7769
7770         prefetch(IGB_RX_DESC(rx_ring, ntc));
7771
7772         if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
7773                 return false;
7774
7775         return true;
7776 }
7777
7778 /**
7779  *  igb_cleanup_headers - Correct corrupted or empty headers
7780  *  @rx_ring: rx descriptor ring packet is being transacted on
7781  *  @rx_desc: pointer to the EOP Rx descriptor
7782  *  @skb: pointer to current skb being fixed
7783  *
7784  *  Address the case where we are pulling data in on pages only
7785  *  and as such no data is present in the skb header.
7786  *
7787  *  In addition if skb is not at least 60 bytes we need to pad it so that
7788  *  it is large enough to qualify as a valid Ethernet frame.
7789  *
7790  *  Returns true if an error was encountered and skb was freed.
7791  **/
7792 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
7793                                 union e1000_adv_rx_desc *rx_desc,
7794                                 struct sk_buff *skb)
7795 {
7796         if (unlikely((igb_test_staterr(rx_desc,
7797                                        E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
7798                 struct net_device *netdev = rx_ring->netdev;
7799                 if (!(netdev->features & NETIF_F_RXALL)) {
7800                         dev_kfree_skb_any(skb);
7801                         return true;
7802                 }
7803         }
7804
7805         /* if eth_skb_pad returns an error the skb was freed */
7806         if (eth_skb_pad(skb))
7807                 return true;
7808
7809         return false;
7810 }
7811
7812 /**
7813  *  igb_process_skb_fields - Populate skb header fields from Rx descriptor
7814  *  @rx_ring: rx descriptor ring packet is being transacted on
7815  *  @rx_desc: pointer to the EOP Rx descriptor
7816  *  @skb: pointer to current skb being populated
7817  *
7818  *  This function checks the ring, descriptor, and packet information in
7819  *  order to populate the hash, checksum, VLAN, timestamp, protocol, and
7820  *  other fields within the skb.
7821  **/
7822 static void igb_process_skb_fields(struct igb_ring *rx_ring,
7823                                    union e1000_adv_rx_desc *rx_desc,
7824                                    struct sk_buff *skb)
7825 {
7826         struct net_device *dev = rx_ring->netdev;
7827
7828         igb_rx_hash(rx_ring, rx_desc, skb);
7829
7830         igb_rx_checksum(rx_ring, rx_desc, skb);
7831
7832         if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
7833             !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
7834                 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
7835
7836         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
7837             igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
7838                 u16 vid;
7839
7840                 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
7841                     test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
7842                         vid = be16_to_cpu(rx_desc->wb.upper.vlan);
7843                 else
7844                         vid = le16_to_cpu(rx_desc->wb.upper.vlan);
7845
7846                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
7847         }
7848
7849         skb_record_rx_queue(skb, rx_ring->queue_index);
7850
7851         skb->protocol = eth_type_trans(skb, rx_ring->netdev);
7852 }
7853
7854 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring,
7855                                                const unsigned int size)
7856 {
7857         struct igb_rx_buffer *rx_buffer;
7858
7859         rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
7860         prefetchw(rx_buffer->page);
7861
7862         /* we are reusing so sync this buffer for CPU use */
7863         dma_sync_single_range_for_cpu(rx_ring->dev,
7864                                       rx_buffer->dma,
7865                                       rx_buffer->page_offset,
7866                                       size,
7867                                       DMA_FROM_DEVICE);
7868
7869         rx_buffer->pagecnt_bias--;
7870
7871         return rx_buffer;
7872 }
7873
7874 static void igb_put_rx_buffer(struct igb_ring *rx_ring,
7875                               struct igb_rx_buffer *rx_buffer)
7876 {
7877         if (igb_can_reuse_rx_page(rx_buffer)) {
7878                 /* hand second half of page back to the ring */
7879                 igb_reuse_rx_page(rx_ring, rx_buffer);
7880         } else {
7881                 /* We are not reusing the buffer so unmap it and free
7882                  * any references we are holding to it
7883                  */
7884                 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
7885                                      igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE,
7886                                      IGB_RX_DMA_ATTR);
7887                 __page_frag_cache_drain(rx_buffer->page,
7888                                         rx_buffer->pagecnt_bias);
7889         }
7890
7891         /* clear contents of rx_buffer */
7892         rx_buffer->page = NULL;
7893 }
7894
7895 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
7896 {
7897         struct igb_ring *rx_ring = q_vector->rx.ring;
7898         struct sk_buff *skb = rx_ring->skb;
7899         unsigned int total_bytes = 0, total_packets = 0;
7900         u16 cleaned_count = igb_desc_unused(rx_ring);
7901
7902         while (likely(total_packets < budget)) {
7903                 union e1000_adv_rx_desc *rx_desc;
7904                 struct igb_rx_buffer *rx_buffer;
7905                 unsigned int size;
7906
7907                 /* return some buffers to hardware, one at a time is too slow */
7908                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
7909                         igb_alloc_rx_buffers(rx_ring, cleaned_count);
7910                         cleaned_count = 0;
7911                 }
7912
7913                 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
7914                 size = le16_to_cpu(rx_desc->wb.upper.length);
7915                 if (!size)
7916                         break;
7917
7918                 /* This memory barrier is needed to keep us from reading
7919                  * any other fields out of the rx_desc until we know the
7920                  * descriptor has been written back
7921                  */
7922                 dma_rmb();
7923
7924                 rx_buffer = igb_get_rx_buffer(rx_ring, size);
7925
7926                 /* retrieve a buffer from the ring */
7927                 if (skb)
7928                         igb_add_rx_frag(rx_ring, rx_buffer, skb, size);
7929                 else if (ring_uses_build_skb(rx_ring))
7930                         skb = igb_build_skb(rx_ring, rx_buffer, rx_desc, size);
7931                 else
7932                         skb = igb_construct_skb(rx_ring, rx_buffer,
7933                                                 rx_desc, size);
7934
7935                 /* exit if we failed to retrieve a buffer */
7936                 if (!skb) {
7937                         rx_ring->rx_stats.alloc_failed++;
7938                         rx_buffer->pagecnt_bias++;
7939                         break;
7940                 }
7941
7942                 igb_put_rx_buffer(rx_ring, rx_buffer);
7943                 cleaned_count++;
7944
7945                 /* fetch next buffer in frame if non-eop */
7946                 if (igb_is_non_eop(rx_ring, rx_desc))
7947                         continue;
7948
7949                 /* verify the packet layout is correct */
7950                 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
7951                         skb = NULL;
7952                         continue;
7953                 }
7954
7955                 /* probably a little skewed due to removing CRC */
7956                 total_bytes += skb->len;
7957
7958                 /* populate checksum, timestamp, VLAN, and protocol */
7959                 igb_process_skb_fields(rx_ring, rx_desc, skb);
7960
7961                 napi_gro_receive(&q_vector->napi, skb);
7962
7963                 /* reset skb pointer */
7964                 skb = NULL;
7965
7966                 /* update budget accounting */
7967                 total_packets++;
7968         }
7969
7970         /* place incomplete frames back on ring for completion */
7971         rx_ring->skb = skb;
7972
7973         u64_stats_update_begin(&rx_ring->rx_syncp);
7974         rx_ring->rx_stats.packets += total_packets;
7975         rx_ring->rx_stats.bytes += total_bytes;
7976         u64_stats_update_end(&rx_ring->rx_syncp);
7977         q_vector->rx.total_packets += total_packets;
7978         q_vector->rx.total_bytes += total_bytes;
7979
7980         if (cleaned_count)
7981                 igb_alloc_rx_buffers(rx_ring, cleaned_count);
7982
7983         return total_packets;
7984 }
7985
7986 static inline unsigned int igb_rx_offset(struct igb_ring *rx_ring)
7987 {
7988         return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0;
7989 }
7990
7991 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
7992                                   struct igb_rx_buffer *bi)
7993 {
7994         struct page *page = bi->page;
7995         dma_addr_t dma;
7996
7997         /* since we are recycling buffers we should seldom need to alloc */
7998         if (likely(page))
7999                 return true;
8000
8001         /* alloc new page for storage */
8002         page = dev_alloc_pages(igb_rx_pg_order(rx_ring));
8003         if (unlikely(!page)) {
8004                 rx_ring->rx_stats.alloc_failed++;
8005                 return false;
8006         }
8007
8008         /* map page for use */
8009         dma = dma_map_page_attrs(rx_ring->dev, page, 0,
8010                                  igb_rx_pg_size(rx_ring),
8011                                  DMA_FROM_DEVICE,
8012                                  IGB_RX_DMA_ATTR);
8013
8014         /* if mapping failed free memory back to system since
8015          * there isn't much point in holding memory we can't use
8016          */
8017         if (dma_mapping_error(rx_ring->dev, dma)) {
8018                 __free_pages(page, igb_rx_pg_order(rx_ring));
8019
8020                 rx_ring->rx_stats.alloc_failed++;
8021                 return false;
8022         }
8023
8024         bi->dma = dma;
8025         bi->page = page;
8026         bi->page_offset = igb_rx_offset(rx_ring);
8027         bi->pagecnt_bias = 1;
8028
8029         return true;
8030 }
8031
8032 /**
8033  *  igb_alloc_rx_buffers - Replace used receive buffers; packet split
8034  *  @adapter: address of board private structure
8035  **/
8036 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
8037 {
8038         union e1000_adv_rx_desc *rx_desc;
8039         struct igb_rx_buffer *bi;
8040         u16 i = rx_ring->next_to_use;
8041         u16 bufsz;
8042
8043         /* nothing to do */
8044         if (!cleaned_count)
8045                 return;
8046
8047         rx_desc = IGB_RX_DESC(rx_ring, i);
8048         bi = &rx_ring->rx_buffer_info[i];
8049         i -= rx_ring->count;
8050
8051         bufsz = igb_rx_bufsz(rx_ring);
8052
8053         do {
8054                 if (!igb_alloc_mapped_page(rx_ring, bi))
8055                         break;
8056
8057                 /* sync the buffer for use by the device */
8058                 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
8059                                                  bi->page_offset, bufsz,
8060                                                  DMA_FROM_DEVICE);
8061
8062                 /* Refresh the desc even if buffer_addrs didn't change
8063                  * because each write-back erases this info.
8064                  */
8065                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
8066
8067                 rx_desc++;
8068                 bi++;
8069                 i++;
8070                 if (unlikely(!i)) {
8071                         rx_desc = IGB_RX_DESC(rx_ring, 0);
8072                         bi = rx_ring->rx_buffer_info;
8073                         i -= rx_ring->count;
8074                 }
8075
8076                 /* clear the length for the next_to_use descriptor */
8077                 rx_desc->wb.upper.length = 0;
8078
8079                 cleaned_count--;
8080         } while (cleaned_count);
8081
8082         i += rx_ring->count;
8083
8084         if (rx_ring->next_to_use != i) {
8085                 /* record the next descriptor to use */
8086                 rx_ring->next_to_use = i;
8087
8088                 /* update next to alloc since we have filled the ring */
8089                 rx_ring->next_to_alloc = i;
8090
8091                 /* Force memory writes to complete before letting h/w
8092                  * know there are new descriptors to fetch.  (Only
8093                  * applicable for weak-ordered memory model archs,
8094                  * such as IA-64).
8095                  */
8096                 wmb();
8097                 writel(i, rx_ring->tail);
8098         }
8099 }
8100
8101 /**
8102  * igb_mii_ioctl -
8103  * @netdev:
8104  * @ifreq:
8105  * @cmd:
8106  **/
8107 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
8108 {
8109         struct igb_adapter *adapter = netdev_priv(netdev);
8110         struct mii_ioctl_data *data = if_mii(ifr);
8111
8112         if (adapter->hw.phy.media_type != e1000_media_type_copper)
8113                 return -EOPNOTSUPP;
8114
8115         switch (cmd) {
8116         case SIOCGMIIPHY:
8117                 data->phy_id = adapter->hw.phy.addr;
8118                 break;
8119         case SIOCGMIIREG:
8120                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
8121                                      &data->val_out))
8122                         return -EIO;
8123                 break;
8124         case SIOCSMIIREG:
8125         default:
8126                 return -EOPNOTSUPP;
8127         }
8128         return 0;
8129 }
8130
8131 /**
8132  * igb_ioctl -
8133  * @netdev:
8134  * @ifreq:
8135  * @cmd:
8136  **/
8137 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
8138 {
8139         switch (cmd) {
8140         case SIOCGMIIPHY:
8141         case SIOCGMIIREG:
8142         case SIOCSMIIREG:
8143                 return igb_mii_ioctl(netdev, ifr, cmd);
8144         case SIOCGHWTSTAMP:
8145                 return igb_ptp_get_ts_config(netdev, ifr);
8146         case SIOCSHWTSTAMP:
8147                 return igb_ptp_set_ts_config(netdev, ifr);
8148         default:
8149                 return -EOPNOTSUPP;
8150         }
8151 }
8152
8153 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
8154 {
8155         struct igb_adapter *adapter = hw->back;
8156
8157         pci_read_config_word(adapter->pdev, reg, value);
8158 }
8159
8160 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
8161 {
8162         struct igb_adapter *adapter = hw->back;
8163
8164         pci_write_config_word(adapter->pdev, reg, *value);
8165 }
8166
8167 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
8168 {
8169         struct igb_adapter *adapter = hw->back;
8170
8171         if (pcie_capability_read_word(adapter->pdev, reg, value))
8172                 return -E1000_ERR_CONFIG;
8173
8174         return 0;
8175 }
8176
8177 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
8178 {
8179         struct igb_adapter *adapter = hw->back;
8180
8181         if (pcie_capability_write_word(adapter->pdev, reg, *value))
8182                 return -E1000_ERR_CONFIG;
8183
8184         return 0;
8185 }
8186
8187 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
8188 {
8189         struct igb_adapter *adapter = netdev_priv(netdev);
8190         struct e1000_hw *hw = &adapter->hw;
8191         u32 ctrl, rctl;
8192         bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
8193
8194         if (enable) {
8195                 /* enable VLAN tag insert/strip */
8196                 ctrl = rd32(E1000_CTRL);
8197                 ctrl |= E1000_CTRL_VME;
8198                 wr32(E1000_CTRL, ctrl);
8199
8200                 /* Disable CFI check */
8201                 rctl = rd32(E1000_RCTL);
8202                 rctl &= ~E1000_RCTL_CFIEN;
8203                 wr32(E1000_RCTL, rctl);
8204         } else {
8205                 /* disable VLAN tag insert/strip */
8206                 ctrl = rd32(E1000_CTRL);
8207                 ctrl &= ~E1000_CTRL_VME;
8208                 wr32(E1000_CTRL, ctrl);
8209         }
8210
8211         igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable);
8212 }
8213
8214 static int igb_vlan_rx_add_vid(struct net_device *netdev,
8215                                __be16 proto, u16 vid)
8216 {
8217         struct igb_adapter *adapter = netdev_priv(netdev);
8218         struct e1000_hw *hw = &adapter->hw;
8219         int pf_id = adapter->vfs_allocated_count;
8220
8221         /* add the filter since PF can receive vlans w/o entry in vlvf */
8222         if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
8223                 igb_vfta_set(hw, vid, pf_id, true, !!vid);
8224
8225         set_bit(vid, adapter->active_vlans);
8226
8227         return 0;
8228 }
8229
8230 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
8231                                 __be16 proto, u16 vid)
8232 {
8233         struct igb_adapter *adapter = netdev_priv(netdev);
8234         int pf_id = adapter->vfs_allocated_count;
8235         struct e1000_hw *hw = &adapter->hw;
8236
8237         /* remove VID from filter table */
8238         if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
8239                 igb_vfta_set(hw, vid, pf_id, false, true);
8240
8241         clear_bit(vid, adapter->active_vlans);
8242
8243         return 0;
8244 }
8245
8246 static void igb_restore_vlan(struct igb_adapter *adapter)
8247 {
8248         u16 vid = 1;
8249
8250         igb_vlan_mode(adapter->netdev, adapter->netdev->features);
8251         igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
8252
8253         for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
8254                 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
8255 }
8256
8257 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
8258 {
8259         struct pci_dev *pdev = adapter->pdev;
8260         struct e1000_mac_info *mac = &adapter->hw.mac;
8261
8262         mac->autoneg = 0;
8263
8264         /* Make sure dplx is at most 1 bit and lsb of speed is not set
8265          * for the switch() below to work
8266          */
8267         if ((spd & 1) || (dplx & ~1))
8268                 goto err_inval;
8269
8270         /* Fiber NIC's only allow 1000 gbps Full duplex
8271          * and 100Mbps Full duplex for 100baseFx sfp
8272          */
8273         if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
8274                 switch (spd + dplx) {
8275                 case SPEED_10 + DUPLEX_HALF:
8276                 case SPEED_10 + DUPLEX_FULL:
8277                 case SPEED_100 + DUPLEX_HALF:
8278                         goto err_inval;
8279                 default:
8280                         break;
8281                 }
8282         }
8283
8284         switch (spd + dplx) {
8285         case SPEED_10 + DUPLEX_HALF:
8286                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
8287                 break;
8288         case SPEED_10 + DUPLEX_FULL:
8289                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
8290                 break;
8291         case SPEED_100 + DUPLEX_HALF:
8292                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
8293                 break;
8294         case SPEED_100 + DUPLEX_FULL:
8295                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
8296                 break;
8297         case SPEED_1000 + DUPLEX_FULL:
8298                 mac->autoneg = 1;
8299                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
8300                 break;
8301         case SPEED_1000 + DUPLEX_HALF: /* not supported */
8302         default:
8303                 goto err_inval;
8304         }
8305
8306         /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
8307         adapter->hw.phy.mdix = AUTO_ALL_MODES;
8308
8309         return 0;
8310
8311 err_inval:
8312         dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
8313         return -EINVAL;
8314 }
8315
8316 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
8317                           bool runtime)
8318 {
8319         struct net_device *netdev = pci_get_drvdata(pdev);
8320         struct igb_adapter *adapter = netdev_priv(netdev);
8321         struct e1000_hw *hw = &adapter->hw;
8322         u32 ctrl, rctl, status;
8323         u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
8324 #ifdef CONFIG_PM
8325         int retval = 0;
8326 #endif
8327
8328         rtnl_lock();
8329         netif_device_detach(netdev);
8330
8331         if (netif_running(netdev))
8332                 __igb_close(netdev, true);
8333
8334         igb_ptp_suspend(adapter);
8335
8336         igb_clear_interrupt_scheme(adapter);
8337         rtnl_unlock();
8338
8339 #ifdef CONFIG_PM
8340         retval = pci_save_state(pdev);
8341         if (retval)
8342                 return retval;
8343 #endif
8344
8345         status = rd32(E1000_STATUS);
8346         if (status & E1000_STATUS_LU)
8347                 wufc &= ~E1000_WUFC_LNKC;
8348
8349         if (wufc) {
8350                 igb_setup_rctl(adapter);
8351                 igb_set_rx_mode(netdev);
8352
8353                 /* turn on all-multi mode if wake on multicast is enabled */
8354                 if (wufc & E1000_WUFC_MC) {
8355                         rctl = rd32(E1000_RCTL);
8356                         rctl |= E1000_RCTL_MPE;
8357                         wr32(E1000_RCTL, rctl);
8358                 }
8359
8360                 ctrl = rd32(E1000_CTRL);
8361                 /* advertise wake from D3Cold */
8362                 #define E1000_CTRL_ADVD3WUC 0x00100000
8363                 /* phy power management enable */
8364                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
8365                 ctrl |= E1000_CTRL_ADVD3WUC;
8366                 wr32(E1000_CTRL, ctrl);
8367
8368                 /* Allow time for pending master requests to run */
8369                 igb_disable_pcie_master(hw);
8370
8371                 wr32(E1000_WUC, E1000_WUC_PME_EN);
8372                 wr32(E1000_WUFC, wufc);
8373         } else {
8374                 wr32(E1000_WUC, 0);
8375                 wr32(E1000_WUFC, 0);
8376         }
8377
8378         *enable_wake = wufc || adapter->en_mng_pt;
8379         if (!*enable_wake)
8380                 igb_power_down_link(adapter);
8381         else
8382                 igb_power_up_link(adapter);
8383
8384         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
8385          * would have already happened in close and is redundant.
8386          */
8387         igb_release_hw_control(adapter);
8388
8389         pci_disable_device(pdev);
8390
8391         return 0;
8392 }
8393
8394 static void igb_deliver_wake_packet(struct net_device *netdev)
8395 {
8396         struct igb_adapter *adapter = netdev_priv(netdev);
8397         struct e1000_hw *hw = &adapter->hw;
8398         struct sk_buff *skb;
8399         u32 wupl;
8400
8401         wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK;
8402
8403         /* WUPM stores only the first 128 bytes of the wake packet.
8404          * Read the packet only if we have the whole thing.
8405          */
8406         if ((wupl == 0) || (wupl > E1000_WUPM_BYTES))
8407                 return;
8408
8409         skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES);
8410         if (!skb)
8411                 return;
8412
8413         skb_put(skb, wupl);
8414
8415         /* Ensure reads are 32-bit aligned */
8416         wupl = roundup(wupl, 4);
8417
8418         memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl);
8419
8420         skb->protocol = eth_type_trans(skb, netdev);
8421         netif_rx(skb);
8422 }
8423
8424 static int __maybe_unused igb_suspend(struct device *dev)
8425 {
8426         int retval;
8427         bool wake;
8428         struct pci_dev *pdev = to_pci_dev(dev);
8429
8430         retval = __igb_shutdown(pdev, &wake, 0);
8431         if (retval)
8432                 return retval;
8433
8434         if (wake) {
8435                 pci_prepare_to_sleep(pdev);
8436         } else {
8437                 pci_wake_from_d3(pdev, false);
8438                 pci_set_power_state(pdev, PCI_D3hot);
8439         }
8440
8441         return 0;
8442 }
8443
8444 static int __maybe_unused igb_resume(struct device *dev)
8445 {
8446         struct pci_dev *pdev = to_pci_dev(dev);
8447         struct net_device *netdev = pci_get_drvdata(pdev);
8448         struct igb_adapter *adapter = netdev_priv(netdev);
8449         struct e1000_hw *hw = &adapter->hw;
8450         u32 err, val;
8451
8452         pci_set_power_state(pdev, PCI_D0);
8453         pci_restore_state(pdev);
8454         pci_save_state(pdev);
8455
8456         if (!pci_device_is_present(pdev))
8457                 return -ENODEV;
8458         err = pci_enable_device_mem(pdev);
8459         if (err) {
8460                 dev_err(&pdev->dev,
8461                         "igb: Cannot enable PCI device from suspend\n");
8462                 return err;
8463         }
8464         pci_set_master(pdev);
8465
8466         pci_enable_wake(pdev, PCI_D3hot, 0);
8467         pci_enable_wake(pdev, PCI_D3cold, 0);
8468
8469         if (igb_init_interrupt_scheme(adapter, true)) {
8470                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8471                 return -ENOMEM;
8472         }
8473
8474         igb_reset(adapter);
8475
8476         /* let the f/w know that the h/w is now under the control of the
8477          * driver.
8478          */
8479         igb_get_hw_control(adapter);
8480
8481         val = rd32(E1000_WUS);
8482         if (val & WAKE_PKT_WUS)
8483                 igb_deliver_wake_packet(netdev);
8484
8485         wr32(E1000_WUS, ~0);
8486
8487         rtnl_lock();
8488         if (!err && netif_running(netdev))
8489                 err = __igb_open(netdev, true);
8490
8491         if (!err)
8492                 netif_device_attach(netdev);
8493         rtnl_unlock();
8494
8495         return err;
8496 }
8497
8498 static int __maybe_unused igb_runtime_idle(struct device *dev)
8499 {
8500         struct pci_dev *pdev = to_pci_dev(dev);
8501         struct net_device *netdev = pci_get_drvdata(pdev);
8502         struct igb_adapter *adapter = netdev_priv(netdev);
8503
8504         if (!igb_has_link(adapter))
8505                 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
8506
8507         return -EBUSY;
8508 }
8509
8510 static int __maybe_unused igb_runtime_suspend(struct device *dev)
8511 {
8512         struct pci_dev *pdev = to_pci_dev(dev);
8513         int retval;
8514         bool wake;
8515
8516         retval = __igb_shutdown(pdev, &wake, 1);
8517         if (retval)
8518                 return retval;
8519
8520         if (wake) {
8521                 pci_prepare_to_sleep(pdev);
8522         } else {
8523                 pci_wake_from_d3(pdev, false);
8524                 pci_set_power_state(pdev, PCI_D3hot);
8525         }
8526
8527         return 0;
8528 }
8529
8530 static int __maybe_unused igb_runtime_resume(struct device *dev)
8531 {
8532         return igb_resume(dev);
8533 }
8534
8535 static void igb_shutdown(struct pci_dev *pdev)
8536 {
8537         bool wake;
8538
8539         __igb_shutdown(pdev, &wake, 0);
8540
8541         if (system_state == SYSTEM_POWER_OFF) {
8542                 pci_wake_from_d3(pdev, wake);
8543                 pci_set_power_state(pdev, PCI_D3hot);
8544         }
8545 }
8546
8547 #ifdef CONFIG_PCI_IOV
8548 static int igb_sriov_reinit(struct pci_dev *dev)
8549 {
8550         struct net_device *netdev = pci_get_drvdata(dev);
8551         struct igb_adapter *adapter = netdev_priv(netdev);
8552         struct pci_dev *pdev = adapter->pdev;
8553
8554         rtnl_lock();
8555
8556         if (netif_running(netdev))
8557                 igb_close(netdev);
8558         else
8559                 igb_reset(adapter);
8560
8561         igb_clear_interrupt_scheme(adapter);
8562
8563         igb_init_queue_configuration(adapter);
8564
8565         if (igb_init_interrupt_scheme(adapter, true)) {
8566                 rtnl_unlock();
8567                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8568                 return -ENOMEM;
8569         }
8570
8571         if (netif_running(netdev))
8572                 igb_open(netdev);
8573
8574         rtnl_unlock();
8575
8576         return 0;
8577 }
8578
8579 static int igb_pci_disable_sriov(struct pci_dev *dev)
8580 {
8581         int err = igb_disable_sriov(dev);
8582
8583         if (!err)
8584                 err = igb_sriov_reinit(dev);
8585
8586         return err;
8587 }
8588
8589 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
8590 {
8591         int err = igb_enable_sriov(dev, num_vfs);
8592
8593         if (err)
8594                 goto out;
8595
8596         err = igb_sriov_reinit(dev);
8597         if (!err)
8598                 return num_vfs;
8599
8600 out:
8601         return err;
8602 }
8603
8604 #endif
8605 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
8606 {
8607 #ifdef CONFIG_PCI_IOV
8608         if (num_vfs == 0)
8609                 return igb_pci_disable_sriov(dev);
8610         else
8611                 return igb_pci_enable_sriov(dev, num_vfs);
8612 #endif
8613         return 0;
8614 }
8615
8616 #ifdef CONFIG_NET_POLL_CONTROLLER
8617 /* Polling 'interrupt' - used by things like netconsole to send skbs
8618  * without having to re-enable interrupts. It's not called while
8619  * the interrupt routine is executing.
8620  */
8621 static void igb_netpoll(struct net_device *netdev)
8622 {
8623         struct igb_adapter *adapter = netdev_priv(netdev);
8624         struct e1000_hw *hw = &adapter->hw;
8625         struct igb_q_vector *q_vector;
8626         int i;
8627
8628         for (i = 0; i < adapter->num_q_vectors; i++) {
8629                 q_vector = adapter->q_vector[i];
8630                 if (adapter->flags & IGB_FLAG_HAS_MSIX)
8631                         wr32(E1000_EIMC, q_vector->eims_value);
8632                 else
8633                         igb_irq_disable(adapter);
8634                 napi_schedule(&q_vector->napi);
8635         }
8636 }
8637 #endif /* CONFIG_NET_POLL_CONTROLLER */
8638
8639 /**
8640  *  igb_io_error_detected - called when PCI error is detected
8641  *  @pdev: Pointer to PCI device
8642  *  @state: The current pci connection state
8643  *
8644  *  This function is called after a PCI bus error affecting
8645  *  this device has been detected.
8646  **/
8647 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
8648                                               pci_channel_state_t state)
8649 {
8650         struct net_device *netdev = pci_get_drvdata(pdev);
8651         struct igb_adapter *adapter = netdev_priv(netdev);
8652
8653         netif_device_detach(netdev);
8654
8655         if (state == pci_channel_io_perm_failure)
8656                 return PCI_ERS_RESULT_DISCONNECT;
8657
8658         if (netif_running(netdev))
8659                 igb_down(adapter);
8660         pci_disable_device(pdev);
8661
8662         /* Request a slot slot reset. */
8663         return PCI_ERS_RESULT_NEED_RESET;
8664 }
8665
8666 /**
8667  *  igb_io_slot_reset - called after the pci bus has been reset.
8668  *  @pdev: Pointer to PCI device
8669  *
8670  *  Restart the card from scratch, as if from a cold-boot. Implementation
8671  *  resembles the first-half of the igb_resume routine.
8672  **/
8673 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
8674 {
8675         struct net_device *netdev = pci_get_drvdata(pdev);
8676         struct igb_adapter *adapter = netdev_priv(netdev);
8677         struct e1000_hw *hw = &adapter->hw;
8678         pci_ers_result_t result;
8679         int err;
8680
8681         if (pci_enable_device_mem(pdev)) {
8682                 dev_err(&pdev->dev,
8683                         "Cannot re-enable PCI device after reset.\n");
8684                 result = PCI_ERS_RESULT_DISCONNECT;
8685         } else {
8686                 pci_set_master(pdev);
8687                 pci_restore_state(pdev);
8688                 pci_save_state(pdev);
8689
8690                 pci_enable_wake(pdev, PCI_D3hot, 0);
8691                 pci_enable_wake(pdev, PCI_D3cold, 0);
8692
8693                 /* In case of PCI error, adapter lose its HW address
8694                  * so we should re-assign it here.
8695                  */
8696                 hw->hw_addr = adapter->io_addr;
8697
8698                 igb_reset(adapter);
8699                 wr32(E1000_WUS, ~0);
8700                 result = PCI_ERS_RESULT_RECOVERED;
8701         }
8702
8703         err = pci_cleanup_aer_uncorrect_error_status(pdev);
8704         if (err) {
8705                 dev_err(&pdev->dev,
8706                         "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8707                         err);
8708                 /* non-fatal, continue */
8709         }
8710
8711         return result;
8712 }
8713
8714 /**
8715  *  igb_io_resume - called when traffic can start flowing again.
8716  *  @pdev: Pointer to PCI device
8717  *
8718  *  This callback is called when the error recovery driver tells us that
8719  *  its OK to resume normal operation. Implementation resembles the
8720  *  second-half of the igb_resume routine.
8721  */
8722 static void igb_io_resume(struct pci_dev *pdev)
8723 {
8724         struct net_device *netdev = pci_get_drvdata(pdev);
8725         struct igb_adapter *adapter = netdev_priv(netdev);
8726
8727         if (netif_running(netdev)) {
8728                 if (igb_up(adapter)) {
8729                         dev_err(&pdev->dev, "igb_up failed after reset\n");
8730                         return;
8731                 }
8732         }
8733
8734         netif_device_attach(netdev);
8735
8736         /* let the f/w know that the h/w is now under the control of the
8737          * driver.
8738          */
8739         igb_get_hw_control(adapter);
8740 }
8741
8742 /**
8743  *  igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table
8744  *  @adapter: Pointer to adapter structure
8745  *  @index: Index of the RAR entry which need to be synced with MAC table
8746  **/
8747 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index)
8748 {
8749         struct e1000_hw *hw = &adapter->hw;
8750         u32 rar_low, rar_high;
8751         u8 *addr = adapter->mac_table[index].addr;
8752
8753         /* HW expects these to be in network order when they are plugged
8754          * into the registers which are little endian.  In order to guarantee
8755          * that ordering we need to do an leXX_to_cpup here in order to be
8756          * ready for the byteswap that occurs with writel
8757          */
8758         rar_low = le32_to_cpup((__le32 *)(addr));
8759         rar_high = le16_to_cpup((__le16 *)(addr + 4));
8760
8761         /* Indicate to hardware the Address is Valid. */
8762         if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) {
8763                 if (is_valid_ether_addr(addr))
8764                         rar_high |= E1000_RAH_AV;
8765
8766                 if (hw->mac.type == e1000_82575)
8767                         rar_high |= E1000_RAH_POOL_1 *
8768                                     adapter->mac_table[index].queue;
8769                 else
8770                         rar_high |= E1000_RAH_POOL_1 <<
8771                                     adapter->mac_table[index].queue;
8772         }
8773
8774         wr32(E1000_RAL(index), rar_low);
8775         wrfl();
8776         wr32(E1000_RAH(index), rar_high);
8777         wrfl();
8778 }
8779
8780 static int igb_set_vf_mac(struct igb_adapter *adapter,
8781                           int vf, unsigned char *mac_addr)
8782 {
8783         struct e1000_hw *hw = &adapter->hw;
8784         /* VF MAC addresses start at end of receive addresses and moves
8785          * towards the first, as a result a collision should not be possible
8786          */
8787         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
8788         unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses;
8789
8790         ether_addr_copy(vf_mac_addr, mac_addr);
8791         ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr);
8792         adapter->mac_table[rar_entry].queue = vf;
8793         adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE;
8794         igb_rar_set_index(adapter, rar_entry);
8795
8796         return 0;
8797 }
8798
8799 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
8800 {
8801         struct igb_adapter *adapter = netdev_priv(netdev);
8802
8803         if (vf >= adapter->vfs_allocated_count)
8804                 return -EINVAL;
8805
8806         /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC
8807          * flag and allows to overwrite the MAC via VF netdev.  This
8808          * is necessary to allow libvirt a way to restore the original
8809          * MAC after unbinding vfio-pci and reloading igbvf after shutting
8810          * down a VM.
8811          */
8812         if (is_zero_ether_addr(mac)) {
8813                 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC;
8814                 dev_info(&adapter->pdev->dev,
8815                          "remove administratively set MAC on VF %d\n",
8816                          vf);
8817         } else if (is_valid_ether_addr(mac)) {
8818                 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
8819                 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n",
8820                          mac, vf);
8821                 dev_info(&adapter->pdev->dev,
8822                          "Reload the VF driver to make this change effective.");
8823                 /* Generate additional warning if PF is down */
8824                 if (test_bit(__IGB_DOWN, &adapter->state)) {
8825                         dev_warn(&adapter->pdev->dev,
8826                                  "The VF MAC address has been set, but the PF device is not up.\n");
8827                         dev_warn(&adapter->pdev->dev,
8828                                  "Bring the PF device up before attempting to use the VF device.\n");
8829                 }
8830         } else {
8831                 return -EINVAL;
8832         }
8833         return igb_set_vf_mac(adapter, vf, mac);
8834 }
8835
8836 static int igb_link_mbps(int internal_link_speed)
8837 {
8838         switch (internal_link_speed) {
8839         case SPEED_100:
8840                 return 100;
8841         case SPEED_1000:
8842                 return 1000;
8843         default:
8844                 return 0;
8845         }
8846 }
8847
8848 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
8849                                   int link_speed)
8850 {
8851         int rf_dec, rf_int;
8852         u32 bcnrc_val;
8853
8854         if (tx_rate != 0) {
8855                 /* Calculate the rate factor values to set */
8856                 rf_int = link_speed / tx_rate;
8857                 rf_dec = (link_speed - (rf_int * tx_rate));
8858                 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) /
8859                          tx_rate;
8860
8861                 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
8862                 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
8863                               E1000_RTTBCNRC_RF_INT_MASK);
8864                 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
8865         } else {
8866                 bcnrc_val = 0;
8867         }
8868
8869         wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
8870         /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
8871          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
8872          */
8873         wr32(E1000_RTTBCNRM, 0x14);
8874         wr32(E1000_RTTBCNRC, bcnrc_val);
8875 }
8876
8877 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
8878 {
8879         int actual_link_speed, i;
8880         bool reset_rate = false;
8881
8882         /* VF TX rate limit was not set or not supported */
8883         if ((adapter->vf_rate_link_speed == 0) ||
8884             (adapter->hw.mac.type != e1000_82576))
8885                 return;
8886
8887         actual_link_speed = igb_link_mbps(adapter->link_speed);
8888         if (actual_link_speed != adapter->vf_rate_link_speed) {
8889                 reset_rate = true;
8890                 adapter->vf_rate_link_speed = 0;
8891                 dev_info(&adapter->pdev->dev,
8892                          "Link speed has been changed. VF Transmit rate is disabled\n");
8893         }
8894
8895         for (i = 0; i < adapter->vfs_allocated_count; i++) {
8896                 if (reset_rate)
8897                         adapter->vf_data[i].tx_rate = 0;
8898
8899                 igb_set_vf_rate_limit(&adapter->hw, i,
8900                                       adapter->vf_data[i].tx_rate,
8901                                       actual_link_speed);
8902         }
8903 }
8904
8905 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
8906                              int min_tx_rate, int max_tx_rate)
8907 {
8908         struct igb_adapter *adapter = netdev_priv(netdev);
8909         struct e1000_hw *hw = &adapter->hw;
8910         int actual_link_speed;
8911
8912         if (hw->mac.type != e1000_82576)
8913                 return -EOPNOTSUPP;
8914
8915         if (min_tx_rate)
8916                 return -EINVAL;
8917
8918         actual_link_speed = igb_link_mbps(adapter->link_speed);
8919         if ((vf >= adapter->vfs_allocated_count) ||
8920             (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
8921             (max_tx_rate < 0) ||
8922             (max_tx_rate > actual_link_speed))
8923                 return -EINVAL;
8924
8925         adapter->vf_rate_link_speed = actual_link_speed;
8926         adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
8927         igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
8928
8929         return 0;
8930 }
8931
8932 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
8933                                    bool setting)
8934 {
8935         struct igb_adapter *adapter = netdev_priv(netdev);
8936         struct e1000_hw *hw = &adapter->hw;
8937         u32 reg_val, reg_offset;
8938
8939         if (!adapter->vfs_allocated_count)
8940                 return -EOPNOTSUPP;
8941
8942         if (vf >= adapter->vfs_allocated_count)
8943                 return -EINVAL;
8944
8945         reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
8946         reg_val = rd32(reg_offset);
8947         if (setting)
8948                 reg_val |= (BIT(vf) |
8949                             BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
8950         else
8951                 reg_val &= ~(BIT(vf) |
8952                              BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
8953         wr32(reg_offset, reg_val);
8954
8955         adapter->vf_data[vf].spoofchk_enabled = setting;
8956         return 0;
8957 }
8958
8959 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting)
8960 {
8961         struct igb_adapter *adapter = netdev_priv(netdev);
8962
8963         if (vf >= adapter->vfs_allocated_count)
8964                 return -EINVAL;
8965         if (adapter->vf_data[vf].trusted == setting)
8966                 return 0;
8967
8968         adapter->vf_data[vf].trusted = setting;
8969
8970         dev_info(&adapter->pdev->dev, "VF %u is %strusted\n",
8971                  vf, setting ? "" : "not ");
8972         return 0;
8973 }
8974
8975 static int igb_ndo_get_vf_config(struct net_device *netdev,
8976                                  int vf, struct ifla_vf_info *ivi)
8977 {
8978         struct igb_adapter *adapter = netdev_priv(netdev);
8979         if (vf >= adapter->vfs_allocated_count)
8980                 return -EINVAL;
8981         ivi->vf = vf;
8982         memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
8983         ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
8984         ivi->min_tx_rate = 0;
8985         ivi->vlan = adapter->vf_data[vf].pf_vlan;
8986         ivi->qos = adapter->vf_data[vf].pf_qos;
8987         ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8988         ivi->trusted = adapter->vf_data[vf].trusted;
8989         return 0;
8990 }
8991
8992 static void igb_vmm_control(struct igb_adapter *adapter)
8993 {
8994         struct e1000_hw *hw = &adapter->hw;
8995         u32 reg;
8996
8997         switch (hw->mac.type) {
8998         case e1000_82575:
8999         case e1000_i210:
9000         case e1000_i211:
9001         case e1000_i354:
9002         default:
9003                 /* replication is not supported for 82575 */
9004                 return;
9005         case e1000_82576:
9006                 /* notify HW that the MAC is adding vlan tags */
9007                 reg = rd32(E1000_DTXCTL);
9008                 reg |= E1000_DTXCTL_VLAN_ADDED;
9009                 wr32(E1000_DTXCTL, reg);
9010                 /* Fall through */
9011         case e1000_82580:
9012                 /* enable replication vlan tag stripping */
9013                 reg = rd32(E1000_RPLOLR);
9014                 reg |= E1000_RPLOLR_STRVLAN;
9015                 wr32(E1000_RPLOLR, reg);
9016                 /* Fall through */
9017         case e1000_i350:
9018                 /* none of the above registers are supported by i350 */
9019                 break;
9020         }
9021
9022         if (adapter->vfs_allocated_count) {
9023                 igb_vmdq_set_loopback_pf(hw, true);
9024                 igb_vmdq_set_replication_pf(hw, true);
9025                 igb_vmdq_set_anti_spoofing_pf(hw, true,
9026                                               adapter->vfs_allocated_count);
9027         } else {
9028                 igb_vmdq_set_loopback_pf(hw, false);
9029                 igb_vmdq_set_replication_pf(hw, false);
9030         }
9031 }
9032
9033 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
9034 {
9035         struct e1000_hw *hw = &adapter->hw;
9036         u32 dmac_thr;
9037         u16 hwm;
9038
9039         if (hw->mac.type > e1000_82580) {
9040                 if (adapter->flags & IGB_FLAG_DMAC) {
9041                         u32 reg;
9042
9043                         /* force threshold to 0. */
9044                         wr32(E1000_DMCTXTH, 0);
9045
9046                         /* DMA Coalescing high water mark needs to be greater
9047                          * than the Rx threshold. Set hwm to PBA - max frame
9048                          * size in 16B units, capping it at PBA - 6KB.
9049                          */
9050                         hwm = 64 * (pba - 6);
9051                         reg = rd32(E1000_FCRTC);
9052                         reg &= ~E1000_FCRTC_RTH_COAL_MASK;
9053                         reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
9054                                 & E1000_FCRTC_RTH_COAL_MASK);
9055                         wr32(E1000_FCRTC, reg);
9056
9057                         /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
9058                          * frame size, capping it at PBA - 10KB.
9059                          */
9060                         dmac_thr = pba - 10;
9061                         reg = rd32(E1000_DMACR);
9062                         reg &= ~E1000_DMACR_DMACTHR_MASK;
9063                         reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
9064                                 & E1000_DMACR_DMACTHR_MASK);
9065
9066                         /* transition to L0x or L1 if available..*/
9067                         reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
9068
9069                         /* watchdog timer= +-1000 usec in 32usec intervals */
9070                         reg |= (1000 >> 5);
9071
9072                         /* Disable BMC-to-OS Watchdog Enable */
9073                         if (hw->mac.type != e1000_i354)
9074                                 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
9075
9076                         wr32(E1000_DMACR, reg);
9077
9078                         /* no lower threshold to disable
9079                          * coalescing(smart fifb)-UTRESH=0
9080                          */
9081                         wr32(E1000_DMCRTRH, 0);
9082
9083                         reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
9084
9085                         wr32(E1000_DMCTLX, reg);
9086
9087                         /* free space in tx packet buffer to wake from
9088                          * DMA coal
9089                          */
9090                         wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
9091                              (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
9092
9093                         /* make low power state decision controlled
9094                          * by DMA coal
9095                          */
9096                         reg = rd32(E1000_PCIEMISC);
9097                         reg &= ~E1000_PCIEMISC_LX_DECISION;
9098                         wr32(E1000_PCIEMISC, reg);
9099                 } /* endif adapter->dmac is not disabled */
9100         } else if (hw->mac.type == e1000_82580) {
9101                 u32 reg = rd32(E1000_PCIEMISC);
9102
9103                 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
9104                 wr32(E1000_DMACR, 0);
9105         }
9106 }
9107
9108 /**
9109  *  igb_read_i2c_byte - Reads 8 bit word over I2C
9110  *  @hw: pointer to hardware structure
9111  *  @byte_offset: byte offset to read
9112  *  @dev_addr: device address
9113  *  @data: value read
9114  *
9115  *  Performs byte read operation over I2C interface at
9116  *  a specified device address.
9117  **/
9118 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
9119                       u8 dev_addr, u8 *data)
9120 {
9121         struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
9122         struct i2c_client *this_client = adapter->i2c_client;
9123         s32 status;
9124         u16 swfw_mask = 0;
9125
9126         if (!this_client)
9127                 return E1000_ERR_I2C;
9128
9129         swfw_mask = E1000_SWFW_PHY0_SM;
9130
9131         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
9132                 return E1000_ERR_SWFW_SYNC;
9133
9134         status = i2c_smbus_read_byte_data(this_client, byte_offset);
9135         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
9136
9137         if (status < 0)
9138                 return E1000_ERR_I2C;
9139         else {
9140                 *data = status;
9141                 return 0;
9142         }
9143 }
9144
9145 /**
9146  *  igb_write_i2c_byte - Writes 8 bit word over I2C
9147  *  @hw: pointer to hardware structure
9148  *  @byte_offset: byte offset to write
9149  *  @dev_addr: device address
9150  *  @data: value to write
9151  *
9152  *  Performs byte write operation over I2C interface at
9153  *  a specified device address.
9154  **/
9155 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
9156                        u8 dev_addr, u8 data)
9157 {
9158         struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
9159         struct i2c_client *this_client = adapter->i2c_client;
9160         s32 status;
9161         u16 swfw_mask = E1000_SWFW_PHY0_SM;
9162
9163         if (!this_client)
9164                 return E1000_ERR_I2C;
9165
9166         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
9167                 return E1000_ERR_SWFW_SYNC;
9168         status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
9169         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
9170
9171         if (status)
9172                 return E1000_ERR_I2C;
9173         else
9174                 return 0;
9175
9176 }
9177
9178 int igb_reinit_queues(struct igb_adapter *adapter)
9179 {
9180         struct net_device *netdev = adapter->netdev;
9181         struct pci_dev *pdev = adapter->pdev;
9182         int err = 0;
9183
9184         if (netif_running(netdev))
9185                 igb_close(netdev);
9186
9187         igb_reset_interrupt_capability(adapter);
9188
9189         if (igb_init_interrupt_scheme(adapter, true)) {
9190                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
9191                 return -ENOMEM;
9192         }
9193
9194         if (netif_running(netdev))
9195                 err = igb_open(netdev);
9196
9197         return err;
9198 }
9199
9200 static void igb_nfc_filter_exit(struct igb_adapter *adapter)
9201 {
9202         struct igb_nfc_filter *rule;
9203
9204         spin_lock(&adapter->nfc_lock);
9205
9206         hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
9207                 igb_erase_filter(adapter, rule);
9208
9209         spin_unlock(&adapter->nfc_lock);
9210 }
9211
9212 static void igb_nfc_filter_restore(struct igb_adapter *adapter)
9213 {
9214         struct igb_nfc_filter *rule;
9215
9216         spin_lock(&adapter->nfc_lock);
9217
9218         hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
9219                 igb_add_filter(adapter, rule);
9220
9221         spin_unlock(&adapter->nfc_lock);
9222 }
9223 /* igb_main.c */