1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
6 #include <linux/module.h>
7 #include <linux/types.h>
8 #include <linux/init.h>
9 #include <linux/bitops.h>
10 #include <linux/vmalloc.h>
11 #include <linux/pagemap.h>
12 #include <linux/netdevice.h>
13 #include <linux/ipv6.h>
14 #include <linux/slab.h>
15 #include <net/checksum.h>
16 #include <net/ip6_checksum.h>
17 #include <net/pkt_sched.h>
18 #include <net/pkt_cls.h>
19 #include <linux/net_tstamp.h>
20 #include <linux/mii.h>
21 #include <linux/ethtool.h>
23 #include <linux/if_vlan.h>
24 #include <linux/pci.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
28 #include <linux/tcp.h>
29 #include <linux/sctp.h>
30 #include <linux/if_ether.h>
31 #include <linux/aer.h>
32 #include <linux/prefetch.h>
33 #include <linux/bpf.h>
34 #include <linux/bpf_trace.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/etherdevice.h>
38 #include <linux/dca.h>
40 #include <linux/i2c.h>
44 QUEUE_MODE_STRICT_PRIORITY,
45 QUEUE_MODE_STREAM_RESERVATION,
53 char igb_driver_name[] = "igb";
54 static const char igb_driver_string[] =
55 "Intel(R) Gigabit Ethernet Network Driver";
56 static const char igb_copyright[] =
57 "Copyright (c) 2007-2014 Intel Corporation.";
59 static const struct e1000_info *igb_info_tbl[] = {
60 [board_82575] = &e1000_82575_info,
63 static const struct pci_device_id igb_pci_tbl[] = {
64 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
65 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
66 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
67 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
68 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
69 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
70 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
71 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
72 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
73 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
74 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
75 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
99 /* required last entry */
103 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
105 static int igb_setup_all_tx_resources(struct igb_adapter *);
106 static int igb_setup_all_rx_resources(struct igb_adapter *);
107 static void igb_free_all_tx_resources(struct igb_adapter *);
108 static void igb_free_all_rx_resources(struct igb_adapter *);
109 static void igb_setup_mrqc(struct igb_adapter *);
110 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
111 static void igb_remove(struct pci_dev *pdev);
112 static int igb_sw_init(struct igb_adapter *);
113 int igb_open(struct net_device *);
114 int igb_close(struct net_device *);
115 static void igb_configure(struct igb_adapter *);
116 static void igb_configure_tx(struct igb_adapter *);
117 static void igb_configure_rx(struct igb_adapter *);
118 static void igb_clean_all_tx_rings(struct igb_adapter *);
119 static void igb_clean_all_rx_rings(struct igb_adapter *);
120 static void igb_clean_tx_ring(struct igb_ring *);
121 static void igb_clean_rx_ring(struct igb_ring *);
122 static void igb_set_rx_mode(struct net_device *);
123 static void igb_update_phy_info(struct timer_list *);
124 static void igb_watchdog(struct timer_list *);
125 static void igb_watchdog_task(struct work_struct *);
126 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
127 static void igb_get_stats64(struct net_device *dev,
128 struct rtnl_link_stats64 *stats);
129 static int igb_change_mtu(struct net_device *, int);
130 static int igb_set_mac(struct net_device *, void *);
131 static void igb_set_uta(struct igb_adapter *adapter, bool set);
132 static irqreturn_t igb_intr(int irq, void *);
133 static irqreturn_t igb_intr_msi(int irq, void *);
134 static irqreturn_t igb_msix_other(int irq, void *);
135 static irqreturn_t igb_msix_ring(int irq, void *);
136 #ifdef CONFIG_IGB_DCA
137 static void igb_update_dca(struct igb_q_vector *);
138 static void igb_setup_dca(struct igb_adapter *);
139 #endif /* CONFIG_IGB_DCA */
140 static int igb_poll(struct napi_struct *, int);
141 static bool igb_clean_tx_irq(struct igb_q_vector *, int);
142 static int igb_clean_rx_irq(struct igb_q_vector *, int);
143 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
144 static void igb_tx_timeout(struct net_device *, unsigned int txqueue);
145 static void igb_reset_task(struct work_struct *);
146 static void igb_vlan_mode(struct net_device *netdev,
147 netdev_features_t features);
148 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
149 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
150 static void igb_restore_vlan(struct igb_adapter *);
151 static void igb_rar_set_index(struct igb_adapter *, u32);
152 static void igb_ping_all_vfs(struct igb_adapter *);
153 static void igb_msg_task(struct igb_adapter *);
154 static void igb_vmm_control(struct igb_adapter *);
155 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
156 static void igb_flush_mac_table(struct igb_adapter *);
157 static int igb_available_rars(struct igb_adapter *, u8);
158 static void igb_set_default_mac_filter(struct igb_adapter *);
159 static int igb_uc_sync(struct net_device *, const unsigned char *);
160 static int igb_uc_unsync(struct net_device *, const unsigned char *);
161 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
162 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
163 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
164 int vf, u16 vlan, u8 qos, __be16 vlan_proto);
165 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
166 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
168 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf,
170 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
171 struct ifla_vf_info *ivi);
172 static void igb_check_vf_rate_limit(struct igb_adapter *);
173 static void igb_nfc_filter_exit(struct igb_adapter *adapter);
174 static void igb_nfc_filter_restore(struct igb_adapter *adapter);
176 #ifdef CONFIG_PCI_IOV
177 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
178 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
179 static int igb_disable_sriov(struct pci_dev *dev);
180 static int igb_pci_disable_sriov(struct pci_dev *dev);
183 static int igb_suspend(struct device *);
184 static int igb_resume(struct device *);
185 static int igb_runtime_suspend(struct device *dev);
186 static int igb_runtime_resume(struct device *dev);
187 static int igb_runtime_idle(struct device *dev);
188 static const struct dev_pm_ops igb_pm_ops = {
189 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
190 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
193 static void igb_shutdown(struct pci_dev *);
194 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
195 #ifdef CONFIG_IGB_DCA
196 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
197 static struct notifier_block dca_notifier = {
198 .notifier_call = igb_notify_dca,
203 #ifdef CONFIG_PCI_IOV
204 static unsigned int max_vfs;
205 module_param(max_vfs, uint, 0);
206 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
207 #endif /* CONFIG_PCI_IOV */
209 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
210 pci_channel_state_t);
211 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
212 static void igb_io_resume(struct pci_dev *);
214 static const struct pci_error_handlers igb_err_handler = {
215 .error_detected = igb_io_error_detected,
216 .slot_reset = igb_io_slot_reset,
217 .resume = igb_io_resume,
220 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
222 static struct pci_driver igb_driver = {
223 .name = igb_driver_name,
224 .id_table = igb_pci_tbl,
226 .remove = igb_remove,
228 .driver.pm = &igb_pm_ops,
230 .shutdown = igb_shutdown,
231 .sriov_configure = igb_pci_sriov_configure,
232 .err_handler = &igb_err_handler
235 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
236 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
237 MODULE_LICENSE("GPL v2");
239 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
240 static int debug = -1;
241 module_param(debug, int, 0);
242 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
244 struct igb_reg_info {
249 static const struct igb_reg_info igb_reg_info_tbl[] = {
251 /* General Registers */
252 {E1000_CTRL, "CTRL"},
253 {E1000_STATUS, "STATUS"},
254 {E1000_CTRL_EXT, "CTRL_EXT"},
256 /* Interrupt Registers */
260 {E1000_RCTL, "RCTL"},
261 {E1000_RDLEN(0), "RDLEN"},
262 {E1000_RDH(0), "RDH"},
263 {E1000_RDT(0), "RDT"},
264 {E1000_RXDCTL(0), "RXDCTL"},
265 {E1000_RDBAL(0), "RDBAL"},
266 {E1000_RDBAH(0), "RDBAH"},
269 {E1000_TCTL, "TCTL"},
270 {E1000_TDBAL(0), "TDBAL"},
271 {E1000_TDBAH(0), "TDBAH"},
272 {E1000_TDLEN(0), "TDLEN"},
273 {E1000_TDH(0), "TDH"},
274 {E1000_TDT(0), "TDT"},
275 {E1000_TXDCTL(0), "TXDCTL"},
276 {E1000_TDFH, "TDFH"},
277 {E1000_TDFT, "TDFT"},
278 {E1000_TDFHS, "TDFHS"},
279 {E1000_TDFPC, "TDFPC"},
281 /* List Terminator */
285 /* igb_regdump - register printout routine */
286 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
292 switch (reginfo->ofs) {
294 for (n = 0; n < 4; n++)
295 regs[n] = rd32(E1000_RDLEN(n));
298 for (n = 0; n < 4; n++)
299 regs[n] = rd32(E1000_RDH(n));
302 for (n = 0; n < 4; n++)
303 regs[n] = rd32(E1000_RDT(n));
305 case E1000_RXDCTL(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RXDCTL(n));
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDBAL(n));
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDBAH(n));
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_TDBAL(n));
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_TDBAH(n));
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_TDLEN(n));
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_TDH(n));
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDT(n));
337 case E1000_TXDCTL(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TXDCTL(n));
342 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
346 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
347 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
351 /* igb_dump - Print registers, Tx-rings and Rx-rings */
352 static void igb_dump(struct igb_adapter *adapter)
354 struct net_device *netdev = adapter->netdev;
355 struct e1000_hw *hw = &adapter->hw;
356 struct igb_reg_info *reginfo;
357 struct igb_ring *tx_ring;
358 union e1000_adv_tx_desc *tx_desc;
359 struct my_u0 { __le64 a; __le64 b; } *u0;
360 struct igb_ring *rx_ring;
361 union e1000_adv_rx_desc *rx_desc;
365 if (!netif_msg_hw(adapter))
368 /* Print netdevice Info */
370 dev_info(&adapter->pdev->dev, "Net device Info\n");
371 pr_info("Device Name state trans_start\n");
372 pr_info("%-15s %016lX %016lX\n", netdev->name,
373 netdev->state, dev_trans_start(netdev));
376 /* Print Registers */
377 dev_info(&adapter->pdev->dev, "Register Dump\n");
378 pr_info(" Register Name Value\n");
379 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
380 reginfo->name; reginfo++) {
381 igb_regdump(hw, reginfo);
384 /* Print TX Ring Summary */
385 if (!netdev || !netif_running(netdev))
388 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
389 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
390 for (n = 0; n < adapter->num_tx_queues; n++) {
391 struct igb_tx_buffer *buffer_info;
392 tx_ring = adapter->tx_ring[n];
393 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
394 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
395 n, tx_ring->next_to_use, tx_ring->next_to_clean,
396 (u64)dma_unmap_addr(buffer_info, dma),
397 dma_unmap_len(buffer_info, len),
398 buffer_info->next_to_watch,
399 (u64)buffer_info->time_stamp);
403 if (!netif_msg_tx_done(adapter))
404 goto rx_ring_summary;
406 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
408 /* Transmit Descriptor Formats
410 * Advanced Transmit Descriptor
411 * +--------------------------------------------------------------+
412 * 0 | Buffer Address [63:0] |
413 * +--------------------------------------------------------------+
414 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
415 * +--------------------------------------------------------------+
416 * 63 46 45 40 39 38 36 35 32 31 24 15 0
419 for (n = 0; n < adapter->num_tx_queues; n++) {
420 tx_ring = adapter->tx_ring[n];
421 pr_info("------------------------------------\n");
422 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
423 pr_info("------------------------------------\n");
424 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
426 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
427 const char *next_desc;
428 struct igb_tx_buffer *buffer_info;
429 tx_desc = IGB_TX_DESC(tx_ring, i);
430 buffer_info = &tx_ring->tx_buffer_info[i];
431 u0 = (struct my_u0 *)tx_desc;
432 if (i == tx_ring->next_to_use &&
433 i == tx_ring->next_to_clean)
434 next_desc = " NTC/U";
435 else if (i == tx_ring->next_to_use)
437 else if (i == tx_ring->next_to_clean)
442 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
443 i, le64_to_cpu(u0->a),
445 (u64)dma_unmap_addr(buffer_info, dma),
446 dma_unmap_len(buffer_info, len),
447 buffer_info->next_to_watch,
448 (u64)buffer_info->time_stamp,
449 buffer_info->skb, next_desc);
451 if (netif_msg_pktdata(adapter) && buffer_info->skb)
452 print_hex_dump(KERN_INFO, "",
454 16, 1, buffer_info->skb->data,
455 dma_unmap_len(buffer_info, len),
460 /* Print RX Rings Summary */
462 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
463 pr_info("Queue [NTU] [NTC]\n");
464 for (n = 0; n < adapter->num_rx_queues; n++) {
465 rx_ring = adapter->rx_ring[n];
466 pr_info(" %5d %5X %5X\n",
467 n, rx_ring->next_to_use, rx_ring->next_to_clean);
471 if (!netif_msg_rx_status(adapter))
474 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
476 /* Advanced Receive Descriptor (Read) Format
478 * +-----------------------------------------------------+
479 * 0 | Packet Buffer Address [63:1] |A0/NSE|
480 * +----------------------------------------------+------+
481 * 8 | Header Buffer Address [63:1] | DD |
482 * +-----------------------------------------------------+
485 * Advanced Receive Descriptor (Write-Back) Format
487 * 63 48 47 32 31 30 21 20 17 16 4 3 0
488 * +------------------------------------------------------+
489 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
490 * | Checksum Ident | | | | Type | Type |
491 * +------------------------------------------------------+
492 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
493 * +------------------------------------------------------+
494 * 63 48 47 32 31 20 19 0
497 for (n = 0; n < adapter->num_rx_queues; n++) {
498 rx_ring = adapter->rx_ring[n];
499 pr_info("------------------------------------\n");
500 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
501 pr_info("------------------------------------\n");
502 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
503 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
505 for (i = 0; i < rx_ring->count; i++) {
506 const char *next_desc;
507 struct igb_rx_buffer *buffer_info;
508 buffer_info = &rx_ring->rx_buffer_info[i];
509 rx_desc = IGB_RX_DESC(rx_ring, i);
510 u0 = (struct my_u0 *)rx_desc;
511 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
513 if (i == rx_ring->next_to_use)
515 else if (i == rx_ring->next_to_clean)
520 if (staterr & E1000_RXD_STAT_DD) {
521 /* Descriptor Done */
522 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
528 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
532 (u64)buffer_info->dma,
535 if (netif_msg_pktdata(adapter) &&
536 buffer_info->dma && buffer_info->page) {
537 print_hex_dump(KERN_INFO, "",
540 page_address(buffer_info->page) +
541 buffer_info->page_offset,
542 igb_rx_bufsz(rx_ring), true);
553 * igb_get_i2c_data - Reads the I2C SDA data bit
554 * @data: opaque pointer to adapter struct
556 * Returns the I2C data bit value
558 static int igb_get_i2c_data(void *data)
560 struct igb_adapter *adapter = (struct igb_adapter *)data;
561 struct e1000_hw *hw = &adapter->hw;
562 s32 i2cctl = rd32(E1000_I2CPARAMS);
564 return !!(i2cctl & E1000_I2C_DATA_IN);
568 * igb_set_i2c_data - Sets the I2C data bit
569 * @data: pointer to hardware structure
570 * @state: I2C data value (0 or 1) to set
572 * Sets the I2C data bit
574 static void igb_set_i2c_data(void *data, int state)
576 struct igb_adapter *adapter = (struct igb_adapter *)data;
577 struct e1000_hw *hw = &adapter->hw;
578 s32 i2cctl = rd32(E1000_I2CPARAMS);
581 i2cctl |= E1000_I2C_DATA_OUT;
583 i2cctl &= ~E1000_I2C_DATA_OUT;
585 i2cctl &= ~E1000_I2C_DATA_OE_N;
586 i2cctl |= E1000_I2C_CLK_OE_N;
587 wr32(E1000_I2CPARAMS, i2cctl);
593 * igb_set_i2c_clk - Sets the I2C SCL clock
594 * @data: pointer to hardware structure
595 * @state: state to set clock
597 * Sets the I2C clock line to state
599 static void igb_set_i2c_clk(void *data, int state)
601 struct igb_adapter *adapter = (struct igb_adapter *)data;
602 struct e1000_hw *hw = &adapter->hw;
603 s32 i2cctl = rd32(E1000_I2CPARAMS);
606 i2cctl |= E1000_I2C_CLK_OUT;
607 i2cctl &= ~E1000_I2C_CLK_OE_N;
609 i2cctl &= ~E1000_I2C_CLK_OUT;
610 i2cctl &= ~E1000_I2C_CLK_OE_N;
612 wr32(E1000_I2CPARAMS, i2cctl);
617 * igb_get_i2c_clk - Gets the I2C SCL clock state
618 * @data: pointer to hardware structure
620 * Gets the I2C clock state
622 static int igb_get_i2c_clk(void *data)
624 struct igb_adapter *adapter = (struct igb_adapter *)data;
625 struct e1000_hw *hw = &adapter->hw;
626 s32 i2cctl = rd32(E1000_I2CPARAMS);
628 return !!(i2cctl & E1000_I2C_CLK_IN);
631 static const struct i2c_algo_bit_data igb_i2c_algo = {
632 .setsda = igb_set_i2c_data,
633 .setscl = igb_set_i2c_clk,
634 .getsda = igb_get_i2c_data,
635 .getscl = igb_get_i2c_clk,
641 * igb_get_hw_dev - return device
642 * @hw: pointer to hardware structure
644 * used by hardware layer to print debugging information
646 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
648 struct igb_adapter *adapter = hw->back;
649 return adapter->netdev;
653 * igb_init_module - Driver Registration Routine
655 * igb_init_module is the first routine called when the driver is
656 * loaded. All it does is register with the PCI subsystem.
658 static int __init igb_init_module(void)
662 pr_info("%s\n", igb_driver_string);
663 pr_info("%s\n", igb_copyright);
665 #ifdef CONFIG_IGB_DCA
666 dca_register_notify(&dca_notifier);
668 ret = pci_register_driver(&igb_driver);
672 module_init(igb_init_module);
675 * igb_exit_module - Driver Exit Cleanup Routine
677 * igb_exit_module is called just before the driver is removed
680 static void __exit igb_exit_module(void)
682 #ifdef CONFIG_IGB_DCA
683 dca_unregister_notify(&dca_notifier);
685 pci_unregister_driver(&igb_driver);
688 module_exit(igb_exit_module);
690 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
692 * igb_cache_ring_register - Descriptor ring to register mapping
693 * @adapter: board private structure to initialize
695 * Once we know the feature-set enabled for the device, we'll cache
696 * the register offset the descriptor ring is assigned to.
698 static void igb_cache_ring_register(struct igb_adapter *adapter)
701 u32 rbase_offset = adapter->vfs_allocated_count;
703 switch (adapter->hw.mac.type) {
705 /* The queues are allocated for virtualization such that VF 0
706 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
707 * In order to avoid collision we start at the first free queue
708 * and continue consuming queues in the same sequence
710 if (adapter->vfs_allocated_count) {
711 for (; i < adapter->rss_queues; i++)
712 adapter->rx_ring[i]->reg_idx = rbase_offset +
723 for (; i < adapter->num_rx_queues; i++)
724 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
725 for (; j < adapter->num_tx_queues; j++)
726 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
731 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
733 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
734 u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr);
737 if (E1000_REMOVED(hw_addr))
740 value = readl(&hw_addr[reg]);
742 /* reads should not return all F's */
743 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
744 struct net_device *netdev = igb->netdev;
746 netdev_err(netdev, "PCIe link lost\n");
747 WARN(pci_device_is_present(igb->pdev),
748 "igb: Failed to read reg 0x%x!\n", reg);
755 * igb_write_ivar - configure ivar for given MSI-X vector
756 * @hw: pointer to the HW structure
757 * @msix_vector: vector number we are allocating to a given ring
758 * @index: row index of IVAR register to write within IVAR table
759 * @offset: column offset of in IVAR, should be multiple of 8
761 * This function is intended to handle the writing of the IVAR register
762 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
763 * each containing an cause allocation for an Rx and Tx ring, and a
764 * variable number of rows depending on the number of queues supported.
766 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
767 int index, int offset)
769 u32 ivar = array_rd32(E1000_IVAR0, index);
771 /* clear any bits that are currently set */
772 ivar &= ~((u32)0xFF << offset);
774 /* write vector and valid bit */
775 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
777 array_wr32(E1000_IVAR0, index, ivar);
780 #define IGB_N0_QUEUE -1
781 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
783 struct igb_adapter *adapter = q_vector->adapter;
784 struct e1000_hw *hw = &adapter->hw;
785 int rx_queue = IGB_N0_QUEUE;
786 int tx_queue = IGB_N0_QUEUE;
789 if (q_vector->rx.ring)
790 rx_queue = q_vector->rx.ring->reg_idx;
791 if (q_vector->tx.ring)
792 tx_queue = q_vector->tx.ring->reg_idx;
794 switch (hw->mac.type) {
796 /* The 82575 assigns vectors using a bitmask, which matches the
797 * bitmask for the EICR/EIMS/EIMC registers. To assign one
798 * or more queues to a vector, we write the appropriate bits
799 * into the MSIXBM register for that vector.
801 if (rx_queue > IGB_N0_QUEUE)
802 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
803 if (tx_queue > IGB_N0_QUEUE)
804 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
805 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
806 msixbm |= E1000_EIMS_OTHER;
807 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
808 q_vector->eims_value = msixbm;
811 /* 82576 uses a table that essentially consists of 2 columns
812 * with 8 rows. The ordering is column-major so we use the
813 * lower 3 bits as the row index, and the 4th bit as the
816 if (rx_queue > IGB_N0_QUEUE)
817 igb_write_ivar(hw, msix_vector,
819 (rx_queue & 0x8) << 1);
820 if (tx_queue > IGB_N0_QUEUE)
821 igb_write_ivar(hw, msix_vector,
823 ((tx_queue & 0x8) << 1) + 8);
824 q_vector->eims_value = BIT(msix_vector);
831 /* On 82580 and newer adapters the scheme is similar to 82576
832 * however instead of ordering column-major we have things
833 * ordered row-major. So we traverse the table by using
834 * bit 0 as the column offset, and the remaining bits as the
837 if (rx_queue > IGB_N0_QUEUE)
838 igb_write_ivar(hw, msix_vector,
840 (rx_queue & 0x1) << 4);
841 if (tx_queue > IGB_N0_QUEUE)
842 igb_write_ivar(hw, msix_vector,
844 ((tx_queue & 0x1) << 4) + 8);
845 q_vector->eims_value = BIT(msix_vector);
852 /* add q_vector eims value to global eims_enable_mask */
853 adapter->eims_enable_mask |= q_vector->eims_value;
855 /* configure q_vector to set itr on first interrupt */
856 q_vector->set_itr = 1;
860 * igb_configure_msix - Configure MSI-X hardware
861 * @adapter: board private structure to initialize
863 * igb_configure_msix sets up the hardware to properly
864 * generate MSI-X interrupts.
866 static void igb_configure_msix(struct igb_adapter *adapter)
870 struct e1000_hw *hw = &adapter->hw;
872 adapter->eims_enable_mask = 0;
874 /* set vector for other causes, i.e. link changes */
875 switch (hw->mac.type) {
877 tmp = rd32(E1000_CTRL_EXT);
878 /* enable MSI-X PBA support*/
879 tmp |= E1000_CTRL_EXT_PBA_CLR;
881 /* Auto-Mask interrupts upon ICR read. */
882 tmp |= E1000_CTRL_EXT_EIAME;
883 tmp |= E1000_CTRL_EXT_IRCA;
885 wr32(E1000_CTRL_EXT, tmp);
887 /* enable msix_other interrupt */
888 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
889 adapter->eims_other = E1000_EIMS_OTHER;
899 /* Turn on MSI-X capability first, or our settings
900 * won't stick. And it will take days to debug.
902 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
903 E1000_GPIE_PBA | E1000_GPIE_EIAME |
906 /* enable msix_other interrupt */
907 adapter->eims_other = BIT(vector);
908 tmp = (vector++ | E1000_IVAR_VALID) << 8;
910 wr32(E1000_IVAR_MISC, tmp);
913 /* do nothing, since nothing else supports MSI-X */
915 } /* switch (hw->mac.type) */
917 adapter->eims_enable_mask |= adapter->eims_other;
919 for (i = 0; i < adapter->num_q_vectors; i++)
920 igb_assign_vector(adapter->q_vector[i], vector++);
926 * igb_request_msix - Initialize MSI-X interrupts
927 * @adapter: board private structure to initialize
929 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
932 static int igb_request_msix(struct igb_adapter *adapter)
934 unsigned int num_q_vectors = adapter->num_q_vectors;
935 struct net_device *netdev = adapter->netdev;
936 int i, err = 0, vector = 0, free_vector = 0;
938 err = request_irq(adapter->msix_entries[vector].vector,
939 igb_msix_other, 0, netdev->name, adapter);
943 if (num_q_vectors > MAX_Q_VECTORS) {
944 num_q_vectors = MAX_Q_VECTORS;
945 dev_warn(&adapter->pdev->dev,
946 "The number of queue vectors (%d) is higher than max allowed (%d)\n",
947 adapter->num_q_vectors, MAX_Q_VECTORS);
949 for (i = 0; i < num_q_vectors; i++) {
950 struct igb_q_vector *q_vector = adapter->q_vector[i];
954 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
956 if (q_vector->rx.ring && q_vector->tx.ring)
957 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
958 q_vector->rx.ring->queue_index);
959 else if (q_vector->tx.ring)
960 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
961 q_vector->tx.ring->queue_index);
962 else if (q_vector->rx.ring)
963 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
964 q_vector->rx.ring->queue_index);
966 sprintf(q_vector->name, "%s-unused", netdev->name);
968 err = request_irq(adapter->msix_entries[vector].vector,
969 igb_msix_ring, 0, q_vector->name,
975 igb_configure_msix(adapter);
979 /* free already assigned IRQs */
980 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
983 for (i = 0; i < vector; i++) {
984 free_irq(adapter->msix_entries[free_vector++].vector,
985 adapter->q_vector[i]);
992 * igb_free_q_vector - Free memory allocated for specific interrupt vector
993 * @adapter: board private structure to initialize
994 * @v_idx: Index of vector to be freed
996 * This function frees the memory allocated to the q_vector.
998 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1000 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1002 adapter->q_vector[v_idx] = NULL;
1004 /* igb_get_stats64() might access the rings on this vector,
1005 * we must wait a grace period before freeing it.
1008 kfree_rcu(q_vector, rcu);
1012 * igb_reset_q_vector - Reset config for interrupt vector
1013 * @adapter: board private structure to initialize
1014 * @v_idx: Index of vector to be reset
1016 * If NAPI is enabled it will delete any references to the
1017 * NAPI struct. This is preparation for igb_free_q_vector.
1019 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1021 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1023 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1024 * allocated. So, q_vector is NULL so we should stop here.
1029 if (q_vector->tx.ring)
1030 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1032 if (q_vector->rx.ring)
1033 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1035 netif_napi_del(&q_vector->napi);
1039 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1041 int v_idx = adapter->num_q_vectors;
1043 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1044 pci_disable_msix(adapter->pdev);
1045 else if (adapter->flags & IGB_FLAG_HAS_MSI)
1046 pci_disable_msi(adapter->pdev);
1049 igb_reset_q_vector(adapter, v_idx);
1053 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1054 * @adapter: board private structure to initialize
1056 * This function frees the memory allocated to the q_vectors. In addition if
1057 * NAPI is enabled it will delete any references to the NAPI struct prior
1058 * to freeing the q_vector.
1060 static void igb_free_q_vectors(struct igb_adapter *adapter)
1062 int v_idx = adapter->num_q_vectors;
1064 adapter->num_tx_queues = 0;
1065 adapter->num_rx_queues = 0;
1066 adapter->num_q_vectors = 0;
1069 igb_reset_q_vector(adapter, v_idx);
1070 igb_free_q_vector(adapter, v_idx);
1075 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1076 * @adapter: board private structure to initialize
1078 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1079 * MSI-X interrupts allocated.
1081 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1083 igb_free_q_vectors(adapter);
1084 igb_reset_interrupt_capability(adapter);
1088 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1089 * @adapter: board private structure to initialize
1090 * @msix: boolean value of MSIX capability
1092 * Attempt to configure interrupts using the best available
1093 * capabilities of the hardware and kernel.
1095 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1102 adapter->flags |= IGB_FLAG_HAS_MSIX;
1104 /* Number of supported queues. */
1105 adapter->num_rx_queues = adapter->rss_queues;
1106 if (adapter->vfs_allocated_count)
1107 adapter->num_tx_queues = 1;
1109 adapter->num_tx_queues = adapter->rss_queues;
1111 /* start with one vector for every Rx queue */
1112 numvecs = adapter->num_rx_queues;
1114 /* if Tx handler is separate add 1 for every Tx queue */
1115 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1116 numvecs += adapter->num_tx_queues;
1118 /* store the number of vectors reserved for queues */
1119 adapter->num_q_vectors = numvecs;
1121 /* add 1 vector for link status interrupts */
1123 for (i = 0; i < numvecs; i++)
1124 adapter->msix_entries[i].entry = i;
1126 err = pci_enable_msix_range(adapter->pdev,
1127 adapter->msix_entries,
1133 igb_reset_interrupt_capability(adapter);
1135 /* If we can't do MSI-X, try MSI */
1137 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1138 #ifdef CONFIG_PCI_IOV
1139 /* disable SR-IOV for non MSI-X configurations */
1140 if (adapter->vf_data) {
1141 struct e1000_hw *hw = &adapter->hw;
1142 /* disable iov and allow time for transactions to clear */
1143 pci_disable_sriov(adapter->pdev);
1146 kfree(adapter->vf_mac_list);
1147 adapter->vf_mac_list = NULL;
1148 kfree(adapter->vf_data);
1149 adapter->vf_data = NULL;
1150 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1153 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1156 adapter->vfs_allocated_count = 0;
1157 adapter->rss_queues = 1;
1158 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1159 adapter->num_rx_queues = 1;
1160 adapter->num_tx_queues = 1;
1161 adapter->num_q_vectors = 1;
1162 if (!pci_enable_msi(adapter->pdev))
1163 adapter->flags |= IGB_FLAG_HAS_MSI;
1166 static void igb_add_ring(struct igb_ring *ring,
1167 struct igb_ring_container *head)
1174 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1175 * @adapter: board private structure to initialize
1176 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1177 * @v_idx: index of vector in adapter struct
1178 * @txr_count: total number of Tx rings to allocate
1179 * @txr_idx: index of first Tx ring to allocate
1180 * @rxr_count: total number of Rx rings to allocate
1181 * @rxr_idx: index of first Rx ring to allocate
1183 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1185 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1186 int v_count, int v_idx,
1187 int txr_count, int txr_idx,
1188 int rxr_count, int rxr_idx)
1190 struct igb_q_vector *q_vector;
1191 struct igb_ring *ring;
1195 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1196 if (txr_count > 1 || rxr_count > 1)
1199 ring_count = txr_count + rxr_count;
1200 size = struct_size(q_vector, ring, ring_count);
1202 /* allocate q_vector and rings */
1203 q_vector = adapter->q_vector[v_idx];
1205 q_vector = kzalloc(size, GFP_KERNEL);
1206 } else if (size > ksize(q_vector)) {
1207 kfree_rcu(q_vector, rcu);
1208 q_vector = kzalloc(size, GFP_KERNEL);
1210 memset(q_vector, 0, size);
1215 /* initialize NAPI */
1216 netif_napi_add(adapter->netdev, &q_vector->napi,
1219 /* tie q_vector and adapter together */
1220 adapter->q_vector[v_idx] = q_vector;
1221 q_vector->adapter = adapter;
1223 /* initialize work limits */
1224 q_vector->tx.work_limit = adapter->tx_work_limit;
1226 /* initialize ITR configuration */
1227 q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
1228 q_vector->itr_val = IGB_START_ITR;
1230 /* initialize pointer to rings */
1231 ring = q_vector->ring;
1235 /* rx or rx/tx vector */
1236 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1237 q_vector->itr_val = adapter->rx_itr_setting;
1239 /* tx only vector */
1240 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1241 q_vector->itr_val = adapter->tx_itr_setting;
1245 /* assign generic ring traits */
1246 ring->dev = &adapter->pdev->dev;
1247 ring->netdev = adapter->netdev;
1249 /* configure backlink on ring */
1250 ring->q_vector = q_vector;
1252 /* update q_vector Tx values */
1253 igb_add_ring(ring, &q_vector->tx);
1255 /* For 82575, context index must be unique per ring. */
1256 if (adapter->hw.mac.type == e1000_82575)
1257 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1259 /* apply Tx specific ring traits */
1260 ring->count = adapter->tx_ring_count;
1261 ring->queue_index = txr_idx;
1263 ring->cbs_enable = false;
1264 ring->idleslope = 0;
1265 ring->sendslope = 0;
1269 u64_stats_init(&ring->tx_syncp);
1270 u64_stats_init(&ring->tx_syncp2);
1272 /* assign ring to adapter */
1273 adapter->tx_ring[txr_idx] = ring;
1275 /* push pointer to next ring */
1280 /* assign generic ring traits */
1281 ring->dev = &adapter->pdev->dev;
1282 ring->netdev = adapter->netdev;
1284 /* configure backlink on ring */
1285 ring->q_vector = q_vector;
1287 /* update q_vector Rx values */
1288 igb_add_ring(ring, &q_vector->rx);
1290 /* set flag indicating ring supports SCTP checksum offload */
1291 if (adapter->hw.mac.type >= e1000_82576)
1292 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1294 /* On i350, i354, i210, and i211, loopback VLAN packets
1295 * have the tag byte-swapped.
1297 if (adapter->hw.mac.type >= e1000_i350)
1298 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1300 /* apply Rx specific ring traits */
1301 ring->count = adapter->rx_ring_count;
1302 ring->queue_index = rxr_idx;
1304 u64_stats_init(&ring->rx_syncp);
1306 /* assign ring to adapter */
1307 adapter->rx_ring[rxr_idx] = ring;
1315 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1316 * @adapter: board private structure to initialize
1318 * We allocate one q_vector per queue interrupt. If allocation fails we
1321 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1323 int q_vectors = adapter->num_q_vectors;
1324 int rxr_remaining = adapter->num_rx_queues;
1325 int txr_remaining = adapter->num_tx_queues;
1326 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1329 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1330 for (; rxr_remaining; v_idx++) {
1331 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1337 /* update counts and index */
1343 for (; v_idx < q_vectors; v_idx++) {
1344 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1345 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1347 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1348 tqpv, txr_idx, rqpv, rxr_idx);
1353 /* update counts and index */
1354 rxr_remaining -= rqpv;
1355 txr_remaining -= tqpv;
1363 adapter->num_tx_queues = 0;
1364 adapter->num_rx_queues = 0;
1365 adapter->num_q_vectors = 0;
1368 igb_free_q_vector(adapter, v_idx);
1374 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1375 * @adapter: board private structure to initialize
1376 * @msix: boolean value of MSIX capability
1378 * This function initializes the interrupts and allocates all of the queues.
1380 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1382 struct pci_dev *pdev = adapter->pdev;
1385 igb_set_interrupt_capability(adapter, msix);
1387 err = igb_alloc_q_vectors(adapter);
1389 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1390 goto err_alloc_q_vectors;
1393 igb_cache_ring_register(adapter);
1397 err_alloc_q_vectors:
1398 igb_reset_interrupt_capability(adapter);
1403 * igb_request_irq - initialize interrupts
1404 * @adapter: board private structure to initialize
1406 * Attempts to configure interrupts using the best available
1407 * capabilities of the hardware and kernel.
1409 static int igb_request_irq(struct igb_adapter *adapter)
1411 struct net_device *netdev = adapter->netdev;
1412 struct pci_dev *pdev = adapter->pdev;
1415 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1416 err = igb_request_msix(adapter);
1419 /* fall back to MSI */
1420 igb_free_all_tx_resources(adapter);
1421 igb_free_all_rx_resources(adapter);
1423 igb_clear_interrupt_scheme(adapter);
1424 err = igb_init_interrupt_scheme(adapter, false);
1428 igb_setup_all_tx_resources(adapter);
1429 igb_setup_all_rx_resources(adapter);
1430 igb_configure(adapter);
1433 igb_assign_vector(adapter->q_vector[0], 0);
1435 if (adapter->flags & IGB_FLAG_HAS_MSI) {
1436 err = request_irq(pdev->irq, igb_intr_msi, 0,
1437 netdev->name, adapter);
1441 /* fall back to legacy interrupts */
1442 igb_reset_interrupt_capability(adapter);
1443 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1446 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1447 netdev->name, adapter);
1450 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1457 static void igb_free_irq(struct igb_adapter *adapter)
1459 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1462 free_irq(adapter->msix_entries[vector++].vector, adapter);
1464 for (i = 0; i < adapter->num_q_vectors; i++)
1465 free_irq(adapter->msix_entries[vector++].vector,
1466 adapter->q_vector[i]);
1468 free_irq(adapter->pdev->irq, adapter);
1473 * igb_irq_disable - Mask off interrupt generation on the NIC
1474 * @adapter: board private structure
1476 static void igb_irq_disable(struct igb_adapter *adapter)
1478 struct e1000_hw *hw = &adapter->hw;
1480 /* we need to be careful when disabling interrupts. The VFs are also
1481 * mapped into these registers and so clearing the bits can cause
1482 * issues on the VF drivers so we only need to clear what we set
1484 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1485 u32 regval = rd32(E1000_EIAM);
1487 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1488 wr32(E1000_EIMC, adapter->eims_enable_mask);
1489 regval = rd32(E1000_EIAC);
1490 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1494 wr32(E1000_IMC, ~0);
1496 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1499 for (i = 0; i < adapter->num_q_vectors; i++)
1500 synchronize_irq(adapter->msix_entries[i].vector);
1502 synchronize_irq(adapter->pdev->irq);
1507 * igb_irq_enable - Enable default interrupt generation settings
1508 * @adapter: board private structure
1510 static void igb_irq_enable(struct igb_adapter *adapter)
1512 struct e1000_hw *hw = &adapter->hw;
1514 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1515 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1516 u32 regval = rd32(E1000_EIAC);
1518 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1519 regval = rd32(E1000_EIAM);
1520 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1521 wr32(E1000_EIMS, adapter->eims_enable_mask);
1522 if (adapter->vfs_allocated_count) {
1523 wr32(E1000_MBVFIMR, 0xFF);
1524 ims |= E1000_IMS_VMMB;
1526 wr32(E1000_IMS, ims);
1528 wr32(E1000_IMS, IMS_ENABLE_MASK |
1530 wr32(E1000_IAM, IMS_ENABLE_MASK |
1535 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1537 struct e1000_hw *hw = &adapter->hw;
1538 u16 pf_id = adapter->vfs_allocated_count;
1539 u16 vid = adapter->hw.mng_cookie.vlan_id;
1540 u16 old_vid = adapter->mng_vlan_id;
1542 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1543 /* add VID to filter table */
1544 igb_vfta_set(hw, vid, pf_id, true, true);
1545 adapter->mng_vlan_id = vid;
1547 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1550 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1552 !test_bit(old_vid, adapter->active_vlans)) {
1553 /* remove VID from filter table */
1554 igb_vfta_set(hw, vid, pf_id, false, true);
1559 * igb_release_hw_control - release control of the h/w to f/w
1560 * @adapter: address of board private structure
1562 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1563 * For ASF and Pass Through versions of f/w this means that the
1564 * driver is no longer loaded.
1566 static void igb_release_hw_control(struct igb_adapter *adapter)
1568 struct e1000_hw *hw = &adapter->hw;
1571 /* Let firmware take over control of h/w */
1572 ctrl_ext = rd32(E1000_CTRL_EXT);
1573 wr32(E1000_CTRL_EXT,
1574 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1578 * igb_get_hw_control - get control of the h/w from f/w
1579 * @adapter: address of board private structure
1581 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1582 * For ASF and Pass Through versions of f/w this means that
1583 * the driver is loaded.
1585 static void igb_get_hw_control(struct igb_adapter *adapter)
1587 struct e1000_hw *hw = &adapter->hw;
1590 /* Let firmware know the driver has taken over */
1591 ctrl_ext = rd32(E1000_CTRL_EXT);
1592 wr32(E1000_CTRL_EXT,
1593 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1596 static void enable_fqtss(struct igb_adapter *adapter, bool enable)
1598 struct net_device *netdev = adapter->netdev;
1599 struct e1000_hw *hw = &adapter->hw;
1601 WARN_ON(hw->mac.type != e1000_i210);
1604 adapter->flags |= IGB_FLAG_FQTSS;
1606 adapter->flags &= ~IGB_FLAG_FQTSS;
1608 if (netif_running(netdev))
1609 schedule_work(&adapter->reset_task);
1612 static bool is_fqtss_enabled(struct igb_adapter *adapter)
1614 return (adapter->flags & IGB_FLAG_FQTSS) ? true : false;
1617 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue,
1618 enum tx_queue_prio prio)
1622 WARN_ON(hw->mac.type != e1000_i210);
1623 WARN_ON(queue < 0 || queue > 4);
1625 val = rd32(E1000_I210_TXDCTL(queue));
1627 if (prio == TX_QUEUE_PRIO_HIGH)
1628 val |= E1000_TXDCTL_PRIORITY;
1630 val &= ~E1000_TXDCTL_PRIORITY;
1632 wr32(E1000_I210_TXDCTL(queue), val);
1635 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode)
1639 WARN_ON(hw->mac.type != e1000_i210);
1640 WARN_ON(queue < 0 || queue > 1);
1642 val = rd32(E1000_I210_TQAVCC(queue));
1644 if (mode == QUEUE_MODE_STREAM_RESERVATION)
1645 val |= E1000_TQAVCC_QUEUEMODE;
1647 val &= ~E1000_TQAVCC_QUEUEMODE;
1649 wr32(E1000_I210_TQAVCC(queue), val);
1652 static bool is_any_cbs_enabled(struct igb_adapter *adapter)
1656 for (i = 0; i < adapter->num_tx_queues; i++) {
1657 if (adapter->tx_ring[i]->cbs_enable)
1664 static bool is_any_txtime_enabled(struct igb_adapter *adapter)
1668 for (i = 0; i < adapter->num_tx_queues; i++) {
1669 if (adapter->tx_ring[i]->launchtime_enable)
1677 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb
1678 * @adapter: pointer to adapter struct
1679 * @queue: queue number
1681 * Configure CBS and Launchtime for a given hardware queue.
1682 * Parameters are retrieved from the correct Tx ring, so
1683 * igb_save_cbs_params() and igb_save_txtime_params() should be used
1684 * for setting those correctly prior to this function being called.
1686 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue)
1688 struct net_device *netdev = adapter->netdev;
1689 struct e1000_hw *hw = &adapter->hw;
1690 struct igb_ring *ring;
1691 u32 tqavcc, tqavctrl;
1694 WARN_ON(hw->mac.type != e1000_i210);
1695 WARN_ON(queue < 0 || queue > 1);
1696 ring = adapter->tx_ring[queue];
1698 /* If any of the Qav features is enabled, configure queues as SR and
1699 * with HIGH PRIO. If none is, then configure them with LOW PRIO and
1702 if (ring->cbs_enable || ring->launchtime_enable) {
1703 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH);
1704 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION);
1706 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW);
1707 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY);
1710 /* If CBS is enabled, set DataTranARB and config its parameters. */
1711 if (ring->cbs_enable || queue == 0) {
1712 /* i210 does not allow the queue 0 to be in the Strict
1713 * Priority mode while the Qav mode is enabled, so,
1714 * instead of disabling strict priority mode, we give
1715 * queue 0 the maximum of credits possible.
1717 * See section 8.12.19 of the i210 datasheet, "Note:
1718 * Queue0 QueueMode must be set to 1b when
1719 * TransmitMode is set to Qav."
1721 if (queue == 0 && !ring->cbs_enable) {
1722 /* max "linkspeed" idleslope in kbps */
1723 ring->idleslope = 1000000;
1724 ring->hicredit = ETH_FRAME_LEN;
1727 /* Always set data transfer arbitration to credit-based
1728 * shaper algorithm on TQAVCTRL if CBS is enabled for any of
1731 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1732 tqavctrl |= E1000_TQAVCTRL_DATATRANARB;
1733 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1735 /* According to i210 datasheet section 7.2.7.7, we should set
1736 * the 'idleSlope' field from TQAVCC register following the
1739 * For 100 Mbps link speed:
1741 * value = BW * 0x7735 * 0.2 (E1)
1743 * For 1000Mbps link speed:
1745 * value = BW * 0x7735 * 2 (E2)
1747 * E1 and E2 can be merged into one equation as shown below.
1748 * Note that 'link-speed' is in Mbps.
1750 * value = BW * 0x7735 * 2 * link-speed
1751 * -------------- (E3)
1754 * 'BW' is the percentage bandwidth out of full link speed
1755 * which can be found with the following equation. Note that
1756 * idleSlope here is the parameter from this function which
1760 * ----------------- (E4)
1763 * That said, we can come up with a generic equation to
1764 * calculate the value we should set it TQAVCC register by
1765 * replacing 'BW' in E3 by E4. The resulting equation is:
1767 * value = idleSlope * 0x7735 * 2 * link-speed
1768 * ----------------- -------------- (E5)
1769 * link-speed * 1000 1000
1771 * 'link-speed' is present in both sides of the fraction so
1772 * it is canceled out. The final equation is the following:
1774 * value = idleSlope * 61034
1775 * ----------------- (E6)
1778 * NOTE: For i210, given the above, we can see that idleslope
1779 * is represented in 16.38431 kbps units by the value at
1780 * the TQAVCC register (1Gbps / 61034), which reduces
1781 * the granularity for idleslope increments.
1782 * For instance, if you want to configure a 2576kbps
1783 * idleslope, the value to be written on the register
1784 * would have to be 157.23. If rounded down, you end
1785 * up with less bandwidth available than originally
1786 * required (~2572 kbps). If rounded up, you end up
1787 * with a higher bandwidth (~2589 kbps). Below the
1788 * approach we take is to always round up the
1789 * calculated value, so the resulting bandwidth might
1790 * be slightly higher for some configurations.
1792 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000);
1794 tqavcc = rd32(E1000_I210_TQAVCC(queue));
1795 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1797 wr32(E1000_I210_TQAVCC(queue), tqavcc);
1799 wr32(E1000_I210_TQAVHC(queue),
1800 0x80000000 + ring->hicredit * 0x7735);
1803 /* Set idleSlope to zero. */
1804 tqavcc = rd32(E1000_I210_TQAVCC(queue));
1805 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1806 wr32(E1000_I210_TQAVCC(queue), tqavcc);
1808 /* Set hiCredit to zero. */
1809 wr32(E1000_I210_TQAVHC(queue), 0);
1811 /* If CBS is not enabled for any queues anymore, then return to
1812 * the default state of Data Transmission Arbitration on
1815 if (!is_any_cbs_enabled(adapter)) {
1816 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1817 tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB;
1818 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1822 /* If LaunchTime is enabled, set DataTranTIM. */
1823 if (ring->launchtime_enable) {
1824 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled
1825 * for any of the SR queues, and configure fetchtime delta.
1827 * - LaunchTime will be enabled for all SR queues.
1828 * - A fixed offset can be added relative to the launch
1829 * time of all packets if configured at reg LAUNCH_OS0.
1830 * We are keeping it as 0 for now (default value).
1832 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1833 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM |
1834 E1000_TQAVCTRL_FETCHTIME_DELTA;
1835 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1837 /* If Launchtime is not enabled for any SR queues anymore,
1838 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta,
1839 * effectively disabling Launchtime.
1841 if (!is_any_txtime_enabled(adapter)) {
1842 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1843 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM;
1844 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA;
1845 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1849 /* XXX: In i210 controller the sendSlope and loCredit parameters from
1850 * CBS are not configurable by software so we don't do any 'controller
1851 * configuration' in respect to these parameters.
1854 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n",
1855 ring->cbs_enable ? "enabled" : "disabled",
1856 ring->launchtime_enable ? "enabled" : "disabled",
1858 ring->idleslope, ring->sendslope,
1859 ring->hicredit, ring->locredit);
1862 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue,
1865 struct igb_ring *ring;
1867 if (queue < 0 || queue > adapter->num_tx_queues)
1870 ring = adapter->tx_ring[queue];
1871 ring->launchtime_enable = enable;
1876 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue,
1877 bool enable, int idleslope, int sendslope,
1878 int hicredit, int locredit)
1880 struct igb_ring *ring;
1882 if (queue < 0 || queue > adapter->num_tx_queues)
1885 ring = adapter->tx_ring[queue];
1887 ring->cbs_enable = enable;
1888 ring->idleslope = idleslope;
1889 ring->sendslope = sendslope;
1890 ring->hicredit = hicredit;
1891 ring->locredit = locredit;
1897 * igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable
1898 * @adapter: pointer to adapter struct
1900 * Configure TQAVCTRL register switching the controller's Tx mode
1901 * if FQTSS mode is enabled or disabled. Additionally, will issue
1902 * a call to igb_config_tx_modes() per queue so any previously saved
1903 * Tx parameters are applied.
1905 static void igb_setup_tx_mode(struct igb_adapter *adapter)
1907 struct net_device *netdev = adapter->netdev;
1908 struct e1000_hw *hw = &adapter->hw;
1911 /* Only i210 controller supports changing the transmission mode. */
1912 if (hw->mac.type != e1000_i210)
1915 if (is_fqtss_enabled(adapter)) {
1918 /* Configure TQAVCTRL register: set transmit mode to 'Qav',
1919 * set data fetch arbitration to 'round robin', set SP_WAIT_SR
1920 * so SP queues wait for SR ones.
1922 val = rd32(E1000_I210_TQAVCTRL);
1923 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR;
1924 val &= ~E1000_TQAVCTRL_DATAFETCHARB;
1925 wr32(E1000_I210_TQAVCTRL, val);
1927 /* Configure Tx and Rx packet buffers sizes as described in
1928 * i210 datasheet section 7.2.7.7.
1930 val = rd32(E1000_TXPBS);
1931 val &= ~I210_TXPBSIZE_MASK;
1932 val |= I210_TXPBSIZE_PB0_6KB | I210_TXPBSIZE_PB1_6KB |
1933 I210_TXPBSIZE_PB2_6KB | I210_TXPBSIZE_PB3_6KB;
1934 wr32(E1000_TXPBS, val);
1936 val = rd32(E1000_RXPBS);
1937 val &= ~I210_RXPBSIZE_MASK;
1938 val |= I210_RXPBSIZE_PB_30KB;
1939 wr32(E1000_RXPBS, val);
1941 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ
1942 * register should not exceed the buffer size programmed in
1943 * TXPBS. The smallest buffer size programmed in TXPBS is 4kB
1944 * so according to the datasheet we should set MAX_TPKT_SIZE to
1947 * However, when we do so, no frame from queue 2 and 3 are
1948 * transmitted. It seems the MAX_TPKT_SIZE should not be great
1949 * or _equal_ to the buffer size programmed in TXPBS. For this
1950 * reason, we set set MAX_ TPKT_SIZE to (4kB - 1) / 64.
1952 val = (4096 - 1) / 64;
1953 wr32(E1000_I210_DTXMXPKTSZ, val);
1955 /* Since FQTSS mode is enabled, apply any CBS configuration
1956 * previously set. If no previous CBS configuration has been
1957 * done, then the initial configuration is applied, which means
1960 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ?
1961 adapter->num_tx_queues : I210_SR_QUEUES_NUM;
1963 for (i = 0; i < max_queue; i++) {
1964 igb_config_tx_modes(adapter, i);
1967 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
1968 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
1969 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT);
1971 val = rd32(E1000_I210_TQAVCTRL);
1972 /* According to Section 8.12.21, the other flags we've set when
1973 * enabling FQTSS are not relevant when disabling FQTSS so we
1974 * don't set they here.
1976 val &= ~E1000_TQAVCTRL_XMIT_MODE;
1977 wr32(E1000_I210_TQAVCTRL, val);
1980 netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ?
1981 "enabled" : "disabled");
1985 * igb_configure - configure the hardware for RX and TX
1986 * @adapter: private board structure
1988 static void igb_configure(struct igb_adapter *adapter)
1990 struct net_device *netdev = adapter->netdev;
1993 igb_get_hw_control(adapter);
1994 igb_set_rx_mode(netdev);
1995 igb_setup_tx_mode(adapter);
1997 igb_restore_vlan(adapter);
1999 igb_setup_tctl(adapter);
2000 igb_setup_mrqc(adapter);
2001 igb_setup_rctl(adapter);
2003 igb_nfc_filter_restore(adapter);
2004 igb_configure_tx(adapter);
2005 igb_configure_rx(adapter);
2007 igb_rx_fifo_flush_82575(&adapter->hw);
2009 /* call igb_desc_unused which always leaves
2010 * at least 1 descriptor unused to make sure
2011 * next_to_use != next_to_clean
2013 for (i = 0; i < adapter->num_rx_queues; i++) {
2014 struct igb_ring *ring = adapter->rx_ring[i];
2015 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
2020 * igb_power_up_link - Power up the phy/serdes link
2021 * @adapter: address of board private structure
2023 void igb_power_up_link(struct igb_adapter *adapter)
2025 igb_reset_phy(&adapter->hw);
2027 if (adapter->hw.phy.media_type == e1000_media_type_copper)
2028 igb_power_up_phy_copper(&adapter->hw);
2030 igb_power_up_serdes_link_82575(&adapter->hw);
2032 igb_setup_link(&adapter->hw);
2036 * igb_power_down_link - Power down the phy/serdes link
2037 * @adapter: address of board private structure
2039 static void igb_power_down_link(struct igb_adapter *adapter)
2041 if (adapter->hw.phy.media_type == e1000_media_type_copper)
2042 igb_power_down_phy_copper_82575(&adapter->hw);
2044 igb_shutdown_serdes_link_82575(&adapter->hw);
2048 * igb_check_swap_media - Detect and switch function for Media Auto Sense
2049 * @adapter: address of the board private structure
2051 static void igb_check_swap_media(struct igb_adapter *adapter)
2053 struct e1000_hw *hw = &adapter->hw;
2054 u32 ctrl_ext, connsw;
2055 bool swap_now = false;
2057 ctrl_ext = rd32(E1000_CTRL_EXT);
2058 connsw = rd32(E1000_CONNSW);
2060 /* need to live swap if current media is copper and we have fiber/serdes
2064 if ((hw->phy.media_type == e1000_media_type_copper) &&
2065 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
2067 } else if ((hw->phy.media_type != e1000_media_type_copper) &&
2068 !(connsw & E1000_CONNSW_SERDESD)) {
2069 /* copper signal takes time to appear */
2070 if (adapter->copper_tries < 4) {
2071 adapter->copper_tries++;
2072 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
2073 wr32(E1000_CONNSW, connsw);
2076 adapter->copper_tries = 0;
2077 if ((connsw & E1000_CONNSW_PHYSD) &&
2078 (!(connsw & E1000_CONNSW_PHY_PDN))) {
2080 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
2081 wr32(E1000_CONNSW, connsw);
2089 switch (hw->phy.media_type) {
2090 case e1000_media_type_copper:
2091 netdev_info(adapter->netdev,
2092 "MAS: changing media to fiber/serdes\n");
2094 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2095 adapter->flags |= IGB_FLAG_MEDIA_RESET;
2096 adapter->copper_tries = 0;
2098 case e1000_media_type_internal_serdes:
2099 case e1000_media_type_fiber:
2100 netdev_info(adapter->netdev,
2101 "MAS: changing media to copper\n");
2103 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2104 adapter->flags |= IGB_FLAG_MEDIA_RESET;
2107 /* shouldn't get here during regular operation */
2108 netdev_err(adapter->netdev,
2109 "AMS: Invalid media type found, returning\n");
2112 wr32(E1000_CTRL_EXT, ctrl_ext);
2116 * igb_up - Open the interface and prepare it to handle traffic
2117 * @adapter: board private structure
2119 int igb_up(struct igb_adapter *adapter)
2121 struct e1000_hw *hw = &adapter->hw;
2124 /* hardware has been reset, we need to reload some things */
2125 igb_configure(adapter);
2127 clear_bit(__IGB_DOWN, &adapter->state);
2129 for (i = 0; i < adapter->num_q_vectors; i++)
2130 napi_enable(&(adapter->q_vector[i]->napi));
2132 if (adapter->flags & IGB_FLAG_HAS_MSIX)
2133 igb_configure_msix(adapter);
2135 igb_assign_vector(adapter->q_vector[0], 0);
2137 /* Clear any pending interrupts. */
2140 igb_irq_enable(adapter);
2142 /* notify VFs that reset has been completed */
2143 if (adapter->vfs_allocated_count) {
2144 u32 reg_data = rd32(E1000_CTRL_EXT);
2146 reg_data |= E1000_CTRL_EXT_PFRSTD;
2147 wr32(E1000_CTRL_EXT, reg_data);
2150 netif_tx_start_all_queues(adapter->netdev);
2152 /* start the watchdog. */
2153 hw->mac.get_link_status = 1;
2154 schedule_work(&adapter->watchdog_task);
2156 if ((adapter->flags & IGB_FLAG_EEE) &&
2157 (!hw->dev_spec._82575.eee_disable))
2158 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
2163 void igb_down(struct igb_adapter *adapter)
2165 struct net_device *netdev = adapter->netdev;
2166 struct e1000_hw *hw = &adapter->hw;
2170 /* signal that we're down so the interrupt handler does not
2171 * reschedule our watchdog timer
2173 set_bit(__IGB_DOWN, &adapter->state);
2175 /* disable receives in the hardware */
2176 rctl = rd32(E1000_RCTL);
2177 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2178 /* flush and sleep below */
2180 igb_nfc_filter_exit(adapter);
2182 netif_carrier_off(netdev);
2183 netif_tx_stop_all_queues(netdev);
2185 /* disable transmits in the hardware */
2186 tctl = rd32(E1000_TCTL);
2187 tctl &= ~E1000_TCTL_EN;
2188 wr32(E1000_TCTL, tctl);
2189 /* flush both disables and wait for them to finish */
2191 usleep_range(10000, 11000);
2193 igb_irq_disable(adapter);
2195 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
2197 for (i = 0; i < adapter->num_q_vectors; i++) {
2198 if (adapter->q_vector[i]) {
2199 napi_synchronize(&adapter->q_vector[i]->napi);
2200 napi_disable(&adapter->q_vector[i]->napi);
2204 del_timer_sync(&adapter->watchdog_timer);
2205 del_timer_sync(&adapter->phy_info_timer);
2207 /* record the stats before reset*/
2208 spin_lock(&adapter->stats64_lock);
2209 igb_update_stats(adapter);
2210 spin_unlock(&adapter->stats64_lock);
2212 adapter->link_speed = 0;
2213 adapter->link_duplex = 0;
2215 if (!pci_channel_offline(adapter->pdev))
2218 /* clear VLAN promisc flag so VFTA will be updated if necessary */
2219 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
2221 igb_clean_all_tx_rings(adapter);
2222 igb_clean_all_rx_rings(adapter);
2223 #ifdef CONFIG_IGB_DCA
2225 /* since we reset the hardware DCA settings were cleared */
2226 igb_setup_dca(adapter);
2230 void igb_reinit_locked(struct igb_adapter *adapter)
2232 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2233 usleep_range(1000, 2000);
2236 clear_bit(__IGB_RESETTING, &adapter->state);
2239 /** igb_enable_mas - Media Autosense re-enable after swap
2241 * @adapter: adapter struct
2243 static void igb_enable_mas(struct igb_adapter *adapter)
2245 struct e1000_hw *hw = &adapter->hw;
2246 u32 connsw = rd32(E1000_CONNSW);
2248 /* configure for SerDes media detect */
2249 if ((hw->phy.media_type == e1000_media_type_copper) &&
2250 (!(connsw & E1000_CONNSW_SERDESD))) {
2251 connsw |= E1000_CONNSW_ENRGSRC;
2252 connsw |= E1000_CONNSW_AUTOSENSE_EN;
2253 wr32(E1000_CONNSW, connsw);
2258 void igb_reset(struct igb_adapter *adapter)
2260 struct pci_dev *pdev = adapter->pdev;
2261 struct e1000_hw *hw = &adapter->hw;
2262 struct e1000_mac_info *mac = &hw->mac;
2263 struct e1000_fc_info *fc = &hw->fc;
2266 /* Repartition Pba for greater than 9k mtu
2267 * To take effect CTRL.RST is required.
2269 switch (mac->type) {
2273 pba = rd32(E1000_RXPBS);
2274 pba = igb_rxpbs_adjust_82580(pba);
2277 pba = rd32(E1000_RXPBS);
2278 pba &= E1000_RXPBS_SIZE_MASK_82576;
2284 pba = E1000_PBA_34K;
2288 if (mac->type == e1000_82575) {
2289 u32 min_rx_space, min_tx_space, needed_tx_space;
2291 /* write Rx PBA so that hardware can report correct Tx PBA */
2292 wr32(E1000_PBA, pba);
2294 /* To maintain wire speed transmits, the Tx FIFO should be
2295 * large enough to accommodate two full transmit packets,
2296 * rounded up to the next 1KB and expressed in KB. Likewise,
2297 * the Rx FIFO should be large enough to accommodate at least
2298 * one full receive packet and is similarly rounded up and
2301 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
2303 /* The Tx FIFO also stores 16 bytes of information about the Tx
2304 * but don't include Ethernet FCS because hardware appends it.
2305 * We only need to round down to the nearest 512 byte block
2306 * count since the value we care about is 2 frames, not 1.
2308 min_tx_space = adapter->max_frame_size;
2309 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
2310 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
2312 /* upper 16 bits has Tx packet buffer allocation size in KB */
2313 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
2315 /* If current Tx allocation is less than the min Tx FIFO size,
2316 * and the min Tx FIFO size is less than the current Rx FIFO
2317 * allocation, take space away from current Rx allocation.
2319 if (needed_tx_space < pba) {
2320 pba -= needed_tx_space;
2322 /* if short on Rx space, Rx wins and must trump Tx
2325 if (pba < min_rx_space)
2329 /* adjust PBA for jumbo frames */
2330 wr32(E1000_PBA, pba);
2333 /* flow control settings
2334 * The high water mark must be low enough to fit one full frame
2335 * after transmitting the pause frame. As such we must have enough
2336 * space to allow for us to complete our current transmit and then
2337 * receive the frame that is in progress from the link partner.
2339 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
2341 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
2343 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
2344 fc->low_water = fc->high_water - 16;
2345 fc->pause_time = 0xFFFF;
2347 fc->current_mode = fc->requested_mode;
2349 /* disable receive for all VFs and wait one second */
2350 if (adapter->vfs_allocated_count) {
2353 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
2354 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
2356 /* ping all the active vfs to let them know we are going down */
2357 igb_ping_all_vfs(adapter);
2359 /* disable transmits and receives */
2360 wr32(E1000_VFRE, 0);
2361 wr32(E1000_VFTE, 0);
2364 /* Allow time for pending master requests to run */
2365 hw->mac.ops.reset_hw(hw);
2368 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
2369 /* need to resetup here after media swap */
2370 adapter->ei.get_invariants(hw);
2371 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
2373 if ((mac->type == e1000_82575 || mac->type == e1000_i350) &&
2374 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
2375 igb_enable_mas(adapter);
2377 if (hw->mac.ops.init_hw(hw))
2378 dev_err(&pdev->dev, "Hardware Error\n");
2380 /* RAR registers were cleared during init_hw, clear mac table */
2381 igb_flush_mac_table(adapter);
2382 __dev_uc_unsync(adapter->netdev, NULL);
2384 /* Recover default RAR entry */
2385 igb_set_default_mac_filter(adapter);
2387 /* Flow control settings reset on hardware reset, so guarantee flow
2388 * control is off when forcing speed.
2390 if (!hw->mac.autoneg)
2391 igb_force_mac_fc(hw);
2393 igb_init_dmac(adapter, pba);
2394 #ifdef CONFIG_IGB_HWMON
2395 /* Re-initialize the thermal sensor on i350 devices. */
2396 if (!test_bit(__IGB_DOWN, &adapter->state)) {
2397 if (mac->type == e1000_i350 && hw->bus.func == 0) {
2398 /* If present, re-initialize the external thermal sensor
2402 mac->ops.init_thermal_sensor_thresh(hw);
2406 /* Re-establish EEE setting */
2407 if (hw->phy.media_type == e1000_media_type_copper) {
2408 switch (mac->type) {
2412 igb_set_eee_i350(hw, true, true);
2415 igb_set_eee_i354(hw, true, true);
2421 if (!netif_running(adapter->netdev))
2422 igb_power_down_link(adapter);
2424 igb_update_mng_vlan(adapter);
2426 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2427 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2429 /* Re-enable PTP, where applicable. */
2430 if (adapter->ptp_flags & IGB_PTP_ENABLED)
2431 igb_ptp_reset(adapter);
2433 igb_get_phy_info(hw);
2436 static netdev_features_t igb_fix_features(struct net_device *netdev,
2437 netdev_features_t features)
2439 /* Since there is no support for separate Rx/Tx vlan accel
2440 * enable/disable make sure Tx flag is always in same state as Rx.
2442 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2443 features |= NETIF_F_HW_VLAN_CTAG_TX;
2445 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2450 static int igb_set_features(struct net_device *netdev,
2451 netdev_features_t features)
2453 netdev_features_t changed = netdev->features ^ features;
2454 struct igb_adapter *adapter = netdev_priv(netdev);
2456 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2457 igb_vlan_mode(netdev, features);
2459 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
2462 if (!(features & NETIF_F_NTUPLE)) {
2463 struct hlist_node *node2;
2464 struct igb_nfc_filter *rule;
2466 spin_lock(&adapter->nfc_lock);
2467 hlist_for_each_entry_safe(rule, node2,
2468 &adapter->nfc_filter_list, nfc_node) {
2469 igb_erase_filter(adapter, rule);
2470 hlist_del(&rule->nfc_node);
2473 spin_unlock(&adapter->nfc_lock);
2474 adapter->nfc_filter_count = 0;
2477 netdev->features = features;
2479 if (netif_running(netdev))
2480 igb_reinit_locked(adapter);
2487 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2488 struct net_device *dev,
2489 const unsigned char *addr, u16 vid,
2491 struct netlink_ext_ack *extack)
2493 /* guarantee we can provide a unique filter for the unicast address */
2494 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2495 struct igb_adapter *adapter = netdev_priv(dev);
2496 int vfn = adapter->vfs_allocated_count;
2498 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn))
2502 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2505 #define IGB_MAX_MAC_HDR_LEN 127
2506 #define IGB_MAX_NETWORK_HDR_LEN 511
2508 static netdev_features_t
2509 igb_features_check(struct sk_buff *skb, struct net_device *dev,
2510 netdev_features_t features)
2512 unsigned int network_hdr_len, mac_hdr_len;
2514 /* Make certain the headers can be described by a context descriptor */
2515 mac_hdr_len = skb_network_header(skb) - skb->data;
2516 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN))
2517 return features & ~(NETIF_F_HW_CSUM |
2519 NETIF_F_GSO_UDP_L4 |
2520 NETIF_F_HW_VLAN_CTAG_TX |
2524 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
2525 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN))
2526 return features & ~(NETIF_F_HW_CSUM |
2528 NETIF_F_GSO_UDP_L4 |
2532 /* We can only support IPV4 TSO in tunnels if we can mangle the
2533 * inner IP ID field, so strip TSO if MANGLEID is not supported.
2535 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
2536 features &= ~NETIF_F_TSO;
2541 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue)
2543 if (!is_fqtss_enabled(adapter)) {
2544 enable_fqtss(adapter, true);
2548 igb_config_tx_modes(adapter, queue);
2550 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter))
2551 enable_fqtss(adapter, false);
2554 static int igb_offload_cbs(struct igb_adapter *adapter,
2555 struct tc_cbs_qopt_offload *qopt)
2557 struct e1000_hw *hw = &adapter->hw;
2560 /* CBS offloading is only supported by i210 controller. */
2561 if (hw->mac.type != e1000_i210)
2564 /* CBS offloading is only supported by queue 0 and queue 1. */
2565 if (qopt->queue < 0 || qopt->queue > 1)
2568 err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable,
2569 qopt->idleslope, qopt->sendslope,
2570 qopt->hicredit, qopt->locredit);
2574 igb_offload_apply(adapter, qopt->queue);
2579 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0)
2580 #define VLAN_PRIO_FULL_MASK (0x07)
2582 static int igb_parse_cls_flower(struct igb_adapter *adapter,
2583 struct flow_cls_offload *f,
2585 struct igb_nfc_filter *input)
2587 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2588 struct flow_dissector *dissector = rule->match.dissector;
2589 struct netlink_ext_ack *extack = f->common.extack;
2591 if (dissector->used_keys &
2592 ~(BIT(FLOW_DISSECTOR_KEY_BASIC) |
2593 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
2594 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
2595 BIT(FLOW_DISSECTOR_KEY_VLAN))) {
2596 NL_SET_ERR_MSG_MOD(extack,
2597 "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported");
2601 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2602 struct flow_match_eth_addrs match;
2604 flow_rule_match_eth_addrs(rule, &match);
2605 if (!is_zero_ether_addr(match.mask->dst)) {
2606 if (!is_broadcast_ether_addr(match.mask->dst)) {
2607 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address");
2611 input->filter.match_flags |=
2612 IGB_FILTER_FLAG_DST_MAC_ADDR;
2613 ether_addr_copy(input->filter.dst_addr, match.key->dst);
2616 if (!is_zero_ether_addr(match.mask->src)) {
2617 if (!is_broadcast_ether_addr(match.mask->src)) {
2618 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address");
2622 input->filter.match_flags |=
2623 IGB_FILTER_FLAG_SRC_MAC_ADDR;
2624 ether_addr_copy(input->filter.src_addr, match.key->src);
2628 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2629 struct flow_match_basic match;
2631 flow_rule_match_basic(rule, &match);
2632 if (match.mask->n_proto) {
2633 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) {
2634 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter");
2638 input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE;
2639 input->filter.etype = match.key->n_proto;
2643 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
2644 struct flow_match_vlan match;
2646 flow_rule_match_vlan(rule, &match);
2647 if (match.mask->vlan_priority) {
2648 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) {
2649 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority");
2653 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI;
2654 input->filter.vlan_tci =
2655 (__force __be16)match.key->vlan_priority;
2659 input->action = traffic_class;
2660 input->cookie = f->cookie;
2665 static int igb_configure_clsflower(struct igb_adapter *adapter,
2666 struct flow_cls_offload *cls_flower)
2668 struct netlink_ext_ack *extack = cls_flower->common.extack;
2669 struct igb_nfc_filter *filter, *f;
2672 tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid);
2674 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class");
2678 filter = kzalloc(sizeof(*filter), GFP_KERNEL);
2682 err = igb_parse_cls_flower(adapter, cls_flower, tc, filter);
2686 spin_lock(&adapter->nfc_lock);
2688 hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) {
2689 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2691 NL_SET_ERR_MSG_MOD(extack,
2692 "This filter is already set in ethtool");
2697 hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) {
2698 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2700 NL_SET_ERR_MSG_MOD(extack,
2701 "This filter is already set in cls_flower");
2706 err = igb_add_filter(adapter, filter);
2708 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter");
2712 hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list);
2714 spin_unlock(&adapter->nfc_lock);
2719 spin_unlock(&adapter->nfc_lock);
2727 static int igb_delete_clsflower(struct igb_adapter *adapter,
2728 struct flow_cls_offload *cls_flower)
2730 struct igb_nfc_filter *filter;
2733 spin_lock(&adapter->nfc_lock);
2735 hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node)
2736 if (filter->cookie == cls_flower->cookie)
2744 err = igb_erase_filter(adapter, filter);
2748 hlist_del(&filter->nfc_node);
2752 spin_unlock(&adapter->nfc_lock);
2757 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter,
2758 struct flow_cls_offload *cls_flower)
2760 switch (cls_flower->command) {
2761 case FLOW_CLS_REPLACE:
2762 return igb_configure_clsflower(adapter, cls_flower);
2763 case FLOW_CLS_DESTROY:
2764 return igb_delete_clsflower(adapter, cls_flower);
2765 case FLOW_CLS_STATS:
2772 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2775 struct igb_adapter *adapter = cb_priv;
2777 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data))
2781 case TC_SETUP_CLSFLOWER:
2782 return igb_setup_tc_cls_flower(adapter, type_data);
2789 static int igb_offload_txtime(struct igb_adapter *adapter,
2790 struct tc_etf_qopt_offload *qopt)
2792 struct e1000_hw *hw = &adapter->hw;
2795 /* Launchtime offloading is only supported by i210 controller. */
2796 if (hw->mac.type != e1000_i210)
2799 /* Launchtime offloading is only supported by queues 0 and 1. */
2800 if (qopt->queue < 0 || qopt->queue > 1)
2803 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable);
2807 igb_offload_apply(adapter, qopt->queue);
2812 static LIST_HEAD(igb_block_cb_list);
2814 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type,
2817 struct igb_adapter *adapter = netdev_priv(dev);
2820 case TC_SETUP_QDISC_CBS:
2821 return igb_offload_cbs(adapter, type_data);
2822 case TC_SETUP_BLOCK:
2823 return flow_block_cb_setup_simple(type_data,
2825 igb_setup_tc_block_cb,
2826 adapter, adapter, true);
2828 case TC_SETUP_QDISC_ETF:
2829 return igb_offload_txtime(adapter, type_data);
2836 static int igb_xdp_setup(struct net_device *dev, struct netdev_bpf *bpf)
2838 int i, frame_size = dev->mtu + IGB_ETH_PKT_HDR_PAD;
2839 struct igb_adapter *adapter = netdev_priv(dev);
2840 struct bpf_prog *prog = bpf->prog, *old_prog;
2841 bool running = netif_running(dev);
2844 /* verify igb ring attributes are sufficient for XDP */
2845 for (i = 0; i < adapter->num_rx_queues; i++) {
2846 struct igb_ring *ring = adapter->rx_ring[i];
2848 if (frame_size > igb_rx_bufsz(ring)) {
2849 NL_SET_ERR_MSG_MOD(bpf->extack,
2850 "The RX buffer size is too small for the frame size");
2851 netdev_warn(dev, "XDP RX buffer size %d is too small for the frame size %d\n",
2852 igb_rx_bufsz(ring), frame_size);
2857 old_prog = xchg(&adapter->xdp_prog, prog);
2858 need_reset = (!!prog != !!old_prog);
2860 /* device is up and bpf is added/removed, must setup the RX queues */
2861 if (need_reset && running) {
2864 for (i = 0; i < adapter->num_rx_queues; i++)
2865 (void)xchg(&adapter->rx_ring[i]->xdp_prog,
2870 bpf_prog_put(old_prog);
2872 /* bpf is just replaced, RXQ and MTU are already setup */
2882 static int igb_xdp(struct net_device *dev, struct netdev_bpf *xdp)
2884 switch (xdp->command) {
2885 case XDP_SETUP_PROG:
2886 return igb_xdp_setup(dev, xdp);
2892 static void igb_xdp_ring_update_tail(struct igb_ring *ring)
2894 /* Force memory writes to complete before letting h/w know there
2895 * are new descriptors to fetch.
2898 writel(ring->next_to_use, ring->tail);
2901 static struct igb_ring *igb_xdp_tx_queue_mapping(struct igb_adapter *adapter)
2903 unsigned int r_idx = smp_processor_id();
2905 if (r_idx >= adapter->num_tx_queues)
2906 r_idx = r_idx % adapter->num_tx_queues;
2908 return adapter->tx_ring[r_idx];
2911 static int igb_xdp_xmit_back(struct igb_adapter *adapter, struct xdp_buff *xdp)
2913 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
2914 int cpu = smp_processor_id();
2915 struct igb_ring *tx_ring;
2916 struct netdev_queue *nq;
2919 if (unlikely(!xdpf))
2920 return IGB_XDP_CONSUMED;
2922 /* During program transitions its possible adapter->xdp_prog is assigned
2923 * but ring has not been configured yet. In this case simply abort xmit.
2925 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL;
2926 if (unlikely(!tx_ring))
2927 return IGB_XDP_CONSUMED;
2929 nq = txring_txq(tx_ring);
2930 __netif_tx_lock(nq, cpu);
2931 /* Avoid transmit queue timeout since we share it with the slow path */
2932 nq->trans_start = jiffies;
2933 ret = igb_xmit_xdp_ring(adapter, tx_ring, xdpf);
2934 __netif_tx_unlock(nq);
2939 static int igb_xdp_xmit(struct net_device *dev, int n,
2940 struct xdp_frame **frames, u32 flags)
2942 struct igb_adapter *adapter = netdev_priv(dev);
2943 int cpu = smp_processor_id();
2944 struct igb_ring *tx_ring;
2945 struct netdev_queue *nq;
2949 if (unlikely(test_bit(__IGB_DOWN, &adapter->state)))
2952 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
2955 /* During program transitions its possible adapter->xdp_prog is assigned
2956 * but ring has not been configured yet. In this case simply abort xmit.
2958 tx_ring = adapter->xdp_prog ? igb_xdp_tx_queue_mapping(adapter) : NULL;
2959 if (unlikely(!tx_ring))
2962 nq = txring_txq(tx_ring);
2963 __netif_tx_lock(nq, cpu);
2965 /* Avoid transmit queue timeout since we share it with the slow path */
2966 nq->trans_start = jiffies;
2968 for (i = 0; i < n; i++) {
2969 struct xdp_frame *xdpf = frames[i];
2972 err = igb_xmit_xdp_ring(adapter, tx_ring, xdpf);
2973 if (err != IGB_XDP_TX)
2978 __netif_tx_unlock(nq);
2980 if (unlikely(flags & XDP_XMIT_FLUSH))
2981 igb_xdp_ring_update_tail(tx_ring);
2986 static const struct net_device_ops igb_netdev_ops = {
2987 .ndo_open = igb_open,
2988 .ndo_stop = igb_close,
2989 .ndo_start_xmit = igb_xmit_frame,
2990 .ndo_get_stats64 = igb_get_stats64,
2991 .ndo_set_rx_mode = igb_set_rx_mode,
2992 .ndo_set_mac_address = igb_set_mac,
2993 .ndo_change_mtu = igb_change_mtu,
2994 .ndo_eth_ioctl = igb_ioctl,
2995 .ndo_tx_timeout = igb_tx_timeout,
2996 .ndo_validate_addr = eth_validate_addr,
2997 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2998 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
2999 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
3000 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
3001 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
3002 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
3003 .ndo_set_vf_trust = igb_ndo_set_vf_trust,
3004 .ndo_get_vf_config = igb_ndo_get_vf_config,
3005 .ndo_fix_features = igb_fix_features,
3006 .ndo_set_features = igb_set_features,
3007 .ndo_fdb_add = igb_ndo_fdb_add,
3008 .ndo_features_check = igb_features_check,
3009 .ndo_setup_tc = igb_setup_tc,
3011 .ndo_xdp_xmit = igb_xdp_xmit,
3015 * igb_set_fw_version - Configure version string for ethtool
3016 * @adapter: adapter struct
3018 void igb_set_fw_version(struct igb_adapter *adapter)
3020 struct e1000_hw *hw = &adapter->hw;
3021 struct e1000_fw_version fw;
3023 igb_get_fw_version(hw, &fw);
3025 switch (hw->mac.type) {
3028 if (!(igb_get_flash_presence_i210(hw))) {
3029 snprintf(adapter->fw_version,
3030 sizeof(adapter->fw_version),
3032 fw.invm_major, fw.invm_minor,
3038 /* if option is rom valid, display its version too */
3040 snprintf(adapter->fw_version,
3041 sizeof(adapter->fw_version),
3042 "%d.%d, 0x%08x, %d.%d.%d",
3043 fw.eep_major, fw.eep_minor, fw.etrack_id,
3044 fw.or_major, fw.or_build, fw.or_patch);
3046 } else if (fw.etrack_id != 0X0000) {
3047 snprintf(adapter->fw_version,
3048 sizeof(adapter->fw_version),
3050 fw.eep_major, fw.eep_minor, fw.etrack_id);
3052 snprintf(adapter->fw_version,
3053 sizeof(adapter->fw_version),
3055 fw.eep_major, fw.eep_minor, fw.eep_build);
3062 * igb_init_mas - init Media Autosense feature if enabled in the NVM
3064 * @adapter: adapter struct
3066 static void igb_init_mas(struct igb_adapter *adapter)
3068 struct e1000_hw *hw = &adapter->hw;
3071 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
3072 switch (hw->bus.func) {
3074 if (eeprom_data & IGB_MAS_ENABLE_0) {
3075 adapter->flags |= IGB_FLAG_MAS_ENABLE;
3076 netdev_info(adapter->netdev,
3077 "MAS: Enabling Media Autosense for port %d\n",
3082 if (eeprom_data & IGB_MAS_ENABLE_1) {
3083 adapter->flags |= IGB_FLAG_MAS_ENABLE;
3084 netdev_info(adapter->netdev,
3085 "MAS: Enabling Media Autosense for port %d\n",
3090 if (eeprom_data & IGB_MAS_ENABLE_2) {
3091 adapter->flags |= IGB_FLAG_MAS_ENABLE;
3092 netdev_info(adapter->netdev,
3093 "MAS: Enabling Media Autosense for port %d\n",
3098 if (eeprom_data & IGB_MAS_ENABLE_3) {
3099 adapter->flags |= IGB_FLAG_MAS_ENABLE;
3100 netdev_info(adapter->netdev,
3101 "MAS: Enabling Media Autosense for port %d\n",
3106 /* Shouldn't get here */
3107 netdev_err(adapter->netdev,
3108 "MAS: Invalid port configuration, returning\n");
3114 * igb_init_i2c - Init I2C interface
3115 * @adapter: pointer to adapter structure
3117 static s32 igb_init_i2c(struct igb_adapter *adapter)
3121 /* I2C interface supported on i350 devices */
3122 if (adapter->hw.mac.type != e1000_i350)
3125 /* Initialize the i2c bus which is controlled by the registers.
3126 * This bus will use the i2c_algo_bit structure that implements
3127 * the protocol through toggling of the 4 bits in the register.
3129 adapter->i2c_adap.owner = THIS_MODULE;
3130 adapter->i2c_algo = igb_i2c_algo;
3131 adapter->i2c_algo.data = adapter;
3132 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
3133 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
3134 strlcpy(adapter->i2c_adap.name, "igb BB",
3135 sizeof(adapter->i2c_adap.name));
3136 status = i2c_bit_add_bus(&adapter->i2c_adap);
3141 * igb_probe - Device Initialization Routine
3142 * @pdev: PCI device information struct
3143 * @ent: entry in igb_pci_tbl
3145 * Returns 0 on success, negative on failure
3147 * igb_probe initializes an adapter identified by a pci_dev structure.
3148 * The OS initialization, configuring of the adapter private structure,
3149 * and a hardware reset occur.
3151 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3153 struct net_device *netdev;
3154 struct igb_adapter *adapter;
3155 struct e1000_hw *hw;
3156 u16 eeprom_data = 0;
3158 static int global_quad_port_a; /* global quad port a indication */
3159 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
3160 int err, pci_using_dac;
3161 u8 part_str[E1000_PBANUM_LENGTH];
3163 /* Catch broken hardware that put the wrong VF device ID in
3164 * the PCIe SR-IOV capability.
3166 if (pdev->is_virtfn) {
3167 WARN(1, KERN_ERR "%s (%x:%x) should not be a VF!\n",
3168 pci_name(pdev), pdev->vendor, pdev->device);
3172 err = pci_enable_device_mem(pdev);
3177 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3181 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3184 "No usable DMA configuration, aborting\n");
3189 err = pci_request_mem_regions(pdev, igb_driver_name);
3193 pci_enable_pcie_error_reporting(pdev);
3195 pci_set_master(pdev);
3196 pci_save_state(pdev);
3199 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
3202 goto err_alloc_etherdev;
3204 SET_NETDEV_DEV(netdev, &pdev->dev);
3206 pci_set_drvdata(pdev, netdev);
3207 adapter = netdev_priv(netdev);
3208 adapter->netdev = netdev;
3209 adapter->pdev = pdev;
3212 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3215 adapter->io_addr = pci_iomap(pdev, 0, 0);
3216 if (!adapter->io_addr)
3218 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
3219 hw->hw_addr = adapter->io_addr;
3221 netdev->netdev_ops = &igb_netdev_ops;
3222 igb_set_ethtool_ops(netdev);
3223 netdev->watchdog_timeo = 5 * HZ;
3225 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
3227 netdev->mem_start = pci_resource_start(pdev, 0);
3228 netdev->mem_end = pci_resource_end(pdev, 0);
3230 /* PCI config space info */
3231 hw->vendor_id = pdev->vendor;
3232 hw->device_id = pdev->device;
3233 hw->revision_id = pdev->revision;
3234 hw->subsystem_vendor_id = pdev->subsystem_vendor;
3235 hw->subsystem_device_id = pdev->subsystem_device;
3237 /* Copy the default MAC, PHY and NVM function pointers */
3238 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
3239 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
3240 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
3241 /* Initialize skew-specific constants */
3242 err = ei->get_invariants(hw);
3246 /* setup the private structure */
3247 err = igb_sw_init(adapter);
3251 igb_get_bus_info_pcie(hw);
3253 hw->phy.autoneg_wait_to_complete = false;
3255 /* Copper options */
3256 if (hw->phy.media_type == e1000_media_type_copper) {
3257 hw->phy.mdix = AUTO_ALL_MODES;
3258 hw->phy.disable_polarity_correction = false;
3259 hw->phy.ms_type = e1000_ms_hw_default;
3262 if (igb_check_reset_block(hw))
3263 dev_info(&pdev->dev,
3264 "PHY reset is blocked due to SOL/IDER session.\n");
3266 /* features is initialized to 0 in allocation, it might have bits
3267 * set by igb_sw_init so we should use an or instead of an
3270 netdev->features |= NETIF_F_SG |
3277 if (hw->mac.type >= e1000_82576)
3278 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4;
3280 if (hw->mac.type >= e1000_i350)
3281 netdev->features |= NETIF_F_HW_TC;
3283 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
3284 NETIF_F_GSO_GRE_CSUM | \
3285 NETIF_F_GSO_IPXIP4 | \
3286 NETIF_F_GSO_IPXIP6 | \
3287 NETIF_F_GSO_UDP_TUNNEL | \
3288 NETIF_F_GSO_UDP_TUNNEL_CSUM)
3290 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES;
3291 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES;
3293 /* copy netdev features into list of user selectable features */
3294 netdev->hw_features |= netdev->features |
3295 NETIF_F_HW_VLAN_CTAG_RX |
3296 NETIF_F_HW_VLAN_CTAG_TX |
3299 if (hw->mac.type >= e1000_i350)
3300 netdev->hw_features |= NETIF_F_NTUPLE;
3303 netdev->features |= NETIF_F_HIGHDMA;
3305 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
3306 netdev->mpls_features |= NETIF_F_HW_CSUM;
3307 netdev->hw_enc_features |= netdev->vlan_features;
3309 /* set this bit last since it cannot be part of vlan_features */
3310 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3311 NETIF_F_HW_VLAN_CTAG_RX |
3312 NETIF_F_HW_VLAN_CTAG_TX;
3314 netdev->priv_flags |= IFF_SUPP_NOFCS;
3316 netdev->priv_flags |= IFF_UNICAST_FLT;
3318 /* MTU range: 68 - 9216 */
3319 netdev->min_mtu = ETH_MIN_MTU;
3320 netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE;
3322 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
3324 /* before reading the NVM, reset the controller to put the device in a
3325 * known good starting state
3327 hw->mac.ops.reset_hw(hw);
3329 /* make sure the NVM is good , i211/i210 parts can have special NVM
3330 * that doesn't contain a checksum
3332 switch (hw->mac.type) {
3335 if (igb_get_flash_presence_i210(hw)) {
3336 if (hw->nvm.ops.validate(hw) < 0) {
3338 "The NVM Checksum Is Not Valid\n");
3345 if (hw->nvm.ops.validate(hw) < 0) {
3346 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
3353 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {
3354 /* copy the MAC address out of the NVM */
3355 if (hw->mac.ops.read_mac_addr(hw))
3356 dev_err(&pdev->dev, "NVM Read Error\n");
3359 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
3361 if (!is_valid_ether_addr(netdev->dev_addr)) {
3362 dev_err(&pdev->dev, "Invalid MAC Address\n");
3367 igb_set_default_mac_filter(adapter);
3369 /* get firmware version for ethtool -i */
3370 igb_set_fw_version(adapter);
3372 /* configure RXPBSIZE and TXPBSIZE */
3373 if (hw->mac.type == e1000_i210) {
3374 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
3375 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
3378 timer_setup(&adapter->watchdog_timer, igb_watchdog, 0);
3379 timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0);
3381 INIT_WORK(&adapter->reset_task, igb_reset_task);
3382 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
3384 /* Initialize link properties that are user-changeable */
3385 adapter->fc_autoneg = true;
3386 hw->mac.autoneg = true;
3387 hw->phy.autoneg_advertised = 0x2f;
3389 hw->fc.requested_mode = e1000_fc_default;
3390 hw->fc.current_mode = e1000_fc_default;
3392 igb_validate_mdi_setting(hw);
3394 /* By default, support wake on port A */
3395 if (hw->bus.func == 0)
3396 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3398 /* Check the NVM for wake support on non-port A ports */
3399 if (hw->mac.type >= e1000_82580)
3400 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
3401 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
3403 else if (hw->bus.func == 1)
3404 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3406 if (eeprom_data & IGB_EEPROM_APME)
3407 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3409 /* now that we have the eeprom settings, apply the special cases where
3410 * the eeprom may be wrong or the board simply won't support wake on
3411 * lan on a particular port
3413 switch (pdev->device) {
3414 case E1000_DEV_ID_82575GB_QUAD_COPPER:
3415 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3417 case E1000_DEV_ID_82575EB_FIBER_SERDES:
3418 case E1000_DEV_ID_82576_FIBER:
3419 case E1000_DEV_ID_82576_SERDES:
3420 /* Wake events only supported on port A for dual fiber
3421 * regardless of eeprom setting
3423 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
3424 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3426 case E1000_DEV_ID_82576_QUAD_COPPER:
3427 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
3428 /* if quad port adapter, disable WoL on all but port A */
3429 if (global_quad_port_a != 0)
3430 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3432 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
3433 /* Reset for multiple quad port adapters */
3434 if (++global_quad_port_a == 4)
3435 global_quad_port_a = 0;
3438 /* If the device can't wake, don't set software support */
3439 if (!device_can_wakeup(&adapter->pdev->dev))
3440 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3443 /* initialize the wol settings based on the eeprom settings */
3444 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
3445 adapter->wol |= E1000_WUFC_MAG;
3447 /* Some vendors want WoL disabled by default, but still supported */
3448 if ((hw->mac.type == e1000_i350) &&
3449 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
3450 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3454 /* Some vendors want the ability to Use the EEPROM setting as
3455 * enable/disable only, and not for capability
3457 if (((hw->mac.type == e1000_i350) ||
3458 (hw->mac.type == e1000_i354)) &&
3459 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) {
3460 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3463 if (hw->mac.type == e1000_i350) {
3464 if (((pdev->subsystem_device == 0x5001) ||
3465 (pdev->subsystem_device == 0x5002)) &&
3466 (hw->bus.func == 0)) {
3467 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3470 if (pdev->subsystem_device == 0x1F52)
3471 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3474 device_set_wakeup_enable(&adapter->pdev->dev,
3475 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
3477 /* reset the hardware with the new settings */
3480 /* Init the I2C interface */
3481 err = igb_init_i2c(adapter);
3483 dev_err(&pdev->dev, "failed to init i2c interface\n");
3487 /* let the f/w know that the h/w is now under the control of the
3490 igb_get_hw_control(adapter);
3492 strcpy(netdev->name, "eth%d");
3493 err = register_netdev(netdev);
3497 /* carrier off reporting is important to ethtool even BEFORE open */
3498 netif_carrier_off(netdev);
3500 #ifdef CONFIG_IGB_DCA
3501 if (dca_add_requester(&pdev->dev) == 0) {
3502 adapter->flags |= IGB_FLAG_DCA_ENABLED;
3503 dev_info(&pdev->dev, "DCA enabled\n");
3504 igb_setup_dca(adapter);
3508 #ifdef CONFIG_IGB_HWMON
3509 /* Initialize the thermal sensor on i350 devices. */
3510 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
3513 /* Read the NVM to determine if this i350 device supports an
3514 * external thermal sensor.
3516 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
3517 if (ets_word != 0x0000 && ets_word != 0xFFFF)
3518 adapter->ets = true;
3520 adapter->ets = false;
3521 if (igb_sysfs_init(adapter))
3523 "failed to allocate sysfs resources\n");
3525 adapter->ets = false;
3528 /* Check if Media Autosense is enabled */
3530 if (hw->dev_spec._82575.mas_capable)
3531 igb_init_mas(adapter);
3533 /* do hw tstamp init after resetting */
3534 igb_ptp_init(adapter);
3536 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
3537 /* print bus type/speed/width info, not applicable to i354 */
3538 if (hw->mac.type != e1000_i354) {
3539 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
3541 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
3542 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
3544 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
3546 (hw->bus.width == e1000_bus_width_pcie_x2) ?
3548 (hw->bus.width == e1000_bus_width_pcie_x1) ?
3549 "Width x1" : "unknown"), netdev->dev_addr);
3552 if ((hw->mac.type == e1000_82576 &&
3553 rd32(E1000_EECD) & E1000_EECD_PRES) ||
3554 (hw->mac.type >= e1000_i210 ||
3555 igb_get_flash_presence_i210(hw))) {
3556 ret_val = igb_read_part_string(hw, part_str,
3557 E1000_PBANUM_LENGTH);
3559 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
3563 strcpy(part_str, "Unknown");
3564 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
3565 dev_info(&pdev->dev,
3566 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
3567 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
3568 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
3569 adapter->num_rx_queues, adapter->num_tx_queues);
3570 if (hw->phy.media_type == e1000_media_type_copper) {
3571 switch (hw->mac.type) {
3575 /* Enable EEE for internal copper PHY devices */
3576 err = igb_set_eee_i350(hw, true, true);
3578 (!hw->dev_spec._82575.eee_disable)) {
3579 adapter->eee_advert =
3580 MDIO_EEE_100TX | MDIO_EEE_1000T;
3581 adapter->flags |= IGB_FLAG_EEE;
3585 if ((rd32(E1000_CTRL_EXT) &
3586 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3587 err = igb_set_eee_i354(hw, true, true);
3589 (!hw->dev_spec._82575.eee_disable)) {
3590 adapter->eee_advert =
3591 MDIO_EEE_100TX | MDIO_EEE_1000T;
3592 adapter->flags |= IGB_FLAG_EEE;
3601 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
3603 pm_runtime_put_noidle(&pdev->dev);
3607 igb_release_hw_control(adapter);
3608 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
3610 if (!igb_check_reset_block(hw))
3613 if (hw->flash_address)
3614 iounmap(hw->flash_address);
3616 kfree(adapter->mac_table);
3617 kfree(adapter->shadow_vfta);
3618 igb_clear_interrupt_scheme(adapter);
3619 #ifdef CONFIG_PCI_IOV
3620 igb_disable_sriov(pdev);
3622 pci_iounmap(pdev, adapter->io_addr);
3624 free_netdev(netdev);
3626 pci_disable_pcie_error_reporting(pdev);
3627 pci_release_mem_regions(pdev);
3630 pci_disable_device(pdev);
3634 #ifdef CONFIG_PCI_IOV
3635 static int igb_disable_sriov(struct pci_dev *pdev)
3637 struct net_device *netdev = pci_get_drvdata(pdev);
3638 struct igb_adapter *adapter = netdev_priv(netdev);
3639 struct e1000_hw *hw = &adapter->hw;
3641 /* reclaim resources allocated to VFs */
3642 if (adapter->vf_data) {
3643 /* disable iov and allow time for transactions to clear */
3644 if (pci_vfs_assigned(pdev)) {
3645 dev_warn(&pdev->dev,
3646 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
3649 pci_disable_sriov(pdev);
3653 kfree(adapter->vf_mac_list);
3654 adapter->vf_mac_list = NULL;
3655 kfree(adapter->vf_data);
3656 adapter->vf_data = NULL;
3657 adapter->vfs_allocated_count = 0;
3658 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
3661 dev_info(&pdev->dev, "IOV Disabled\n");
3663 /* Re-enable DMA Coalescing flag since IOV is turned off */
3664 adapter->flags |= IGB_FLAG_DMAC;
3670 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
3672 struct net_device *netdev = pci_get_drvdata(pdev);
3673 struct igb_adapter *adapter = netdev_priv(netdev);
3674 int old_vfs = pci_num_vf(pdev);
3675 struct vf_mac_filter *mac_list;
3677 int num_vf_mac_filters, i;
3679 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
3687 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
3689 adapter->vfs_allocated_count = old_vfs;
3691 adapter->vfs_allocated_count = num_vfs;
3693 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
3694 sizeof(struct vf_data_storage), GFP_KERNEL);
3696 /* if allocation failed then we do not support SR-IOV */
3697 if (!adapter->vf_data) {
3698 adapter->vfs_allocated_count = 0;
3703 /* Due to the limited number of RAR entries calculate potential
3704 * number of MAC filters available for the VFs. Reserve entries
3705 * for PF default MAC, PF MAC filters and at least one RAR entry
3706 * for each VF for VF MAC.
3708 num_vf_mac_filters = adapter->hw.mac.rar_entry_count -
3709 (1 + IGB_PF_MAC_FILTERS_RESERVED +
3710 adapter->vfs_allocated_count);
3712 adapter->vf_mac_list = kcalloc(num_vf_mac_filters,
3713 sizeof(struct vf_mac_filter),
3716 mac_list = adapter->vf_mac_list;
3717 INIT_LIST_HEAD(&adapter->vf_macs.l);
3719 if (adapter->vf_mac_list) {
3720 /* Initialize list of VF MAC filters */
3721 for (i = 0; i < num_vf_mac_filters; i++) {
3723 mac_list->free = true;
3724 list_add(&mac_list->l, &adapter->vf_macs.l);
3728 /* If we could not allocate memory for the VF MAC filters
3729 * we can continue without this feature but warn user.
3732 "Unable to allocate memory for VF MAC filter list\n");
3735 /* only call pci_enable_sriov() if no VFs are allocated already */
3737 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
3741 dev_info(&pdev->dev, "%d VFs allocated\n",
3742 adapter->vfs_allocated_count);
3743 for (i = 0; i < adapter->vfs_allocated_count; i++)
3744 igb_vf_configure(adapter, i);
3746 /* DMA Coalescing is not supported in IOV mode. */
3747 adapter->flags &= ~IGB_FLAG_DMAC;
3751 kfree(adapter->vf_mac_list);
3752 adapter->vf_mac_list = NULL;
3753 kfree(adapter->vf_data);
3754 adapter->vf_data = NULL;
3755 adapter->vfs_allocated_count = 0;
3762 * igb_remove_i2c - Cleanup I2C interface
3763 * @adapter: pointer to adapter structure
3765 static void igb_remove_i2c(struct igb_adapter *adapter)
3767 /* free the adapter bus structure */
3768 i2c_del_adapter(&adapter->i2c_adap);
3772 * igb_remove - Device Removal Routine
3773 * @pdev: PCI device information struct
3775 * igb_remove is called by the PCI subsystem to alert the driver
3776 * that it should release a PCI device. The could be caused by a
3777 * Hot-Plug event, or because the driver is going to be removed from
3780 static void igb_remove(struct pci_dev *pdev)
3782 struct net_device *netdev = pci_get_drvdata(pdev);
3783 struct igb_adapter *adapter = netdev_priv(netdev);
3784 struct e1000_hw *hw = &adapter->hw;
3786 pm_runtime_get_noresume(&pdev->dev);
3787 #ifdef CONFIG_IGB_HWMON
3788 igb_sysfs_exit(adapter);
3790 igb_remove_i2c(adapter);
3791 igb_ptp_stop(adapter);
3792 /* The watchdog timer may be rescheduled, so explicitly
3793 * disable watchdog from being rescheduled.
3795 set_bit(__IGB_DOWN, &adapter->state);
3796 del_timer_sync(&adapter->watchdog_timer);
3797 del_timer_sync(&adapter->phy_info_timer);
3799 cancel_work_sync(&adapter->reset_task);
3800 cancel_work_sync(&adapter->watchdog_task);
3802 #ifdef CONFIG_IGB_DCA
3803 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3804 dev_info(&pdev->dev, "DCA disabled\n");
3805 dca_remove_requester(&pdev->dev);
3806 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3807 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3811 /* Release control of h/w to f/w. If f/w is AMT enabled, this
3812 * would have already happened in close and is redundant.
3814 igb_release_hw_control(adapter);
3816 #ifdef CONFIG_PCI_IOV
3817 igb_disable_sriov(pdev);
3820 unregister_netdev(netdev);
3822 igb_clear_interrupt_scheme(adapter);
3824 pci_iounmap(pdev, adapter->io_addr);
3825 if (hw->flash_address)
3826 iounmap(hw->flash_address);
3827 pci_release_mem_regions(pdev);
3829 kfree(adapter->mac_table);
3830 kfree(adapter->shadow_vfta);
3831 free_netdev(netdev);
3833 pci_disable_pcie_error_reporting(pdev);
3835 pci_disable_device(pdev);
3839 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
3840 * @adapter: board private structure to initialize
3842 * This function initializes the vf specific data storage and then attempts to
3843 * allocate the VFs. The reason for ordering it this way is because it is much
3844 * mor expensive time wise to disable SR-IOV than it is to allocate and free
3845 * the memory for the VFs.
3847 static void igb_probe_vfs(struct igb_adapter *adapter)
3849 #ifdef CONFIG_PCI_IOV
3850 struct pci_dev *pdev = adapter->pdev;
3851 struct e1000_hw *hw = &adapter->hw;
3853 /* Virtualization features not supported on i210 family. */
3854 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
3857 /* Of the below we really only want the effect of getting
3858 * IGB_FLAG_HAS_MSIX set (if available), without which
3859 * igb_enable_sriov() has no effect.
3861 igb_set_interrupt_capability(adapter, true);
3862 igb_reset_interrupt_capability(adapter);
3864 pci_sriov_set_totalvfs(pdev, 7);
3865 igb_enable_sriov(pdev, max_vfs);
3867 #endif /* CONFIG_PCI_IOV */
3870 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter)
3872 struct e1000_hw *hw = &adapter->hw;
3873 unsigned int max_rss_queues;
3875 /* Determine the maximum number of RSS queues supported. */
3876 switch (hw->mac.type) {
3878 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
3882 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
3885 /* I350 cannot do RSS and SR-IOV at the same time */
3886 if (!!adapter->vfs_allocated_count) {
3892 if (!!adapter->vfs_allocated_count) {
3900 max_rss_queues = IGB_MAX_RX_QUEUES;
3904 return max_rss_queues;
3907 static void igb_init_queue_configuration(struct igb_adapter *adapter)
3911 max_rss_queues = igb_get_max_rss_queues(adapter);
3912 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
3914 igb_set_flag_queue_pairs(adapter, max_rss_queues);
3917 void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
3918 const u32 max_rss_queues)
3920 struct e1000_hw *hw = &adapter->hw;
3922 /* Determine if we need to pair queues. */
3923 switch (hw->mac.type) {
3926 /* Device supports enough interrupts without queue pairing. */
3934 /* If rss_queues > half of max_rss_queues, pair the queues in
3935 * order to conserve interrupts due to limited supply.
3937 if (adapter->rss_queues > (max_rss_queues / 2))
3938 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
3940 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
3946 * igb_sw_init - Initialize general software structures (struct igb_adapter)
3947 * @adapter: board private structure to initialize
3949 * igb_sw_init initializes the Adapter private data structure.
3950 * Fields are initialized based on PCI device information and
3951 * OS network device settings (MTU size).
3953 static int igb_sw_init(struct igb_adapter *adapter)
3955 struct e1000_hw *hw = &adapter->hw;
3956 struct net_device *netdev = adapter->netdev;
3957 struct pci_dev *pdev = adapter->pdev;
3959 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
3961 /* set default ring sizes */
3962 adapter->tx_ring_count = IGB_DEFAULT_TXD;
3963 adapter->rx_ring_count = IGB_DEFAULT_RXD;
3965 /* set default ITR values */
3966 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
3967 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
3969 /* set default work limits */
3970 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
3972 adapter->max_frame_size = netdev->mtu + IGB_ETH_PKT_HDR_PAD;
3973 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
3975 spin_lock_init(&adapter->nfc_lock);
3976 spin_lock_init(&adapter->stats64_lock);
3977 #ifdef CONFIG_PCI_IOV
3978 switch (hw->mac.type) {
3982 dev_warn(&pdev->dev,
3983 "Maximum of 7 VFs per PF, using max\n");
3984 max_vfs = adapter->vfs_allocated_count = 7;
3986 adapter->vfs_allocated_count = max_vfs;
3987 if (adapter->vfs_allocated_count)
3988 dev_warn(&pdev->dev,
3989 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
3994 #endif /* CONFIG_PCI_IOV */
3996 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
3997 adapter->flags |= IGB_FLAG_HAS_MSIX;
3999 adapter->mac_table = kcalloc(hw->mac.rar_entry_count,
4000 sizeof(struct igb_mac_addr),
4002 if (!adapter->mac_table)
4005 igb_probe_vfs(adapter);
4007 igb_init_queue_configuration(adapter);
4009 /* Setup and initialize a copy of the hw vlan table array */
4010 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
4012 if (!adapter->shadow_vfta)
4015 /* This call may decrease the number of queues */
4016 if (igb_init_interrupt_scheme(adapter, true)) {
4017 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
4021 /* Explicitly disable IRQ since the NIC can be in any state. */
4022 igb_irq_disable(adapter);
4024 if (hw->mac.type >= e1000_i350)
4025 adapter->flags &= ~IGB_FLAG_DMAC;
4027 set_bit(__IGB_DOWN, &adapter->state);
4032 * __igb_open - Called when a network interface is made active
4033 * @netdev: network interface device structure
4034 * @resuming: indicates whether we are in a resume call
4036 * Returns 0 on success, negative value on failure
4038 * The open entry point is called when a network interface is made
4039 * active by the system (IFF_UP). At this point all resources needed
4040 * for transmit and receive operations are allocated, the interrupt
4041 * handler is registered with the OS, the watchdog timer is started,
4042 * and the stack is notified that the interface is ready.
4044 static int __igb_open(struct net_device *netdev, bool resuming)
4046 struct igb_adapter *adapter = netdev_priv(netdev);
4047 struct e1000_hw *hw = &adapter->hw;
4048 struct pci_dev *pdev = adapter->pdev;
4052 /* disallow open during test */
4053 if (test_bit(__IGB_TESTING, &adapter->state)) {
4059 pm_runtime_get_sync(&pdev->dev);
4061 netif_carrier_off(netdev);
4063 /* allocate transmit descriptors */
4064 err = igb_setup_all_tx_resources(adapter);
4068 /* allocate receive descriptors */
4069 err = igb_setup_all_rx_resources(adapter);
4073 igb_power_up_link(adapter);
4075 /* before we allocate an interrupt, we must be ready to handle it.
4076 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4077 * as soon as we call pci_request_irq, so we have to setup our
4078 * clean_rx handler before we do so.
4080 igb_configure(adapter);
4082 err = igb_request_irq(adapter);
4086 /* Notify the stack of the actual queue counts. */
4087 err = netif_set_real_num_tx_queues(adapter->netdev,
4088 adapter->num_tx_queues);
4090 goto err_set_queues;
4092 err = netif_set_real_num_rx_queues(adapter->netdev,
4093 adapter->num_rx_queues);
4095 goto err_set_queues;
4097 /* From here on the code is the same as igb_up() */
4098 clear_bit(__IGB_DOWN, &adapter->state);
4100 for (i = 0; i < adapter->num_q_vectors; i++)
4101 napi_enable(&(adapter->q_vector[i]->napi));
4103 /* Clear any pending interrupts. */
4107 igb_irq_enable(adapter);
4109 /* notify VFs that reset has been completed */
4110 if (adapter->vfs_allocated_count) {
4111 u32 reg_data = rd32(E1000_CTRL_EXT);
4113 reg_data |= E1000_CTRL_EXT_PFRSTD;
4114 wr32(E1000_CTRL_EXT, reg_data);
4117 netif_tx_start_all_queues(netdev);
4120 pm_runtime_put(&pdev->dev);
4122 /* start the watchdog. */
4123 hw->mac.get_link_status = 1;
4124 schedule_work(&adapter->watchdog_task);
4129 igb_free_irq(adapter);
4131 igb_release_hw_control(adapter);
4132 igb_power_down_link(adapter);
4133 igb_free_all_rx_resources(adapter);
4135 igb_free_all_tx_resources(adapter);
4139 pm_runtime_put(&pdev->dev);
4144 int igb_open(struct net_device *netdev)
4146 return __igb_open(netdev, false);
4150 * __igb_close - Disables a network interface
4151 * @netdev: network interface device structure
4152 * @suspending: indicates we are in a suspend call
4154 * Returns 0, this is not allowed to fail
4156 * The close entry point is called when an interface is de-activated
4157 * by the OS. The hardware is still under the driver's control, but
4158 * needs to be disabled. A global MAC reset is issued to stop the
4159 * hardware, and all transmit and receive resources are freed.
4161 static int __igb_close(struct net_device *netdev, bool suspending)
4163 struct igb_adapter *adapter = netdev_priv(netdev);
4164 struct pci_dev *pdev = adapter->pdev;
4166 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
4169 pm_runtime_get_sync(&pdev->dev);
4172 igb_free_irq(adapter);
4174 igb_free_all_tx_resources(adapter);
4175 igb_free_all_rx_resources(adapter);
4178 pm_runtime_put_sync(&pdev->dev);
4182 int igb_close(struct net_device *netdev)
4184 if (netif_device_present(netdev) || netdev->dismantle)
4185 return __igb_close(netdev, false);
4190 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
4191 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4193 * Return 0 on success, negative on failure
4195 int igb_setup_tx_resources(struct igb_ring *tx_ring)
4197 struct device *dev = tx_ring->dev;
4200 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
4202 tx_ring->tx_buffer_info = vmalloc(size);
4203 if (!tx_ring->tx_buffer_info)
4206 /* round up to nearest 4K */
4207 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
4208 tx_ring->size = ALIGN(tx_ring->size, 4096);
4210 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4211 &tx_ring->dma, GFP_KERNEL);
4215 tx_ring->next_to_use = 0;
4216 tx_ring->next_to_clean = 0;
4221 vfree(tx_ring->tx_buffer_info);
4222 tx_ring->tx_buffer_info = NULL;
4223 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4228 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
4229 * (Descriptors) for all queues
4230 * @adapter: board private structure
4232 * Return 0 on success, negative on failure
4234 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
4236 struct pci_dev *pdev = adapter->pdev;
4239 for (i = 0; i < adapter->num_tx_queues; i++) {
4240 err = igb_setup_tx_resources(adapter->tx_ring[i]);
4243 "Allocation for Tx Queue %u failed\n", i);
4244 for (i--; i >= 0; i--)
4245 igb_free_tx_resources(adapter->tx_ring[i]);
4254 * igb_setup_tctl - configure the transmit control registers
4255 * @adapter: Board private structure
4257 void igb_setup_tctl(struct igb_adapter *adapter)
4259 struct e1000_hw *hw = &adapter->hw;
4262 /* disable queue 0 which is enabled by default on 82575 and 82576 */
4263 wr32(E1000_TXDCTL(0), 0);
4265 /* Program the Transmit Control Register */
4266 tctl = rd32(E1000_TCTL);
4267 tctl &= ~E1000_TCTL_CT;
4268 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
4269 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
4271 igb_config_collision_dist(hw);
4273 /* Enable transmits */
4274 tctl |= E1000_TCTL_EN;
4276 wr32(E1000_TCTL, tctl);
4280 * igb_configure_tx_ring - Configure transmit ring after Reset
4281 * @adapter: board private structure
4282 * @ring: tx ring to configure
4284 * Configure a transmit ring after a reset.
4286 void igb_configure_tx_ring(struct igb_adapter *adapter,
4287 struct igb_ring *ring)
4289 struct e1000_hw *hw = &adapter->hw;
4291 u64 tdba = ring->dma;
4292 int reg_idx = ring->reg_idx;
4294 wr32(E1000_TDLEN(reg_idx),
4295 ring->count * sizeof(union e1000_adv_tx_desc));
4296 wr32(E1000_TDBAL(reg_idx),
4297 tdba & 0x00000000ffffffffULL);
4298 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
4300 ring->tail = adapter->io_addr + E1000_TDT(reg_idx);
4301 wr32(E1000_TDH(reg_idx), 0);
4302 writel(0, ring->tail);
4304 txdctl |= IGB_TX_PTHRESH;
4305 txdctl |= IGB_TX_HTHRESH << 8;
4306 txdctl |= IGB_TX_WTHRESH << 16;
4308 /* reinitialize tx_buffer_info */
4309 memset(ring->tx_buffer_info, 0,
4310 sizeof(struct igb_tx_buffer) * ring->count);
4312 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
4313 wr32(E1000_TXDCTL(reg_idx), txdctl);
4317 * igb_configure_tx - Configure transmit Unit after Reset
4318 * @adapter: board private structure
4320 * Configure the Tx unit of the MAC after a reset.
4322 static void igb_configure_tx(struct igb_adapter *adapter)
4324 struct e1000_hw *hw = &adapter->hw;
4327 /* disable the queues */
4328 for (i = 0; i < adapter->num_tx_queues; i++)
4329 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0);
4332 usleep_range(10000, 20000);
4334 for (i = 0; i < adapter->num_tx_queues; i++)
4335 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
4339 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
4340 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
4342 * Returns 0 on success, negative on failure
4344 int igb_setup_rx_resources(struct igb_ring *rx_ring)
4346 struct igb_adapter *adapter = netdev_priv(rx_ring->netdev);
4347 struct device *dev = rx_ring->dev;
4350 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
4352 rx_ring->rx_buffer_info = vmalloc(size);
4353 if (!rx_ring->rx_buffer_info)
4356 /* Round up to nearest 4K */
4357 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
4358 rx_ring->size = ALIGN(rx_ring->size, 4096);
4360 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4361 &rx_ring->dma, GFP_KERNEL);
4365 rx_ring->next_to_alloc = 0;
4366 rx_ring->next_to_clean = 0;
4367 rx_ring->next_to_use = 0;
4369 rx_ring->xdp_prog = adapter->xdp_prog;
4371 /* XDP RX-queue info */
4372 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev,
4373 rx_ring->queue_index, 0) < 0)
4379 vfree(rx_ring->rx_buffer_info);
4380 rx_ring->rx_buffer_info = NULL;
4381 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4386 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
4387 * (Descriptors) for all queues
4388 * @adapter: board private structure
4390 * Return 0 on success, negative on failure
4392 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
4394 struct pci_dev *pdev = adapter->pdev;
4397 for (i = 0; i < adapter->num_rx_queues; i++) {
4398 err = igb_setup_rx_resources(adapter->rx_ring[i]);
4401 "Allocation for Rx Queue %u failed\n", i);
4402 for (i--; i >= 0; i--)
4403 igb_free_rx_resources(adapter->rx_ring[i]);
4412 * igb_setup_mrqc - configure the multiple receive queue control registers
4413 * @adapter: Board private structure
4415 static void igb_setup_mrqc(struct igb_adapter *adapter)
4417 struct e1000_hw *hw = &adapter->hw;
4419 u32 j, num_rx_queues;
4422 netdev_rss_key_fill(rss_key, sizeof(rss_key));
4423 for (j = 0; j < 10; j++)
4424 wr32(E1000_RSSRK(j), rss_key[j]);
4426 num_rx_queues = adapter->rss_queues;
4428 switch (hw->mac.type) {
4430 /* 82576 supports 2 RSS queues for SR-IOV */
4431 if (adapter->vfs_allocated_count)
4438 if (adapter->rss_indir_tbl_init != num_rx_queues) {
4439 for (j = 0; j < IGB_RETA_SIZE; j++)
4440 adapter->rss_indir_tbl[j] =
4441 (j * num_rx_queues) / IGB_RETA_SIZE;
4442 adapter->rss_indir_tbl_init = num_rx_queues;
4444 igb_write_rss_indir_tbl(adapter);
4446 /* Disable raw packet checksumming so that RSS hash is placed in
4447 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
4448 * offloads as they are enabled by default
4450 rxcsum = rd32(E1000_RXCSUM);
4451 rxcsum |= E1000_RXCSUM_PCSD;
4453 if (adapter->hw.mac.type >= e1000_82576)
4454 /* Enable Receive Checksum Offload for SCTP */
4455 rxcsum |= E1000_RXCSUM_CRCOFL;
4457 /* Don't need to set TUOFL or IPOFL, they default to 1 */
4458 wr32(E1000_RXCSUM, rxcsum);
4460 /* Generate RSS hash based on packet types, TCP/UDP
4461 * port numbers and/or IPv4/v6 src and dst addresses
4463 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
4464 E1000_MRQC_RSS_FIELD_IPV4_TCP |
4465 E1000_MRQC_RSS_FIELD_IPV6 |
4466 E1000_MRQC_RSS_FIELD_IPV6_TCP |
4467 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
4469 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
4470 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
4471 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
4472 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
4474 /* If VMDq is enabled then we set the appropriate mode for that, else
4475 * we default to RSS so that an RSS hash is calculated per packet even
4476 * if we are only using one queue
4478 if (adapter->vfs_allocated_count) {
4479 if (hw->mac.type > e1000_82575) {
4480 /* Set the default pool for the PF's first queue */
4481 u32 vtctl = rd32(E1000_VT_CTL);
4483 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
4484 E1000_VT_CTL_DISABLE_DEF_POOL);
4485 vtctl |= adapter->vfs_allocated_count <<
4486 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
4487 wr32(E1000_VT_CTL, vtctl);
4489 if (adapter->rss_queues > 1)
4490 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ;
4492 mrqc |= E1000_MRQC_ENABLE_VMDQ;
4494 mrqc |= E1000_MRQC_ENABLE_RSS_MQ;
4496 igb_vmm_control(adapter);
4498 wr32(E1000_MRQC, mrqc);
4502 * igb_setup_rctl - configure the receive control registers
4503 * @adapter: Board private structure
4505 void igb_setup_rctl(struct igb_adapter *adapter)
4507 struct e1000_hw *hw = &adapter->hw;
4510 rctl = rd32(E1000_RCTL);
4512 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4513 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
4515 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
4516 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
4518 /* enable stripping of CRC. It's unlikely this will break BMC
4519 * redirection as it did with e1000. Newer features require
4520 * that the HW strips the CRC.
4522 rctl |= E1000_RCTL_SECRC;
4524 /* disable store bad packets and clear size bits. */
4525 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
4527 /* enable LPE to allow for reception of jumbo frames */
4528 rctl |= E1000_RCTL_LPE;
4530 /* disable queue 0 to prevent tail write w/o re-config */
4531 wr32(E1000_RXDCTL(0), 0);
4533 /* Attention!!! For SR-IOV PF driver operations you must enable
4534 * queue drop for all VF and PF queues to prevent head of line blocking
4535 * if an un-trusted VF does not provide descriptors to hardware.
4537 if (adapter->vfs_allocated_count) {
4538 /* set all queue drop enable bits */
4539 wr32(E1000_QDE, ALL_QUEUES);
4542 /* This is useful for sniffing bad packets. */
4543 if (adapter->netdev->features & NETIF_F_RXALL) {
4544 /* UPE and MPE will be handled by normal PROMISC logic
4545 * in e1000e_set_rx_mode
4547 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
4548 E1000_RCTL_BAM | /* RX All Bcast Pkts */
4549 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
4551 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
4552 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
4553 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
4554 * and that breaks VLANs.
4558 wr32(E1000_RCTL, rctl);
4561 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
4564 struct e1000_hw *hw = &adapter->hw;
4567 if (size > MAX_JUMBO_FRAME_SIZE)
4568 size = MAX_JUMBO_FRAME_SIZE;
4570 vmolr = rd32(E1000_VMOLR(vfn));
4571 vmolr &= ~E1000_VMOLR_RLPML_MASK;
4572 vmolr |= size | E1000_VMOLR_LPE;
4573 wr32(E1000_VMOLR(vfn), vmolr);
4578 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter,
4579 int vfn, bool enable)
4581 struct e1000_hw *hw = &adapter->hw;
4584 if (hw->mac.type < e1000_82576)
4587 if (hw->mac.type == e1000_i350)
4588 reg = E1000_DVMOLR(vfn);
4590 reg = E1000_VMOLR(vfn);
4594 val |= E1000_VMOLR_STRVLAN;
4596 val &= ~(E1000_VMOLR_STRVLAN);
4600 static inline void igb_set_vmolr(struct igb_adapter *adapter,
4603 struct e1000_hw *hw = &adapter->hw;
4606 /* This register exists only on 82576 and newer so if we are older then
4607 * we should exit and do nothing
4609 if (hw->mac.type < e1000_82576)
4612 vmolr = rd32(E1000_VMOLR(vfn));
4614 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
4616 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
4618 /* clear all bits that might not be set */
4619 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
4621 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
4622 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
4623 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
4626 if (vfn <= adapter->vfs_allocated_count)
4627 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
4629 wr32(E1000_VMOLR(vfn), vmolr);
4633 * igb_setup_srrctl - configure the split and replication receive control
4635 * @adapter: Board private structure
4636 * @ring: receive ring to be configured
4638 void igb_setup_srrctl(struct igb_adapter *adapter, struct igb_ring *ring)
4640 struct e1000_hw *hw = &adapter->hw;
4641 int reg_idx = ring->reg_idx;
4644 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
4645 if (ring_uses_large_buffer(ring))
4646 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4648 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4649 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
4650 if (hw->mac.type >= e1000_82580)
4651 srrctl |= E1000_SRRCTL_TIMESTAMP;
4652 /* Only set Drop Enable if VFs allocated, or we are supporting multiple
4653 * queues and rx flow control is disabled
4655 if (adapter->vfs_allocated_count ||
4656 (!(hw->fc.current_mode & e1000_fc_rx_pause) &&
4657 adapter->num_rx_queues > 1))
4658 srrctl |= E1000_SRRCTL_DROP_EN;
4660 wr32(E1000_SRRCTL(reg_idx), srrctl);
4664 * igb_configure_rx_ring - Configure a receive ring after Reset
4665 * @adapter: board private structure
4666 * @ring: receive ring to be configured
4668 * Configure the Rx unit of the MAC after a reset.
4670 void igb_configure_rx_ring(struct igb_adapter *adapter,
4671 struct igb_ring *ring)
4673 struct e1000_hw *hw = &adapter->hw;
4674 union e1000_adv_rx_desc *rx_desc;
4675 u64 rdba = ring->dma;
4676 int reg_idx = ring->reg_idx;
4679 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);
4680 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
4681 MEM_TYPE_PAGE_SHARED, NULL));
4683 /* disable the queue */
4684 wr32(E1000_RXDCTL(reg_idx), 0);
4686 /* Set DMA base address registers */
4687 wr32(E1000_RDBAL(reg_idx),
4688 rdba & 0x00000000ffffffffULL);
4689 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
4690 wr32(E1000_RDLEN(reg_idx),
4691 ring->count * sizeof(union e1000_adv_rx_desc));
4693 /* initialize head and tail */
4694 ring->tail = adapter->io_addr + E1000_RDT(reg_idx);
4695 wr32(E1000_RDH(reg_idx), 0);
4696 writel(0, ring->tail);
4698 /* set descriptor configuration */
4699 igb_setup_srrctl(adapter, ring);
4701 /* set filtering for VMDQ pools */
4702 igb_set_vmolr(adapter, reg_idx & 0x7, true);
4704 rxdctl |= IGB_RX_PTHRESH;
4705 rxdctl |= IGB_RX_HTHRESH << 8;
4706 rxdctl |= IGB_RX_WTHRESH << 16;
4708 /* initialize rx_buffer_info */
4709 memset(ring->rx_buffer_info, 0,
4710 sizeof(struct igb_rx_buffer) * ring->count);
4712 /* initialize Rx descriptor 0 */
4713 rx_desc = IGB_RX_DESC(ring, 0);
4714 rx_desc->wb.upper.length = 0;
4716 /* enable receive descriptor fetching */
4717 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
4718 wr32(E1000_RXDCTL(reg_idx), rxdctl);
4721 static void igb_set_rx_buffer_len(struct igb_adapter *adapter,
4722 struct igb_ring *rx_ring)
4724 /* set build_skb and buffer size flags */
4725 clear_ring_build_skb_enabled(rx_ring);
4726 clear_ring_uses_large_buffer(rx_ring);
4728 if (adapter->flags & IGB_FLAG_RX_LEGACY)
4731 set_ring_build_skb_enabled(rx_ring);
4733 #if (PAGE_SIZE < 8192)
4734 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
4737 set_ring_uses_large_buffer(rx_ring);
4742 * igb_configure_rx - Configure receive Unit after Reset
4743 * @adapter: board private structure
4745 * Configure the Rx unit of the MAC after a reset.
4747 static void igb_configure_rx(struct igb_adapter *adapter)
4751 /* set the correct pool for the PF default MAC address in entry 0 */
4752 igb_set_default_mac_filter(adapter);
4754 /* Setup the HW Rx Head and Tail Descriptor Pointers and
4755 * the Base and Length of the Rx Descriptor Ring
4757 for (i = 0; i < adapter->num_rx_queues; i++) {
4758 struct igb_ring *rx_ring = adapter->rx_ring[i];
4760 igb_set_rx_buffer_len(adapter, rx_ring);
4761 igb_configure_rx_ring(adapter, rx_ring);
4766 * igb_free_tx_resources - Free Tx Resources per Queue
4767 * @tx_ring: Tx descriptor ring for a specific queue
4769 * Free all transmit software resources
4771 void igb_free_tx_resources(struct igb_ring *tx_ring)
4773 igb_clean_tx_ring(tx_ring);
4775 vfree(tx_ring->tx_buffer_info);
4776 tx_ring->tx_buffer_info = NULL;
4778 /* if not set, then don't free */
4782 dma_free_coherent(tx_ring->dev, tx_ring->size,
4783 tx_ring->desc, tx_ring->dma);
4785 tx_ring->desc = NULL;
4789 * igb_free_all_tx_resources - Free Tx Resources for All Queues
4790 * @adapter: board private structure
4792 * Free all transmit software resources
4794 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
4798 for (i = 0; i < adapter->num_tx_queues; i++)
4799 if (adapter->tx_ring[i])
4800 igb_free_tx_resources(adapter->tx_ring[i]);
4804 * igb_clean_tx_ring - Free Tx Buffers
4805 * @tx_ring: ring to be cleaned
4807 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
4809 u16 i = tx_ring->next_to_clean;
4810 struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
4812 while (i != tx_ring->next_to_use) {
4813 union e1000_adv_tx_desc *eop_desc, *tx_desc;
4815 /* Free all the Tx ring sk_buffs */
4816 dev_kfree_skb_any(tx_buffer->skb);
4818 /* unmap skb header data */
4819 dma_unmap_single(tx_ring->dev,
4820 dma_unmap_addr(tx_buffer, dma),
4821 dma_unmap_len(tx_buffer, len),
4824 /* check for eop_desc to determine the end of the packet */
4825 eop_desc = tx_buffer->next_to_watch;
4826 tx_desc = IGB_TX_DESC(tx_ring, i);
4828 /* unmap remaining buffers */
4829 while (tx_desc != eop_desc) {
4833 if (unlikely(i == tx_ring->count)) {
4835 tx_buffer = tx_ring->tx_buffer_info;
4836 tx_desc = IGB_TX_DESC(tx_ring, 0);
4839 /* unmap any remaining paged data */
4840 if (dma_unmap_len(tx_buffer, len))
4841 dma_unmap_page(tx_ring->dev,
4842 dma_unmap_addr(tx_buffer, dma),
4843 dma_unmap_len(tx_buffer, len),
4847 tx_buffer->next_to_watch = NULL;
4849 /* move us one more past the eop_desc for start of next pkt */
4852 if (unlikely(i == tx_ring->count)) {
4854 tx_buffer = tx_ring->tx_buffer_info;
4858 /* reset BQL for queue */
4859 netdev_tx_reset_queue(txring_txq(tx_ring));
4861 /* reset next_to_use and next_to_clean */
4862 tx_ring->next_to_use = 0;
4863 tx_ring->next_to_clean = 0;
4867 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
4868 * @adapter: board private structure
4870 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
4874 for (i = 0; i < adapter->num_tx_queues; i++)
4875 if (adapter->tx_ring[i])
4876 igb_clean_tx_ring(adapter->tx_ring[i]);
4880 * igb_free_rx_resources - Free Rx Resources
4881 * @rx_ring: ring to clean the resources from
4883 * Free all receive software resources
4885 void igb_free_rx_resources(struct igb_ring *rx_ring)
4887 igb_clean_rx_ring(rx_ring);
4889 rx_ring->xdp_prog = NULL;
4890 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
4891 vfree(rx_ring->rx_buffer_info);
4892 rx_ring->rx_buffer_info = NULL;
4894 /* if not set, then don't free */
4898 dma_free_coherent(rx_ring->dev, rx_ring->size,
4899 rx_ring->desc, rx_ring->dma);
4901 rx_ring->desc = NULL;
4905 * igb_free_all_rx_resources - Free Rx Resources for All Queues
4906 * @adapter: board private structure
4908 * Free all receive software resources
4910 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
4914 for (i = 0; i < adapter->num_rx_queues; i++)
4915 if (adapter->rx_ring[i])
4916 igb_free_rx_resources(adapter->rx_ring[i]);
4920 * igb_clean_rx_ring - Free Rx Buffers per Queue
4921 * @rx_ring: ring to free buffers from
4923 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
4925 u16 i = rx_ring->next_to_clean;
4927 dev_kfree_skb(rx_ring->skb);
4928 rx_ring->skb = NULL;
4930 /* Free all the Rx ring sk_buffs */
4931 while (i != rx_ring->next_to_alloc) {
4932 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
4934 /* Invalidate cache lines that may have been written to by
4935 * device so that we avoid corrupting memory.
4937 dma_sync_single_range_for_cpu(rx_ring->dev,
4939 buffer_info->page_offset,
4940 igb_rx_bufsz(rx_ring),
4943 /* free resources associated with mapping */
4944 dma_unmap_page_attrs(rx_ring->dev,
4946 igb_rx_pg_size(rx_ring),
4949 __page_frag_cache_drain(buffer_info->page,
4950 buffer_info->pagecnt_bias);
4953 if (i == rx_ring->count)
4957 rx_ring->next_to_alloc = 0;
4958 rx_ring->next_to_clean = 0;
4959 rx_ring->next_to_use = 0;
4963 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
4964 * @adapter: board private structure
4966 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
4970 for (i = 0; i < adapter->num_rx_queues; i++)
4971 if (adapter->rx_ring[i])
4972 igb_clean_rx_ring(adapter->rx_ring[i]);
4976 * igb_set_mac - Change the Ethernet Address of the NIC
4977 * @netdev: network interface device structure
4978 * @p: pointer to an address structure
4980 * Returns 0 on success, negative on failure
4982 static int igb_set_mac(struct net_device *netdev, void *p)
4984 struct igb_adapter *adapter = netdev_priv(netdev);
4985 struct e1000_hw *hw = &adapter->hw;
4986 struct sockaddr *addr = p;
4988 if (!is_valid_ether_addr(addr->sa_data))
4989 return -EADDRNOTAVAIL;
4991 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4992 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
4994 /* set the correct pool for the new PF MAC address in entry 0 */
4995 igb_set_default_mac_filter(adapter);
5001 * igb_write_mc_addr_list - write multicast addresses to MTA
5002 * @netdev: network interface device structure
5004 * Writes multicast address list to the MTA hash table.
5005 * Returns: -ENOMEM on failure
5006 * 0 on no addresses written
5007 * X on writing X addresses to MTA
5009 static int igb_write_mc_addr_list(struct net_device *netdev)
5011 struct igb_adapter *adapter = netdev_priv(netdev);
5012 struct e1000_hw *hw = &adapter->hw;
5013 struct netdev_hw_addr *ha;
5017 if (netdev_mc_empty(netdev)) {
5018 /* nothing to program, so clear mc list */
5019 igb_update_mc_addr_list(hw, NULL, 0);
5020 igb_restore_vf_multicasts(adapter);
5024 mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC);
5028 /* The shared function expects a packed array of only addresses. */
5030 netdev_for_each_mc_addr(ha, netdev)
5031 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
5033 igb_update_mc_addr_list(hw, mta_list, i);
5036 return netdev_mc_count(netdev);
5039 static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
5041 struct e1000_hw *hw = &adapter->hw;
5044 switch (hw->mac.type) {
5048 /* VLAN filtering needed for VLAN prio filter */
5049 if (adapter->netdev->features & NETIF_F_NTUPLE)
5055 /* VLAN filtering needed for pool filtering */
5056 if (adapter->vfs_allocated_count)
5063 /* We are already in VLAN promisc, nothing to do */
5064 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
5067 if (!adapter->vfs_allocated_count)
5070 /* Add PF to all active pools */
5071 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
5073 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
5074 u32 vlvf = rd32(E1000_VLVF(i));
5077 wr32(E1000_VLVF(i), vlvf);
5081 /* Set all bits in the VLAN filter table array */
5082 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
5083 hw->mac.ops.write_vfta(hw, i, ~0U);
5085 /* Set flag so we don't redo unnecessary work */
5086 adapter->flags |= IGB_FLAG_VLAN_PROMISC;
5091 #define VFTA_BLOCK_SIZE 8
5092 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
5094 struct e1000_hw *hw = &adapter->hw;
5095 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
5096 u32 vid_start = vfta_offset * 32;
5097 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
5098 u32 i, vid, word, bits, pf_id;
5100 /* guarantee that we don't scrub out management VLAN */
5101 vid = adapter->mng_vlan_id;
5102 if (vid >= vid_start && vid < vid_end)
5103 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
5105 if (!adapter->vfs_allocated_count)
5108 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
5110 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
5111 u32 vlvf = rd32(E1000_VLVF(i));
5113 /* pull VLAN ID from VLVF */
5114 vid = vlvf & VLAN_VID_MASK;
5116 /* only concern ourselves with a certain range */
5117 if (vid < vid_start || vid >= vid_end)
5120 if (vlvf & E1000_VLVF_VLANID_ENABLE) {
5121 /* record VLAN ID in VFTA */
5122 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
5124 /* if PF is part of this then continue */
5125 if (test_bit(vid, adapter->active_vlans))
5129 /* remove PF from the pool */
5131 bits &= rd32(E1000_VLVF(i));
5132 wr32(E1000_VLVF(i), bits);
5136 /* extract values from active_vlans and write back to VFTA */
5137 for (i = VFTA_BLOCK_SIZE; i--;) {
5138 vid = (vfta_offset + i) * 32;
5139 word = vid / BITS_PER_LONG;
5140 bits = vid % BITS_PER_LONG;
5142 vfta[i] |= adapter->active_vlans[word] >> bits;
5144 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
5148 static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
5152 /* We are not in VLAN promisc, nothing to do */
5153 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
5156 /* Set flag so we don't redo unnecessary work */
5157 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
5159 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
5160 igb_scrub_vfta(adapter, i);
5164 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
5165 * @netdev: network interface device structure
5167 * The set_rx_mode entry point is called whenever the unicast or multicast
5168 * address lists or the network interface flags are updated. This routine is
5169 * responsible for configuring the hardware for proper unicast, multicast,
5170 * promiscuous mode, and all-multi behavior.
5172 static void igb_set_rx_mode(struct net_device *netdev)
5174 struct igb_adapter *adapter = netdev_priv(netdev);
5175 struct e1000_hw *hw = &adapter->hw;
5176 unsigned int vfn = adapter->vfs_allocated_count;
5177 u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE;
5180 /* Check for Promiscuous and All Multicast modes */
5181 if (netdev->flags & IFF_PROMISC) {
5182 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
5183 vmolr |= E1000_VMOLR_MPME;
5185 /* enable use of UTA filter to force packets to default pool */
5186 if (hw->mac.type == e1000_82576)
5187 vmolr |= E1000_VMOLR_ROPE;
5189 if (netdev->flags & IFF_ALLMULTI) {
5190 rctl |= E1000_RCTL_MPE;
5191 vmolr |= E1000_VMOLR_MPME;
5193 /* Write addresses to the MTA, if the attempt fails
5194 * then we should just turn on promiscuous mode so
5195 * that we can at least receive multicast traffic
5197 count = igb_write_mc_addr_list(netdev);
5199 rctl |= E1000_RCTL_MPE;
5200 vmolr |= E1000_VMOLR_MPME;
5202 vmolr |= E1000_VMOLR_ROMPE;
5207 /* Write addresses to available RAR registers, if there is not
5208 * sufficient space to store all the addresses then enable
5209 * unicast promiscuous mode
5211 if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) {
5212 rctl |= E1000_RCTL_UPE;
5213 vmolr |= E1000_VMOLR_ROPE;
5216 /* enable VLAN filtering by default */
5217 rctl |= E1000_RCTL_VFE;
5219 /* disable VLAN filtering for modes that require it */
5220 if ((netdev->flags & IFF_PROMISC) ||
5221 (netdev->features & NETIF_F_RXALL)) {
5222 /* if we fail to set all rules then just clear VFE */
5223 if (igb_vlan_promisc_enable(adapter))
5224 rctl &= ~E1000_RCTL_VFE;
5226 igb_vlan_promisc_disable(adapter);
5229 /* update state of unicast, multicast, and VLAN filtering modes */
5230 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
5232 wr32(E1000_RCTL, rctl);
5234 #if (PAGE_SIZE < 8192)
5235 if (!adapter->vfs_allocated_count) {
5236 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
5237 rlpml = IGB_MAX_FRAME_BUILD_SKB;
5240 wr32(E1000_RLPML, rlpml);
5242 /* In order to support SR-IOV and eventually VMDq it is necessary to set
5243 * the VMOLR to enable the appropriate modes. Without this workaround
5244 * we will have issues with VLAN tag stripping not being done for frames
5245 * that are only arriving because we are the default pool
5247 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
5250 /* set UTA to appropriate mode */
5251 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE));
5253 vmolr |= rd32(E1000_VMOLR(vfn)) &
5254 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
5256 /* enable Rx jumbo frames, restrict as needed to support build_skb */
5257 vmolr &= ~E1000_VMOLR_RLPML_MASK;
5258 #if (PAGE_SIZE < 8192)
5259 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
5260 vmolr |= IGB_MAX_FRAME_BUILD_SKB;
5263 vmolr |= MAX_JUMBO_FRAME_SIZE;
5264 vmolr |= E1000_VMOLR_LPE;
5266 wr32(E1000_VMOLR(vfn), vmolr);
5268 igb_restore_vf_multicasts(adapter);
5271 static void igb_check_wvbr(struct igb_adapter *adapter)
5273 struct e1000_hw *hw = &adapter->hw;
5276 switch (hw->mac.type) {
5279 wvbr = rd32(E1000_WVBR);
5287 adapter->wvbr |= wvbr;
5290 #define IGB_STAGGERED_QUEUE_OFFSET 8
5292 static void igb_spoof_check(struct igb_adapter *adapter)
5299 for (j = 0; j < adapter->vfs_allocated_count; j++) {
5300 if (adapter->wvbr & BIT(j) ||
5301 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) {
5302 dev_warn(&adapter->pdev->dev,
5303 "Spoof event(s) detected on VF %d\n", j);
5306 BIT(j + IGB_STAGGERED_QUEUE_OFFSET));
5311 /* Need to wait a few seconds after link up to get diagnostic information from
5314 static void igb_update_phy_info(struct timer_list *t)
5316 struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer);
5317 igb_get_phy_info(&adapter->hw);
5321 * igb_has_link - check shared code for link and determine up/down
5322 * @adapter: pointer to driver private info
5324 bool igb_has_link(struct igb_adapter *adapter)
5326 struct e1000_hw *hw = &adapter->hw;
5327 bool link_active = false;
5329 /* get_link_status is set on LSC (link status) interrupt or
5330 * rx sequence error interrupt. get_link_status will stay
5331 * false until the e1000_check_for_link establishes link
5332 * for copper adapters ONLY
5334 switch (hw->phy.media_type) {
5335 case e1000_media_type_copper:
5336 if (!hw->mac.get_link_status)
5339 case e1000_media_type_internal_serdes:
5340 hw->mac.ops.check_for_link(hw);
5341 link_active = !hw->mac.get_link_status;
5344 case e1000_media_type_unknown:
5348 if (((hw->mac.type == e1000_i210) ||
5349 (hw->mac.type == e1000_i211)) &&
5350 (hw->phy.id == I210_I_PHY_ID)) {
5351 if (!netif_carrier_ok(adapter->netdev)) {
5352 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
5353 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
5354 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
5355 adapter->link_check_timeout = jiffies;
5362 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
5365 u32 ctrl_ext, thstat;
5367 /* check for thermal sensor event on i350 copper only */
5368 if (hw->mac.type == e1000_i350) {
5369 thstat = rd32(E1000_THSTAT);
5370 ctrl_ext = rd32(E1000_CTRL_EXT);
5372 if ((hw->phy.media_type == e1000_media_type_copper) &&
5373 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
5374 ret = !!(thstat & event);
5381 * igb_check_lvmmc - check for malformed packets received
5382 * and indicated in LVMMC register
5383 * @adapter: pointer to adapter
5385 static void igb_check_lvmmc(struct igb_adapter *adapter)
5387 struct e1000_hw *hw = &adapter->hw;
5390 lvmmc = rd32(E1000_LVMMC);
5392 if (unlikely(net_ratelimit())) {
5393 netdev_warn(adapter->netdev,
5394 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
5401 * igb_watchdog - Timer Call-back
5402 * @t: pointer to timer_list containing our private info pointer
5404 static void igb_watchdog(struct timer_list *t)
5406 struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5407 /* Do the rest outside of interrupt context */
5408 schedule_work(&adapter->watchdog_task);
5411 static void igb_watchdog_task(struct work_struct *work)
5413 struct igb_adapter *adapter = container_of(work,
5416 struct e1000_hw *hw = &adapter->hw;
5417 struct e1000_phy_info *phy = &hw->phy;
5418 struct net_device *netdev = adapter->netdev;
5422 u16 phy_data, retry_count = 20;
5424 link = igb_has_link(adapter);
5426 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
5427 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
5428 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
5433 /* Force link down if we have fiber to swap to */
5434 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5435 if (hw->phy.media_type == e1000_media_type_copper) {
5436 connsw = rd32(E1000_CONNSW);
5437 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
5442 /* Perform a reset if the media type changed. */
5443 if (hw->dev_spec._82575.media_changed) {
5444 hw->dev_spec._82575.media_changed = false;
5445 adapter->flags |= IGB_FLAG_MEDIA_RESET;
5448 /* Cancel scheduled suspend requests. */
5449 pm_runtime_resume(netdev->dev.parent);
5451 if (!netif_carrier_ok(netdev)) {
5454 hw->mac.ops.get_speed_and_duplex(hw,
5455 &adapter->link_speed,
5456 &adapter->link_duplex);
5458 ctrl = rd32(E1000_CTRL);
5459 /* Links status message must follow this format */
5461 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5463 adapter->link_speed,
5464 adapter->link_duplex == FULL_DUPLEX ?
5466 (ctrl & E1000_CTRL_TFCE) &&
5467 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
5468 (ctrl & E1000_CTRL_RFCE) ? "RX" :
5469 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
5471 /* disable EEE if enabled */
5472 if ((adapter->flags & IGB_FLAG_EEE) &&
5473 (adapter->link_duplex == HALF_DUPLEX)) {
5474 dev_info(&adapter->pdev->dev,
5475 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
5476 adapter->hw.dev_spec._82575.eee_disable = true;
5477 adapter->flags &= ~IGB_FLAG_EEE;
5480 /* check if SmartSpeed worked */
5481 igb_check_downshift(hw);
5482 if (phy->speed_downgraded)
5483 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
5485 /* check for thermal sensor event */
5486 if (igb_thermal_sensor_event(hw,
5487 E1000_THSTAT_LINK_THROTTLE))
5488 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
5490 /* adjust timeout factor according to speed/duplex */
5491 adapter->tx_timeout_factor = 1;
5492 switch (adapter->link_speed) {
5494 adapter->tx_timeout_factor = 14;
5497 /* maybe add some timeout factor ? */
5501 if (adapter->link_speed != SPEED_1000)
5504 /* wait for Remote receiver status OK */
5506 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
5508 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
5512 goto retry_read_status;
5513 } else if (!retry_count) {
5514 dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
5517 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
5520 netif_carrier_on(netdev);
5522 igb_ping_all_vfs(adapter);
5523 igb_check_vf_rate_limit(adapter);
5525 /* link state has changed, schedule phy info update */
5526 if (!test_bit(__IGB_DOWN, &adapter->state))
5527 mod_timer(&adapter->phy_info_timer,
5528 round_jiffies(jiffies + 2 * HZ));
5531 if (netif_carrier_ok(netdev)) {
5532 adapter->link_speed = 0;
5533 adapter->link_duplex = 0;
5535 /* check for thermal sensor event */
5536 if (igb_thermal_sensor_event(hw,
5537 E1000_THSTAT_PWR_DOWN)) {
5538 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
5541 /* Links status message must follow this format */
5542 netdev_info(netdev, "igb: %s NIC Link is Down\n",
5544 netif_carrier_off(netdev);
5546 igb_ping_all_vfs(adapter);
5548 /* link state has changed, schedule phy info update */
5549 if (!test_bit(__IGB_DOWN, &adapter->state))
5550 mod_timer(&adapter->phy_info_timer,
5551 round_jiffies(jiffies + 2 * HZ));
5553 /* link is down, time to check for alternate media */
5554 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5555 igb_check_swap_media(adapter);
5556 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5557 schedule_work(&adapter->reset_task);
5558 /* return immediately */
5562 pm_schedule_suspend(netdev->dev.parent,
5565 /* also check for alternate media here */
5566 } else if (!netif_carrier_ok(netdev) &&
5567 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
5568 igb_check_swap_media(adapter);
5569 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5570 schedule_work(&adapter->reset_task);
5571 /* return immediately */
5577 spin_lock(&adapter->stats64_lock);
5578 igb_update_stats(adapter);
5579 spin_unlock(&adapter->stats64_lock);
5581 for (i = 0; i < adapter->num_tx_queues; i++) {
5582 struct igb_ring *tx_ring = adapter->tx_ring[i];
5583 if (!netif_carrier_ok(netdev)) {
5584 /* We've lost link, so the controller stops DMA,
5585 * but we've got queued Tx work that's never going
5586 * to get done, so reset controller to flush Tx.
5587 * (Do the reset outside of interrupt context).
5589 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
5590 adapter->tx_timeout_count++;
5591 schedule_work(&adapter->reset_task);
5592 /* return immediately since reset is imminent */
5597 /* Force detection of hung controller every watchdog period */
5598 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
5601 /* Cause software interrupt to ensure Rx ring is cleaned */
5602 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
5605 for (i = 0; i < adapter->num_q_vectors; i++)
5606 eics |= adapter->q_vector[i]->eims_value;
5607 wr32(E1000_EICS, eics);
5609 wr32(E1000_ICS, E1000_ICS_RXDMT0);
5612 igb_spoof_check(adapter);
5613 igb_ptp_rx_hang(adapter);
5614 igb_ptp_tx_hang(adapter);
5616 /* Check LVMMC register on i350/i354 only */
5617 if ((adapter->hw.mac.type == e1000_i350) ||
5618 (adapter->hw.mac.type == e1000_i354))
5619 igb_check_lvmmc(adapter);
5621 /* Reset the timer */
5622 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5623 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
5624 mod_timer(&adapter->watchdog_timer,
5625 round_jiffies(jiffies + HZ));
5627 mod_timer(&adapter->watchdog_timer,
5628 round_jiffies(jiffies + 2 * HZ));
5632 enum latency_range {
5636 latency_invalid = 255
5640 * igb_update_ring_itr - update the dynamic ITR value based on packet size
5641 * @q_vector: pointer to q_vector
5643 * Stores a new ITR value based on strictly on packet size. This
5644 * algorithm is less sophisticated than that used in igb_update_itr,
5645 * due to the difficulty of synchronizing statistics across multiple
5646 * receive rings. The divisors and thresholds used by this function
5647 * were determined based on theoretical maximum wire speed and testing
5648 * data, in order to minimize response time while increasing bulk
5650 * This functionality is controlled by ethtool's coalescing settings.
5651 * NOTE: This function is called only when operating in a multiqueue
5652 * receive environment.
5654 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
5656 int new_val = q_vector->itr_val;
5657 int avg_wire_size = 0;
5658 struct igb_adapter *adapter = q_vector->adapter;
5659 unsigned int packets;
5661 /* For non-gigabit speeds, just fix the interrupt rate at 4000
5662 * ints/sec - ITR timer value of 120 ticks.
5664 if (adapter->link_speed != SPEED_1000) {
5665 new_val = IGB_4K_ITR;
5669 packets = q_vector->rx.total_packets;
5671 avg_wire_size = q_vector->rx.total_bytes / packets;
5673 packets = q_vector->tx.total_packets;
5675 avg_wire_size = max_t(u32, avg_wire_size,
5676 q_vector->tx.total_bytes / packets);
5678 /* if avg_wire_size isn't set no work was done */
5682 /* Add 24 bytes to size to account for CRC, preamble, and gap */
5683 avg_wire_size += 24;
5685 /* Don't starve jumbo frames */
5686 avg_wire_size = min(avg_wire_size, 3000);
5688 /* Give a little boost to mid-size frames */
5689 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
5690 new_val = avg_wire_size / 3;
5692 new_val = avg_wire_size / 2;
5694 /* conservative mode (itr 3) eliminates the lowest_latency setting */
5695 if (new_val < IGB_20K_ITR &&
5696 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5697 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5698 new_val = IGB_20K_ITR;
5701 if (new_val != q_vector->itr_val) {
5702 q_vector->itr_val = new_val;
5703 q_vector->set_itr = 1;
5706 q_vector->rx.total_bytes = 0;
5707 q_vector->rx.total_packets = 0;
5708 q_vector->tx.total_bytes = 0;
5709 q_vector->tx.total_packets = 0;
5713 * igb_update_itr - update the dynamic ITR value based on statistics
5714 * @q_vector: pointer to q_vector
5715 * @ring_container: ring info to update the itr for
5717 * Stores a new ITR value based on packets and byte
5718 * counts during the last interrupt. The advantage of per interrupt
5719 * computation is faster updates and more accurate ITR for the current
5720 * traffic pattern. Constants in this function were computed
5721 * based on theoretical maximum wire speed and thresholds were set based
5722 * on testing data as well as attempting to minimize response time
5723 * while increasing bulk throughput.
5724 * This functionality is controlled by ethtool's coalescing settings.
5725 * NOTE: These calculations are only valid when operating in a single-
5726 * queue environment.
5728 static void igb_update_itr(struct igb_q_vector *q_vector,
5729 struct igb_ring_container *ring_container)
5731 unsigned int packets = ring_container->total_packets;
5732 unsigned int bytes = ring_container->total_bytes;
5733 u8 itrval = ring_container->itr;
5735 /* no packets, exit with status unchanged */
5740 case lowest_latency:
5741 /* handle TSO and jumbo frames */
5742 if (bytes/packets > 8000)
5743 itrval = bulk_latency;
5744 else if ((packets < 5) && (bytes > 512))
5745 itrval = low_latency;
5747 case low_latency: /* 50 usec aka 20000 ints/s */
5748 if (bytes > 10000) {
5749 /* this if handles the TSO accounting */
5750 if (bytes/packets > 8000)
5751 itrval = bulk_latency;
5752 else if ((packets < 10) || ((bytes/packets) > 1200))
5753 itrval = bulk_latency;
5754 else if ((packets > 35))
5755 itrval = lowest_latency;
5756 } else if (bytes/packets > 2000) {
5757 itrval = bulk_latency;
5758 } else if (packets <= 2 && bytes < 512) {
5759 itrval = lowest_latency;
5762 case bulk_latency: /* 250 usec aka 4000 ints/s */
5763 if (bytes > 25000) {
5765 itrval = low_latency;
5766 } else if (bytes < 1500) {
5767 itrval = low_latency;
5772 /* clear work counters since we have the values we need */
5773 ring_container->total_bytes = 0;
5774 ring_container->total_packets = 0;
5776 /* write updated itr to ring container */
5777 ring_container->itr = itrval;
5780 static void igb_set_itr(struct igb_q_vector *q_vector)
5782 struct igb_adapter *adapter = q_vector->adapter;
5783 u32 new_itr = q_vector->itr_val;
5786 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
5787 if (adapter->link_speed != SPEED_1000) {
5789 new_itr = IGB_4K_ITR;
5793 igb_update_itr(q_vector, &q_vector->tx);
5794 igb_update_itr(q_vector, &q_vector->rx);
5796 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
5798 /* conservative mode (itr 3) eliminates the lowest_latency setting */
5799 if (current_itr == lowest_latency &&
5800 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5801 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5802 current_itr = low_latency;
5804 switch (current_itr) {
5805 /* counts and packets in update_itr are dependent on these numbers */
5806 case lowest_latency:
5807 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
5810 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
5813 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
5820 if (new_itr != q_vector->itr_val) {
5821 /* this attempts to bias the interrupt rate towards Bulk
5822 * by adding intermediate steps when interrupt rate is
5825 new_itr = new_itr > q_vector->itr_val ?
5826 max((new_itr * q_vector->itr_val) /
5827 (new_itr + (q_vector->itr_val >> 2)),
5829 /* Don't write the value here; it resets the adapter's
5830 * internal timer, and causes us to delay far longer than
5831 * we should between interrupts. Instead, we write the ITR
5832 * value at the beginning of the next interrupt so the timing
5833 * ends up being correct.
5835 q_vector->itr_val = new_itr;
5836 q_vector->set_itr = 1;
5840 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring,
5841 struct igb_tx_buffer *first,
5842 u32 vlan_macip_lens, u32 type_tucmd,
5845 struct e1000_adv_tx_context_desc *context_desc;
5846 u16 i = tx_ring->next_to_use;
5847 struct timespec64 ts;
5849 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
5852 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
5854 /* set bits to identify this as an advanced context descriptor */
5855 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
5857 /* For 82575, context index must be unique per ring. */
5858 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
5859 mss_l4len_idx |= tx_ring->reg_idx << 4;
5861 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5862 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
5863 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5865 /* We assume there is always a valid tx time available. Invalid times
5866 * should have been handled by the upper layers.
5868 if (tx_ring->launchtime_enable) {
5869 ts = ktime_to_timespec64(first->skb->tstamp);
5870 skb_txtime_consumed(first->skb);
5871 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32);
5873 context_desc->seqnum_seed = 0;
5877 static int igb_tso(struct igb_ring *tx_ring,
5878 struct igb_tx_buffer *first,
5881 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
5882 struct sk_buff *skb = first->skb;
5893 u32 paylen, l4_offset;
5896 if (skb->ip_summed != CHECKSUM_PARTIAL)
5899 if (!skb_is_gso(skb))
5902 err = skb_cow_head(skb, 0);
5906 ip.hdr = skb_network_header(skb);
5907 l4.hdr = skb_checksum_start(skb);
5909 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5910 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ?
5911 E1000_ADVTXD_TUCMD_L4T_UDP : E1000_ADVTXD_TUCMD_L4T_TCP;
5913 /* initialize outer IP header fields */
5914 if (ip.v4->version == 4) {
5915 unsigned char *csum_start = skb_checksum_start(skb);
5916 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
5918 /* IP header will have to cancel out any data that
5919 * is not a part of the outer IP header
5921 ip.v4->check = csum_fold(csum_partial(trans_start,
5922 csum_start - trans_start,
5924 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
5927 first->tx_flags |= IGB_TX_FLAGS_TSO |
5931 ip.v6->payload_len = 0;
5932 first->tx_flags |= IGB_TX_FLAGS_TSO |
5936 /* determine offset of inner transport header */
5937 l4_offset = l4.hdr - skb->data;
5939 /* remove payload length from inner checksum */
5940 paylen = skb->len - l4_offset;
5941 if (type_tucmd & E1000_ADVTXD_TUCMD_L4T_TCP) {
5942 /* compute length of segmentation header */
5943 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
5944 csum_replace_by_diff(&l4.tcp->check,
5945 (__force __wsum)htonl(paylen));
5947 /* compute length of segmentation header */
5948 *hdr_len = sizeof(*l4.udp) + l4_offset;
5949 csum_replace_by_diff(&l4.udp->check,
5950 (__force __wsum)htonl(paylen));
5953 /* update gso size and bytecount with header size */
5954 first->gso_segs = skb_shinfo(skb)->gso_segs;
5955 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5958 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT;
5959 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
5961 /* VLAN MACLEN IPLEN */
5962 vlan_macip_lens = l4.hdr - ip.hdr;
5963 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT;
5964 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
5966 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens,
5967 type_tucmd, mss_l4len_idx);
5972 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
5974 struct sk_buff *skb = first->skb;
5975 u32 vlan_macip_lens = 0;
5978 if (skb->ip_summed != CHECKSUM_PARTIAL) {
5980 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) &&
5981 !tx_ring->launchtime_enable)
5986 switch (skb->csum_offset) {
5987 case offsetof(struct tcphdr, check):
5988 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
5990 case offsetof(struct udphdr, check):
5992 case offsetof(struct sctphdr, checksum):
5993 /* validate that this is actually an SCTP request */
5994 if (skb_csum_is_sctp(skb)) {
5995 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP;
6000 skb_checksum_help(skb);
6004 /* update TX checksum flag */
6005 first->tx_flags |= IGB_TX_FLAGS_CSUM;
6006 vlan_macip_lens = skb_checksum_start_offset(skb) -
6007 skb_network_offset(skb);
6009 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
6010 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
6012 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0);
6015 #define IGB_SET_FLAG(_input, _flag, _result) \
6016 ((_flag <= _result) ? \
6017 ((u32)(_input & _flag) * (_result / _flag)) : \
6018 ((u32)(_input & _flag) / (_flag / _result)))
6020 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
6022 /* set type for advanced descriptor with frame checksum insertion */
6023 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
6024 E1000_ADVTXD_DCMD_DEXT |
6025 E1000_ADVTXD_DCMD_IFCS;
6027 /* set HW vlan bit if vlan is present */
6028 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
6029 (E1000_ADVTXD_DCMD_VLE));
6031 /* set segmentation bits for TSO */
6032 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
6033 (E1000_ADVTXD_DCMD_TSE));
6035 /* set timestamp bit if present */
6036 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
6037 (E1000_ADVTXD_MAC_TSTAMP));
6039 /* insert frame checksum */
6040 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
6045 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
6046 union e1000_adv_tx_desc *tx_desc,
6047 u32 tx_flags, unsigned int paylen)
6049 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
6051 /* 82575 requires a unique index per ring */
6052 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
6053 olinfo_status |= tx_ring->reg_idx << 4;
6055 /* insert L4 checksum */
6056 olinfo_status |= IGB_SET_FLAG(tx_flags,
6058 (E1000_TXD_POPTS_TXSM << 8));
6060 /* insert IPv4 checksum */
6061 olinfo_status |= IGB_SET_FLAG(tx_flags,
6063 (E1000_TXD_POPTS_IXSM << 8));
6065 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6068 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
6070 struct net_device *netdev = tx_ring->netdev;
6072 netif_stop_subqueue(netdev, tx_ring->queue_index);
6074 /* Herbert's original patch had:
6075 * smp_mb__after_netif_stop_queue();
6076 * but since that doesn't exist yet, just open code it.
6080 /* We need to check again in a case another CPU has just
6081 * made room available.
6083 if (igb_desc_unused(tx_ring) < size)
6087 netif_wake_subqueue(netdev, tx_ring->queue_index);
6089 u64_stats_update_begin(&tx_ring->tx_syncp2);
6090 tx_ring->tx_stats.restart_queue2++;
6091 u64_stats_update_end(&tx_ring->tx_syncp2);
6096 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
6098 if (igb_desc_unused(tx_ring) >= size)
6100 return __igb_maybe_stop_tx(tx_ring, size);
6103 static int igb_tx_map(struct igb_ring *tx_ring,
6104 struct igb_tx_buffer *first,
6107 struct sk_buff *skb = first->skb;
6108 struct igb_tx_buffer *tx_buffer;
6109 union e1000_adv_tx_desc *tx_desc;
6112 unsigned int data_len, size;
6113 u32 tx_flags = first->tx_flags;
6114 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
6115 u16 i = tx_ring->next_to_use;
6117 tx_desc = IGB_TX_DESC(tx_ring, i);
6119 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
6121 size = skb_headlen(skb);
6122 data_len = skb->data_len;
6124 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6128 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6129 if (dma_mapping_error(tx_ring->dev, dma))
6132 /* record length, and DMA address */
6133 dma_unmap_len_set(tx_buffer, len, size);
6134 dma_unmap_addr_set(tx_buffer, dma, dma);
6136 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6138 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
6139 tx_desc->read.cmd_type_len =
6140 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
6144 if (i == tx_ring->count) {
6145 tx_desc = IGB_TX_DESC(tx_ring, 0);
6148 tx_desc->read.olinfo_status = 0;
6150 dma += IGB_MAX_DATA_PER_TXD;
6151 size -= IGB_MAX_DATA_PER_TXD;
6153 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6156 if (likely(!data_len))
6159 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
6163 if (i == tx_ring->count) {
6164 tx_desc = IGB_TX_DESC(tx_ring, 0);
6167 tx_desc->read.olinfo_status = 0;
6169 size = skb_frag_size(frag);
6172 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
6173 size, DMA_TO_DEVICE);
6175 tx_buffer = &tx_ring->tx_buffer_info[i];
6178 /* write last descriptor with RS and EOP bits */
6179 cmd_type |= size | IGB_TXD_DCMD;
6180 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6182 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6184 /* set the timestamp */
6185 first->time_stamp = jiffies;
6187 skb_tx_timestamp(skb);
6189 /* Force memory writes to complete before letting h/w know there
6190 * are new descriptors to fetch. (Only applicable for weak-ordered
6191 * memory model archs, such as IA-64).
6193 * We also need this memory barrier to make certain all of the
6194 * status bits have been updated before next_to_watch is written.
6198 /* set next_to_watch value indicating a packet is present */
6199 first->next_to_watch = tx_desc;
6202 if (i == tx_ring->count)
6205 tx_ring->next_to_use = i;
6207 /* Make sure there is space in the ring for the next send. */
6208 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
6210 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
6211 writel(i, tx_ring->tail);
6216 dev_err(tx_ring->dev, "TX DMA map failed\n");
6217 tx_buffer = &tx_ring->tx_buffer_info[i];
6219 /* clear dma mappings for failed tx_buffer_info map */
6220 while (tx_buffer != first) {
6221 if (dma_unmap_len(tx_buffer, len))
6222 dma_unmap_page(tx_ring->dev,
6223 dma_unmap_addr(tx_buffer, dma),
6224 dma_unmap_len(tx_buffer, len),
6226 dma_unmap_len_set(tx_buffer, len, 0);
6229 i += tx_ring->count;
6230 tx_buffer = &tx_ring->tx_buffer_info[i];
6233 if (dma_unmap_len(tx_buffer, len))
6234 dma_unmap_single(tx_ring->dev,
6235 dma_unmap_addr(tx_buffer, dma),
6236 dma_unmap_len(tx_buffer, len),
6238 dma_unmap_len_set(tx_buffer, len, 0);
6240 dev_kfree_skb_any(tx_buffer->skb);
6241 tx_buffer->skb = NULL;
6243 tx_ring->next_to_use = i;
6248 int igb_xmit_xdp_ring(struct igb_adapter *adapter,
6249 struct igb_ring *tx_ring,
6250 struct xdp_frame *xdpf)
6252 union e1000_adv_tx_desc *tx_desc;
6253 u32 len, cmd_type, olinfo_status;
6254 struct igb_tx_buffer *tx_buffer;
6260 if (unlikely(!igb_desc_unused(tx_ring)))
6261 return IGB_XDP_CONSUMED;
6263 dma = dma_map_single(tx_ring->dev, xdpf->data, len, DMA_TO_DEVICE);
6264 if (dma_mapping_error(tx_ring->dev, dma))
6265 return IGB_XDP_CONSUMED;
6267 /* record the location of the first descriptor for this packet */
6268 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6269 tx_buffer->bytecount = len;
6270 tx_buffer->gso_segs = 1;
6271 tx_buffer->protocol = 0;
6273 i = tx_ring->next_to_use;
6274 tx_desc = IGB_TX_DESC(tx_ring, i);
6276 dma_unmap_len_set(tx_buffer, len, len);
6277 dma_unmap_addr_set(tx_buffer, dma, dma);
6278 tx_buffer->type = IGB_TYPE_XDP;
6279 tx_buffer->xdpf = xdpf;
6281 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6283 /* put descriptor type bits */
6284 cmd_type = E1000_ADVTXD_DTYP_DATA |
6285 E1000_ADVTXD_DCMD_DEXT |
6286 E1000_ADVTXD_DCMD_IFCS;
6287 cmd_type |= len | IGB_TXD_DCMD;
6288 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6290 olinfo_status = len << E1000_ADVTXD_PAYLEN_SHIFT;
6291 /* 82575 requires a unique index per ring */
6292 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
6293 olinfo_status |= tx_ring->reg_idx << 4;
6295 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6297 netdev_tx_sent_queue(txring_txq(tx_ring), tx_buffer->bytecount);
6299 /* set the timestamp */
6300 tx_buffer->time_stamp = jiffies;
6302 /* Avoid any potential race with xdp_xmit and cleanup */
6305 /* set next_to_watch value indicating a packet is present */
6307 if (i == tx_ring->count)
6310 tx_buffer->next_to_watch = tx_desc;
6311 tx_ring->next_to_use = i;
6313 /* Make sure there is space in the ring for the next send. */
6314 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
6316 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more())
6317 writel(i, tx_ring->tail);
6322 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
6323 struct igb_ring *tx_ring)
6325 struct igb_tx_buffer *first;
6329 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6330 __be16 protocol = vlan_get_protocol(skb);
6333 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
6334 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
6335 * + 2 desc gap to keep tail from touching head,
6336 * + 1 desc for context descriptor,
6337 * otherwise try next time
6339 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6340 count += TXD_USE_COUNT(skb_frag_size(
6341 &skb_shinfo(skb)->frags[f]));
6343 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
6344 /* this is a hard error */
6345 return NETDEV_TX_BUSY;
6348 /* record the location of the first descriptor for this packet */
6349 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6350 first->type = IGB_TYPE_SKB;
6352 first->bytecount = skb->len;
6353 first->gso_segs = 1;
6355 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6356 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
6358 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
6359 !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
6361 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6362 tx_flags |= IGB_TX_FLAGS_TSTAMP;
6364 adapter->ptp_tx_skb = skb_get(skb);
6365 adapter->ptp_tx_start = jiffies;
6366 if (adapter->hw.mac.type == e1000_82576)
6367 schedule_work(&adapter->ptp_tx_work);
6369 adapter->tx_hwtstamp_skipped++;
6373 if (skb_vlan_tag_present(skb)) {
6374 tx_flags |= IGB_TX_FLAGS_VLAN;
6375 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
6378 /* record initial flags and protocol */
6379 first->tx_flags = tx_flags;
6380 first->protocol = protocol;
6382 tso = igb_tso(tx_ring, first, &hdr_len);
6386 igb_tx_csum(tx_ring, first);
6388 if (igb_tx_map(tx_ring, first, hdr_len))
6389 goto cleanup_tx_tstamp;
6391 return NETDEV_TX_OK;
6394 dev_kfree_skb_any(first->skb);
6397 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) {
6398 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
6400 dev_kfree_skb_any(adapter->ptp_tx_skb);
6401 adapter->ptp_tx_skb = NULL;
6402 if (adapter->hw.mac.type == e1000_82576)
6403 cancel_work_sync(&adapter->ptp_tx_work);
6404 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
6407 return NETDEV_TX_OK;
6410 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
6411 struct sk_buff *skb)
6413 unsigned int r_idx = skb->queue_mapping;
6415 if (r_idx >= adapter->num_tx_queues)
6416 r_idx = r_idx % adapter->num_tx_queues;
6418 return adapter->tx_ring[r_idx];
6421 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
6422 struct net_device *netdev)
6424 struct igb_adapter *adapter = netdev_priv(netdev);
6426 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
6427 * in order to meet this minimum size requirement.
6429 if (skb_put_padto(skb, 17))
6430 return NETDEV_TX_OK;
6432 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
6436 * igb_tx_timeout - Respond to a Tx Hang
6437 * @netdev: network interface device structure
6438 * @txqueue: number of the Tx queue that hung (unused)
6440 static void igb_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
6442 struct igb_adapter *adapter = netdev_priv(netdev);
6443 struct e1000_hw *hw = &adapter->hw;
6445 /* Do the reset outside of interrupt context */
6446 adapter->tx_timeout_count++;
6448 if (hw->mac.type >= e1000_82580)
6449 hw->dev_spec._82575.global_device_reset = true;
6451 schedule_work(&adapter->reset_task);
6453 (adapter->eims_enable_mask & ~adapter->eims_other));
6456 static void igb_reset_task(struct work_struct *work)
6458 struct igb_adapter *adapter;
6459 adapter = container_of(work, struct igb_adapter, reset_task);
6462 /* If we're already down or resetting, just bail */
6463 if (test_bit(__IGB_DOWN, &adapter->state) ||
6464 test_bit(__IGB_RESETTING, &adapter->state)) {
6470 netdev_err(adapter->netdev, "Reset adapter\n");
6471 igb_reinit_locked(adapter);
6476 * igb_get_stats64 - Get System Network Statistics
6477 * @netdev: network interface device structure
6478 * @stats: rtnl_link_stats64 pointer
6480 static void igb_get_stats64(struct net_device *netdev,
6481 struct rtnl_link_stats64 *stats)
6483 struct igb_adapter *adapter = netdev_priv(netdev);
6485 spin_lock(&adapter->stats64_lock);
6486 igb_update_stats(adapter);
6487 memcpy(stats, &adapter->stats64, sizeof(*stats));
6488 spin_unlock(&adapter->stats64_lock);
6492 * igb_change_mtu - Change the Maximum Transfer Unit
6493 * @netdev: network interface device structure
6494 * @new_mtu: new value for maximum frame size
6496 * Returns 0 on success, negative on failure
6498 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
6500 struct igb_adapter *adapter = netdev_priv(netdev);
6501 int max_frame = new_mtu + IGB_ETH_PKT_HDR_PAD;
6503 if (adapter->xdp_prog) {
6506 for (i = 0; i < adapter->num_rx_queues; i++) {
6507 struct igb_ring *ring = adapter->rx_ring[i];
6509 if (max_frame > igb_rx_bufsz(ring)) {
6510 netdev_warn(adapter->netdev,
6511 "Requested MTU size is not supported with XDP. Max frame size is %d\n",
6518 /* adjust max frame to be at least the size of a standard frame */
6519 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
6520 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
6522 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
6523 usleep_range(1000, 2000);
6525 /* igb_down has a dependency on max_frame_size */
6526 adapter->max_frame_size = max_frame;
6528 if (netif_running(netdev))
6531 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6532 netdev->mtu, new_mtu);
6533 netdev->mtu = new_mtu;
6535 if (netif_running(netdev))
6540 clear_bit(__IGB_RESETTING, &adapter->state);
6546 * igb_update_stats - Update the board statistics counters
6547 * @adapter: board private structure
6549 void igb_update_stats(struct igb_adapter *adapter)
6551 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
6552 struct e1000_hw *hw = &adapter->hw;
6553 struct pci_dev *pdev = adapter->pdev;
6558 u64 _bytes, _packets;
6560 /* Prevent stats update while adapter is being reset, or if the pci
6561 * connection is down.
6563 if (adapter->link_speed == 0)
6565 if (pci_channel_offline(pdev))
6572 for (i = 0; i < adapter->num_rx_queues; i++) {
6573 struct igb_ring *ring = adapter->rx_ring[i];
6574 u32 rqdpc = rd32(E1000_RQDPC(i));
6575 if (hw->mac.type >= e1000_i210)
6576 wr32(E1000_RQDPC(i), 0);
6579 ring->rx_stats.drops += rqdpc;
6580 net_stats->rx_fifo_errors += rqdpc;
6584 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
6585 _bytes = ring->rx_stats.bytes;
6586 _packets = ring->rx_stats.packets;
6587 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
6589 packets += _packets;
6592 net_stats->rx_bytes = bytes;
6593 net_stats->rx_packets = packets;
6597 for (i = 0; i < adapter->num_tx_queues; i++) {
6598 struct igb_ring *ring = adapter->tx_ring[i];
6600 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
6601 _bytes = ring->tx_stats.bytes;
6602 _packets = ring->tx_stats.packets;
6603 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
6605 packets += _packets;
6607 net_stats->tx_bytes = bytes;
6608 net_stats->tx_packets = packets;
6611 /* read stats registers */
6612 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
6613 adapter->stats.gprc += rd32(E1000_GPRC);
6614 adapter->stats.gorc += rd32(E1000_GORCL);
6615 rd32(E1000_GORCH); /* clear GORCL */
6616 adapter->stats.bprc += rd32(E1000_BPRC);
6617 adapter->stats.mprc += rd32(E1000_MPRC);
6618 adapter->stats.roc += rd32(E1000_ROC);
6620 adapter->stats.prc64 += rd32(E1000_PRC64);
6621 adapter->stats.prc127 += rd32(E1000_PRC127);
6622 adapter->stats.prc255 += rd32(E1000_PRC255);
6623 adapter->stats.prc511 += rd32(E1000_PRC511);
6624 adapter->stats.prc1023 += rd32(E1000_PRC1023);
6625 adapter->stats.prc1522 += rd32(E1000_PRC1522);
6626 adapter->stats.symerrs += rd32(E1000_SYMERRS);
6627 adapter->stats.sec += rd32(E1000_SEC);
6629 mpc = rd32(E1000_MPC);
6630 adapter->stats.mpc += mpc;
6631 net_stats->rx_fifo_errors += mpc;
6632 adapter->stats.scc += rd32(E1000_SCC);
6633 adapter->stats.ecol += rd32(E1000_ECOL);
6634 adapter->stats.mcc += rd32(E1000_MCC);
6635 adapter->stats.latecol += rd32(E1000_LATECOL);
6636 adapter->stats.dc += rd32(E1000_DC);
6637 adapter->stats.rlec += rd32(E1000_RLEC);
6638 adapter->stats.xonrxc += rd32(E1000_XONRXC);
6639 adapter->stats.xontxc += rd32(E1000_XONTXC);
6640 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
6641 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
6642 adapter->stats.fcruc += rd32(E1000_FCRUC);
6643 adapter->stats.gptc += rd32(E1000_GPTC);
6644 adapter->stats.gotc += rd32(E1000_GOTCL);
6645 rd32(E1000_GOTCH); /* clear GOTCL */
6646 adapter->stats.rnbc += rd32(E1000_RNBC);
6647 adapter->stats.ruc += rd32(E1000_RUC);
6648 adapter->stats.rfc += rd32(E1000_RFC);
6649 adapter->stats.rjc += rd32(E1000_RJC);
6650 adapter->stats.tor += rd32(E1000_TORH);
6651 adapter->stats.tot += rd32(E1000_TOTH);
6652 adapter->stats.tpr += rd32(E1000_TPR);
6654 adapter->stats.ptc64 += rd32(E1000_PTC64);
6655 adapter->stats.ptc127 += rd32(E1000_PTC127);
6656 adapter->stats.ptc255 += rd32(E1000_PTC255);
6657 adapter->stats.ptc511 += rd32(E1000_PTC511);
6658 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
6659 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
6661 adapter->stats.mptc += rd32(E1000_MPTC);
6662 adapter->stats.bptc += rd32(E1000_BPTC);
6664 adapter->stats.tpt += rd32(E1000_TPT);
6665 adapter->stats.colc += rd32(E1000_COLC);
6667 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
6668 /* read internal phy specific stats */
6669 reg = rd32(E1000_CTRL_EXT);
6670 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
6671 adapter->stats.rxerrc += rd32(E1000_RXERRC);
6673 /* this stat has invalid values on i210/i211 */
6674 if ((hw->mac.type != e1000_i210) &&
6675 (hw->mac.type != e1000_i211))
6676 adapter->stats.tncrs += rd32(E1000_TNCRS);
6679 adapter->stats.tsctc += rd32(E1000_TSCTC);
6680 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
6682 adapter->stats.iac += rd32(E1000_IAC);
6683 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
6684 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
6685 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
6686 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
6687 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
6688 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
6689 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
6690 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
6692 /* Fill out the OS statistics structure */
6693 net_stats->multicast = adapter->stats.mprc;
6694 net_stats->collisions = adapter->stats.colc;
6698 /* RLEC on some newer hardware can be incorrect so build
6699 * our own version based on RUC and ROC
6701 net_stats->rx_errors = adapter->stats.rxerrc +
6702 adapter->stats.crcerrs + adapter->stats.algnerrc +
6703 adapter->stats.ruc + adapter->stats.roc +
6704 adapter->stats.cexterr;
6705 net_stats->rx_length_errors = adapter->stats.ruc +
6707 net_stats->rx_crc_errors = adapter->stats.crcerrs;
6708 net_stats->rx_frame_errors = adapter->stats.algnerrc;
6709 net_stats->rx_missed_errors = adapter->stats.mpc;
6712 net_stats->tx_errors = adapter->stats.ecol +
6713 adapter->stats.latecol;
6714 net_stats->tx_aborted_errors = adapter->stats.ecol;
6715 net_stats->tx_window_errors = adapter->stats.latecol;
6716 net_stats->tx_carrier_errors = adapter->stats.tncrs;
6718 /* Tx Dropped needs to be maintained elsewhere */
6720 /* Management Stats */
6721 adapter->stats.mgptc += rd32(E1000_MGTPTC);
6722 adapter->stats.mgprc += rd32(E1000_MGTPRC);
6723 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
6726 reg = rd32(E1000_MANC);
6727 if (reg & E1000_MANC_EN_BMC2OS) {
6728 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
6729 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
6730 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
6731 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
6735 static void igb_tsync_interrupt(struct igb_adapter *adapter)
6737 struct e1000_hw *hw = &adapter->hw;
6738 struct ptp_clock_event event;
6739 struct timespec64 ts;
6740 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
6742 if (tsicr & TSINTR_SYS_WRAP) {
6743 event.type = PTP_CLOCK_PPS;
6744 if (adapter->ptp_caps.pps)
6745 ptp_clock_event(adapter->ptp_clock, &event);
6746 ack |= TSINTR_SYS_WRAP;
6749 if (tsicr & E1000_TSICR_TXTS) {
6750 /* retrieve hardware timestamp */
6751 schedule_work(&adapter->ptp_tx_work);
6752 ack |= E1000_TSICR_TXTS;
6755 if (tsicr & TSINTR_TT0) {
6756 spin_lock(&adapter->tmreg_lock);
6757 ts = timespec64_add(adapter->perout[0].start,
6758 adapter->perout[0].period);
6759 /* u32 conversion of tv_sec is safe until y2106 */
6760 wr32(E1000_TRGTTIML0, ts.tv_nsec);
6761 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
6762 tsauxc = rd32(E1000_TSAUXC);
6763 tsauxc |= TSAUXC_EN_TT0;
6764 wr32(E1000_TSAUXC, tsauxc);
6765 adapter->perout[0].start = ts;
6766 spin_unlock(&adapter->tmreg_lock);
6770 if (tsicr & TSINTR_TT1) {
6771 spin_lock(&adapter->tmreg_lock);
6772 ts = timespec64_add(adapter->perout[1].start,
6773 adapter->perout[1].period);
6774 wr32(E1000_TRGTTIML1, ts.tv_nsec);
6775 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
6776 tsauxc = rd32(E1000_TSAUXC);
6777 tsauxc |= TSAUXC_EN_TT1;
6778 wr32(E1000_TSAUXC, tsauxc);
6779 adapter->perout[1].start = ts;
6780 spin_unlock(&adapter->tmreg_lock);
6784 if (tsicr & TSINTR_AUTT0) {
6785 nsec = rd32(E1000_AUXSTMPL0);
6786 sec = rd32(E1000_AUXSTMPH0);
6787 event.type = PTP_CLOCK_EXTTS;
6789 event.timestamp = sec * 1000000000ULL + nsec;
6790 ptp_clock_event(adapter->ptp_clock, &event);
6791 ack |= TSINTR_AUTT0;
6794 if (tsicr & TSINTR_AUTT1) {
6795 nsec = rd32(E1000_AUXSTMPL1);
6796 sec = rd32(E1000_AUXSTMPH1);
6797 event.type = PTP_CLOCK_EXTTS;
6799 event.timestamp = sec * 1000000000ULL + nsec;
6800 ptp_clock_event(adapter->ptp_clock, &event);
6801 ack |= TSINTR_AUTT1;
6804 /* acknowledge the interrupts */
6805 wr32(E1000_TSICR, ack);
6808 static irqreturn_t igb_msix_other(int irq, void *data)
6810 struct igb_adapter *adapter = data;
6811 struct e1000_hw *hw = &adapter->hw;
6812 u32 icr = rd32(E1000_ICR);
6813 /* reading ICR causes bit 31 of EICR to be cleared */
6815 if (icr & E1000_ICR_DRSTA)
6816 schedule_work(&adapter->reset_task);
6818 if (icr & E1000_ICR_DOUTSYNC) {
6819 /* HW is reporting DMA is out of sync */
6820 adapter->stats.doosync++;
6821 /* The DMA Out of Sync is also indication of a spoof event
6822 * in IOV mode. Check the Wrong VM Behavior register to
6823 * see if it is really a spoof event.
6825 igb_check_wvbr(adapter);
6828 /* Check for a mailbox event */
6829 if (icr & E1000_ICR_VMMB)
6830 igb_msg_task(adapter);
6832 if (icr & E1000_ICR_LSC) {
6833 hw->mac.get_link_status = 1;
6834 /* guard against interrupt when we're going down */
6835 if (!test_bit(__IGB_DOWN, &adapter->state))
6836 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6839 if (icr & E1000_ICR_TS)
6840 igb_tsync_interrupt(adapter);
6842 wr32(E1000_EIMS, adapter->eims_other);
6847 static void igb_write_itr(struct igb_q_vector *q_vector)
6849 struct igb_adapter *adapter = q_vector->adapter;
6850 u32 itr_val = q_vector->itr_val & 0x7FFC;
6852 if (!q_vector->set_itr)
6858 if (adapter->hw.mac.type == e1000_82575)
6859 itr_val |= itr_val << 16;
6861 itr_val |= E1000_EITR_CNT_IGNR;
6863 writel(itr_val, q_vector->itr_register);
6864 q_vector->set_itr = 0;
6867 static irqreturn_t igb_msix_ring(int irq, void *data)
6869 struct igb_q_vector *q_vector = data;
6871 /* Write the ITR value calculated from the previous interrupt. */
6872 igb_write_itr(q_vector);
6874 napi_schedule(&q_vector->napi);
6879 #ifdef CONFIG_IGB_DCA
6880 static void igb_update_tx_dca(struct igb_adapter *adapter,
6881 struct igb_ring *tx_ring,
6884 struct e1000_hw *hw = &adapter->hw;
6885 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
6887 if (hw->mac.type != e1000_82575)
6888 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
6890 /* We can enable relaxed ordering for reads, but not writes when
6891 * DCA is enabled. This is due to a known issue in some chipsets
6892 * which will cause the DCA tag to be cleared.
6894 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
6895 E1000_DCA_TXCTRL_DATA_RRO_EN |
6896 E1000_DCA_TXCTRL_DESC_DCA_EN;
6898 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
6901 static void igb_update_rx_dca(struct igb_adapter *adapter,
6902 struct igb_ring *rx_ring,
6905 struct e1000_hw *hw = &adapter->hw;
6906 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
6908 if (hw->mac.type != e1000_82575)
6909 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
6911 /* We can enable relaxed ordering for reads, but not writes when
6912 * DCA is enabled. This is due to a known issue in some chipsets
6913 * which will cause the DCA tag to be cleared.
6915 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
6916 E1000_DCA_RXCTRL_DESC_DCA_EN;
6918 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
6921 static void igb_update_dca(struct igb_q_vector *q_vector)
6923 struct igb_adapter *adapter = q_vector->adapter;
6924 int cpu = get_cpu();
6926 if (q_vector->cpu == cpu)
6929 if (q_vector->tx.ring)
6930 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
6932 if (q_vector->rx.ring)
6933 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
6935 q_vector->cpu = cpu;
6940 static void igb_setup_dca(struct igb_adapter *adapter)
6942 struct e1000_hw *hw = &adapter->hw;
6945 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
6948 /* Always use CB2 mode, difference is masked in the CB driver. */
6949 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
6951 for (i = 0; i < adapter->num_q_vectors; i++) {
6952 adapter->q_vector[i]->cpu = -1;
6953 igb_update_dca(adapter->q_vector[i]);
6957 static int __igb_notify_dca(struct device *dev, void *data)
6959 struct net_device *netdev = dev_get_drvdata(dev);
6960 struct igb_adapter *adapter = netdev_priv(netdev);
6961 struct pci_dev *pdev = adapter->pdev;
6962 struct e1000_hw *hw = &adapter->hw;
6963 unsigned long event = *(unsigned long *)data;
6966 case DCA_PROVIDER_ADD:
6967 /* if already enabled, don't do it again */
6968 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
6970 if (dca_add_requester(dev) == 0) {
6971 adapter->flags |= IGB_FLAG_DCA_ENABLED;
6972 dev_info(&pdev->dev, "DCA enabled\n");
6973 igb_setup_dca(adapter);
6976 fallthrough; /* since DCA is disabled. */
6977 case DCA_PROVIDER_REMOVE:
6978 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
6979 /* without this a class_device is left
6980 * hanging around in the sysfs model
6982 dca_remove_requester(dev);
6983 dev_info(&pdev->dev, "DCA disabled\n");
6984 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
6985 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
6993 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
6998 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
7001 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7003 #endif /* CONFIG_IGB_DCA */
7005 #ifdef CONFIG_PCI_IOV
7006 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
7008 unsigned char mac_addr[ETH_ALEN];
7010 eth_zero_addr(mac_addr);
7011 igb_set_vf_mac(adapter, vf, mac_addr);
7013 /* By default spoof check is enabled for all VFs */
7014 adapter->vf_data[vf].spoofchk_enabled = true;
7016 /* By default VFs are not trusted */
7017 adapter->vf_data[vf].trusted = false;
7023 static void igb_ping_all_vfs(struct igb_adapter *adapter)
7025 struct e1000_hw *hw = &adapter->hw;
7029 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
7030 ping = E1000_PF_CONTROL_MSG;
7031 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
7032 ping |= E1000_VT_MSGTYPE_CTS;
7033 igb_write_mbx(hw, &ping, 1, i);
7037 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
7039 struct e1000_hw *hw = &adapter->hw;
7040 u32 vmolr = rd32(E1000_VMOLR(vf));
7041 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7043 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7044 IGB_VF_FLAG_MULTI_PROMISC);
7045 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
7047 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
7048 vmolr |= E1000_VMOLR_MPME;
7049 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7050 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
7052 /* if we have hashes and we are clearing a multicast promisc
7053 * flag we need to write the hashes to the MTA as this step
7054 * was previously skipped
7056 if (vf_data->num_vf_mc_hashes > 30) {
7057 vmolr |= E1000_VMOLR_MPME;
7058 } else if (vf_data->num_vf_mc_hashes) {
7061 vmolr |= E1000_VMOLR_ROMPE;
7062 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
7063 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
7067 wr32(E1000_VMOLR(vf), vmolr);
7069 /* there are flags left unprocessed, likely not supported */
7070 if (*msgbuf & E1000_VT_MSGINFO_MASK)
7076 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
7077 u32 *msgbuf, u32 vf)
7079 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
7080 u16 *hash_list = (u16 *)&msgbuf[1];
7081 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7084 /* salt away the number of multicast addresses assigned
7085 * to this VF for later use to restore when the PF multi cast
7088 vf_data->num_vf_mc_hashes = n;
7090 /* only up to 30 hash values supported */
7094 /* store the hashes for later use */
7095 for (i = 0; i < n; i++)
7096 vf_data->vf_mc_hashes[i] = hash_list[i];
7098 /* Flush and reset the mta with the new values */
7099 igb_set_rx_mode(adapter->netdev);
7104 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
7106 struct e1000_hw *hw = &adapter->hw;
7107 struct vf_data_storage *vf_data;
7110 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7111 u32 vmolr = rd32(E1000_VMOLR(i));
7113 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
7115 vf_data = &adapter->vf_data[i];
7117 if ((vf_data->num_vf_mc_hashes > 30) ||
7118 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
7119 vmolr |= E1000_VMOLR_MPME;
7120 } else if (vf_data->num_vf_mc_hashes) {
7121 vmolr |= E1000_VMOLR_ROMPE;
7122 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
7123 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
7125 wr32(E1000_VMOLR(i), vmolr);
7129 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
7131 struct e1000_hw *hw = &adapter->hw;
7132 u32 pool_mask, vlvf_mask, i;
7134 /* create mask for VF and other pools */
7135 pool_mask = E1000_VLVF_POOLSEL_MASK;
7136 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf);
7138 /* drop PF from pool bits */
7139 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT +
7140 adapter->vfs_allocated_count);
7142 /* Find the vlan filter for this id */
7143 for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
7144 u32 vlvf = rd32(E1000_VLVF(i));
7145 u32 vfta_mask, vid, vfta;
7147 /* remove the vf from the pool */
7148 if (!(vlvf & vlvf_mask))
7151 /* clear out bit from VLVF */
7154 /* if other pools are present, just remove ourselves */
7155 if (vlvf & pool_mask)
7158 /* if PF is present, leave VFTA */
7159 if (vlvf & E1000_VLVF_POOLSEL_MASK)
7162 vid = vlvf & E1000_VLVF_VLANID_MASK;
7163 vfta_mask = BIT(vid % 32);
7165 /* clear bit from VFTA */
7166 vfta = adapter->shadow_vfta[vid / 32];
7167 if (vfta & vfta_mask)
7168 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
7170 /* clear pool selection enable */
7171 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
7172 vlvf &= E1000_VLVF_POOLSEL_MASK;
7176 /* clear pool bits */
7177 wr32(E1000_VLVF(i), vlvf);
7181 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
7186 /* short cut the special case */
7190 /* Search for the VLAN id in the VLVF entries */
7191 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
7192 vlvf = rd32(E1000_VLVF(idx));
7193 if ((vlvf & VLAN_VID_MASK) == vlan)
7200 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
7202 struct e1000_hw *hw = &adapter->hw;
7206 idx = igb_find_vlvf_entry(hw, vid);
7210 /* See if any other pools are set for this VLAN filter
7211 * entry other than the PF.
7213 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
7214 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK;
7215 bits &= rd32(E1000_VLVF(idx));
7217 /* Disable the filter so this falls into the default pool. */
7219 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
7220 wr32(E1000_VLVF(idx), BIT(pf_id));
7222 wr32(E1000_VLVF(idx), 0);
7226 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
7229 int pf_id = adapter->vfs_allocated_count;
7230 struct e1000_hw *hw = &adapter->hw;
7233 /* If VLAN overlaps with one the PF is currently monitoring make
7234 * sure that we are able to allocate a VLVF entry. This may be
7235 * redundant but it guarantees PF will maintain visibility to
7238 if (add && test_bit(vid, adapter->active_vlans)) {
7239 err = igb_vfta_set(hw, vid, pf_id, true, false);
7244 err = igb_vfta_set(hw, vid, vf, add, false);
7249 /* If we failed to add the VF VLAN or we are removing the VF VLAN
7250 * we may need to drop the PF pool bit in order to allow us to free
7251 * up the VLVF resources.
7253 if (test_bit(vid, adapter->active_vlans) ||
7254 (adapter->flags & IGB_FLAG_VLAN_PROMISC))
7255 igb_update_pf_vlvf(adapter, vid);
7260 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
7262 struct e1000_hw *hw = &adapter->hw;
7265 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
7267 wr32(E1000_VMVIR(vf), 0);
7270 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
7275 err = igb_set_vf_vlan(adapter, vlan, true, vf);
7279 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
7280 igb_set_vmolr(adapter, vf, !vlan);
7282 /* revoke access to previous VLAN */
7283 if (vlan != adapter->vf_data[vf].pf_vlan)
7284 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
7287 adapter->vf_data[vf].pf_vlan = vlan;
7288 adapter->vf_data[vf].pf_qos = qos;
7289 igb_set_vf_vlan_strip(adapter, vf, true);
7290 dev_info(&adapter->pdev->dev,
7291 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
7292 if (test_bit(__IGB_DOWN, &adapter->state)) {
7293 dev_warn(&adapter->pdev->dev,
7294 "The VF VLAN has been set, but the PF device is not up.\n");
7295 dev_warn(&adapter->pdev->dev,
7296 "Bring the PF device up before attempting to use the VF device.\n");
7302 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
7304 /* Restore tagless access via VLAN 0 */
7305 igb_set_vf_vlan(adapter, 0, true, vf);
7307 igb_set_vmvir(adapter, 0, vf);
7308 igb_set_vmolr(adapter, vf, true);
7310 /* Remove any PF assigned VLAN */
7311 if (adapter->vf_data[vf].pf_vlan)
7312 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
7315 adapter->vf_data[vf].pf_vlan = 0;
7316 adapter->vf_data[vf].pf_qos = 0;
7317 igb_set_vf_vlan_strip(adapter, vf, false);
7322 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf,
7323 u16 vlan, u8 qos, __be16 vlan_proto)
7325 struct igb_adapter *adapter = netdev_priv(netdev);
7327 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
7330 if (vlan_proto != htons(ETH_P_8021Q))
7331 return -EPROTONOSUPPORT;
7333 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
7334 igb_disable_port_vlan(adapter, vf);
7337 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
7339 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
7340 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
7343 if (adapter->vf_data[vf].pf_vlan)
7346 /* VLAN 0 is a special case, don't allow it to be removed */
7350 ret = igb_set_vf_vlan(adapter, vid, !!add, vf);
7352 igb_set_vf_vlan_strip(adapter, vf, !!vid);
7356 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
7358 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7360 /* clear flags - except flag that indicates PF has set the MAC */
7361 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
7362 vf_data->last_nack = jiffies;
7364 /* reset vlans for device */
7365 igb_clear_vf_vfta(adapter, vf);
7366 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
7367 igb_set_vmvir(adapter, vf_data->pf_vlan |
7368 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
7369 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
7370 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan));
7372 /* reset multicast table array for vf */
7373 adapter->vf_data[vf].num_vf_mc_hashes = 0;
7375 /* Flush and reset the mta with the new values */
7376 igb_set_rx_mode(adapter->netdev);
7379 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
7381 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
7383 /* clear mac address as we were hotplug removed/added */
7384 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
7385 eth_zero_addr(vf_mac);
7387 /* process remaining reset events */
7388 igb_vf_reset(adapter, vf);
7391 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
7393 struct e1000_hw *hw = &adapter->hw;
7394 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
7396 u8 *addr = (u8 *)(&msgbuf[1]);
7398 /* process all the same items cleared in a function level reset */
7399 igb_vf_reset(adapter, vf);
7401 /* set vf mac address */
7402 igb_set_vf_mac(adapter, vf, vf_mac);
7404 /* enable transmit and receive for vf */
7405 reg = rd32(E1000_VFTE);
7406 wr32(E1000_VFTE, reg | BIT(vf));
7407 reg = rd32(E1000_VFRE);
7408 wr32(E1000_VFRE, reg | BIT(vf));
7410 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
7412 /* reply to reset with ack and vf mac address */
7413 if (!is_zero_ether_addr(vf_mac)) {
7414 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
7415 memcpy(addr, vf_mac, ETH_ALEN);
7417 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
7419 igb_write_mbx(hw, msgbuf, 3, vf);
7422 static void igb_flush_mac_table(struct igb_adapter *adapter)
7424 struct e1000_hw *hw = &adapter->hw;
7427 for (i = 0; i < hw->mac.rar_entry_count; i++) {
7428 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE;
7429 eth_zero_addr(adapter->mac_table[i].addr);
7430 adapter->mac_table[i].queue = 0;
7431 igb_rar_set_index(adapter, i);
7435 static int igb_available_rars(struct igb_adapter *adapter, u8 queue)
7437 struct e1000_hw *hw = &adapter->hw;
7438 /* do not count rar entries reserved for VFs MAC addresses */
7439 int rar_entries = hw->mac.rar_entry_count -
7440 adapter->vfs_allocated_count;
7443 for (i = 0; i < rar_entries; i++) {
7444 /* do not count default entries */
7445 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT)
7448 /* do not count "in use" entries for different queues */
7449 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) &&
7450 (adapter->mac_table[i].queue != queue))
7459 /* Set default MAC address for the PF in the first RAR entry */
7460 static void igb_set_default_mac_filter(struct igb_adapter *adapter)
7462 struct igb_mac_addr *mac_table = &adapter->mac_table[0];
7464 ether_addr_copy(mac_table->addr, adapter->hw.mac.addr);
7465 mac_table->queue = adapter->vfs_allocated_count;
7466 mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
7468 igb_rar_set_index(adapter, 0);
7471 /* If the filter to be added and an already existing filter express
7472 * the same address and address type, it should be possible to only
7473 * override the other configurations, for example the queue to steer
7476 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry,
7477 const u8 *addr, const u8 flags)
7479 if (!(entry->state & IGB_MAC_STATE_IN_USE))
7482 if ((entry->state & IGB_MAC_STATE_SRC_ADDR) !=
7483 (flags & IGB_MAC_STATE_SRC_ADDR))
7486 if (!ether_addr_equal(addr, entry->addr))
7492 /* Add a MAC filter for 'addr' directing matching traffic to 'queue',
7493 * 'flags' is used to indicate what kind of match is made, match is by
7494 * default for the destination address, if matching by source address
7495 * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used.
7497 static int igb_add_mac_filter_flags(struct igb_adapter *adapter,
7498 const u8 *addr, const u8 queue,
7501 struct e1000_hw *hw = &adapter->hw;
7502 int rar_entries = hw->mac.rar_entry_count -
7503 adapter->vfs_allocated_count;
7506 if (is_zero_ether_addr(addr))
7509 /* Search for the first empty entry in the MAC table.
7510 * Do not touch entries at the end of the table reserved for the VF MAC
7513 for (i = 0; i < rar_entries; i++) {
7514 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i],
7518 ether_addr_copy(adapter->mac_table[i].addr, addr);
7519 adapter->mac_table[i].queue = queue;
7520 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags;
7522 igb_rar_set_index(adapter, i);
7529 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr,
7532 return igb_add_mac_filter_flags(adapter, addr, queue, 0);
7535 /* Remove a MAC filter for 'addr' directing matching traffic to
7536 * 'queue', 'flags' is used to indicate what kind of match need to be
7537 * removed, match is by default for the destination address, if
7538 * matching by source address is to be removed the flag
7539 * IGB_MAC_STATE_SRC_ADDR can be used.
7541 static int igb_del_mac_filter_flags(struct igb_adapter *adapter,
7542 const u8 *addr, const u8 queue,
7545 struct e1000_hw *hw = &adapter->hw;
7546 int rar_entries = hw->mac.rar_entry_count -
7547 adapter->vfs_allocated_count;
7550 if (is_zero_ether_addr(addr))
7553 /* Search for matching entry in the MAC table based on given address
7554 * and queue. Do not touch entries at the end of the table reserved
7555 * for the VF MAC addresses.
7557 for (i = 0; i < rar_entries; i++) {
7558 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE))
7560 if ((adapter->mac_table[i].state & flags) != flags)
7562 if (adapter->mac_table[i].queue != queue)
7564 if (!ether_addr_equal(adapter->mac_table[i].addr, addr))
7567 /* When a filter for the default address is "deleted",
7568 * we return it to its initial configuration
7570 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) {
7571 adapter->mac_table[i].state =
7572 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
7573 adapter->mac_table[i].queue =
7574 adapter->vfs_allocated_count;
7576 adapter->mac_table[i].state = 0;
7577 adapter->mac_table[i].queue = 0;
7578 eth_zero_addr(adapter->mac_table[i].addr);
7581 igb_rar_set_index(adapter, i);
7588 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr,
7591 return igb_del_mac_filter_flags(adapter, addr, queue, 0);
7594 int igb_add_mac_steering_filter(struct igb_adapter *adapter,
7595 const u8 *addr, u8 queue, u8 flags)
7597 struct e1000_hw *hw = &adapter->hw;
7599 /* In theory, this should be supported on 82575 as well, but
7600 * that part wasn't easily accessible during development.
7602 if (hw->mac.type != e1000_i210)
7605 return igb_add_mac_filter_flags(adapter, addr, queue,
7606 IGB_MAC_STATE_QUEUE_STEERING | flags);
7609 int igb_del_mac_steering_filter(struct igb_adapter *adapter,
7610 const u8 *addr, u8 queue, u8 flags)
7612 return igb_del_mac_filter_flags(adapter, addr, queue,
7613 IGB_MAC_STATE_QUEUE_STEERING | flags);
7616 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr)
7618 struct igb_adapter *adapter = netdev_priv(netdev);
7621 ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count);
7623 return min_t(int, ret, 0);
7626 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr)
7628 struct igb_adapter *adapter = netdev_priv(netdev);
7630 igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count);
7635 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf,
7636 const u32 info, const u8 *addr)
7638 struct pci_dev *pdev = adapter->pdev;
7639 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7640 struct list_head *pos;
7641 struct vf_mac_filter *entry = NULL;
7645 case E1000_VF_MAC_FILTER_CLR:
7646 /* remove all unicast MAC filters related to the current VF */
7647 list_for_each(pos, &adapter->vf_macs.l) {
7648 entry = list_entry(pos, struct vf_mac_filter, l);
7649 if (entry->vf == vf) {
7652 igb_del_mac_filter(adapter, entry->vf_mac, vf);
7656 case E1000_VF_MAC_FILTER_ADD:
7657 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7658 !vf_data->trusted) {
7659 dev_warn(&pdev->dev,
7660 "VF %d requested MAC filter but is administratively denied\n",
7664 if (!is_valid_ether_addr(addr)) {
7665 dev_warn(&pdev->dev,
7666 "VF %d attempted to set invalid MAC filter\n",
7671 /* try to find empty slot in the list */
7672 list_for_each(pos, &adapter->vf_macs.l) {
7673 entry = list_entry(pos, struct vf_mac_filter, l);
7678 if (entry && entry->free) {
7679 entry->free = false;
7681 ether_addr_copy(entry->vf_mac, addr);
7683 ret = igb_add_mac_filter(adapter, addr, vf);
7684 ret = min_t(int, ret, 0);
7690 dev_warn(&pdev->dev,
7691 "VF %d has requested MAC filter but there is no space for it\n",
7702 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
7704 struct pci_dev *pdev = adapter->pdev;
7705 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7706 u32 info = msg[0] & E1000_VT_MSGINFO_MASK;
7708 /* The VF MAC Address is stored in a packed array of bytes
7709 * starting at the second 32 bit word of the msg array
7711 unsigned char *addr = (unsigned char *)&msg[1];
7715 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7716 !vf_data->trusted) {
7717 dev_warn(&pdev->dev,
7718 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
7723 if (!is_valid_ether_addr(addr)) {
7724 dev_warn(&pdev->dev,
7725 "VF %d attempted to set invalid MAC\n",
7730 ret = igb_set_vf_mac(adapter, vf, addr);
7732 ret = igb_set_vf_mac_filter(adapter, vf, info, addr);
7738 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
7740 struct e1000_hw *hw = &adapter->hw;
7741 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7742 u32 msg = E1000_VT_MSGTYPE_NACK;
7744 /* if device isn't clear to send it shouldn't be reading either */
7745 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
7746 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
7747 igb_write_mbx(hw, &msg, 1, vf);
7748 vf_data->last_nack = jiffies;
7752 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
7754 struct pci_dev *pdev = adapter->pdev;
7755 u32 msgbuf[E1000_VFMAILBOX_SIZE];
7756 struct e1000_hw *hw = &adapter->hw;
7757 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7760 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false);
7763 /* if receive failed revoke VF CTS stats and restart init */
7764 dev_err(&pdev->dev, "Error receiving message from VF\n");
7765 vf_data->flags &= ~IGB_VF_FLAG_CTS;
7766 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7771 /* this is a message we already processed, do nothing */
7772 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
7775 /* until the vf completes a reset it should not be
7776 * allowed to start any configuration.
7778 if (msgbuf[0] == E1000_VF_RESET) {
7779 /* unlocks mailbox */
7780 igb_vf_reset_msg(adapter, vf);
7784 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
7785 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7791 switch ((msgbuf[0] & 0xFFFF)) {
7792 case E1000_VF_SET_MAC_ADDR:
7793 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
7795 case E1000_VF_SET_PROMISC:
7796 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
7798 case E1000_VF_SET_MULTICAST:
7799 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
7801 case E1000_VF_SET_LPE:
7802 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
7804 case E1000_VF_SET_VLAN:
7806 if (vf_data->pf_vlan)
7807 dev_warn(&pdev->dev,
7808 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
7811 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
7814 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
7819 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
7821 /* notify the VF of the results of what it sent us */
7823 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
7825 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
7827 /* unlocks mailbox */
7828 igb_write_mbx(hw, msgbuf, 1, vf);
7832 igb_unlock_mbx(hw, vf);
7835 static void igb_msg_task(struct igb_adapter *adapter)
7837 struct e1000_hw *hw = &adapter->hw;
7840 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
7841 /* process any reset requests */
7842 if (!igb_check_for_rst(hw, vf))
7843 igb_vf_reset_event(adapter, vf);
7845 /* process any messages pending */
7846 if (!igb_check_for_msg(hw, vf))
7847 igb_rcv_msg_from_vf(adapter, vf);
7849 /* process any acks */
7850 if (!igb_check_for_ack(hw, vf))
7851 igb_rcv_ack_from_vf(adapter, vf);
7856 * igb_set_uta - Set unicast filter table address
7857 * @adapter: board private structure
7858 * @set: boolean indicating if we are setting or clearing bits
7860 * The unicast table address is a register array of 32-bit registers.
7861 * The table is meant to be used in a way similar to how the MTA is used
7862 * however due to certain limitations in the hardware it is necessary to
7863 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
7864 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
7866 static void igb_set_uta(struct igb_adapter *adapter, bool set)
7868 struct e1000_hw *hw = &adapter->hw;
7869 u32 uta = set ? ~0 : 0;
7872 /* we only need to do this if VMDq is enabled */
7873 if (!adapter->vfs_allocated_count)
7876 for (i = hw->mac.uta_reg_count; i--;)
7877 array_wr32(E1000_UTA, i, uta);
7881 * igb_intr_msi - Interrupt Handler
7882 * @irq: interrupt number
7883 * @data: pointer to a network interface device structure
7885 static irqreturn_t igb_intr_msi(int irq, void *data)
7887 struct igb_adapter *adapter = data;
7888 struct igb_q_vector *q_vector = adapter->q_vector[0];
7889 struct e1000_hw *hw = &adapter->hw;
7890 /* read ICR disables interrupts using IAM */
7891 u32 icr = rd32(E1000_ICR);
7893 igb_write_itr(q_vector);
7895 if (icr & E1000_ICR_DRSTA)
7896 schedule_work(&adapter->reset_task);
7898 if (icr & E1000_ICR_DOUTSYNC) {
7899 /* HW is reporting DMA is out of sync */
7900 adapter->stats.doosync++;
7903 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
7904 hw->mac.get_link_status = 1;
7905 if (!test_bit(__IGB_DOWN, &adapter->state))
7906 mod_timer(&adapter->watchdog_timer, jiffies + 1);
7909 if (icr & E1000_ICR_TS)
7910 igb_tsync_interrupt(adapter);
7912 napi_schedule(&q_vector->napi);
7918 * igb_intr - Legacy Interrupt Handler
7919 * @irq: interrupt number
7920 * @data: pointer to a network interface device structure
7922 static irqreturn_t igb_intr(int irq, void *data)
7924 struct igb_adapter *adapter = data;
7925 struct igb_q_vector *q_vector = adapter->q_vector[0];
7926 struct e1000_hw *hw = &adapter->hw;
7927 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
7928 * need for the IMC write
7930 u32 icr = rd32(E1000_ICR);
7932 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
7933 * not set, then the adapter didn't send an interrupt
7935 if (!(icr & E1000_ICR_INT_ASSERTED))
7938 igb_write_itr(q_vector);
7940 if (icr & E1000_ICR_DRSTA)
7941 schedule_work(&adapter->reset_task);
7943 if (icr & E1000_ICR_DOUTSYNC) {
7944 /* HW is reporting DMA is out of sync */
7945 adapter->stats.doosync++;
7948 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
7949 hw->mac.get_link_status = 1;
7950 /* guard against interrupt when we're going down */
7951 if (!test_bit(__IGB_DOWN, &adapter->state))
7952 mod_timer(&adapter->watchdog_timer, jiffies + 1);
7955 if (icr & E1000_ICR_TS)
7956 igb_tsync_interrupt(adapter);
7958 napi_schedule(&q_vector->napi);
7963 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
7965 struct igb_adapter *adapter = q_vector->adapter;
7966 struct e1000_hw *hw = &adapter->hw;
7968 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
7969 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
7970 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
7971 igb_set_itr(q_vector);
7973 igb_update_ring_itr(q_vector);
7976 if (!test_bit(__IGB_DOWN, &adapter->state)) {
7977 if (adapter->flags & IGB_FLAG_HAS_MSIX)
7978 wr32(E1000_EIMS, q_vector->eims_value);
7980 igb_irq_enable(adapter);
7985 * igb_poll - NAPI Rx polling callback
7986 * @napi: napi polling structure
7987 * @budget: count of how many packets we should handle
7989 static int igb_poll(struct napi_struct *napi, int budget)
7991 struct igb_q_vector *q_vector = container_of(napi,
7992 struct igb_q_vector,
7994 bool clean_complete = true;
7997 #ifdef CONFIG_IGB_DCA
7998 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
7999 igb_update_dca(q_vector);
8001 if (q_vector->tx.ring)
8002 clean_complete = igb_clean_tx_irq(q_vector, budget);
8004 if (q_vector->rx.ring) {
8005 int cleaned = igb_clean_rx_irq(q_vector, budget);
8007 work_done += cleaned;
8008 if (cleaned >= budget)
8009 clean_complete = false;
8012 /* If all work not completed, return budget and keep polling */
8013 if (!clean_complete)
8016 /* Exit the polling mode, but don't re-enable interrupts if stack might
8017 * poll us due to busy-polling
8019 if (likely(napi_complete_done(napi, work_done)))
8020 igb_ring_irq_enable(q_vector);
8022 return min(work_done, budget - 1);
8026 * igb_clean_tx_irq - Reclaim resources after transmit completes
8027 * @q_vector: pointer to q_vector containing needed info
8028 * @napi_budget: Used to determine if we are in netpoll
8030 * returns true if ring is completely cleaned
8032 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget)
8034 struct igb_adapter *adapter = q_vector->adapter;
8035 struct igb_ring *tx_ring = q_vector->tx.ring;
8036 struct igb_tx_buffer *tx_buffer;
8037 union e1000_adv_tx_desc *tx_desc;
8038 unsigned int total_bytes = 0, total_packets = 0;
8039 unsigned int budget = q_vector->tx.work_limit;
8040 unsigned int i = tx_ring->next_to_clean;
8042 if (test_bit(__IGB_DOWN, &adapter->state))
8045 tx_buffer = &tx_ring->tx_buffer_info[i];
8046 tx_desc = IGB_TX_DESC(tx_ring, i);
8047 i -= tx_ring->count;
8050 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8052 /* if next_to_watch is not set then there is no work pending */
8056 /* prevent any other reads prior to eop_desc */
8059 /* if DD is not set pending work has not been completed */
8060 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
8063 /* clear next_to_watch to prevent false hangs */
8064 tx_buffer->next_to_watch = NULL;
8066 /* update the statistics for this packet */
8067 total_bytes += tx_buffer->bytecount;
8068 total_packets += tx_buffer->gso_segs;
8071 if (tx_buffer->type == IGB_TYPE_SKB)
8072 napi_consume_skb(tx_buffer->skb, napi_budget);
8074 xdp_return_frame(tx_buffer->xdpf);
8076 /* unmap skb header data */
8077 dma_unmap_single(tx_ring->dev,
8078 dma_unmap_addr(tx_buffer, dma),
8079 dma_unmap_len(tx_buffer, len),
8082 /* clear tx_buffer data */
8083 dma_unmap_len_set(tx_buffer, len, 0);
8085 /* clear last DMA location and unmap remaining buffers */
8086 while (tx_desc != eop_desc) {
8091 i -= tx_ring->count;
8092 tx_buffer = tx_ring->tx_buffer_info;
8093 tx_desc = IGB_TX_DESC(tx_ring, 0);
8096 /* unmap any remaining paged data */
8097 if (dma_unmap_len(tx_buffer, len)) {
8098 dma_unmap_page(tx_ring->dev,
8099 dma_unmap_addr(tx_buffer, dma),
8100 dma_unmap_len(tx_buffer, len),
8102 dma_unmap_len_set(tx_buffer, len, 0);
8106 /* move us one more past the eop_desc for start of next pkt */
8111 i -= tx_ring->count;
8112 tx_buffer = tx_ring->tx_buffer_info;
8113 tx_desc = IGB_TX_DESC(tx_ring, 0);
8116 /* issue prefetch for next Tx descriptor */
8119 /* update budget accounting */
8121 } while (likely(budget));
8123 netdev_tx_completed_queue(txring_txq(tx_ring),
8124 total_packets, total_bytes);
8125 i += tx_ring->count;
8126 tx_ring->next_to_clean = i;
8127 u64_stats_update_begin(&tx_ring->tx_syncp);
8128 tx_ring->tx_stats.bytes += total_bytes;
8129 tx_ring->tx_stats.packets += total_packets;
8130 u64_stats_update_end(&tx_ring->tx_syncp);
8131 q_vector->tx.total_bytes += total_bytes;
8132 q_vector->tx.total_packets += total_packets;
8134 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
8135 struct e1000_hw *hw = &adapter->hw;
8137 /* Detect a transmit hang in hardware, this serializes the
8138 * check with the clearing of time_stamp and movement of i
8140 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
8141 if (tx_buffer->next_to_watch &&
8142 time_after(jiffies, tx_buffer->time_stamp +
8143 (adapter->tx_timeout_factor * HZ)) &&
8144 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
8146 /* detected Tx unit hang */
8147 dev_err(tx_ring->dev,
8148 "Detected Tx Unit Hang\n"
8152 " next_to_use <%x>\n"
8153 " next_to_clean <%x>\n"
8154 "buffer_info[next_to_clean]\n"
8155 " time_stamp <%lx>\n"
8156 " next_to_watch <%p>\n"
8158 " desc.status <%x>\n",
8159 tx_ring->queue_index,
8160 rd32(E1000_TDH(tx_ring->reg_idx)),
8161 readl(tx_ring->tail),
8162 tx_ring->next_to_use,
8163 tx_ring->next_to_clean,
8164 tx_buffer->time_stamp,
8165 tx_buffer->next_to_watch,
8167 tx_buffer->next_to_watch->wb.status);
8168 netif_stop_subqueue(tx_ring->netdev,
8169 tx_ring->queue_index);
8171 /* we are about to reset, no point in enabling stuff */
8176 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
8177 if (unlikely(total_packets &&
8178 netif_carrier_ok(tx_ring->netdev) &&
8179 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
8180 /* Make sure that anybody stopping the queue after this
8181 * sees the new next_to_clean.
8184 if (__netif_subqueue_stopped(tx_ring->netdev,
8185 tx_ring->queue_index) &&
8186 !(test_bit(__IGB_DOWN, &adapter->state))) {
8187 netif_wake_subqueue(tx_ring->netdev,
8188 tx_ring->queue_index);
8190 u64_stats_update_begin(&tx_ring->tx_syncp);
8191 tx_ring->tx_stats.restart_queue++;
8192 u64_stats_update_end(&tx_ring->tx_syncp);
8200 * igb_reuse_rx_page - page flip buffer and store it back on the ring
8201 * @rx_ring: rx descriptor ring to store buffers on
8202 * @old_buff: donor buffer to have page reused
8204 * Synchronizes page for reuse by the adapter
8206 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
8207 struct igb_rx_buffer *old_buff)
8209 struct igb_rx_buffer *new_buff;
8210 u16 nta = rx_ring->next_to_alloc;
8212 new_buff = &rx_ring->rx_buffer_info[nta];
8214 /* update, and store next to alloc */
8216 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
8218 /* Transfer page from old buffer to new buffer.
8219 * Move each member individually to avoid possible store
8220 * forwarding stalls.
8222 new_buff->dma = old_buff->dma;
8223 new_buff->page = old_buff->page;
8224 new_buff->page_offset = old_buff->page_offset;
8225 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
8228 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
8231 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
8232 struct page *page = rx_buffer->page;
8234 /* avoid re-using remote and pfmemalloc pages */
8235 if (!dev_page_is_reusable(page))
8238 #if (PAGE_SIZE < 8192)
8239 /* if we are only owner of page we can reuse it */
8240 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1))
8243 #define IGB_LAST_OFFSET \
8244 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048)
8246 if (rx_buffer->page_offset > IGB_LAST_OFFSET)
8250 /* If we have drained the page fragment pool we need to update
8251 * the pagecnt_bias and page count so that we fully restock the
8252 * number of references the driver holds.
8254 if (unlikely(pagecnt_bias == 1)) {
8255 page_ref_add(page, USHRT_MAX - 1);
8256 rx_buffer->pagecnt_bias = USHRT_MAX;
8263 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
8264 * @rx_ring: rx descriptor ring to transact packets on
8265 * @rx_buffer: buffer containing page to add
8266 * @skb: sk_buff to place the data into
8267 * @size: size of buffer to be added
8269 * This function will add the data contained in rx_buffer->page to the skb.
8271 static void igb_add_rx_frag(struct igb_ring *rx_ring,
8272 struct igb_rx_buffer *rx_buffer,
8273 struct sk_buff *skb,
8276 #if (PAGE_SIZE < 8192)
8277 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8279 unsigned int truesize = ring_uses_build_skb(rx_ring) ?
8280 SKB_DATA_ALIGN(IGB_SKB_PAD + size) :
8281 SKB_DATA_ALIGN(size);
8283 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
8284 rx_buffer->page_offset, size, truesize);
8285 #if (PAGE_SIZE < 8192)
8286 rx_buffer->page_offset ^= truesize;
8288 rx_buffer->page_offset += truesize;
8292 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring,
8293 struct igb_rx_buffer *rx_buffer,
8294 struct xdp_buff *xdp,
8297 #if (PAGE_SIZE < 8192)
8298 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8300 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end -
8301 xdp->data_hard_start);
8303 unsigned int size = xdp->data_end - xdp->data;
8304 unsigned int headlen;
8305 struct sk_buff *skb;
8307 /* prefetch first cache line of first page */
8308 net_prefetch(xdp->data);
8310 /* allocate a skb to store the frags */
8311 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
8316 skb_hwtstamps(skb)->hwtstamp = timestamp;
8318 /* Determine available headroom for copy */
8320 if (headlen > IGB_RX_HDR_LEN)
8321 headlen = eth_get_headlen(skb->dev, xdp->data, IGB_RX_HDR_LEN);
8323 /* align pull length to size of long to optimize memcpy performance */
8324 memcpy(__skb_put(skb, headlen), xdp->data, ALIGN(headlen, sizeof(long)));
8326 /* update all of the pointers */
8329 skb_add_rx_frag(skb, 0, rx_buffer->page,
8330 (xdp->data + headlen) - page_address(rx_buffer->page),
8332 #if (PAGE_SIZE < 8192)
8333 rx_buffer->page_offset ^= truesize;
8335 rx_buffer->page_offset += truesize;
8338 rx_buffer->pagecnt_bias++;
8344 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring,
8345 struct igb_rx_buffer *rx_buffer,
8346 struct xdp_buff *xdp,
8349 #if (PAGE_SIZE < 8192)
8350 unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8352 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
8353 SKB_DATA_ALIGN(xdp->data_end -
8354 xdp->data_hard_start);
8356 unsigned int metasize = xdp->data - xdp->data_meta;
8357 struct sk_buff *skb;
8359 /* prefetch first cache line of first page */
8360 net_prefetch(xdp->data_meta);
8362 /* build an skb around the page buffer */
8363 skb = build_skb(xdp->data_hard_start, truesize);
8367 /* update pointers within the skb to store the data */
8368 skb_reserve(skb, xdp->data - xdp->data_hard_start);
8369 __skb_put(skb, xdp->data_end - xdp->data);
8372 skb_metadata_set(skb, metasize);
8375 skb_hwtstamps(skb)->hwtstamp = timestamp;
8377 /* update buffer offset */
8378 #if (PAGE_SIZE < 8192)
8379 rx_buffer->page_offset ^= truesize;
8381 rx_buffer->page_offset += truesize;
8387 static struct sk_buff *igb_run_xdp(struct igb_adapter *adapter,
8388 struct igb_ring *rx_ring,
8389 struct xdp_buff *xdp)
8391 int err, result = IGB_XDP_PASS;
8392 struct bpf_prog *xdp_prog;
8395 xdp_prog = READ_ONCE(rx_ring->xdp_prog);
8400 prefetchw(xdp->data_hard_start); /* xdp_frame write */
8402 act = bpf_prog_run_xdp(xdp_prog, xdp);
8407 result = igb_xdp_xmit_back(adapter, xdp);
8408 if (result == IGB_XDP_CONSUMED)
8412 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog);
8415 result = IGB_XDP_REDIR;
8418 bpf_warn_invalid_xdp_action(act);
8422 trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
8425 result = IGB_XDP_CONSUMED;
8429 return ERR_PTR(-result);
8432 static unsigned int igb_rx_frame_truesize(struct igb_ring *rx_ring,
8435 unsigned int truesize;
8437 #if (PAGE_SIZE < 8192)
8438 truesize = igb_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */
8440 truesize = ring_uses_build_skb(rx_ring) ?
8441 SKB_DATA_ALIGN(IGB_SKB_PAD + size) +
8442 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
8443 SKB_DATA_ALIGN(size);
8448 static void igb_rx_buffer_flip(struct igb_ring *rx_ring,
8449 struct igb_rx_buffer *rx_buffer,
8452 unsigned int truesize = igb_rx_frame_truesize(rx_ring, size);
8453 #if (PAGE_SIZE < 8192)
8454 rx_buffer->page_offset ^= truesize;
8456 rx_buffer->page_offset += truesize;
8460 static inline void igb_rx_checksum(struct igb_ring *ring,
8461 union e1000_adv_rx_desc *rx_desc,
8462 struct sk_buff *skb)
8464 skb_checksum_none_assert(skb);
8466 /* Ignore Checksum bit is set */
8467 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
8470 /* Rx checksum disabled via ethtool */
8471 if (!(ring->netdev->features & NETIF_F_RXCSUM))
8474 /* TCP/UDP checksum error bit is set */
8475 if (igb_test_staterr(rx_desc,
8476 E1000_RXDEXT_STATERR_TCPE |
8477 E1000_RXDEXT_STATERR_IPE)) {
8478 /* work around errata with sctp packets where the TCPE aka
8479 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
8480 * packets, (aka let the stack check the crc32c)
8482 if (!((skb->len == 60) &&
8483 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
8484 u64_stats_update_begin(&ring->rx_syncp);
8485 ring->rx_stats.csum_err++;
8486 u64_stats_update_end(&ring->rx_syncp);
8488 /* let the stack verify checksum errors */
8491 /* It must be a TCP or UDP packet with a valid checksum */
8492 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
8493 E1000_RXD_STAT_UDPCS))
8494 skb->ip_summed = CHECKSUM_UNNECESSARY;
8496 dev_dbg(ring->dev, "cksum success: bits %08X\n",
8497 le32_to_cpu(rx_desc->wb.upper.status_error));
8500 static inline void igb_rx_hash(struct igb_ring *ring,
8501 union e1000_adv_rx_desc *rx_desc,
8502 struct sk_buff *skb)
8504 if (ring->netdev->features & NETIF_F_RXHASH)
8506 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
8511 * igb_is_non_eop - process handling of non-EOP buffers
8512 * @rx_ring: Rx ring being processed
8513 * @rx_desc: Rx descriptor for current buffer
8515 * This function updates next to clean. If the buffer is an EOP buffer
8516 * this function exits returning false, otherwise it will place the
8517 * sk_buff in the next buffer to be chained and return true indicating
8518 * that this is in fact a non-EOP buffer.
8520 static bool igb_is_non_eop(struct igb_ring *rx_ring,
8521 union e1000_adv_rx_desc *rx_desc)
8523 u32 ntc = rx_ring->next_to_clean + 1;
8525 /* fetch, update, and store next to clean */
8526 ntc = (ntc < rx_ring->count) ? ntc : 0;
8527 rx_ring->next_to_clean = ntc;
8529 prefetch(IGB_RX_DESC(rx_ring, ntc));
8531 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
8538 * igb_cleanup_headers - Correct corrupted or empty headers
8539 * @rx_ring: rx descriptor ring packet is being transacted on
8540 * @rx_desc: pointer to the EOP Rx descriptor
8541 * @skb: pointer to current skb being fixed
8543 * Address the case where we are pulling data in on pages only
8544 * and as such no data is present in the skb header.
8546 * In addition if skb is not at least 60 bytes we need to pad it so that
8547 * it is large enough to qualify as a valid Ethernet frame.
8549 * Returns true if an error was encountered and skb was freed.
8551 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
8552 union e1000_adv_rx_desc *rx_desc,
8553 struct sk_buff *skb)
8555 /* XDP packets use error pointer so abort at this point */
8559 if (unlikely((igb_test_staterr(rx_desc,
8560 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
8561 struct net_device *netdev = rx_ring->netdev;
8562 if (!(netdev->features & NETIF_F_RXALL)) {
8563 dev_kfree_skb_any(skb);
8568 /* if eth_skb_pad returns an error the skb was freed */
8569 if (eth_skb_pad(skb))
8576 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
8577 * @rx_ring: rx descriptor ring packet is being transacted on
8578 * @rx_desc: pointer to the EOP Rx descriptor
8579 * @skb: pointer to current skb being populated
8581 * This function checks the ring, descriptor, and packet information in
8582 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
8583 * other fields within the skb.
8585 static void igb_process_skb_fields(struct igb_ring *rx_ring,
8586 union e1000_adv_rx_desc *rx_desc,
8587 struct sk_buff *skb)
8589 struct net_device *dev = rx_ring->netdev;
8591 igb_rx_hash(rx_ring, rx_desc, skb);
8593 igb_rx_checksum(rx_ring, rx_desc, skb);
8595 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
8596 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
8597 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
8599 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
8600 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
8603 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
8604 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
8605 vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan);
8607 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
8609 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
8612 skb_record_rx_queue(skb, rx_ring->queue_index);
8614 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
8617 static unsigned int igb_rx_offset(struct igb_ring *rx_ring)
8619 return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0;
8622 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring,
8623 const unsigned int size, int *rx_buf_pgcnt)
8625 struct igb_rx_buffer *rx_buffer;
8627 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
8629 #if (PAGE_SIZE < 8192)
8630 page_count(rx_buffer->page);
8634 prefetchw(rx_buffer->page);
8636 /* we are reusing so sync this buffer for CPU use */
8637 dma_sync_single_range_for_cpu(rx_ring->dev,
8639 rx_buffer->page_offset,
8643 rx_buffer->pagecnt_bias--;
8648 static void igb_put_rx_buffer(struct igb_ring *rx_ring,
8649 struct igb_rx_buffer *rx_buffer, int rx_buf_pgcnt)
8651 if (igb_can_reuse_rx_page(rx_buffer, rx_buf_pgcnt)) {
8652 /* hand second half of page back to the ring */
8653 igb_reuse_rx_page(rx_ring, rx_buffer);
8655 /* We are not reusing the buffer so unmap it and free
8656 * any references we are holding to it
8658 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
8659 igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE,
8661 __page_frag_cache_drain(rx_buffer->page,
8662 rx_buffer->pagecnt_bias);
8665 /* clear contents of rx_buffer */
8666 rx_buffer->page = NULL;
8669 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
8671 struct igb_adapter *adapter = q_vector->adapter;
8672 struct igb_ring *rx_ring = q_vector->rx.ring;
8673 struct sk_buff *skb = rx_ring->skb;
8674 unsigned int total_bytes = 0, total_packets = 0;
8675 u16 cleaned_count = igb_desc_unused(rx_ring);
8676 unsigned int xdp_xmit = 0;
8677 struct xdp_buff xdp;
8681 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */
8682 #if (PAGE_SIZE < 8192)
8683 frame_sz = igb_rx_frame_truesize(rx_ring, 0);
8685 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq);
8687 while (likely(total_packets < budget)) {
8688 union e1000_adv_rx_desc *rx_desc;
8689 struct igb_rx_buffer *rx_buffer;
8690 ktime_t timestamp = 0;
8695 /* return some buffers to hardware, one at a time is too slow */
8696 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
8697 igb_alloc_rx_buffers(rx_ring, cleaned_count);
8701 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
8702 size = le16_to_cpu(rx_desc->wb.upper.length);
8706 /* This memory barrier is needed to keep us from reading
8707 * any other fields out of the rx_desc until we know the
8708 * descriptor has been written back
8712 rx_buffer = igb_get_rx_buffer(rx_ring, size, &rx_buf_pgcnt);
8713 pktbuf = page_address(rx_buffer->page) + rx_buffer->page_offset;
8715 /* pull rx packet timestamp if available and valid */
8716 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
8719 ts_hdr_len = igb_ptp_rx_pktstamp(rx_ring->q_vector,
8720 pktbuf, ×tamp);
8722 pkt_offset += ts_hdr_len;
8726 /* retrieve a buffer from the ring */
8728 unsigned char *hard_start = pktbuf - igb_rx_offset(rx_ring);
8729 unsigned int offset = pkt_offset + igb_rx_offset(rx_ring);
8731 xdp_prepare_buff(&xdp, hard_start, offset, size, true);
8732 #if (PAGE_SIZE > 4096)
8733 /* At larger PAGE_SIZE, frame_sz depend on len size */
8734 xdp.frame_sz = igb_rx_frame_truesize(rx_ring, size);
8736 skb = igb_run_xdp(adapter, rx_ring, &xdp);
8740 unsigned int xdp_res = -PTR_ERR(skb);
8742 if (xdp_res & (IGB_XDP_TX | IGB_XDP_REDIR)) {
8743 xdp_xmit |= xdp_res;
8744 igb_rx_buffer_flip(rx_ring, rx_buffer, size);
8746 rx_buffer->pagecnt_bias++;
8749 total_bytes += size;
8751 igb_add_rx_frag(rx_ring, rx_buffer, skb, size);
8752 else if (ring_uses_build_skb(rx_ring))
8753 skb = igb_build_skb(rx_ring, rx_buffer, &xdp,
8756 skb = igb_construct_skb(rx_ring, rx_buffer,
8759 /* exit if we failed to retrieve a buffer */
8761 rx_ring->rx_stats.alloc_failed++;
8762 rx_buffer->pagecnt_bias++;
8766 igb_put_rx_buffer(rx_ring, rx_buffer, rx_buf_pgcnt);
8769 /* fetch next buffer in frame if non-eop */
8770 if (igb_is_non_eop(rx_ring, rx_desc))
8773 /* verify the packet layout is correct */
8774 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
8779 /* probably a little skewed due to removing CRC */
8780 total_bytes += skb->len;
8782 /* populate checksum, timestamp, VLAN, and protocol */
8783 igb_process_skb_fields(rx_ring, rx_desc, skb);
8785 napi_gro_receive(&q_vector->napi, skb);
8787 /* reset skb pointer */
8790 /* update budget accounting */
8794 /* place incomplete frames back on ring for completion */
8797 if (xdp_xmit & IGB_XDP_REDIR)
8800 if (xdp_xmit & IGB_XDP_TX) {
8801 struct igb_ring *tx_ring = igb_xdp_tx_queue_mapping(adapter);
8803 igb_xdp_ring_update_tail(tx_ring);
8806 u64_stats_update_begin(&rx_ring->rx_syncp);
8807 rx_ring->rx_stats.packets += total_packets;
8808 rx_ring->rx_stats.bytes += total_bytes;
8809 u64_stats_update_end(&rx_ring->rx_syncp);
8810 q_vector->rx.total_packets += total_packets;
8811 q_vector->rx.total_bytes += total_bytes;
8814 igb_alloc_rx_buffers(rx_ring, cleaned_count);
8816 return total_packets;
8819 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
8820 struct igb_rx_buffer *bi)
8822 struct page *page = bi->page;
8825 /* since we are recycling buffers we should seldom need to alloc */
8829 /* alloc new page for storage */
8830 page = dev_alloc_pages(igb_rx_pg_order(rx_ring));
8831 if (unlikely(!page)) {
8832 rx_ring->rx_stats.alloc_failed++;
8836 /* map page for use */
8837 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
8838 igb_rx_pg_size(rx_ring),
8842 /* if mapping failed free memory back to system since
8843 * there isn't much point in holding memory we can't use
8845 if (dma_mapping_error(rx_ring->dev, dma)) {
8846 __free_pages(page, igb_rx_pg_order(rx_ring));
8848 rx_ring->rx_stats.alloc_failed++;
8854 bi->page_offset = igb_rx_offset(rx_ring);
8855 page_ref_add(page, USHRT_MAX - 1);
8856 bi->pagecnt_bias = USHRT_MAX;
8862 * igb_alloc_rx_buffers - Replace used receive buffers
8863 * @rx_ring: rx descriptor ring to allocate new receive buffers
8864 * @cleaned_count: count of buffers to allocate
8866 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
8868 union e1000_adv_rx_desc *rx_desc;
8869 struct igb_rx_buffer *bi;
8870 u16 i = rx_ring->next_to_use;
8877 rx_desc = IGB_RX_DESC(rx_ring, i);
8878 bi = &rx_ring->rx_buffer_info[i];
8879 i -= rx_ring->count;
8881 bufsz = igb_rx_bufsz(rx_ring);
8884 if (!igb_alloc_mapped_page(rx_ring, bi))
8887 /* sync the buffer for use by the device */
8888 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
8889 bi->page_offset, bufsz,
8892 /* Refresh the desc even if buffer_addrs didn't change
8893 * because each write-back erases this info.
8895 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
8901 rx_desc = IGB_RX_DESC(rx_ring, 0);
8902 bi = rx_ring->rx_buffer_info;
8903 i -= rx_ring->count;
8906 /* clear the length for the next_to_use descriptor */
8907 rx_desc->wb.upper.length = 0;
8910 } while (cleaned_count);
8912 i += rx_ring->count;
8914 if (rx_ring->next_to_use != i) {
8915 /* record the next descriptor to use */
8916 rx_ring->next_to_use = i;
8918 /* update next to alloc since we have filled the ring */
8919 rx_ring->next_to_alloc = i;
8921 /* Force memory writes to complete before letting h/w
8922 * know there are new descriptors to fetch. (Only
8923 * applicable for weak-ordered memory model archs,
8927 writel(i, rx_ring->tail);
8933 * @netdev: pointer to netdev struct
8934 * @ifr: interface structure
8935 * @cmd: ioctl command to execute
8937 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
8939 struct igb_adapter *adapter = netdev_priv(netdev);
8940 struct mii_ioctl_data *data = if_mii(ifr);
8942 if (adapter->hw.phy.media_type != e1000_media_type_copper)
8947 data->phy_id = adapter->hw.phy.addr;
8950 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
8963 * @netdev: pointer to netdev struct
8964 * @ifr: interface structure
8965 * @cmd: ioctl command to execute
8967 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
8973 return igb_mii_ioctl(netdev, ifr, cmd);
8975 return igb_ptp_get_ts_config(netdev, ifr);
8977 return igb_ptp_set_ts_config(netdev, ifr);
8983 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
8985 struct igb_adapter *adapter = hw->back;
8987 pci_read_config_word(adapter->pdev, reg, value);
8990 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
8992 struct igb_adapter *adapter = hw->back;
8994 pci_write_config_word(adapter->pdev, reg, *value);
8997 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
8999 struct igb_adapter *adapter = hw->back;
9001 if (pcie_capability_read_word(adapter->pdev, reg, value))
9002 return -E1000_ERR_CONFIG;
9007 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
9009 struct igb_adapter *adapter = hw->back;
9011 if (pcie_capability_write_word(adapter->pdev, reg, *value))
9012 return -E1000_ERR_CONFIG;
9017 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9019 struct igb_adapter *adapter = netdev_priv(netdev);
9020 struct e1000_hw *hw = &adapter->hw;
9022 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9025 /* enable VLAN tag insert/strip */
9026 ctrl = rd32(E1000_CTRL);
9027 ctrl |= E1000_CTRL_VME;
9028 wr32(E1000_CTRL, ctrl);
9030 /* Disable CFI check */
9031 rctl = rd32(E1000_RCTL);
9032 rctl &= ~E1000_RCTL_CFIEN;
9033 wr32(E1000_RCTL, rctl);
9035 /* disable VLAN tag insert/strip */
9036 ctrl = rd32(E1000_CTRL);
9037 ctrl &= ~E1000_CTRL_VME;
9038 wr32(E1000_CTRL, ctrl);
9041 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable);
9044 static int igb_vlan_rx_add_vid(struct net_device *netdev,
9045 __be16 proto, u16 vid)
9047 struct igb_adapter *adapter = netdev_priv(netdev);
9048 struct e1000_hw *hw = &adapter->hw;
9049 int pf_id = adapter->vfs_allocated_count;
9051 /* add the filter since PF can receive vlans w/o entry in vlvf */
9052 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
9053 igb_vfta_set(hw, vid, pf_id, true, !!vid);
9055 set_bit(vid, adapter->active_vlans);
9060 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
9061 __be16 proto, u16 vid)
9063 struct igb_adapter *adapter = netdev_priv(netdev);
9064 int pf_id = adapter->vfs_allocated_count;
9065 struct e1000_hw *hw = &adapter->hw;
9067 /* remove VID from filter table */
9068 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
9069 igb_vfta_set(hw, vid, pf_id, false, true);
9071 clear_bit(vid, adapter->active_vlans);
9076 static void igb_restore_vlan(struct igb_adapter *adapter)
9080 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
9081 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
9083 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
9084 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9087 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9089 struct pci_dev *pdev = adapter->pdev;
9090 struct e1000_mac_info *mac = &adapter->hw.mac;
9094 /* Make sure dplx is at most 1 bit and lsb of speed is not set
9095 * for the switch() below to work
9097 if ((spd & 1) || (dplx & ~1))
9100 /* Fiber NIC's only allow 1000 gbps Full duplex
9101 * and 100Mbps Full duplex for 100baseFx sfp
9103 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
9104 switch (spd + dplx) {
9105 case SPEED_10 + DUPLEX_HALF:
9106 case SPEED_10 + DUPLEX_FULL:
9107 case SPEED_100 + DUPLEX_HALF:
9114 switch (spd + dplx) {
9115 case SPEED_10 + DUPLEX_HALF:
9116 mac->forced_speed_duplex = ADVERTISE_10_HALF;
9118 case SPEED_10 + DUPLEX_FULL:
9119 mac->forced_speed_duplex = ADVERTISE_10_FULL;
9121 case SPEED_100 + DUPLEX_HALF:
9122 mac->forced_speed_duplex = ADVERTISE_100_HALF;
9124 case SPEED_100 + DUPLEX_FULL:
9125 mac->forced_speed_duplex = ADVERTISE_100_FULL;
9127 case SPEED_1000 + DUPLEX_FULL:
9129 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
9131 case SPEED_1000 + DUPLEX_HALF: /* not supported */
9136 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
9137 adapter->hw.phy.mdix = AUTO_ALL_MODES;
9142 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
9146 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
9149 struct net_device *netdev = pci_get_drvdata(pdev);
9150 struct igb_adapter *adapter = netdev_priv(netdev);
9151 struct e1000_hw *hw = &adapter->hw;
9152 u32 ctrl, rctl, status;
9153 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9157 netif_device_detach(netdev);
9159 if (netif_running(netdev))
9160 __igb_close(netdev, true);
9162 igb_ptp_suspend(adapter);
9164 igb_clear_interrupt_scheme(adapter);
9167 status = rd32(E1000_STATUS);
9168 if (status & E1000_STATUS_LU)
9169 wufc &= ~E1000_WUFC_LNKC;
9172 igb_setup_rctl(adapter);
9173 igb_set_rx_mode(netdev);
9175 /* turn on all-multi mode if wake on multicast is enabled */
9176 if (wufc & E1000_WUFC_MC) {
9177 rctl = rd32(E1000_RCTL);
9178 rctl |= E1000_RCTL_MPE;
9179 wr32(E1000_RCTL, rctl);
9182 ctrl = rd32(E1000_CTRL);
9183 ctrl |= E1000_CTRL_ADVD3WUC;
9184 wr32(E1000_CTRL, ctrl);
9186 /* Allow time for pending master requests to run */
9187 igb_disable_pcie_master(hw);
9189 wr32(E1000_WUC, E1000_WUC_PME_EN);
9190 wr32(E1000_WUFC, wufc);
9193 wr32(E1000_WUFC, 0);
9196 wake = wufc || adapter->en_mng_pt;
9198 igb_power_down_link(adapter);
9200 igb_power_up_link(adapter);
9203 *enable_wake = wake;
9205 /* Release control of h/w to f/w. If f/w is AMT enabled, this
9206 * would have already happened in close and is redundant.
9208 igb_release_hw_control(adapter);
9210 pci_disable_device(pdev);
9215 static void igb_deliver_wake_packet(struct net_device *netdev)
9217 struct igb_adapter *adapter = netdev_priv(netdev);
9218 struct e1000_hw *hw = &adapter->hw;
9219 struct sk_buff *skb;
9222 wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK;
9224 /* WUPM stores only the first 128 bytes of the wake packet.
9225 * Read the packet only if we have the whole thing.
9227 if ((wupl == 0) || (wupl > E1000_WUPM_BYTES))
9230 skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES);
9236 /* Ensure reads are 32-bit aligned */
9237 wupl = roundup(wupl, 4);
9239 memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl);
9241 skb->protocol = eth_type_trans(skb, netdev);
9245 static int __maybe_unused igb_suspend(struct device *dev)
9247 return __igb_shutdown(to_pci_dev(dev), NULL, 0);
9250 static int __maybe_unused igb_resume(struct device *dev)
9252 struct pci_dev *pdev = to_pci_dev(dev);
9253 struct net_device *netdev = pci_get_drvdata(pdev);
9254 struct igb_adapter *adapter = netdev_priv(netdev);
9255 struct e1000_hw *hw = &adapter->hw;
9258 pci_set_power_state(pdev, PCI_D0);
9259 pci_restore_state(pdev);
9260 pci_save_state(pdev);
9262 if (!pci_device_is_present(pdev))
9264 err = pci_enable_device_mem(pdev);
9267 "igb: Cannot enable PCI device from suspend\n");
9270 pci_set_master(pdev);
9272 pci_enable_wake(pdev, PCI_D3hot, 0);
9273 pci_enable_wake(pdev, PCI_D3cold, 0);
9275 if (igb_init_interrupt_scheme(adapter, true)) {
9276 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
9282 /* let the f/w know that the h/w is now under the control of the
9285 igb_get_hw_control(adapter);
9287 val = rd32(E1000_WUS);
9288 if (val & WAKE_PKT_WUS)
9289 igb_deliver_wake_packet(netdev);
9291 wr32(E1000_WUS, ~0);
9294 if (!err && netif_running(netdev))
9295 err = __igb_open(netdev, true);
9298 netif_device_attach(netdev);
9304 static int __maybe_unused igb_runtime_idle(struct device *dev)
9306 struct net_device *netdev = dev_get_drvdata(dev);
9307 struct igb_adapter *adapter = netdev_priv(netdev);
9309 if (!igb_has_link(adapter))
9310 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
9315 static int __maybe_unused igb_runtime_suspend(struct device *dev)
9317 return __igb_shutdown(to_pci_dev(dev), NULL, 1);
9320 static int __maybe_unused igb_runtime_resume(struct device *dev)
9322 return igb_resume(dev);
9325 static void igb_shutdown(struct pci_dev *pdev)
9329 __igb_shutdown(pdev, &wake, 0);
9331 if (system_state == SYSTEM_POWER_OFF) {
9332 pci_wake_from_d3(pdev, wake);
9333 pci_set_power_state(pdev, PCI_D3hot);
9337 #ifdef CONFIG_PCI_IOV
9338 static int igb_sriov_reinit(struct pci_dev *dev)
9340 struct net_device *netdev = pci_get_drvdata(dev);
9341 struct igb_adapter *adapter = netdev_priv(netdev);
9342 struct pci_dev *pdev = adapter->pdev;
9346 if (netif_running(netdev))
9351 igb_clear_interrupt_scheme(adapter);
9353 igb_init_queue_configuration(adapter);
9355 if (igb_init_interrupt_scheme(adapter, true)) {
9357 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
9361 if (netif_running(netdev))
9369 static int igb_pci_disable_sriov(struct pci_dev *dev)
9371 int err = igb_disable_sriov(dev);
9374 err = igb_sriov_reinit(dev);
9379 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
9381 int err = igb_enable_sriov(dev, num_vfs);
9386 err = igb_sriov_reinit(dev);
9395 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
9397 #ifdef CONFIG_PCI_IOV
9399 return igb_pci_disable_sriov(dev);
9401 return igb_pci_enable_sriov(dev, num_vfs);
9407 * igb_io_error_detected - called when PCI error is detected
9408 * @pdev: Pointer to PCI device
9409 * @state: The current pci connection state
9411 * This function is called after a PCI bus error affecting
9412 * this device has been detected.
9414 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
9415 pci_channel_state_t state)
9417 struct net_device *netdev = pci_get_drvdata(pdev);
9418 struct igb_adapter *adapter = netdev_priv(netdev);
9420 netif_device_detach(netdev);
9422 if (state == pci_channel_io_perm_failure)
9423 return PCI_ERS_RESULT_DISCONNECT;
9425 if (netif_running(netdev))
9427 pci_disable_device(pdev);
9429 /* Request a slot slot reset. */
9430 return PCI_ERS_RESULT_NEED_RESET;
9434 * igb_io_slot_reset - called after the pci bus has been reset.
9435 * @pdev: Pointer to PCI device
9437 * Restart the card from scratch, as if from a cold-boot. Implementation
9438 * resembles the first-half of the igb_resume routine.
9440 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
9442 struct net_device *netdev = pci_get_drvdata(pdev);
9443 struct igb_adapter *adapter = netdev_priv(netdev);
9444 struct e1000_hw *hw = &adapter->hw;
9445 pci_ers_result_t result;
9447 if (pci_enable_device_mem(pdev)) {
9449 "Cannot re-enable PCI device after reset.\n");
9450 result = PCI_ERS_RESULT_DISCONNECT;
9452 pci_set_master(pdev);
9453 pci_restore_state(pdev);
9454 pci_save_state(pdev);
9456 pci_enable_wake(pdev, PCI_D3hot, 0);
9457 pci_enable_wake(pdev, PCI_D3cold, 0);
9459 /* In case of PCI error, adapter lose its HW address
9460 * so we should re-assign it here.
9462 hw->hw_addr = adapter->io_addr;
9465 wr32(E1000_WUS, ~0);
9466 result = PCI_ERS_RESULT_RECOVERED;
9473 * igb_io_resume - called when traffic can start flowing again.
9474 * @pdev: Pointer to PCI device
9476 * This callback is called when the error recovery driver tells us that
9477 * its OK to resume normal operation. Implementation resembles the
9478 * second-half of the igb_resume routine.
9480 static void igb_io_resume(struct pci_dev *pdev)
9482 struct net_device *netdev = pci_get_drvdata(pdev);
9483 struct igb_adapter *adapter = netdev_priv(netdev);
9485 if (netif_running(netdev)) {
9486 if (igb_up(adapter)) {
9487 dev_err(&pdev->dev, "igb_up failed after reset\n");
9492 netif_device_attach(netdev);
9494 /* let the f/w know that the h/w is now under the control of the
9497 igb_get_hw_control(adapter);
9501 * igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table
9502 * @adapter: Pointer to adapter structure
9503 * @index: Index of the RAR entry which need to be synced with MAC table
9505 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index)
9507 struct e1000_hw *hw = &adapter->hw;
9508 u32 rar_low, rar_high;
9509 u8 *addr = adapter->mac_table[index].addr;
9511 /* HW expects these to be in network order when they are plugged
9512 * into the registers which are little endian. In order to guarantee
9513 * that ordering we need to do an leXX_to_cpup here in order to be
9514 * ready for the byteswap that occurs with writel
9516 rar_low = le32_to_cpup((__le32 *)(addr));
9517 rar_high = le16_to_cpup((__le16 *)(addr + 4));
9519 /* Indicate to hardware the Address is Valid. */
9520 if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) {
9521 if (is_valid_ether_addr(addr))
9522 rar_high |= E1000_RAH_AV;
9524 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR)
9525 rar_high |= E1000_RAH_ASEL_SRC_ADDR;
9527 switch (hw->mac.type) {
9530 if (adapter->mac_table[index].state &
9531 IGB_MAC_STATE_QUEUE_STEERING)
9532 rar_high |= E1000_RAH_QSEL_ENABLE;
9534 rar_high |= E1000_RAH_POOL_1 *
9535 adapter->mac_table[index].queue;
9538 rar_high |= E1000_RAH_POOL_1 <<
9539 adapter->mac_table[index].queue;
9544 wr32(E1000_RAL(index), rar_low);
9546 wr32(E1000_RAH(index), rar_high);
9550 static int igb_set_vf_mac(struct igb_adapter *adapter,
9551 int vf, unsigned char *mac_addr)
9553 struct e1000_hw *hw = &adapter->hw;
9554 /* VF MAC addresses start at end of receive addresses and moves
9555 * towards the first, as a result a collision should not be possible
9557 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
9558 unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses;
9560 ether_addr_copy(vf_mac_addr, mac_addr);
9561 ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr);
9562 adapter->mac_table[rar_entry].queue = vf;
9563 adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE;
9564 igb_rar_set_index(adapter, rar_entry);
9569 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
9571 struct igb_adapter *adapter = netdev_priv(netdev);
9573 if (vf >= adapter->vfs_allocated_count)
9576 /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC
9577 * flag and allows to overwrite the MAC via VF netdev. This
9578 * is necessary to allow libvirt a way to restore the original
9579 * MAC after unbinding vfio-pci and reloading igbvf after shutting
9582 if (is_zero_ether_addr(mac)) {
9583 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC;
9584 dev_info(&adapter->pdev->dev,
9585 "remove administratively set MAC on VF %d\n",
9587 } else if (is_valid_ether_addr(mac)) {
9588 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
9589 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n",
9591 dev_info(&adapter->pdev->dev,
9592 "Reload the VF driver to make this change effective.");
9593 /* Generate additional warning if PF is down */
9594 if (test_bit(__IGB_DOWN, &adapter->state)) {
9595 dev_warn(&adapter->pdev->dev,
9596 "The VF MAC address has been set, but the PF device is not up.\n");
9597 dev_warn(&adapter->pdev->dev,
9598 "Bring the PF device up before attempting to use the VF device.\n");
9603 return igb_set_vf_mac(adapter, vf, mac);
9606 static int igb_link_mbps(int internal_link_speed)
9608 switch (internal_link_speed) {
9618 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
9625 /* Calculate the rate factor values to set */
9626 rf_int = link_speed / tx_rate;
9627 rf_dec = (link_speed - (rf_int * tx_rate));
9628 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) /
9631 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
9632 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
9633 E1000_RTTBCNRC_RF_INT_MASK);
9634 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
9639 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
9640 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
9641 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
9643 wr32(E1000_RTTBCNRM, 0x14);
9644 wr32(E1000_RTTBCNRC, bcnrc_val);
9647 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
9649 int actual_link_speed, i;
9650 bool reset_rate = false;
9652 /* VF TX rate limit was not set or not supported */
9653 if ((adapter->vf_rate_link_speed == 0) ||
9654 (adapter->hw.mac.type != e1000_82576))
9657 actual_link_speed = igb_link_mbps(adapter->link_speed);
9658 if (actual_link_speed != adapter->vf_rate_link_speed) {
9660 adapter->vf_rate_link_speed = 0;
9661 dev_info(&adapter->pdev->dev,
9662 "Link speed has been changed. VF Transmit rate is disabled\n");
9665 for (i = 0; i < adapter->vfs_allocated_count; i++) {
9667 adapter->vf_data[i].tx_rate = 0;
9669 igb_set_vf_rate_limit(&adapter->hw, i,
9670 adapter->vf_data[i].tx_rate,
9675 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
9676 int min_tx_rate, int max_tx_rate)
9678 struct igb_adapter *adapter = netdev_priv(netdev);
9679 struct e1000_hw *hw = &adapter->hw;
9680 int actual_link_speed;
9682 if (hw->mac.type != e1000_82576)
9688 actual_link_speed = igb_link_mbps(adapter->link_speed);
9689 if ((vf >= adapter->vfs_allocated_count) ||
9690 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
9691 (max_tx_rate < 0) ||
9692 (max_tx_rate > actual_link_speed))
9695 adapter->vf_rate_link_speed = actual_link_speed;
9696 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
9697 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
9702 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
9705 struct igb_adapter *adapter = netdev_priv(netdev);
9706 struct e1000_hw *hw = &adapter->hw;
9707 u32 reg_val, reg_offset;
9709 if (!adapter->vfs_allocated_count)
9712 if (vf >= adapter->vfs_allocated_count)
9715 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
9716 reg_val = rd32(reg_offset);
9718 reg_val |= (BIT(vf) |
9719 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
9721 reg_val &= ~(BIT(vf) |
9722 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
9723 wr32(reg_offset, reg_val);
9725 adapter->vf_data[vf].spoofchk_enabled = setting;
9729 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting)
9731 struct igb_adapter *adapter = netdev_priv(netdev);
9733 if (vf >= adapter->vfs_allocated_count)
9735 if (adapter->vf_data[vf].trusted == setting)
9738 adapter->vf_data[vf].trusted = setting;
9740 dev_info(&adapter->pdev->dev, "VF %u is %strusted\n",
9741 vf, setting ? "" : "not ");
9745 static int igb_ndo_get_vf_config(struct net_device *netdev,
9746 int vf, struct ifla_vf_info *ivi)
9748 struct igb_adapter *adapter = netdev_priv(netdev);
9749 if (vf >= adapter->vfs_allocated_count)
9752 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
9753 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
9754 ivi->min_tx_rate = 0;
9755 ivi->vlan = adapter->vf_data[vf].pf_vlan;
9756 ivi->qos = adapter->vf_data[vf].pf_qos;
9757 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
9758 ivi->trusted = adapter->vf_data[vf].trusted;
9762 static void igb_vmm_control(struct igb_adapter *adapter)
9764 struct e1000_hw *hw = &adapter->hw;
9767 switch (hw->mac.type) {
9773 /* replication is not supported for 82575 */
9776 /* notify HW that the MAC is adding vlan tags */
9777 reg = rd32(E1000_DTXCTL);
9778 reg |= E1000_DTXCTL_VLAN_ADDED;
9779 wr32(E1000_DTXCTL, reg);
9782 /* enable replication vlan tag stripping */
9783 reg = rd32(E1000_RPLOLR);
9784 reg |= E1000_RPLOLR_STRVLAN;
9785 wr32(E1000_RPLOLR, reg);
9788 /* none of the above registers are supported by i350 */
9792 if (adapter->vfs_allocated_count) {
9793 igb_vmdq_set_loopback_pf(hw, true);
9794 igb_vmdq_set_replication_pf(hw, true);
9795 igb_vmdq_set_anti_spoofing_pf(hw, true,
9796 adapter->vfs_allocated_count);
9798 igb_vmdq_set_loopback_pf(hw, false);
9799 igb_vmdq_set_replication_pf(hw, false);
9803 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
9805 struct e1000_hw *hw = &adapter->hw;
9809 if (hw->mac.type > e1000_82580) {
9810 if (adapter->flags & IGB_FLAG_DMAC) {
9813 /* force threshold to 0. */
9814 wr32(E1000_DMCTXTH, 0);
9816 /* DMA Coalescing high water mark needs to be greater
9817 * than the Rx threshold. Set hwm to PBA - max frame
9818 * size in 16B units, capping it at PBA - 6KB.
9820 hwm = 64 * (pba - 6);
9821 reg = rd32(E1000_FCRTC);
9822 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
9823 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
9824 & E1000_FCRTC_RTH_COAL_MASK);
9825 wr32(E1000_FCRTC, reg);
9827 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
9828 * frame size, capping it at PBA - 10KB.
9830 dmac_thr = pba - 10;
9831 reg = rd32(E1000_DMACR);
9832 reg &= ~E1000_DMACR_DMACTHR_MASK;
9833 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
9834 & E1000_DMACR_DMACTHR_MASK);
9836 /* transition to L0x or L1 if available..*/
9837 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
9839 /* watchdog timer= +-1000 usec in 32usec intervals */
9842 /* Disable BMC-to-OS Watchdog Enable */
9843 if (hw->mac.type != e1000_i354)
9844 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
9846 wr32(E1000_DMACR, reg);
9848 /* no lower threshold to disable
9849 * coalescing(smart fifb)-UTRESH=0
9851 wr32(E1000_DMCRTRH, 0);
9853 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
9855 wr32(E1000_DMCTLX, reg);
9857 /* free space in tx packet buffer to wake from
9860 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
9861 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
9863 /* make low power state decision controlled
9866 reg = rd32(E1000_PCIEMISC);
9867 reg &= ~E1000_PCIEMISC_LX_DECISION;
9868 wr32(E1000_PCIEMISC, reg);
9869 } /* endif adapter->dmac is not disabled */
9870 } else if (hw->mac.type == e1000_82580) {
9871 u32 reg = rd32(E1000_PCIEMISC);
9873 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
9874 wr32(E1000_DMACR, 0);
9879 * igb_read_i2c_byte - Reads 8 bit word over I2C
9880 * @hw: pointer to hardware structure
9881 * @byte_offset: byte offset to read
9882 * @dev_addr: device address
9885 * Performs byte read operation over I2C interface at
9886 * a specified device address.
9888 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
9889 u8 dev_addr, u8 *data)
9891 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
9892 struct i2c_client *this_client = adapter->i2c_client;
9897 return E1000_ERR_I2C;
9899 swfw_mask = E1000_SWFW_PHY0_SM;
9901 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
9902 return E1000_ERR_SWFW_SYNC;
9904 status = i2c_smbus_read_byte_data(this_client, byte_offset);
9905 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
9908 return E1000_ERR_I2C;
9916 * igb_write_i2c_byte - Writes 8 bit word over I2C
9917 * @hw: pointer to hardware structure
9918 * @byte_offset: byte offset to write
9919 * @dev_addr: device address
9920 * @data: value to write
9922 * Performs byte write operation over I2C interface at
9923 * a specified device address.
9925 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
9926 u8 dev_addr, u8 data)
9928 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
9929 struct i2c_client *this_client = adapter->i2c_client;
9931 u16 swfw_mask = E1000_SWFW_PHY0_SM;
9934 return E1000_ERR_I2C;
9936 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
9937 return E1000_ERR_SWFW_SYNC;
9938 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
9939 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
9942 return E1000_ERR_I2C;
9948 int igb_reinit_queues(struct igb_adapter *adapter)
9950 struct net_device *netdev = adapter->netdev;
9951 struct pci_dev *pdev = adapter->pdev;
9954 if (netif_running(netdev))
9957 igb_reset_interrupt_capability(adapter);
9959 if (igb_init_interrupt_scheme(adapter, true)) {
9960 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
9964 if (netif_running(netdev))
9965 err = igb_open(netdev);
9970 static void igb_nfc_filter_exit(struct igb_adapter *adapter)
9972 struct igb_nfc_filter *rule;
9974 spin_lock(&adapter->nfc_lock);
9976 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
9977 igb_erase_filter(adapter, rule);
9979 hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node)
9980 igb_erase_filter(adapter, rule);
9982 spin_unlock(&adapter->nfc_lock);
9985 static void igb_nfc_filter_restore(struct igb_adapter *adapter)
9987 struct igb_nfc_filter *rule;
9989 spin_lock(&adapter->nfc_lock);
9991 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
9992 igb_add_filter(adapter, rule);
9994 spin_unlock(&adapter->nfc_lock);