drivers/net/ethernet/intel/igb/igb_ethtool.c

   1 /* Intel(R) Gigabit Ethernet Linux driver
   2  * Copyright(c) 2007-2014 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, see <http://www.gnu.org/licenses/>.
  15  *
  16  * The full GNU General Public License is included in this distribution in
  17  * the file called "COPYING".
  18  *
  19  * Contact Information:
  20  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22  */
  23
  24 /* ethtool support for igb */
  25
  26 #include <linux/vmalloc.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/if_ether.h>
  32 #include <linux/ethtool.h>
  33 #include <linux/sched.h>
  34 #include <linux/slab.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/highmem.h>
  37 #include <linux/mdio.h>
  38
  39 #include "igb.h"
  40
  41 struct igb_stats {
  42         char stat_string[ETH_GSTRING_LEN];
  43         int sizeof_stat;
  44         int stat_offset;
  45 };
  46
  47 #define IGB_STAT(_name, _stat) { \
  48         .stat_string = _name, \
  49         .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
  50         .stat_offset = offsetof(struct igb_adapter, _stat) \
  51 }
  52 static const struct igb_stats igb_gstrings_stats[] = {
  53         IGB_STAT("rx_packets", stats.gprc),
  54         IGB_STAT("tx_packets", stats.gptc),
  55         IGB_STAT("rx_bytes", stats.gorc),
  56         IGB_STAT("tx_bytes", stats.gotc),
  57         IGB_STAT("rx_broadcast", stats.bprc),
  58         IGB_STAT("tx_broadcast", stats.bptc),
  59         IGB_STAT("rx_multicast", stats.mprc),
  60         IGB_STAT("tx_multicast", stats.mptc),
  61         IGB_STAT("multicast", stats.mprc),
  62         IGB_STAT("collisions", stats.colc),
  63         IGB_STAT("rx_crc_errors", stats.crcerrs),
  64         IGB_STAT("rx_no_buffer_count", stats.rnbc),
  65         IGB_STAT("rx_missed_errors", stats.mpc),
  66         IGB_STAT("tx_aborted_errors", stats.ecol),
  67         IGB_STAT("tx_carrier_errors", stats.tncrs),
  68         IGB_STAT("tx_window_errors", stats.latecol),
  69         IGB_STAT("tx_abort_late_coll", stats.latecol),
  70         IGB_STAT("tx_deferred_ok", stats.dc),
  71         IGB_STAT("tx_single_coll_ok", stats.scc),
  72         IGB_STAT("tx_multi_coll_ok", stats.mcc),
  73         IGB_STAT("tx_timeout_count", tx_timeout_count),
  74         IGB_STAT("rx_long_length_errors", stats.roc),
  75         IGB_STAT("rx_short_length_errors", stats.ruc),
  76         IGB_STAT("rx_align_errors", stats.algnerrc),
  77         IGB_STAT("tx_tcp_seg_good", stats.tsctc),
  78         IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
  79         IGB_STAT("rx_flow_control_xon", stats.xonrxc),
  80         IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
  81         IGB_STAT("tx_flow_control_xon", stats.xontxc),
  82         IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
  83         IGB_STAT("rx_long_byte_count", stats.gorc),
  84         IGB_STAT("tx_dma_out_of_sync", stats.doosync),
  85         IGB_STAT("tx_smbus", stats.mgptc),
  86         IGB_STAT("rx_smbus", stats.mgprc),
  87         IGB_STAT("dropped_smbus", stats.mgpdc),
  88         IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
  89         IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
  90         IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
  91         IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
  92         IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
  93         IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),
  94 };
  95
  96 #define IGB_NETDEV_STAT(_net_stat) { \
  97         .stat_string = __stringify(_net_stat), \
  98         .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \
  99         .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
 100 }
 101 static const struct igb_stats igb_gstrings_net_stats[] = {
 102         IGB_NETDEV_STAT(rx_errors),
 103         IGB_NETDEV_STAT(tx_errors),
 104         IGB_NETDEV_STAT(tx_dropped),
 105         IGB_NETDEV_STAT(rx_length_errors),
 106         IGB_NETDEV_STAT(rx_over_errors),
 107         IGB_NETDEV_STAT(rx_frame_errors),
 108         IGB_NETDEV_STAT(rx_fifo_errors),
 109         IGB_NETDEV_STAT(tx_fifo_errors),
 110         IGB_NETDEV_STAT(tx_heartbeat_errors)
 111 };
 112
 113 #define IGB_GLOBAL_STATS_LEN    \
 114         (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
 115 #define IGB_NETDEV_STATS_LEN    \
 116         (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
 117 #define IGB_RX_QUEUE_STATS_LEN \
 118         (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
 119
 120 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
 121
 122 #define IGB_QUEUE_STATS_LEN \
 123         ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
 124           IGB_RX_QUEUE_STATS_LEN) + \
 125          (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
 126           IGB_TX_QUEUE_STATS_LEN))
 127 #define IGB_STATS_LEN \
 128         (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
 129
 130 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
 131         "Register test  (offline)", "Eeprom test    (offline)",
 132         "Interrupt test (offline)", "Loopback test  (offline)",
 133         "Link test   (on/offline)"
 134 };
 135 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
 136
 137 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
 138 {
 139         struct igb_adapter *adapter = netdev_priv(netdev);
 140         struct e1000_hw *hw = &adapter->hw;
 141         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 142         struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
 143         u32 status;
 144
 145         status = rd32(E1000_STATUS);
 146         if (hw->phy.media_type == e1000_media_type_copper) {
 147
 148                 ecmd->supported = (SUPPORTED_10baseT_Half |
 149                                    SUPPORTED_10baseT_Full |
 150                                    SUPPORTED_100baseT_Half |
 151                                    SUPPORTED_100baseT_Full |
 152                                    SUPPORTED_1000baseT_Full|
 153                                    SUPPORTED_Autoneg |
 154                                    SUPPORTED_TP |
 155                                    SUPPORTED_Pause);
 156                 ecmd->advertising = ADVERTISED_TP;
 157
 158                 if (hw->mac.autoneg == 1) {
 159                         ecmd->advertising |= ADVERTISED_Autoneg;
 160                         /* the e1000 autoneg seems to match ethtool nicely */
 161                         ecmd->advertising |= hw->phy.autoneg_advertised;
 162                 }
 163
 164                 ecmd->port = PORT_TP;
 165                 ecmd->phy_address = hw->phy.addr;
 166                 ecmd->transceiver = XCVR_INTERNAL;
 167         } else {
 168                 ecmd->supported = (SUPPORTED_FIBRE |
 169                                    SUPPORTED_1000baseKX_Full |
 170                                    SUPPORTED_Autoneg |
 171                                    SUPPORTED_Pause);
 172                 ecmd->advertising = (ADVERTISED_FIBRE |
 173                                      ADVERTISED_1000baseKX_Full);
 174                 if (hw->mac.type == e1000_i354) {
 175                         if ((hw->device_id ==
 176                              E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) &&
 177                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
 178                                 ecmd->supported |= SUPPORTED_2500baseX_Full;
 179                                 ecmd->supported &=
 180                                         ~SUPPORTED_1000baseKX_Full;
 181                                 ecmd->advertising |= ADVERTISED_2500baseX_Full;
 182                                 ecmd->advertising &=
 183                                         ~ADVERTISED_1000baseKX_Full;
 184                         }
 185                 }
 186                 if (eth_flags->e100_base_fx) {
 187                         ecmd->supported |= SUPPORTED_100baseT_Full;
 188                         ecmd->advertising |= ADVERTISED_100baseT_Full;
 189                 }
 190                 if (hw->mac.autoneg == 1)
 191                         ecmd->advertising |= ADVERTISED_Autoneg;
 192
 193                 ecmd->port = PORT_FIBRE;
 194                 ecmd->transceiver = XCVR_EXTERNAL;
 195         }
 196         if (hw->mac.autoneg != 1)
 197                 ecmd->advertising &= ~(ADVERTISED_Pause |
 198                                        ADVERTISED_Asym_Pause);
 199
 200         switch (hw->fc.requested_mode) {
 201         case e1000_fc_full:
 202                 ecmd->advertising |= ADVERTISED_Pause;
 203                 break;
 204         case e1000_fc_rx_pause:
 205                 ecmd->advertising |= (ADVERTISED_Pause |
 206                                       ADVERTISED_Asym_Pause);
 207                 break;
 208         case e1000_fc_tx_pause:
 209                 ecmd->advertising |=  ADVERTISED_Asym_Pause;
 210                 break;
 211         default:
 212                 ecmd->advertising &= ~(ADVERTISED_Pause |
 213                                        ADVERTISED_Asym_Pause);
 214         }
 215         if (status & E1000_STATUS_LU) {
 216                 if ((status & E1000_STATUS_2P5_SKU) &&
 217                     !(status & E1000_STATUS_2P5_SKU_OVER)) {
 218                         ecmd->speed = SPEED_2500;
 219                 } else if (status & E1000_STATUS_SPEED_1000) {
 220                         ecmd->speed = SPEED_1000;
 221                 } else if (status & E1000_STATUS_SPEED_100) {
 222                         ecmd->speed = SPEED_100;
 223                 } else {
 224                         ecmd->speed = SPEED_10;
 225                 }
 226                 if ((status & E1000_STATUS_FD) ||
 227                     hw->phy.media_type != e1000_media_type_copper)
 228                         ecmd->duplex = DUPLEX_FULL;
 229                 else
 230                         ecmd->duplex = DUPLEX_HALF;
 231         } else {
 232                 ecmd->speed = SPEED_UNKNOWN;
 233                 ecmd->duplex = DUPLEX_UNKNOWN;
 234         }
 235         if ((hw->phy.media_type == e1000_media_type_fiber) ||
 236             hw->mac.autoneg)
 237                 ecmd->autoneg = AUTONEG_ENABLE;
 238         else
 239                 ecmd->autoneg = AUTONEG_DISABLE;
 240
 241         /* MDI-X => 2; MDI =>1; Invalid =>0 */
 242         if (hw->phy.media_type == e1000_media_type_copper)
 243                 ecmd->eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X :
 244                                                       ETH_TP_MDI;
 245         else
 246                 ecmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
 247
 248         if (hw->phy.mdix == AUTO_ALL_MODES)
 249                 ecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
 250         else
 251                 ecmd->eth_tp_mdix_ctrl = hw->phy.mdix;
 252
 253         return 0;
 254 }
 255
 256 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
 257 {
 258         struct igb_adapter *adapter = netdev_priv(netdev);
 259         struct e1000_hw *hw = &adapter->hw;
 260
 261         /* When SoL/IDER sessions are active, autoneg/speed/duplex
 262          * cannot be changed
 263          */
 264         if (igb_check_reset_block(hw)) {
 265                 dev_err(&adapter->pdev->dev,
 266                         "Cannot change link characteristics when SoL/IDER is active.\n");
 267                 return -EINVAL;
 268         }
 269
 270         /* MDI setting is only allowed when autoneg enabled because
 271          * some hardware doesn't allow MDI setting when speed or
 272          * duplex is forced.
 273          */
 274         if (ecmd->eth_tp_mdix_ctrl) {
 275                 if (hw->phy.media_type != e1000_media_type_copper)
 276                         return -EOPNOTSUPP;
 277
 278                 if ((ecmd->eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&
 279                     (ecmd->autoneg != AUTONEG_ENABLE)) {
 280                         dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n");
 281                         return -EINVAL;
 282                 }
 283         }
 284
 285         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 286                 usleep_range(1000, 2000);
 287
 288         if (ecmd->autoneg == AUTONEG_ENABLE) {
 289                 hw->mac.autoneg = 1;
 290                 if (hw->phy.media_type == e1000_media_type_fiber) {
 291                         hw->phy.autoneg_advertised = ecmd->advertising |
 292                                                      ADVERTISED_FIBRE |
 293                                                      ADVERTISED_Autoneg;
 294                         switch (adapter->link_speed) {
 295                         case SPEED_2500:
 296                                 hw->phy.autoneg_advertised =
 297                                         ADVERTISED_2500baseX_Full;
 298                                 break;
 299                         case SPEED_1000:
 300                                 hw->phy.autoneg_advertised =
 301                                         ADVERTISED_1000baseT_Full;
 302                                 break;
 303                         case SPEED_100:
 304                                 hw->phy.autoneg_advertised =
 305                                         ADVERTISED_100baseT_Full;
 306                                 break;
 307                         default:
 308                                 break;
 309                         }
 310                 } else {
 311                         hw->phy.autoneg_advertised = ecmd->advertising |
 312                                                      ADVERTISED_TP |
 313                                                      ADVERTISED_Autoneg;
 314                 }
 315                 ecmd->advertising = hw->phy.autoneg_advertised;
 316                 if (adapter->fc_autoneg)
 317                         hw->fc.requested_mode = e1000_fc_default;
 318         } else {
 319                 u32 speed = ethtool_cmd_speed(ecmd);
 320                 /* calling this overrides forced MDI setting */
 321                 if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) {
 322                         clear_bit(__IGB_RESETTING, &adapter->state);
 323                         return -EINVAL;
 324                 }
 325         }
 326
 327         /* MDI-X => 2; MDI => 1; Auto => 3 */
 328         if (ecmd->eth_tp_mdix_ctrl) {
 329                 /* fix up the value for auto (3 => 0) as zero is mapped
 330                  * internally to auto
 331                  */
 332                 if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)
 333                         hw->phy.mdix = AUTO_ALL_MODES;
 334                 else
 335                         hw->phy.mdix = ecmd->eth_tp_mdix_ctrl;
 336         }
 337
 338         /* reset the link */
 339         if (netif_running(adapter->netdev)) {
 340                 igb_down(adapter);
 341                 igb_up(adapter);
 342         } else
 343                 igb_reset(adapter);
 344
 345         clear_bit(__IGB_RESETTING, &adapter->state);
 346         return 0;
 347 }
 348
 349 static u32 igb_get_link(struct net_device *netdev)
 350 {
 351         struct igb_adapter *adapter = netdev_priv(netdev);
 352         struct e1000_mac_info *mac = &adapter->hw.mac;
 353
 354         /* If the link is not reported up to netdev, interrupts are disabled,
 355          * and so the physical link state may have changed since we last
 356          * looked. Set get_link_status to make sure that the true link
 357          * state is interrogated, rather than pulling a cached and possibly
 358          * stale link state from the driver.
 359          */
 360         if (!netif_carrier_ok(netdev))
 361                 mac->get_link_status = 1;
 362
 363         return igb_has_link(adapter);
 364 }
 365
 366 static void igb_get_pauseparam(struct net_device *netdev,
 367                                struct ethtool_pauseparam *pause)
 368 {
 369         struct igb_adapter *adapter = netdev_priv(netdev);
 370         struct e1000_hw *hw = &adapter->hw;
 371
 372         pause->autoneg =
 373                 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
 374
 375         if (hw->fc.current_mode == e1000_fc_rx_pause)
 376                 pause->rx_pause = 1;
 377         else if (hw->fc.current_mode == e1000_fc_tx_pause)
 378                 pause->tx_pause = 1;
 379         else if (hw->fc.current_mode == e1000_fc_full) {
 380                 pause->rx_pause = 1;
 381                 pause->tx_pause = 1;
 382         }
 383 }
 384
 385 static int igb_set_pauseparam(struct net_device *netdev,
 386                               struct ethtool_pauseparam *pause)
 387 {
 388         struct igb_adapter *adapter = netdev_priv(netdev);
 389         struct e1000_hw *hw = &adapter->hw;
 390         int retval = 0;
 391
 392         /* 100basefx does not support setting link flow control */
 393         if (hw->dev_spec._82575.eth_flags.e100_base_fx)
 394                 return -EINVAL;
 395
 396         adapter->fc_autoneg = pause->autoneg;
 397
 398         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 399                 usleep_range(1000, 2000);
 400
 401         if (adapter->fc_autoneg == AUTONEG_ENABLE) {
 402                 hw->fc.requested_mode = e1000_fc_default;
 403                 if (netif_running(adapter->netdev)) {
 404                         igb_down(adapter);
 405                         igb_up(adapter);
 406                 } else {
 407                         igb_reset(adapter);
 408                 }
 409         } else {
 410                 if (pause->rx_pause && pause->tx_pause)
 411                         hw->fc.requested_mode = e1000_fc_full;
 412                 else if (pause->rx_pause && !pause->tx_pause)
 413                         hw->fc.requested_mode = e1000_fc_rx_pause;
 414                 else if (!pause->rx_pause && pause->tx_pause)
 415                         hw->fc.requested_mode = e1000_fc_tx_pause;
 416                 else if (!pause->rx_pause && !pause->tx_pause)
 417                         hw->fc.requested_mode = e1000_fc_none;
 418
 419                 hw->fc.current_mode = hw->fc.requested_mode;
 420
 421                 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
 422                           igb_force_mac_fc(hw) : igb_setup_link(hw));
 423         }
 424
 425         clear_bit(__IGB_RESETTING, &adapter->state);
 426         return retval;
 427 }
 428
 429 static u32 igb_get_msglevel(struct net_device *netdev)
 430 {
 431         struct igb_adapter *adapter = netdev_priv(netdev);
 432         return adapter->msg_enable;
 433 }
 434
 435 static void igb_set_msglevel(struct net_device *netdev, u32 data)
 436 {
 437         struct igb_adapter *adapter = netdev_priv(netdev);
 438         adapter->msg_enable = data;
 439 }
 440
 441 static int igb_get_regs_len(struct net_device *netdev)
 442 {
 443 #define IGB_REGS_LEN 739
 444         return IGB_REGS_LEN * sizeof(u32);
 445 }
 446
 447 static void igb_get_regs(struct net_device *netdev,
 448                          struct ethtool_regs *regs, void *p)
 449 {
 450         struct igb_adapter *adapter = netdev_priv(netdev);
 451         struct e1000_hw *hw = &adapter->hw;
 452         u32 *regs_buff = p;
 453         u8 i;
 454
 455         memset(p, 0, IGB_REGS_LEN * sizeof(u32));
 456
 457         regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
 458
 459         /* General Registers */
 460         regs_buff[0] = rd32(E1000_CTRL);
 461         regs_buff[1] = rd32(E1000_STATUS);
 462         regs_buff[2] = rd32(E1000_CTRL_EXT);
 463         regs_buff[3] = rd32(E1000_MDIC);
 464         regs_buff[4] = rd32(E1000_SCTL);
 465         regs_buff[5] = rd32(E1000_CONNSW);
 466         regs_buff[6] = rd32(E1000_VET);
 467         regs_buff[7] = rd32(E1000_LEDCTL);
 468         regs_buff[8] = rd32(E1000_PBA);
 469         regs_buff[9] = rd32(E1000_PBS);
 470         regs_buff[10] = rd32(E1000_FRTIMER);
 471         regs_buff[11] = rd32(E1000_TCPTIMER);
 472
 473         /* NVM Register */
 474         regs_buff[12] = rd32(E1000_EECD);
 475
 476         /* Interrupt */
 477         /* Reading EICS for EICR because they read the
 478          * same but EICS does not clear on read
 479          */
 480         regs_buff[13] = rd32(E1000_EICS);
 481         regs_buff[14] = rd32(E1000_EICS);
 482         regs_buff[15] = rd32(E1000_EIMS);
 483         regs_buff[16] = rd32(E1000_EIMC);
 484         regs_buff[17] = rd32(E1000_EIAC);
 485         regs_buff[18] = rd32(E1000_EIAM);
 486         /* Reading ICS for ICR because they read the
 487          * same but ICS does not clear on read
 488          */
 489         regs_buff[19] = rd32(E1000_ICS);
 490         regs_buff[20] = rd32(E1000_ICS);
 491         regs_buff[21] = rd32(E1000_IMS);
 492         regs_buff[22] = rd32(E1000_IMC);
 493         regs_buff[23] = rd32(E1000_IAC);
 494         regs_buff[24] = rd32(E1000_IAM);
 495         regs_buff[25] = rd32(E1000_IMIRVP);
 496
 497         /* Flow Control */
 498         regs_buff[26] = rd32(E1000_FCAL);
 499         regs_buff[27] = rd32(E1000_FCAH);
 500         regs_buff[28] = rd32(E1000_FCTTV);
 501         regs_buff[29] = rd32(E1000_FCRTL);
 502         regs_buff[30] = rd32(E1000_FCRTH);
 503         regs_buff[31] = rd32(E1000_FCRTV);
 504
 505         /* Receive */
 506         regs_buff[32] = rd32(E1000_RCTL);
 507         regs_buff[33] = rd32(E1000_RXCSUM);
 508         regs_buff[34] = rd32(E1000_RLPML);
 509         regs_buff[35] = rd32(E1000_RFCTL);
 510         regs_buff[36] = rd32(E1000_MRQC);
 511         regs_buff[37] = rd32(E1000_VT_CTL);
 512
 513         /* Transmit */
 514         regs_buff[38] = rd32(E1000_TCTL);
 515         regs_buff[39] = rd32(E1000_TCTL_EXT);
 516         regs_buff[40] = rd32(E1000_TIPG);
 517         regs_buff[41] = rd32(E1000_DTXCTL);
 518
 519         /* Wake Up */
 520         regs_buff[42] = rd32(E1000_WUC);
 521         regs_buff[43] = rd32(E1000_WUFC);
 522         regs_buff[44] = rd32(E1000_WUS);
 523         regs_buff[45] = rd32(E1000_IPAV);
 524         regs_buff[46] = rd32(E1000_WUPL);
 525
 526         /* MAC */
 527         regs_buff[47] = rd32(E1000_PCS_CFG0);
 528         regs_buff[48] = rd32(E1000_PCS_LCTL);
 529         regs_buff[49] = rd32(E1000_PCS_LSTAT);
 530         regs_buff[50] = rd32(E1000_PCS_ANADV);
 531         regs_buff[51] = rd32(E1000_PCS_LPAB);
 532         regs_buff[52] = rd32(E1000_PCS_NPTX);
 533         regs_buff[53] = rd32(E1000_PCS_LPABNP);
 534
 535         /* Statistics */
 536         regs_buff[54] = adapter->stats.crcerrs;
 537         regs_buff[55] = adapter->stats.algnerrc;
 538         regs_buff[56] = adapter->stats.symerrs;
 539         regs_buff[57] = adapter->stats.rxerrc;
 540         regs_buff[58] = adapter->stats.mpc;
 541         regs_buff[59] = adapter->stats.scc;
 542         regs_buff[60] = adapter->stats.ecol;
 543         regs_buff[61] = adapter->stats.mcc;
 544         regs_buff[62] = adapter->stats.latecol;
 545         regs_buff[63] = adapter->stats.colc;
 546         regs_buff[64] = adapter->stats.dc;
 547         regs_buff[65] = adapter->stats.tncrs;
 548         regs_buff[66] = adapter->stats.sec;
 549         regs_buff[67] = adapter->stats.htdpmc;
 550         regs_buff[68] = adapter->stats.rlec;
 551         regs_buff[69] = adapter->stats.xonrxc;
 552         regs_buff[70] = adapter->stats.xontxc;
 553         regs_buff[71] = adapter->stats.xoffrxc;
 554         regs_buff[72] = adapter->stats.xofftxc;
 555         regs_buff[73] = adapter->stats.fcruc;
 556         regs_buff[74] = adapter->stats.prc64;
 557         regs_buff[75] = adapter->stats.prc127;
 558         regs_buff[76] = adapter->stats.prc255;
 559         regs_buff[77] = adapter->stats.prc511;
 560         regs_buff[78] = adapter->stats.prc1023;
 561         regs_buff[79] = adapter->stats.prc1522;
 562         regs_buff[80] = adapter->stats.gprc;
 563         regs_buff[81] = adapter->stats.bprc;
 564         regs_buff[82] = adapter->stats.mprc;
 565         regs_buff[83] = adapter->stats.gptc;
 566         regs_buff[84] = adapter->stats.gorc;
 567         regs_buff[86] = adapter->stats.gotc;
 568         regs_buff[88] = adapter->stats.rnbc;
 569         regs_buff[89] = adapter->stats.ruc;
 570         regs_buff[90] = adapter->stats.rfc;
 571         regs_buff[91] = adapter->stats.roc;
 572         regs_buff[92] = adapter->stats.rjc;
 573         regs_buff[93] = adapter->stats.mgprc;
 574         regs_buff[94] = adapter->stats.mgpdc;
 575         regs_buff[95] = adapter->stats.mgptc;
 576         regs_buff[96] = adapter->stats.tor;
 577         regs_buff[98] = adapter->stats.tot;
 578         regs_buff[100] = adapter->stats.tpr;
 579         regs_buff[101] = adapter->stats.tpt;
 580         regs_buff[102] = adapter->stats.ptc64;
 581         regs_buff[103] = adapter->stats.ptc127;
 582         regs_buff[104] = adapter->stats.ptc255;
 583         regs_buff[105] = adapter->stats.ptc511;
 584         regs_buff[106] = adapter->stats.ptc1023;
 585         regs_buff[107] = adapter->stats.ptc1522;
 586         regs_buff[108] = adapter->stats.mptc;
 587         regs_buff[109] = adapter->stats.bptc;
 588         regs_buff[110] = adapter->stats.tsctc;
 589         regs_buff[111] = adapter->stats.iac;
 590         regs_buff[112] = adapter->stats.rpthc;
 591         regs_buff[113] = adapter->stats.hgptc;
 592         regs_buff[114] = adapter->stats.hgorc;
 593         regs_buff[116] = adapter->stats.hgotc;
 594         regs_buff[118] = adapter->stats.lenerrs;
 595         regs_buff[119] = adapter->stats.scvpc;
 596         regs_buff[120] = adapter->stats.hrmpc;
 597
 598         for (i = 0; i < 4; i++)
 599                 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
 600         for (i = 0; i < 4; i++)
 601                 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
 602         for (i = 0; i < 4; i++)
 603                 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
 604         for (i = 0; i < 4; i++)
 605                 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
 606         for (i = 0; i < 4; i++)
 607                 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
 608         for (i = 0; i < 4; i++)
 609                 regs_buff[141 + i] = rd32(E1000_RDH(i));
 610         for (i = 0; i < 4; i++)
 611                 regs_buff[145 + i] = rd32(E1000_RDT(i));
 612         for (i = 0; i < 4; i++)
 613                 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
 614
 615         for (i = 0; i < 10; i++)
 616                 regs_buff[153 + i] = rd32(E1000_EITR(i));
 617         for (i = 0; i < 8; i++)
 618                 regs_buff[163 + i] = rd32(E1000_IMIR(i));
 619         for (i = 0; i < 8; i++)
 620                 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
 621         for (i = 0; i < 16; i++)
 622                 regs_buff[179 + i] = rd32(E1000_RAL(i));
 623         for (i = 0; i < 16; i++)
 624                 regs_buff[195 + i] = rd32(E1000_RAH(i));
 625
 626         for (i = 0; i < 4; i++)
 627                 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
 628         for (i = 0; i < 4; i++)
 629                 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
 630         for (i = 0; i < 4; i++)
 631                 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
 632         for (i = 0; i < 4; i++)
 633                 regs_buff[223 + i] = rd32(E1000_TDH(i));
 634         for (i = 0; i < 4; i++)
 635                 regs_buff[227 + i] = rd32(E1000_TDT(i));
 636         for (i = 0; i < 4; i++)
 637                 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
 638         for (i = 0; i < 4; i++)
 639                 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
 640         for (i = 0; i < 4; i++)
 641                 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
 642         for (i = 0; i < 4; i++)
 643                 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
 644
 645         for (i = 0; i < 4; i++)
 646                 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
 647         for (i = 0; i < 4; i++)
 648                 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
 649         for (i = 0; i < 32; i++)
 650                 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
 651         for (i = 0; i < 128; i++)
 652                 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
 653         for (i = 0; i < 128; i++)
 654                 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
 655         for (i = 0; i < 4; i++)
 656                 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
 657
 658         regs_buff[547] = rd32(E1000_TDFH);
 659         regs_buff[548] = rd32(E1000_TDFT);
 660         regs_buff[549] = rd32(E1000_TDFHS);
 661         regs_buff[550] = rd32(E1000_TDFPC);
 662
 663         if (hw->mac.type > e1000_82580) {
 664                 regs_buff[551] = adapter->stats.o2bgptc;
 665                 regs_buff[552] = adapter->stats.b2ospc;
 666                 regs_buff[553] = adapter->stats.o2bspc;
 667                 regs_buff[554] = adapter->stats.b2ogprc;
 668         }
 669
 670         if (hw->mac.type != e1000_82576)
 671                 return;
 672         for (i = 0; i < 12; i++)
 673                 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4));
 674         for (i = 0; i < 4; i++)
 675                 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4));
 676         for (i = 0; i < 12; i++)
 677                 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4));
 678         for (i = 0; i < 12; i++)
 679                 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4));
 680         for (i = 0; i < 12; i++)
 681                 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4));
 682         for (i = 0; i < 12; i++)
 683                 regs_buff[607 + i] = rd32(E1000_RDH(i + 4));
 684         for (i = 0; i < 12; i++)
 685                 regs_buff[619 + i] = rd32(E1000_RDT(i + 4));
 686         for (i = 0; i < 12; i++)
 687                 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4));
 688
 689         for (i = 0; i < 12; i++)
 690                 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4));
 691         for (i = 0; i < 12; i++)
 692                 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4));
 693         for (i = 0; i < 12; i++)
 694                 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4));
 695         for (i = 0; i < 12; i++)
 696                 regs_buff[679 + i] = rd32(E1000_TDH(i + 4));
 697         for (i = 0; i < 12; i++)
 698                 regs_buff[691 + i] = rd32(E1000_TDT(i + 4));
 699         for (i = 0; i < 12; i++)
 700                 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4));
 701         for (i = 0; i < 12; i++)
 702                 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4));
 703         for (i = 0; i < 12; i++)
 704                 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4));
 705 }
 706
 707 static int igb_get_eeprom_len(struct net_device *netdev)
 708 {
 709         struct igb_adapter *adapter = netdev_priv(netdev);
 710         return adapter->hw.nvm.word_size * 2;
 711 }
 712
 713 static int igb_get_eeprom(struct net_device *netdev,
 714                           struct ethtool_eeprom *eeprom, u8 *bytes)
 715 {
 716         struct igb_adapter *adapter = netdev_priv(netdev);
 717         struct e1000_hw *hw = &adapter->hw;
 718         u16 *eeprom_buff;
 719         int first_word, last_word;
 720         int ret_val = 0;
 721         u16 i;
 722
 723         if (eeprom->len == 0)
 724                 return -EINVAL;
 725
 726         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
 727
 728         first_word = eeprom->offset >> 1;
 729         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 730
 731         eeprom_buff = kmalloc(sizeof(u16) *
 732                         (last_word - first_word + 1), GFP_KERNEL);
 733         if (!eeprom_buff)
 734                 return -ENOMEM;
 735
 736         if (hw->nvm.type == e1000_nvm_eeprom_spi)
 737                 ret_val = hw->nvm.ops.read(hw, first_word,
 738                                            last_word - first_word + 1,
 739                                            eeprom_buff);
 740         else {
 741                 for (i = 0; i < last_word - first_word + 1; i++) {
 742                         ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
 743                                                    &eeprom_buff[i]);
 744                         if (ret_val)
 745                                 break;
 746                 }
 747         }
 748
 749         /* Device's eeprom is always little-endian, word addressable */
 750         for (i = 0; i < last_word - first_word + 1; i++)
 751                 le16_to_cpus(&eeprom_buff[i]);
 752
 753         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
 754                         eeprom->len);
 755         kfree(eeprom_buff);
 756
 757         return ret_val;
 758 }
 759
 760 static int igb_set_eeprom(struct net_device *netdev,
 761                           struct ethtool_eeprom *eeprom, u8 *bytes)
 762 {
 763         struct igb_adapter *adapter = netdev_priv(netdev);
 764         struct e1000_hw *hw = &adapter->hw;
 765         u16 *eeprom_buff;
 766         void *ptr;
 767         int max_len, first_word, last_word, ret_val = 0;
 768         u16 i;
 769
 770         if (eeprom->len == 0)
 771                 return -EOPNOTSUPP;
 772
 773         if ((hw->mac.type >= e1000_i210) &&
 774             !igb_get_flash_presence_i210(hw)) {
 775                 return -EOPNOTSUPP;
 776         }
 777
 778         if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
 779                 return -EFAULT;
 780
 781         max_len = hw->nvm.word_size * 2;
 782
 783         first_word = eeprom->offset >> 1;
 784         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 785         eeprom_buff = kmalloc(max_len, GFP_KERNEL);
 786         if (!eeprom_buff)
 787                 return -ENOMEM;
 788
 789         ptr = (void *)eeprom_buff;
 790
 791         if (eeprom->offset & 1) {
 792                 /* need read/modify/write of first changed EEPROM word
 793                  * only the second byte of the word is being modified
 794                  */
 795                 ret_val = hw->nvm.ops.read(hw, first_word, 1,
 796                                             &eeprom_buff[0]);
 797                 ptr++;
 798         }
 799         if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
 800                 /* need read/modify/write of last changed EEPROM word
 801                  * only the first byte of the word is being modified
 802                  */
 803                 ret_val = hw->nvm.ops.read(hw, last_word, 1,
 804                                    &eeprom_buff[last_word - first_word]);
 805         }
 806
 807         /* Device's eeprom is always little-endian, word addressable */
 808         for (i = 0; i < last_word - first_word + 1; i++)
 809                 le16_to_cpus(&eeprom_buff[i]);
 810
 811         memcpy(ptr, bytes, eeprom->len);
 812
 813         for (i = 0; i < last_word - first_word + 1; i++)
 814                 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
 815
 816         ret_val = hw->nvm.ops.write(hw, first_word,
 817                                     last_word - first_word + 1, eeprom_buff);
 818
 819         /* Update the checksum if nvm write succeeded */
 820         if (ret_val == 0)
 821                 hw->nvm.ops.update(hw);
 822
 823         igb_set_fw_version(adapter);
 824         kfree(eeprom_buff);
 825         return ret_val;
 826 }
 827
 828 static void igb_get_drvinfo(struct net_device *netdev,
 829                             struct ethtool_drvinfo *drvinfo)
 830 {
 831         struct igb_adapter *adapter = netdev_priv(netdev);
 832
 833         strlcpy(drvinfo->driver,  igb_driver_name, sizeof(drvinfo->driver));
 834         strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version));
 835
 836         /* EEPROM image version # is reported as firmware version # for
 837          * 82575 controllers
 838          */
 839         strlcpy(drvinfo->fw_version, adapter->fw_version,
 840                 sizeof(drvinfo->fw_version));
 841         strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
 842                 sizeof(drvinfo->bus_info));
 843         drvinfo->n_stats = IGB_STATS_LEN;
 844         drvinfo->testinfo_len = IGB_TEST_LEN;
 845         drvinfo->regdump_len = igb_get_regs_len(netdev);
 846         drvinfo->eedump_len = igb_get_eeprom_len(netdev);
 847 }
 848
 849 static void igb_get_ringparam(struct net_device *netdev,
 850                               struct ethtool_ringparam *ring)
 851 {
 852         struct igb_adapter *adapter = netdev_priv(netdev);
 853
 854         ring->rx_max_pending = IGB_MAX_RXD;
 855         ring->tx_max_pending = IGB_MAX_TXD;
 856         ring->rx_pending = adapter->rx_ring_count;
 857         ring->tx_pending = adapter->tx_ring_count;
 858 }
 859
 860 static int igb_set_ringparam(struct net_device *netdev,
 861                              struct ethtool_ringparam *ring)
 862 {
 863         struct igb_adapter *adapter = netdev_priv(netdev);
 864         struct igb_ring *temp_ring;
 865         int i, err = 0;
 866         u16 new_rx_count, new_tx_count;
 867
 868         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
 869                 return -EINVAL;
 870
 871         new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
 872         new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
 873         new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
 874
 875         new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
 876         new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
 877         new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
 878
 879         if ((new_tx_count == adapter->tx_ring_count) &&
 880             (new_rx_count == adapter->rx_ring_count)) {
 881                 /* nothing to do */
 882                 return 0;
 883         }
 884
 885         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 886                 usleep_range(1000, 2000);
 887
 888         if (!netif_running(adapter->netdev)) {
 889                 for (i = 0; i < adapter->num_tx_queues; i++)
 890                         adapter->tx_ring[i]->count = new_tx_count;
 891                 for (i = 0; i < adapter->num_rx_queues; i++)
 892                         adapter->rx_ring[i]->count = new_rx_count;
 893                 adapter->tx_ring_count = new_tx_count;
 894                 adapter->rx_ring_count = new_rx_count;
 895                 goto clear_reset;
 896         }
 897
 898         if (adapter->num_tx_queues > adapter->num_rx_queues)
 899                 temp_ring = vmalloc(adapter->num_tx_queues *
 900                                     sizeof(struct igb_ring));
 901         else
 902                 temp_ring = vmalloc(adapter->num_rx_queues *
 903                                     sizeof(struct igb_ring));
 904
 905         if (!temp_ring) {
 906                 err = -ENOMEM;
 907                 goto clear_reset;
 908         }
 909
 910         igb_down(adapter);
 911
 912         /* We can't just free everything and then setup again,
 913          * because the ISRs in MSI-X mode get passed pointers
 914          * to the Tx and Rx ring structs.
 915          */
 916         if (new_tx_count != adapter->tx_ring_count) {
 917                 for (i = 0; i < adapter->num_tx_queues; i++) {
 918                         memcpy(&temp_ring[i], adapter->tx_ring[i],
 919                                sizeof(struct igb_ring));
 920
 921                         temp_ring[i].count = new_tx_count;
 922                         err = igb_setup_tx_resources(&temp_ring[i]);
 923                         if (err) {
 924                                 while (i) {
 925                                         i--;
 926                                         igb_free_tx_resources(&temp_ring[i]);
 927                                 }
 928                                 goto err_setup;
 929                         }
 930                 }
 931
 932                 for (i = 0; i < adapter->num_tx_queues; i++) {
 933                         igb_free_tx_resources(adapter->tx_ring[i]);
 934
 935                         memcpy(adapter->tx_ring[i], &temp_ring[i],
 936                                sizeof(struct igb_ring));
 937                 }
 938
 939                 adapter->tx_ring_count = new_tx_count;
 940         }
 941
 942         if (new_rx_count != adapter->rx_ring_count) {
 943                 for (i = 0; i < adapter->num_rx_queues; i++) {
 944                         memcpy(&temp_ring[i], adapter->rx_ring[i],
 945                                sizeof(struct igb_ring));
 946
 947                         temp_ring[i].count = new_rx_count;
 948                         err = igb_setup_rx_resources(&temp_ring[i]);
 949                         if (err) {
 950                                 while (i) {
 951                                         i--;
 952                                         igb_free_rx_resources(&temp_ring[i]);
 953                                 }
 954                                 goto err_setup;
 955                         }
 956
 957                 }
 958
 959                 for (i = 0; i < adapter->num_rx_queues; i++) {
 960                         igb_free_rx_resources(adapter->rx_ring[i]);
 961
 962                         memcpy(adapter->rx_ring[i], &temp_ring[i],
 963                                sizeof(struct igb_ring));
 964                 }
 965
 966                 adapter->rx_ring_count = new_rx_count;
 967         }
 968 err_setup:
 969         igb_up(adapter);
 970         vfree(temp_ring);
 971 clear_reset:
 972         clear_bit(__IGB_RESETTING, &adapter->state);
 973         return err;
 974 }
 975
 976 /* ethtool register test data */
 977 struct igb_reg_test {
 978         u16 reg;
 979         u16 reg_offset;
 980         u16 array_len;
 981         u16 test_type;
 982         u32 mask;
 983         u32 write;
 984 };
 985
 986 /* In the hardware, registers are laid out either singly, in arrays
 987  * spaced 0x100 bytes apart, or in contiguous tables.  We assume
 988  * most tests take place on arrays or single registers (handled
 989  * as a single-element array) and special-case the tables.
 990  * Table tests are always pattern tests.
 991  *
 992  * We also make provision for some required setup steps by specifying
 993  * registers to be written without any read-back testing.
 994  */
 995
 996 #define PATTERN_TEST    1
 997 #define SET_READ_TEST   2
 998 #define WRITE_NO_TEST   3
 999 #define TABLE32_TEST    4
1000 #define TABLE64_TEST_LO 5
1001 #define TABLE64_TEST_HI 6
1002
1003 /* i210 reg test */
1004 static struct igb_reg_test reg_test_i210[] = {
1005         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1006         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1007         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1008         { E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1009         { E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1010         { E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1011         /* RDH is read-only for i210, only test RDT. */
1012         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1013         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1014         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1015         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1016         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1017         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1018         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1019         { E1000_TDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1020         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1021         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1022         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1023         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1024         { E1000_RA,        0, 16, TABLE64_TEST_LO,
1025                                                 0xFFFFFFFF, 0xFFFFFFFF },
1026         { E1000_RA,        0, 16, TABLE64_TEST_HI,
1027                                                 0x900FFFFF, 0xFFFFFFFF },
1028         { E1000_MTA,       0, 128, TABLE32_TEST,
1029                                                 0xFFFFFFFF, 0xFFFFFFFF },
1030         { 0, 0, 0, 0, 0 }
1031 };
1032
1033 /* i350 reg test */
1034 static struct igb_reg_test reg_test_i350[] = {
1035         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1036         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1037         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1038         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
1039         { E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1040         { E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1041         { E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1042         { E1000_RDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1043         { E1000_RDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1044         { E1000_RDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1045         /* RDH is read-only for i350, only test RDT. */
1046         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1047         { E1000_RDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1048         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1049         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1050         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1051         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1052         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1053         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1054         { E1000_TDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1055         { E1000_TDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1056         { E1000_TDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1057         { E1000_TDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1058         { E1000_TDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1059         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1060         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1061         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1062         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1063         { E1000_RA,        0, 16, TABLE64_TEST_LO,
1064                                                 0xFFFFFFFF, 0xFFFFFFFF },
1065         { E1000_RA,        0, 16, TABLE64_TEST_HI,
1066                                                 0xC3FFFFFF, 0xFFFFFFFF },
1067         { E1000_RA2,       0, 16, TABLE64_TEST_LO,
1068                                                 0xFFFFFFFF, 0xFFFFFFFF },
1069         { E1000_RA2,       0, 16, TABLE64_TEST_HI,
1070                                                 0xC3FFFFFF, 0xFFFFFFFF },
1071         { E1000_MTA,       0, 128, TABLE32_TEST,
1072                                                 0xFFFFFFFF, 0xFFFFFFFF },
1073         { 0, 0, 0, 0 }
1074 };
1075
1076 /* 82580 reg test */
1077 static struct igb_reg_test reg_test_82580[] = {
1078         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1079         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1080         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1081         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1082         { E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1083         { E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1084         { E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1085         { E1000_RDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1086         { E1000_RDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1087         { E1000_RDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1088         /* RDH is read-only for 82580, only test RDT. */
1089         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1090         { E1000_RDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1091         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1092         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1093         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1094         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1095         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1096         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1097         { E1000_TDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1098         { E1000_TDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1099         { E1000_TDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1100         { E1000_TDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1101         { E1000_TDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1102         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1103         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1104         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1105         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1106         { E1000_RA,        0, 16, TABLE64_TEST_LO,
1107                                                 0xFFFFFFFF, 0xFFFFFFFF },
1108         { E1000_RA,        0, 16, TABLE64_TEST_HI,
1109                                                 0x83FFFFFF, 0xFFFFFFFF },
1110         { E1000_RA2,       0, 8, TABLE64_TEST_LO,
1111                                                 0xFFFFFFFF, 0xFFFFFFFF },
1112         { E1000_RA2,       0, 8, TABLE64_TEST_HI,
1113                                                 0x83FFFFFF, 0xFFFFFFFF },
1114         { E1000_MTA,       0, 128, TABLE32_TEST,
1115                                                 0xFFFFFFFF, 0xFFFFFFFF },
1116         { 0, 0, 0, 0 }
1117 };
1118
1119 /* 82576 reg test */
1120 static struct igb_reg_test reg_test_82576[] = {
1121         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1122         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1123         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1124         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1125         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1126         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1127         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1128         { E1000_RDBAL(4),  0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1129         { E1000_RDBAH(4),  0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1130         { E1000_RDLEN(4),  0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1131         /* Enable all RX queues before testing. */
1132         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1133           E1000_RXDCTL_QUEUE_ENABLE },
1134         { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0,
1135           E1000_RXDCTL_QUEUE_ENABLE },
1136         /* RDH is read-only for 82576, only test RDT. */
1137         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1138         { E1000_RDT(4),    0x40, 12,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1139         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, 0 },
1140         { E1000_RXDCTL(4), 0x40, 12,  WRITE_NO_TEST, 0, 0 },
1141         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1142         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1143         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1144         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1145         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1146         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1147         { E1000_TDBAL(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1148         { E1000_TDBAH(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1149         { E1000_TDLEN(4),  0x40, 12,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1150         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1151         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1152         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1153         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1154         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1155         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1156         { E1000_RA2,       0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1157         { E1000_RA2,       0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1158         { E1000_MTA,       0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1159         { 0, 0, 0, 0 }
1160 };
1161
1162 /* 82575 register test */
1163 static struct igb_reg_test reg_test_82575[] = {
1164         { E1000_FCAL,      0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1165         { E1000_FCAH,      0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1166         { E1000_FCT,       0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1167         { E1000_VET,       0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1168         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1169         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1170         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1171         /* Enable all four RX queues before testing. */
1172         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1173           E1000_RXDCTL_QUEUE_ENABLE },
1174         /* RDH is read-only for 82575, only test RDT. */
1175         { E1000_RDT(0),    0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1176         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1177         { E1000_FCRTH,     0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1178         { E1000_FCTTV,     0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1179         { E1000_TIPG,      0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1180         { E1000_TDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1181         { E1000_TDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1182         { E1000_TDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1183         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1184         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1185         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1186         { E1000_TCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1187         { E1000_TXCW,      0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1188         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1189         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1190         { E1000_MTA,       0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1191         { 0, 0, 0, 0 }
1192 };
1193
1194 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1195                              int reg, u32 mask, u32 write)
1196 {
1197         struct e1000_hw *hw = &adapter->hw;
1198         u32 pat, val;
1199         static const u32 _test[] = {
1200                 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1201         for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
1202                 wr32(reg, (_test[pat] & write));
1203                 val = rd32(reg) & mask;
1204                 if (val != (_test[pat] & write & mask)) {
1205                         dev_err(&adapter->pdev->dev,
1206                                 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
1207                                 reg, val, (_test[pat] & write & mask));
1208                         *data = reg;
1209                         return true;
1210                 }
1211         }
1212
1213         return false;
1214 }
1215
1216 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1217                               int reg, u32 mask, u32 write)
1218 {
1219         struct e1000_hw *hw = &adapter->hw;
1220         u32 val;
1221
1222         wr32(reg, write & mask);
1223         val = rd32(reg);
1224         if ((write & mask) != (val & mask)) {
1225                 dev_err(&adapter->pdev->dev,
1226                         "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
1227                         reg, (val & mask), (write & mask));
1228                 *data = reg;
1229                 return true;
1230         }
1231
1232         return false;
1233 }
1234
1235 #define REG_PATTERN_TEST(reg, mask, write) \
1236         do { \
1237                 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1238                         return 1; \
1239         } while (0)
1240
1241 #define REG_SET_AND_CHECK(reg, mask, write) \
1242         do { \
1243                 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1244                         return 1; \
1245         } while (0)
1246
1247 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1248 {
1249         struct e1000_hw *hw = &adapter->hw;
1250         struct igb_reg_test *test;
1251         u32 value, before, after;
1252         u32 i, toggle;
1253
1254         switch (adapter->hw.mac.type) {
1255         case e1000_i350:
1256         case e1000_i354:
1257                 test = reg_test_i350;
1258                 toggle = 0x7FEFF3FF;
1259                 break;
1260         case e1000_i210:
1261         case e1000_i211:
1262                 test = reg_test_i210;
1263                 toggle = 0x7FEFF3FF;
1264                 break;
1265         case e1000_82580:
1266                 test = reg_test_82580;
1267                 toggle = 0x7FEFF3FF;
1268                 break;
1269         case e1000_82576:
1270                 test = reg_test_82576;
1271                 toggle = 0x7FFFF3FF;
1272                 break;
1273         default:
1274                 test = reg_test_82575;
1275                 toggle = 0x7FFFF3FF;
1276                 break;
1277         }
1278
1279         /* Because the status register is such a special case,
1280          * we handle it separately from the rest of the register
1281          * tests.  Some bits are read-only, some toggle, and some
1282          * are writable on newer MACs.
1283          */
1284         before = rd32(E1000_STATUS);
1285         value = (rd32(E1000_STATUS) & toggle);
1286         wr32(E1000_STATUS, toggle);
1287         after = rd32(E1000_STATUS) & toggle;
1288         if (value != after) {
1289                 dev_err(&adapter->pdev->dev,
1290                         "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1291                         after, value);
1292                 *data = 1;
1293                 return 1;
1294         }
1295         /* restore previous status */
1296         wr32(E1000_STATUS, before);
1297
1298         /* Perform the remainder of the register test, looping through
1299          * the test table until we either fail or reach the null entry.
1300          */
1301         while (test->reg) {
1302                 for (i = 0; i < test->array_len; i++) {
1303                         switch (test->test_type) {
1304                         case PATTERN_TEST:
1305                                 REG_PATTERN_TEST(test->reg +
1306                                                 (i * test->reg_offset),
1307                                                 test->mask,
1308                                                 test->write);
1309                                 break;
1310                         case SET_READ_TEST:
1311                                 REG_SET_AND_CHECK(test->reg +
1312                                                 (i * test->reg_offset),
1313                                                 test->mask,
1314                                                 test->write);
1315                                 break;
1316                         case WRITE_NO_TEST:
1317                                 writel(test->write,
1318                                     (adapter->hw.hw_addr + test->reg)
1319                                         + (i * test->reg_offset));
1320                                 break;
1321                         case TABLE32_TEST:
1322                                 REG_PATTERN_TEST(test->reg + (i * 4),
1323                                                 test->mask,
1324                                                 test->write);
1325                                 break;
1326                         case TABLE64_TEST_LO:
1327                                 REG_PATTERN_TEST(test->reg + (i * 8),
1328                                                 test->mask,
1329                                                 test->write);
1330                                 break;
1331                         case TABLE64_TEST_HI:
1332                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1333                                                 test->mask,
1334                                                 test->write);
1335                                 break;
1336                         }
1337                 }
1338                 test++;
1339         }
1340
1341         *data = 0;
1342         return 0;
1343 }
1344
1345 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1346 {
1347         struct e1000_hw *hw = &adapter->hw;
1348
1349         *data = 0;
1350
1351         /* Validate eeprom on all parts but flashless */
1352         switch (hw->mac.type) {
1353         case e1000_i210:
1354         case e1000_i211:
1355                 if (igb_get_flash_presence_i210(hw)) {
1356                         if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1357                                 *data = 2;
1358                 }
1359                 break;
1360         default:
1361                 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1362                         *data = 2;
1363                 break;
1364         }
1365
1366         return *data;
1367 }
1368
1369 static irqreturn_t igb_test_intr(int irq, void *data)
1370 {
1371         struct igb_adapter *adapter = (struct igb_adapter *) data;
1372         struct e1000_hw *hw = &adapter->hw;
1373
1374         adapter->test_icr |= rd32(E1000_ICR);
1375
1376         return IRQ_HANDLED;
1377 }
1378
1379 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1380 {
1381         struct e1000_hw *hw = &adapter->hw;
1382         struct net_device *netdev = adapter->netdev;
1383         u32 mask, ics_mask, i = 0, shared_int = true;
1384         u32 irq = adapter->pdev->irq;
1385
1386         *data = 0;
1387
1388         /* Hook up test interrupt handler just for this test */
1389         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1390                 if (request_irq(adapter->msix_entries[0].vector,
1391                                 igb_test_intr, 0, netdev->name, adapter)) {
1392                         *data = 1;
1393                         return -1;
1394                 }
1395         } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1396                 shared_int = false;
1397                 if (request_irq(irq,
1398                                 igb_test_intr, 0, netdev->name, adapter)) {
1399                         *data = 1;
1400                         return -1;
1401                 }
1402         } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
1403                                 netdev->name, adapter)) {
1404                 shared_int = false;
1405         } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
1406                  netdev->name, adapter)) {
1407                 *data = 1;
1408                 return -1;
1409         }
1410         dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1411                 (shared_int ? "shared" : "unshared"));
1412
1413         /* Disable all the interrupts */
1414         wr32(E1000_IMC, ~0);
1415         wrfl();
1416         usleep_range(10000, 11000);
1417
1418         /* Define all writable bits for ICS */
1419         switch (hw->mac.type) {
1420         case e1000_82575:
1421                 ics_mask = 0x37F47EDD;
1422                 break;
1423         case e1000_82576:
1424                 ics_mask = 0x77D4FBFD;
1425                 break;
1426         case e1000_82580:
1427                 ics_mask = 0x77DCFED5;
1428                 break;
1429         case e1000_i350:
1430         case e1000_i354:
1431         case e1000_i210:
1432         case e1000_i211:
1433                 ics_mask = 0x77DCFED5;
1434                 break;
1435         default:
1436                 ics_mask = 0x7FFFFFFF;
1437                 break;
1438         }
1439
1440         /* Test each interrupt */
1441         for (; i < 31; i++) {
1442                 /* Interrupt to test */
1443                 mask = 1 << i;
1444
1445                 if (!(mask & ics_mask))
1446                         continue;
1447
1448                 if (!shared_int) {
1449                         /* Disable the interrupt to be reported in
1450                          * the cause register and then force the same
1451                          * interrupt and see if one gets posted.  If
1452                          * an interrupt was posted to the bus, the
1453                          * test failed.
1454                          */
1455                         adapter->test_icr = 0;
1456
1457                         /* Flush any pending interrupts */
1458                         wr32(E1000_ICR, ~0);
1459
1460                         wr32(E1000_IMC, mask);
1461                         wr32(E1000_ICS, mask);
1462                         wrfl();
1463                         usleep_range(10000, 11000);
1464
1465                         if (adapter->test_icr & mask) {
1466                                 *data = 3;
1467                                 break;
1468                         }
1469                 }
1470
1471                 /* Enable the interrupt to be reported in
1472                  * the cause register and then force the same
1473                  * interrupt and see if one gets posted.  If
1474                  * an interrupt was not posted to the bus, the
1475                  * test failed.
1476                  */
1477                 adapter->test_icr = 0;
1478
1479                 /* Flush any pending interrupts */
1480                 wr32(E1000_ICR, ~0);
1481
1482                 wr32(E1000_IMS, mask);
1483                 wr32(E1000_ICS, mask);
1484                 wrfl();
1485                 usleep_range(10000, 11000);
1486
1487                 if (!(adapter->test_icr & mask)) {
1488                         *data = 4;
1489                         break;
1490                 }
1491
1492                 if (!shared_int) {
1493                         /* Disable the other interrupts to be reported in
1494                          * the cause register and then force the other
1495                          * interrupts and see if any get posted.  If
1496                          * an interrupt was posted to the bus, the
1497                          * test failed.
1498                          */
1499                         adapter->test_icr = 0;
1500
1501                         /* Flush any pending interrupts */
1502                         wr32(E1000_ICR, ~0);
1503
1504                         wr32(E1000_IMC, ~mask);
1505                         wr32(E1000_ICS, ~mask);
1506                         wrfl();
1507                         usleep_range(10000, 11000);
1508
1509                         if (adapter->test_icr & mask) {
1510                                 *data = 5;
1511                                 break;
1512                         }
1513                 }
1514         }
1515
1516         /* Disable all the interrupts */
1517         wr32(E1000_IMC, ~0);
1518         wrfl();
1519         usleep_range(10000, 11000);
1520
1521         /* Unhook test interrupt handler */
1522         if (adapter->flags & IGB_FLAG_HAS_MSIX)
1523                 free_irq(adapter->msix_entries[0].vector, adapter);
1524         else
1525                 free_irq(irq, adapter);
1526
1527         return *data;
1528 }
1529
1530 static void igb_free_desc_rings(struct igb_adapter *adapter)
1531 {
1532         igb_free_tx_resources(&adapter->test_tx_ring);
1533         igb_free_rx_resources(&adapter->test_rx_ring);
1534 }
1535
1536 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1537 {
1538         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1539         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1540         struct e1000_hw *hw = &adapter->hw;
1541         int ret_val;
1542
1543         /* Setup Tx descriptor ring and Tx buffers */
1544         tx_ring->count = IGB_DEFAULT_TXD;
1545         tx_ring->dev = &adapter->pdev->dev;
1546         tx_ring->netdev = adapter->netdev;
1547         tx_ring->reg_idx = adapter->vfs_allocated_count;
1548
1549         if (igb_setup_tx_resources(tx_ring)) {
1550                 ret_val = 1;
1551                 goto err_nomem;
1552         }
1553
1554         igb_setup_tctl(adapter);
1555         igb_configure_tx_ring(adapter, tx_ring);
1556
1557         /* Setup Rx descriptor ring and Rx buffers */
1558         rx_ring->count = IGB_DEFAULT_RXD;
1559         rx_ring->dev = &adapter->pdev->dev;
1560         rx_ring->netdev = adapter->netdev;
1561         rx_ring->reg_idx = adapter->vfs_allocated_count;
1562
1563         if (igb_setup_rx_resources(rx_ring)) {
1564                 ret_val = 3;
1565                 goto err_nomem;
1566         }
1567
1568         /* set the default queue to queue 0 of PF */
1569         wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
1570
1571         /* enable receive ring */
1572         igb_setup_rctl(adapter);
1573         igb_configure_rx_ring(adapter, rx_ring);
1574
1575         igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));
1576
1577         return 0;
1578
1579 err_nomem:
1580         igb_free_desc_rings(adapter);
1581         return ret_val;
1582 }
1583
1584 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1585 {
1586         struct e1000_hw *hw = &adapter->hw;
1587
1588         /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1589         igb_write_phy_reg(hw, 29, 0x001F);
1590         igb_write_phy_reg(hw, 30, 0x8FFC);
1591         igb_write_phy_reg(hw, 29, 0x001A);
1592         igb_write_phy_reg(hw, 30, 0x8FF0);
1593 }
1594
1595 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1596 {
1597         struct e1000_hw *hw = &adapter->hw;
1598         u32 ctrl_reg = 0;
1599
1600         hw->mac.autoneg = false;
1601
1602         if (hw->phy.type == e1000_phy_m88) {
1603                 if (hw->phy.id != I210_I_PHY_ID) {
1604                         /* Auto-MDI/MDIX Off */
1605                         igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1606                         /* reset to update Auto-MDI/MDIX */
1607                         igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1608                         /* autoneg off */
1609                         igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1610                 } else {
1611                         /* force 1000, set loopback  */
1612                         igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0);
1613                         igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1614                 }
1615         } else if (hw->phy.type == e1000_phy_82580) {
1616                 /* enable MII loopback */
1617                 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
1618         }
1619
1620         /* add small delay to avoid loopback test failure */
1621         msleep(50);
1622
1623         /* force 1000, set loopback */
1624         igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1625
1626         /* Now set up the MAC to the same speed/duplex as the PHY. */
1627         ctrl_reg = rd32(E1000_CTRL);
1628         ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1629         ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1630                      E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1631                      E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1632                      E1000_CTRL_FD |     /* Force Duplex to FULL */
1633                      E1000_CTRL_SLU);    /* Set link up enable bit */
1634
1635         if (hw->phy.type == e1000_phy_m88)
1636                 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1637
1638         wr32(E1000_CTRL, ctrl_reg);
1639
1640         /* Disable the receiver on the PHY so when a cable is plugged in, the
1641          * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1642          */
1643         if (hw->phy.type == e1000_phy_m88)
1644                 igb_phy_disable_receiver(adapter);
1645
1646         mdelay(500);
1647         return 0;
1648 }
1649
1650 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1651 {
1652         return igb_integrated_phy_loopback(adapter);
1653 }
1654
1655 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1656 {
1657         struct e1000_hw *hw = &adapter->hw;
1658         u32 reg;
1659
1660         reg = rd32(E1000_CTRL_EXT);
1661
1662         /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1663         if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
1664                 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1665                 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1666                 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1667                 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1668                 (hw->device_id == E1000_DEV_ID_I354_SGMII) ||
1669                 (hw->device_id == E1000_DEV_ID_I354_BACKPLANE_2_5GBPS)) {
1670                         /* Enable DH89xxCC MPHY for near end loopback */
1671                         reg = rd32(E1000_MPHY_ADDR_CTL);
1672                         reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1673                         E1000_MPHY_PCS_CLK_REG_OFFSET;
1674                         wr32(E1000_MPHY_ADDR_CTL, reg);
1675
1676                         reg = rd32(E1000_MPHY_DATA);
1677                         reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1678                         wr32(E1000_MPHY_DATA, reg);
1679                 }
1680
1681                 reg = rd32(E1000_RCTL);
1682                 reg |= E1000_RCTL_LBM_TCVR;
1683                 wr32(E1000_RCTL, reg);
1684
1685                 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1686
1687                 reg = rd32(E1000_CTRL);
1688                 reg &= ~(E1000_CTRL_RFCE |
1689                          E1000_CTRL_TFCE |
1690                          E1000_CTRL_LRST);
1691                 reg |= E1000_CTRL_SLU |
1692                        E1000_CTRL_FD;
1693                 wr32(E1000_CTRL, reg);
1694
1695                 /* Unset switch control to serdes energy detect */
1696                 reg = rd32(E1000_CONNSW);
1697                 reg &= ~E1000_CONNSW_ENRGSRC;
1698                 wr32(E1000_CONNSW, reg);
1699
1700                 /* Unset sigdetect for SERDES loopback on
1701                  * 82580 and newer devices.
1702                  */
1703                 if (hw->mac.type >= e1000_82580) {
1704                         reg = rd32(E1000_PCS_CFG0);
1705                         reg |= E1000_PCS_CFG_IGN_SD;
1706                         wr32(E1000_PCS_CFG0, reg);
1707                 }
1708
1709                 /* Set PCS register for forced speed */
1710                 reg = rd32(E1000_PCS_LCTL);
1711                 reg &= ~E1000_PCS_LCTL_AN_ENABLE;     /* Disable Autoneg*/
1712                 reg |= E1000_PCS_LCTL_FLV_LINK_UP |   /* Force link up */
1713                        E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
1714                        E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
1715                        E1000_PCS_LCTL_FSD |           /* Force Speed */
1716                        E1000_PCS_LCTL_FORCE_LINK;     /* Force Link */
1717                 wr32(E1000_PCS_LCTL, reg);
1718
1719                 return 0;
1720         }
1721
1722         return igb_set_phy_loopback(adapter);
1723 }
1724
1725 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1726 {
1727         struct e1000_hw *hw = &adapter->hw;
1728         u32 rctl;
1729         u16 phy_reg;
1730
1731         if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1732         (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1733         (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1734         (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1735         (hw->device_id == E1000_DEV_ID_I354_SGMII)) {
1736                 u32 reg;
1737
1738                 /* Disable near end loopback on DH89xxCC */
1739                 reg = rd32(E1000_MPHY_ADDR_CTL);
1740                 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1741                 E1000_MPHY_PCS_CLK_REG_OFFSET;
1742                 wr32(E1000_MPHY_ADDR_CTL, reg);
1743
1744                 reg = rd32(E1000_MPHY_DATA);
1745                 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1746                 wr32(E1000_MPHY_DATA, reg);
1747         }
1748
1749         rctl = rd32(E1000_RCTL);
1750         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1751         wr32(E1000_RCTL, rctl);
1752
1753         hw->mac.autoneg = true;
1754         igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1755         if (phy_reg & MII_CR_LOOPBACK) {
1756                 phy_reg &= ~MII_CR_LOOPBACK;
1757                 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1758                 igb_phy_sw_reset(hw);
1759         }
1760 }
1761
1762 static void igb_create_lbtest_frame(struct sk_buff *skb,
1763                                     unsigned int frame_size)
1764 {
1765         memset(skb->data, 0xFF, frame_size);
1766         frame_size /= 2;
1767         memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1768         memset(&skb->data[frame_size + 10], 0xBE, 1);
1769         memset(&skb->data[frame_size + 12], 0xAF, 1);
1770 }
1771
1772 static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer,
1773                                   unsigned int frame_size)
1774 {
1775         unsigned char *data;
1776         bool match = true;
1777
1778         frame_size >>= 1;
1779
1780         data = kmap(rx_buffer->page);
1781
1782         if (data[3] != 0xFF ||
1783             data[frame_size + 10] != 0xBE ||
1784             data[frame_size + 12] != 0xAF)
1785                 match = false;
1786
1787         kunmap(rx_buffer->page);
1788
1789         return match;
1790 }
1791
1792 static int igb_clean_test_rings(struct igb_ring *rx_ring,
1793                                 struct igb_ring *tx_ring,
1794                                 unsigned int size)
1795 {
1796         union e1000_adv_rx_desc *rx_desc;
1797         struct igb_rx_buffer *rx_buffer_info;
1798         struct igb_tx_buffer *tx_buffer_info;
1799         u16 rx_ntc, tx_ntc, count = 0;
1800
1801         /* initialize next to clean and descriptor values */
1802         rx_ntc = rx_ring->next_to_clean;
1803         tx_ntc = tx_ring->next_to_clean;
1804         rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1805
1806         while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) {
1807                 /* check Rx buffer */
1808                 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1809
1810                 /* sync Rx buffer for CPU read */
1811                 dma_sync_single_for_cpu(rx_ring->dev,
1812                                         rx_buffer_info->dma,
1813                                         IGB_RX_BUFSZ,
1814                                         DMA_FROM_DEVICE);
1815
1816                 /* verify contents of skb */
1817                 if (igb_check_lbtest_frame(rx_buffer_info, size))
1818                         count++;
1819
1820                 /* sync Rx buffer for device write */
1821                 dma_sync_single_for_device(rx_ring->dev,
1822                                            rx_buffer_info->dma,
1823                                            IGB_RX_BUFSZ,
1824                                            DMA_FROM_DEVICE);
1825
1826                 /* unmap buffer on Tx side */
1827                 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1828                 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
1829
1830                 /* increment Rx/Tx next to clean counters */
1831                 rx_ntc++;
1832                 if (rx_ntc == rx_ring->count)
1833                         rx_ntc = 0;
1834                 tx_ntc++;
1835                 if (tx_ntc == tx_ring->count)
1836                         tx_ntc = 0;
1837
1838                 /* fetch next descriptor */
1839                 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1840         }
1841
1842         netdev_tx_reset_queue(txring_txq(tx_ring));
1843
1844         /* re-map buffers to ring, store next to clean values */
1845         igb_alloc_rx_buffers(rx_ring, count);
1846         rx_ring->next_to_clean = rx_ntc;
1847         tx_ring->next_to_clean = tx_ntc;
1848
1849         return count;
1850 }
1851
1852 static int igb_run_loopback_test(struct igb_adapter *adapter)
1853 {
1854         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1855         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1856         u16 i, j, lc, good_cnt;
1857         int ret_val = 0;
1858         unsigned int size = IGB_RX_HDR_LEN;
1859         netdev_tx_t tx_ret_val;
1860         struct sk_buff *skb;
1861
1862         /* allocate test skb */
1863         skb = alloc_skb(size, GFP_KERNEL);
1864         if (!skb)
1865                 return 11;
1866
1867         /* place data into test skb */
1868         igb_create_lbtest_frame(skb, size);
1869         skb_put(skb, size);
1870
1871         /* Calculate the loop count based on the largest descriptor ring
1872          * The idea is to wrap the largest ring a number of times using 64
1873          * send/receive pairs during each loop
1874          */
1875
1876         if (rx_ring->count <= tx_ring->count)
1877                 lc = ((tx_ring->count / 64) * 2) + 1;
1878         else
1879                 lc = ((rx_ring->count / 64) * 2) + 1;
1880
1881         for (j = 0; j <= lc; j++) { /* loop count loop */
1882                 /* reset count of good packets */
1883                 good_cnt = 0;
1884
1885                 /* place 64 packets on the transmit queue*/
1886                 for (i = 0; i < 64; i++) {
1887                         skb_get(skb);
1888                         tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);
1889                         if (tx_ret_val == NETDEV_TX_OK)
1890                                 good_cnt++;
1891                 }
1892
1893                 if (good_cnt != 64) {
1894                         ret_val = 12;
1895                         break;
1896                 }
1897
1898                 /* allow 200 milliseconds for packets to go from Tx to Rx */
1899                 msleep(200);
1900
1901                 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1902                 if (good_cnt != 64) {
1903                         ret_val = 13;
1904                         break;
1905                 }
1906         } /* end loop count loop */
1907
1908         /* free the original skb */
1909         kfree_skb(skb);
1910
1911         return ret_val;
1912 }
1913
1914 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1915 {
1916         /* PHY loopback cannot be performed if SoL/IDER
1917          * sessions are active
1918          */
1919         if (igb_check_reset_block(&adapter->hw)) {
1920                 dev_err(&adapter->pdev->dev,
1921                         "Cannot do PHY loopback test when SoL/IDER is active.\n");
1922                 *data = 0;
1923                 goto out;
1924         }
1925
1926         if (adapter->hw.mac.type == e1000_i354) {
1927                 dev_info(&adapter->pdev->dev,
1928                         "Loopback test not supported on i354.\n");
1929                 *data = 0;
1930                 goto out;
1931         }
1932         *data = igb_setup_desc_rings(adapter);
1933         if (*data)
1934                 goto out;
1935         *data = igb_setup_loopback_test(adapter);
1936         if (*data)
1937                 goto err_loopback;
1938         *data = igb_run_loopback_test(adapter);
1939         igb_loopback_cleanup(adapter);
1940
1941 err_loopback:
1942         igb_free_desc_rings(adapter);
1943 out:
1944         return *data;
1945 }
1946
1947 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1948 {
1949         struct e1000_hw *hw = &adapter->hw;
1950         *data = 0;
1951         if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1952                 int i = 0;
1953
1954                 hw->mac.serdes_has_link = false;
1955
1956                 /* On some blade server designs, link establishment
1957                  * could take as long as 2-3 minutes
1958                  */
1959                 do {
1960                         hw->mac.ops.check_for_link(&adapter->hw);
1961                         if (hw->mac.serdes_has_link)
1962                                 return *data;
1963                         msleep(20);
1964                 } while (i++ < 3750);
1965
1966                 *data = 1;
1967         } else {
1968                 hw->mac.ops.check_for_link(&adapter->hw);
1969                 if (hw->mac.autoneg)
1970                         msleep(5000);
1971
1972                 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
1973                         *data = 1;
1974         }
1975         return *data;
1976 }
1977
1978 static void igb_diag_test(struct net_device *netdev,
1979                           struct ethtool_test *eth_test, u64 *data)
1980 {
1981         struct igb_adapter *adapter = netdev_priv(netdev);
1982         u16 autoneg_advertised;
1983         u8 forced_speed_duplex, autoneg;
1984         bool if_running = netif_running(netdev);
1985
1986         set_bit(__IGB_TESTING, &adapter->state);
1987
1988         /* can't do offline tests on media switching devices */
1989         if (adapter->hw.dev_spec._82575.mas_capable)
1990                 eth_test->flags &= ~ETH_TEST_FL_OFFLINE;
1991         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1992                 /* Offline tests */
1993
1994                 /* save speed, duplex, autoneg settings */
1995                 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1996                 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1997                 autoneg = adapter->hw.mac.autoneg;
1998
1999                 dev_info(&adapter->pdev->dev, "offline testing starting\n");
2000
2001                 /* power up link for link test */
2002                 igb_power_up_link(adapter);
2003
2004                 /* Link test performed before hardware reset so autoneg doesn't
2005                  * interfere with test result
2006                  */
2007                 if (igb_link_test(adapter, &data[4]))
2008                         eth_test->flags |= ETH_TEST_FL_FAILED;
2009
2010                 if (if_running)
2011                         /* indicate we're in test mode */
2012                         dev_close(netdev);
2013                 else
2014                         igb_reset(adapter);
2015
2016                 if (igb_reg_test(adapter, &data[0]))
2017                         eth_test->flags |= ETH_TEST_FL_FAILED;
2018
2019                 igb_reset(adapter);
2020                 if (igb_eeprom_test(adapter, &data[1]))
2021                         eth_test->flags |= ETH_TEST_FL_FAILED;
2022
2023                 igb_reset(adapter);
2024                 if (igb_intr_test(adapter, &data[2]))
2025                         eth_test->flags |= ETH_TEST_FL_FAILED;
2026
2027                 igb_reset(adapter);
2028                 /* power up link for loopback test */
2029                 igb_power_up_link(adapter);
2030                 if (igb_loopback_test(adapter, &data[3]))
2031                         eth_test->flags |= ETH_TEST_FL_FAILED;
2032
2033                 /* restore speed, duplex, autoneg settings */
2034                 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
2035                 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
2036                 adapter->hw.mac.autoneg = autoneg;
2037
2038                 /* force this routine to wait until autoneg complete/timeout */
2039                 adapter->hw.phy.autoneg_wait_to_complete = true;
2040                 igb_reset(adapter);
2041                 adapter->hw.phy.autoneg_wait_to_complete = false;
2042
2043                 clear_bit(__IGB_TESTING, &adapter->state);
2044                 if (if_running)
2045                         dev_open(netdev);
2046         } else {
2047                 dev_info(&adapter->pdev->dev, "online testing starting\n");
2048
2049                 /* PHY is powered down when interface is down */
2050                 if (if_running && igb_link_test(adapter, &data[4]))
2051                         eth_test->flags |= ETH_TEST_FL_FAILED;
2052                 else
2053                         data[4] = 0;
2054
2055                 /* Online tests aren't run; pass by default */
2056                 data[0] = 0;
2057                 data[1] = 0;
2058                 data[2] = 0;
2059                 data[3] = 0;
2060
2061                 clear_bit(__IGB_TESTING, &adapter->state);
2062         }
2063         msleep_interruptible(4 * 1000);
2064 }
2065
2066 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2067 {
2068         struct igb_adapter *adapter = netdev_priv(netdev);
2069
2070         wol->wolopts = 0;
2071
2072         if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2073                 return;
2074
2075         wol->supported = WAKE_UCAST | WAKE_MCAST |
2076                          WAKE_BCAST | WAKE_MAGIC |
2077                          WAKE_PHY;
2078
2079         /* apply any specific unsupported masks here */
2080         switch (adapter->hw.device_id) {
2081         default:
2082                 break;
2083         }
2084
2085         if (adapter->wol & E1000_WUFC_EX)
2086                 wol->wolopts |= WAKE_UCAST;
2087         if (adapter->wol & E1000_WUFC_MC)
2088                 wol->wolopts |= WAKE_MCAST;
2089         if (adapter->wol & E1000_WUFC_BC)
2090                 wol->wolopts |= WAKE_BCAST;
2091         if (adapter->wol & E1000_WUFC_MAG)
2092                 wol->wolopts |= WAKE_MAGIC;
2093         if (adapter->wol & E1000_WUFC_LNKC)
2094                 wol->wolopts |= WAKE_PHY;
2095 }
2096
2097 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2098 {
2099         struct igb_adapter *adapter = netdev_priv(netdev);
2100
2101         if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2102                 return -EOPNOTSUPP;
2103
2104         if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2105                 return wol->wolopts ? -EOPNOTSUPP : 0;
2106
2107         /* these settings will always override what we currently have */
2108         adapter->wol = 0;
2109
2110         if (wol->wolopts & WAKE_UCAST)
2111                 adapter->wol |= E1000_WUFC_EX;
2112         if (wol->wolopts & WAKE_MCAST)
2113                 adapter->wol |= E1000_WUFC_MC;
2114         if (wol->wolopts & WAKE_BCAST)
2115                 adapter->wol |= E1000_WUFC_BC;
2116         if (wol->wolopts & WAKE_MAGIC)
2117                 adapter->wol |= E1000_WUFC_MAG;
2118         if (wol->wolopts & WAKE_PHY)
2119                 adapter->wol |= E1000_WUFC_LNKC;
2120         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2121
2122         return 0;
2123 }
2124
2125 /* bit defines for adapter->led_status */
2126 #define IGB_LED_ON              0
2127
2128 static int igb_set_phys_id(struct net_device *netdev,
2129                            enum ethtool_phys_id_state state)
2130 {
2131         struct igb_adapter *adapter = netdev_priv(netdev);
2132         struct e1000_hw *hw = &adapter->hw;
2133
2134         switch (state) {
2135         case ETHTOOL_ID_ACTIVE:
2136                 igb_blink_led(hw);
2137                 return 2;
2138         case ETHTOOL_ID_ON:
2139                 igb_blink_led(hw);
2140                 break;
2141         case ETHTOOL_ID_OFF:
2142                 igb_led_off(hw);
2143                 break;
2144         case ETHTOOL_ID_INACTIVE:
2145                 igb_led_off(hw);
2146                 clear_bit(IGB_LED_ON, &adapter->led_status);
2147                 igb_cleanup_led(hw);
2148                 break;
2149         }
2150
2151         return 0;
2152 }
2153
2154 static int igb_set_coalesce(struct net_device *netdev,
2155                             struct ethtool_coalesce *ec)
2156 {
2157         struct igb_adapter *adapter = netdev_priv(netdev);
2158         int i;
2159
2160         if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2161             ((ec->rx_coalesce_usecs > 3) &&
2162              (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2163             (ec->rx_coalesce_usecs == 2))
2164                 return -EINVAL;
2165
2166         if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2167             ((ec->tx_coalesce_usecs > 3) &&
2168              (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2169             (ec->tx_coalesce_usecs == 2))
2170                 return -EINVAL;
2171
2172         if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2173                 return -EINVAL;
2174
2175         /* If ITR is disabled, disable DMAC */
2176         if (ec->rx_coalesce_usecs == 0) {
2177                 if (adapter->flags & IGB_FLAG_DMAC)
2178                         adapter->flags &= ~IGB_FLAG_DMAC;
2179         }
2180
2181         /* convert to rate of irq's per second */
2182         if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2183                 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2184         else
2185                 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2186
2187         /* convert to rate of irq's per second */
2188         if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2189                 adapter->tx_itr_setting = adapter->rx_itr_setting;
2190         else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2191                 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2192         else
2193                 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2194
2195         for (i = 0; i < adapter->num_q_vectors; i++) {
2196                 struct igb_q_vector *q_vector = adapter->q_vector[i];
2197                 q_vector->tx.work_limit = adapter->tx_work_limit;
2198                 if (q_vector->rx.ring)
2199                         q_vector->itr_val = adapter->rx_itr_setting;
2200                 else
2201                         q_vector->itr_val = adapter->tx_itr_setting;
2202                 if (q_vector->itr_val && q_vector->itr_val <= 3)
2203                         q_vector->itr_val = IGB_START_ITR;
2204                 q_vector->set_itr = 1;
2205         }
2206
2207         return 0;
2208 }
2209
2210 static int igb_get_coalesce(struct net_device *netdev,
2211                             struct ethtool_coalesce *ec)
2212 {
2213         struct igb_adapter *adapter = netdev_priv(netdev);
2214
2215         if (adapter->rx_itr_setting <= 3)
2216                 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2217         else
2218                 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2219
2220         if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2221                 if (adapter->tx_itr_setting <= 3)
2222                         ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2223                 else
2224                         ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2225         }
2226
2227         return 0;
2228 }
2229
2230 static int igb_nway_reset(struct net_device *netdev)
2231 {
2232         struct igb_adapter *adapter = netdev_priv(netdev);
2233         if (netif_running(netdev))
2234                 igb_reinit_locked(adapter);
2235         return 0;
2236 }
2237
2238 static int igb_get_sset_count(struct net_device *netdev, int sset)
2239 {
2240         switch (sset) {
2241         case ETH_SS_STATS:
2242                 return IGB_STATS_LEN;
2243         case ETH_SS_TEST:
2244                 return IGB_TEST_LEN;
2245         default:
2246                 return -ENOTSUPP;
2247         }
2248 }
2249
2250 static void igb_get_ethtool_stats(struct net_device *netdev,
2251                                   struct ethtool_stats *stats, u64 *data)
2252 {
2253         struct igb_adapter *adapter = netdev_priv(netdev);
2254         struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2255         unsigned int start;
2256         struct igb_ring *ring;
2257         int i, j;
2258         char *p;
2259
2260         spin_lock(&adapter->stats64_lock);
2261         igb_update_stats(adapter, net_stats);
2262
2263         for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2264                 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
2265                 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2266                         sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2267         }
2268         for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2269                 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2270                 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2271                         sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2272         }
2273         for (j = 0; j < adapter->num_tx_queues; j++) {
2274                 u64     restart2;
2275
2276                 ring = adapter->tx_ring[j];
2277                 do {
2278                         start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
2279                         data[i]   = ring->tx_stats.packets;
2280                         data[i+1] = ring->tx_stats.bytes;
2281                         data[i+2] = ring->tx_stats.restart_queue;
2282                 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
2283                 do {
2284                         start = u64_stats_fetch_begin_irq(&ring->tx_syncp2);
2285                         restart2  = ring->tx_stats.restart_queue2;
2286                 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp2, start));
2287                 data[i+2] += restart2;
2288
2289                 i += IGB_TX_QUEUE_STATS_LEN;
2290         }
2291         for (j = 0; j < adapter->num_rx_queues; j++) {
2292                 ring = adapter->rx_ring[j];
2293                 do {
2294                         start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
2295                         data[i]   = ring->rx_stats.packets;
2296                         data[i+1] = ring->rx_stats.bytes;
2297                         data[i+2] = ring->rx_stats.drops;
2298                         data[i+3] = ring->rx_stats.csum_err;
2299                         data[i+4] = ring->rx_stats.alloc_failed;
2300                 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
2301                 i += IGB_RX_QUEUE_STATS_LEN;
2302         }
2303         spin_unlock(&adapter->stats64_lock);
2304 }
2305
2306 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2307 {
2308         struct igb_adapter *adapter = netdev_priv(netdev);
2309         u8 *p = data;
2310         int i;
2311
2312         switch (stringset) {
2313         case ETH_SS_TEST:
2314                 memcpy(data, *igb_gstrings_test,
2315                         IGB_TEST_LEN*ETH_GSTRING_LEN);
2316                 break;
2317         case ETH_SS_STATS:
2318                 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2319                         memcpy(p, igb_gstrings_stats[i].stat_string,
2320                                ETH_GSTRING_LEN);
2321                         p += ETH_GSTRING_LEN;
2322                 }
2323                 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2324                         memcpy(p, igb_gstrings_net_stats[i].stat_string,
2325                                ETH_GSTRING_LEN);
2326                         p += ETH_GSTRING_LEN;
2327                 }
2328                 for (i = 0; i < adapter->num_tx_queues; i++) {
2329                         sprintf(p, "tx_queue_%u_packets", i);
2330                         p += ETH_GSTRING_LEN;
2331                         sprintf(p, "tx_queue_%u_bytes", i);
2332                         p += ETH_GSTRING_LEN;
2333                         sprintf(p, "tx_queue_%u_restart", i);
2334                         p += ETH_GSTRING_LEN;
2335                 }
2336                 for (i = 0; i < adapter->num_rx_queues; i++) {
2337                         sprintf(p, "rx_queue_%u_packets", i);
2338                         p += ETH_GSTRING_LEN;
2339                         sprintf(p, "rx_queue_%u_bytes", i);
2340                         p += ETH_GSTRING_LEN;
2341                         sprintf(p, "rx_queue_%u_drops", i);
2342                         p += ETH_GSTRING_LEN;
2343                         sprintf(p, "rx_queue_%u_csum_err", i);
2344                         p += ETH_GSTRING_LEN;
2345                         sprintf(p, "rx_queue_%u_alloc_failed", i);
2346                         p += ETH_GSTRING_LEN;
2347                 }
2348                 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2349                 break;
2350         }
2351 }
2352
2353 static int igb_get_ts_info(struct net_device *dev,
2354                            struct ethtool_ts_info *info)
2355 {
2356         struct igb_adapter *adapter = netdev_priv(dev);
2357
2358         if (adapter->ptp_clock)
2359                 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2360         else
2361                 info->phc_index = -1;
2362
2363         switch (adapter->hw.mac.type) {
2364         case e1000_82575:
2365                 info->so_timestamping =
2366                         SOF_TIMESTAMPING_TX_SOFTWARE |
2367                         SOF_TIMESTAMPING_RX_SOFTWARE |
2368                         SOF_TIMESTAMPING_SOFTWARE;
2369                 return 0;
2370         case e1000_82576:
2371         case e1000_82580:
2372         case e1000_i350:
2373         case e1000_i354:
2374         case e1000_i210:
2375         case e1000_i211:
2376                 info->so_timestamping =
2377                         SOF_TIMESTAMPING_TX_SOFTWARE |
2378                         SOF_TIMESTAMPING_RX_SOFTWARE |
2379                         SOF_TIMESTAMPING_SOFTWARE |
2380                         SOF_TIMESTAMPING_TX_HARDWARE |
2381                         SOF_TIMESTAMPING_RX_HARDWARE |
2382                         SOF_TIMESTAMPING_RAW_HARDWARE;
2383
2384                 info->tx_types =
2385                         (1 << HWTSTAMP_TX_OFF) |
2386                         (1 << HWTSTAMP_TX_ON);
2387
2388                 info->rx_filters = 1 << HWTSTAMP_FILTER_NONE;
2389
2390                 /* 82576 does not support timestamping all packets. */
2391                 if (adapter->hw.mac.type >= e1000_82580)
2392                         info->rx_filters |= 1 << HWTSTAMP_FILTER_ALL;
2393                 else
2394                         info->rx_filters |=
2395                                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2396                                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2397                                 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2398                                 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2399                                 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
2400                                 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
2401                                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2402
2403                 return 0;
2404         default:
2405                 return -EOPNOTSUPP;
2406         }
2407 }
2408
2409 static int igb_get_rss_hash_opts(struct igb_adapter *adapter,
2410                                  struct ethtool_rxnfc *cmd)
2411 {
2412         cmd->data = 0;
2413
2414         /* Report default options for RSS on igb */
2415         switch (cmd->flow_type) {
2416         case TCP_V4_FLOW:
2417                 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2418                 /* Fall through */
2419         case UDP_V4_FLOW:
2420                 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2421                         cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2422                 /* Fall through */
2423         case SCTP_V4_FLOW:
2424         case AH_ESP_V4_FLOW:
2425         case AH_V4_FLOW:
2426         case ESP_V4_FLOW:
2427         case IPV4_FLOW:
2428                 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2429                 break;
2430         case TCP_V6_FLOW:
2431                 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2432                 /* Fall through */
2433         case UDP_V6_FLOW:
2434                 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2435                         cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2436                 /* Fall through */
2437         case SCTP_V6_FLOW:
2438         case AH_ESP_V6_FLOW:
2439         case AH_V6_FLOW:
2440         case ESP_V6_FLOW:
2441         case IPV6_FLOW:
2442                 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2443                 break;
2444         default:
2445                 return -EINVAL;
2446         }
2447
2448         return 0;
2449 }
2450
2451 static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2452                          u32 *rule_locs)
2453 {
2454         struct igb_adapter *adapter = netdev_priv(dev);
2455         int ret = -EOPNOTSUPP;
2456
2457         switch (cmd->cmd) {
2458         case ETHTOOL_GRXRINGS:
2459                 cmd->data = adapter->num_rx_queues;
2460                 ret = 0;
2461                 break;
2462         case ETHTOOL_GRXFH:
2463                 ret = igb_get_rss_hash_opts(adapter, cmd);
2464                 break;
2465         default:
2466                 break;
2467         }
2468
2469         return ret;
2470 }
2471
2472 #define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \
2473                        IGB_FLAG_RSS_FIELD_IPV6_UDP)
2474 static int igb_set_rss_hash_opt(struct igb_adapter *adapter,
2475                                 struct ethtool_rxnfc *nfc)
2476 {
2477         u32 flags = adapter->flags;
2478
2479         /* RSS does not support anything other than hashing
2480          * to queues on src and dst IPs and ports
2481          */
2482         if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2483                           RXH_L4_B_0_1 | RXH_L4_B_2_3))
2484                 return -EINVAL;
2485
2486         switch (nfc->flow_type) {
2487         case TCP_V4_FLOW:
2488         case TCP_V6_FLOW:
2489                 if (!(nfc->data & RXH_IP_SRC) ||
2490                     !(nfc->data & RXH_IP_DST) ||
2491                     !(nfc->data & RXH_L4_B_0_1) ||
2492                     !(nfc->data & RXH_L4_B_2_3))
2493                         return -EINVAL;
2494                 break;
2495         case UDP_V4_FLOW:
2496                 if (!(nfc->data & RXH_IP_SRC) ||
2497                     !(nfc->data & RXH_IP_DST))
2498                         return -EINVAL;
2499                 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2500                 case 0:
2501                         flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP;
2502                         break;
2503                 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2504                         flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP;
2505                         break;
2506                 default:
2507                         return -EINVAL;
2508                 }
2509                 break;
2510         case UDP_V6_FLOW:
2511                 if (!(nfc->data & RXH_IP_SRC) ||
2512                     !(nfc->data & RXH_IP_DST))
2513                         return -EINVAL;
2514                 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2515                 case 0:
2516                         flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP;
2517                         break;
2518                 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2519                         flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP;
2520                         break;
2521                 default:
2522                         return -EINVAL;
2523                 }
2524                 break;
2525         case AH_ESP_V4_FLOW:
2526         case AH_V4_FLOW:
2527         case ESP_V4_FLOW:
2528         case SCTP_V4_FLOW:
2529         case AH_ESP_V6_FLOW:
2530         case AH_V6_FLOW:
2531         case ESP_V6_FLOW:
2532         case SCTP_V6_FLOW:
2533                 if (!(nfc->data & RXH_IP_SRC) ||
2534                     !(nfc->data & RXH_IP_DST) ||
2535                     (nfc->data & RXH_L4_B_0_1) ||
2536                     (nfc->data & RXH_L4_B_2_3))
2537                         return -EINVAL;
2538                 break;
2539         default:
2540                 return -EINVAL;
2541         }
2542
2543         /* if we changed something we need to update flags */
2544         if (flags != adapter->flags) {
2545                 struct e1000_hw *hw = &adapter->hw;
2546                 u32 mrqc = rd32(E1000_MRQC);
2547
2548                 if ((flags & UDP_RSS_FLAGS) &&
2549                     !(adapter->flags & UDP_RSS_FLAGS))
2550                         dev_err(&adapter->pdev->dev,
2551                                 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2552
2553                 adapter->flags = flags;
2554
2555                 /* Perform hash on these packet types */
2556                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2557                         E1000_MRQC_RSS_FIELD_IPV4_TCP |
2558                         E1000_MRQC_RSS_FIELD_IPV6 |
2559                         E1000_MRQC_RSS_FIELD_IPV6_TCP;
2560
2561                 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP |
2562                           E1000_MRQC_RSS_FIELD_IPV6_UDP);
2563
2564                 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2565                         mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2566
2567                 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2568                         mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2569
2570                 wr32(E1000_MRQC, mrqc);
2571         }
2572
2573         return 0;
2574 }
2575
2576 static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2577 {
2578         struct igb_adapter *adapter = netdev_priv(dev);
2579         int ret = -EOPNOTSUPP;
2580
2581         switch (cmd->cmd) {
2582         case ETHTOOL_SRXFH:
2583                 ret = igb_set_rss_hash_opt(adapter, cmd);
2584                 break;
2585         default:
2586                 break;
2587         }
2588
2589         return ret;
2590 }
2591
2592 static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
2593 {
2594         struct igb_adapter *adapter = netdev_priv(netdev);
2595         struct e1000_hw *hw = &adapter->hw;
2596         u32 ret_val;
2597         u16 phy_data;
2598
2599         if ((hw->mac.type < e1000_i350) ||
2600             (hw->phy.media_type != e1000_media_type_copper))
2601                 return -EOPNOTSUPP;
2602
2603         edata->supported = (SUPPORTED_1000baseT_Full |
2604                             SUPPORTED_100baseT_Full);
2605         if (!hw->dev_spec._82575.eee_disable)
2606                 edata->advertised =
2607                         mmd_eee_adv_to_ethtool_adv_t(adapter->eee_advert);
2608
2609         /* The IPCNFG and EEER registers are not supported on I354. */
2610         if (hw->mac.type == e1000_i354) {
2611                 igb_get_eee_status_i354(hw, (bool *)&edata->eee_active);
2612         } else {
2613                 u32 eeer;
2614
2615                 eeer = rd32(E1000_EEER);
2616
2617                 /* EEE status on negotiated link */
2618                 if (eeer & E1000_EEER_EEE_NEG)
2619                         edata->eee_active = true;
2620
2621                 if (eeer & E1000_EEER_TX_LPI_EN)
2622                         edata->tx_lpi_enabled = true;
2623         }
2624
2625         /* EEE Link Partner Advertised */
2626         switch (hw->mac.type) {
2627         case e1000_i350:
2628                 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350,
2629                                            &phy_data);
2630                 if (ret_val)
2631                         return -ENODATA;
2632
2633                 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
2634                 break;
2635         case e1000_i354:
2636         case e1000_i210:
2637         case e1000_i211:
2638                 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210,
2639                                              E1000_EEE_LP_ADV_DEV_I210,
2640                                              &phy_data);
2641                 if (ret_val)
2642                         return -ENODATA;
2643
2644                 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
2645
2646                 break;
2647         default:
2648                 break;
2649         }
2650
2651         edata->eee_enabled = !hw->dev_spec._82575.eee_disable;
2652
2653         if ((hw->mac.type == e1000_i354) &&
2654             (edata->eee_enabled))
2655                 edata->tx_lpi_enabled = true;
2656
2657         /* Report correct negotiated EEE status for devices that
2658          * wrongly report EEE at half-duplex
2659          */
2660         if (adapter->link_duplex == HALF_DUPLEX) {
2661                 edata->eee_enabled = false;
2662                 edata->eee_active = false;
2663                 edata->tx_lpi_enabled = false;
2664                 edata->advertised &= ~edata->advertised;
2665         }
2666
2667         return 0;
2668 }
2669
2670 static int igb_set_eee(struct net_device *netdev,
2671                        struct ethtool_eee *edata)
2672 {
2673         struct igb_adapter *adapter = netdev_priv(netdev);
2674         struct e1000_hw *hw = &adapter->hw;
2675         struct ethtool_eee eee_curr;
2676         s32 ret_val;
2677
2678         if ((hw->mac.type < e1000_i350) ||
2679             (hw->phy.media_type != e1000_media_type_copper))
2680                 return -EOPNOTSUPP;
2681
2682         memset(&eee_curr, 0, sizeof(struct ethtool_eee));
2683
2684         ret_val = igb_get_eee(netdev, &eee_curr);
2685         if (ret_val)
2686                 return ret_val;
2687
2688         if (eee_curr.eee_enabled) {
2689                 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) {
2690                         dev_err(&adapter->pdev->dev,
2691                                 "Setting EEE tx-lpi is not supported\n");
2692                         return -EINVAL;
2693                 }
2694
2695                 /* Tx LPI timer is not implemented currently */
2696                 if (edata->tx_lpi_timer) {
2697                         dev_err(&adapter->pdev->dev,
2698                                 "Setting EEE Tx LPI timer is not supported\n");
2699                         return -EINVAL;
2700                 }
2701
2702                 if (edata->advertised &
2703                     ~(ADVERTISE_100_FULL | ADVERTISE_1000_FULL)) {
2704                         dev_err(&adapter->pdev->dev,
2705                                 "EEE Advertisement supports only 100Tx and or 100T full duplex\n");
2706                         return -EINVAL;
2707                 }
2708
2709         } else if (!edata->eee_enabled) {
2710                 dev_err(&adapter->pdev->dev,
2711                         "Setting EEE options are not supported with EEE disabled\n");
2712                         return -EINVAL;
2713                 }
2714
2715         adapter->eee_advert = ethtool_adv_to_mmd_eee_adv_t(edata->advertised);
2716         if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) {
2717                 hw->dev_spec._82575.eee_disable = !edata->eee_enabled;
2718                 adapter->flags |= IGB_FLAG_EEE;
2719                 if (hw->mac.type == e1000_i350)
2720                         igb_set_eee_i350(hw);
2721                 else
2722                         igb_set_eee_i354(hw);
2723
2724                 /* reset link */
2725                 if (netif_running(netdev))
2726                         igb_reinit_locked(adapter);
2727                 else
2728                         igb_reset(adapter);
2729         }
2730
2731         return 0;
2732 }
2733
2734 static int igb_get_module_info(struct net_device *netdev,
2735                                struct ethtool_modinfo *modinfo)
2736 {
2737         struct igb_adapter *adapter = netdev_priv(netdev);
2738         struct e1000_hw *hw = &adapter->hw;
2739         u32 status = E1000_SUCCESS;
2740         u16 sff8472_rev, addr_mode;
2741         bool page_swap = false;
2742
2743         if ((hw->phy.media_type == e1000_media_type_copper) ||
2744             (hw->phy.media_type == e1000_media_type_unknown))
2745                 return -EOPNOTSUPP;
2746
2747         /* Check whether we support SFF-8472 or not */
2748         status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
2749         if (status != E1000_SUCCESS)
2750                 return -EIO;
2751
2752         /* addressing mode is not supported */
2753         status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
2754         if (status != E1000_SUCCESS)
2755                 return -EIO;
2756
2757         /* addressing mode is not supported */
2758         if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
2759                 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
2760                 page_swap = true;
2761         }
2762
2763         if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
2764                 /* We have an SFP, but it does not support SFF-8472 */
2765                 modinfo->type = ETH_MODULE_SFF_8079;
2766                 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
2767         } else {
2768                 /* We have an SFP which supports a revision of SFF-8472 */
2769                 modinfo->type = ETH_MODULE_SFF_8472;
2770                 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2771         }
2772
2773         return 0;
2774 }
2775
2776 static int igb_get_module_eeprom(struct net_device *netdev,
2777                                  struct ethtool_eeprom *ee, u8 *data)
2778 {
2779         struct igb_adapter *adapter = netdev_priv(netdev);
2780         struct e1000_hw *hw = &adapter->hw;
2781         u32 status = E1000_SUCCESS;
2782         u16 *dataword;
2783         u16 first_word, last_word;
2784         int i = 0;
2785
2786         if (ee->len == 0)
2787                 return -EINVAL;
2788
2789         first_word = ee->offset >> 1;
2790         last_word = (ee->offset + ee->len - 1) >> 1;
2791
2792         dataword = kmalloc(sizeof(u16) * (last_word - first_word + 1),
2793                            GFP_KERNEL);
2794         if (!dataword)
2795                 return -ENOMEM;
2796
2797         /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
2798         for (i = 0; i < last_word - first_word + 1; i++) {
2799                 status = igb_read_phy_reg_i2c(hw, first_word + i, &dataword[i]);
2800                 if (status != E1000_SUCCESS) {
2801                         /* Error occurred while reading module */
2802                         kfree(dataword);
2803                         return -EIO;
2804                 }
2805
2806                 be16_to_cpus(&dataword[i]);
2807         }
2808
2809         memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len);
2810         kfree(dataword);
2811
2812         return 0;
2813 }
2814
2815 static int igb_ethtool_begin(struct net_device *netdev)
2816 {
2817         struct igb_adapter *adapter = netdev_priv(netdev);
2818         pm_runtime_get_sync(&adapter->pdev->dev);
2819         return 0;
2820 }
2821
2822 static void igb_ethtool_complete(struct net_device *netdev)
2823 {
2824         struct igb_adapter *adapter = netdev_priv(netdev);
2825         pm_runtime_put(&adapter->pdev->dev);
2826 }
2827
2828 static u32 igb_get_rxfh_indir_size(struct net_device *netdev)
2829 {
2830         return IGB_RETA_SIZE;
2831 }
2832
2833 static int igb_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key)
2834 {
2835         struct igb_adapter *adapter = netdev_priv(netdev);
2836         int i;
2837
2838         for (i = 0; i < IGB_RETA_SIZE; i++)
2839                 indir[i] = adapter->rss_indir_tbl[i];
2840
2841         return 0;
2842 }
2843
2844 void igb_write_rss_indir_tbl(struct igb_adapter *adapter)
2845 {
2846         struct e1000_hw *hw = &adapter->hw;
2847         u32 reg = E1000_RETA(0);
2848         u32 shift = 0;
2849         int i = 0;
2850
2851         switch (hw->mac.type) {
2852         case e1000_82575:
2853                 shift = 6;
2854                 break;
2855         case e1000_82576:
2856                 /* 82576 supports 2 RSS queues for SR-IOV */
2857                 if (adapter->vfs_allocated_count)
2858                         shift = 3;
2859                 break;
2860         default:
2861                 break;
2862         }
2863
2864         while (i < IGB_RETA_SIZE) {
2865                 u32 val = 0;
2866                 int j;
2867
2868                 for (j = 3; j >= 0; j--) {
2869                         val <<= 8;
2870                         val |= adapter->rss_indir_tbl[i + j];
2871                 }
2872
2873                 wr32(reg, val << shift);
2874                 reg += 4;
2875                 i += 4;
2876         }
2877 }
2878
2879 static int igb_set_rxfh(struct net_device *netdev, const u32 *indir,
2880                         const u8 *key)
2881 {
2882         struct igb_adapter *adapter = netdev_priv(netdev);
2883         struct e1000_hw *hw = &adapter->hw;
2884         int i;
2885         u32 num_queues;
2886
2887         num_queues = adapter->rss_queues;
2888
2889         switch (hw->mac.type) {
2890         case e1000_82576:
2891                 /* 82576 supports 2 RSS queues for SR-IOV */
2892                 if (adapter->vfs_allocated_count)
2893                         num_queues = 2;
2894                 break;
2895         default:
2896                 break;
2897         }
2898
2899         /* Verify user input. */
2900         for (i = 0; i < IGB_RETA_SIZE; i++)
2901                 if (indir[i] >= num_queues)
2902                         return -EINVAL;
2903
2904
2905         for (i = 0; i < IGB_RETA_SIZE; i++)
2906                 adapter->rss_indir_tbl[i] = indir[i];
2907
2908         igb_write_rss_indir_tbl(adapter);
2909
2910         return 0;
2911 }
2912
2913 static unsigned int igb_max_channels(struct igb_adapter *adapter)
2914 {
2915         struct e1000_hw *hw = &adapter->hw;
2916         unsigned int max_combined = 0;
2917
2918         switch (hw->mac.type) {
2919         case e1000_i211:
2920                 max_combined = IGB_MAX_RX_QUEUES_I211;
2921                 break;
2922         case e1000_82575:
2923         case e1000_i210:
2924                 max_combined = IGB_MAX_RX_QUEUES_82575;
2925                 break;
2926         case e1000_i350:
2927                 if (!!adapter->vfs_allocated_count) {
2928                         max_combined = 1;
2929                         break;
2930                 }
2931                 /* fall through */
2932         case e1000_82576:
2933                 if (!!adapter->vfs_allocated_count) {
2934                         max_combined = 2;
2935                         break;
2936                 }
2937                 /* fall through */
2938         case e1000_82580:
2939         case e1000_i354:
2940         default:
2941                 max_combined = IGB_MAX_RX_QUEUES;
2942                 break;
2943         }
2944
2945         return max_combined;
2946 }
2947
2948 static void igb_get_channels(struct net_device *netdev,
2949                              struct ethtool_channels *ch)
2950 {
2951         struct igb_adapter *adapter = netdev_priv(netdev);
2952
2953         /* Report maximum channels */
2954         ch->max_combined = igb_max_channels(adapter);
2955
2956         /* Report info for other vector */
2957         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2958                 ch->max_other = NON_Q_VECTORS;
2959                 ch->other_count = NON_Q_VECTORS;
2960         }
2961
2962         ch->combined_count = adapter->rss_queues;
2963 }
2964
2965 static int igb_set_channels(struct net_device *netdev,
2966                             struct ethtool_channels *ch)
2967 {
2968         struct igb_adapter *adapter = netdev_priv(netdev);
2969         unsigned int count = ch->combined_count;
2970
2971         /* Verify they are not requesting separate vectors */
2972         if (!count || ch->rx_count || ch->tx_count)
2973                 return -EINVAL;
2974
2975         /* Verify other_count is valid and has not been changed */
2976         if (ch->other_count != NON_Q_VECTORS)
2977                 return -EINVAL;
2978
2979         /* Verify the number of channels doesn't exceed hw limits */
2980         if (count > igb_max_channels(adapter))
2981                 return -EINVAL;
2982
2983         if (count != adapter->rss_queues) {
2984                 adapter->rss_queues = count;
2985
2986                 /* Hardware has to reinitialize queues and interrupts to
2987                  * match the new configuration.
2988                  */
2989                 return igb_reinit_queues(adapter);
2990         }
2991
2992         return 0;
2993 }
2994
2995 static const struct ethtool_ops igb_ethtool_ops = {
2996         .get_settings           = igb_get_settings,
2997         .set_settings           = igb_set_settings,
2998         .get_drvinfo            = igb_get_drvinfo,
2999         .get_regs_len           = igb_get_regs_len,
3000         .get_regs               = igb_get_regs,
3001         .get_wol                = igb_get_wol,
3002         .set_wol                = igb_set_wol,
3003         .get_msglevel           = igb_get_msglevel,
3004         .set_msglevel           = igb_set_msglevel,
3005         .nway_reset             = igb_nway_reset,
3006         .get_link               = igb_get_link,
3007         .get_eeprom_len         = igb_get_eeprom_len,
3008         .get_eeprom             = igb_get_eeprom,
3009         .set_eeprom             = igb_set_eeprom,
3010         .get_ringparam          = igb_get_ringparam,
3011         .set_ringparam          = igb_set_ringparam,
3012         .get_pauseparam         = igb_get_pauseparam,
3013         .set_pauseparam         = igb_set_pauseparam,
3014         .self_test              = igb_diag_test,
3015         .get_strings            = igb_get_strings,
3016         .set_phys_id            = igb_set_phys_id,
3017         .get_sset_count         = igb_get_sset_count,
3018         .get_ethtool_stats      = igb_get_ethtool_stats,
3019         .get_coalesce           = igb_get_coalesce,
3020         .set_coalesce           = igb_set_coalesce,
3021         .get_ts_info            = igb_get_ts_info,
3022         .get_rxnfc              = igb_get_rxnfc,
3023         .set_rxnfc              = igb_set_rxnfc,
3024         .get_eee                = igb_get_eee,
3025         .set_eee                = igb_set_eee,
3026         .get_module_info        = igb_get_module_info,
3027         .get_module_eeprom      = igb_get_module_eeprom,
3028         .get_rxfh_indir_size    = igb_get_rxfh_indir_size,
3029         .get_rxfh               = igb_get_rxfh,
3030         .set_rxfh               = igb_set_rxfh,
3031         .get_channels           = igb_get_channels,
3032         .set_channels           = igb_set_channels,
3033         .begin                  = igb_ethtool_begin,
3034         .complete               = igb_ethtool_complete,
3035 };
3036
3037 void igb_set_ethtool_ops(struct net_device *netdev)
3038 {
3039         netdev->ethtool_ops = &igb_ethtool_ops;
3040 }