1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
4 /* ethtool support for igb */
6 #include <linux/vmalloc.h>
7 #include <linux/netdevice.h>
9 #include <linux/delay.h>
10 #include <linux/interrupt.h>
11 #include <linux/if_ether.h>
12 #include <linux/ethtool.h>
13 #include <linux/sched.h>
14 #include <linux/slab.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/highmem.h>
17 #include <linux/mdio.h>
22 char stat_string[ETH_GSTRING_LEN];
27 #define IGB_STAT(_name, _stat) { \
28 .stat_string = _name, \
29 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
30 .stat_offset = offsetof(struct igb_adapter, _stat) \
32 static const struct igb_stats igb_gstrings_stats[] = {
33 IGB_STAT("rx_packets", stats.gprc),
34 IGB_STAT("tx_packets", stats.gptc),
35 IGB_STAT("rx_bytes", stats.gorc),
36 IGB_STAT("tx_bytes", stats.gotc),
37 IGB_STAT("rx_broadcast", stats.bprc),
38 IGB_STAT("tx_broadcast", stats.bptc),
39 IGB_STAT("rx_multicast", stats.mprc),
40 IGB_STAT("tx_multicast", stats.mptc),
41 IGB_STAT("multicast", stats.mprc),
42 IGB_STAT("collisions", stats.colc),
43 IGB_STAT("rx_crc_errors", stats.crcerrs),
44 IGB_STAT("rx_no_buffer_count", stats.rnbc),
45 IGB_STAT("rx_missed_errors", stats.mpc),
46 IGB_STAT("tx_aborted_errors", stats.ecol),
47 IGB_STAT("tx_carrier_errors", stats.tncrs),
48 IGB_STAT("tx_window_errors", stats.latecol),
49 IGB_STAT("tx_abort_late_coll", stats.latecol),
50 IGB_STAT("tx_deferred_ok", stats.dc),
51 IGB_STAT("tx_single_coll_ok", stats.scc),
52 IGB_STAT("tx_multi_coll_ok", stats.mcc),
53 IGB_STAT("tx_timeout_count", tx_timeout_count),
54 IGB_STAT("rx_long_length_errors", stats.roc),
55 IGB_STAT("rx_short_length_errors", stats.ruc),
56 IGB_STAT("rx_align_errors", stats.algnerrc),
57 IGB_STAT("tx_tcp_seg_good", stats.tsctc),
58 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
59 IGB_STAT("rx_flow_control_xon", stats.xonrxc),
60 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
61 IGB_STAT("tx_flow_control_xon", stats.xontxc),
62 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
63 IGB_STAT("rx_long_byte_count", stats.gorc),
64 IGB_STAT("tx_dma_out_of_sync", stats.doosync),
65 IGB_STAT("tx_smbus", stats.mgptc),
66 IGB_STAT("rx_smbus", stats.mgprc),
67 IGB_STAT("dropped_smbus", stats.mgpdc),
68 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
69 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
70 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
71 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
72 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
73 IGB_STAT("tx_hwtstamp_skipped", tx_hwtstamp_skipped),
74 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),
77 #define IGB_NETDEV_STAT(_net_stat) { \
78 .stat_string = __stringify(_net_stat), \
79 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \
80 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
82 static const struct igb_stats igb_gstrings_net_stats[] = {
83 IGB_NETDEV_STAT(rx_errors),
84 IGB_NETDEV_STAT(tx_errors),
85 IGB_NETDEV_STAT(tx_dropped),
86 IGB_NETDEV_STAT(rx_length_errors),
87 IGB_NETDEV_STAT(rx_over_errors),
88 IGB_NETDEV_STAT(rx_frame_errors),
89 IGB_NETDEV_STAT(rx_fifo_errors),
90 IGB_NETDEV_STAT(tx_fifo_errors),
91 IGB_NETDEV_STAT(tx_heartbeat_errors)
94 #define IGB_GLOBAL_STATS_LEN \
95 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
96 #define IGB_NETDEV_STATS_LEN \
97 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
98 #define IGB_RX_QUEUE_STATS_LEN \
99 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
101 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
103 #define IGB_QUEUE_STATS_LEN \
104 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
105 IGB_RX_QUEUE_STATS_LEN) + \
106 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
107 IGB_TX_QUEUE_STATS_LEN))
108 #define IGB_STATS_LEN \
109 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
111 enum igb_diagnostics_results {
119 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
120 [TEST_REG] = "Register test (offline)",
121 [TEST_EEP] = "Eeprom test (offline)",
122 [TEST_IRQ] = "Interrupt test (offline)",
123 [TEST_LOOP] = "Loopback test (offline)",
124 [TEST_LINK] = "Link test (on/offline)"
126 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
128 static const char igb_priv_flags_strings[][ETH_GSTRING_LEN] = {
129 #define IGB_PRIV_FLAGS_LEGACY_RX BIT(0)
133 #define IGB_PRIV_FLAGS_STR_LEN ARRAY_SIZE(igb_priv_flags_strings)
135 static int igb_get_link_ksettings(struct net_device *netdev,
136 struct ethtool_link_ksettings *cmd)
138 struct igb_adapter *adapter = netdev_priv(netdev);
139 struct e1000_hw *hw = &adapter->hw;
140 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
141 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
144 u32 supported, advertising;
146 status = rd32(E1000_STATUS);
147 if (hw->phy.media_type == e1000_media_type_copper) {
149 supported = (SUPPORTED_10baseT_Half |
150 SUPPORTED_10baseT_Full |
151 SUPPORTED_100baseT_Half |
152 SUPPORTED_100baseT_Full |
153 SUPPORTED_1000baseT_Full|
157 advertising = ADVERTISED_TP;
159 if (hw->mac.autoneg == 1) {
160 advertising |= ADVERTISED_Autoneg;
161 /* the e1000 autoneg seems to match ethtool nicely */
162 advertising |= hw->phy.autoneg_advertised;
165 cmd->base.port = PORT_TP;
166 cmd->base.phy_address = hw->phy.addr;
168 supported = (SUPPORTED_FIBRE |
169 SUPPORTED_1000baseKX_Full |
172 advertising = (ADVERTISED_FIBRE |
173 ADVERTISED_1000baseKX_Full);
174 if (hw->mac.type == e1000_i354) {
175 if ((hw->device_id ==
176 E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) &&
177 !(status & E1000_STATUS_2P5_SKU_OVER)) {
178 supported |= SUPPORTED_2500baseX_Full;
179 supported &= ~SUPPORTED_1000baseKX_Full;
180 advertising |= ADVERTISED_2500baseX_Full;
181 advertising &= ~ADVERTISED_1000baseKX_Full;
184 if (eth_flags->e100_base_fx) {
185 supported |= SUPPORTED_100baseT_Full;
186 advertising |= ADVERTISED_100baseT_Full;
188 if (hw->mac.autoneg == 1)
189 advertising |= ADVERTISED_Autoneg;
191 cmd->base.port = PORT_FIBRE;
193 if (hw->mac.autoneg != 1)
194 advertising &= ~(ADVERTISED_Pause |
195 ADVERTISED_Asym_Pause);
197 switch (hw->fc.requested_mode) {
199 advertising |= ADVERTISED_Pause;
201 case e1000_fc_rx_pause:
202 advertising |= (ADVERTISED_Pause |
203 ADVERTISED_Asym_Pause);
205 case e1000_fc_tx_pause:
206 advertising |= ADVERTISED_Asym_Pause;
209 advertising &= ~(ADVERTISED_Pause |
210 ADVERTISED_Asym_Pause);
212 if (status & E1000_STATUS_LU) {
213 if ((status & E1000_STATUS_2P5_SKU) &&
214 !(status & E1000_STATUS_2P5_SKU_OVER)) {
216 } else if (status & E1000_STATUS_SPEED_1000) {
218 } else if (status & E1000_STATUS_SPEED_100) {
223 if ((status & E1000_STATUS_FD) ||
224 hw->phy.media_type != e1000_media_type_copper)
225 cmd->base.duplex = DUPLEX_FULL;
227 cmd->base.duplex = DUPLEX_HALF;
229 speed = SPEED_UNKNOWN;
230 cmd->base.duplex = DUPLEX_UNKNOWN;
232 cmd->base.speed = speed;
233 if ((hw->phy.media_type == e1000_media_type_fiber) ||
235 cmd->base.autoneg = AUTONEG_ENABLE;
237 cmd->base.autoneg = AUTONEG_DISABLE;
239 /* MDI-X => 2; MDI =>1; Invalid =>0 */
240 if (hw->phy.media_type == e1000_media_type_copper)
241 cmd->base.eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X :
244 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID;
246 if (hw->phy.mdix == AUTO_ALL_MODES)
247 cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
249 cmd->base.eth_tp_mdix_ctrl = hw->phy.mdix;
251 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
253 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
259 static int igb_set_link_ksettings(struct net_device *netdev,
260 const struct ethtool_link_ksettings *cmd)
262 struct igb_adapter *adapter = netdev_priv(netdev);
263 struct e1000_hw *hw = &adapter->hw;
266 /* When SoL/IDER sessions are active, autoneg/speed/duplex
269 if (igb_check_reset_block(hw)) {
270 dev_err(&adapter->pdev->dev,
271 "Cannot change link characteristics when SoL/IDER is active.\n");
275 /* MDI setting is only allowed when autoneg enabled because
276 * some hardware doesn't allow MDI setting when speed or
279 if (cmd->base.eth_tp_mdix_ctrl) {
280 if (hw->phy.media_type != e1000_media_type_copper)
283 if ((cmd->base.eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&
284 (cmd->base.autoneg != AUTONEG_ENABLE)) {
285 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n");
290 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
291 usleep_range(1000, 2000);
293 ethtool_convert_link_mode_to_legacy_u32(&advertising,
294 cmd->link_modes.advertising);
296 if (cmd->base.autoneg == AUTONEG_ENABLE) {
298 if (hw->phy.media_type == e1000_media_type_fiber) {
299 hw->phy.autoneg_advertised = advertising |
302 switch (adapter->link_speed) {
304 hw->phy.autoneg_advertised =
305 ADVERTISED_2500baseX_Full;
308 hw->phy.autoneg_advertised =
309 ADVERTISED_1000baseT_Full;
312 hw->phy.autoneg_advertised =
313 ADVERTISED_100baseT_Full;
319 hw->phy.autoneg_advertised = advertising |
323 advertising = hw->phy.autoneg_advertised;
324 if (adapter->fc_autoneg)
325 hw->fc.requested_mode = e1000_fc_default;
327 u32 speed = cmd->base.speed;
328 /* calling this overrides forced MDI setting */
329 if (igb_set_spd_dplx(adapter, speed, cmd->base.duplex)) {
330 clear_bit(__IGB_RESETTING, &adapter->state);
335 /* MDI-X => 2; MDI => 1; Auto => 3 */
336 if (cmd->base.eth_tp_mdix_ctrl) {
337 /* fix up the value for auto (3 => 0) as zero is mapped
340 if (cmd->base.eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)
341 hw->phy.mdix = AUTO_ALL_MODES;
343 hw->phy.mdix = cmd->base.eth_tp_mdix_ctrl;
347 if (netif_running(adapter->netdev)) {
353 clear_bit(__IGB_RESETTING, &adapter->state);
357 static u32 igb_get_link(struct net_device *netdev)
359 struct igb_adapter *adapter = netdev_priv(netdev);
360 struct e1000_mac_info *mac = &adapter->hw.mac;
362 /* If the link is not reported up to netdev, interrupts are disabled,
363 * and so the physical link state may have changed since we last
364 * looked. Set get_link_status to make sure that the true link
365 * state is interrogated, rather than pulling a cached and possibly
366 * stale link state from the driver.
368 if (!netif_carrier_ok(netdev))
369 mac->get_link_status = 1;
371 return igb_has_link(adapter);
374 static void igb_get_pauseparam(struct net_device *netdev,
375 struct ethtool_pauseparam *pause)
377 struct igb_adapter *adapter = netdev_priv(netdev);
378 struct e1000_hw *hw = &adapter->hw;
381 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
383 if (hw->fc.current_mode == e1000_fc_rx_pause)
385 else if (hw->fc.current_mode == e1000_fc_tx_pause)
387 else if (hw->fc.current_mode == e1000_fc_full) {
393 static int igb_set_pauseparam(struct net_device *netdev,
394 struct ethtool_pauseparam *pause)
396 struct igb_adapter *adapter = netdev_priv(netdev);
397 struct e1000_hw *hw = &adapter->hw;
400 /* 100basefx does not support setting link flow control */
401 if (hw->dev_spec._82575.eth_flags.e100_base_fx)
404 adapter->fc_autoneg = pause->autoneg;
406 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
407 usleep_range(1000, 2000);
409 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
410 hw->fc.requested_mode = e1000_fc_default;
411 if (netif_running(adapter->netdev)) {
418 if (pause->rx_pause && pause->tx_pause)
419 hw->fc.requested_mode = e1000_fc_full;
420 else if (pause->rx_pause && !pause->tx_pause)
421 hw->fc.requested_mode = e1000_fc_rx_pause;
422 else if (!pause->rx_pause && pause->tx_pause)
423 hw->fc.requested_mode = e1000_fc_tx_pause;
424 else if (!pause->rx_pause && !pause->tx_pause)
425 hw->fc.requested_mode = e1000_fc_none;
427 hw->fc.current_mode = hw->fc.requested_mode;
429 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
430 igb_force_mac_fc(hw) : igb_setup_link(hw));
433 clear_bit(__IGB_RESETTING, &adapter->state);
437 static u32 igb_get_msglevel(struct net_device *netdev)
439 struct igb_adapter *adapter = netdev_priv(netdev);
440 return adapter->msg_enable;
443 static void igb_set_msglevel(struct net_device *netdev, u32 data)
445 struct igb_adapter *adapter = netdev_priv(netdev);
446 adapter->msg_enable = data;
449 static int igb_get_regs_len(struct net_device *netdev)
451 #define IGB_REGS_LEN 740
452 return IGB_REGS_LEN * sizeof(u32);
455 static void igb_get_regs(struct net_device *netdev,
456 struct ethtool_regs *regs, void *p)
458 struct igb_adapter *adapter = netdev_priv(netdev);
459 struct e1000_hw *hw = &adapter->hw;
463 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
465 regs->version = (1u << 24) | (hw->revision_id << 16) | hw->device_id;
467 /* General Registers */
468 regs_buff[0] = rd32(E1000_CTRL);
469 regs_buff[1] = rd32(E1000_STATUS);
470 regs_buff[2] = rd32(E1000_CTRL_EXT);
471 regs_buff[3] = rd32(E1000_MDIC);
472 regs_buff[4] = rd32(E1000_SCTL);
473 regs_buff[5] = rd32(E1000_CONNSW);
474 regs_buff[6] = rd32(E1000_VET);
475 regs_buff[7] = rd32(E1000_LEDCTL);
476 regs_buff[8] = rd32(E1000_PBA);
477 regs_buff[9] = rd32(E1000_PBS);
478 regs_buff[10] = rd32(E1000_FRTIMER);
479 regs_buff[11] = rd32(E1000_TCPTIMER);
482 regs_buff[12] = rd32(E1000_EECD);
485 /* Reading EICS for EICR because they read the
486 * same but EICS does not clear on read
488 regs_buff[13] = rd32(E1000_EICS);
489 regs_buff[14] = rd32(E1000_EICS);
490 regs_buff[15] = rd32(E1000_EIMS);
491 regs_buff[16] = rd32(E1000_EIMC);
492 regs_buff[17] = rd32(E1000_EIAC);
493 regs_buff[18] = rd32(E1000_EIAM);
494 /* Reading ICS for ICR because they read the
495 * same but ICS does not clear on read
497 regs_buff[19] = rd32(E1000_ICS);
498 regs_buff[20] = rd32(E1000_ICS);
499 regs_buff[21] = rd32(E1000_IMS);
500 regs_buff[22] = rd32(E1000_IMC);
501 regs_buff[23] = rd32(E1000_IAC);
502 regs_buff[24] = rd32(E1000_IAM);
503 regs_buff[25] = rd32(E1000_IMIRVP);
506 regs_buff[26] = rd32(E1000_FCAL);
507 regs_buff[27] = rd32(E1000_FCAH);
508 regs_buff[28] = rd32(E1000_FCTTV);
509 regs_buff[29] = rd32(E1000_FCRTL);
510 regs_buff[30] = rd32(E1000_FCRTH);
511 regs_buff[31] = rd32(E1000_FCRTV);
514 regs_buff[32] = rd32(E1000_RCTL);
515 regs_buff[33] = rd32(E1000_RXCSUM);
516 regs_buff[34] = rd32(E1000_RLPML);
517 regs_buff[35] = rd32(E1000_RFCTL);
518 regs_buff[36] = rd32(E1000_MRQC);
519 regs_buff[37] = rd32(E1000_VT_CTL);
522 regs_buff[38] = rd32(E1000_TCTL);
523 regs_buff[39] = rd32(E1000_TCTL_EXT);
524 regs_buff[40] = rd32(E1000_TIPG);
525 regs_buff[41] = rd32(E1000_DTXCTL);
528 regs_buff[42] = rd32(E1000_WUC);
529 regs_buff[43] = rd32(E1000_WUFC);
530 regs_buff[44] = rd32(E1000_WUS);
531 regs_buff[45] = rd32(E1000_IPAV);
532 regs_buff[46] = rd32(E1000_WUPL);
535 regs_buff[47] = rd32(E1000_PCS_CFG0);
536 regs_buff[48] = rd32(E1000_PCS_LCTL);
537 regs_buff[49] = rd32(E1000_PCS_LSTAT);
538 regs_buff[50] = rd32(E1000_PCS_ANADV);
539 regs_buff[51] = rd32(E1000_PCS_LPAB);
540 regs_buff[52] = rd32(E1000_PCS_NPTX);
541 regs_buff[53] = rd32(E1000_PCS_LPABNP);
544 regs_buff[54] = adapter->stats.crcerrs;
545 regs_buff[55] = adapter->stats.algnerrc;
546 regs_buff[56] = adapter->stats.symerrs;
547 regs_buff[57] = adapter->stats.rxerrc;
548 regs_buff[58] = adapter->stats.mpc;
549 regs_buff[59] = adapter->stats.scc;
550 regs_buff[60] = adapter->stats.ecol;
551 regs_buff[61] = adapter->stats.mcc;
552 regs_buff[62] = adapter->stats.latecol;
553 regs_buff[63] = adapter->stats.colc;
554 regs_buff[64] = adapter->stats.dc;
555 regs_buff[65] = adapter->stats.tncrs;
556 regs_buff[66] = adapter->stats.sec;
557 regs_buff[67] = adapter->stats.htdpmc;
558 regs_buff[68] = adapter->stats.rlec;
559 regs_buff[69] = adapter->stats.xonrxc;
560 regs_buff[70] = adapter->stats.xontxc;
561 regs_buff[71] = adapter->stats.xoffrxc;
562 regs_buff[72] = adapter->stats.xofftxc;
563 regs_buff[73] = adapter->stats.fcruc;
564 regs_buff[74] = adapter->stats.prc64;
565 regs_buff[75] = adapter->stats.prc127;
566 regs_buff[76] = adapter->stats.prc255;
567 regs_buff[77] = adapter->stats.prc511;
568 regs_buff[78] = adapter->stats.prc1023;
569 regs_buff[79] = adapter->stats.prc1522;
570 regs_buff[80] = adapter->stats.gprc;
571 regs_buff[81] = adapter->stats.bprc;
572 regs_buff[82] = adapter->stats.mprc;
573 regs_buff[83] = adapter->stats.gptc;
574 regs_buff[84] = adapter->stats.gorc;
575 regs_buff[86] = adapter->stats.gotc;
576 regs_buff[88] = adapter->stats.rnbc;
577 regs_buff[89] = adapter->stats.ruc;
578 regs_buff[90] = adapter->stats.rfc;
579 regs_buff[91] = adapter->stats.roc;
580 regs_buff[92] = adapter->stats.rjc;
581 regs_buff[93] = adapter->stats.mgprc;
582 regs_buff[94] = adapter->stats.mgpdc;
583 regs_buff[95] = adapter->stats.mgptc;
584 regs_buff[96] = adapter->stats.tor;
585 regs_buff[98] = adapter->stats.tot;
586 regs_buff[100] = adapter->stats.tpr;
587 regs_buff[101] = adapter->stats.tpt;
588 regs_buff[102] = adapter->stats.ptc64;
589 regs_buff[103] = adapter->stats.ptc127;
590 regs_buff[104] = adapter->stats.ptc255;
591 regs_buff[105] = adapter->stats.ptc511;
592 regs_buff[106] = adapter->stats.ptc1023;
593 regs_buff[107] = adapter->stats.ptc1522;
594 regs_buff[108] = adapter->stats.mptc;
595 regs_buff[109] = adapter->stats.bptc;
596 regs_buff[110] = adapter->stats.tsctc;
597 regs_buff[111] = adapter->stats.iac;
598 regs_buff[112] = adapter->stats.rpthc;
599 regs_buff[113] = adapter->stats.hgptc;
600 regs_buff[114] = adapter->stats.hgorc;
601 regs_buff[116] = adapter->stats.hgotc;
602 regs_buff[118] = adapter->stats.lenerrs;
603 regs_buff[119] = adapter->stats.scvpc;
604 regs_buff[120] = adapter->stats.hrmpc;
606 for (i = 0; i < 4; i++)
607 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
608 for (i = 0; i < 4; i++)
609 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
610 for (i = 0; i < 4; i++)
611 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
612 for (i = 0; i < 4; i++)
613 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
614 for (i = 0; i < 4; i++)
615 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
616 for (i = 0; i < 4; i++)
617 regs_buff[141 + i] = rd32(E1000_RDH(i));
618 for (i = 0; i < 4; i++)
619 regs_buff[145 + i] = rd32(E1000_RDT(i));
620 for (i = 0; i < 4; i++)
621 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
623 for (i = 0; i < 10; i++)
624 regs_buff[153 + i] = rd32(E1000_EITR(i));
625 for (i = 0; i < 8; i++)
626 regs_buff[163 + i] = rd32(E1000_IMIR(i));
627 for (i = 0; i < 8; i++)
628 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
629 for (i = 0; i < 16; i++)
630 regs_buff[179 + i] = rd32(E1000_RAL(i));
631 for (i = 0; i < 16; i++)
632 regs_buff[195 + i] = rd32(E1000_RAH(i));
634 for (i = 0; i < 4; i++)
635 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
636 for (i = 0; i < 4; i++)
637 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
638 for (i = 0; i < 4; i++)
639 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
640 for (i = 0; i < 4; i++)
641 regs_buff[223 + i] = rd32(E1000_TDH(i));
642 for (i = 0; i < 4; i++)
643 regs_buff[227 + i] = rd32(E1000_TDT(i));
644 for (i = 0; i < 4; i++)
645 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
646 for (i = 0; i < 4; i++)
647 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
648 for (i = 0; i < 4; i++)
649 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
650 for (i = 0; i < 4; i++)
651 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
653 for (i = 0; i < 4; i++)
654 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
655 for (i = 0; i < 4; i++)
656 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
657 for (i = 0; i < 32; i++)
658 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
659 for (i = 0; i < 128; i++)
660 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
661 for (i = 0; i < 128; i++)
662 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
663 for (i = 0; i < 4; i++)
664 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
666 regs_buff[547] = rd32(E1000_TDFH);
667 regs_buff[548] = rd32(E1000_TDFT);
668 regs_buff[549] = rd32(E1000_TDFHS);
669 regs_buff[550] = rd32(E1000_TDFPC);
671 if (hw->mac.type > e1000_82580) {
672 regs_buff[551] = adapter->stats.o2bgptc;
673 regs_buff[552] = adapter->stats.b2ospc;
674 regs_buff[553] = adapter->stats.o2bspc;
675 regs_buff[554] = adapter->stats.b2ogprc;
678 if (hw->mac.type == e1000_82576) {
679 for (i = 0; i < 12; i++)
680 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4));
681 for (i = 0; i < 4; i++)
682 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4));
683 for (i = 0; i < 12; i++)
684 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4));
685 for (i = 0; i < 12; i++)
686 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4));
687 for (i = 0; i < 12; i++)
688 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4));
689 for (i = 0; i < 12; i++)
690 regs_buff[607 + i] = rd32(E1000_RDH(i + 4));
691 for (i = 0; i < 12; i++)
692 regs_buff[619 + i] = rd32(E1000_RDT(i + 4));
693 for (i = 0; i < 12; i++)
694 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4));
696 for (i = 0; i < 12; i++)
697 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4));
698 for (i = 0; i < 12; i++)
699 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4));
700 for (i = 0; i < 12; i++)
701 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4));
702 for (i = 0; i < 12; i++)
703 regs_buff[679 + i] = rd32(E1000_TDH(i + 4));
704 for (i = 0; i < 12; i++)
705 regs_buff[691 + i] = rd32(E1000_TDT(i + 4));
706 for (i = 0; i < 12; i++)
707 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4));
708 for (i = 0; i < 12; i++)
709 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4));
710 for (i = 0; i < 12; i++)
711 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4));
714 if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211)
715 regs_buff[739] = rd32(E1000_I210_RR2DCDELAY);
718 static int igb_get_eeprom_len(struct net_device *netdev)
720 struct igb_adapter *adapter = netdev_priv(netdev);
721 return adapter->hw.nvm.word_size * 2;
724 static int igb_get_eeprom(struct net_device *netdev,
725 struct ethtool_eeprom *eeprom, u8 *bytes)
727 struct igb_adapter *adapter = netdev_priv(netdev);
728 struct e1000_hw *hw = &adapter->hw;
730 int first_word, last_word;
734 if (eeprom->len == 0)
737 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
739 first_word = eeprom->offset >> 1;
740 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
742 eeprom_buff = kmalloc_array(last_word - first_word + 1, sizeof(u16),
747 if (hw->nvm.type == e1000_nvm_eeprom_spi)
748 ret_val = hw->nvm.ops.read(hw, first_word,
749 last_word - first_word + 1,
752 for (i = 0; i < last_word - first_word + 1; i++) {
753 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
760 /* Device's eeprom is always little-endian, word addressable */
761 for (i = 0; i < last_word - first_word + 1; i++)
762 le16_to_cpus(&eeprom_buff[i]);
764 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
771 static int igb_set_eeprom(struct net_device *netdev,
772 struct ethtool_eeprom *eeprom, u8 *bytes)
774 struct igb_adapter *adapter = netdev_priv(netdev);
775 struct e1000_hw *hw = &adapter->hw;
778 int max_len, first_word, last_word, ret_val = 0;
781 if (eeprom->len == 0)
784 if ((hw->mac.type >= e1000_i210) &&
785 !igb_get_flash_presence_i210(hw)) {
789 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
792 max_len = hw->nvm.word_size * 2;
794 first_word = eeprom->offset >> 1;
795 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
796 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
800 ptr = (void *)eeprom_buff;
802 if (eeprom->offset & 1) {
803 /* need read/modify/write of first changed EEPROM word
804 * only the second byte of the word is being modified
806 ret_val = hw->nvm.ops.read(hw, first_word, 1,
810 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
811 /* need read/modify/write of last changed EEPROM word
812 * only the first byte of the word is being modified
814 ret_val = hw->nvm.ops.read(hw, last_word, 1,
815 &eeprom_buff[last_word - first_word]);
818 /* Device's eeprom is always little-endian, word addressable */
819 for (i = 0; i < last_word - first_word + 1; i++)
820 le16_to_cpus(&eeprom_buff[i]);
822 memcpy(ptr, bytes, eeprom->len);
824 for (i = 0; i < last_word - first_word + 1; i++)
825 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
827 ret_val = hw->nvm.ops.write(hw, first_word,
828 last_word - first_word + 1, eeprom_buff);
830 /* Update the checksum if nvm write succeeded */
832 hw->nvm.ops.update(hw);
834 igb_set_fw_version(adapter);
839 static void igb_get_drvinfo(struct net_device *netdev,
840 struct ethtool_drvinfo *drvinfo)
842 struct igb_adapter *adapter = netdev_priv(netdev);
844 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver));
845 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version));
847 /* EEPROM image version # is reported as firmware version # for
850 strlcpy(drvinfo->fw_version, adapter->fw_version,
851 sizeof(drvinfo->fw_version));
852 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
853 sizeof(drvinfo->bus_info));
855 drvinfo->n_priv_flags = IGB_PRIV_FLAGS_STR_LEN;
858 static void igb_get_ringparam(struct net_device *netdev,
859 struct ethtool_ringparam *ring)
861 struct igb_adapter *adapter = netdev_priv(netdev);
863 ring->rx_max_pending = IGB_MAX_RXD;
864 ring->tx_max_pending = IGB_MAX_TXD;
865 ring->rx_pending = adapter->rx_ring_count;
866 ring->tx_pending = adapter->tx_ring_count;
869 static int igb_set_ringparam(struct net_device *netdev,
870 struct ethtool_ringparam *ring)
872 struct igb_adapter *adapter = netdev_priv(netdev);
873 struct igb_ring *temp_ring;
875 u16 new_rx_count, new_tx_count;
877 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
880 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
881 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
882 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
884 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
885 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
886 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
888 if ((new_tx_count == adapter->tx_ring_count) &&
889 (new_rx_count == adapter->rx_ring_count)) {
894 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
895 usleep_range(1000, 2000);
897 if (!netif_running(adapter->netdev)) {
898 for (i = 0; i < adapter->num_tx_queues; i++)
899 adapter->tx_ring[i]->count = new_tx_count;
900 for (i = 0; i < adapter->num_rx_queues; i++)
901 adapter->rx_ring[i]->count = new_rx_count;
902 adapter->tx_ring_count = new_tx_count;
903 adapter->rx_ring_count = new_rx_count;
907 if (adapter->num_tx_queues > adapter->num_rx_queues)
908 temp_ring = vmalloc(array_size(sizeof(struct igb_ring),
909 adapter->num_tx_queues));
911 temp_ring = vmalloc(array_size(sizeof(struct igb_ring),
912 adapter->num_rx_queues));
921 /* We can't just free everything and then setup again,
922 * because the ISRs in MSI-X mode get passed pointers
923 * to the Tx and Rx ring structs.
925 if (new_tx_count != adapter->tx_ring_count) {
926 for (i = 0; i < adapter->num_tx_queues; i++) {
927 memcpy(&temp_ring[i], adapter->tx_ring[i],
928 sizeof(struct igb_ring));
930 temp_ring[i].count = new_tx_count;
931 err = igb_setup_tx_resources(&temp_ring[i]);
935 igb_free_tx_resources(&temp_ring[i]);
941 for (i = 0; i < adapter->num_tx_queues; i++) {
942 igb_free_tx_resources(adapter->tx_ring[i]);
944 memcpy(adapter->tx_ring[i], &temp_ring[i],
945 sizeof(struct igb_ring));
948 adapter->tx_ring_count = new_tx_count;
951 if (new_rx_count != adapter->rx_ring_count) {
952 for (i = 0; i < adapter->num_rx_queues; i++) {
953 memcpy(&temp_ring[i], adapter->rx_ring[i],
954 sizeof(struct igb_ring));
956 temp_ring[i].count = new_rx_count;
957 err = igb_setup_rx_resources(&temp_ring[i]);
961 igb_free_rx_resources(&temp_ring[i]);
968 for (i = 0; i < adapter->num_rx_queues; i++) {
969 igb_free_rx_resources(adapter->rx_ring[i]);
971 memcpy(adapter->rx_ring[i], &temp_ring[i],
972 sizeof(struct igb_ring));
975 adapter->rx_ring_count = new_rx_count;
981 clear_bit(__IGB_RESETTING, &adapter->state);
985 /* ethtool register test data */
986 struct igb_reg_test {
995 /* In the hardware, registers are laid out either singly, in arrays
996 * spaced 0x100 bytes apart, or in contiguous tables. We assume
997 * most tests take place on arrays or single registers (handled
998 * as a single-element array) and special-case the tables.
999 * Table tests are always pattern tests.
1001 * We also make provision for some required setup steps by specifying
1002 * registers to be written without any read-back testing.
1005 #define PATTERN_TEST 1
1006 #define SET_READ_TEST 2
1007 #define WRITE_NO_TEST 3
1008 #define TABLE32_TEST 4
1009 #define TABLE64_TEST_LO 5
1010 #define TABLE64_TEST_HI 6
1013 static struct igb_reg_test reg_test_i210[] = {
1014 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1015 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1016 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1017 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1018 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1019 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1020 /* RDH is read-only for i210, only test RDT. */
1021 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1022 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1023 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1024 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1025 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1026 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1027 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1028 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1029 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1030 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1031 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1032 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1033 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1034 0xFFFFFFFF, 0xFFFFFFFF },
1035 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1036 0x900FFFFF, 0xFFFFFFFF },
1037 { E1000_MTA, 0, 128, TABLE32_TEST,
1038 0xFFFFFFFF, 0xFFFFFFFF },
1043 static struct igb_reg_test reg_test_i350[] = {
1044 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1045 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1046 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1047 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
1048 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1049 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1050 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1051 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1052 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1053 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1054 /* RDH is read-only for i350, only test RDT. */
1055 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1056 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1057 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1058 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1059 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1060 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1061 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1062 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1063 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1064 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1065 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1066 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1067 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1068 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1069 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1070 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1071 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1072 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1073 0xFFFFFFFF, 0xFFFFFFFF },
1074 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1075 0xC3FFFFFF, 0xFFFFFFFF },
1076 { E1000_RA2, 0, 16, TABLE64_TEST_LO,
1077 0xFFFFFFFF, 0xFFFFFFFF },
1078 { E1000_RA2, 0, 16, TABLE64_TEST_HI,
1079 0xC3FFFFFF, 0xFFFFFFFF },
1080 { E1000_MTA, 0, 128, TABLE32_TEST,
1081 0xFFFFFFFF, 0xFFFFFFFF },
1085 /* 82580 reg test */
1086 static struct igb_reg_test reg_test_82580[] = {
1087 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1088 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1089 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1090 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1091 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1092 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1093 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1094 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1095 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1096 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1097 /* RDH is read-only for 82580, only test RDT. */
1098 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1099 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1100 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1101 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1102 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1103 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1104 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1105 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1106 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1107 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1108 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1109 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1110 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1111 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1112 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1113 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1114 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1115 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1116 0xFFFFFFFF, 0xFFFFFFFF },
1117 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1118 0x83FFFFFF, 0xFFFFFFFF },
1119 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
1120 0xFFFFFFFF, 0xFFFFFFFF },
1121 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
1122 0x83FFFFFF, 0xFFFFFFFF },
1123 { E1000_MTA, 0, 128, TABLE32_TEST,
1124 0xFFFFFFFF, 0xFFFFFFFF },
1128 /* 82576 reg test */
1129 static struct igb_reg_test reg_test_82576[] = {
1130 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1131 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1132 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1133 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1134 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1135 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1136 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1137 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1138 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1139 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1140 /* Enable all RX queues before testing. */
1141 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1142 E1000_RXDCTL_QUEUE_ENABLE },
1143 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0,
1144 E1000_RXDCTL_QUEUE_ENABLE },
1145 /* RDH is read-only for 82576, only test RDT. */
1146 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1147 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1148 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1149 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
1150 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1151 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1152 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1153 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1154 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1155 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1156 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1157 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1158 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1159 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1160 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1161 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1162 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1163 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1164 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1165 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1166 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1167 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1171 /* 82575 register test */
1172 static struct igb_reg_test reg_test_82575[] = {
1173 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1174 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1175 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1176 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1177 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1178 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1179 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1180 /* Enable all four RX queues before testing. */
1181 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1182 E1000_RXDCTL_QUEUE_ENABLE },
1183 /* RDH is read-only for 82575, only test RDT. */
1184 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1185 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1186 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1187 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1188 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1189 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1190 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1191 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1192 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1193 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1194 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1195 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1196 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1197 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1198 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1199 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1203 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1204 int reg, u32 mask, u32 write)
1206 struct e1000_hw *hw = &adapter->hw;
1208 static const u32 _test[] = {
1209 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1210 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
1211 wr32(reg, (_test[pat] & write));
1212 val = rd32(reg) & mask;
1213 if (val != (_test[pat] & write & mask)) {
1214 dev_err(&adapter->pdev->dev,
1215 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
1216 reg, val, (_test[pat] & write & mask));
1225 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1226 int reg, u32 mask, u32 write)
1228 struct e1000_hw *hw = &adapter->hw;
1231 wr32(reg, write & mask);
1233 if ((write & mask) != (val & mask)) {
1234 dev_err(&adapter->pdev->dev,
1235 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
1236 reg, (val & mask), (write & mask));
1244 #define REG_PATTERN_TEST(reg, mask, write) \
1246 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1250 #define REG_SET_AND_CHECK(reg, mask, write) \
1252 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1256 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1258 struct e1000_hw *hw = &adapter->hw;
1259 struct igb_reg_test *test;
1260 u32 value, before, after;
1263 switch (adapter->hw.mac.type) {
1266 test = reg_test_i350;
1267 toggle = 0x7FEFF3FF;
1271 test = reg_test_i210;
1272 toggle = 0x7FEFF3FF;
1275 test = reg_test_82580;
1276 toggle = 0x7FEFF3FF;
1279 test = reg_test_82576;
1280 toggle = 0x7FFFF3FF;
1283 test = reg_test_82575;
1284 toggle = 0x7FFFF3FF;
1288 /* Because the status register is such a special case,
1289 * we handle it separately from the rest of the register
1290 * tests. Some bits are read-only, some toggle, and some
1291 * are writable on newer MACs.
1293 before = rd32(E1000_STATUS);
1294 value = (rd32(E1000_STATUS) & toggle);
1295 wr32(E1000_STATUS, toggle);
1296 after = rd32(E1000_STATUS) & toggle;
1297 if (value != after) {
1298 dev_err(&adapter->pdev->dev,
1299 "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1304 /* restore previous status */
1305 wr32(E1000_STATUS, before);
1307 /* Perform the remainder of the register test, looping through
1308 * the test table until we either fail or reach the null entry.
1311 for (i = 0; i < test->array_len; i++) {
1312 switch (test->test_type) {
1314 REG_PATTERN_TEST(test->reg +
1315 (i * test->reg_offset),
1320 REG_SET_AND_CHECK(test->reg +
1321 (i * test->reg_offset),
1327 (adapter->hw.hw_addr + test->reg)
1328 + (i * test->reg_offset));
1331 REG_PATTERN_TEST(test->reg + (i * 4),
1335 case TABLE64_TEST_LO:
1336 REG_PATTERN_TEST(test->reg + (i * 8),
1340 case TABLE64_TEST_HI:
1341 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1354 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1356 struct e1000_hw *hw = &adapter->hw;
1360 /* Validate eeprom on all parts but flashless */
1361 switch (hw->mac.type) {
1364 if (igb_get_flash_presence_i210(hw)) {
1365 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1370 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1378 static irqreturn_t igb_test_intr(int irq, void *data)
1380 struct igb_adapter *adapter = (struct igb_adapter *) data;
1381 struct e1000_hw *hw = &adapter->hw;
1383 adapter->test_icr |= rd32(E1000_ICR);
1388 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1390 struct e1000_hw *hw = &adapter->hw;
1391 struct net_device *netdev = adapter->netdev;
1392 u32 mask, ics_mask, i = 0, shared_int = true;
1393 u32 irq = adapter->pdev->irq;
1397 /* Hook up test interrupt handler just for this test */
1398 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1399 if (request_irq(adapter->msix_entries[0].vector,
1400 igb_test_intr, 0, netdev->name, adapter)) {
1404 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1406 if (request_irq(irq,
1407 igb_test_intr, 0, netdev->name, adapter)) {
1411 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
1412 netdev->name, adapter)) {
1414 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
1415 netdev->name, adapter)) {
1419 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1420 (shared_int ? "shared" : "unshared"));
1422 /* Disable all the interrupts */
1423 wr32(E1000_IMC, ~0);
1425 usleep_range(10000, 11000);
1427 /* Define all writable bits for ICS */
1428 switch (hw->mac.type) {
1430 ics_mask = 0x37F47EDD;
1433 ics_mask = 0x77D4FBFD;
1436 ics_mask = 0x77DCFED5;
1442 ics_mask = 0x77DCFED5;
1445 ics_mask = 0x7FFFFFFF;
1449 /* Test each interrupt */
1450 for (; i < 31; i++) {
1451 /* Interrupt to test */
1454 if (!(mask & ics_mask))
1458 /* Disable the interrupt to be reported in
1459 * the cause register and then force the same
1460 * interrupt and see if one gets posted. If
1461 * an interrupt was posted to the bus, the
1464 adapter->test_icr = 0;
1466 /* Flush any pending interrupts */
1467 wr32(E1000_ICR, ~0);
1469 wr32(E1000_IMC, mask);
1470 wr32(E1000_ICS, mask);
1472 usleep_range(10000, 11000);
1474 if (adapter->test_icr & mask) {
1480 /* Enable the interrupt to be reported in
1481 * the cause register and then force the same
1482 * interrupt and see if one gets posted. If
1483 * an interrupt was not posted to the bus, the
1486 adapter->test_icr = 0;
1488 /* Flush any pending interrupts */
1489 wr32(E1000_ICR, ~0);
1491 wr32(E1000_IMS, mask);
1492 wr32(E1000_ICS, mask);
1494 usleep_range(10000, 11000);
1496 if (!(adapter->test_icr & mask)) {
1502 /* Disable the other interrupts to be reported in
1503 * the cause register and then force the other
1504 * interrupts and see if any get posted. If
1505 * an interrupt was posted to the bus, the
1508 adapter->test_icr = 0;
1510 /* Flush any pending interrupts */
1511 wr32(E1000_ICR, ~0);
1513 wr32(E1000_IMC, ~mask);
1514 wr32(E1000_ICS, ~mask);
1516 usleep_range(10000, 11000);
1518 if (adapter->test_icr & mask) {
1525 /* Disable all the interrupts */
1526 wr32(E1000_IMC, ~0);
1528 usleep_range(10000, 11000);
1530 /* Unhook test interrupt handler */
1531 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1532 free_irq(adapter->msix_entries[0].vector, adapter);
1534 free_irq(irq, adapter);
1539 static void igb_free_desc_rings(struct igb_adapter *adapter)
1541 igb_free_tx_resources(&adapter->test_tx_ring);
1542 igb_free_rx_resources(&adapter->test_rx_ring);
1545 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1547 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1548 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1549 struct e1000_hw *hw = &adapter->hw;
1552 /* Setup Tx descriptor ring and Tx buffers */
1553 tx_ring->count = IGB_DEFAULT_TXD;
1554 tx_ring->dev = &adapter->pdev->dev;
1555 tx_ring->netdev = adapter->netdev;
1556 tx_ring->reg_idx = adapter->vfs_allocated_count;
1558 if (igb_setup_tx_resources(tx_ring)) {
1563 igb_setup_tctl(adapter);
1564 igb_configure_tx_ring(adapter, tx_ring);
1566 /* Setup Rx descriptor ring and Rx buffers */
1567 rx_ring->count = IGB_DEFAULT_RXD;
1568 rx_ring->dev = &adapter->pdev->dev;
1569 rx_ring->netdev = adapter->netdev;
1570 rx_ring->reg_idx = adapter->vfs_allocated_count;
1572 if (igb_setup_rx_resources(rx_ring)) {
1577 /* set the default queue to queue 0 of PF */
1578 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
1580 /* enable receive ring */
1581 igb_setup_rctl(adapter);
1582 igb_configure_rx_ring(adapter, rx_ring);
1584 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));
1589 igb_free_desc_rings(adapter);
1593 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1595 struct e1000_hw *hw = &adapter->hw;
1597 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1598 igb_write_phy_reg(hw, 29, 0x001F);
1599 igb_write_phy_reg(hw, 30, 0x8FFC);
1600 igb_write_phy_reg(hw, 29, 0x001A);
1601 igb_write_phy_reg(hw, 30, 0x8FF0);
1604 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1606 struct e1000_hw *hw = &adapter->hw;
1609 hw->mac.autoneg = false;
1611 if (hw->phy.type == e1000_phy_m88) {
1612 if (hw->phy.id != I210_I_PHY_ID) {
1613 /* Auto-MDI/MDIX Off */
1614 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1615 /* reset to update Auto-MDI/MDIX */
1616 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1618 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1620 /* force 1000, set loopback */
1621 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0);
1622 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1624 } else if (hw->phy.type == e1000_phy_82580) {
1625 /* enable MII loopback */
1626 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
1629 /* add small delay to avoid loopback test failure */
1632 /* force 1000, set loopback */
1633 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1635 /* Now set up the MAC to the same speed/duplex as the PHY. */
1636 ctrl_reg = rd32(E1000_CTRL);
1637 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1638 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1639 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1640 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1641 E1000_CTRL_FD | /* Force Duplex to FULL */
1642 E1000_CTRL_SLU); /* Set link up enable bit */
1644 if (hw->phy.type == e1000_phy_m88)
1645 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1647 wr32(E1000_CTRL, ctrl_reg);
1649 /* Disable the receiver on the PHY so when a cable is plugged in, the
1650 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1652 if (hw->phy.type == e1000_phy_m88)
1653 igb_phy_disable_receiver(adapter);
1659 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1661 return igb_integrated_phy_loopback(adapter);
1664 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1666 struct e1000_hw *hw = &adapter->hw;
1669 reg = rd32(E1000_CTRL_EXT);
1671 /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1672 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
1673 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1674 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1675 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1676 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1677 (hw->device_id == E1000_DEV_ID_I354_SGMII) ||
1678 (hw->device_id == E1000_DEV_ID_I354_BACKPLANE_2_5GBPS)) {
1679 /* Enable DH89xxCC MPHY for near end loopback */
1680 reg = rd32(E1000_MPHY_ADDR_CTL);
1681 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1682 E1000_MPHY_PCS_CLK_REG_OFFSET;
1683 wr32(E1000_MPHY_ADDR_CTL, reg);
1685 reg = rd32(E1000_MPHY_DATA);
1686 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1687 wr32(E1000_MPHY_DATA, reg);
1690 reg = rd32(E1000_RCTL);
1691 reg |= E1000_RCTL_LBM_TCVR;
1692 wr32(E1000_RCTL, reg);
1694 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1696 reg = rd32(E1000_CTRL);
1697 reg &= ~(E1000_CTRL_RFCE |
1700 reg |= E1000_CTRL_SLU |
1702 wr32(E1000_CTRL, reg);
1704 /* Unset switch control to serdes energy detect */
1705 reg = rd32(E1000_CONNSW);
1706 reg &= ~E1000_CONNSW_ENRGSRC;
1707 wr32(E1000_CONNSW, reg);
1709 /* Unset sigdetect for SERDES loopback on
1710 * 82580 and newer devices.
1712 if (hw->mac.type >= e1000_82580) {
1713 reg = rd32(E1000_PCS_CFG0);
1714 reg |= E1000_PCS_CFG_IGN_SD;
1715 wr32(E1000_PCS_CFG0, reg);
1718 /* Set PCS register for forced speed */
1719 reg = rd32(E1000_PCS_LCTL);
1720 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1721 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1722 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1723 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1724 E1000_PCS_LCTL_FSD | /* Force Speed */
1725 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1726 wr32(E1000_PCS_LCTL, reg);
1731 return igb_set_phy_loopback(adapter);
1734 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1736 struct e1000_hw *hw = &adapter->hw;
1740 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1741 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1742 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1743 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1744 (hw->device_id == E1000_DEV_ID_I354_SGMII)) {
1747 /* Disable near end loopback on DH89xxCC */
1748 reg = rd32(E1000_MPHY_ADDR_CTL);
1749 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1750 E1000_MPHY_PCS_CLK_REG_OFFSET;
1751 wr32(E1000_MPHY_ADDR_CTL, reg);
1753 reg = rd32(E1000_MPHY_DATA);
1754 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1755 wr32(E1000_MPHY_DATA, reg);
1758 rctl = rd32(E1000_RCTL);
1759 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1760 wr32(E1000_RCTL, rctl);
1762 hw->mac.autoneg = true;
1763 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1764 if (phy_reg & MII_CR_LOOPBACK) {
1765 phy_reg &= ~MII_CR_LOOPBACK;
1766 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1767 igb_phy_sw_reset(hw);
1771 static void igb_create_lbtest_frame(struct sk_buff *skb,
1772 unsigned int frame_size)
1774 memset(skb->data, 0xFF, frame_size);
1776 memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1777 memset(&skb->data[frame_size + 10], 0xBE, 1);
1778 memset(&skb->data[frame_size + 12], 0xAF, 1);
1781 static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer,
1782 unsigned int frame_size)
1784 unsigned char *data;
1789 data = kmap(rx_buffer->page);
1791 if (data[3] != 0xFF ||
1792 data[frame_size + 10] != 0xBE ||
1793 data[frame_size + 12] != 0xAF)
1796 kunmap(rx_buffer->page);
1801 static int igb_clean_test_rings(struct igb_ring *rx_ring,
1802 struct igb_ring *tx_ring,
1805 union e1000_adv_rx_desc *rx_desc;
1806 struct igb_rx_buffer *rx_buffer_info;
1807 struct igb_tx_buffer *tx_buffer_info;
1808 u16 rx_ntc, tx_ntc, count = 0;
1810 /* initialize next to clean and descriptor values */
1811 rx_ntc = rx_ring->next_to_clean;
1812 tx_ntc = tx_ring->next_to_clean;
1813 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1815 while (rx_desc->wb.upper.length) {
1816 /* check Rx buffer */
1817 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1819 /* sync Rx buffer for CPU read */
1820 dma_sync_single_for_cpu(rx_ring->dev,
1821 rx_buffer_info->dma,
1825 /* verify contents of skb */
1826 if (igb_check_lbtest_frame(rx_buffer_info, size))
1829 /* sync Rx buffer for device write */
1830 dma_sync_single_for_device(rx_ring->dev,
1831 rx_buffer_info->dma,
1835 /* unmap buffer on Tx side */
1836 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1838 /* Free all the Tx ring sk_buffs */
1839 dev_kfree_skb_any(tx_buffer_info->skb);
1841 /* unmap skb header data */
1842 dma_unmap_single(tx_ring->dev,
1843 dma_unmap_addr(tx_buffer_info, dma),
1844 dma_unmap_len(tx_buffer_info, len),
1846 dma_unmap_len_set(tx_buffer_info, len, 0);
1848 /* increment Rx/Tx next to clean counters */
1850 if (rx_ntc == rx_ring->count)
1853 if (tx_ntc == tx_ring->count)
1856 /* fetch next descriptor */
1857 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1860 netdev_tx_reset_queue(txring_txq(tx_ring));
1862 /* re-map buffers to ring, store next to clean values */
1863 igb_alloc_rx_buffers(rx_ring, count);
1864 rx_ring->next_to_clean = rx_ntc;
1865 tx_ring->next_to_clean = tx_ntc;
1870 static int igb_run_loopback_test(struct igb_adapter *adapter)
1872 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1873 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1874 u16 i, j, lc, good_cnt;
1876 unsigned int size = IGB_RX_HDR_LEN;
1877 netdev_tx_t tx_ret_val;
1878 struct sk_buff *skb;
1880 /* allocate test skb */
1881 skb = alloc_skb(size, GFP_KERNEL);
1885 /* place data into test skb */
1886 igb_create_lbtest_frame(skb, size);
1889 /* Calculate the loop count based on the largest descriptor ring
1890 * The idea is to wrap the largest ring a number of times using 64
1891 * send/receive pairs during each loop
1894 if (rx_ring->count <= tx_ring->count)
1895 lc = ((tx_ring->count / 64) * 2) + 1;
1897 lc = ((rx_ring->count / 64) * 2) + 1;
1899 for (j = 0; j <= lc; j++) { /* loop count loop */
1900 /* reset count of good packets */
1903 /* place 64 packets on the transmit queue*/
1904 for (i = 0; i < 64; i++) {
1906 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);
1907 if (tx_ret_val == NETDEV_TX_OK)
1911 if (good_cnt != 64) {
1916 /* allow 200 milliseconds for packets to go from Tx to Rx */
1919 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1920 if (good_cnt != 64) {
1924 } /* end loop count loop */
1926 /* free the original skb */
1932 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1934 /* PHY loopback cannot be performed if SoL/IDER
1935 * sessions are active
1937 if (igb_check_reset_block(&adapter->hw)) {
1938 dev_err(&adapter->pdev->dev,
1939 "Cannot do PHY loopback test when SoL/IDER is active.\n");
1944 if (adapter->hw.mac.type == e1000_i354) {
1945 dev_info(&adapter->pdev->dev,
1946 "Loopback test not supported on i354.\n");
1950 *data = igb_setup_desc_rings(adapter);
1953 *data = igb_setup_loopback_test(adapter);
1956 *data = igb_run_loopback_test(adapter);
1957 igb_loopback_cleanup(adapter);
1960 igb_free_desc_rings(adapter);
1965 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1967 struct e1000_hw *hw = &adapter->hw;
1969 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1972 hw->mac.serdes_has_link = false;
1974 /* On some blade server designs, link establishment
1975 * could take as long as 2-3 minutes
1978 hw->mac.ops.check_for_link(&adapter->hw);
1979 if (hw->mac.serdes_has_link)
1982 } while (i++ < 3750);
1986 hw->mac.ops.check_for_link(&adapter->hw);
1987 if (hw->mac.autoneg)
1990 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
1996 static void igb_diag_test(struct net_device *netdev,
1997 struct ethtool_test *eth_test, u64 *data)
1999 struct igb_adapter *adapter = netdev_priv(netdev);
2000 u16 autoneg_advertised;
2001 u8 forced_speed_duplex, autoneg;
2002 bool if_running = netif_running(netdev);
2004 set_bit(__IGB_TESTING, &adapter->state);
2006 /* can't do offline tests on media switching devices */
2007 if (adapter->hw.dev_spec._82575.mas_capable)
2008 eth_test->flags &= ~ETH_TEST_FL_OFFLINE;
2009 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
2012 /* save speed, duplex, autoneg settings */
2013 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
2014 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
2015 autoneg = adapter->hw.mac.autoneg;
2017 dev_info(&adapter->pdev->dev, "offline testing starting\n");
2019 /* power up link for link test */
2020 igb_power_up_link(adapter);
2022 /* Link test performed before hardware reset so autoneg doesn't
2023 * interfere with test result
2025 if (igb_link_test(adapter, &data[TEST_LINK]))
2026 eth_test->flags |= ETH_TEST_FL_FAILED;
2029 /* indicate we're in test mode */
2034 if (igb_reg_test(adapter, &data[TEST_REG]))
2035 eth_test->flags |= ETH_TEST_FL_FAILED;
2038 if (igb_eeprom_test(adapter, &data[TEST_EEP]))
2039 eth_test->flags |= ETH_TEST_FL_FAILED;
2042 if (igb_intr_test(adapter, &data[TEST_IRQ]))
2043 eth_test->flags |= ETH_TEST_FL_FAILED;
2046 /* power up link for loopback test */
2047 igb_power_up_link(adapter);
2048 if (igb_loopback_test(adapter, &data[TEST_LOOP]))
2049 eth_test->flags |= ETH_TEST_FL_FAILED;
2051 /* restore speed, duplex, autoneg settings */
2052 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
2053 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
2054 adapter->hw.mac.autoneg = autoneg;
2056 /* force this routine to wait until autoneg complete/timeout */
2057 adapter->hw.phy.autoneg_wait_to_complete = true;
2059 adapter->hw.phy.autoneg_wait_to_complete = false;
2061 clear_bit(__IGB_TESTING, &adapter->state);
2065 dev_info(&adapter->pdev->dev, "online testing starting\n");
2067 /* PHY is powered down when interface is down */
2068 if (if_running && igb_link_test(adapter, &data[TEST_LINK]))
2069 eth_test->flags |= ETH_TEST_FL_FAILED;
2071 data[TEST_LINK] = 0;
2073 /* Online tests aren't run; pass by default */
2077 data[TEST_LOOP] = 0;
2079 clear_bit(__IGB_TESTING, &adapter->state);
2081 msleep_interruptible(4 * 1000);
2084 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2086 struct igb_adapter *adapter = netdev_priv(netdev);
2090 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2093 wol->supported = WAKE_UCAST | WAKE_MCAST |
2094 WAKE_BCAST | WAKE_MAGIC |
2097 /* apply any specific unsupported masks here */
2098 switch (adapter->hw.device_id) {
2103 if (adapter->wol & E1000_WUFC_EX)
2104 wol->wolopts |= WAKE_UCAST;
2105 if (adapter->wol & E1000_WUFC_MC)
2106 wol->wolopts |= WAKE_MCAST;
2107 if (adapter->wol & E1000_WUFC_BC)
2108 wol->wolopts |= WAKE_BCAST;
2109 if (adapter->wol & E1000_WUFC_MAG)
2110 wol->wolopts |= WAKE_MAGIC;
2111 if (adapter->wol & E1000_WUFC_LNKC)
2112 wol->wolopts |= WAKE_PHY;
2115 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2117 struct igb_adapter *adapter = netdev_priv(netdev);
2119 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE | WAKE_FILTER))
2122 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2123 return wol->wolopts ? -EOPNOTSUPP : 0;
2125 /* these settings will always override what we currently have */
2128 if (wol->wolopts & WAKE_UCAST)
2129 adapter->wol |= E1000_WUFC_EX;
2130 if (wol->wolopts & WAKE_MCAST)
2131 adapter->wol |= E1000_WUFC_MC;
2132 if (wol->wolopts & WAKE_BCAST)
2133 adapter->wol |= E1000_WUFC_BC;
2134 if (wol->wolopts & WAKE_MAGIC)
2135 adapter->wol |= E1000_WUFC_MAG;
2136 if (wol->wolopts & WAKE_PHY)
2137 adapter->wol |= E1000_WUFC_LNKC;
2138 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2143 /* bit defines for adapter->led_status */
2144 #define IGB_LED_ON 0
2146 static int igb_set_phys_id(struct net_device *netdev,
2147 enum ethtool_phys_id_state state)
2149 struct igb_adapter *adapter = netdev_priv(netdev);
2150 struct e1000_hw *hw = &adapter->hw;
2153 case ETHTOOL_ID_ACTIVE:
2159 case ETHTOOL_ID_OFF:
2162 case ETHTOOL_ID_INACTIVE:
2164 clear_bit(IGB_LED_ON, &adapter->led_status);
2165 igb_cleanup_led(hw);
2172 static int igb_set_coalesce(struct net_device *netdev,
2173 struct ethtool_coalesce *ec)
2175 struct igb_adapter *adapter = netdev_priv(netdev);
2178 if (ec->rx_max_coalesced_frames ||
2179 ec->rx_coalesce_usecs_irq ||
2180 ec->rx_max_coalesced_frames_irq ||
2181 ec->tx_max_coalesced_frames ||
2182 ec->tx_coalesce_usecs_irq ||
2183 ec->stats_block_coalesce_usecs ||
2184 ec->use_adaptive_rx_coalesce ||
2185 ec->use_adaptive_tx_coalesce ||
2187 ec->rx_coalesce_usecs_low ||
2188 ec->rx_max_coalesced_frames_low ||
2189 ec->tx_coalesce_usecs_low ||
2190 ec->tx_max_coalesced_frames_low ||
2191 ec->pkt_rate_high ||
2192 ec->rx_coalesce_usecs_high ||
2193 ec->rx_max_coalesced_frames_high ||
2194 ec->tx_coalesce_usecs_high ||
2195 ec->tx_max_coalesced_frames_high ||
2196 ec->rate_sample_interval)
2199 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2200 ((ec->rx_coalesce_usecs > 3) &&
2201 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2202 (ec->rx_coalesce_usecs == 2))
2205 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2206 ((ec->tx_coalesce_usecs > 3) &&
2207 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2208 (ec->tx_coalesce_usecs == 2))
2211 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2214 /* If ITR is disabled, disable DMAC */
2215 if (ec->rx_coalesce_usecs == 0) {
2216 if (adapter->flags & IGB_FLAG_DMAC)
2217 adapter->flags &= ~IGB_FLAG_DMAC;
2220 /* convert to rate of irq's per second */
2221 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2222 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2224 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2226 /* convert to rate of irq's per second */
2227 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2228 adapter->tx_itr_setting = adapter->rx_itr_setting;
2229 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2230 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2232 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2234 for (i = 0; i < adapter->num_q_vectors; i++) {
2235 struct igb_q_vector *q_vector = adapter->q_vector[i];
2236 q_vector->tx.work_limit = adapter->tx_work_limit;
2237 if (q_vector->rx.ring)
2238 q_vector->itr_val = adapter->rx_itr_setting;
2240 q_vector->itr_val = adapter->tx_itr_setting;
2241 if (q_vector->itr_val && q_vector->itr_val <= 3)
2242 q_vector->itr_val = IGB_START_ITR;
2243 q_vector->set_itr = 1;
2249 static int igb_get_coalesce(struct net_device *netdev,
2250 struct ethtool_coalesce *ec)
2252 struct igb_adapter *adapter = netdev_priv(netdev);
2254 if (adapter->rx_itr_setting <= 3)
2255 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2257 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2259 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2260 if (adapter->tx_itr_setting <= 3)
2261 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2263 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2269 static int igb_nway_reset(struct net_device *netdev)
2271 struct igb_adapter *adapter = netdev_priv(netdev);
2272 if (netif_running(netdev))
2273 igb_reinit_locked(adapter);
2277 static int igb_get_sset_count(struct net_device *netdev, int sset)
2281 return IGB_STATS_LEN;
2283 return IGB_TEST_LEN;
2284 case ETH_SS_PRIV_FLAGS:
2285 return IGB_PRIV_FLAGS_STR_LEN;
2291 static void igb_get_ethtool_stats(struct net_device *netdev,
2292 struct ethtool_stats *stats, u64 *data)
2294 struct igb_adapter *adapter = netdev_priv(netdev);
2295 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2297 struct igb_ring *ring;
2301 spin_lock(&adapter->stats64_lock);
2302 igb_update_stats(adapter);
2304 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2305 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
2306 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2307 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2309 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2310 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2311 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2312 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2314 for (j = 0; j < adapter->num_tx_queues; j++) {
2317 ring = adapter->tx_ring[j];
2319 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
2320 data[i] = ring->tx_stats.packets;
2321 data[i+1] = ring->tx_stats.bytes;
2322 data[i+2] = ring->tx_stats.restart_queue;
2323 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
2325 start = u64_stats_fetch_begin_irq(&ring->tx_syncp2);
2326 restart2 = ring->tx_stats.restart_queue2;
2327 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp2, start));
2328 data[i+2] += restart2;
2330 i += IGB_TX_QUEUE_STATS_LEN;
2332 for (j = 0; j < adapter->num_rx_queues; j++) {
2333 ring = adapter->rx_ring[j];
2335 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
2336 data[i] = ring->rx_stats.packets;
2337 data[i+1] = ring->rx_stats.bytes;
2338 data[i+2] = ring->rx_stats.drops;
2339 data[i+3] = ring->rx_stats.csum_err;
2340 data[i+4] = ring->rx_stats.alloc_failed;
2341 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
2342 i += IGB_RX_QUEUE_STATS_LEN;
2344 spin_unlock(&adapter->stats64_lock);
2347 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2349 struct igb_adapter *adapter = netdev_priv(netdev);
2353 switch (stringset) {
2355 memcpy(data, *igb_gstrings_test,
2356 IGB_TEST_LEN*ETH_GSTRING_LEN);
2359 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2360 memcpy(p, igb_gstrings_stats[i].stat_string,
2362 p += ETH_GSTRING_LEN;
2364 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2365 memcpy(p, igb_gstrings_net_stats[i].stat_string,
2367 p += ETH_GSTRING_LEN;
2369 for (i = 0; i < adapter->num_tx_queues; i++) {
2370 sprintf(p, "tx_queue_%u_packets", i);
2371 p += ETH_GSTRING_LEN;
2372 sprintf(p, "tx_queue_%u_bytes", i);
2373 p += ETH_GSTRING_LEN;
2374 sprintf(p, "tx_queue_%u_restart", i);
2375 p += ETH_GSTRING_LEN;
2377 for (i = 0; i < adapter->num_rx_queues; i++) {
2378 sprintf(p, "rx_queue_%u_packets", i);
2379 p += ETH_GSTRING_LEN;
2380 sprintf(p, "rx_queue_%u_bytes", i);
2381 p += ETH_GSTRING_LEN;
2382 sprintf(p, "rx_queue_%u_drops", i);
2383 p += ETH_GSTRING_LEN;
2384 sprintf(p, "rx_queue_%u_csum_err", i);
2385 p += ETH_GSTRING_LEN;
2386 sprintf(p, "rx_queue_%u_alloc_failed", i);
2387 p += ETH_GSTRING_LEN;
2389 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2391 case ETH_SS_PRIV_FLAGS:
2392 memcpy(data, igb_priv_flags_strings,
2393 IGB_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN);
2398 static int igb_get_ts_info(struct net_device *dev,
2399 struct ethtool_ts_info *info)
2401 struct igb_adapter *adapter = netdev_priv(dev);
2403 if (adapter->ptp_clock)
2404 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2406 info->phc_index = -1;
2408 switch (adapter->hw.mac.type) {
2410 info->so_timestamping =
2411 SOF_TIMESTAMPING_TX_SOFTWARE |
2412 SOF_TIMESTAMPING_RX_SOFTWARE |
2413 SOF_TIMESTAMPING_SOFTWARE;
2421 info->so_timestamping =
2422 SOF_TIMESTAMPING_TX_SOFTWARE |
2423 SOF_TIMESTAMPING_RX_SOFTWARE |
2424 SOF_TIMESTAMPING_SOFTWARE |
2425 SOF_TIMESTAMPING_TX_HARDWARE |
2426 SOF_TIMESTAMPING_RX_HARDWARE |
2427 SOF_TIMESTAMPING_RAW_HARDWARE;
2430 BIT(HWTSTAMP_TX_OFF) |
2431 BIT(HWTSTAMP_TX_ON);
2433 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE);
2435 /* 82576 does not support timestamping all packets. */
2436 if (adapter->hw.mac.type >= e1000_82580)
2437 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL);
2440 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2441 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2442 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT);
2450 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0)
2451 static int igb_get_ethtool_nfc_entry(struct igb_adapter *adapter,
2452 struct ethtool_rxnfc *cmd)
2454 struct ethtool_rx_flow_spec *fsp = &cmd->fs;
2455 struct igb_nfc_filter *rule = NULL;
2457 /* report total rule count */
2458 cmd->data = IGB_MAX_RXNFC_FILTERS;
2460 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2461 if (fsp->location <= rule->sw_idx)
2465 if (!rule || fsp->location != rule->sw_idx)
2468 if (rule->filter.match_flags) {
2469 fsp->flow_type = ETHER_FLOW;
2470 fsp->ring_cookie = rule->action;
2471 if (rule->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) {
2472 fsp->h_u.ether_spec.h_proto = rule->filter.etype;
2473 fsp->m_u.ether_spec.h_proto = ETHER_TYPE_FULL_MASK;
2475 if (rule->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) {
2476 fsp->flow_type |= FLOW_EXT;
2477 fsp->h_ext.vlan_tci = rule->filter.vlan_tci;
2478 fsp->m_ext.vlan_tci = htons(VLAN_PRIO_MASK);
2480 if (rule->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR) {
2481 ether_addr_copy(fsp->h_u.ether_spec.h_dest,
2482 rule->filter.dst_addr);
2483 /* As we only support matching by the full
2484 * mask, return the mask to userspace
2486 eth_broadcast_addr(fsp->m_u.ether_spec.h_dest);
2488 if (rule->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR) {
2489 ether_addr_copy(fsp->h_u.ether_spec.h_source,
2490 rule->filter.src_addr);
2491 /* As we only support matching by the full
2492 * mask, return the mask to userspace
2494 eth_broadcast_addr(fsp->m_u.ether_spec.h_source);
2502 static int igb_get_ethtool_nfc_all(struct igb_adapter *adapter,
2503 struct ethtool_rxnfc *cmd,
2506 struct igb_nfc_filter *rule;
2509 /* report total rule count */
2510 cmd->data = IGB_MAX_RXNFC_FILTERS;
2512 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2513 if (cnt == cmd->rule_cnt)
2515 rule_locs[cnt] = rule->sw_idx;
2519 cmd->rule_cnt = cnt;
2524 static int igb_get_rss_hash_opts(struct igb_adapter *adapter,
2525 struct ethtool_rxnfc *cmd)
2529 /* Report default options for RSS on igb */
2530 switch (cmd->flow_type) {
2532 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2535 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2536 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2539 case AH_ESP_V4_FLOW:
2543 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2546 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2549 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2550 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2553 case AH_ESP_V6_FLOW:
2557 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2566 static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2569 struct igb_adapter *adapter = netdev_priv(dev);
2570 int ret = -EOPNOTSUPP;
2573 case ETHTOOL_GRXRINGS:
2574 cmd->data = adapter->num_rx_queues;
2577 case ETHTOOL_GRXCLSRLCNT:
2578 cmd->rule_cnt = adapter->nfc_filter_count;
2581 case ETHTOOL_GRXCLSRULE:
2582 ret = igb_get_ethtool_nfc_entry(adapter, cmd);
2584 case ETHTOOL_GRXCLSRLALL:
2585 ret = igb_get_ethtool_nfc_all(adapter, cmd, rule_locs);
2588 ret = igb_get_rss_hash_opts(adapter, cmd);
2597 #define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \
2598 IGB_FLAG_RSS_FIELD_IPV6_UDP)
2599 static int igb_set_rss_hash_opt(struct igb_adapter *adapter,
2600 struct ethtool_rxnfc *nfc)
2602 u32 flags = adapter->flags;
2604 /* RSS does not support anything other than hashing
2605 * to queues on src and dst IPs and ports
2607 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2608 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2611 switch (nfc->flow_type) {
2614 if (!(nfc->data & RXH_IP_SRC) ||
2615 !(nfc->data & RXH_IP_DST) ||
2616 !(nfc->data & RXH_L4_B_0_1) ||
2617 !(nfc->data & RXH_L4_B_2_3))
2621 if (!(nfc->data & RXH_IP_SRC) ||
2622 !(nfc->data & RXH_IP_DST))
2624 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2626 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP;
2628 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2629 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP;
2636 if (!(nfc->data & RXH_IP_SRC) ||
2637 !(nfc->data & RXH_IP_DST))
2639 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2641 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP;
2643 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2644 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP;
2650 case AH_ESP_V4_FLOW:
2654 case AH_ESP_V6_FLOW:
2658 if (!(nfc->data & RXH_IP_SRC) ||
2659 !(nfc->data & RXH_IP_DST) ||
2660 (nfc->data & RXH_L4_B_0_1) ||
2661 (nfc->data & RXH_L4_B_2_3))
2668 /* if we changed something we need to update flags */
2669 if (flags != adapter->flags) {
2670 struct e1000_hw *hw = &adapter->hw;
2671 u32 mrqc = rd32(E1000_MRQC);
2673 if ((flags & UDP_RSS_FLAGS) &&
2674 !(adapter->flags & UDP_RSS_FLAGS))
2675 dev_err(&adapter->pdev->dev,
2676 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2678 adapter->flags = flags;
2680 /* Perform hash on these packet types */
2681 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2682 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2683 E1000_MRQC_RSS_FIELD_IPV6 |
2684 E1000_MRQC_RSS_FIELD_IPV6_TCP;
2686 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP |
2687 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2689 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2690 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2692 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2693 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2695 wr32(E1000_MRQC, mrqc);
2701 static int igb_rxnfc_write_etype_filter(struct igb_adapter *adapter,
2702 struct igb_nfc_filter *input)
2704 struct e1000_hw *hw = &adapter->hw;
2709 /* find an empty etype filter register */
2710 for (i = 0; i < MAX_ETYPE_FILTER; ++i) {
2711 if (!adapter->etype_bitmap[i])
2714 if (i == MAX_ETYPE_FILTER) {
2715 dev_err(&adapter->pdev->dev, "ethtool -N: etype filters are all used.\n");
2719 adapter->etype_bitmap[i] = true;
2721 etqf = rd32(E1000_ETQF(i));
2722 etype = ntohs(input->filter.etype & ETHER_TYPE_FULL_MASK);
2724 etqf |= E1000_ETQF_FILTER_ENABLE;
2725 etqf &= ~E1000_ETQF_ETYPE_MASK;
2726 etqf |= (etype & E1000_ETQF_ETYPE_MASK);
2728 etqf &= ~E1000_ETQF_QUEUE_MASK;
2729 etqf |= ((input->action << E1000_ETQF_QUEUE_SHIFT)
2730 & E1000_ETQF_QUEUE_MASK);
2731 etqf |= E1000_ETQF_QUEUE_ENABLE;
2733 wr32(E1000_ETQF(i), etqf);
2735 input->etype_reg_index = i;
2740 static int igb_rxnfc_write_vlan_prio_filter(struct igb_adapter *adapter,
2741 struct igb_nfc_filter *input)
2743 struct e1000_hw *hw = &adapter->hw;
2748 vlapqf = rd32(E1000_VLAPQF);
2749 vlan_priority = (ntohs(input->filter.vlan_tci) & VLAN_PRIO_MASK)
2751 queue_index = (vlapqf >> (vlan_priority * 4)) & E1000_VLAPQF_QUEUE_MASK;
2753 /* check whether this vlan prio is already set */
2754 if ((vlapqf & E1000_VLAPQF_P_VALID(vlan_priority)) &&
2755 (queue_index != input->action)) {
2756 dev_err(&adapter->pdev->dev, "ethtool rxnfc set vlan prio filter failed.\n");
2760 vlapqf |= E1000_VLAPQF_P_VALID(vlan_priority);
2761 vlapqf |= E1000_VLAPQF_QUEUE_SEL(vlan_priority, input->action);
2763 wr32(E1000_VLAPQF, vlapqf);
2768 int igb_add_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input)
2770 struct e1000_hw *hw = &adapter->hw;
2773 if (hw->mac.type == e1000_i210 &&
2774 !(input->filter.match_flags & ~IGB_FILTER_FLAG_SRC_MAC_ADDR)) {
2775 dev_err(&adapter->pdev->dev,
2776 "i210 doesn't support flow classification rules specifying only source addresses.\n");
2780 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) {
2781 err = igb_rxnfc_write_etype_filter(adapter, input);
2786 if (input->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR) {
2787 err = igb_add_mac_steering_filter(adapter,
2788 input->filter.dst_addr,
2790 err = min_t(int, err, 0);
2795 if (input->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR) {
2796 err = igb_add_mac_steering_filter(adapter,
2797 input->filter.src_addr,
2799 IGB_MAC_STATE_SRC_ADDR);
2800 err = min_t(int, err, 0);
2805 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI)
2806 err = igb_rxnfc_write_vlan_prio_filter(adapter, input);
2811 static void igb_clear_etype_filter_regs(struct igb_adapter *adapter,
2814 struct e1000_hw *hw = &adapter->hw;
2815 u32 etqf = rd32(E1000_ETQF(reg_index));
2817 etqf &= ~E1000_ETQF_QUEUE_ENABLE;
2818 etqf &= ~E1000_ETQF_QUEUE_MASK;
2819 etqf &= ~E1000_ETQF_FILTER_ENABLE;
2821 wr32(E1000_ETQF(reg_index), etqf);
2823 adapter->etype_bitmap[reg_index] = false;
2826 static void igb_clear_vlan_prio_filter(struct igb_adapter *adapter,
2829 struct e1000_hw *hw = &adapter->hw;
2833 vlan_priority = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
2835 vlapqf = rd32(E1000_VLAPQF);
2836 vlapqf &= ~E1000_VLAPQF_P_VALID(vlan_priority);
2837 vlapqf &= ~E1000_VLAPQF_QUEUE_SEL(vlan_priority,
2838 E1000_VLAPQF_QUEUE_MASK);
2840 wr32(E1000_VLAPQF, vlapqf);
2843 int igb_erase_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input)
2845 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE)
2846 igb_clear_etype_filter_regs(adapter,
2847 input->etype_reg_index);
2849 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI)
2850 igb_clear_vlan_prio_filter(adapter,
2851 ntohs(input->filter.vlan_tci));
2853 if (input->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR)
2854 igb_del_mac_steering_filter(adapter, input->filter.src_addr,
2856 IGB_MAC_STATE_SRC_ADDR);
2858 if (input->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR)
2859 igb_del_mac_steering_filter(adapter, input->filter.dst_addr,
2865 static int igb_update_ethtool_nfc_entry(struct igb_adapter *adapter,
2866 struct igb_nfc_filter *input,
2869 struct igb_nfc_filter *rule, *parent;
2875 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2876 /* hash found, or no matching entry */
2877 if (rule->sw_idx >= sw_idx)
2882 /* if there is an old rule occupying our place remove it */
2883 if (rule && (rule->sw_idx == sw_idx)) {
2885 err = igb_erase_filter(adapter, rule);
2887 hlist_del(&rule->nfc_node);
2889 adapter->nfc_filter_count--;
2892 /* If no input this was a delete, err should be 0 if a rule was
2893 * successfully found and removed from the list else -EINVAL
2898 /* initialize node */
2899 INIT_HLIST_NODE(&input->nfc_node);
2901 /* add filter to the list */
2903 hlist_add_behind(&input->nfc_node, &parent->nfc_node);
2905 hlist_add_head(&input->nfc_node, &adapter->nfc_filter_list);
2908 adapter->nfc_filter_count++;
2913 static int igb_add_ethtool_nfc_entry(struct igb_adapter *adapter,
2914 struct ethtool_rxnfc *cmd)
2916 struct net_device *netdev = adapter->netdev;
2917 struct ethtool_rx_flow_spec *fsp =
2918 (struct ethtool_rx_flow_spec *)&cmd->fs;
2919 struct igb_nfc_filter *input, *rule;
2922 if (!(netdev->hw_features & NETIF_F_NTUPLE))
2925 /* Don't allow programming if the action is a queue greater than
2926 * the number of online Rx queues.
2928 if ((fsp->ring_cookie == RX_CLS_FLOW_DISC) ||
2929 (fsp->ring_cookie >= adapter->num_rx_queues)) {
2930 dev_err(&adapter->pdev->dev, "ethtool -N: The specified action is invalid\n");
2934 /* Don't allow indexes to exist outside of available space */
2935 if (fsp->location >= IGB_MAX_RXNFC_FILTERS) {
2936 dev_err(&adapter->pdev->dev, "Location out of range\n");
2940 if ((fsp->flow_type & ~FLOW_EXT) != ETHER_FLOW)
2943 input = kzalloc(sizeof(*input), GFP_KERNEL);
2947 if (fsp->m_u.ether_spec.h_proto == ETHER_TYPE_FULL_MASK) {
2948 input->filter.etype = fsp->h_u.ether_spec.h_proto;
2949 input->filter.match_flags = IGB_FILTER_FLAG_ETHER_TYPE;
2952 /* Only support matching addresses by the full mask */
2953 if (is_broadcast_ether_addr(fsp->m_u.ether_spec.h_source)) {
2954 input->filter.match_flags |= IGB_FILTER_FLAG_SRC_MAC_ADDR;
2955 ether_addr_copy(input->filter.src_addr,
2956 fsp->h_u.ether_spec.h_source);
2959 /* Only support matching addresses by the full mask */
2960 if (is_broadcast_ether_addr(fsp->m_u.ether_spec.h_dest)) {
2961 input->filter.match_flags |= IGB_FILTER_FLAG_DST_MAC_ADDR;
2962 ether_addr_copy(input->filter.dst_addr,
2963 fsp->h_u.ether_spec.h_dest);
2966 if ((fsp->flow_type & FLOW_EXT) && fsp->m_ext.vlan_tci) {
2967 if (fsp->m_ext.vlan_tci != htons(VLAN_PRIO_MASK)) {
2971 input->filter.vlan_tci = fsp->h_ext.vlan_tci;
2972 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI;
2975 input->action = fsp->ring_cookie;
2976 input->sw_idx = fsp->location;
2978 spin_lock(&adapter->nfc_lock);
2980 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2981 if (!memcmp(&input->filter, &rule->filter,
2982 sizeof(input->filter))) {
2984 dev_err(&adapter->pdev->dev,
2985 "ethtool: this filter is already set\n");
2986 goto err_out_w_lock;
2990 err = igb_add_filter(adapter, input);
2992 goto err_out_w_lock;
2994 igb_update_ethtool_nfc_entry(adapter, input, input->sw_idx);
2996 spin_unlock(&adapter->nfc_lock);
3000 spin_unlock(&adapter->nfc_lock);
3006 static int igb_del_ethtool_nfc_entry(struct igb_adapter *adapter,
3007 struct ethtool_rxnfc *cmd)
3009 struct ethtool_rx_flow_spec *fsp =
3010 (struct ethtool_rx_flow_spec *)&cmd->fs;
3013 spin_lock(&adapter->nfc_lock);
3014 err = igb_update_ethtool_nfc_entry(adapter, NULL, fsp->location);
3015 spin_unlock(&adapter->nfc_lock);
3020 static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
3022 struct igb_adapter *adapter = netdev_priv(dev);
3023 int ret = -EOPNOTSUPP;
3027 ret = igb_set_rss_hash_opt(adapter, cmd);
3029 case ETHTOOL_SRXCLSRLINS:
3030 ret = igb_add_ethtool_nfc_entry(adapter, cmd);
3032 case ETHTOOL_SRXCLSRLDEL:
3033 ret = igb_del_ethtool_nfc_entry(adapter, cmd);
3041 static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
3043 struct igb_adapter *adapter = netdev_priv(netdev);
3044 struct e1000_hw *hw = &adapter->hw;
3048 if ((hw->mac.type < e1000_i350) ||
3049 (hw->phy.media_type != e1000_media_type_copper))
3052 edata->supported = (SUPPORTED_1000baseT_Full |
3053 SUPPORTED_100baseT_Full);
3054 if (!hw->dev_spec._82575.eee_disable)
3056 mmd_eee_adv_to_ethtool_adv_t(adapter->eee_advert);
3058 /* The IPCNFG and EEER registers are not supported on I354. */
3059 if (hw->mac.type == e1000_i354) {
3060 igb_get_eee_status_i354(hw, (bool *)&edata->eee_active);
3064 eeer = rd32(E1000_EEER);
3066 /* EEE status on negotiated link */
3067 if (eeer & E1000_EEER_EEE_NEG)
3068 edata->eee_active = true;
3070 if (eeer & E1000_EEER_TX_LPI_EN)
3071 edata->tx_lpi_enabled = true;
3074 /* EEE Link Partner Advertised */
3075 switch (hw->mac.type) {
3077 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350,
3082 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
3087 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210,
3088 E1000_EEE_LP_ADV_DEV_I210,
3093 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
3100 edata->eee_enabled = !hw->dev_spec._82575.eee_disable;
3102 if ((hw->mac.type == e1000_i354) &&
3103 (edata->eee_enabled))
3104 edata->tx_lpi_enabled = true;
3106 /* Report correct negotiated EEE status for devices that
3107 * wrongly report EEE at half-duplex
3109 if (adapter->link_duplex == HALF_DUPLEX) {
3110 edata->eee_enabled = false;
3111 edata->eee_active = false;
3112 edata->tx_lpi_enabled = false;
3113 edata->advertised &= ~edata->advertised;
3119 static int igb_set_eee(struct net_device *netdev,
3120 struct ethtool_eee *edata)
3122 struct igb_adapter *adapter = netdev_priv(netdev);
3123 struct e1000_hw *hw = &adapter->hw;
3124 struct ethtool_eee eee_curr;
3125 bool adv1g_eee = true, adv100m_eee = true;
3128 if ((hw->mac.type < e1000_i350) ||
3129 (hw->phy.media_type != e1000_media_type_copper))
3132 memset(&eee_curr, 0, sizeof(struct ethtool_eee));
3134 ret_val = igb_get_eee(netdev, &eee_curr);
3138 if (eee_curr.eee_enabled) {
3139 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) {
3140 dev_err(&adapter->pdev->dev,
3141 "Setting EEE tx-lpi is not supported\n");
3145 /* Tx LPI timer is not implemented currently */
3146 if (edata->tx_lpi_timer) {
3147 dev_err(&adapter->pdev->dev,
3148 "Setting EEE Tx LPI timer is not supported\n");
3152 if (!edata->advertised || (edata->advertised &
3153 ~(ADVERTISE_100_FULL | ADVERTISE_1000_FULL))) {
3154 dev_err(&adapter->pdev->dev,
3155 "EEE Advertisement supports only 100Tx and/or 100T full duplex\n");
3158 adv100m_eee = !!(edata->advertised & ADVERTISE_100_FULL);
3159 adv1g_eee = !!(edata->advertised & ADVERTISE_1000_FULL);
3161 } else if (!edata->eee_enabled) {
3162 dev_err(&adapter->pdev->dev,
3163 "Setting EEE options are not supported with EEE disabled\n");
3167 adapter->eee_advert = ethtool_adv_to_mmd_eee_adv_t(edata->advertised);
3168 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) {
3169 hw->dev_spec._82575.eee_disable = !edata->eee_enabled;
3170 adapter->flags |= IGB_FLAG_EEE;
3173 if (netif_running(netdev))
3174 igb_reinit_locked(adapter);
3179 if (hw->mac.type == e1000_i354)
3180 ret_val = igb_set_eee_i354(hw, adv1g_eee, adv100m_eee);
3182 ret_val = igb_set_eee_i350(hw, adv1g_eee, adv100m_eee);
3185 dev_err(&adapter->pdev->dev,
3186 "Problem setting EEE advertisement options\n");
3193 static int igb_get_module_info(struct net_device *netdev,
3194 struct ethtool_modinfo *modinfo)
3196 struct igb_adapter *adapter = netdev_priv(netdev);
3197 struct e1000_hw *hw = &adapter->hw;
3199 u16 sff8472_rev, addr_mode;
3200 bool page_swap = false;
3202 if ((hw->phy.media_type == e1000_media_type_copper) ||
3203 (hw->phy.media_type == e1000_media_type_unknown))
3206 /* Check whether we support SFF-8472 or not */
3207 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
3211 /* addressing mode is not supported */
3212 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
3216 /* addressing mode is not supported */
3217 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
3218 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
3222 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
3223 /* We have an SFP, but it does not support SFF-8472 */
3224 modinfo->type = ETH_MODULE_SFF_8079;
3225 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
3227 /* We have an SFP which supports a revision of SFF-8472 */
3228 modinfo->type = ETH_MODULE_SFF_8472;
3229 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3235 static int igb_get_module_eeprom(struct net_device *netdev,
3236 struct ethtool_eeprom *ee, u8 *data)
3238 struct igb_adapter *adapter = netdev_priv(netdev);
3239 struct e1000_hw *hw = &adapter->hw;
3242 u16 first_word, last_word;
3248 first_word = ee->offset >> 1;
3249 last_word = (ee->offset + ee->len - 1) >> 1;
3251 dataword = kmalloc_array(last_word - first_word + 1, sizeof(u16),
3256 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
3257 for (i = 0; i < last_word - first_word + 1; i++) {
3258 status = igb_read_phy_reg_i2c(hw, (first_word + i) * 2,
3261 /* Error occurred while reading module */
3266 be16_to_cpus(&dataword[i]);
3269 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len);
3275 static int igb_ethtool_begin(struct net_device *netdev)
3277 struct igb_adapter *adapter = netdev_priv(netdev);
3278 pm_runtime_get_sync(&adapter->pdev->dev);
3282 static void igb_ethtool_complete(struct net_device *netdev)
3284 struct igb_adapter *adapter = netdev_priv(netdev);
3285 pm_runtime_put(&adapter->pdev->dev);
3288 static u32 igb_get_rxfh_indir_size(struct net_device *netdev)
3290 return IGB_RETA_SIZE;
3293 static int igb_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
3296 struct igb_adapter *adapter = netdev_priv(netdev);
3300 *hfunc = ETH_RSS_HASH_TOP;
3303 for (i = 0; i < IGB_RETA_SIZE; i++)
3304 indir[i] = adapter->rss_indir_tbl[i];
3309 void igb_write_rss_indir_tbl(struct igb_adapter *adapter)
3311 struct e1000_hw *hw = &adapter->hw;
3312 u32 reg = E1000_RETA(0);
3316 switch (hw->mac.type) {
3321 /* 82576 supports 2 RSS queues for SR-IOV */
3322 if (adapter->vfs_allocated_count)
3329 while (i < IGB_RETA_SIZE) {
3333 for (j = 3; j >= 0; j--) {
3335 val |= adapter->rss_indir_tbl[i + j];
3338 wr32(reg, val << shift);
3344 static int igb_set_rxfh(struct net_device *netdev, const u32 *indir,
3345 const u8 *key, const u8 hfunc)
3347 struct igb_adapter *adapter = netdev_priv(netdev);
3348 struct e1000_hw *hw = &adapter->hw;
3352 /* We do not allow change in unsupported parameters */
3354 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3359 num_queues = adapter->rss_queues;
3361 switch (hw->mac.type) {
3363 /* 82576 supports 2 RSS queues for SR-IOV */
3364 if (adapter->vfs_allocated_count)
3371 /* Verify user input. */
3372 for (i = 0; i < IGB_RETA_SIZE; i++)
3373 if (indir[i] >= num_queues)
3377 for (i = 0; i < IGB_RETA_SIZE; i++)
3378 adapter->rss_indir_tbl[i] = indir[i];
3380 igb_write_rss_indir_tbl(adapter);
3385 static unsigned int igb_max_channels(struct igb_adapter *adapter)
3387 return igb_get_max_rss_queues(adapter);
3390 static void igb_get_channels(struct net_device *netdev,
3391 struct ethtool_channels *ch)
3393 struct igb_adapter *adapter = netdev_priv(netdev);
3395 /* Report maximum channels */
3396 ch->max_combined = igb_max_channels(adapter);
3398 /* Report info for other vector */
3399 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
3400 ch->max_other = NON_Q_VECTORS;
3401 ch->other_count = NON_Q_VECTORS;
3404 ch->combined_count = adapter->rss_queues;
3407 static int igb_set_channels(struct net_device *netdev,
3408 struct ethtool_channels *ch)
3410 struct igb_adapter *adapter = netdev_priv(netdev);
3411 unsigned int count = ch->combined_count;
3412 unsigned int max_combined = 0;
3414 /* Verify they are not requesting separate vectors */
3415 if (!count || ch->rx_count || ch->tx_count)
3418 /* Verify other_count is valid and has not been changed */
3419 if (ch->other_count != NON_Q_VECTORS)
3422 /* Verify the number of channels doesn't exceed hw limits */
3423 max_combined = igb_max_channels(adapter);
3424 if (count > max_combined)
3427 if (count != adapter->rss_queues) {
3428 adapter->rss_queues = count;
3429 igb_set_flag_queue_pairs(adapter, max_combined);
3431 /* Hardware has to reinitialize queues and interrupts to
3432 * match the new configuration.
3434 return igb_reinit_queues(adapter);
3440 static u32 igb_get_priv_flags(struct net_device *netdev)
3442 struct igb_adapter *adapter = netdev_priv(netdev);
3445 if (adapter->flags & IGB_FLAG_RX_LEGACY)
3446 priv_flags |= IGB_PRIV_FLAGS_LEGACY_RX;
3451 static int igb_set_priv_flags(struct net_device *netdev, u32 priv_flags)
3453 struct igb_adapter *adapter = netdev_priv(netdev);
3454 unsigned int flags = adapter->flags;
3456 flags &= ~IGB_FLAG_RX_LEGACY;
3457 if (priv_flags & IGB_PRIV_FLAGS_LEGACY_RX)
3458 flags |= IGB_FLAG_RX_LEGACY;
3460 if (flags != adapter->flags) {
3461 adapter->flags = flags;
3463 /* reset interface to repopulate queues */
3464 if (netif_running(netdev))
3465 igb_reinit_locked(adapter);
3471 static const struct ethtool_ops igb_ethtool_ops = {
3472 .get_drvinfo = igb_get_drvinfo,
3473 .get_regs_len = igb_get_regs_len,
3474 .get_regs = igb_get_regs,
3475 .get_wol = igb_get_wol,
3476 .set_wol = igb_set_wol,
3477 .get_msglevel = igb_get_msglevel,
3478 .set_msglevel = igb_set_msglevel,
3479 .nway_reset = igb_nway_reset,
3480 .get_link = igb_get_link,
3481 .get_eeprom_len = igb_get_eeprom_len,
3482 .get_eeprom = igb_get_eeprom,
3483 .set_eeprom = igb_set_eeprom,
3484 .get_ringparam = igb_get_ringparam,
3485 .set_ringparam = igb_set_ringparam,
3486 .get_pauseparam = igb_get_pauseparam,
3487 .set_pauseparam = igb_set_pauseparam,
3488 .self_test = igb_diag_test,
3489 .get_strings = igb_get_strings,
3490 .set_phys_id = igb_set_phys_id,
3491 .get_sset_count = igb_get_sset_count,
3492 .get_ethtool_stats = igb_get_ethtool_stats,
3493 .get_coalesce = igb_get_coalesce,
3494 .set_coalesce = igb_set_coalesce,
3495 .get_ts_info = igb_get_ts_info,
3496 .get_rxnfc = igb_get_rxnfc,
3497 .set_rxnfc = igb_set_rxnfc,
3498 .get_eee = igb_get_eee,
3499 .set_eee = igb_set_eee,
3500 .get_module_info = igb_get_module_info,
3501 .get_module_eeprom = igb_get_module_eeprom,
3502 .get_rxfh_indir_size = igb_get_rxfh_indir_size,
3503 .get_rxfh = igb_get_rxfh,
3504 .set_rxfh = igb_set_rxfh,
3505 .get_channels = igb_get_channels,
3506 .set_channels = igb_set_channels,
3507 .get_priv_flags = igb_get_priv_flags,
3508 .set_priv_flags = igb_set_priv_flags,
3509 .begin = igb_ethtool_begin,
3510 .complete = igb_ethtool_complete,
3511 .get_link_ksettings = igb_get_link_ksettings,
3512 .set_link_ksettings = igb_set_link_ksettings,
3515 void igb_set_ethtool_ops(struct net_device *netdev)
3517 netdev->ethtool_ops = &igb_ethtool_ops;