1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2023, Intel Corporation. */
7 #define ICE_BYTES_PER_WORD 2
8 #define ICE_BYTES_PER_DWORD 4
9 #define ICE_CHNL_MAX_TC 16
11 #include "ice_hw_autogen.h"
12 #include "ice_devids.h"
13 #include "ice_osdep.h"
14 #include "ice_controlq.h"
15 #include "ice_lan_tx_rx.h"
16 #include "ice_flex_type.h"
17 #include "ice_protocol_type.h"
18 #include "ice_sbq_cmd.h"
19 #include "ice_vlan_mode.h"
20 #include "ice_fwlog.h"
22 static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc)
24 return test_bit(tc, &bitmap);
27 static inline u64 round_up_64bit(u64 a, u32 b)
29 return div64_long(((a) + (b) / 2), (b));
32 static inline u32 ice_round_to_num(u32 N, u32 R)
34 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
35 ((((N) + (R) - 1) / (R)) * (R)));
38 /* Driver always calls main vsi_handle first */
39 #define ICE_MAIN_VSI_HANDLE 0
41 /* debug masks - set these bits in hw->debug_mask to control output */
42 #define ICE_DBG_INIT BIT_ULL(1)
43 #define ICE_DBG_FW_LOG BIT_ULL(3)
44 #define ICE_DBG_LINK BIT_ULL(4)
45 #define ICE_DBG_PHY BIT_ULL(5)
46 #define ICE_DBG_QCTX BIT_ULL(6)
47 #define ICE_DBG_NVM BIT_ULL(7)
48 #define ICE_DBG_LAN BIT_ULL(8)
49 #define ICE_DBG_FLOW BIT_ULL(9)
50 #define ICE_DBG_SW BIT_ULL(13)
51 #define ICE_DBG_SCHED BIT_ULL(14)
52 #define ICE_DBG_RDMA BIT_ULL(15)
53 #define ICE_DBG_PKG BIT_ULL(16)
54 #define ICE_DBG_RES BIT_ULL(17)
55 #define ICE_DBG_PTP BIT_ULL(19)
56 #define ICE_DBG_AQ_MSG BIT_ULL(24)
57 #define ICE_DBG_AQ_DESC BIT_ULL(25)
58 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
59 #define ICE_DBG_AQ_CMD BIT_ULL(27)
60 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
62 ICE_DBG_AQ_DESC_BUF | \
65 #define ICE_DBG_USER BIT_ULL(31)
70 ICE_CHANGE_LOCK_RES_ID,
71 ICE_GLOBAL_CFG_LOCK_RES_ID
74 /* FW update timeout definitions are in milliseconds */
75 #define ICE_NVM_TIMEOUT 180000
76 #define ICE_CHANGE_LOCK_TIMEOUT 1000
77 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 5000
79 enum ice_aq_res_access_type {
84 struct ice_driver_ver {
101 enum ice_phy_cache_mode {
114 struct ice_phy_cache_mode_data {
116 enum ice_fec_mode curr_user_fec_req;
117 enum ice_fc_mode curr_user_fc_req;
118 u16 curr_user_speed_req;
122 enum ice_set_fc_aq_failures {
123 ICE_SET_FC_AQ_FAIL_NONE = 0,
124 ICE_SET_FC_AQ_FAIL_GET,
125 ICE_SET_FC_AQ_FAIL_SET,
126 ICE_SET_FC_AQ_FAIL_UPDATE
129 /* Various MAC types */
138 enum ice_media_type {
139 ICE_MEDIA_UNKNOWN = 0,
149 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
152 ICE_VSI_SWITCHDEV_CTRL = 7,
155 struct ice_link_status {
156 /* Refer to ice_aq_phy_type for bits definition */
159 u8 topo_media_conflict;
164 u8 lse_ena; /* Link Status Event notification */
170 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
171 * ice_aqc_get_phy_caps structure
173 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
176 /* Different reset sources for which a disable queue AQ call has to be made in
177 * order to clean the Tx scheduler as a part of the reset
179 enum ice_disq_rst_src {
185 /* PHY info such as phy_type, etc... */
186 struct ice_phy_info {
187 struct ice_link_status link_info;
188 struct ice_link_status link_info_old;
191 enum ice_media_type media_type;
193 /* Please refer to struct ice_aqc_get_link_status_data to get
194 * detail of enable bit in curr_user_speed_req
196 u16 curr_user_speed_req;
197 enum ice_fec_mode curr_user_fec_req;
198 enum ice_fc_mode curr_user_fc_req;
199 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
202 /* protocol enumeration for filters */
203 enum ice_fltr_ptype {
204 /* NONE - used for undef/error */
205 ICE_FLTR_PTYPE_NONF_NONE = 0,
206 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
207 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
208 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
209 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
210 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
211 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
212 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
213 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER,
214 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER,
215 ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3,
216 ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3,
217 ICE_FLTR_PTYPE_NONF_IPV4_ESP,
218 ICE_FLTR_PTYPE_NONF_IPV6_ESP,
219 ICE_FLTR_PTYPE_NONF_IPV4_AH,
220 ICE_FLTR_PTYPE_NONF_IPV6_AH,
221 ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP,
222 ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP,
223 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE,
224 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION,
225 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE,
226 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION,
227 ICE_FLTR_PTYPE_NON_IP_L2,
228 ICE_FLTR_PTYPE_FRAG_IPV4,
229 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
230 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
231 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
232 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
237 ICE_FD_HW_SEG_NON_TUN = 0,
242 /* 1 ICE_VSI_PF + 1 ICE_VSI_CTRL + ICE_CHNL_MAX_TC */
243 #define ICE_MAX_FDIR_VSI_PER_FILTER (2 + ICE_CHNL_MAX_TC)
245 struct ice_fd_hw_prof {
246 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
248 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
249 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
250 u64 prof_id[ICE_FD_HW_SEG_MAX];
253 /* Common HW capabilities for SW use */
254 struct ice_hw_common_caps {
256 /* DCB capabilities */
257 u32 active_tc_bitmap;
261 u16 num_rxq; /* Number/Total Rx queues */
262 u16 rxq_first_id; /* First queue ID for Rx queues */
263 u16 num_txq; /* Number/Total Tx queues */
264 u16 txq_first_id; /* First queue ID for Tx queues */
267 u16 num_msix_vectors;
268 u16 msix_vector_first_id;
270 /* Max MTU for function or device */
273 /* Virtualization support */
274 u8 sr_iov_1_1; /* SR-IOV enabled */
276 /* RSS related capabilities */
277 u16 rss_table_size; /* 512 for PFs and 64 for VFs */
278 u8 rss_table_entry_width; /* RSS Entry width in bits */
286 bool nvm_update_pending_nvm;
287 bool nvm_update_pending_orom;
288 bool nvm_update_pending_netlist;
289 #define ICE_NVM_PENDING_NVM_IMAGE BIT(0)
290 #define ICE_NVM_PENDING_OROM BIT(1)
291 #define ICE_NVM_PENDING_NETLIST BIT(2)
292 bool nvm_unified_update;
293 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
294 /* PCIe reset avoidance */
295 bool pcie_reset_avoidance;
296 /* Post update reset restriction */
297 bool reset_restrict_support;
300 /* IEEE 1588 TIME_SYNC specific info */
301 /* Function specific definitions */
302 #define ICE_TS_FUNC_ENA_M BIT(0)
303 #define ICE_TS_SRC_TMR_OWND_M BIT(1)
304 #define ICE_TS_TMR_ENA_M BIT(2)
305 #define ICE_TS_TMR_IDX_OWND_S 4
306 #define ICE_TS_TMR_IDX_OWND_M BIT(4)
307 #define ICE_TS_CLK_FREQ_S 16
308 #define ICE_TS_CLK_FREQ_M ICE_M(0x7, ICE_TS_CLK_FREQ_S)
309 #define ICE_TS_CLK_SRC_S 20
310 #define ICE_TS_CLK_SRC_M BIT(20)
311 #define ICE_TS_TMR_IDX_ASSOC_S 24
312 #define ICE_TS_TMR_IDX_ASSOC_M BIT(24)
314 /* TIME_REF clock rate specification */
315 enum ice_time_ref_freq {
316 ICE_TIME_REF_FREQ_25_000 = 0,
317 ICE_TIME_REF_FREQ_122_880 = 1,
318 ICE_TIME_REF_FREQ_125_000 = 2,
319 ICE_TIME_REF_FREQ_153_600 = 3,
320 ICE_TIME_REF_FREQ_156_250 = 4,
321 ICE_TIME_REF_FREQ_245_760 = 5,
323 NUM_ICE_TIME_REF_FREQ
326 /* Clock source specification */
328 ICE_CLK_SRC_TCX0 = 0, /* Temperature compensated oscillator */
329 ICE_CLK_SRC_TIME_REF = 1, /* Use TIME_REF reference clock */
334 struct ice_ts_func_info {
335 /* Function specific info */
336 enum ice_time_ref_freq time_ref;
346 /* Device specific definitions */
347 #define ICE_TS_TMR0_OWNR_M 0x7
348 #define ICE_TS_TMR0_OWND_M BIT(3)
349 #define ICE_TS_TMR1_OWNR_S 4
350 #define ICE_TS_TMR1_OWNR_M ICE_M(0x7, ICE_TS_TMR1_OWNR_S)
351 #define ICE_TS_TMR1_OWND_M BIT(7)
352 #define ICE_TS_DEV_ENA_M BIT(24)
353 #define ICE_TS_TMR0_ENA_M BIT(25)
354 #define ICE_TS_TMR1_ENA_M BIT(26)
355 #define ICE_TS_LL_TX_TS_READ_M BIT(28)
356 #define ICE_TS_LL_TX_TS_INT_READ_M BIT(29)
358 struct ice_ts_dev_info {
359 /* Device specific info */
373 /* Function specific capabilities */
374 struct ice_hw_func_caps {
375 struct ice_hw_common_caps common_cap;
376 u32 num_allocd_vfs; /* Number of allocated VFs */
377 u32 vf_base_id; /* Logical ID of the first VF */
379 u32 fd_fltr_guar; /* Number of filters guaranteed */
380 u32 fd_fltr_best_effort; /* Number of best effort filters */
381 struct ice_ts_func_info ts_func_info;
384 #define ICE_SENSOR_SUPPORT_E810_INT_TEMP_BIT 0
386 /* Device wide capabilities */
387 struct ice_hw_dev_caps {
388 struct ice_hw_common_caps common_cap;
389 u32 num_vfs_exposed; /* Total number of VFs exposed */
390 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
391 u32 num_flow_director_fltr; /* Number of FD filters available */
392 struct ice_ts_dev_info ts_dev_info;
394 /* bitmap of supported sensors
395 * bit 0 - internal temperature sensor
396 * bit 31:1 - Reserved
398 u32 supported_sensors;
402 struct ice_mac_info {
403 u8 lan_addr[ETH_ALEN];
404 u8 perm_addr[ETH_ALEN];
407 /* Reset types used to determine which kind of reset was requested. These
408 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
409 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
410 * because its reset source is different than the other types listed.
422 struct ice_bus_info {
427 /* Flow control (FC) parameters */
429 enum ice_fc_mode current_mode; /* FC mode in effect */
430 enum ice_fc_mode req_mode; /* FC mode requested by caller */
433 /* Option ROM version information */
434 struct ice_orom_info {
435 u8 major; /* Major version of OROM */
436 u8 patch; /* Patch version of OROM */
437 u16 build; /* Build version of OROM */
440 /* NVM version information */
441 struct ice_nvm_info {
447 /* netlist version information */
448 struct ice_netlist_info {
449 u32 major; /* major high/low */
450 u32 minor; /* minor high/low */
451 u32 type; /* type high/low */
452 u32 rev; /* revision high/low */
453 u32 hash; /* SHA-1 hash word */
454 u16 cust_ver; /* customer version */
457 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
458 * of the flash image.
460 enum ice_flash_bank {
461 ICE_INVALID_FLASH_BANK,
466 /* Enumeration of which flash bank is desired to read from, either the active
467 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from
468 * code which just wants to read the active or inactive flash bank.
470 enum ice_bank_select {
471 ICE_ACTIVE_FLASH_BANK,
472 ICE_INACTIVE_FLASH_BANK,
475 /* information for accessing NVM, OROM, and Netlist flash banks */
476 struct ice_bank_info {
477 u32 nvm_ptr; /* Pointer to 1st NVM bank */
478 u32 nvm_size; /* Size of NVM bank */
479 u32 orom_ptr; /* Pointer to 1st OROM bank */
480 u32 orom_size; /* Size of OROM bank */
481 u32 netlist_ptr; /* Pointer to 1st Netlist bank */
482 u32 netlist_size; /* Size of Netlist bank */
483 enum ice_flash_bank nvm_bank; /* Active NVM bank */
484 enum ice_flash_bank orom_bank; /* Active OROM bank */
485 enum ice_flash_bank netlist_bank; /* Active Netlist bank */
488 /* Flash Chip Information */
489 struct ice_flash_info {
490 struct ice_orom_info orom; /* Option ROM version info */
491 struct ice_nvm_info nvm; /* NVM version information */
492 struct ice_netlist_info netlist;/* Netlist version info */
493 struct ice_bank_info banks; /* Flash Bank information */
494 u16 sr_words; /* Shadow RAM size in words */
495 u32 flash_size; /* Size of available flash in bytes */
496 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
499 struct ice_link_default_override_tlv {
501 #define ICE_LINK_OVERRIDE_OPT_M 0x3F
502 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
503 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
504 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
505 #define ICE_LINK_OVERRIDE_EN BIT(3)
506 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
507 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
509 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
510 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
511 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
512 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
513 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
515 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
521 #define ICE_NVM_VER_LEN 32
523 /* Max number of port to queue branches w.r.t topology */
524 #define ICE_MAX_TRAFFIC_CLASS 8
525 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
527 #define ice_for_each_traffic_class(_i) \
528 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
530 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
531 * to driver defined policy for default aggregator
533 #define ICE_INVAL_TEID 0xFFFFFFFF
534 #define ICE_DFLT_AGG_ID 0
536 struct ice_sched_node {
537 struct ice_sched_node *parent;
538 struct ice_sched_node *sibling; /* next sibling in the same layer */
539 struct ice_sched_node **children;
540 struct ice_aqc_txsched_elem_data info;
542 struct devlink_rate *rate_node;
545 u32 agg_id; /* aggregator group ID */
550 u8 in_use; /* suspended or in use */
551 u8 tx_sched_layer; /* Logical Layer (1-9) */
555 #define ICE_SCHED_NODE_OWNER_LAN 0
556 #define ICE_SCHED_NODE_OWNER_RDMA 2
559 /* Access Macros for Tx Sched Elements data */
560 #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid)
562 /* The aggregator type determines if identifier is for a VSI group,
563 * aggregator group, aggregator of queues, or queue group.
566 ICE_AGG_TYPE_UNKNOWN = 0,
568 ICE_AGG_TYPE_AGG, /* aggregator */
573 /* Rate limit types */
576 ICE_MIN_BW, /* for CIR profile */
577 ICE_MAX_BW, /* for EIR profile */
578 ICE_SHARED_BW /* for shared profile */
581 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
582 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
583 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
584 #define ICE_SCHED_DFLT_RL_PROF_ID 0
585 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
586 #define ICE_SCHED_DFLT_BW_WT 4
587 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
588 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
590 #define ICE_MAX_PORT_PER_PCI_DEV 8
592 /* Data structure for saving BW information */
600 ICE_BW_TYPE_CNT /* This must be last */
608 struct ice_bw_type_info {
609 DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT);
611 struct ice_bw cir_bw;
612 struct ice_bw eir_bw;
616 /* VSI queue context structure for given TC */
620 /* bw_t_info saves queue BW information */
621 struct ice_bw_type_info bw_t_info;
624 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
625 struct ice_sched_vsi_info {
626 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
627 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
628 struct list_head list_entry;
629 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
630 u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS];
631 /* bw_t_info saves VSI BW information */
632 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
635 /* driver defines the policy */
636 struct ice_sched_tx_policy {
638 u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS];
642 /* CEE or IEEE 802.1Qaz ETS Configuration data */
643 struct ice_dcb_ets_cfg {
647 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
648 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
649 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
652 /* CEE or IEEE 802.1Qaz PFC Configuration data */
653 struct ice_dcb_pfc_cfg {
660 /* CEE or IEEE 802.1Qaz Application Priority data */
661 struct ice_dcb_app_priority_table {
667 #define ICE_MAX_USER_PRIORITY 8
668 #define ICE_DCBX_MAX_APPS 64
669 #define ICE_DSCP_NUM_VAL 64
670 #define ICE_LLDPDU_SIZE 1500
671 #define ICE_TLV_STATUS_OPER 0x1
672 #define ICE_TLV_STATUS_SYNC 0x2
673 #define ICE_TLV_STATUS_ERR 0x4
674 #define ICE_APP_PROT_ID_ISCSI_860 0x035c
675 #define ICE_APP_SEL_ETHTYPE 0x1
676 #define ICE_APP_SEL_TCPIP 0x2
677 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
678 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
679 #define ICE_CEE_APP_SEL_TCPIP 0x1
681 struct ice_dcbx_cfg {
683 u32 tlv_status; /* CEE mode TLV status */
684 struct ice_dcb_ets_cfg etscfg;
685 struct ice_dcb_ets_cfg etsrec;
686 struct ice_dcb_pfc_cfg pfc;
687 #define ICE_QOS_MODE_VLAN 0x0
688 #define ICE_QOS_MODE_DSCP 0x1
690 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
691 /* when DSCP mapping defined by user set its bit to 1 */
692 DECLARE_BITMAP(dscp_mapped, ICE_DSCP_NUM_VAL);
693 /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */
694 u8 dscp_map[ICE_DSCP_NUM_VAL];
696 #define ICE_DCBX_MODE_CEE 0x1
697 #define ICE_DCBX_MODE_IEEE 0x2
699 #define ICE_DCBX_APPS_NON_WILLING 0x1
703 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
704 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
705 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
706 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */
710 struct ice_port_info {
711 struct ice_sched_node *root; /* Root Node per Port */
712 struct ice_hw *hw; /* back pointer to HW instance */
713 u32 last_node_teid; /* scheduler last node info */
714 u16 sw_id; /* Initial switch ID belongs to port */
717 #define ICE_SCHED_PORT_STATE_INIT 0x0
718 #define ICE_SCHED_PORT_STATE_READY 0x1
720 #define ICE_LPORT_MASK 0xff
721 struct ice_fc_info fc;
722 struct ice_mac_info mac;
723 struct ice_phy_info phy;
724 struct mutex sched_lock; /* protect access to TXSched tree */
725 struct ice_sched_node *
726 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
727 /* List contain profile ID(s) and other params per layer */
728 struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
729 struct ice_qos_cfg qos_cfg;
730 struct xarray sched_node_ids;
732 u8 is_custom_tx_enabled:1;
735 struct ice_switch_info {
736 struct list_head vsi_list_map_head;
737 struct ice_sw_recipe *recp_list;
738 u16 prof_res_bm_init;
739 u16 max_used_prof_index;
741 DECLARE_BITMAP(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
744 /* Enum defining the different states of the mailbox snapshot in the
745 * PF-VF mailbox overflow detection algorithm. The snapshot can be in
747 * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot
748 * within the mailbox buffer.
749 * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot
750 * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the
751 * mailbox and mark any VFs sending more messages than the threshold limit set.
752 * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF.
754 enum ice_mbx_snapshot_state {
755 ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0,
756 ICE_MAL_VF_DETECT_STATE_TRAVERSE,
757 ICE_MAL_VF_DETECT_STATE_DETECT,
758 ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF,
761 /* Structure to hold information of the static snapshot and the mailbox
762 * buffer data used to generate and track the snapshot.
763 * 1. state: the state of the mailbox snapshot in the malicious VF
764 * detection state handler ice_mbx_vf_state_handler()
765 * 2. head: head of the mailbox snapshot in a circular mailbox buffer
766 * 3. tail: tail of the mailbox snapshot in a circular mailbox buffer
767 * 4. num_iterations: number of messages traversed in circular mailbox buffer
768 * 5. num_msg_proc: number of messages processed in mailbox
769 * 6. num_pending_arq: number of pending asynchronous messages
770 * 7. max_num_msgs_mbx: maximum messages in mailbox for currently
771 * serviced work item or interrupt.
773 struct ice_mbx_snap_buffer_data {
774 enum ice_mbx_snapshot_state state;
780 u16 max_num_msgs_mbx;
783 /* Structure used to track a single VF's messages on the mailbox:
784 * 1. list_entry: linked list entry node
785 * 2. msg_count: the number of asynchronous messages sent by this VF
786 * 3. malicious: whether this VF has been detected as malicious before
788 struct ice_mbx_vf_info {
789 struct list_head list_entry;
794 /* Structure to hold data relevant to the captured static snapshot
795 * of the PF-VF mailbox.
797 struct ice_mbx_snapshot {
798 struct ice_mbx_snap_buffer_data mbx_buf;
799 struct list_head mbx_vf;
802 /* Structure to hold data to be used for capturing or updating a
804 * 1. num_msg_proc: number of messages processed in mailbox
805 * 2. num_pending_arq: number of pending asynchronous messages
806 * 3. max_num_msgs_mbx: maximum messages in mailbox for currently
807 * serviced work item or interrupt.
808 * 4. async_watermark_val: An upper threshold set by caller to determine
809 * if the pending arq count is large enough to assume that there is
810 * the possibility of a mailicious VF.
812 struct ice_mbx_data {
815 u16 max_num_msgs_mbx;
816 u16 async_watermark_val;
826 /* Port hardware description */
830 struct ice_aqc_layer_props *layer_info;
831 struct ice_port_info *port_info;
832 /* PSM clock frequency for calculating RL profile params */
834 u64 debug_mask; /* bitmap for debug mask */
835 enum ice_mac_type mac_type;
837 u16 fd_ctr_base; /* FD counter base index */
842 u16 subsystem_device_id;
843 u16 subsystem_vendor_id;
846 u8 pf_id; /* device profile info */
847 enum ice_phy_model phy_model;
849 u16 max_burst_size; /* driver sets this value */
851 /* Tx Scheduler values */
852 u8 num_tx_sched_layers;
853 u8 num_tx_sched_phys_layers;
856 u8 sw_entry_point_layer;
857 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
858 struct list_head agg_list; /* lists all aggregator */
860 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
861 u8 evb_veb; /* true for VEB, false for VEPA */
862 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
863 struct ice_bus_info bus;
864 struct ice_flash_info flash;
865 struct ice_hw_dev_caps dev_caps; /* device capabilities */
866 struct ice_hw_func_caps func_caps; /* function capabilities */
868 struct ice_switch_info *switch_info; /* switch filter lists */
870 /* Control Queue info */
871 struct ice_ctl_q_info adminq;
872 struct ice_ctl_q_info sbq;
873 struct ice_ctl_q_info mailboxq;
875 u8 api_branch; /* API branch version */
876 u8 api_maj_ver; /* API major version */
877 u8 api_min_ver; /* API minor version */
878 u8 api_patch; /* API patch version */
879 u8 fw_branch; /* firmware branch version */
880 u8 fw_maj_ver; /* firmware major version */
881 u8 fw_min_ver; /* firmware minor version */
882 u8 fw_patch; /* firmware patch version */
883 u32 fw_build; /* firmware build number */
885 struct ice_fwlog_cfg fwlog_cfg;
886 bool fwlog_supported; /* does hardware support FW logging? */
887 struct ice_fwlog_ring fwlog_ring;
889 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
890 * register. Used for determining the ITR/INTRL granularity during
893 #define ICE_MAX_AGG_BW_200G 0x0
894 #define ICE_MAX_AGG_BW_100G 0X1
895 #define ICE_MAX_AGG_BW_50G 0x2
896 #define ICE_MAX_AGG_BW_25G 0x3
897 /* ITR granularity for different speeds */
898 #define ICE_ITR_GRAN_ABOVE_25 2
899 #define ICE_ITR_GRAN_MAX_25 4
900 /* ITR granularity in 1 us */
902 /* INTRL granularity for different speeds */
903 #define ICE_INTRL_GRAN_ABOVE_25 4
904 #define ICE_INTRL_GRAN_MAX_25 8
905 /* INTRL granularity in 1 us */
908 #define ICE_MAX_QUAD 2
909 #define ICE_QUADS_PER_PHY_E82X 2
910 #define ICE_PORTS_PER_PHY_E82X 8
911 #define ICE_PORTS_PER_QUAD 4
912 #define ICE_PORTS_PER_PHY_E810 4
913 #define ICE_NUM_EXTERNAL_PORTS (ICE_MAX_QUAD * ICE_PORTS_PER_QUAD)
915 /* Active package version (currently active) */
916 struct ice_pkg_ver active_pkg_ver;
920 u8 pkg_has_signing_seg:1;
921 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
922 u8 active_pkg_in_nvm;
924 /* Driver's package ver - (from the Ice Metadata section) */
925 struct ice_pkg_ver pkg_ver;
926 u8 pkg_name[ICE_PKG_NAME_SIZE];
928 /* Driver's Ice segment format version and ID (from the Ice seg) */
929 struct ice_pkg_ver ice_seg_fmt_ver;
930 u8 ice_seg_id[ICE_SEG_ID_SIZE];
932 /* Pointer to the ice segment */
935 /* Pointer to allocated copy of pkg memory */
940 struct mutex tnl_lock;
941 struct ice_tunnel_table tnl;
943 struct udp_tunnel_nic_shared udp_tunnel_shared;
944 struct udp_tunnel_nic_info udp_tunnel_nic;
946 /* dvm boost update information */
947 struct ice_dvm_table dvm_upd;
949 /* HW block tables */
950 struct ice_blk_info blk[ICE_BLK_COUNT];
951 struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
952 struct list_head fl_profs[ICE_BLK_COUNT];
954 /* Flow Director filter info */
955 int fdir_active_fltr;
957 struct mutex fdir_fltr_lock; /* protect Flow Director */
958 struct list_head fdir_list_head;
960 /* Book-keeping of side-band filter count per flow-type.
961 * This is used to detect and handle input set changes for
962 * respective flow-type.
964 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
966 struct ice_fd_hw_prof **fdir_prof;
967 DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
968 struct mutex rss_locks; /* protect RSS configuration */
969 struct list_head rss_list_head;
970 struct ice_mbx_snapshot mbx_snapshot;
971 DECLARE_BITMAP(hw_ptype, ICE_FLOW_PTYPE_MAX);
973 u16 io_expander_handle;
977 /* Statistics collected by each port, VSI, VEB, and S-channel */
978 struct ice_eth_stats {
979 u64 rx_bytes; /* gorc */
980 u64 rx_unicast; /* uprc */
981 u64 rx_multicast; /* mprc */
982 u64 rx_broadcast; /* bprc */
983 u64 rx_discards; /* rdpc */
984 u64 rx_unknown_protocol; /* rupp */
985 u64 tx_bytes; /* gotc */
986 u64 tx_unicast; /* uptc */
987 u64 tx_multicast; /* mptc */
988 u64 tx_broadcast; /* bptc */
989 u64 tx_discards; /* tdpc */
990 u64 tx_errors; /* tepc */
995 /* Statistics collected by the MAC */
996 struct ice_hw_port_stats {
997 /* eth stats collected by the port */
998 struct ice_eth_stats eth;
999 /* additional port specific stats */
1000 u64 tx_dropped_link_down; /* tdold */
1001 u64 crc_errors; /* crcerrs */
1002 u64 illegal_bytes; /* illerrc */
1003 u64 error_bytes; /* errbc */
1004 u64 mac_local_faults; /* mlfc */
1005 u64 mac_remote_faults; /* mrfc */
1006 u64 link_xon_rx; /* lxonrxc */
1007 u64 link_xoff_rx; /* lxoffrxc */
1008 u64 link_xon_tx; /* lxontxc */
1009 u64 link_xoff_tx; /* lxofftxc */
1010 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1011 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1012 u64 priority_xon_tx[8]; /* pxontxc[8] */
1013 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1014 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1015 u64 rx_size_64; /* prc64 */
1016 u64 rx_size_127; /* prc127 */
1017 u64 rx_size_255; /* prc255 */
1018 u64 rx_size_511; /* prc511 */
1019 u64 rx_size_1023; /* prc1023 */
1020 u64 rx_size_1522; /* prc1522 */
1021 u64 rx_size_big; /* prc9522 */
1022 u64 rx_undersize; /* ruc */
1023 u64 rx_fragments; /* rfc */
1024 u64 rx_oversize; /* roc */
1025 u64 rx_jabber; /* rjc */
1026 u64 tx_size_64; /* ptc64 */
1027 u64 tx_size_127; /* ptc127 */
1028 u64 tx_size_255; /* ptc255 */
1029 u64 tx_size_511; /* ptc511 */
1030 u64 tx_size_1023; /* ptc1023 */
1031 u64 tx_size_1522; /* ptc1522 */
1032 u64 tx_size_big; /* ptc9522 */
1033 /* flow director stats */
1038 enum ice_sw_fwd_act_type {
1040 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
1049 struct ice_aq_get_set_rss_lut_params {
1050 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */
1051 enum ice_lut_size lut_size; /* size of the LUT buffer */
1052 enum ice_lut_type lut_type; /* type of the LUT (i.e. VSI, PF, Global) */
1053 u16 vsi_handle; /* software VSI handle */
1054 u8 global_lut_id; /* only valid when lut_type is global */
1057 /* Checksum and Shadow RAM pointers */
1058 #define ICE_SR_NVM_CTRL_WORD 0x00
1059 #define ICE_SR_BOOT_CFG_PTR 0x132
1060 #define ICE_SR_NVM_WOL_CFG 0x19
1061 #define ICE_NVM_OROM_VER_OFF 0x02
1062 #define ICE_SR_PBA_BLOCK_PTR 0x16
1063 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
1064 #define ICE_SR_NVM_EETRACK_LO 0x2D
1065 #define ICE_SR_NVM_EETRACK_HI 0x2E
1066 #define ICE_NVM_VER_LO_SHIFT 0
1067 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
1068 #define ICE_NVM_VER_HI_SHIFT 12
1069 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
1070 #define ICE_OROM_VER_PATCH_SHIFT 0
1071 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
1072 #define ICE_OROM_VER_BUILD_SHIFT 8
1073 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
1074 #define ICE_OROM_VER_SHIFT 24
1075 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT)
1076 #define ICE_SR_PFA_PTR 0x40
1077 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
1078 #define ICE_SR_NVM_BANK_SIZE 0x43
1079 #define ICE_SR_1ST_OROM_BANK_PTR 0x44
1080 #define ICE_SR_OROM_BANK_SIZE 0x45
1081 #define ICE_SR_NETLIST_BANK_PTR 0x46
1082 #define ICE_SR_NETLIST_BANK_SIZE 0x47
1083 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1085 /* CSS Header words */
1086 #define ICE_NVM_CSS_SREV_L 0x14
1087 #define ICE_NVM_CSS_SREV_H 0x15
1089 /* Length of CSS header section in words */
1090 #define ICE_CSS_HEADER_LENGTH 330
1092 /* Offset of Shadow RAM copy in the NVM bank area. */
1093 #define ICE_NVM_SR_COPY_WORD_OFFSET roundup(ICE_CSS_HEADER_LENGTH, 32)
1095 /* Size in bytes of Option ROM trailer */
1096 #define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH)
1098 /* The Link Topology Netlist section is stored as a series of words. It is
1099 * stored in the NVM as a TLV, with the first two words containing the type
1102 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B
1103 #define ICE_NETLIST_TYPE_OFFSET 0x0000
1104 #define ICE_NETLIST_LEN_OFFSET 0x0001
1106 /* The Link Topology section follows the TLV header. When reading the netlist
1107 * using ice_read_netlist_module, we need to account for the 2-word TLV
1110 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2)
1112 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000)
1113 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001)
1115 #define ICE_LINK_TOPO_NODE_COUNT_M ICE_M(0x3FF, 0)
1117 /* The Netlist ID Block is located after all of the Link Topology nodes. */
1118 #define ICE_NETLIST_ID_BLK_SIZE 0x30
1119 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n))
1121 /* netlist ID block field offsets (word offsets) */
1122 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02
1123 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03
1124 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04
1125 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05
1126 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06
1127 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07
1128 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08
1129 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09
1130 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n))
1131 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F
1133 /* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */
1134 #define ICE_SR_CTRL_WORD_1_S 0x06
1135 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
1136 #define ICE_SR_CTRL_WORD_VALID 0x1
1137 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3)
1138 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4)
1139 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5)
1141 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15)
1143 /* Link override related */
1144 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
1145 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
1146 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
1147 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
1148 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
1149 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
1150 #define ICE_FW_API_LINK_OVERRIDE_MIN 5
1151 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
1153 #define ICE_SR_WORDS_IN_1KB 512
1155 /* AQ API version for LLDP_FILTER_CONTROL */
1156 #define ICE_FW_API_LLDP_FLTR_MAJ 1
1157 #define ICE_FW_API_LLDP_FLTR_MIN 7
1158 #define ICE_FW_API_LLDP_FLTR_PATCH 1
1160 /* AQ API version for report default configuration */
1161 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1
1162 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7
1163 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3
1165 #endif /* _ICE_TYPE_H_ */