1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2021, Intel Corporation. */
8 #define E810_OUT_PROP_DELAY_NS 1
10 #define UNKNOWN_INCVAL_E82X 0x100000000ULL
12 static const struct ptp_pin_desc ice_pin_desc_e810t[] = {
13 /* name idx func chan */
14 { "GNSS", GNSS, PTP_PF_EXTTS, 0, { 0, } },
15 { "SMA1", SMA1, PTP_PF_NONE, 1, { 0, } },
16 { "U.FL1", UFL1, PTP_PF_NONE, 1, { 0, } },
17 { "SMA2", SMA2, PTP_PF_NONE, 2, { 0, } },
18 { "U.FL2", UFL2, PTP_PF_NONE, 2, { 0, } },
22 * ice_get_sma_config_e810t
23 * @hw: pointer to the hw struct
24 * @ptp_pins: pointer to the ptp_pin_desc struture
26 * Read the configuration of the SMA control logic and put it into the
27 * ptp_pin_desc structure
30 ice_get_sma_config_e810t(struct ice_hw *hw, struct ptp_pin_desc *ptp_pins)
35 /* Read initial pin state */
36 status = ice_read_sma_ctrl_e810t(hw, &data);
40 /* initialize with defaults */
41 for (i = 0; i < NUM_PTP_PINS_E810T; i++) {
42 strscpy(ptp_pins[i].name, ice_pin_desc_e810t[i].name,
43 sizeof(ptp_pins[i].name));
44 ptp_pins[i].index = ice_pin_desc_e810t[i].index;
45 ptp_pins[i].func = ice_pin_desc_e810t[i].func;
46 ptp_pins[i].chan = ice_pin_desc_e810t[i].chan;
50 switch (data & ICE_SMA1_MASK_E810T) {
51 case ICE_SMA1_MASK_E810T:
53 ptp_pins[SMA1].func = PTP_PF_NONE;
54 ptp_pins[UFL1].func = PTP_PF_NONE;
56 case ICE_SMA1_DIR_EN_E810T:
57 ptp_pins[SMA1].func = PTP_PF_PEROUT;
58 ptp_pins[UFL1].func = PTP_PF_NONE;
60 case ICE_SMA1_TX_EN_E810T:
61 ptp_pins[SMA1].func = PTP_PF_EXTTS;
62 ptp_pins[UFL1].func = PTP_PF_NONE;
65 ptp_pins[SMA1].func = PTP_PF_EXTTS;
66 ptp_pins[UFL1].func = PTP_PF_PEROUT;
71 switch (data & ICE_SMA2_MASK_E810T) {
72 case ICE_SMA2_MASK_E810T:
74 ptp_pins[SMA2].func = PTP_PF_NONE;
75 ptp_pins[UFL2].func = PTP_PF_NONE;
77 case (ICE_SMA2_TX_EN_E810T | ICE_SMA2_UFL2_RX_DIS_E810T):
78 ptp_pins[SMA2].func = PTP_PF_EXTTS;
79 ptp_pins[UFL2].func = PTP_PF_NONE;
81 case (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_UFL2_RX_DIS_E810T):
82 ptp_pins[SMA2].func = PTP_PF_PEROUT;
83 ptp_pins[UFL2].func = PTP_PF_NONE;
85 case (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_TX_EN_E810T):
86 ptp_pins[SMA2].func = PTP_PF_NONE;
87 ptp_pins[UFL2].func = PTP_PF_EXTTS;
89 case ICE_SMA2_DIR_EN_E810T:
90 ptp_pins[SMA2].func = PTP_PF_PEROUT;
91 ptp_pins[UFL2].func = PTP_PF_EXTTS;
99 * ice_ptp_set_sma_config_e810t
100 * @hw: pointer to the hw struct
101 * @ptp_pins: pointer to the ptp_pin_desc struture
103 * Set the configuration of the SMA control logic based on the configuration in
107 ice_ptp_set_sma_config_e810t(struct ice_hw *hw,
108 const struct ptp_pin_desc *ptp_pins)
113 /* SMA1 and UFL1 cannot be set to TX at the same time */
114 if (ptp_pins[SMA1].func == PTP_PF_PEROUT &&
115 ptp_pins[UFL1].func == PTP_PF_PEROUT)
118 /* SMA2 and UFL2 cannot be set to RX at the same time */
119 if (ptp_pins[SMA2].func == PTP_PF_EXTTS &&
120 ptp_pins[UFL2].func == PTP_PF_EXTTS)
123 /* Read initial pin state value */
124 status = ice_read_sma_ctrl_e810t(hw, &data);
128 /* Set the right sate based on the desired configuration */
129 data &= ~ICE_SMA1_MASK_E810T;
130 if (ptp_pins[SMA1].func == PTP_PF_NONE &&
131 ptp_pins[UFL1].func == PTP_PF_NONE) {
132 dev_info(ice_hw_to_dev(hw), "SMA1 + U.FL1 disabled");
133 data |= ICE_SMA1_MASK_E810T;
134 } else if (ptp_pins[SMA1].func == PTP_PF_EXTTS &&
135 ptp_pins[UFL1].func == PTP_PF_NONE) {
136 dev_info(ice_hw_to_dev(hw), "SMA1 RX");
137 data |= ICE_SMA1_TX_EN_E810T;
138 } else if (ptp_pins[SMA1].func == PTP_PF_NONE &&
139 ptp_pins[UFL1].func == PTP_PF_PEROUT) {
140 /* U.FL 1 TX will always enable SMA 1 RX */
141 dev_info(ice_hw_to_dev(hw), "SMA1 RX + U.FL1 TX");
142 } else if (ptp_pins[SMA1].func == PTP_PF_EXTTS &&
143 ptp_pins[UFL1].func == PTP_PF_PEROUT) {
144 dev_info(ice_hw_to_dev(hw), "SMA1 RX + U.FL1 TX");
145 } else if (ptp_pins[SMA1].func == PTP_PF_PEROUT &&
146 ptp_pins[UFL1].func == PTP_PF_NONE) {
147 dev_info(ice_hw_to_dev(hw), "SMA1 TX");
148 data |= ICE_SMA1_DIR_EN_E810T;
151 data &= ~ICE_SMA2_MASK_E810T;
152 if (ptp_pins[SMA2].func == PTP_PF_NONE &&
153 ptp_pins[UFL2].func == PTP_PF_NONE) {
154 dev_info(ice_hw_to_dev(hw), "SMA2 + U.FL2 disabled");
155 data |= ICE_SMA2_MASK_E810T;
156 } else if (ptp_pins[SMA2].func == PTP_PF_EXTTS &&
157 ptp_pins[UFL2].func == PTP_PF_NONE) {
158 dev_info(ice_hw_to_dev(hw), "SMA2 RX");
159 data |= (ICE_SMA2_TX_EN_E810T |
160 ICE_SMA2_UFL2_RX_DIS_E810T);
161 } else if (ptp_pins[SMA2].func == PTP_PF_NONE &&
162 ptp_pins[UFL2].func == PTP_PF_EXTTS) {
163 dev_info(ice_hw_to_dev(hw), "UFL2 RX");
164 data |= (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_TX_EN_E810T);
165 } else if (ptp_pins[SMA2].func == PTP_PF_PEROUT &&
166 ptp_pins[UFL2].func == PTP_PF_NONE) {
167 dev_info(ice_hw_to_dev(hw), "SMA2 TX");
168 data |= (ICE_SMA2_DIR_EN_E810T |
169 ICE_SMA2_UFL2_RX_DIS_E810T);
170 } else if (ptp_pins[SMA2].func == PTP_PF_PEROUT &&
171 ptp_pins[UFL2].func == PTP_PF_EXTTS) {
172 dev_info(ice_hw_to_dev(hw), "SMA2 TX + U.FL2 RX");
173 data |= ICE_SMA2_DIR_EN_E810T;
176 return ice_write_sma_ctrl_e810t(hw, data);
180 * ice_ptp_set_sma_e810t
181 * @info: the driver's PTP info structure
182 * @pin: pin index in kernel structure
183 * @func: Pin function to be set (PTP_PF_NONE, PTP_PF_EXTTS or PTP_PF_PEROUT)
185 * Set the configuration of a single SMA pin
188 ice_ptp_set_sma_e810t(struct ptp_clock_info *info, unsigned int pin,
189 enum ptp_pin_function func)
191 struct ptp_pin_desc ptp_pins[NUM_PTP_PINS_E810T];
192 struct ice_pf *pf = ptp_info_to_pf(info);
193 struct ice_hw *hw = &pf->hw;
196 if (pin < SMA1 || func > PTP_PF_PEROUT)
199 err = ice_get_sma_config_e810t(hw, ptp_pins);
203 /* Disable the same function on the other pin sharing the channel */
204 if (pin == SMA1 && ptp_pins[UFL1].func == func)
205 ptp_pins[UFL1].func = PTP_PF_NONE;
206 if (pin == UFL1 && ptp_pins[SMA1].func == func)
207 ptp_pins[SMA1].func = PTP_PF_NONE;
209 if (pin == SMA2 && ptp_pins[UFL2].func == func)
210 ptp_pins[UFL2].func = PTP_PF_NONE;
211 if (pin == UFL2 && ptp_pins[SMA2].func == func)
212 ptp_pins[SMA2].func = PTP_PF_NONE;
214 /* Set up new pin function in the temp table */
215 ptp_pins[pin].func = func;
217 return ice_ptp_set_sma_config_e810t(hw, ptp_pins);
221 * ice_verify_pin_e810t
222 * @info: the driver's PTP info structure
224 * @func: Assigned function
225 * @chan: Assigned channel
227 * Verify if pin supports requested pin function. If the Check pins consistency.
228 * Reconfigure the SMA logic attached to the given pin to enable its
229 * desired functionality
232 ice_verify_pin_e810t(struct ptp_clock_info *info, unsigned int pin,
233 enum ptp_pin_function func, unsigned int chan)
235 /* Don't allow channel reassignment */
236 if (chan != ice_pin_desc_e810t[pin].chan)
239 /* Check if functions are properly assigned */
248 if (pin == UFL2 || pin == GNSS)
255 return ice_ptp_set_sma_e810t(info, pin, func);
259 * ice_ptp_cfg_tx_interrupt - Configure Tx timestamp interrupt for the device
260 * @pf: Board private structure
262 * Program the device to respond appropriately to the Tx timestamp interrupt
265 static void ice_ptp_cfg_tx_interrupt(struct ice_pf *pf)
267 struct ice_hw *hw = &pf->hw;
271 switch (pf->ptp.tx_interrupt_mode) {
272 case ICE_PTP_TX_INTERRUPT_ALL:
273 /* React to interrupts across all quads. */
274 wr32(hw, PFINT_TSYN_MSK + (0x4 * hw->pf_id), (u32)0x1f);
277 case ICE_PTP_TX_INTERRUPT_NONE:
278 /* Do not react to interrupts on any quad. */
279 wr32(hw, PFINT_TSYN_MSK + (0x4 * hw->pf_id), (u32)0x0);
282 case ICE_PTP_TX_INTERRUPT_SELF:
284 enable = pf->ptp.tstamp_config.tx_type == HWTSTAMP_TX_ON;
288 /* Configure the Tx timestamp interrupt */
289 val = rd32(hw, PFINT_OICR_ENA);
291 val |= PFINT_OICR_TSYN_TX_M;
293 val &= ~PFINT_OICR_TSYN_TX_M;
294 wr32(hw, PFINT_OICR_ENA, val);
298 * ice_set_rx_tstamp - Enable or disable Rx timestamping
299 * @pf: The PF pointer to search in
300 * @on: bool value for whether timestamps are enabled or disabled
302 static void ice_set_rx_tstamp(struct ice_pf *pf, bool on)
307 vsi = ice_get_main_vsi(pf);
308 if (!vsi || !vsi->rx_rings)
311 /* Set the timestamp flag for all the Rx rings */
312 ice_for_each_rxq(vsi, i) {
313 if (!vsi->rx_rings[i])
315 vsi->rx_rings[i]->ptp_rx = on;
320 * ice_ptp_disable_timestamp_mode - Disable current timestamp mode
321 * @pf: Board private structure
323 * Called during preparation for reset to temporarily disable timestamping on
324 * the device. Called during remove to disable timestamping while cleaning up
327 static void ice_ptp_disable_timestamp_mode(struct ice_pf *pf)
329 struct ice_hw *hw = &pf->hw;
332 val = rd32(hw, PFINT_OICR_ENA);
333 val &= ~PFINT_OICR_TSYN_TX_M;
334 wr32(hw, PFINT_OICR_ENA, val);
336 ice_set_rx_tstamp(pf, false);
340 * ice_ptp_restore_timestamp_mode - Restore timestamp configuration
341 * @pf: Board private structure
343 * Called at the end of rebuild to restore timestamp configuration after
346 void ice_ptp_restore_timestamp_mode(struct ice_pf *pf)
348 struct ice_hw *hw = &pf->hw;
351 ice_ptp_cfg_tx_interrupt(pf);
353 enable_rx = pf->ptp.tstamp_config.rx_filter == HWTSTAMP_FILTER_ALL;
354 ice_set_rx_tstamp(pf, enable_rx);
356 /* Trigger an immediate software interrupt to ensure that timestamps
357 * which occurred during reset are handled now.
359 wr32(hw, PFINT_OICR, PFINT_OICR_TSYN_TX_M);
364 * ice_ptp_read_src_clk_reg - Read the source clock register
365 * @pf: Board private structure
366 * @sts: Optional parameter for holding a pair of system timestamps from
367 * the system clock. Will be ignored if NULL is given.
370 ice_ptp_read_src_clk_reg(struct ice_pf *pf, struct ptp_system_timestamp *sts)
372 struct ice_hw *hw = &pf->hw;
376 tmr_idx = ice_get_ptp_src_clock_index(hw);
377 /* Read the system timestamp pre PHC read */
378 ptp_read_system_prets(sts);
380 lo = rd32(hw, GLTSYN_TIME_L(tmr_idx));
382 /* Read the system timestamp post PHC read */
383 ptp_read_system_postts(sts);
385 hi = rd32(hw, GLTSYN_TIME_H(tmr_idx));
386 lo2 = rd32(hw, GLTSYN_TIME_L(tmr_idx));
389 /* if TIME_L rolled over read TIME_L again and update
392 ptp_read_system_prets(sts);
393 lo = rd32(hw, GLTSYN_TIME_L(tmr_idx));
394 ptp_read_system_postts(sts);
395 hi = rd32(hw, GLTSYN_TIME_H(tmr_idx));
398 return ((u64)hi << 32) | lo;
402 * ice_ptp_extend_32b_ts - Convert a 32b nanoseconds timestamp to 64b
403 * @cached_phc_time: recently cached copy of PHC time
404 * @in_tstamp: Ingress/egress 32b nanoseconds timestamp value
406 * Hardware captures timestamps which contain only 32 bits of nominal
407 * nanoseconds, as opposed to the 64bit timestamps that the stack expects.
408 * Note that the captured timestamp values may be 40 bits, but the lower
409 * 8 bits are sub-nanoseconds and generally discarded.
411 * Extend the 32bit nanosecond timestamp using the following algorithm and
414 * 1) have a recently cached copy of the PHC time
415 * 2) assume that the in_tstamp was captured 2^31 nanoseconds (~2.1
416 * seconds) before or after the PHC time was captured.
417 * 3) calculate the delta between the cached time and the timestamp
418 * 4) if the delta is smaller than 2^31 nanoseconds, then the timestamp was
419 * captured after the PHC time. In this case, the full timestamp is just
420 * the cached PHC time plus the delta.
421 * 5) otherwise, if the delta is larger than 2^31 nanoseconds, then the
422 * timestamp was captured *before* the PHC time, i.e. because the PHC
423 * cache was updated after the timestamp was captured by hardware. In this
424 * case, the full timestamp is the cached time minus the inverse delta.
426 * This algorithm works even if the PHC time was updated after a Tx timestamp
427 * was requested, but before the Tx timestamp event was reported from
430 * This calculation primarily relies on keeping the cached PHC time up to
431 * date. If the timestamp was captured more than 2^31 nanoseconds after the
432 * PHC time, it is possible that the lower 32bits of PHC time have
433 * overflowed more than once, and we might generate an incorrect timestamp.
435 * This is prevented by (a) periodically updating the cached PHC time once
436 * a second, and (b) discarding any Tx timestamp packet if it has waited for
437 * a timestamp for more than one second.
439 static u64 ice_ptp_extend_32b_ts(u64 cached_phc_time, u32 in_tstamp)
441 u32 delta, phc_time_lo;
444 /* Extract the lower 32 bits of the PHC time */
445 phc_time_lo = (u32)cached_phc_time;
447 /* Calculate the delta between the lower 32bits of the cached PHC
448 * time and the in_tstamp value
450 delta = (in_tstamp - phc_time_lo);
452 /* Do not assume that the in_tstamp is always more recent than the
453 * cached PHC time. If the delta is large, it indicates that the
454 * in_tstamp was taken in the past, and should be converted
457 if (delta > (U32_MAX / 2)) {
458 /* reverse the delta calculation here */
459 delta = (phc_time_lo - in_tstamp);
460 ns = cached_phc_time - delta;
462 ns = cached_phc_time + delta;
469 * ice_ptp_extend_40b_ts - Convert a 40b timestamp to 64b nanoseconds
470 * @pf: Board private structure
471 * @in_tstamp: Ingress/egress 40b timestamp value
473 * The Tx and Rx timestamps are 40 bits wide, including 32 bits of nominal
474 * nanoseconds, 7 bits of sub-nanoseconds, and a valid bit.
476 * *--------------------------------------------------------------*
477 * | 32 bits of nanoseconds | 7 high bits of sub ns underflow | v |
478 * *--------------------------------------------------------------*
480 * The low bit is an indicator of whether the timestamp is valid. The next
481 * 7 bits are a capture of the upper 7 bits of the sub-nanosecond underflow,
482 * and the remaining 32 bits are the lower 32 bits of the PHC timer.
484 * It is assumed that the caller verifies the timestamp is valid prior to
485 * calling this function.
487 * Extract the 32bit nominal nanoseconds and extend them. Use the cached PHC
488 * time stored in the device private PTP structure as the basis for timestamp
491 * See ice_ptp_extend_32b_ts for a detailed explanation of the extension
494 static u64 ice_ptp_extend_40b_ts(struct ice_pf *pf, u64 in_tstamp)
496 const u64 mask = GENMASK_ULL(31, 0);
497 unsigned long discard_time;
499 /* Discard the hardware timestamp if the cached PHC time is too old */
500 discard_time = pf->ptp.cached_phc_jiffies + msecs_to_jiffies(2000);
501 if (time_is_before_jiffies(discard_time)) {
502 pf->ptp.tx_hwtstamp_discarded++;
506 return ice_ptp_extend_32b_ts(pf->ptp.cached_phc_time,
507 (in_tstamp >> 8) & mask);
511 * ice_ptp_is_tx_tracker_up - Check if Tx tracker is ready for new timestamps
512 * @tx: the PTP Tx timestamp tracker to check
514 * Check that a given PTP Tx timestamp tracker is up, i.e. that it is ready
515 * to accept new timestamp requests.
517 * Assumes the tx->lock spinlock is already held.
520 ice_ptp_is_tx_tracker_up(struct ice_ptp_tx *tx)
522 lockdep_assert_held(&tx->lock);
524 return tx->init && !tx->calibrating;
528 * ice_ptp_req_tx_single_tstamp - Request Tx timestamp for a port from FW
529 * @tx: the PTP Tx timestamp tracker
530 * @idx: index of the timestamp to request
532 void ice_ptp_req_tx_single_tstamp(struct ice_ptp_tx *tx, u8 idx)
534 struct ice_ptp_port *ptp_port;
541 ptp_port = container_of(tx, struct ice_ptp_port, tx);
542 pf = ptp_port_to_pf(ptp_port);
544 /* Drop packets which have waited for more than 2 seconds */
545 if (time_is_before_jiffies(tx->tstamps[idx].start + 2 * HZ)) {
546 /* Count the number of Tx timestamps that timed out */
547 pf->ptp.tx_hwtstamp_timeouts++;
549 skb = tx->tstamps[idx].skb;
550 tx->tstamps[idx].skb = NULL;
551 clear_bit(idx, tx->in_use);
553 dev_kfree_skb_any(skb);
557 ice_trace(tx_tstamp_fw_req, tx->tstamps[idx].skb, idx);
559 /* Write TS index to read to the PF register so the FW can read it */
560 wr32(&pf->hw, PF_SB_ATQBAL,
561 TS_LL_READ_TS_INTR | FIELD_PREP(TS_LL_READ_TS_IDX, idx) |
563 tx->last_ll_ts_idx_read = idx;
567 * ice_ptp_complete_tx_single_tstamp - Complete Tx timestamp for a port
568 * @tx: the PTP Tx timestamp tracker
570 void ice_ptp_complete_tx_single_tstamp(struct ice_ptp_tx *tx)
572 struct skb_shared_hwtstamps shhwtstamps = {};
573 u8 idx = tx->last_ll_ts_idx_read;
574 struct ice_ptp_port *ptp_port;
575 u64 raw_tstamp, tstamp;
576 bool drop_ts = false;
581 if (!tx->init || tx->last_ll_ts_idx_read < 0)
584 ptp_port = container_of(tx, struct ice_ptp_port, tx);
585 pf = ptp_port_to_pf(ptp_port);
587 ice_trace(tx_tstamp_fw_done, tx->tstamps[idx].skb, idx);
589 val = rd32(&pf->hw, PF_SB_ATQBAL);
591 /* When the bit is cleared, the TS is ready in the register */
592 if (val & TS_LL_READ_TS) {
593 dev_err(ice_pf_to_dev(pf), "Failed to get the Tx tstamp - FW not ready");
597 /* High 8 bit value of the TS is on the bits 16:23 */
598 raw_tstamp = FIELD_GET(TS_LL_READ_TS_HIGH, val);
601 /* Read the low 32 bit value */
602 raw_tstamp |= (u64)rd32(&pf->hw, PF_SB_ATQBAH);
604 /* Devices using this interface always verify the timestamp differs
605 * relative to the last cached timestamp value.
607 if (raw_tstamp == tx->tstamps[idx].cached_tstamp)
610 tx->tstamps[idx].cached_tstamp = raw_tstamp;
611 clear_bit(idx, tx->in_use);
612 skb = tx->tstamps[idx].skb;
613 tx->tstamps[idx].skb = NULL;
614 if (test_and_clear_bit(idx, tx->stale))
621 dev_kfree_skb_any(skb);
625 /* Extend the timestamp using cached PHC time */
626 tstamp = ice_ptp_extend_40b_ts(pf, raw_tstamp);
628 shhwtstamps.hwtstamp = ns_to_ktime(tstamp);
629 ice_trace(tx_tstamp_complete, skb, idx);
632 skb_tstamp_tx(skb, &shhwtstamps);
633 dev_kfree_skb_any(skb);
637 * ice_ptp_process_tx_tstamp - Process Tx timestamps for a port
638 * @tx: the PTP Tx timestamp tracker
640 * Process timestamps captured by the PHY associated with this port. To do
641 * this, loop over each index with a waiting skb.
643 * If a given index has a valid timestamp, perform the following steps:
645 * 1) check that the timestamp request is not stale
646 * 2) check that a timestamp is ready and available in the PHY memory bank
647 * 3) read and copy the timestamp out of the PHY register
648 * 4) unlock the index by clearing the associated in_use bit
649 * 5) check if the timestamp is stale, and discard if so
650 * 6) extend the 40 bit timestamp value to get a 64 bit timestamp value
651 * 7) send this 64 bit timestamp to the stack
653 * Note that we do not hold the tracking lock while reading the Tx timestamp.
654 * This is because reading the timestamp requires taking a mutex that might
657 * The only place where we set in_use is when a new timestamp is initiated
658 * with a slot index. This is only called in the hard xmit routine where an
659 * SKB has a request flag set. The only places where we clear this bit is this
660 * function, or during teardown when the Tx timestamp tracker is being
661 * removed. A timestamp index will never be re-used until the in_use bit for
662 * that index is cleared.
664 * If a Tx thread starts a new timestamp, we might not begin processing it
665 * right away but we will notice it at the end when we re-queue the task.
667 * If a Tx thread starts a new timestamp just after this function exits, the
668 * interrupt for that timestamp should re-trigger this function once
669 * a timestamp is ready.
671 * In cases where the PTP hardware clock was directly adjusted, some
672 * timestamps may not be able to safely use the timestamp extension math. In
673 * this case, software will set the stale bit for any outstanding Tx
674 * timestamps when the clock is adjusted. Then this function will discard
675 * those captured timestamps instead of sending them to the stack.
677 * If a Tx packet has been waiting for more than 2 seconds, it is not possible
678 * to correctly extend the timestamp using the cached PHC time. It is
679 * extremely unlikely that a packet will ever take this long to timestamp. If
680 * we detect a Tx timestamp request that has waited for this long we assume
681 * the packet will never be sent by hardware and discard it without reading
682 * the timestamp register.
684 static void ice_ptp_process_tx_tstamp(struct ice_ptp_tx *tx)
686 struct ice_ptp_port *ptp_port;
695 ptp_port = container_of(tx, struct ice_ptp_port, tx);
696 pf = ptp_port_to_pf(ptp_port);
699 /* Read the Tx ready status first */
700 if (tx->has_ready_bitmap) {
701 err = ice_get_phy_tx_tstamp_ready(hw, tx->block, &tstamp_ready);
706 /* Drop packets if the link went down */
707 link_up = ptp_port->link_up;
709 for_each_set_bit(idx, tx->in_use, tx->len) {
710 struct skb_shared_hwtstamps shhwtstamps = {};
711 u8 phy_idx = idx + tx->offset;
712 u64 raw_tstamp = 0, tstamp;
713 bool drop_ts = !link_up;
716 /* Drop packets which have waited for more than 2 seconds */
717 if (time_is_before_jiffies(tx->tstamps[idx].start + 2 * HZ)) {
720 /* Count the number of Tx timestamps that timed out */
721 pf->ptp.tx_hwtstamp_timeouts++;
724 /* Only read a timestamp from the PHY if its marked as ready
725 * by the tstamp_ready register. This avoids unnecessary
726 * reading of timestamps which are not yet valid. This is
727 * important as we must read all timestamps which are valid
728 * and only timestamps which are valid during each interrupt.
729 * If we do not, the hardware logic for generating a new
730 * interrupt can get stuck on some devices.
732 if (tx->has_ready_bitmap &&
733 !(tstamp_ready & BIT_ULL(phy_idx))) {
740 ice_trace(tx_tstamp_fw_req, tx->tstamps[idx].skb, idx);
742 err = ice_read_phy_tstamp(hw, tx->block, phy_idx, &raw_tstamp);
746 ice_trace(tx_tstamp_fw_done, tx->tstamps[idx].skb, idx);
748 /* For PHYs which don't implement a proper timestamp ready
749 * bitmap, verify that the timestamp value is different
750 * from the last cached timestamp. If it is not, skip this for
751 * now assuming it hasn't yet been captured by hardware.
753 if (!drop_ts && !tx->has_ready_bitmap &&
754 raw_tstamp == tx->tstamps[idx].cached_tstamp)
757 /* Discard any timestamp value without the valid bit set */
758 if (!(raw_tstamp & ICE_PTP_TS_VALID))
762 spin_lock_irqsave(&tx->lock, flags);
763 if (!tx->has_ready_bitmap && raw_tstamp)
764 tx->tstamps[idx].cached_tstamp = raw_tstamp;
765 clear_bit(idx, tx->in_use);
766 skb = tx->tstamps[idx].skb;
767 tx->tstamps[idx].skb = NULL;
768 if (test_and_clear_bit(idx, tx->stale))
770 spin_unlock_irqrestore(&tx->lock, flags);
772 /* It is unlikely but possible that the SKB will have been
773 * flushed at this point due to link change or teardown.
779 dev_kfree_skb_any(skb);
783 /* Extend the timestamp using cached PHC time */
784 tstamp = ice_ptp_extend_40b_ts(pf, raw_tstamp);
786 shhwtstamps.hwtstamp = ns_to_ktime(tstamp);
787 ice_trace(tx_tstamp_complete, skb, idx);
790 skb_tstamp_tx(skb, &shhwtstamps);
791 dev_kfree_skb_any(skb);
796 * ice_ptp_tx_tstamp_owner - Process Tx timestamps for all ports on the device
797 * @pf: Board private structure
799 static enum ice_tx_tstamp_work ice_ptp_tx_tstamp_owner(struct ice_pf *pf)
801 struct ice_ptp_port *port;
804 mutex_lock(&pf->ptp.ports_owner.lock);
805 list_for_each_entry(port, &pf->ptp.ports_owner.ports, list_member) {
806 struct ice_ptp_tx *tx = &port->tx;
808 if (!tx || !tx->init)
811 ice_ptp_process_tx_tstamp(tx);
813 mutex_unlock(&pf->ptp.ports_owner.lock);
815 for (i = 0; i < ICE_MAX_QUAD; i++) {
819 /* Read the Tx ready status first */
820 err = ice_get_phy_tx_tstamp_ready(&pf->hw, i, &tstamp_ready);
823 else if (tstamp_ready)
824 return ICE_TX_TSTAMP_WORK_PENDING;
827 return ICE_TX_TSTAMP_WORK_DONE;
831 * ice_ptp_tx_tstamp - Process Tx timestamps for this function.
832 * @tx: Tx tracking structure to initialize
834 * Returns: ICE_TX_TSTAMP_WORK_PENDING if there are any outstanding incomplete
835 * Tx timestamps, or ICE_TX_TSTAMP_WORK_DONE otherwise.
837 static enum ice_tx_tstamp_work ice_ptp_tx_tstamp(struct ice_ptp_tx *tx)
839 bool more_timestamps;
843 return ICE_TX_TSTAMP_WORK_DONE;
845 /* Process the Tx timestamp tracker */
846 ice_ptp_process_tx_tstamp(tx);
848 /* Check if there are outstanding Tx timestamps */
849 spin_lock_irqsave(&tx->lock, flags);
850 more_timestamps = tx->init && !bitmap_empty(tx->in_use, tx->len);
851 spin_unlock_irqrestore(&tx->lock, flags);
854 return ICE_TX_TSTAMP_WORK_PENDING;
856 return ICE_TX_TSTAMP_WORK_DONE;
860 * ice_ptp_alloc_tx_tracker - Initialize tracking for Tx timestamps
861 * @tx: Tx tracking structure to initialize
863 * Assumes that the length has already been initialized. Do not call directly,
864 * use the ice_ptp_init_tx_* instead.
867 ice_ptp_alloc_tx_tracker(struct ice_ptp_tx *tx)
869 unsigned long *in_use, *stale;
870 struct ice_tx_tstamp *tstamps;
872 tstamps = kcalloc(tx->len, sizeof(*tstamps), GFP_KERNEL);
873 in_use = bitmap_zalloc(tx->len, GFP_KERNEL);
874 stale = bitmap_zalloc(tx->len, GFP_KERNEL);
876 if (!tstamps || !in_use || !stale) {
884 tx->tstamps = tstamps;
888 tx->last_ll_ts_idx_read = -1;
890 spin_lock_init(&tx->lock);
896 * ice_ptp_flush_tx_tracker - Flush any remaining timestamps from the tracker
897 * @pf: Board private structure
898 * @tx: the tracker to flush
900 * Called during teardown when a Tx tracker is being removed.
903 ice_ptp_flush_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)
905 struct ice_hw *hw = &pf->hw;
911 err = ice_get_phy_tx_tstamp_ready(hw, tx->block, &tstamp_ready);
913 dev_dbg(ice_pf_to_dev(pf), "Failed to get the Tx tstamp ready bitmap for block %u, err %d\n",
916 /* If we fail to read the Tx timestamp ready bitmap just
917 * skip clearing the PHY timestamps.
922 for_each_set_bit(idx, tx->in_use, tx->len) {
923 u8 phy_idx = idx + tx->offset;
926 /* In case this timestamp is ready, we need to clear it. */
927 if (!hw->reset_ongoing && (tstamp_ready & BIT_ULL(phy_idx)))
928 ice_clear_phy_tstamp(hw, tx->block, phy_idx);
930 spin_lock_irqsave(&tx->lock, flags);
931 skb = tx->tstamps[idx].skb;
932 tx->tstamps[idx].skb = NULL;
933 clear_bit(idx, tx->in_use);
934 clear_bit(idx, tx->stale);
935 spin_unlock_irqrestore(&tx->lock, flags);
937 /* Count the number of Tx timestamps flushed */
938 pf->ptp.tx_hwtstamp_flushed++;
940 /* Free the SKB after we've cleared the bit */
941 dev_kfree_skb_any(skb);
946 * ice_ptp_mark_tx_tracker_stale - Mark unfinished timestamps as stale
947 * @tx: the tracker to mark
949 * Mark currently outstanding Tx timestamps as stale. This prevents sending
950 * their timestamp value to the stack. This is required to prevent extending
951 * the 40bit hardware timestamp incorrectly.
953 * This should be called when the PTP clock is modified such as after a set
957 ice_ptp_mark_tx_tracker_stale(struct ice_ptp_tx *tx)
961 spin_lock_irqsave(&tx->lock, flags);
962 bitmap_or(tx->stale, tx->stale, tx->in_use, tx->len);
963 spin_unlock_irqrestore(&tx->lock, flags);
967 * ice_ptp_release_tx_tracker - Release allocated memory for Tx tracker
968 * @pf: Board private structure
969 * @tx: Tx tracking structure to release
971 * Free memory associated with the Tx timestamp tracker.
974 ice_ptp_release_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)
978 spin_lock_irqsave(&tx->lock, flags);
980 spin_unlock_irqrestore(&tx->lock, flags);
982 /* wait for potentially outstanding interrupt to complete */
983 synchronize_irq(pf->oicr_irq.virq);
985 ice_ptp_flush_tx_tracker(pf, tx);
990 bitmap_free(tx->in_use);
993 bitmap_free(tx->stale);
1000 * ice_ptp_init_tx_e82x - Initialize tracking for Tx timestamps
1001 * @pf: Board private structure
1002 * @tx: the Tx tracking structure to initialize
1003 * @port: the port this structure tracks
1005 * Initialize the Tx timestamp tracker for this port. For generic MAC devices,
1006 * the timestamp block is shared for all ports in the same quad. To avoid
1007 * ports using the same timestamp index, logically break the block of
1008 * registers into chunks based on the port number.
1011 ice_ptp_init_tx_e82x(struct ice_pf *pf, struct ice_ptp_tx *tx, u8 port)
1013 tx->block = port / ICE_PORTS_PER_QUAD;
1014 tx->offset = (port % ICE_PORTS_PER_QUAD) * INDEX_PER_PORT_E82X;
1015 tx->len = INDEX_PER_PORT_E82X;
1016 tx->has_ready_bitmap = 1;
1018 return ice_ptp_alloc_tx_tracker(tx);
1022 * ice_ptp_init_tx_e810 - Initialize tracking for Tx timestamps
1023 * @pf: Board private structure
1024 * @tx: the Tx tracking structure to initialize
1026 * Initialize the Tx timestamp tracker for this PF. For E810 devices, each
1027 * port has its own block of timestamps, independent of the other ports.
1030 ice_ptp_init_tx_e810(struct ice_pf *pf, struct ice_ptp_tx *tx)
1032 tx->block = pf->hw.port_info->lport;
1034 tx->len = INDEX_PER_PORT_E810;
1035 /* The E810 PHY does not provide a timestamp ready bitmap. Instead,
1036 * verify new timestamps against cached copy of the last read
1039 tx->has_ready_bitmap = 0;
1041 return ice_ptp_alloc_tx_tracker(tx);
1045 * ice_ptp_update_cached_phctime - Update the cached PHC time values
1046 * @pf: Board specific private structure
1048 * This function updates the system time values which are cached in the PF
1049 * structure and the Rx rings.
1051 * This function must be called periodically to ensure that the cached value
1052 * is never more than 2 seconds old.
1054 * Note that the cached copy in the PF PTP structure is always updated, even
1055 * if we can't update the copy in the Rx rings.
1058 * * 0 - OK, successfully updated
1059 * * -EAGAIN - PF was busy, need to reschedule the update
1061 static int ice_ptp_update_cached_phctime(struct ice_pf *pf)
1063 struct device *dev = ice_pf_to_dev(pf);
1064 unsigned long update_before;
1068 update_before = pf->ptp.cached_phc_jiffies + msecs_to_jiffies(2000);
1069 if (pf->ptp.cached_phc_time &&
1070 time_is_before_jiffies(update_before)) {
1071 unsigned long time_taken = jiffies - pf->ptp.cached_phc_jiffies;
1073 dev_warn(dev, "%u msecs passed between update to cached PHC time\n",
1074 jiffies_to_msecs(time_taken));
1075 pf->ptp.late_cached_phc_updates++;
1078 /* Read the current PHC time */
1079 systime = ice_ptp_read_src_clk_reg(pf, NULL);
1081 /* Update the cached PHC time stored in the PF structure */
1082 WRITE_ONCE(pf->ptp.cached_phc_time, systime);
1083 WRITE_ONCE(pf->ptp.cached_phc_jiffies, jiffies);
1085 if (test_and_set_bit(ICE_CFG_BUSY, pf->state))
1088 ice_for_each_vsi(pf, i) {
1089 struct ice_vsi *vsi = pf->vsi[i];
1095 if (vsi->type != ICE_VSI_PF)
1098 ice_for_each_rxq(vsi, j) {
1099 if (!vsi->rx_rings[j])
1101 WRITE_ONCE(vsi->rx_rings[j]->cached_phctime, systime);
1104 clear_bit(ICE_CFG_BUSY, pf->state);
1110 * ice_ptp_reset_cached_phctime - Reset cached PHC time after an update
1111 * @pf: Board specific private structure
1113 * This function must be called when the cached PHC time is no longer valid,
1114 * such as after a time adjustment. It marks any currently outstanding Tx
1115 * timestamps as stale and updates the cached PHC time for both the PF and Rx
1118 * If updating the PHC time cannot be done immediately, a warning message is
1119 * logged and the work item is scheduled immediately to minimize the window
1120 * with a wrong cached timestamp.
1122 static void ice_ptp_reset_cached_phctime(struct ice_pf *pf)
1124 struct device *dev = ice_pf_to_dev(pf);
1127 /* Update the cached PHC time immediately if possible, otherwise
1128 * schedule the work item to execute soon.
1130 err = ice_ptp_update_cached_phctime(pf);
1132 /* If another thread is updating the Rx rings, we won't
1133 * properly reset them here. This could lead to reporting of
1134 * invalid timestamps, but there isn't much we can do.
1136 dev_warn(dev, "%s: ICE_CFG_BUSY, unable to immediately update cached PHC time\n",
1139 /* Queue the work item to update the Rx rings when possible */
1140 kthread_queue_delayed_work(pf->ptp.kworker, &pf->ptp.work,
1141 msecs_to_jiffies(10));
1144 /* Mark any outstanding timestamps as stale, since they might have
1145 * been captured in hardware before the time update. This could lead
1146 * to us extending them with the wrong cached value resulting in
1147 * incorrect timestamp values.
1149 ice_ptp_mark_tx_tracker_stale(&pf->ptp.port.tx);
1153 * ice_ptp_read_time - Read the time from the device
1154 * @pf: Board private structure
1155 * @ts: timespec structure to hold the current time value
1156 * @sts: Optional parameter for holding a pair of system timestamps from
1157 * the system clock. Will be ignored if NULL is given.
1159 * This function reads the source clock registers and stores them in a timespec.
1160 * However, since the registers are 64 bits of nanoseconds, we must convert the
1161 * result to a timespec before we can return.
1164 ice_ptp_read_time(struct ice_pf *pf, struct timespec64 *ts,
1165 struct ptp_system_timestamp *sts)
1167 u64 time_ns = ice_ptp_read_src_clk_reg(pf, sts);
1169 *ts = ns_to_timespec64(time_ns);
1173 * ice_ptp_write_init - Set PHC time to provided value
1174 * @pf: Board private structure
1175 * @ts: timespec structure that holds the new time value
1177 * Set the PHC time to the specified time provided in the timespec.
1179 static int ice_ptp_write_init(struct ice_pf *pf, struct timespec64 *ts)
1181 u64 ns = timespec64_to_ns(ts);
1182 struct ice_hw *hw = &pf->hw;
1184 return ice_ptp_init_time(hw, ns);
1188 * ice_ptp_write_adj - Adjust PHC clock time atomically
1189 * @pf: Board private structure
1190 * @adj: Adjustment in nanoseconds
1192 * Perform an atomic adjustment of the PHC time by the specified number of
1195 static int ice_ptp_write_adj(struct ice_pf *pf, s32 adj)
1197 struct ice_hw *hw = &pf->hw;
1199 return ice_ptp_adj_clock(hw, adj);
1203 * ice_base_incval - Get base timer increment value
1204 * @pf: Board private structure
1206 * Look up the base timer increment value for this device. The base increment
1207 * value is used to define the nominal clock tick rate. This increment value
1208 * is programmed during device initialization. It is also used as the basis
1209 * for calculating adjustments using scaled_ppm.
1211 static u64 ice_base_incval(struct ice_pf *pf)
1213 struct ice_hw *hw = &pf->hw;
1216 if (ice_is_e810(hw))
1217 incval = ICE_PTP_NOMINAL_INCVAL_E810;
1218 else if (ice_e82x_time_ref(hw) < NUM_ICE_TIME_REF_FREQ)
1219 incval = ice_e82x_nominal_incval(ice_e82x_time_ref(hw));
1221 incval = UNKNOWN_INCVAL_E82X;
1223 dev_dbg(ice_pf_to_dev(pf), "PTP: using base increment value of 0x%016llx\n",
1230 * ice_ptp_check_tx_fifo - Check whether Tx FIFO is in an OK state
1231 * @port: PTP port for which Tx FIFO is checked
1233 static int ice_ptp_check_tx_fifo(struct ice_ptp_port *port)
1235 int quad = port->port_num / ICE_PORTS_PER_QUAD;
1236 int offs = port->port_num % ICE_PORTS_PER_QUAD;
1242 pf = ptp_port_to_pf(port);
1245 if (port->tx_fifo_busy_cnt == FIFO_OK)
1248 /* need to read FIFO state */
1249 if (offs == 0 || offs == 1)
1250 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_FIFO01_STATUS,
1253 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_FIFO23_STATUS,
1257 dev_err(ice_pf_to_dev(pf), "PTP failed to check port %d Tx FIFO, err %d\n",
1258 port->port_num, err);
1263 phy_sts = FIELD_GET(Q_REG_FIFO13_M, val);
1265 phy_sts = FIELD_GET(Q_REG_FIFO02_M, val);
1267 if (phy_sts & FIFO_EMPTY) {
1268 port->tx_fifo_busy_cnt = FIFO_OK;
1272 port->tx_fifo_busy_cnt++;
1274 dev_dbg(ice_pf_to_dev(pf), "Try %d, port %d FIFO not empty\n",
1275 port->tx_fifo_busy_cnt, port->port_num);
1277 if (port->tx_fifo_busy_cnt == ICE_PTP_FIFO_NUM_CHECKS) {
1278 dev_dbg(ice_pf_to_dev(pf),
1279 "Port %d Tx FIFO still not empty; resetting quad %d\n",
1280 port->port_num, quad);
1281 ice_ptp_reset_ts_memory_quad_e82x(hw, quad);
1282 port->tx_fifo_busy_cnt = FIFO_OK;
1290 * ice_ptp_wait_for_offsets - Check for valid Tx and Rx offsets
1291 * @work: Pointer to the kthread_work structure for this task
1293 * Check whether hardware has completed measuring the Tx and Rx offset values
1294 * used to configure and enable vernier timestamp calibration.
1296 * Once the offset in either direction is measured, configure the associated
1297 * registers with the calibrated offset values and enable timestamping. The Tx
1298 * and Rx directions are configured independently as soon as their associated
1299 * offsets are known.
1301 * This function reschedules itself until both Tx and Rx calibration have
1304 static void ice_ptp_wait_for_offsets(struct kthread_work *work)
1306 struct ice_ptp_port *port;
1312 port = container_of(work, struct ice_ptp_port, ov_work.work);
1313 pf = ptp_port_to_pf(port);
1316 if (ice_is_reset_in_progress(pf->state)) {
1317 /* wait for device driver to complete reset */
1318 kthread_queue_delayed_work(pf->ptp.kworker,
1320 msecs_to_jiffies(100));
1324 tx_err = ice_ptp_check_tx_fifo(port);
1326 tx_err = ice_phy_cfg_tx_offset_e82x(hw, port->port_num);
1327 rx_err = ice_phy_cfg_rx_offset_e82x(hw, port->port_num);
1328 if (tx_err || rx_err) {
1329 /* Tx and/or Rx offset not yet configured, try again later */
1330 kthread_queue_delayed_work(pf->ptp.kworker,
1332 msecs_to_jiffies(100));
1338 * ice_ptp_port_phy_stop - Stop timestamping for a PHY port
1339 * @ptp_port: PTP port to stop
1342 ice_ptp_port_phy_stop(struct ice_ptp_port *ptp_port)
1344 struct ice_pf *pf = ptp_port_to_pf(ptp_port);
1345 u8 port = ptp_port->port_num;
1346 struct ice_hw *hw = &pf->hw;
1349 if (ice_is_e810(hw))
1352 mutex_lock(&ptp_port->ps_lock);
1354 kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
1356 err = ice_stop_phy_timer_e82x(hw, port, true);
1358 dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d down, err %d\n",
1361 mutex_unlock(&ptp_port->ps_lock);
1367 * ice_ptp_port_phy_restart - (Re)start and calibrate PHY timestamping
1368 * @ptp_port: PTP port for which the PHY start is set
1370 * Start the PHY timestamping block, and initiate Vernier timestamping
1371 * calibration. If timestamping cannot be calibrated (such as if link is down)
1372 * then disable the timestamping block instead.
1375 ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port)
1377 struct ice_pf *pf = ptp_port_to_pf(ptp_port);
1378 u8 port = ptp_port->port_num;
1379 struct ice_hw *hw = &pf->hw;
1380 unsigned long flags;
1383 if (ice_is_e810(hw))
1386 if (!ptp_port->link_up)
1387 return ice_ptp_port_phy_stop(ptp_port);
1389 mutex_lock(&ptp_port->ps_lock);
1391 kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
1393 /* temporarily disable Tx timestamps while calibrating PHY offset */
1394 spin_lock_irqsave(&ptp_port->tx.lock, flags);
1395 ptp_port->tx.calibrating = true;
1396 spin_unlock_irqrestore(&ptp_port->tx.lock, flags);
1397 ptp_port->tx_fifo_busy_cnt = 0;
1399 /* Start the PHY timer in Vernier mode */
1400 err = ice_start_phy_timer_e82x(hw, port);
1404 /* Enable Tx timestamps right away */
1405 spin_lock_irqsave(&ptp_port->tx.lock, flags);
1406 ptp_port->tx.calibrating = false;
1407 spin_unlock_irqrestore(&ptp_port->tx.lock, flags);
1409 kthread_queue_delayed_work(pf->ptp.kworker, &ptp_port->ov_work, 0);
1413 dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d up, err %d\n",
1416 mutex_unlock(&ptp_port->ps_lock);
1422 * ice_ptp_link_change - Reconfigure PTP after link status change
1423 * @pf: Board private structure
1424 * @port: Port for which the PHY start is set
1425 * @linkup: Link is up or down
1427 void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup)
1429 struct ice_ptp_port *ptp_port;
1430 struct ice_hw *hw = &pf->hw;
1432 if (pf->ptp.state != ICE_PTP_READY)
1435 if (WARN_ON_ONCE(port >= ICE_NUM_EXTERNAL_PORTS))
1438 ptp_port = &pf->ptp.port;
1439 if (WARN_ON_ONCE(ptp_port->port_num != port))
1442 /* Update cached link status for this port immediately */
1443 ptp_port->link_up = linkup;
1445 switch (hw->phy_model) {
1447 /* Do not reconfigure E810 PHY */
1450 ice_ptp_port_phy_restart(ptp_port);
1453 dev_warn(ice_pf_to_dev(pf), "%s: Unknown PHY type\n", __func__);
1458 * ice_ptp_cfg_phy_interrupt - Configure PHY interrupt settings
1459 * @pf: PF private structure
1460 * @ena: bool value to enable or disable interrupt
1461 * @threshold: Minimum number of packets at which intr is triggered
1463 * Utility function to enable or disable Tx timestamp interrupt and threshold
1465 static int ice_ptp_cfg_phy_interrupt(struct ice_pf *pf, bool ena, u32 threshold)
1467 struct ice_hw *hw = &pf->hw;
1472 ice_ptp_reset_ts_memory(hw);
1474 for (quad = 0; quad < ICE_MAX_QUAD; quad++) {
1475 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG,
1481 val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
1482 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;
1483 val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M,
1486 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
1489 err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG,
1496 dev_err(ice_pf_to_dev(pf), "PTP failed in intr ena, err %d\n",
1502 * ice_ptp_reset_phy_timestamping - Reset PHY timestamping block
1503 * @pf: Board private structure
1505 static void ice_ptp_reset_phy_timestamping(struct ice_pf *pf)
1507 ice_ptp_port_phy_restart(&pf->ptp.port);
1511 * ice_ptp_restart_all_phy - Restart all PHYs to recalibrate timestamping
1512 * @pf: Board private structure
1514 static void ice_ptp_restart_all_phy(struct ice_pf *pf)
1516 struct list_head *entry;
1518 list_for_each(entry, &pf->ptp.ports_owner.ports) {
1519 struct ice_ptp_port *port = list_entry(entry,
1520 struct ice_ptp_port,
1524 ice_ptp_port_phy_restart(port);
1529 * ice_ptp_adjfine - Adjust clock increment rate
1530 * @info: the driver's PTP info structure
1531 * @scaled_ppm: Parts per million with 16-bit fractional field
1533 * Adjust the frequency of the clock by the indicated scaled ppm from the
1536 static int ice_ptp_adjfine(struct ptp_clock_info *info, long scaled_ppm)
1538 struct ice_pf *pf = ptp_info_to_pf(info);
1539 struct ice_hw *hw = &pf->hw;
1543 incval = adjust_by_scaled_ppm(ice_base_incval(pf), scaled_ppm);
1544 err = ice_ptp_write_incval_locked(hw, incval);
1546 dev_err(ice_pf_to_dev(pf), "PTP failed to set incval, err %d\n",
1555 * ice_ptp_extts_event - Process PTP external clock event
1556 * @pf: Board private structure
1558 void ice_ptp_extts_event(struct ice_pf *pf)
1560 struct ptp_clock_event event;
1561 struct ice_hw *hw = &pf->hw;
1565 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
1566 /* Event time is captured by one of the two matched registers
1567 * GLTSYN_EVNT_L: 32 LSB of sampled time event
1568 * GLTSYN_EVNT_H: 32 MSB of sampled time event
1569 * Event is defined in GLTSYN_EVNT_0 register
1571 for (chan = 0; chan < GLTSYN_EVNT_H_IDX_MAX; chan++) {
1572 /* Check if channel is enabled */
1573 if (pf->ptp.ext_ts_irq & (1 << chan)) {
1574 lo = rd32(hw, GLTSYN_EVNT_L(chan, tmr_idx));
1575 hi = rd32(hw, GLTSYN_EVNT_H(chan, tmr_idx));
1576 event.timestamp = (((u64)hi) << 32) | lo;
1577 event.type = PTP_CLOCK_EXTTS;
1581 ptp_clock_event(pf->ptp.clock, &event);
1582 pf->ptp.ext_ts_irq &= ~(1 << chan);
1588 * ice_ptp_cfg_extts - Configure EXTTS pin and channel
1589 * @pf: Board private structure
1590 * @ena: true to enable; false to disable
1591 * @chan: GPIO channel (0-3)
1592 * @gpio_pin: GPIO pin
1593 * @extts_flags: request flags from the ptp_extts_request.flags
1596 ice_ptp_cfg_extts(struct ice_pf *pf, bool ena, unsigned int chan, u32 gpio_pin,
1597 unsigned int extts_flags)
1599 u32 func, aux_reg, gpio_reg, irq_reg;
1600 struct ice_hw *hw = &pf->hw;
1603 if (chan > (unsigned int)pf->ptp.info.n_ext_ts)
1606 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
1608 irq_reg = rd32(hw, PFINT_OICR_ENA);
1611 /* Enable the interrupt */
1612 irq_reg |= PFINT_OICR_TSYN_EVNT_M;
1613 aux_reg = GLTSYN_AUX_IN_0_INT_ENA_M;
1615 #define GLTSYN_AUX_IN_0_EVNTLVL_RISING_EDGE BIT(0)
1616 #define GLTSYN_AUX_IN_0_EVNTLVL_FALLING_EDGE BIT(1)
1618 /* set event level to requested edge */
1619 if (extts_flags & PTP_FALLING_EDGE)
1620 aux_reg |= GLTSYN_AUX_IN_0_EVNTLVL_FALLING_EDGE;
1621 if (extts_flags & PTP_RISING_EDGE)
1622 aux_reg |= GLTSYN_AUX_IN_0_EVNTLVL_RISING_EDGE;
1624 /* Write GPIO CTL reg.
1625 * 0x1 is input sampled by EVENT register(channel)
1626 * + num_in_channels * tmr_idx
1628 func = 1 + chan + (tmr_idx * 3);
1629 gpio_reg = FIELD_PREP(GLGEN_GPIO_CTL_PIN_FUNC_M, func);
1630 pf->ptp.ext_ts_chan |= (1 << chan);
1632 /* clear the values we set to reset defaults */
1635 pf->ptp.ext_ts_chan &= ~(1 << chan);
1636 if (!pf->ptp.ext_ts_chan)
1637 irq_reg &= ~PFINT_OICR_TSYN_EVNT_M;
1640 wr32(hw, PFINT_OICR_ENA, irq_reg);
1641 wr32(hw, GLTSYN_AUX_IN(chan, tmr_idx), aux_reg);
1642 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), gpio_reg);
1648 * ice_ptp_cfg_clkout - Configure clock to generate periodic wave
1649 * @pf: Board private structure
1650 * @chan: GPIO channel (0-3)
1651 * @config: desired periodic clk configuration. NULL will disable channel
1652 * @store: If set to true the values will be stored
1654 * Configure the internal clock generator modules to generate the clock wave of
1657 static int ice_ptp_cfg_clkout(struct ice_pf *pf, unsigned int chan,
1658 struct ice_perout_channel *config, bool store)
1660 u64 current_time, period, start_time, phase;
1661 struct ice_hw *hw = &pf->hw;
1662 u32 func, val, gpio_pin;
1665 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
1667 /* 0. Reset mode & out_en in AUX_OUT */
1668 wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), 0);
1670 /* If we're disabling the output, clear out CLKO and TGT and keep
1673 if (!config || !config->ena) {
1674 wr32(hw, GLTSYN_CLKO(chan, tmr_idx), 0);
1675 wr32(hw, GLTSYN_TGT_L(chan, tmr_idx), 0);
1676 wr32(hw, GLTSYN_TGT_H(chan, tmr_idx), 0);
1678 val = GLGEN_GPIO_CTL_PIN_DIR_M;
1679 gpio_pin = pf->ptp.perout_channels[chan].gpio_pin;
1680 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), val);
1682 /* Store the value if requested */
1684 memset(&pf->ptp.perout_channels[chan], 0,
1685 sizeof(struct ice_perout_channel));
1689 period = config->period;
1690 start_time = config->start_time;
1691 div64_u64_rem(start_time, period, &phase);
1692 gpio_pin = config->gpio_pin;
1694 /* 1. Write clkout with half of required period value */
1696 dev_err(ice_pf_to_dev(pf), "CLK Period must be an even value\n");
1702 /* For proper operation, the GLTSYN_CLKO must be larger than clock tick
1705 if (period <= MIN_PULSE || period > U32_MAX) {
1706 dev_err(ice_pf_to_dev(pf), "CLK Period must be > %d && < 2^33",
1711 wr32(hw, GLTSYN_CLKO(chan, tmr_idx), lower_32_bits(period));
1713 /* Allow time for programming before start_time is hit */
1714 current_time = ice_ptp_read_src_clk_reg(pf, NULL);
1716 /* if start time is in the past start the timer at the nearest second
1719 if (start_time < current_time)
1720 start_time = div64_u64(current_time + NSEC_PER_SEC - 1,
1721 NSEC_PER_SEC) * NSEC_PER_SEC + phase;
1723 if (ice_is_e810(hw))
1724 start_time -= E810_OUT_PROP_DELAY_NS;
1726 start_time -= ice_e82x_pps_delay(ice_e82x_time_ref(hw));
1728 /* 2. Write TARGET time */
1729 wr32(hw, GLTSYN_TGT_L(chan, tmr_idx), lower_32_bits(start_time));
1730 wr32(hw, GLTSYN_TGT_H(chan, tmr_idx), upper_32_bits(start_time));
1732 /* 3. Write AUX_OUT register */
1733 val = GLTSYN_AUX_OUT_0_OUT_ENA_M | GLTSYN_AUX_OUT_0_OUTMOD_M;
1734 wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), val);
1736 /* 4. write GPIO CTL reg */
1737 func = 8 + chan + (tmr_idx * 4);
1738 val = GLGEN_GPIO_CTL_PIN_DIR_M |
1739 FIELD_PREP(GLGEN_GPIO_CTL_PIN_FUNC_M, func);
1740 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), val);
1742 /* Store the value if requested */
1744 memcpy(&pf->ptp.perout_channels[chan], config,
1745 sizeof(struct ice_perout_channel));
1746 pf->ptp.perout_channels[chan].start_time = phase;
1751 dev_err(ice_pf_to_dev(pf), "PTP failed to cfg per_clk\n");
1756 * ice_ptp_disable_all_clkout - Disable all currently configured outputs
1757 * @pf: pointer to the PF structure
1759 * Disable all currently configured clock outputs. This is necessary before
1760 * certain changes to the PTP hardware clock. Use ice_ptp_enable_all_clkout to
1761 * re-enable the clocks again.
1763 static void ice_ptp_disable_all_clkout(struct ice_pf *pf)
1767 for (i = 0; i < pf->ptp.info.n_per_out; i++)
1768 if (pf->ptp.perout_channels[i].ena)
1769 ice_ptp_cfg_clkout(pf, i, NULL, false);
1773 * ice_ptp_enable_all_clkout - Enable all configured periodic clock outputs
1774 * @pf: pointer to the PF structure
1776 * Enable all currently configured clock outputs. Use this after
1777 * ice_ptp_disable_all_clkout to reconfigure the output signals according to
1778 * their configuration.
1780 static void ice_ptp_enable_all_clkout(struct ice_pf *pf)
1784 for (i = 0; i < pf->ptp.info.n_per_out; i++)
1785 if (pf->ptp.perout_channels[i].ena)
1786 ice_ptp_cfg_clkout(pf, i, &pf->ptp.perout_channels[i],
1791 * ice_ptp_gpio_enable_e810 - Enable/disable ancillary features of PHC
1792 * @info: the driver's PTP info structure
1793 * @rq: The requested feature to change
1794 * @on: Enable/disable flag
1797 ice_ptp_gpio_enable_e810(struct ptp_clock_info *info,
1798 struct ptp_clock_request *rq, int on)
1800 struct ice_pf *pf = ptp_info_to_pf(info);
1801 struct ice_perout_channel clk_cfg = {0};
1802 bool sma_pres = false;
1807 if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL))
1811 case PTP_CLK_REQ_PEROUT:
1812 chan = rq->perout.index;
1814 if (chan == ice_pin_desc_e810t[SMA1].chan)
1815 clk_cfg.gpio_pin = GPIO_20;
1816 else if (chan == ice_pin_desc_e810t[SMA2].chan)
1817 clk_cfg.gpio_pin = GPIO_22;
1820 } else if (ice_is_e810t(&pf->hw)) {
1822 clk_cfg.gpio_pin = GPIO_20;
1824 clk_cfg.gpio_pin = GPIO_22;
1825 } else if (chan == PPS_CLK_GEN_CHAN) {
1826 clk_cfg.gpio_pin = PPS_PIN_INDEX;
1828 clk_cfg.gpio_pin = chan;
1831 clk_cfg.period = ((rq->perout.period.sec * NSEC_PER_SEC) +
1832 rq->perout.period.nsec);
1833 clk_cfg.start_time = ((rq->perout.start.sec * NSEC_PER_SEC) +
1834 rq->perout.start.nsec);
1837 err = ice_ptp_cfg_clkout(pf, chan, &clk_cfg, true);
1839 case PTP_CLK_REQ_EXTTS:
1840 chan = rq->extts.index;
1842 if (chan < ice_pin_desc_e810t[SMA2].chan)
1846 } else if (ice_is_e810t(&pf->hw)) {
1855 err = ice_ptp_cfg_extts(pf, !!on, chan, gpio_pin,
1866 * ice_ptp_gpio_enable_e823 - Enable/disable ancillary features of PHC
1867 * @info: the driver's PTP info structure
1868 * @rq: The requested feature to change
1869 * @on: Enable/disable flag
1871 static int ice_ptp_gpio_enable_e823(struct ptp_clock_info *info,
1872 struct ptp_clock_request *rq, int on)
1874 struct ice_pf *pf = ptp_info_to_pf(info);
1875 struct ice_perout_channel clk_cfg = {0};
1879 case PTP_CLK_REQ_PPS:
1880 clk_cfg.gpio_pin = PPS_PIN_INDEX;
1881 clk_cfg.period = NSEC_PER_SEC;
1884 err = ice_ptp_cfg_clkout(pf, PPS_CLK_GEN_CHAN, &clk_cfg, true);
1886 case PTP_CLK_REQ_EXTTS:
1887 err = ice_ptp_cfg_extts(pf, !!on, rq->extts.index,
1888 TIME_SYNC_PIN_INDEX, rq->extts.flags);
1898 * ice_ptp_gettimex64 - Get the time of the clock
1899 * @info: the driver's PTP info structure
1900 * @ts: timespec64 structure to hold the current time value
1901 * @sts: Optional parameter for holding a pair of system timestamps from
1902 * the system clock. Will be ignored if NULL is given.
1904 * Read the device clock and return the correct value on ns, after converting it
1905 * into a timespec struct.
1908 ice_ptp_gettimex64(struct ptp_clock_info *info, struct timespec64 *ts,
1909 struct ptp_system_timestamp *sts)
1911 struct ice_pf *pf = ptp_info_to_pf(info);
1912 struct ice_hw *hw = &pf->hw;
1914 if (!ice_ptp_lock(hw)) {
1915 dev_err(ice_pf_to_dev(pf), "PTP failed to get time\n");
1919 ice_ptp_read_time(pf, ts, sts);
1926 * ice_ptp_settime64 - Set the time of the clock
1927 * @info: the driver's PTP info structure
1928 * @ts: timespec64 structure that holds the new time value
1930 * Set the device clock to the user input value. The conversion from timespec
1931 * to ns happens in the write function.
1934 ice_ptp_settime64(struct ptp_clock_info *info, const struct timespec64 *ts)
1936 struct ice_pf *pf = ptp_info_to_pf(info);
1937 struct timespec64 ts64 = *ts;
1938 struct ice_hw *hw = &pf->hw;
1941 /* For Vernier mode, we need to recalibrate after new settime
1942 * Start with disabling timestamp block
1944 if (pf->ptp.port.link_up)
1945 ice_ptp_port_phy_stop(&pf->ptp.port);
1947 if (!ice_ptp_lock(hw)) {
1952 /* Disable periodic outputs */
1953 ice_ptp_disable_all_clkout(pf);
1955 err = ice_ptp_write_init(pf, &ts64);
1959 ice_ptp_reset_cached_phctime(pf);
1961 /* Reenable periodic outputs */
1962 ice_ptp_enable_all_clkout(pf);
1964 /* Recalibrate and re-enable timestamp blocks for E822/E823 */
1965 if (hw->phy_model == ICE_PHY_E82X)
1966 ice_ptp_restart_all_phy(pf);
1969 dev_err(ice_pf_to_dev(pf), "PTP failed to set time %d\n", err);
1977 * ice_ptp_adjtime_nonatomic - Do a non-atomic clock adjustment
1978 * @info: the driver's PTP info structure
1979 * @delta: Offset in nanoseconds to adjust the time by
1981 static int ice_ptp_adjtime_nonatomic(struct ptp_clock_info *info, s64 delta)
1983 struct timespec64 now, then;
1986 then = ns_to_timespec64(delta);
1987 ret = ice_ptp_gettimex64(info, &now, NULL);
1990 now = timespec64_add(now, then);
1992 return ice_ptp_settime64(info, (const struct timespec64 *)&now);
1996 * ice_ptp_adjtime - Adjust the time of the clock by the indicated delta
1997 * @info: the driver's PTP info structure
1998 * @delta: Offset in nanoseconds to adjust the time by
2000 static int ice_ptp_adjtime(struct ptp_clock_info *info, s64 delta)
2002 struct ice_pf *pf = ptp_info_to_pf(info);
2003 struct ice_hw *hw = &pf->hw;
2007 dev = ice_pf_to_dev(pf);
2009 /* Hardware only supports atomic adjustments using signed 32-bit
2010 * integers. For any adjustment outside this range, perform
2011 * a non-atomic get->adjust->set flow.
2013 if (delta > S32_MAX || delta < S32_MIN) {
2014 dev_dbg(dev, "delta = %lld, adjtime non-atomic\n", delta);
2015 return ice_ptp_adjtime_nonatomic(info, delta);
2018 if (!ice_ptp_lock(hw)) {
2019 dev_err(dev, "PTP failed to acquire semaphore in adjtime\n");
2023 /* Disable periodic outputs */
2024 ice_ptp_disable_all_clkout(pf);
2026 err = ice_ptp_write_adj(pf, delta);
2028 /* Reenable periodic outputs */
2029 ice_ptp_enable_all_clkout(pf);
2034 dev_err(dev, "PTP failed to adjust time, err %d\n", err);
2038 ice_ptp_reset_cached_phctime(pf);
2043 #ifdef CONFIG_ICE_HWTS
2045 * ice_ptp_get_syncdevicetime - Get the cross time stamp info
2046 * @device: Current device time
2047 * @system: System counter value read synchronously with device time
2048 * @ctx: Context provided by timekeeping code
2050 * Read device and system (ART) clock simultaneously and return the corrected
2051 * clock values in ns.
2054 ice_ptp_get_syncdevicetime(ktime_t *device,
2055 struct system_counterval_t *system,
2058 struct ice_pf *pf = (struct ice_pf *)ctx;
2059 struct ice_hw *hw = &pf->hw;
2060 u32 hh_lock, hh_art_ctl;
2063 #define MAX_HH_HW_LOCK_TRIES 5
2064 #define MAX_HH_CTL_LOCK_TRIES 100
2066 for (i = 0; i < MAX_HH_HW_LOCK_TRIES; i++) {
2067 /* Get the HW lock */
2068 hh_lock = rd32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
2069 if (hh_lock & PFHH_SEM_BUSY_M) {
2070 usleep_range(10000, 15000);
2075 if (hh_lock & PFHH_SEM_BUSY_M) {
2076 dev_err(ice_pf_to_dev(pf), "PTP failed to get hh lock\n");
2080 /* Program cmd to master timer */
2081 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);
2083 /* Start the ART and device clock sync sequence */
2084 hh_art_ctl = rd32(hw, GLHH_ART_CTL);
2085 hh_art_ctl = hh_art_ctl | GLHH_ART_CTL_ACTIVE_M;
2086 wr32(hw, GLHH_ART_CTL, hh_art_ctl);
2088 for (i = 0; i < MAX_HH_CTL_LOCK_TRIES; i++) {
2089 /* Wait for sync to complete */
2090 hh_art_ctl = rd32(hw, GLHH_ART_CTL);
2091 if (hh_art_ctl & GLHH_ART_CTL_ACTIVE_M) {
2095 u32 hh_ts_lo, hh_ts_hi, tmr_idx;
2098 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
2100 hh_ts_lo = rd32(hw, GLHH_ART_TIME_L);
2101 hh_ts_hi = rd32(hw, GLHH_ART_TIME_H);
2102 hh_ts = ((u64)hh_ts_hi << 32) | hh_ts_lo;
2103 *system = convert_art_ns_to_tsc(hh_ts);
2104 /* Read Device source clock time */
2105 hh_ts_lo = rd32(hw, GLTSYN_HHTIME_L(tmr_idx));
2106 hh_ts_hi = rd32(hw, GLTSYN_HHTIME_H(tmr_idx));
2107 hh_ts = ((u64)hh_ts_hi << 32) | hh_ts_lo;
2108 *device = ns_to_ktime(hh_ts);
2113 /* Clear the master timer */
2114 ice_ptp_src_cmd(hw, ICE_PTP_NOP);
2116 /* Release HW lock */
2117 hh_lock = rd32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
2118 hh_lock = hh_lock & ~PFHH_SEM_BUSY_M;
2119 wr32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), hh_lock);
2121 if (i == MAX_HH_CTL_LOCK_TRIES)
2128 * ice_ptp_getcrosststamp_e82x - Capture a device cross timestamp
2129 * @info: the driver's PTP info structure
2130 * @cts: The memory to fill the cross timestamp info
2132 * Capture a cross timestamp between the ART and the device PTP hardware
2133 * clock. Fill the cross timestamp information and report it back to the
2136 * This is only valid for E822 and E823 devices which have support for
2137 * generating the cross timestamp via PCIe PTM.
2139 * In order to correctly correlate the ART timestamp back to the TSC time, the
2140 * CPU must have X86_FEATURE_TSC_KNOWN_FREQ.
2143 ice_ptp_getcrosststamp_e82x(struct ptp_clock_info *info,
2144 struct system_device_crosststamp *cts)
2146 struct ice_pf *pf = ptp_info_to_pf(info);
2148 return get_device_system_crosststamp(ice_ptp_get_syncdevicetime,
2151 #endif /* CONFIG_ICE_HWTS */
2154 * ice_ptp_get_ts_config - ioctl interface to read the timestamping config
2155 * @pf: Board private structure
2158 * Copy the timestamping config to user buffer
2160 int ice_ptp_get_ts_config(struct ice_pf *pf, struct ifreq *ifr)
2162 struct hwtstamp_config *config;
2164 if (pf->ptp.state != ICE_PTP_READY)
2167 config = &pf->ptp.tstamp_config;
2169 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
2174 * ice_ptp_set_timestamp_mode - Setup driver for requested timestamp mode
2175 * @pf: Board private structure
2176 * @config: hwtstamp settings requested or saved
2179 ice_ptp_set_timestamp_mode(struct ice_pf *pf, struct hwtstamp_config *config)
2181 switch (config->tx_type) {
2182 case HWTSTAMP_TX_OFF:
2183 pf->ptp.tstamp_config.tx_type = HWTSTAMP_TX_OFF;
2185 case HWTSTAMP_TX_ON:
2186 pf->ptp.tstamp_config.tx_type = HWTSTAMP_TX_ON;
2192 switch (config->rx_filter) {
2193 case HWTSTAMP_FILTER_NONE:
2194 pf->ptp.tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
2196 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2197 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2198 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2199 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2200 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2201 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2202 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2203 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2204 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2205 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2206 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2207 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2208 case HWTSTAMP_FILTER_NTP_ALL:
2209 case HWTSTAMP_FILTER_ALL:
2210 pf->ptp.tstamp_config.rx_filter = HWTSTAMP_FILTER_ALL;
2216 /* Immediately update the device timestamping mode */
2217 ice_ptp_restore_timestamp_mode(pf);
2223 * ice_ptp_set_ts_config - ioctl interface to control the timestamping
2224 * @pf: Board private structure
2227 * Get the user config and store it
2229 int ice_ptp_set_ts_config(struct ice_pf *pf, struct ifreq *ifr)
2231 struct hwtstamp_config config;
2234 if (pf->ptp.state != ICE_PTP_READY)
2237 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2240 err = ice_ptp_set_timestamp_mode(pf, &config);
2244 /* Return the actual configuration set */
2245 config = pf->ptp.tstamp_config;
2247 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2252 * ice_ptp_get_rx_hwts - Get packet Rx timestamp in ns
2253 * @rx_desc: Receive descriptor
2254 * @pkt_ctx: Packet context to get the cached time
2256 * The driver receives a notification in the receive descriptor with timestamp.
2258 u64 ice_ptp_get_rx_hwts(const union ice_32b_rx_flex_desc *rx_desc,
2259 const struct ice_pkt_ctx *pkt_ctx)
2261 u64 ts_ns, cached_time;
2264 if (!(rx_desc->wb.time_stamp_low & ICE_PTP_TS_VALID))
2267 cached_time = READ_ONCE(pkt_ctx->cached_phctime);
2269 /* Do not report a timestamp if we don't have a cached PHC time */
2273 /* Use ice_ptp_extend_32b_ts directly, using the ring-specific cached
2274 * PHC value, rather than accessing the PF. This also allows us to
2275 * simply pass the upper 32bits of nanoseconds directly. Calling
2276 * ice_ptp_extend_40b_ts is unnecessary as it would just discard these
2279 ts_high = le32_to_cpu(rx_desc->wb.flex_ts.ts_high);
2280 ts_ns = ice_ptp_extend_32b_ts(cached_time, ts_high);
2286 * ice_ptp_disable_sma_pins_e810t - Disable E810-T SMA pins
2287 * @pf: pointer to the PF structure
2288 * @info: PTP clock info structure
2290 * Disable the OS access to the SMA pins. Called to clear out the OS
2291 * indications of pin support when we fail to setup the E810-T SMA control
2295 ice_ptp_disable_sma_pins_e810t(struct ice_pf *pf, struct ptp_clock_info *info)
2297 struct device *dev = ice_pf_to_dev(pf);
2299 dev_warn(dev, "Failed to configure E810-T SMA pin control\n");
2301 info->enable = NULL;
2302 info->verify = NULL;
2305 info->n_per_out = 0;
2309 * ice_ptp_setup_sma_pins_e810t - Setup the SMA pins
2310 * @pf: pointer to the PF structure
2311 * @info: PTP clock info structure
2313 * Finish setting up the SMA pins by allocating pin_config, and setting it up
2314 * according to the current status of the SMA. On failure, disable all of the
2315 * extended SMA pin support.
2318 ice_ptp_setup_sma_pins_e810t(struct ice_pf *pf, struct ptp_clock_info *info)
2320 struct device *dev = ice_pf_to_dev(pf);
2323 /* Allocate memory for kernel pins interface */
2324 info->pin_config = devm_kcalloc(dev, info->n_pins,
2325 sizeof(*info->pin_config), GFP_KERNEL);
2326 if (!info->pin_config) {
2327 ice_ptp_disable_sma_pins_e810t(pf, info);
2331 /* Read current SMA status */
2332 err = ice_get_sma_config_e810t(&pf->hw, info->pin_config);
2334 ice_ptp_disable_sma_pins_e810t(pf, info);
2338 * ice_ptp_setup_pins_e810 - Setup PTP pins in sysfs
2339 * @pf: pointer to the PF instance
2340 * @info: PTP clock capabilities
2343 ice_ptp_setup_pins_e810(struct ice_pf *pf, struct ptp_clock_info *info)
2345 if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL)) {
2346 info->n_ext_ts = N_EXT_TS_E810;
2347 info->n_per_out = N_PER_OUT_E810T;
2348 info->n_pins = NUM_PTP_PINS_E810T;
2349 info->verify = ice_verify_pin_e810t;
2351 /* Complete setup of the SMA pins */
2352 ice_ptp_setup_sma_pins_e810t(pf, info);
2353 } else if (ice_is_e810t(&pf->hw)) {
2354 info->n_ext_ts = N_EXT_TS_NO_SMA_E810T;
2355 info->n_per_out = N_PER_OUT_NO_SMA_E810T;
2357 info->n_per_out = N_PER_OUT_E810;
2358 info->n_ext_ts = N_EXT_TS_E810;
2363 * ice_ptp_setup_pins_e823 - Setup PTP pins in sysfs
2364 * @pf: pointer to the PF instance
2365 * @info: PTP clock capabilities
2368 ice_ptp_setup_pins_e823(struct ice_pf *pf, struct ptp_clock_info *info)
2371 info->n_per_out = 0;
2376 * ice_ptp_set_funcs_e82x - Set specialized functions for E82x support
2377 * @pf: Board private structure
2378 * @info: PTP info to fill
2380 * Assign functions to the PTP capabiltiies structure for E82x devices.
2381 * Functions which operate across all device families should be set directly
2382 * in ice_ptp_set_caps. Only add functions here which are distinct for E82x
2386 ice_ptp_set_funcs_e82x(struct ice_pf *pf, struct ptp_clock_info *info)
2388 #ifdef CONFIG_ICE_HWTS
2389 if (boot_cpu_has(X86_FEATURE_ART) &&
2390 boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ))
2391 info->getcrosststamp = ice_ptp_getcrosststamp_e82x;
2392 #endif /* CONFIG_ICE_HWTS */
2396 * ice_ptp_set_funcs_e810 - Set specialized functions for E810 support
2397 * @pf: Board private structure
2398 * @info: PTP info to fill
2400 * Assign functions to the PTP capabiltiies structure for E810 devices.
2401 * Functions which operate across all device families should be set directly
2402 * in ice_ptp_set_caps. Only add functions here which are distinct for e810
2406 ice_ptp_set_funcs_e810(struct ice_pf *pf, struct ptp_clock_info *info)
2408 info->enable = ice_ptp_gpio_enable_e810;
2409 ice_ptp_setup_pins_e810(pf, info);
2413 * ice_ptp_set_funcs_e823 - Set specialized functions for E823 support
2414 * @pf: Board private structure
2415 * @info: PTP info to fill
2417 * Assign functions to the PTP capabiltiies structure for E823 devices.
2418 * Functions which operate across all device families should be set directly
2419 * in ice_ptp_set_caps. Only add functions here which are distinct for e823
2423 ice_ptp_set_funcs_e823(struct ice_pf *pf, struct ptp_clock_info *info)
2425 ice_ptp_set_funcs_e82x(pf, info);
2427 info->enable = ice_ptp_gpio_enable_e823;
2428 ice_ptp_setup_pins_e823(pf, info);
2432 * ice_ptp_set_caps - Set PTP capabilities
2433 * @pf: Board private structure
2435 static void ice_ptp_set_caps(struct ice_pf *pf)
2437 struct ptp_clock_info *info = &pf->ptp.info;
2438 struct device *dev = ice_pf_to_dev(pf);
2440 snprintf(info->name, sizeof(info->name) - 1, "%s-%s-clk",
2441 dev_driver_string(dev), dev_name(dev));
2442 info->owner = THIS_MODULE;
2443 info->max_adj = 100000000;
2444 info->adjtime = ice_ptp_adjtime;
2445 info->adjfine = ice_ptp_adjfine;
2446 info->gettimex64 = ice_ptp_gettimex64;
2447 info->settime64 = ice_ptp_settime64;
2449 if (ice_is_e810(&pf->hw))
2450 ice_ptp_set_funcs_e810(pf, info);
2451 else if (ice_is_e823(&pf->hw))
2452 ice_ptp_set_funcs_e823(pf, info);
2454 ice_ptp_set_funcs_e82x(pf, info);
2458 * ice_ptp_create_clock - Create PTP clock device for userspace
2459 * @pf: Board private structure
2461 * This function creates a new PTP clock device. It only creates one if we
2462 * don't already have one. Will return error if it can't create one, but success
2463 * if we already have a device. Should be used by ice_ptp_init to create clock
2464 * initially, and prevent global resets from creating new clock devices.
2466 static long ice_ptp_create_clock(struct ice_pf *pf)
2468 struct ptp_clock_info *info;
2471 /* No need to create a clock device if we already have one */
2475 ice_ptp_set_caps(pf);
2477 info = &pf->ptp.info;
2478 dev = ice_pf_to_dev(pf);
2480 /* Attempt to register the clock before enabling the hardware. */
2481 pf->ptp.clock = ptp_clock_register(info, dev);
2482 if (IS_ERR(pf->ptp.clock)) {
2483 dev_err(ice_pf_to_dev(pf), "Failed to register PTP clock device");
2484 return PTR_ERR(pf->ptp.clock);
2491 * ice_ptp_request_ts - Request an available Tx timestamp index
2492 * @tx: the PTP Tx timestamp tracker to request from
2493 * @skb: the SKB to associate with this timestamp request
2495 s8 ice_ptp_request_ts(struct ice_ptp_tx *tx, struct sk_buff *skb)
2497 unsigned long flags;
2500 spin_lock_irqsave(&tx->lock, flags);
2502 /* Check that this tracker is accepting new timestamp requests */
2503 if (!ice_ptp_is_tx_tracker_up(tx)) {
2504 spin_unlock_irqrestore(&tx->lock, flags);
2508 /* Find and set the first available index */
2509 idx = find_next_zero_bit(tx->in_use, tx->len,
2510 tx->last_ll_ts_idx_read + 1);
2512 idx = find_first_zero_bit(tx->in_use, tx->len);
2514 if (idx < tx->len) {
2515 /* We got a valid index that no other thread could have set. Store
2516 * a reference to the skb and the start time to allow discarding old
2519 set_bit(idx, tx->in_use);
2520 clear_bit(idx, tx->stale);
2521 tx->tstamps[idx].start = jiffies;
2522 tx->tstamps[idx].skb = skb_get(skb);
2523 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2524 ice_trace(tx_tstamp_request, skb, idx);
2527 spin_unlock_irqrestore(&tx->lock, flags);
2529 /* return the appropriate PHY timestamp register index, -1 if no
2530 * indexes were available.
2535 return idx + tx->offset;
2539 * ice_ptp_process_ts - Process the PTP Tx timestamps
2540 * @pf: Board private structure
2542 * Returns: ICE_TX_TSTAMP_WORK_PENDING if there are any outstanding Tx
2543 * timestamps that need processing, and ICE_TX_TSTAMP_WORK_DONE otherwise.
2545 enum ice_tx_tstamp_work ice_ptp_process_ts(struct ice_pf *pf)
2547 switch (pf->ptp.tx_interrupt_mode) {
2548 case ICE_PTP_TX_INTERRUPT_NONE:
2549 /* This device has the clock owner handle timestamps for it */
2550 return ICE_TX_TSTAMP_WORK_DONE;
2551 case ICE_PTP_TX_INTERRUPT_SELF:
2552 /* This device handles its own timestamps */
2553 return ice_ptp_tx_tstamp(&pf->ptp.port.tx);
2554 case ICE_PTP_TX_INTERRUPT_ALL:
2555 /* This device handles timestamps for all ports */
2556 return ice_ptp_tx_tstamp_owner(pf);
2558 WARN_ONCE(1, "Unexpected Tx timestamp interrupt mode %u\n",
2559 pf->ptp.tx_interrupt_mode);
2560 return ICE_TX_TSTAMP_WORK_DONE;
2565 * ice_ptp_maybe_trigger_tx_interrupt - Trigger Tx timstamp interrupt
2566 * @pf: Board private structure
2568 * The device PHY issues Tx timestamp interrupts to the driver for processing
2569 * timestamp data from the PHY. It will not interrupt again until all
2570 * current timestamp data is read. In rare circumstances, it is possible that
2571 * the driver fails to read all outstanding data.
2573 * To avoid getting permanently stuck, periodically check if the PHY has
2574 * outstanding timestamp data. If so, trigger an interrupt from software to
2575 * process this data.
2577 static void ice_ptp_maybe_trigger_tx_interrupt(struct ice_pf *pf)
2579 struct device *dev = ice_pf_to_dev(pf);
2580 struct ice_hw *hw = &pf->hw;
2581 bool trigger_oicr = false;
2584 if (ice_is_e810(hw))
2587 if (!ice_pf_src_tmr_owned(pf))
2590 for (i = 0; i < ICE_MAX_QUAD; i++) {
2594 err = ice_get_phy_tx_tstamp_ready(&pf->hw, i, &tstamp_ready);
2595 if (!err && tstamp_ready) {
2596 trigger_oicr = true;
2602 /* Trigger a software interrupt, to ensure this data
2605 dev_dbg(dev, "PTP periodic task detected waiting timestamps. Triggering Tx timestamp interrupt now.\n");
2607 wr32(hw, PFINT_OICR, PFINT_OICR_TSYN_TX_M);
2612 static void ice_ptp_periodic_work(struct kthread_work *work)
2614 struct ice_ptp *ptp = container_of(work, struct ice_ptp, work.work);
2615 struct ice_pf *pf = container_of(ptp, struct ice_pf, ptp);
2618 if (pf->ptp.state != ICE_PTP_READY)
2621 err = ice_ptp_update_cached_phctime(pf);
2623 ice_ptp_maybe_trigger_tx_interrupt(pf);
2625 /* Run twice a second or reschedule if phc update failed */
2626 kthread_queue_delayed_work(ptp->kworker, &ptp->work,
2627 msecs_to_jiffies(err ? 10 : 500));
2631 * ice_ptp_prepare_for_reset - Prepare PTP for reset
2632 * @pf: Board private structure
2633 * @reset_type: the reset type being performed
2635 void ice_ptp_prepare_for_reset(struct ice_pf *pf, enum ice_reset_req reset_type)
2637 struct ice_ptp *ptp = &pf->ptp;
2640 if (ptp->state != ICE_PTP_READY)
2643 ptp->state = ICE_PTP_RESETTING;
2645 /* Disable timestamping for both Tx and Rx */
2646 ice_ptp_disable_timestamp_mode(pf);
2648 kthread_cancel_delayed_work_sync(&ptp->work);
2650 if (reset_type == ICE_RESET_PFR)
2653 ice_ptp_release_tx_tracker(pf, &pf->ptp.port.tx);
2655 /* Disable periodic outputs */
2656 ice_ptp_disable_all_clkout(pf);
2658 src_tmr = ice_get_ptp_src_clock_index(&pf->hw);
2660 /* Disable source clock */
2661 wr32(&pf->hw, GLTSYN_ENA(src_tmr), (u32)~GLTSYN_ENA_TSYN_ENA_M);
2663 /* Acquire PHC and system timer to restore after reset */
2664 ptp->reset_time = ktime_get_real_ns();
2668 * ice_ptp_rebuild_owner - Initialize PTP clock owner after reset
2669 * @pf: Board private structure
2671 * Companion function for ice_ptp_rebuild() which handles tasks that only the
2672 * PTP clock owner instance should perform.
2674 static int ice_ptp_rebuild_owner(struct ice_pf *pf)
2676 struct ice_ptp *ptp = &pf->ptp;
2677 struct ice_hw *hw = &pf->hw;
2678 struct timespec64 ts;
2682 err = ice_ptp_init_phc(hw);
2686 /* Acquire the global hardware lock */
2687 if (!ice_ptp_lock(hw)) {
2692 /* Write the increment time value to PHY and LAN */
2693 err = ice_ptp_write_incval(hw, ice_base_incval(pf));
2699 /* Write the initial Time value to PHY and LAN using the cached PHC
2700 * time before the reset and time difference between stopping and
2701 * starting the clock.
2703 if (ptp->cached_phc_time) {
2704 time_diff = ktime_get_real_ns() - ptp->reset_time;
2705 ts = ns_to_timespec64(ptp->cached_phc_time + time_diff);
2707 ts = ktime_to_timespec64(ktime_get_real());
2709 err = ice_ptp_write_init(pf, &ts);
2715 /* Release the global hardware lock */
2718 if (!ice_is_e810(hw)) {
2719 /* Enable quad interrupts */
2720 err = ice_ptp_cfg_phy_interrupt(pf, true, 1);
2724 ice_ptp_restart_all_phy(pf);
2731 * ice_ptp_rebuild - Initialize PTP hardware clock support after reset
2732 * @pf: Board private structure
2733 * @reset_type: the reset type being performed
2735 void ice_ptp_rebuild(struct ice_pf *pf, enum ice_reset_req reset_type)
2737 struct ice_ptp *ptp = &pf->ptp;
2740 if (ptp->state == ICE_PTP_READY) {
2741 ice_ptp_prepare_for_reset(pf, reset_type);
2742 } else if (ptp->state != ICE_PTP_RESETTING) {
2744 dev_err(ice_pf_to_dev(pf), "PTP was not initialized\n");
2748 if (ice_pf_src_tmr_owned(pf) && reset_type != ICE_RESET_PFR) {
2749 err = ice_ptp_rebuild_owner(pf);
2754 /* Init Tx structures */
2755 if (ice_is_e810(&pf->hw)) {
2756 err = ice_ptp_init_tx_e810(pf, &ptp->port.tx);
2758 kthread_init_delayed_work(&ptp->port.ov_work,
2759 ice_ptp_wait_for_offsets);
2760 err = ice_ptp_init_tx_e82x(pf, &ptp->port.tx,
2761 ptp->port.port_num);
2766 ptp->state = ICE_PTP_READY;
2768 /* Start periodic work going */
2769 kthread_queue_delayed_work(ptp->kworker, &ptp->work, 0);
2771 dev_info(ice_pf_to_dev(pf), "PTP reset successful\n");
2775 ptp->state = ICE_PTP_ERROR;
2776 dev_err(ice_pf_to_dev(pf), "PTP reset failed %d\n", err);
2780 * ice_ptp_aux_dev_to_aux_pf - Get auxiliary PF handle for the auxiliary device
2781 * @aux_dev: auxiliary device to get the auxiliary PF for
2783 static struct ice_pf *
2784 ice_ptp_aux_dev_to_aux_pf(struct auxiliary_device *aux_dev)
2786 struct ice_ptp_port *aux_port;
2787 struct ice_ptp *aux_ptp;
2789 aux_port = container_of(aux_dev, struct ice_ptp_port, aux_dev);
2790 aux_ptp = container_of(aux_port, struct ice_ptp, port);
2792 return container_of(aux_ptp, struct ice_pf, ptp);
2796 * ice_ptp_aux_dev_to_owner_pf - Get PF handle for the auxiliary device
2797 * @aux_dev: auxiliary device to get the PF for
2799 static struct ice_pf *
2800 ice_ptp_aux_dev_to_owner_pf(struct auxiliary_device *aux_dev)
2802 struct ice_ptp_port_owner *ports_owner;
2803 struct auxiliary_driver *aux_drv;
2804 struct ice_ptp *owner_ptp;
2806 if (!aux_dev->dev.driver)
2809 aux_drv = to_auxiliary_drv(aux_dev->dev.driver);
2810 ports_owner = container_of(aux_drv, struct ice_ptp_port_owner,
2812 owner_ptp = container_of(ports_owner, struct ice_ptp, ports_owner);
2813 return container_of(owner_ptp, struct ice_pf, ptp);
2817 * ice_ptp_auxbus_probe - Probe auxiliary devices
2818 * @aux_dev: PF's auxiliary device
2819 * @id: Auxiliary device ID
2821 static int ice_ptp_auxbus_probe(struct auxiliary_device *aux_dev,
2822 const struct auxiliary_device_id *id)
2824 struct ice_pf *owner_pf = ice_ptp_aux_dev_to_owner_pf(aux_dev);
2825 struct ice_pf *aux_pf = ice_ptp_aux_dev_to_aux_pf(aux_dev);
2827 if (WARN_ON(!owner_pf))
2830 INIT_LIST_HEAD(&aux_pf->ptp.port.list_member);
2831 mutex_lock(&owner_pf->ptp.ports_owner.lock);
2832 list_add(&aux_pf->ptp.port.list_member,
2833 &owner_pf->ptp.ports_owner.ports);
2834 mutex_unlock(&owner_pf->ptp.ports_owner.lock);
2840 * ice_ptp_auxbus_remove - Remove auxiliary devices from the bus
2841 * @aux_dev: PF's auxiliary device
2843 static void ice_ptp_auxbus_remove(struct auxiliary_device *aux_dev)
2845 struct ice_pf *owner_pf = ice_ptp_aux_dev_to_owner_pf(aux_dev);
2846 struct ice_pf *aux_pf = ice_ptp_aux_dev_to_aux_pf(aux_dev);
2848 mutex_lock(&owner_pf->ptp.ports_owner.lock);
2849 list_del(&aux_pf->ptp.port.list_member);
2850 mutex_unlock(&owner_pf->ptp.ports_owner.lock);
2854 * ice_ptp_auxbus_shutdown
2855 * @aux_dev: PF's auxiliary device
2857 static void ice_ptp_auxbus_shutdown(struct auxiliary_device *aux_dev)
2859 /* Doing nothing here, but handle to auxbus driver must be satisfied */
2863 * ice_ptp_auxbus_suspend
2864 * @aux_dev: PF's auxiliary device
2865 * @state: power management state indicator
2868 ice_ptp_auxbus_suspend(struct auxiliary_device *aux_dev, pm_message_t state)
2870 /* Doing nothing here, but handle to auxbus driver must be satisfied */
2875 * ice_ptp_auxbus_resume
2876 * @aux_dev: PF's auxiliary device
2878 static int ice_ptp_auxbus_resume(struct auxiliary_device *aux_dev)
2880 /* Doing nothing here, but handle to auxbus driver must be satisfied */
2885 * ice_ptp_auxbus_create_id_table - Create auxiliary device ID table
2886 * @pf: Board private structure
2887 * @name: auxiliary bus driver name
2889 static struct auxiliary_device_id *
2890 ice_ptp_auxbus_create_id_table(struct ice_pf *pf, const char *name)
2892 struct auxiliary_device_id *ids;
2894 /* Second id left empty to terminate the array */
2895 ids = devm_kcalloc(ice_pf_to_dev(pf), 2,
2896 sizeof(struct auxiliary_device_id), GFP_KERNEL);
2900 snprintf(ids[0].name, sizeof(ids[0].name), "ice.%s", name);
2906 * ice_ptp_register_auxbus_driver - Register PTP auxiliary bus driver
2907 * @pf: Board private structure
2909 static int ice_ptp_register_auxbus_driver(struct ice_pf *pf)
2911 struct auxiliary_driver *aux_driver;
2912 struct ice_ptp *ptp;
2918 dev = ice_pf_to_dev(pf);
2919 aux_driver = &ptp->ports_owner.aux_driver;
2920 INIT_LIST_HEAD(&ptp->ports_owner.ports);
2921 mutex_init(&ptp->ports_owner.lock);
2922 name = devm_kasprintf(dev, GFP_KERNEL, "ptp_aux_dev_%u_%u_clk%u",
2923 pf->pdev->bus->number, PCI_SLOT(pf->pdev->devfn),
2924 ice_get_ptp_src_clock_index(&pf->hw));
2928 aux_driver->name = name;
2929 aux_driver->shutdown = ice_ptp_auxbus_shutdown;
2930 aux_driver->suspend = ice_ptp_auxbus_suspend;
2931 aux_driver->remove = ice_ptp_auxbus_remove;
2932 aux_driver->resume = ice_ptp_auxbus_resume;
2933 aux_driver->probe = ice_ptp_auxbus_probe;
2934 aux_driver->id_table = ice_ptp_auxbus_create_id_table(pf, name);
2935 if (!aux_driver->id_table)
2938 err = auxiliary_driver_register(aux_driver);
2940 devm_kfree(dev, aux_driver->id_table);
2941 dev_err(dev, "Failed registering aux_driver, name <%s>\n",
2949 * ice_ptp_unregister_auxbus_driver - Unregister PTP auxiliary bus driver
2950 * @pf: Board private structure
2952 static void ice_ptp_unregister_auxbus_driver(struct ice_pf *pf)
2954 struct auxiliary_driver *aux_driver = &pf->ptp.ports_owner.aux_driver;
2956 auxiliary_driver_unregister(aux_driver);
2957 devm_kfree(ice_pf_to_dev(pf), aux_driver->id_table);
2959 mutex_destroy(&pf->ptp.ports_owner.lock);
2963 * ice_ptp_clock_index - Get the PTP clock index for this device
2964 * @pf: Board private structure
2966 * Returns: the PTP clock index associated with this PF, or -1 if no PTP clock
2969 int ice_ptp_clock_index(struct ice_pf *pf)
2971 struct auxiliary_device *aux_dev;
2972 struct ice_pf *owner_pf;
2973 struct ptp_clock *clock;
2975 aux_dev = &pf->ptp.port.aux_dev;
2976 owner_pf = ice_ptp_aux_dev_to_owner_pf(aux_dev);
2979 clock = owner_pf->ptp.clock;
2981 return clock ? ptp_clock_index(clock) : -1;
2985 * ice_ptp_init_owner - Initialize PTP_1588_CLOCK device
2986 * @pf: Board private structure
2988 * Setup and initialize a PTP clock device that represents the device hardware
2989 * clock. Save the clock index for other functions connected to the same
2990 * hardware resource.
2992 static int ice_ptp_init_owner(struct ice_pf *pf)
2994 struct ice_hw *hw = &pf->hw;
2995 struct timespec64 ts;
2998 err = ice_ptp_init_phc(hw);
3000 dev_err(ice_pf_to_dev(pf), "Failed to initialize PHC, err %d\n",
3005 /* Acquire the global hardware lock */
3006 if (!ice_ptp_lock(hw)) {
3011 /* Write the increment time value to PHY and LAN */
3012 err = ice_ptp_write_incval(hw, ice_base_incval(pf));
3018 ts = ktime_to_timespec64(ktime_get_real());
3019 /* Write the initial Time value to PHY and LAN */
3020 err = ice_ptp_write_init(pf, &ts);
3026 /* Release the global hardware lock */
3029 if (!ice_is_e810(hw)) {
3030 /* Enable quad interrupts */
3031 err = ice_ptp_cfg_phy_interrupt(pf, true, 1);
3036 /* Ensure we have a clock device */
3037 err = ice_ptp_create_clock(pf);
3041 err = ice_ptp_register_auxbus_driver(pf);
3043 dev_err(ice_pf_to_dev(pf), "Failed to register PTP auxbus driver");
3049 ptp_clock_unregister(pf->ptp.clock);
3051 pf->ptp.clock = NULL;
3057 * ice_ptp_init_work - Initialize PTP work threads
3058 * @pf: Board private structure
3059 * @ptp: PF PTP structure
3061 static int ice_ptp_init_work(struct ice_pf *pf, struct ice_ptp *ptp)
3063 struct kthread_worker *kworker;
3065 /* Initialize work functions */
3066 kthread_init_delayed_work(&ptp->work, ice_ptp_periodic_work);
3068 /* Allocate a kworker for handling work required for the ports
3069 * connected to the PTP hardware clock.
3071 kworker = kthread_create_worker(0, "ice-ptp-%s",
3072 dev_name(ice_pf_to_dev(pf)));
3073 if (IS_ERR(kworker))
3074 return PTR_ERR(kworker);
3076 ptp->kworker = kworker;
3078 /* Start periodic work going */
3079 kthread_queue_delayed_work(ptp->kworker, &ptp->work, 0);
3085 * ice_ptp_init_port - Initialize PTP port structure
3086 * @pf: Board private structure
3087 * @ptp_port: PTP port structure
3089 static int ice_ptp_init_port(struct ice_pf *pf, struct ice_ptp_port *ptp_port)
3091 struct ice_hw *hw = &pf->hw;
3093 mutex_init(&ptp_port->ps_lock);
3095 switch (hw->phy_model) {
3097 return ice_ptp_init_tx_e810(pf, &ptp_port->tx);
3099 kthread_init_delayed_work(&ptp_port->ov_work,
3100 ice_ptp_wait_for_offsets);
3102 return ice_ptp_init_tx_e82x(pf, &ptp_port->tx,
3103 ptp_port->port_num);
3110 * ice_ptp_release_auxbus_device
3111 * @dev: device that utilizes the auxbus
3113 static void ice_ptp_release_auxbus_device(struct device *dev)
3115 /* Doing nothing here, but handle to auxbux device must be satisfied */
3119 * ice_ptp_create_auxbus_device - Create PTP auxiliary bus device
3120 * @pf: Board private structure
3122 static int ice_ptp_create_auxbus_device(struct ice_pf *pf)
3124 struct auxiliary_device *aux_dev;
3125 struct ice_ptp *ptp;
3132 id = ptp->port.port_num;
3133 dev = ice_pf_to_dev(pf);
3135 aux_dev = &ptp->port.aux_dev;
3137 name = devm_kasprintf(dev, GFP_KERNEL, "ptp_aux_dev_%u_%u_clk%u",
3138 pf->pdev->bus->number, PCI_SLOT(pf->pdev->devfn),
3139 ice_get_ptp_src_clock_index(&pf->hw));
3143 aux_dev->name = name;
3145 aux_dev->dev.release = ice_ptp_release_auxbus_device;
3146 aux_dev->dev.parent = dev;
3148 err = auxiliary_device_init(aux_dev);
3152 err = auxiliary_device_add(aux_dev);
3154 auxiliary_device_uninit(aux_dev);
3160 dev_err(dev, "Failed to create PTP auxiliary bus device <%s>\n", name);
3161 devm_kfree(dev, name);
3166 * ice_ptp_remove_auxbus_device - Remove PTP auxiliary bus device
3167 * @pf: Board private structure
3169 static void ice_ptp_remove_auxbus_device(struct ice_pf *pf)
3171 struct auxiliary_device *aux_dev = &pf->ptp.port.aux_dev;
3173 auxiliary_device_delete(aux_dev);
3174 auxiliary_device_uninit(aux_dev);
3176 memset(aux_dev, 0, sizeof(*aux_dev));
3180 * ice_ptp_init_tx_interrupt_mode - Initialize device Tx interrupt mode
3181 * @pf: Board private structure
3183 * Initialize the Tx timestamp interrupt mode for this device. For most device
3184 * types, each PF processes the interrupt and manages its own timestamps. For
3185 * E822-based devices, only the clock owner processes the timestamps. Other
3186 * PFs disable the interrupt and do not process their own timestamps.
3188 static void ice_ptp_init_tx_interrupt_mode(struct ice_pf *pf)
3190 switch (pf->hw.phy_model) {
3192 /* E822 based PHY has the clock owner process the interrupt
3195 if (ice_pf_src_tmr_owned(pf))
3196 pf->ptp.tx_interrupt_mode = ICE_PTP_TX_INTERRUPT_ALL;
3198 pf->ptp.tx_interrupt_mode = ICE_PTP_TX_INTERRUPT_NONE;
3201 /* other PHY types handle their own Tx interrupt */
3202 pf->ptp.tx_interrupt_mode = ICE_PTP_TX_INTERRUPT_SELF;
3207 * ice_ptp_init - Initialize PTP hardware clock support
3208 * @pf: Board private structure
3210 * Set up the device for interacting with the PTP hardware clock for all
3211 * functions, both the function that owns the clock hardware, and the
3212 * functions connected to the clock hardware.
3214 * The clock owner will allocate and register a ptp_clock with the
3215 * PTP_1588_CLOCK infrastructure. All functions allocate a kthread and work
3216 * items used for asynchronous work such as Tx timestamps and periodic work.
3218 void ice_ptp_init(struct ice_pf *pf)
3220 struct ice_ptp *ptp = &pf->ptp;
3221 struct ice_hw *hw = &pf->hw;
3224 ptp->state = ICE_PTP_INITIALIZING;
3226 ice_ptp_init_phy_model(hw);
3228 ice_ptp_init_tx_interrupt_mode(pf);
3230 /* If this function owns the clock hardware, it must allocate and
3231 * configure the PTP clock device to represent it.
3233 if (ice_pf_src_tmr_owned(pf)) {
3234 err = ice_ptp_init_owner(pf);
3239 ptp->port.port_num = hw->pf_id;
3240 err = ice_ptp_init_port(pf, &ptp->port);
3244 /* Start the PHY timestamping block */
3245 ice_ptp_reset_phy_timestamping(pf);
3247 /* Configure initial Tx interrupt settings */
3248 ice_ptp_cfg_tx_interrupt(pf);
3250 err = ice_ptp_create_auxbus_device(pf);
3254 ptp->state = ICE_PTP_READY;
3256 err = ice_ptp_init_work(pf, ptp);
3260 dev_info(ice_pf_to_dev(pf), "PTP init successful\n");
3264 /* If we registered a PTP clock, release it */
3265 if (pf->ptp.clock) {
3266 ptp_clock_unregister(ptp->clock);
3267 pf->ptp.clock = NULL;
3269 ptp->state = ICE_PTP_ERROR;
3270 dev_err(ice_pf_to_dev(pf), "PTP failed %d\n", err);
3274 * ice_ptp_release - Disable the driver/HW support and unregister the clock
3275 * @pf: Board private structure
3277 * This function handles the cleanup work required from the initialization by
3278 * clearing out the important information and unregistering the clock
3280 void ice_ptp_release(struct ice_pf *pf)
3282 if (pf->ptp.state != ICE_PTP_READY)
3285 pf->ptp.state = ICE_PTP_UNINIT;
3287 /* Disable timestamping for both Tx and Rx */
3288 ice_ptp_disable_timestamp_mode(pf);
3290 ice_ptp_remove_auxbus_device(pf);
3292 ice_ptp_release_tx_tracker(pf, &pf->ptp.port.tx);
3294 kthread_cancel_delayed_work_sync(&pf->ptp.work);
3296 ice_ptp_port_phy_stop(&pf->ptp.port);
3297 mutex_destroy(&pf->ptp.port.ps_lock);
3298 if (pf->ptp.kworker) {
3299 kthread_destroy_worker(pf->ptp.kworker);
3300 pf->ptp.kworker = NULL;
3303 if (ice_pf_src_tmr_owned(pf))
3304 ice_ptp_unregister_auxbus_driver(pf);
3309 /* Disable periodic outputs */
3310 ice_ptp_disable_all_clkout(pf);
3312 ptp_clock_unregister(pf->ptp.clock);
3313 pf->ptp.clock = NULL;
3315 dev_info(ice_pf_to_dev(pf), "Removed PTP clock\n");