1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
7 #include <linux/types.h>
8 #include <linux/errno.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/netdevice.h>
12 #include <linux/compiler.h>
13 #include <linux/etherdevice.h>
14 #include <linux/skbuff.h>
15 #include <linux/cpumask.h>
16 #include <linux/if_vlan.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/pci.h>
19 #include <linux/workqueue.h>
20 #include <linux/aer.h>
21 #include <linux/interrupt.h>
22 #include <linux/timer.h>
23 #include <linux/delay.h>
24 #include <linux/bitmap.h>
25 #include <linux/log2.h>
26 #include <linux/if_bridge.h>
27 #include "ice_devids.h"
30 #include "ice_switch.h"
31 #include "ice_common.h"
32 #include "ice_sched.h"
35 #define ICE_DFLT_NUM_DESC 128
36 #define ICE_REQ_DESC_MULTIPLE 32
37 #define ICE_INT_NAME_STR_LEN (IFNAMSIZ + 16)
39 #define ICE_MIN_MSIX 2
40 #define ICE_NO_VSI 0xffff
41 #define ICE_MAX_VSI_ALLOC 130
42 #define ICE_MAX_TXQS 2048
43 #define ICE_MAX_RXQS 2048
44 #define ICE_VSI_MAP_CONTIG 0
45 #define ICE_VSI_MAP_SCATTER 1
46 #define ICE_MAX_SCATTER_TXQS 16
47 #define ICE_MAX_SCATTER_RXQS 16
48 #define ICE_Q_WAIT_RETRY_LIMIT 10
49 #define ICE_Q_WAIT_MAX_RETRY (5 * ICE_Q_WAIT_RETRY_LIMIT)
50 #define ICE_RES_VALID_BIT 0x8000
51 #define ICE_RES_MISC_VEC_ID (ICE_RES_VALID_BIT - 1)
52 #define ICE_INVAL_Q_INDEX 0xffff
54 #define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
56 #define ICE_MAX_MTU (ICE_AQ_SET_MAC_FRAME_SIZE_MAX - \
57 ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
59 #define ICE_UP_TABLE_TRANSLATE(val, i) \
60 (((val) << ICE_AQ_VSI_UP_TABLE_UP##i##_S) & \
61 ICE_AQ_VSI_UP_TABLE_UP##i##_M)
63 #define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->desc))[i]))
65 #define ice_for_each_txq(vsi, i) \
66 for ((i) = 0; (i) < (vsi)->num_txq; (i)++)
68 #define ice_for_each_rxq(vsi, i) \
69 for ((i) = 0; (i) < (vsi)->num_rxq; (i)++)
77 u8 numtc; /* Total number of enabled TCs */
78 u8 ena_tc; /* TX map */
79 struct ice_tc_info tc_info[ICE_MAX_TRAFFIC_CLASS];
82 struct ice_res_tracker {
90 u16 sw_id; /* switch ID for this switch */
91 u16 bridge_mode; /* VEB/VEPA/Port Virtualizer */
96 __ICE_PFR_REQ, /* set by driver and peers */
97 __ICE_ADMINQ_EVENT_PENDING,
99 __ICE_STATE_NBITS /* must be last */
102 /* struct that defines a VSI, associated with a dev */
104 struct net_device *netdev;
105 struct ice_sw *vsw; /* switch this VSI is on */
106 struct ice_pf *back; /* back pointer to PF */
107 struct ice_port_info *port_info; /* back pointer to port_info */
108 struct ice_ring **rx_rings; /* rx ring array */
109 struct ice_ring **tx_rings; /* tx ring array */
110 struct ice_q_vector **q_vectors; /* q_vector array */
112 irqreturn_t (*irq_handler)(int irq, void *data);
114 DECLARE_BITMAP(state, __ICE_STATE_NBITS);
117 enum ice_vsi_type type;
118 u16 vsi_num; /* HW (absolute) index of this VSI */
119 u16 idx; /* software index in pf->vsi[] */
121 /* Interrupt thresholds */
127 struct ice_aqc_vsi_props info; /* VSI properties */
130 bool current_isup; /* Sync 'link up' logging */
132 /* queue information */
133 u8 tx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */
134 u8 rx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */
135 u16 txq_map[ICE_MAX_TXQS]; /* index in pf->avail_txqs */
136 u16 rxq_map[ICE_MAX_RXQS]; /* index in pf->avail_rxqs */
137 u16 alloc_txq; /* Allocated Tx queues */
138 u16 num_txq; /* Used Tx queues */
139 u16 alloc_rxq; /* Allocated Rx queues */
140 u16 num_rxq; /* Used Rx queues */
142 struct ice_tc_cfg tc_cfg;
143 } ____cacheline_internodealigned_in_smp;
145 /* struct that defines an interrupt vector */
146 struct ice_q_vector {
148 cpumask_t affinity_mask;
149 struct napi_struct napi;
150 struct ice_ring_container rx;
151 struct ice_ring_container tx;
152 struct irq_affinity_notify affinity_notify;
153 u16 v_idx; /* index in the vsi->q_vector array. */
154 u8 num_ring_tx; /* total number of tx rings in vector */
155 u8 num_ring_rx; /* total number of rx rings in vector */
156 char name[ICE_INT_NAME_STR_LEN];
157 } ____cacheline_internodealigned_in_smp;
163 ICE_PF_FLAGS_NBITS /* must be last */
167 struct pci_dev *pdev;
168 struct msix_entry *msix_entries;
169 struct ice_res_tracker *irq_tracker;
170 struct ice_vsi **vsi; /* VSIs created by the driver */
171 struct ice_sw *first_sw; /* first switch created by firmware */
172 DECLARE_BITMAP(state, __ICE_STATE_NBITS);
173 DECLARE_BITMAP(avail_txqs, ICE_MAX_TXQS);
174 DECLARE_BITMAP(avail_rxqs, ICE_MAX_RXQS);
175 DECLARE_BITMAP(flags, ICE_PF_FLAGS_NBITS);
176 unsigned long serv_tmr_period;
177 unsigned long serv_tmr_prev;
178 struct timer_list serv_tmr;
179 struct work_struct serv_task;
180 struct mutex avail_q_mutex; /* protects access to avail_[rx|tx]qs */
181 struct mutex sw_mutex; /* lock for protecting VSI alloc flow */
183 u32 oicr_idx; /* Other interrupt cause vector index */
184 u32 num_lan_msix; /* Total MSIX vectors for base driver */
185 u32 num_avail_msix; /* remaining MSIX vectors left unclaimed */
186 u16 num_lan_tx; /* num lan tx queues setup */
187 u16 num_lan_rx; /* num lan rx queues setup */
188 u16 q_left_tx; /* remaining num tx queues left unclaimed */
189 u16 q_left_rx; /* remaining num rx queues left unclaimed */
190 u16 next_vsi; /* Next free slot in pf->vsi[] - 0-based! */
194 char int_name[ICE_INT_NAME_STR_LEN];
197 struct ice_netdev_priv {
202 * ice_irq_dynamic_ena - Enable default interrupt generation settings
203 * @hw: pointer to hw struct
204 * @vsi: pointer to vsi struct, can be NULL
205 * @q_vector: pointer to q_vector, can be NULL
207 static inline void ice_irq_dynamic_ena(struct ice_hw *hw, struct ice_vsi *vsi,
208 struct ice_q_vector *q_vector)
210 u32 vector = (vsi && q_vector) ? vsi->base_vector + q_vector->v_idx :
211 ((struct ice_pf *)hw->back)->oicr_idx;
212 int itr = ICE_ITR_NONE;
215 /* clear the PBA here, as this function is meant to clean out all
216 * previous interrupts and enable the interrupt
218 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
219 (itr << GLINT_DYN_CTL_ITR_INDX_S);
221 if (test_bit(__ICE_DOWN, vsi->state))
223 wr32(hw, GLINT_DYN_CTL(vector), val);