1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * The full GNU General Public License is included in this distribution in
16 * the file called "COPYING".
18 * Contact Information:
19 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
20 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 ******************************************************************************/
27 #include "i40e_status.h"
28 #include "i40e_osdep.h"
29 #include "i40e_register.h"
30 #include "i40e_adminq.h"
32 #include "i40e_lan_hmc.h"
35 #define I40E_DEV_ID_SFP_XL710 0x1572
36 #define I40E_DEV_ID_SFP_X710 0x1573
37 #define I40E_DEV_ID_QEMU 0x1574
38 #define I40E_DEV_ID_KX_A 0x157F
39 #define I40E_DEV_ID_KX_B 0x1580
40 #define I40E_DEV_ID_KX_C 0x1581
41 #define I40E_DEV_ID_KX_D 0x1582
42 #define I40E_DEV_ID_QSFP_A 0x1583
43 #define I40E_DEV_ID_QSFP_B 0x1584
44 #define I40E_DEV_ID_QSFP_C 0x1585
45 #define I40E_DEV_ID_VF 0x154C
46 #define I40E_DEV_ID_VF_HV 0x1571
48 #define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
49 (d) == I40E_DEV_ID_QSFP_B || \
50 (d) == I40E_DEV_ID_QSFP_C)
52 #define I40E_MAX_VSI_QP 16
53 #define I40E_MAX_VF_VSI 3
54 #define I40E_MAX_CHAINED_RX_BUFFERS 5
55 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
57 /* Max default timeout in ms, */
58 #define I40E_MAX_NVM_TIMEOUT 18000
60 /* Switch from mc to the 2usec global time (this is the GTIME resolution) */
61 #define I40E_MS_TO_GTIME(time) (((time) * 1000) / 2)
63 /* forward declaration */
65 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
67 /* Data type manipulation macros. */
69 #define I40E_DESC_UNUSED(R) \
70 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
71 (R)->next_to_clean - (R)->next_to_use - 1)
73 /* bitfields for Tx queue mapping in QTX_CTL */
74 #define I40E_QTX_CTL_VF_QUEUE 0x0
75 #define I40E_QTX_CTL_VM_QUEUE 0x1
76 #define I40E_QTX_CTL_PF_QUEUE 0x2
78 /* debug masks - set these bits in hw->debug_mask to control output */
79 enum i40e_debug_mask {
80 I40E_DEBUG_INIT = 0x00000001,
81 I40E_DEBUG_RELEASE = 0x00000002,
83 I40E_DEBUG_LINK = 0x00000010,
84 I40E_DEBUG_PHY = 0x00000020,
85 I40E_DEBUG_HMC = 0x00000040,
86 I40E_DEBUG_NVM = 0x00000080,
87 I40E_DEBUG_LAN = 0x00000100,
88 I40E_DEBUG_FLOW = 0x00000200,
89 I40E_DEBUG_DCB = 0x00000400,
90 I40E_DEBUG_DIAG = 0x00000800,
92 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
93 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
94 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
95 I40E_DEBUG_AQ_COMMAND = 0x06000000,
96 I40E_DEBUG_AQ = 0x0F000000,
98 I40E_DEBUG_USER = 0xF0000000,
100 I40E_DEBUG_ALL = 0xFFFFFFFF
104 #define I40E_PCI_LINK_WIDTH_1 0x10
105 #define I40E_PCI_LINK_WIDTH_2 0x20
106 #define I40E_PCI_LINK_WIDTH_4 0x40
107 #define I40E_PCI_LINK_WIDTH_8 0x80
108 #define I40E_PCI_LINK_SPEED_2500 0x1
109 #define I40E_PCI_LINK_SPEED_5000 0x2
110 #define I40E_PCI_LINK_SPEED_8000 0x3
112 /* These are structs for managing the hardware information and the operations.
113 * The structures of function pointers are filled out at init time when we
114 * know for sure exactly which hardware we're working with. This gives us the
115 * flexibility of using the same main driver code but adapting to slightly
116 * different hardware needs as new parts are developed. For this architecture,
117 * the Firmware and AdminQ are intended to insulate the driver from most of the
118 * future changes, but these structures will also do part of the job.
121 I40E_MAC_UNKNOWN = 0,
128 enum i40e_media_type {
129 I40E_MEDIA_TYPE_UNKNOWN = 0,
130 I40E_MEDIA_TYPE_FIBER,
131 I40E_MEDIA_TYPE_BASET,
132 I40E_MEDIA_TYPE_BACKPLANE,
135 I40E_MEDIA_TYPE_VIRTUAL
156 I40E_VSI_TYPE_UNKNOWN
159 enum i40e_queue_type {
160 I40E_QUEUE_TYPE_RX = 0,
162 I40E_QUEUE_TYPE_PE_CEQ,
163 I40E_QUEUE_TYPE_UNKNOWN
166 struct i40e_link_status {
167 enum i40e_aq_phy_type phy_type;
168 enum i40e_aq_link_speed link_speed;
173 /* is Link Status Event notification to SW enabled */
177 struct i40e_phy_info {
178 struct i40e_link_status link_info;
179 struct i40e_link_status link_info_old;
180 u32 autoneg_advertised;
184 enum i40e_media_type media_type;
187 #define I40E_HW_CAP_MAX_GPIO 30
188 /* Capabilities of a PF or a VF or the whole device */
189 struct i40e_hw_capabilities {
191 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
192 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
193 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
201 bool evb_802_1_qbg; /* Edge Virtual Bridging */
202 bool evb_802_1_qbh; /* Bridge Port Extension */
210 u32 fd_filters_guaranteed;
211 u32 fd_filters_best_effort;
214 u32 rss_table_entry_width;
215 bool led[I40E_HW_CAP_MAX_GPIO];
216 bool sdp[I40E_HW_CAP_MAX_GPIO];
218 u32 num_flow_director_filters;
225 u32 num_msix_vectors;
226 u32 num_msix_vectors_vf;
236 struct i40e_mac_info {
237 enum i40e_mac_type type;
239 u8 perm_addr[ETH_ALEN];
240 u8 san_addr[ETH_ALEN];
244 enum i40e_aq_resources_ids {
245 I40E_NVM_RESOURCE_ID = 1
248 enum i40e_aq_resource_access_type {
249 I40E_RESOURCE_READ = 1,
253 struct i40e_nvm_info {
254 u64 hw_semaphore_timeout; /* 2usec global time (GTIME resolution) */
255 u64 hw_semaphore_wait; /* - || - */
256 u32 timeout; /* [ms] */
257 u16 sr_size; /* Shadow RAM size in words */
258 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
259 u16 version; /* NVM package version */
260 u32 eetrack; /* NVM data version */
265 i40e_bus_type_unknown = 0,
268 i40e_bus_type_pci_express,
269 i40e_bus_type_reserved
273 enum i40e_bus_speed {
274 i40e_bus_speed_unknown = 0,
275 i40e_bus_speed_33 = 33,
276 i40e_bus_speed_66 = 66,
277 i40e_bus_speed_100 = 100,
278 i40e_bus_speed_120 = 120,
279 i40e_bus_speed_133 = 133,
280 i40e_bus_speed_2500 = 2500,
281 i40e_bus_speed_5000 = 5000,
282 i40e_bus_speed_8000 = 8000,
283 i40e_bus_speed_reserved
287 enum i40e_bus_width {
288 i40e_bus_width_unknown = 0,
289 i40e_bus_width_pcie_x1 = 1,
290 i40e_bus_width_pcie_x2 = 2,
291 i40e_bus_width_pcie_x4 = 4,
292 i40e_bus_width_pcie_x8 = 8,
293 i40e_bus_width_32 = 32,
294 i40e_bus_width_64 = 64,
295 i40e_bus_width_reserved
299 struct i40e_bus_info {
300 enum i40e_bus_speed speed;
301 enum i40e_bus_width width;
302 enum i40e_bus_type type;
309 /* Flow control (FC) parameters */
310 struct i40e_fc_info {
311 enum i40e_fc_mode current_mode; /* FC mode in effect */
312 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
315 #define I40E_MAX_TRAFFIC_CLASS 8
316 #define I40E_MAX_USER_PRIORITY 8
317 #define I40E_DCBX_MAX_APPS 32
318 #define I40E_LLDPDU_SIZE 1500
320 /* IEEE 802.1Qaz ETS Configuration data */
321 struct i40e_ieee_ets_config {
325 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
326 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
327 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
330 /* IEEE 802.1Qaz ETS Recommendation data */
331 struct i40e_ieee_ets_recommend {
332 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
333 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
334 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
337 /* IEEE 802.1Qaz PFC Configuration data */
338 struct i40e_ieee_pfc_config {
345 /* IEEE 802.1Qaz Application Priority data */
346 struct i40e_ieee_app_priority_table {
352 struct i40e_dcbx_config {
354 struct i40e_ieee_ets_config etscfg;
355 struct i40e_ieee_ets_recommend etsrec;
356 struct i40e_ieee_pfc_config pfc;
357 struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
360 /* Port hardware description */
365 /* function pointer structs */
366 struct i40e_phy_info phy;
367 struct i40e_mac_info mac;
368 struct i40e_bus_info bus;
369 struct i40e_nvm_info nvm;
370 struct i40e_fc_info fc;
375 u16 subsystem_device_id;
376 u16 subsystem_vendor_id;
379 bool adapter_stopped;
381 /* capabilities for entire device and PCI func */
382 struct i40e_hw_capabilities dev_caps;
383 struct i40e_hw_capabilities func_caps;
385 /* Flow Director shared filter space */
386 u16 fdir_shared_filter_count;
388 /* device profile info */
392 /* Closest numa node to the device */
395 /* Admin Queue info */
396 struct i40e_adminq_info aq;
399 struct i40e_hmc_info hmc; /* HMC info struct */
401 /* LLDP/DCBX Status */
405 struct i40e_dcbx_config local_dcbx_config;
406 struct i40e_dcbx_config remote_dcbx_config;
412 struct i40e_driver_version {
420 union i40e_16byte_rx_desc {
422 __le64 pkt_addr; /* Packet buffer address */
423 __le64 hdr_addr; /* Header buffer address */
429 __le16 mirroring_status;
435 __le32 rss; /* RSS Hash */
436 __le32 fd_id; /* Flow director filter id */
437 __le32 fcoe_param; /* FCoE DDP Context id */
441 /* ext status/error/pktype/length */
442 __le64 status_error_len;
444 } wb; /* writeback */
447 union i40e_32byte_rx_desc {
449 __le64 pkt_addr; /* Packet buffer address */
450 __le64 hdr_addr; /* Header buffer address */
451 /* bit 0 of hdr_buffer_addr is DD bit */
459 __le16 mirroring_status;
465 __le32 rss; /* RSS Hash */
466 __le32 fcoe_param; /* FCoE DDP Context id */
467 /* Flow director filter id in case of
468 * Programming status desc WB
474 /* status/error/pktype/length */
475 __le64 status_error_len;
478 __le16 ext_status; /* extended status */
485 __le32 flex_bytes_lo;
489 __le32 flex_bytes_hi;
493 } wb; /* writeback */
496 #define I40E_RXD_QW1_STATUS_SHIFT 0
497 #define I40E_RXD_QW1_STATUS_MASK (0x7FFFUL << I40E_RXD_QW1_STATUS_SHIFT)
499 enum i40e_rx_desc_status_bits {
500 /* Note: These are predefined bit offsets */
501 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
502 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
503 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
504 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
505 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
506 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
507 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
508 I40E_RX_DESC_STATUS_PIF_SHIFT = 8,
509 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
510 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
511 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
512 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
513 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
514 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
515 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18
518 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
519 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
520 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
522 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
523 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \
524 I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
526 enum i40e_rx_desc_fltstat_values {
527 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
528 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
529 I40E_RX_DESC_FLTSTAT_RSV = 2,
530 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
533 #define I40E_RXD_QW1_ERROR_SHIFT 19
534 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
536 enum i40e_rx_desc_error_bits {
537 /* Note: These are predefined bit offsets */
538 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
539 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
540 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
541 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
542 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
543 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
544 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
545 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6
548 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
549 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
550 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
551 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
552 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
553 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
556 #define I40E_RXD_QW1_PTYPE_SHIFT 30
557 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
559 /* Packet type non-ip values */
560 enum i40e_rx_l2_ptype {
561 I40E_RX_PTYPE_L2_RESERVED = 0,
562 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
563 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
564 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
565 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
566 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
567 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
568 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
569 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
570 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
571 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
572 I40E_RX_PTYPE_L2_ARP = 11,
573 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
574 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
575 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
576 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
577 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
578 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
579 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
580 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
581 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
582 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
583 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
584 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
585 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
586 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
589 struct i40e_rx_ptype_decoded {
596 u32 tunnel_end_prot:2;
597 u32 tunnel_end_frag:1;
602 enum i40e_rx_ptype_outer_ip {
603 I40E_RX_PTYPE_OUTER_L2 = 0,
604 I40E_RX_PTYPE_OUTER_IP = 1
607 enum i40e_rx_ptype_outer_ip_ver {
608 I40E_RX_PTYPE_OUTER_NONE = 0,
609 I40E_RX_PTYPE_OUTER_IPV4 = 0,
610 I40E_RX_PTYPE_OUTER_IPV6 = 1
613 enum i40e_rx_ptype_outer_fragmented {
614 I40E_RX_PTYPE_NOT_FRAG = 0,
615 I40E_RX_PTYPE_FRAG = 1
618 enum i40e_rx_ptype_tunnel_type {
619 I40E_RX_PTYPE_TUNNEL_NONE = 0,
620 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
621 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
622 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
623 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
626 enum i40e_rx_ptype_tunnel_end_prot {
627 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
628 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
629 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
632 enum i40e_rx_ptype_inner_prot {
633 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
634 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
635 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
636 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
637 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
638 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
641 enum i40e_rx_ptype_payload_layer {
642 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
643 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
644 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
645 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
648 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
649 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
650 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
652 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
653 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
654 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
656 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
657 #define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \
658 I40E_RXD_QW1_LENGTH_SPH_SHIFT)
660 enum i40e_rx_desc_ext_status_bits {
661 /* Note: These are predefined bit offsets */
662 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
663 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
664 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
665 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
666 I40E_RX_DESC_EXT_STATUS_FTYPE_SHIFT = 6, /* 3 BITS */
667 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
668 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
669 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
672 enum i40e_rx_desc_pe_status_bits {
673 /* Note: These are predefined bit offsets */
674 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
675 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
676 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
677 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
678 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
679 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
680 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
681 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
682 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
685 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
686 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
688 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
689 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
690 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
692 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
693 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
694 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
696 enum i40e_rx_prog_status_desc_status_bits {
697 /* Note: These are predefined bit offsets */
698 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
699 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
702 enum i40e_rx_prog_status_desc_prog_id_masks {
703 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
704 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
705 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
708 enum i40e_rx_prog_status_desc_error_bits {
709 /* Note: These are predefined bit offsets */
710 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
711 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
712 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
713 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
717 struct i40e_tx_desc {
718 __le64 buffer_addr; /* Address of descriptor's data buf */
719 __le64 cmd_type_offset_bsz;
722 #define I40E_TXD_QW1_DTYPE_SHIFT 0
723 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
725 enum i40e_tx_desc_dtype_value {
726 I40E_TX_DESC_DTYPE_DATA = 0x0,
727 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
728 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
729 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
730 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
731 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
732 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
733 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
734 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
735 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
738 #define I40E_TXD_QW1_CMD_SHIFT 4
739 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
741 enum i40e_tx_desc_cmd_bits {
742 I40E_TX_DESC_CMD_EOP = 0x0001,
743 I40E_TX_DESC_CMD_RS = 0x0002,
744 I40E_TX_DESC_CMD_ICRC = 0x0004,
745 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
746 I40E_TX_DESC_CMD_DUMMY = 0x0010,
747 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
748 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
749 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
750 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
751 I40E_TX_DESC_CMD_FCOET = 0x0080,
752 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
753 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
754 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
755 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
756 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
757 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
758 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
759 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
762 #define I40E_TXD_QW1_OFFSET_SHIFT 16
763 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
764 I40E_TXD_QW1_OFFSET_SHIFT)
766 enum i40e_tx_desc_length_fields {
767 /* Note: These are predefined bit offsets */
768 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
769 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
770 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
773 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
774 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
775 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
777 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
778 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
780 /* Context descriptors */
781 struct i40e_tx_context_desc {
782 __le32 tunneling_params;
785 __le64 type_cmd_tso_mss;
788 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
789 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
791 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
792 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
794 enum i40e_tx_ctx_desc_cmd_bits {
795 I40E_TX_CTX_DESC_TSO = 0x01,
796 I40E_TX_CTX_DESC_TSYN = 0x02,
797 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
798 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
799 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
800 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
801 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
802 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
803 I40E_TX_CTX_DESC_SWPE = 0x40
806 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
807 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
808 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
810 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
811 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
812 I40E_TXD_CTX_QW1_MSS_SHIFT)
814 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
815 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
817 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
818 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
819 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
821 enum i40e_tx_ctx_desc_eipt_offload {
822 I40E_TX_CTX_EXT_IP_NONE = 0x0,
823 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
824 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
825 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
828 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
829 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
830 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
832 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
833 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
835 #define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
836 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
838 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
839 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
840 I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
842 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
844 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
845 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
846 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
848 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
849 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
850 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
852 struct i40e_filter_program_desc {
853 __le32 qindex_flex_ptype_vsi;
855 __le32 dtype_cmd_cntindex;
858 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
859 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
860 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
861 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
862 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
863 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
864 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
865 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
866 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
868 /* Packet Classifier Types for filters */
869 enum i40e_filter_pctype {
870 /* Note: Values 0-28 are reserved for future use */
871 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
872 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
873 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
874 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN = 32,
875 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
876 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
877 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
878 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
879 /* Note: Values 37-38 are reserved for future use */
880 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
881 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
882 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
883 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN = 42,
884 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
885 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
886 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
887 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
888 /* Note: Value 47 is reserved for future use */
889 I40E_FILTER_PCTYPE_FCOE_OX = 48,
890 I40E_FILTER_PCTYPE_FCOE_RX = 49,
891 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
892 /* Note: Values 51-62 are reserved for future use */
893 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
896 enum i40e_filter_program_desc_dest {
897 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
898 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
899 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
902 enum i40e_filter_program_desc_fd_status {
903 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
904 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
905 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
906 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
909 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
910 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
911 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
913 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
914 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
915 I40E_TXD_FLTR_QW1_CMD_SHIFT)
917 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
918 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
920 enum i40e_filter_program_desc_pcmd {
921 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
922 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
925 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
926 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
928 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
929 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \
930 I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
932 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
933 I40E_TXD_FLTR_QW1_CMD_SHIFT)
934 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
935 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
937 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
938 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
939 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
941 enum i40e_filter_type {
942 I40E_FLOW_DIRECTOR_FLTR = 0,
943 I40E_PE_QUAD_HASH_FLTR = 1,
950 struct i40e_vsi_context {
955 u16 vsis_unallocated;
960 struct i40e_aqc_vsi_properties_data info;
963 /* Statistics collected by each port, VSI, VEB, and S-channel */
964 struct i40e_eth_stats {
965 u64 rx_bytes; /* gorc */
966 u64 rx_unicast; /* uprc */
967 u64 rx_multicast; /* mprc */
968 u64 rx_broadcast; /* bprc */
969 u64 rx_discards; /* rdpc */
970 u64 rx_errors; /* repc */
971 u64 rx_missed; /* rmpc */
972 u64 rx_unknown_protocol; /* rupp */
973 u64 tx_bytes; /* gotc */
974 u64 tx_unicast; /* uptc */
975 u64 tx_multicast; /* mptc */
976 u64 tx_broadcast; /* bptc */
977 u64 tx_discards; /* tdpc */
978 u64 tx_errors; /* tepc */
981 /* Statistics collected by the MAC */
982 struct i40e_hw_port_stats {
983 /* eth stats collected by the port */
984 struct i40e_eth_stats eth;
986 /* additional port specific stats */
987 u64 tx_dropped_link_down; /* tdold */
988 u64 crc_errors; /* crcerrs */
989 u64 illegal_bytes; /* illerrc */
990 u64 error_bytes; /* errbc */
991 u64 mac_local_faults; /* mlfc */
992 u64 mac_remote_faults; /* mrfc */
993 u64 rx_length_errors; /* rlec */
994 u64 link_xon_rx; /* lxonrxc */
995 u64 link_xoff_rx; /* lxoffrxc */
996 u64 priority_xon_rx[8]; /* pxonrxc[8] */
997 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
998 u64 link_xon_tx; /* lxontxc */
999 u64 link_xoff_tx; /* lxofftxc */
1000 u64 priority_xon_tx[8]; /* pxontxc[8] */
1001 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1002 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1003 u64 rx_size_64; /* prc64 */
1004 u64 rx_size_127; /* prc127 */
1005 u64 rx_size_255; /* prc255 */
1006 u64 rx_size_511; /* prc511 */
1007 u64 rx_size_1023; /* prc1023 */
1008 u64 rx_size_1522; /* prc1522 */
1009 u64 rx_size_big; /* prc9522 */
1010 u64 rx_undersize; /* ruc */
1011 u64 rx_fragments; /* rfc */
1012 u64 rx_oversize; /* roc */
1013 u64 rx_jabber; /* rjc */
1014 u64 tx_size_64; /* ptc64 */
1015 u64 tx_size_127; /* ptc127 */
1016 u64 tx_size_255; /* ptc255 */
1017 u64 tx_size_511; /* ptc511 */
1018 u64 tx_size_1023; /* ptc1023 */
1019 u64 tx_size_1522; /* ptc1522 */
1020 u64 tx_size_big; /* ptc9522 */
1021 u64 mac_short_packet_dropped; /* mspdc */
1022 u64 checksum_error; /* xec */
1025 /* Checksum and Shadow RAM pointers */
1026 #define I40E_SR_NVM_CONTROL_WORD 0x00
1027 #define I40E_SR_EMP_MODULE_PTR 0x0F
1028 #define I40E_SR_NVM_IMAGE_VERSION 0x18
1029 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1030 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1031 #define I40E_SR_NVM_EETRACK_LO 0x2D
1032 #define I40E_SR_NVM_EETRACK_HI 0x2E
1033 #define I40E_SR_VPD_PTR 0x2F
1034 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1035 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1037 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1038 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1039 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1040 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1041 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1043 /* Shadow RAM related */
1044 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1045 #define I40E_SR_WORDS_IN_1KB 512
1046 /* Checksum should be calculated such that after adding all the words,
1047 * including the checksum word itself, the sum should be 0xBABA.
1049 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1051 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1053 enum i40e_switch_element_types {
1054 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1055 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1056 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1057 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1058 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1059 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1060 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1061 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1062 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1065 /* Supported EtherType filters */
1066 enum i40e_ether_type_index {
1067 I40E_ETHER_TYPE_1588 = 0,
1068 I40E_ETHER_TYPE_FIP = 1,
1069 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1070 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1071 I40E_ETHER_TYPE_LLDP = 4,
1072 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1073 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1074 I40E_ETHER_TYPE_QCN_CNM = 7,
1075 I40E_ETHER_TYPE_8021X = 8,
1076 I40E_ETHER_TYPE_ARP = 9,
1077 I40E_ETHER_TYPE_RSV1 = 10,
1078 I40E_ETHER_TYPE_RSV2 = 11,
1081 /* Filter context base size is 1K */
1082 #define I40E_HASH_FILTER_BASE_SIZE 1024
1083 /* Supported Hash filter values */
1084 enum i40e_hash_filter_size {
1085 I40E_HASH_FILTER_SIZE_1K = 0,
1086 I40E_HASH_FILTER_SIZE_2K = 1,
1087 I40E_HASH_FILTER_SIZE_4K = 2,
1088 I40E_HASH_FILTER_SIZE_8K = 3,
1089 I40E_HASH_FILTER_SIZE_16K = 4,
1090 I40E_HASH_FILTER_SIZE_32K = 5,
1091 I40E_HASH_FILTER_SIZE_64K = 6,
1092 I40E_HASH_FILTER_SIZE_128K = 7,
1093 I40E_HASH_FILTER_SIZE_256K = 8,
1094 I40E_HASH_FILTER_SIZE_512K = 9,
1095 I40E_HASH_FILTER_SIZE_1M = 10,
1098 /* DMA context base size is 0.5K */
1099 #define I40E_DMA_CNTX_BASE_SIZE 512
1100 /* Supported DMA context values */
1101 enum i40e_dma_cntx_size {
1102 I40E_DMA_CNTX_SIZE_512 = 0,
1103 I40E_DMA_CNTX_SIZE_1K = 1,
1104 I40E_DMA_CNTX_SIZE_2K = 2,
1105 I40E_DMA_CNTX_SIZE_4K = 3,
1106 I40E_DMA_CNTX_SIZE_8K = 4,
1107 I40E_DMA_CNTX_SIZE_16K = 5,
1108 I40E_DMA_CNTX_SIZE_32K = 6,
1109 I40E_DMA_CNTX_SIZE_64K = 7,
1110 I40E_DMA_CNTX_SIZE_128K = 8,
1111 I40E_DMA_CNTX_SIZE_256K = 9,
1114 /* Supported Hash look up table (LUT) sizes */
1115 enum i40e_hash_lut_size {
1116 I40E_HASH_LUT_SIZE_128 = 0,
1117 I40E_HASH_LUT_SIZE_512 = 1,
1120 /* Structure to hold a per PF filter control settings */
1121 struct i40e_filter_control_settings {
1122 /* number of PE Quad Hash filter buckets */
1123 enum i40e_hash_filter_size pe_filt_num;
1124 /* number of PE Quad Hash contexts */
1125 enum i40e_dma_cntx_size pe_cntx_num;
1126 /* number of FCoE filter buckets */
1127 enum i40e_hash_filter_size fcoe_filt_num;
1128 /* number of FCoE DDP contexts */
1129 enum i40e_dma_cntx_size fcoe_cntx_num;
1130 /* size of the Hash LUT */
1131 enum i40e_hash_lut_size hash_lut_size;
1132 /* enable FDIR filters for PF and its VFs */
1134 /* enable Ethertype filters for PF and its VFs */
1135 bool enable_ethtype;
1136 /* enable MAC/VLAN filters for PF and its VFs */
1137 bool enable_macvlan;
1140 /* Structure to hold device level control filter counts */
1141 struct i40e_control_filter_stats {
1142 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1143 u16 etype_used; /* Used perfect EtherType filters */
1144 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1145 u16 etype_free; /* Un-used perfect EtherType filters */
1148 enum i40e_reset_type {
1150 I40E_RESET_CORER = 1,
1151 I40E_RESET_GLOBR = 2,
1152 I40E_RESET_EMPR = 3,
1154 #endif /* _I40E_TYPE_H_ */