drivers/net/ethernet/intel/i40evf/i40e_txrx.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include <linux/prefetch.h>
  28 #include <net/busy_poll.h>
  29
  30 #include "i40evf.h"
  31 #include "i40e_prototype.h"
  32
  33 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
  34                                 u32 td_tag)
  35 {
  36         return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
  37                            ((u64)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
  38                            ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
  39                            ((u64)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
  40                            ((u64)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
  41 }
  42
  43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  44
  45 /**
  46  * i40e_unmap_and_free_tx_resource - Release a Tx buffer
  47  * @ring:      the ring that owns the buffer
  48  * @tx_buffer: the buffer to free
  49  **/
  50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
  51                                             struct i40e_tx_buffer *tx_buffer)
  52 {
  53         if (tx_buffer->skb) {
  54                 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
  55                         kfree(tx_buffer->raw_buf);
  56                 else
  57                         dev_kfree_skb_any(tx_buffer->skb);
  58
  59                 if (dma_unmap_len(tx_buffer, len))
  60                         dma_unmap_single(ring->dev,
  61                                          dma_unmap_addr(tx_buffer, dma),
  62                                          dma_unmap_len(tx_buffer, len),
  63                                          DMA_TO_DEVICE);
  64         } else if (dma_unmap_len(tx_buffer, len)) {
  65                 dma_unmap_page(ring->dev,
  66                                dma_unmap_addr(tx_buffer, dma),
  67                                dma_unmap_len(tx_buffer, len),
  68                                DMA_TO_DEVICE);
  69         }
  70         tx_buffer->next_to_watch = NULL;
  71         tx_buffer->skb = NULL;
  72         dma_unmap_len_set(tx_buffer, len, 0);
  73         /* tx_buffer must be completely set up in the transmit path */
  74 }
  75
  76 /**
  77  * i40evf_clean_tx_ring - Free any empty Tx buffers
  78  * @tx_ring: ring to be cleaned
  79  **/
  80 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
  81 {
  82         unsigned long bi_size;
  83         u16 i;
  84
  85         /* ring already cleared, nothing to do */
  86         if (!tx_ring->tx_bi)
  87                 return;
  88
  89         /* Free all the Tx ring sk_buffs */
  90         for (i = 0; i < tx_ring->count; i++)
  91                 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
  92
  93         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
  94         memset(tx_ring->tx_bi, 0, bi_size);
  95
  96         /* Zero out the descriptor ring */
  97         memset(tx_ring->desc, 0, tx_ring->size);
  98
  99         tx_ring->next_to_use = 0;
 100         tx_ring->next_to_clean = 0;
 101
 102         if (!tx_ring->netdev)
 103                 return;
 104
 105         /* cleanup Tx queue statistics */
 106         netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
 107                                                   tx_ring->queue_index));
 108 }
 109
 110 /**
 111  * i40evf_free_tx_resources - Free Tx resources per queue
 112  * @tx_ring: Tx descriptor ring for a specific queue
 113  *
 114  * Free all transmit software resources
 115  **/
 116 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
 117 {
 118         i40evf_clean_tx_ring(tx_ring);
 119         kfree(tx_ring->tx_bi);
 120         tx_ring->tx_bi = NULL;
 121
 122         if (tx_ring->desc) {
 123                 dma_free_coherent(tx_ring->dev, tx_ring->size,
 124                                   tx_ring->desc, tx_ring->dma);
 125                 tx_ring->desc = NULL;
 126         }
 127 }
 128
 129 /**
 130  * i40e_get_head - Retrieve head from head writeback
 131  * @tx_ring:  tx ring to fetch head of
 132  *
 133  * Returns value of Tx ring head based on value stored
 134  * in head write-back location
 135  **/
 136 static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
 137 {
 138         void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
 139
 140         return le32_to_cpu(*(volatile __le32 *)head);
 141 }
 142
 143 /**
 144  * i40e_get_tx_pending - how many tx descriptors not processed
 145  * @tx_ring: the ring of descriptors
 146  *
 147  * Since there is no access to the ring head register
 148  * in XL710, we need to use our local copies
 149  **/
 150 static u32 i40e_get_tx_pending(struct i40e_ring *ring)
 151 {
 152         u32 head, tail;
 153
 154         head = i40e_get_head(ring);
 155         tail = readl(ring->tail);
 156
 157         if (head != tail)
 158                 return (head < tail) ?
 159                         tail - head : (tail + ring->count - head);
 160
 161         return 0;
 162 }
 163
 164 /**
 165  * i40e_check_tx_hang - Is there a hang in the Tx queue
 166  * @tx_ring: the ring of descriptors
 167  **/
 168 static bool i40e_check_tx_hang(struct i40e_ring *tx_ring)
 169 {
 170         u32 tx_done = tx_ring->stats.packets;
 171         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
 172         u32 tx_pending = i40e_get_tx_pending(tx_ring);
 173         bool ret = false;
 174
 175         clear_check_for_tx_hang(tx_ring);
 176
 177         /* Check for a hung queue, but be thorough. This verifies
 178          * that a transmit has been completed since the previous
 179          * check AND there is at least one packet pending. The
 180          * ARMED bit is set to indicate a potential hang. The
 181          * bit is cleared if a pause frame is received to remove
 182          * false hang detection due to PFC or 802.3x frames. By
 183          * requiring this to fail twice we avoid races with
 184          * PFC clearing the ARMED bit and conditions where we
 185          * run the check_tx_hang logic with a transmit completion
 186          * pending but without time to complete it yet.
 187          */
 188         if ((tx_done_old == tx_done) && tx_pending) {
 189                 /* make sure it is true for two checks in a row */
 190                 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED,
 191                                        &tx_ring->state);
 192         } else if (tx_done_old == tx_done &&
 193                    (tx_pending < I40E_MIN_DESC_PENDING) && (tx_pending > 0)) {
 194                 /* update completed stats and disarm the hang check */
 195                 tx_ring->tx_stats.tx_done_old = tx_done;
 196                 clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state);
 197         }
 198
 199         return ret;
 200 }
 201
 202 #define WB_STRIDE 0x3
 203
 204 /**
 205  * i40e_clean_tx_irq - Reclaim resources after transmit completes
 206  * @tx_ring:  tx ring to clean
 207  * @budget:   how many cleans we're allowed
 208  *
 209  * Returns true if there's any budget left (e.g. the clean is finished)
 210  **/
 211 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
 212 {
 213         u16 i = tx_ring->next_to_clean;
 214         struct i40e_tx_buffer *tx_buf;
 215         struct i40e_tx_desc *tx_head;
 216         struct i40e_tx_desc *tx_desc;
 217         unsigned int total_packets = 0;
 218         unsigned int total_bytes = 0;
 219
 220         tx_buf = &tx_ring->tx_bi[i];
 221         tx_desc = I40E_TX_DESC(tx_ring, i);
 222         i -= tx_ring->count;
 223
 224         tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
 225
 226         do {
 227                 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
 228
 229                 /* if next_to_watch is not set then there is no work pending */
 230                 if (!eop_desc)
 231                         break;
 232
 233                 /* prevent any other reads prior to eop_desc */
 234                 read_barrier_depends();
 235
 236                 /* we have caught up to head, no work left to do */
 237                 if (tx_head == tx_desc)
 238                         break;
 239
 240                 /* clear next_to_watch to prevent false hangs */
 241                 tx_buf->next_to_watch = NULL;
 242
 243                 /* update the statistics for this packet */
 244                 total_bytes += tx_buf->bytecount;
 245                 total_packets += tx_buf->gso_segs;
 246
 247                 /* free the skb */
 248                 dev_kfree_skb_any(tx_buf->skb);
 249
 250                 /* unmap skb header data */
 251                 dma_unmap_single(tx_ring->dev,
 252                                  dma_unmap_addr(tx_buf, dma),
 253                                  dma_unmap_len(tx_buf, len),
 254                                  DMA_TO_DEVICE);
 255
 256                 /* clear tx_buffer data */
 257                 tx_buf->skb = NULL;
 258                 dma_unmap_len_set(tx_buf, len, 0);
 259
 260                 /* unmap remaining buffers */
 261                 while (tx_desc != eop_desc) {
 262
 263                         tx_buf++;
 264                         tx_desc++;
 265                         i++;
 266                         if (unlikely(!i)) {
 267                                 i -= tx_ring->count;
 268                                 tx_buf = tx_ring->tx_bi;
 269                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
 270                         }
 271
 272                         /* unmap any remaining paged data */
 273                         if (dma_unmap_len(tx_buf, len)) {
 274                                 dma_unmap_page(tx_ring->dev,
 275                                                dma_unmap_addr(tx_buf, dma),
 276                                                dma_unmap_len(tx_buf, len),
 277                                                DMA_TO_DEVICE);
 278                                 dma_unmap_len_set(tx_buf, len, 0);
 279                         }
 280                 }
 281
 282                 /* move us one more past the eop_desc for start of next pkt */
 283                 tx_buf++;
 284                 tx_desc++;
 285                 i++;
 286                 if (unlikely(!i)) {
 287                         i -= tx_ring->count;
 288                         tx_buf = tx_ring->tx_bi;
 289                         tx_desc = I40E_TX_DESC(tx_ring, 0);
 290                 }
 291
 292                 prefetch(tx_desc);
 293
 294                 /* update budget accounting */
 295                 budget--;
 296         } while (likely(budget));
 297
 298         i += tx_ring->count;
 299         tx_ring->next_to_clean = i;
 300         u64_stats_update_begin(&tx_ring->syncp);
 301         tx_ring->stats.bytes += total_bytes;
 302         tx_ring->stats.packets += total_packets;
 303         u64_stats_update_end(&tx_ring->syncp);
 304         tx_ring->q_vector->tx.total_bytes += total_bytes;
 305         tx_ring->q_vector->tx.total_packets += total_packets;
 306
 307         if (budget &&
 308             !((i & WB_STRIDE) == WB_STRIDE) &&
 309             !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
 310             (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
 311                 tx_ring->arm_wb = true;
 312         else
 313                 tx_ring->arm_wb = false;
 314
 315         if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) {
 316                 /* schedule immediate reset if we believe we hung */
 317                 dev_info(tx_ring->dev, "Detected Tx Unit Hang\n"
 318                          "  VSI                  <%d>\n"
 319                          "  Tx Queue             <%d>\n"
 320                          "  next_to_use          <%x>\n"
 321                          "  next_to_clean        <%x>\n",
 322                          tx_ring->vsi->seid,
 323                          tx_ring->queue_index,
 324                          tx_ring->next_to_use, i);
 325
 326                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 327
 328                 dev_info(tx_ring->dev,
 329                          "tx hang detected on queue %d, resetting adapter\n",
 330                          tx_ring->queue_index);
 331
 332                 tx_ring->netdev->netdev_ops->ndo_tx_timeout(tx_ring->netdev);
 333
 334                 /* the adapter is about to reset, no point in enabling stuff */
 335                 return true;
 336         }
 337
 338         netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
 339                                                       tx_ring->queue_index),
 340                                   total_packets, total_bytes);
 341
 342 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 343         if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
 344                      (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 345                 /* Make sure that anybody stopping the queue after this
 346                  * sees the new next_to_clean.
 347                  */
 348                 smp_mb();
 349                 if (__netif_subqueue_stopped(tx_ring->netdev,
 350                                              tx_ring->queue_index) &&
 351                    !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
 352                         netif_wake_subqueue(tx_ring->netdev,
 353                                             tx_ring->queue_index);
 354                         ++tx_ring->tx_stats.restart_queue;
 355                 }
 356         }
 357
 358         return budget > 0;
 359 }
 360
 361 /**
 362  * i40e_force_wb -Arm hardware to do a wb on noncache aligned descriptors
 363  * @vsi: the VSI we care about
 364  * @q_vector: the vector  on which to force writeback
 365  *
 366  **/
 367 static void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
 368 {
 369         u32 val = I40E_VFINT_DYN_CTLN_INTENA_MASK |
 370                   I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
 371                   I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK |
 372                   I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
 373                   /* allow 00 to be written to the index */
 374
 375         wr32(&vsi->back->hw,
 376              I40E_VFINT_DYN_CTLN1(q_vector->v_idx + vsi->base_vector - 1),
 377              val);
 378 }
 379
 380 /**
 381  * i40e_set_new_dynamic_itr - Find new ITR level
 382  * @rc: structure containing ring performance data
 383  *
 384  * Stores a new ITR value based on packets and byte counts during
 385  * the last interrupt.  The advantage of per interrupt computation
 386  * is faster updates and more accurate ITR for the current traffic
 387  * pattern.  Constants in this function were computed based on
 388  * theoretical maximum wire speed and thresholds were set based on
 389  * testing data as well as attempting to minimize response time
 390  * while increasing bulk throughput.
 391  **/
 392 static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
 393 {
 394         enum i40e_latency_range new_latency_range = rc->latency_range;
 395         u32 new_itr = rc->itr;
 396         int bytes_per_int;
 397
 398         if (rc->total_packets == 0 || !rc->itr)
 399                 return;
 400
 401         /* simple throttlerate management
 402          *   0-10MB/s   lowest (100000 ints/s)
 403          *  10-20MB/s   low    (20000 ints/s)
 404          *  20-1249MB/s bulk   (8000 ints/s)
 405          */
 406         bytes_per_int = rc->total_bytes / rc->itr;
 407         switch (rc->itr) {
 408         case I40E_LOWEST_LATENCY:
 409                 if (bytes_per_int > 10)
 410                         new_latency_range = I40E_LOW_LATENCY;
 411                 break;
 412         case I40E_LOW_LATENCY:
 413                 if (bytes_per_int > 20)
 414                         new_latency_range = I40E_BULK_LATENCY;
 415                 else if (bytes_per_int <= 10)
 416                         new_latency_range = I40E_LOWEST_LATENCY;
 417                 break;
 418         case I40E_BULK_LATENCY:
 419                 if (bytes_per_int <= 20)
 420                         rc->latency_range = I40E_LOW_LATENCY;
 421                 break;
 422         }
 423
 424         switch (new_latency_range) {
 425         case I40E_LOWEST_LATENCY:
 426                 new_itr = I40E_ITR_100K;
 427                 break;
 428         case I40E_LOW_LATENCY:
 429                 new_itr = I40E_ITR_20K;
 430                 break;
 431         case I40E_BULK_LATENCY:
 432                 new_itr = I40E_ITR_8K;
 433                 break;
 434         default:
 435                 break;
 436         }
 437
 438         if (new_itr != rc->itr) {
 439                 /* do an exponential smoothing */
 440                 new_itr = (10 * new_itr * rc->itr) /
 441                           ((9 * new_itr) + rc->itr);
 442                 rc->itr = new_itr & I40E_MAX_ITR;
 443         }
 444
 445         rc->total_bytes = 0;
 446         rc->total_packets = 0;
 447 }
 448
 449 /**
 450  * i40e_update_dynamic_itr - Adjust ITR based on bytes per int
 451  * @q_vector: the vector to adjust
 452  **/
 453 static void i40e_update_dynamic_itr(struct i40e_q_vector *q_vector)
 454 {
 455         u16 vector = q_vector->vsi->base_vector + q_vector->v_idx;
 456         struct i40e_hw *hw = &q_vector->vsi->back->hw;
 457         u32 reg_addr;
 458         u16 old_itr;
 459
 460         reg_addr = I40E_VFINT_ITRN1(I40E_RX_ITR, vector - 1);
 461         old_itr = q_vector->rx.itr;
 462         i40e_set_new_dynamic_itr(&q_vector->rx);
 463         if (old_itr != q_vector->rx.itr)
 464                 wr32(hw, reg_addr, q_vector->rx.itr);
 465
 466         reg_addr = I40E_VFINT_ITRN1(I40E_TX_ITR, vector - 1);
 467         old_itr = q_vector->tx.itr;
 468         i40e_set_new_dynamic_itr(&q_vector->tx);
 469         if (old_itr != q_vector->tx.itr)
 470                 wr32(hw, reg_addr, q_vector->tx.itr);
 471 }
 472
 473 /**
 474  * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
 475  * @tx_ring: the tx ring to set up
 476  *
 477  * Return 0 on success, negative on error
 478  **/
 479 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
 480 {
 481         struct device *dev = tx_ring->dev;
 482         int bi_size;
 483
 484         if (!dev)
 485                 return -ENOMEM;
 486
 487         bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
 488         tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
 489         if (!tx_ring->tx_bi)
 490                 goto err;
 491
 492         /* round up to nearest 4K */
 493         tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
 494         /* add u32 for head writeback, align after this takes care of
 495          * guaranteeing this is at least one cache line in size
 496          */
 497         tx_ring->size += sizeof(u32);
 498         tx_ring->size = ALIGN(tx_ring->size, 4096);
 499         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
 500                                            &tx_ring->dma, GFP_KERNEL);
 501         if (!tx_ring->desc) {
 502                 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
 503                          tx_ring->size);
 504                 goto err;
 505         }
 506
 507         tx_ring->next_to_use = 0;
 508         tx_ring->next_to_clean = 0;
 509         return 0;
 510
 511 err:
 512         kfree(tx_ring->tx_bi);
 513         tx_ring->tx_bi = NULL;
 514         return -ENOMEM;
 515 }
 516
 517 /**
 518  * i40evf_clean_rx_ring - Free Rx buffers
 519  * @rx_ring: ring to be cleaned
 520  **/
 521 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
 522 {
 523         struct device *dev = rx_ring->dev;
 524         struct i40e_rx_buffer *rx_bi;
 525         unsigned long bi_size;
 526         u16 i;
 527
 528         /* ring already cleared, nothing to do */
 529         if (!rx_ring->rx_bi)
 530                 return;
 531
 532         if (ring_is_ps_enabled(rx_ring)) {
 533                 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
 534
 535                 rx_bi = &rx_ring->rx_bi[0];
 536                 if (rx_bi->hdr_buf) {
 537                         dma_free_coherent(dev,
 538                                           bufsz,
 539                                           rx_bi->hdr_buf,
 540                                           rx_bi->dma);
 541                         for (i = 0; i < rx_ring->count; i++) {
 542                                 rx_bi = &rx_ring->rx_bi[i];
 543                                 rx_bi->dma = 0;
 544                                 rx_bi->hdr_buf = NULL;
 545                         }
 546                 }
 547         }
 548         /* Free all the Rx ring sk_buffs */
 549         for (i = 0; i < rx_ring->count; i++) {
 550                 rx_bi = &rx_ring->rx_bi[i];
 551                 if (rx_bi->dma) {
 552                         dma_unmap_single(dev,
 553                                          rx_bi->dma,
 554                                          rx_ring->rx_buf_len,
 555                                          DMA_FROM_DEVICE);
 556                         rx_bi->dma = 0;
 557                 }
 558                 if (rx_bi->skb) {
 559                         dev_kfree_skb(rx_bi->skb);
 560                         rx_bi->skb = NULL;
 561                 }
 562                 if (rx_bi->page) {
 563                         if (rx_bi->page_dma) {
 564                                 dma_unmap_page(dev,
 565                                                rx_bi->page_dma,
 566                                                PAGE_SIZE / 2,
 567                                                DMA_FROM_DEVICE);
 568                                 rx_bi->page_dma = 0;
 569                         }
 570                         __free_page(rx_bi->page);
 571                         rx_bi->page = NULL;
 572                         rx_bi->page_offset = 0;
 573                 }
 574         }
 575
 576         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 577         memset(rx_ring->rx_bi, 0, bi_size);
 578
 579         /* Zero out the descriptor ring */
 580         memset(rx_ring->desc, 0, rx_ring->size);
 581
 582         rx_ring->next_to_clean = 0;
 583         rx_ring->next_to_use = 0;
 584 }
 585
 586 /**
 587  * i40evf_free_rx_resources - Free Rx resources
 588  * @rx_ring: ring to clean the resources from
 589  *
 590  * Free all receive software resources
 591  **/
 592 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
 593 {
 594         i40evf_clean_rx_ring(rx_ring);
 595         kfree(rx_ring->rx_bi);
 596         rx_ring->rx_bi = NULL;
 597
 598         if (rx_ring->desc) {
 599                 dma_free_coherent(rx_ring->dev, rx_ring->size,
 600                                   rx_ring->desc, rx_ring->dma);
 601                 rx_ring->desc = NULL;
 602         }
 603 }
 604
 605 /**
 606  * i40evf_alloc_rx_headers - allocate rx header buffers
 607  * @rx_ring: ring to alloc buffers
 608  *
 609  * Allocate rx header buffers for the entire ring. As these are static,
 610  * this is only called when setting up a new ring.
 611  **/
 612 void i40evf_alloc_rx_headers(struct i40e_ring *rx_ring)
 613 {
 614         struct device *dev = rx_ring->dev;
 615         struct i40e_rx_buffer *rx_bi;
 616         dma_addr_t dma;
 617         void *buffer;
 618         int buf_size;
 619         int i;
 620
 621         if (rx_ring->rx_bi[0].hdr_buf)
 622                 return;
 623         /* Make sure the buffers don't cross cache line boundaries. */
 624         buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
 625         buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
 626                                     &dma, GFP_KERNEL);
 627         if (!buffer)
 628                 return;
 629         for (i = 0; i < rx_ring->count; i++) {
 630                 rx_bi = &rx_ring->rx_bi[i];
 631                 rx_bi->dma = dma + (i * buf_size);
 632                 rx_bi->hdr_buf = buffer + (i * buf_size);
 633         }
 634 }
 635
 636 /**
 637  * i40evf_setup_rx_descriptors - Allocate Rx descriptors
 638  * @rx_ring: Rx descriptor ring (for a specific queue) to setup
 639  *
 640  * Returns 0 on success, negative on failure
 641  **/
 642 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
 643 {
 644         struct device *dev = rx_ring->dev;
 645         int bi_size;
 646
 647         bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
 648         rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
 649         if (!rx_ring->rx_bi)
 650                 goto err;
 651
 652         u64_stats_init(&rx_ring->syncp);
 653
 654         /* Round up to nearest 4K */
 655         rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
 656                 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
 657                 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
 658         rx_ring->size = ALIGN(rx_ring->size, 4096);
 659         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
 660                                            &rx_ring->dma, GFP_KERNEL);
 661
 662         if (!rx_ring->desc) {
 663                 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
 664                          rx_ring->size);
 665                 goto err;
 666         }
 667
 668         rx_ring->next_to_clean = 0;
 669         rx_ring->next_to_use = 0;
 670
 671         return 0;
 672 err:
 673         kfree(rx_ring->rx_bi);
 674         rx_ring->rx_bi = NULL;
 675         return -ENOMEM;
 676 }
 677
 678 /**
 679  * i40e_release_rx_desc - Store the new tail and head values
 680  * @rx_ring: ring to bump
 681  * @val: new head index
 682  **/
 683 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
 684 {
 685         rx_ring->next_to_use = val;
 686         /* Force memory writes to complete before letting h/w
 687          * know there are new descriptors to fetch.  (Only
 688          * applicable for weak-ordered memory model archs,
 689          * such as IA-64).
 690          */
 691         wmb();
 692         writel(val, rx_ring->tail);
 693 }
 694
 695 /**
 696  * i40evf_alloc_rx_buffers_ps - Replace used receive buffers; packet split
 697  * @rx_ring: ring to place buffers on
 698  * @cleaned_count: number of buffers to replace
 699  **/
 700 void i40evf_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
 701 {
 702         u16 i = rx_ring->next_to_use;
 703         union i40e_rx_desc *rx_desc;
 704         struct i40e_rx_buffer *bi;
 705
 706         /* do nothing if no valid netdev defined */
 707         if (!rx_ring->netdev || !cleaned_count)
 708                 return;
 709
 710         while (cleaned_count--) {
 711                 rx_desc = I40E_RX_DESC(rx_ring, i);
 712                 bi = &rx_ring->rx_bi[i];
 713
 714                 if (bi->skb) /* desc is in use */
 715                         goto no_buffers;
 716                 if (!bi->page) {
 717                         bi->page = alloc_page(GFP_ATOMIC);
 718                         if (!bi->page) {
 719                                 rx_ring->rx_stats.alloc_page_failed++;
 720                                 goto no_buffers;
 721                         }
 722                 }
 723
 724                 if (!bi->page_dma) {
 725                         /* use a half page if we're re-using */
 726                         bi->page_offset ^= PAGE_SIZE / 2;
 727                         bi->page_dma = dma_map_page(rx_ring->dev,
 728                                                     bi->page,
 729                                                     bi->page_offset,
 730                                                     PAGE_SIZE / 2,
 731                                                     DMA_FROM_DEVICE);
 732                         if (dma_mapping_error(rx_ring->dev,
 733                                               bi->page_dma)) {
 734                                 rx_ring->rx_stats.alloc_page_failed++;
 735                                 bi->page_dma = 0;
 736                                 goto no_buffers;
 737                         }
 738                 }
 739
 740                 dma_sync_single_range_for_device(rx_ring->dev,
 741                                                  bi->dma,
 742                                                  0,
 743                                                  rx_ring->rx_hdr_len,
 744                                                  DMA_FROM_DEVICE);
 745                 /* Refresh the desc even if buffer_addrs didn't change
 746                  * because each write-back erases this info.
 747                  */
 748                 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 749                 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 750                 i++;
 751                 if (i == rx_ring->count)
 752                         i = 0;
 753         }
 754
 755 no_buffers:
 756         if (rx_ring->next_to_use != i)
 757                 i40e_release_rx_desc(rx_ring, i);
 758 }
 759
 760 /**
 761  * i40evf_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
 762  * @rx_ring: ring to place buffers on
 763  * @cleaned_count: number of buffers to replace
 764  **/
 765 void i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
 766 {
 767         u16 i = rx_ring->next_to_use;
 768         union i40e_rx_desc *rx_desc;
 769         struct i40e_rx_buffer *bi;
 770         struct sk_buff *skb;
 771
 772         /* do nothing if no valid netdev defined */
 773         if (!rx_ring->netdev || !cleaned_count)
 774                 return;
 775
 776         while (cleaned_count--) {
 777                 rx_desc = I40E_RX_DESC(rx_ring, i);
 778                 bi = &rx_ring->rx_bi[i];
 779                 skb = bi->skb;
 780
 781                 if (!skb) {
 782                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
 783                                                         rx_ring->rx_buf_len);
 784                         if (!skb) {
 785                                 rx_ring->rx_stats.alloc_buff_failed++;
 786                                 goto no_buffers;
 787                         }
 788                         /* initialize queue mapping */
 789                         skb_record_rx_queue(skb, rx_ring->queue_index);
 790                         bi->skb = skb;
 791                 }
 792
 793                 if (!bi->dma) {
 794                         bi->dma = dma_map_single(rx_ring->dev,
 795                                                  skb->data,
 796                                                  rx_ring->rx_buf_len,
 797                                                  DMA_FROM_DEVICE);
 798                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
 799                                 rx_ring->rx_stats.alloc_buff_failed++;
 800                                 bi->dma = 0;
 801                                 goto no_buffers;
 802                         }
 803                 }
 804
 805                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 806                 rx_desc->read.hdr_addr = 0;
 807                 i++;
 808                 if (i == rx_ring->count)
 809                         i = 0;
 810         }
 811
 812 no_buffers:
 813         if (rx_ring->next_to_use != i)
 814                 i40e_release_rx_desc(rx_ring, i);
 815 }
 816
 817 /**
 818  * i40e_receive_skb - Send a completed packet up the stack
 819  * @rx_ring:  rx ring in play
 820  * @skb: packet to send up
 821  * @vlan_tag: vlan tag for packet
 822  **/
 823 static void i40e_receive_skb(struct i40e_ring *rx_ring,
 824                              struct sk_buff *skb, u16 vlan_tag)
 825 {
 826         struct i40e_q_vector *q_vector = rx_ring->q_vector;
 827         struct i40e_vsi *vsi = rx_ring->vsi;
 828         u64 flags = vsi->back->flags;
 829
 830         if (vlan_tag & VLAN_VID_MASK)
 831                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
 832
 833         if (flags & I40E_FLAG_IN_NETPOLL)
 834                 netif_rx(skb);
 835         else
 836                 napi_gro_receive(&q_vector->napi, skb);
 837 }
 838
 839 /**
 840  * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
 841  * @vsi: the VSI we care about
 842  * @skb: skb currently being received and modified
 843  * @rx_status: status value of last descriptor in packet
 844  * @rx_error: error value of last descriptor in packet
 845  * @rx_ptype: ptype value of last descriptor in packet
 846  **/
 847 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
 848                                     struct sk_buff *skb,
 849                                     u32 rx_status,
 850                                     u32 rx_error,
 851                                     u16 rx_ptype)
 852 {
 853         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
 854         bool ipv4 = false, ipv6 = false;
 855         bool ipv4_tunnel, ipv6_tunnel;
 856         __wsum rx_udp_csum;
 857         struct iphdr *iph;
 858         __sum16 csum;
 859
 860         ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
 861                      (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
 862         ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
 863                      (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
 864
 865         skb->ip_summed = CHECKSUM_NONE;
 866
 867         /* Rx csum enabled and ip headers found? */
 868         if (!(vsi->netdev->features & NETIF_F_RXCSUM))
 869                 return;
 870
 871         /* did the hardware decode the packet and checksum? */
 872         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
 873                 return;
 874
 875         /* both known and outer_ip must be set for the below code to work */
 876         if (!(decoded.known && decoded.outer_ip))
 877                 return;
 878
 879         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 880             decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
 881                 ipv4 = true;
 882         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 883                  decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
 884                 ipv6 = true;
 885
 886         if (ipv4 &&
 887             (rx_error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) |
 888                          (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT))))
 889                 goto checksum_fail;
 890
 891         /* likely incorrect csum if alternate IP extension headers found */
 892         if (ipv6 &&
 893             rx_status & (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
 894                 /* don't increment checksum err here, non-fatal err */
 895                 return;
 896
 897         /* there was some L4 error, count error and punt packet to the stack */
 898         if (rx_error & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT))
 899                 goto checksum_fail;
 900
 901         /* handle packets that were not able to be checksummed due
 902          * to arrival speed, in this case the stack can compute
 903          * the csum.
 904          */
 905         if (rx_error & (1 << I40E_RX_DESC_ERROR_PPRS_SHIFT))
 906                 return;
 907
 908         /* If VXLAN traffic has an outer UDPv4 checksum we need to check
 909          * it in the driver, hardware does not do it for us.
 910          * Since L3L4P bit was set we assume a valid IHL value (>=5)
 911          * so the total length of IPv4 header is IHL*4 bytes
 912          * The UDP_0 bit *may* bet set if the *inner* header is UDP
 913          */
 914         if (ipv4_tunnel) {
 915                 skb->transport_header = skb->mac_header +
 916                                         sizeof(struct ethhdr) +
 917                                         (ip_hdr(skb)->ihl * 4);
 918
 919                 /* Add 4 bytes for VLAN tagged packets */
 920                 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
 921                                           skb->protocol == htons(ETH_P_8021AD))
 922                                           ? VLAN_HLEN : 0;
 923
 924                 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
 925                     (udp_hdr(skb)->check != 0)) {
 926                         rx_udp_csum = udp_csum(skb);
 927                         iph = ip_hdr(skb);
 928                         csum = csum_tcpudp_magic(iph->saddr, iph->daddr,
 929                                                  (skb->len -
 930                                                   skb_transport_offset(skb)),
 931                                                  IPPROTO_UDP, rx_udp_csum);
 932
 933                         if (udp_hdr(skb)->check != csum)
 934                                 goto checksum_fail;
 935
 936                 } /* else its GRE and so no outer UDP header */
 937         }
 938
 939         skb->ip_summed = CHECKSUM_UNNECESSARY;
 940         skb->csum_level = ipv4_tunnel || ipv6_tunnel;
 941
 942         return;
 943
 944 checksum_fail:
 945         vsi->back->hw_csum_rx_error++;
 946 }
 947
 948 /**
 949  * i40e_rx_hash - returns the hash value from the Rx descriptor
 950  * @ring: descriptor ring
 951  * @rx_desc: specific descriptor
 952  **/
 953 static inline u32 i40e_rx_hash(struct i40e_ring *ring,
 954                                union i40e_rx_desc *rx_desc)
 955 {
 956         const __le64 rss_mask =
 957                 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
 958                             I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
 959
 960         if ((ring->netdev->features & NETIF_F_RXHASH) &&
 961             (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
 962                 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
 963         else
 964                 return 0;
 965 }
 966
 967 /**
 968  * i40e_ptype_to_hash - get a hash type
 969  * @ptype: the ptype value from the descriptor
 970  *
 971  * Returns a hash type to be used by skb_set_hash
 972  **/
 973 static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
 974 {
 975         struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
 976
 977         if (!decoded.known)
 978                 return PKT_HASH_TYPE_NONE;
 979
 980         if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 981             decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
 982                 return PKT_HASH_TYPE_L4;
 983         else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 984                  decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
 985                 return PKT_HASH_TYPE_L3;
 986         else
 987                 return PKT_HASH_TYPE_L2;
 988 }
 989
 990 /**
 991  * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
 992  * @rx_ring:  rx ring to clean
 993  * @budget:   how many cleans we're allowed
 994  *
 995  * Returns true if there's any budget left (e.g. the clean is finished)
 996  **/
 997 static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
 998 {
 999         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1000         u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
1001         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1002         const int current_node = numa_node_id();
1003         struct i40e_vsi *vsi = rx_ring->vsi;
1004         u16 i = rx_ring->next_to_clean;
1005         union i40e_rx_desc *rx_desc;
1006         u32 rx_error, rx_status;
1007         u8 rx_ptype;
1008         u64 qword;
1009
1010         do {
1011                 struct i40e_rx_buffer *rx_bi;
1012                 struct sk_buff *skb;
1013                 u16 vlan_tag;
1014                 /* return some buffers to hardware, one at a time is too slow */
1015                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1016                         i40evf_alloc_rx_buffers_ps(rx_ring, cleaned_count);
1017                         cleaned_count = 0;
1018                 }
1019
1020                 i = rx_ring->next_to_clean;
1021                 rx_desc = I40E_RX_DESC(rx_ring, i);
1022                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1023                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1024                         I40E_RXD_QW1_STATUS_SHIFT;
1025
1026                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1027                         break;
1028
1029                 /* This memory barrier is needed to keep us from reading
1030                  * any other fields out of the rx_desc until we know the
1031                  * DD bit is set.
1032                  */
1033                 dma_rmb();
1034                 rx_bi = &rx_ring->rx_bi[i];
1035                 skb = rx_bi->skb;
1036                 if (likely(!skb)) {
1037                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1038                                                         rx_ring->rx_hdr_len);
1039                         if (!skb) {
1040                                 rx_ring->rx_stats.alloc_buff_failed++;
1041                                 break;
1042                         }
1043
1044                         /* initialize queue mapping */
1045                         skb_record_rx_queue(skb, rx_ring->queue_index);
1046                         /* we are reusing so sync this buffer for CPU use */
1047                         dma_sync_single_range_for_cpu(rx_ring->dev,
1048                                                       rx_bi->dma,
1049                                                       0,
1050                                                       rx_ring->rx_hdr_len,
1051                                                       DMA_FROM_DEVICE);
1052                 }
1053                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1054                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1055                 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1056                                 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1057                 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1058                          I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1059
1060                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1061                            I40E_RXD_QW1_ERROR_SHIFT;
1062                 rx_hbo = rx_error & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
1063                 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
1064
1065                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1066                            I40E_RXD_QW1_PTYPE_SHIFT;
1067                 prefetch(rx_bi->page);
1068                 rx_bi->skb = NULL;
1069                 cleaned_count++;
1070                 if (rx_hbo || rx_sph) {
1071                         int len;
1072                         if (rx_hbo)
1073                                 len = I40E_RX_HDR_SIZE;
1074                         else
1075                                 len = rx_header_len;
1076                         memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1077                 } else if (skb->len == 0) {
1078                         int len;
1079
1080                         len = (rx_packet_len > skb_headlen(skb) ?
1081                                 skb_headlen(skb) : rx_packet_len);
1082                         memcpy(__skb_put(skb, len),
1083                                rx_bi->page + rx_bi->page_offset,
1084                                len);
1085                         rx_bi->page_offset += len;
1086                         rx_packet_len -= len;
1087                 }
1088
1089                 /* Get the rest of the data if this was a header split */
1090                 if (rx_packet_len) {
1091                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1092                                            rx_bi->page,
1093                                            rx_bi->page_offset,
1094                                            rx_packet_len);
1095
1096                         skb->len += rx_packet_len;
1097                         skb->data_len += rx_packet_len;
1098                         skb->truesize += rx_packet_len;
1099
1100                         if ((page_count(rx_bi->page) == 1) &&
1101                             (page_to_nid(rx_bi->page) == current_node))
1102                                 get_page(rx_bi->page);
1103                         else
1104                                 rx_bi->page = NULL;
1105
1106                         dma_unmap_page(rx_ring->dev,
1107                                        rx_bi->page_dma,
1108                                        PAGE_SIZE / 2,
1109                                        DMA_FROM_DEVICE);
1110                         rx_bi->page_dma = 0;
1111                 }
1112                 I40E_RX_INCREMENT(rx_ring, i);
1113
1114                 if (unlikely(
1115                     !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1116                         struct i40e_rx_buffer *next_buffer;
1117
1118                         next_buffer = &rx_ring->rx_bi[i];
1119                         next_buffer->skb = skb;
1120                         rx_ring->rx_stats.non_eop_descs++;
1121                         continue;
1122                 }
1123
1124                 /* ERR_MASK will only have valid bits if EOP set */
1125                 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1126                         dev_kfree_skb_any(skb);
1127                         continue;
1128                 }
1129
1130                 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1131                              i40e_ptype_to_hash(rx_ptype));
1132                 /* probably a little skewed due to removing CRC */
1133                 total_rx_bytes += skb->len;
1134                 total_rx_packets++;
1135
1136                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1137
1138                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1139
1140                 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1141                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1142                          : 0;
1143 #ifdef I40E_FCOE
1144                 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1145                         dev_kfree_skb_any(skb);
1146                         continue;
1147                 }
1148 #endif
1149                 skb_mark_napi_id(skb, &rx_ring->q_vector->napi);
1150                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1151
1152                 rx_desc->wb.qword1.status_error_len = 0;
1153
1154         } while (likely(total_rx_packets < budget));
1155
1156         u64_stats_update_begin(&rx_ring->syncp);
1157         rx_ring->stats.packets += total_rx_packets;
1158         rx_ring->stats.bytes += total_rx_bytes;
1159         u64_stats_update_end(&rx_ring->syncp);
1160         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1161         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1162
1163         return total_rx_packets;
1164 }
1165
1166 /**
1167  * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1168  * @rx_ring:  rx ring to clean
1169  * @budget:   how many cleans we're allowed
1170  *
1171  * Returns number of packets cleaned
1172  **/
1173 static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1174 {
1175         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1176         u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1177         struct i40e_vsi *vsi = rx_ring->vsi;
1178         union i40e_rx_desc *rx_desc;
1179         u32 rx_error, rx_status;
1180         u16 rx_packet_len;
1181         u8 rx_ptype;
1182         u64 qword;
1183         u16 i;
1184
1185         do {
1186                 struct i40e_rx_buffer *rx_bi;
1187                 struct sk_buff *skb;
1188                 u16 vlan_tag;
1189                 /* return some buffers to hardware, one at a time is too slow */
1190                 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1191                         i40evf_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
1192                         cleaned_count = 0;
1193                 }
1194
1195                 i = rx_ring->next_to_clean;
1196                 rx_desc = I40E_RX_DESC(rx_ring, i);
1197                 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1198                 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1199                         I40E_RXD_QW1_STATUS_SHIFT;
1200
1201                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1202                         break;
1203
1204                 /* This memory barrier is needed to keep us from reading
1205                  * any other fields out of the rx_desc until we know the
1206                  * DD bit is set.
1207                  */
1208                 dma_rmb();
1209
1210                 rx_bi = &rx_ring->rx_bi[i];
1211                 skb = rx_bi->skb;
1212                 prefetch(skb->data);
1213
1214                 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1215                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1216
1217                 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1218                            I40E_RXD_QW1_ERROR_SHIFT;
1219                 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
1220
1221                 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1222                            I40E_RXD_QW1_PTYPE_SHIFT;
1223                 rx_bi->skb = NULL;
1224                 cleaned_count++;
1225
1226                 /* Get the header and possibly the whole packet
1227                  * If this is an skb from previous receive dma will be 0
1228                  */
1229                 skb_put(skb, rx_packet_len);
1230                 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1231                                  DMA_FROM_DEVICE);
1232                 rx_bi->dma = 0;
1233
1234                 I40E_RX_INCREMENT(rx_ring, i);
1235
1236                 if (unlikely(
1237                     !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1238                         rx_ring->rx_stats.non_eop_descs++;
1239                         continue;
1240                 }
1241
1242                 /* ERR_MASK will only have valid bits if EOP set */
1243                 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1244                         dev_kfree_skb_any(skb);
1245                         /* TODO: shouldn't we increment a counter indicating the
1246                          * drop?
1247                          */
1248                         continue;
1249                 }
1250
1251                 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1252                              i40e_ptype_to_hash(rx_ptype));
1253                 /* probably a little skewed due to removing CRC */
1254                 total_rx_bytes += skb->len;
1255                 total_rx_packets++;
1256
1257                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1258
1259                 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1260
1261                 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1262                          ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1263                          : 0;
1264                 i40e_receive_skb(rx_ring, skb, vlan_tag);
1265
1266                 rx_desc->wb.qword1.status_error_len = 0;
1267         } while (likely(total_rx_packets < budget));
1268
1269         u64_stats_update_begin(&rx_ring->syncp);
1270         rx_ring->stats.packets += total_rx_packets;
1271         rx_ring->stats.bytes += total_rx_bytes;
1272         u64_stats_update_end(&rx_ring->syncp);
1273         rx_ring->q_vector->rx.total_packets += total_rx_packets;
1274         rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1275
1276         return total_rx_packets;
1277 }
1278
1279 /**
1280  * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1281  * @napi: napi struct with our devices info in it
1282  * @budget: amount of work driver is allowed to do this pass, in packets
1283  *
1284  * This function will clean all queues associated with a q_vector.
1285  *
1286  * Returns the amount of work done
1287  **/
1288 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1289 {
1290         struct i40e_q_vector *q_vector =
1291                                container_of(napi, struct i40e_q_vector, napi);
1292         struct i40e_vsi *vsi = q_vector->vsi;
1293         struct i40e_ring *ring;
1294         bool clean_complete = true;
1295         bool arm_wb = false;
1296         int budget_per_ring;
1297         int cleaned;
1298
1299         if (test_bit(__I40E_DOWN, &vsi->state)) {
1300                 napi_complete(napi);
1301                 return 0;
1302         }
1303
1304         /* Since the actual Tx work is minimal, we can give the Tx a larger
1305          * budget and be more aggressive about cleaning up the Tx descriptors.
1306          */
1307         i40e_for_each_ring(ring, q_vector->tx) {
1308                 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1309                 arm_wb |= ring->arm_wb;
1310         }
1311
1312         /* We attempt to distribute budget to each Rx queue fairly, but don't
1313          * allow the budget to go below 1 because that would exit polling early.
1314          */
1315         budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1316
1317         i40e_for_each_ring(ring, q_vector->rx) {
1318                 if (ring_is_ps_enabled(ring))
1319                         cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1320                 else
1321                         cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1322                 /* if we didn't clean as many as budgeted, we must be done */
1323                 clean_complete &= (budget_per_ring != cleaned);
1324         }
1325
1326         /* If work not completed, return budget and polling will return */
1327         if (!clean_complete) {
1328                 if (arm_wb)
1329                         i40e_force_wb(vsi, q_vector);
1330                 return budget;
1331         }
1332
1333         /* Work is done so exit the polling mode and re-enable the interrupt */
1334         napi_complete(napi);
1335         if (ITR_IS_DYNAMIC(vsi->rx_itr_setting) ||
1336             ITR_IS_DYNAMIC(vsi->tx_itr_setting))
1337                 i40e_update_dynamic_itr(q_vector);
1338
1339         if (!test_bit(__I40E_DOWN, &vsi->state))
1340                 i40evf_irq_enable_queues(vsi->back, 1 << q_vector->v_idx);
1341
1342         return 0;
1343 }
1344
1345 /**
1346  * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1347  * @skb:     send buffer
1348  * @tx_ring: ring to send buffer on
1349  * @flags:   the tx flags to be set
1350  *
1351  * Checks the skb and set up correspondingly several generic transmit flags
1352  * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1353  *
1354  * Returns error code indicate the frame should be dropped upon error and the
1355  * otherwise  returns 0 to indicate the flags has been set properly.
1356  **/
1357 static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1358                                                struct i40e_ring *tx_ring,
1359                                                u32 *flags)
1360 {
1361         __be16 protocol = skb->protocol;
1362         u32  tx_flags = 0;
1363
1364         if (protocol == htons(ETH_P_8021Q) &&
1365             !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1366                 /* When HW VLAN acceleration is turned off by the user the
1367                  * stack sets the protocol to 8021q so that the driver
1368                  * can take any steps required to support the SW only
1369                  * VLAN handling.  In our case the driver doesn't need
1370                  * to take any further steps so just set the protocol
1371                  * to the encapsulated ethertype.
1372                  */
1373                 skb->protocol = vlan_get_protocol(skb);
1374                 goto out;
1375         }
1376
1377         /* if we have a HW VLAN tag being added, default to the HW one */
1378         if (skb_vlan_tag_present(skb)) {
1379                 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1380                 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1381         /* else if it is a SW VLAN, check the next protocol and store the tag */
1382         } else if (protocol == htons(ETH_P_8021Q)) {
1383                 struct vlan_hdr *vhdr, _vhdr;
1384                 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1385                 if (!vhdr)
1386                         return -EINVAL;
1387
1388                 protocol = vhdr->h_vlan_encapsulated_proto;
1389                 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1390                 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1391         }
1392
1393 out:
1394         *flags = tx_flags;
1395         return 0;
1396 }
1397
1398 /**
1399  * i40e_tso - set up the tso context descriptor
1400  * @tx_ring:  ptr to the ring to send
1401  * @skb:      ptr to the skb we're sending
1402  * @hdr_len:  ptr to the size of the packet header
1403  * @cd_tunneling: ptr to context descriptor bits
1404  *
1405  * Returns 0 if no TSO can happen, 1 if tso is going, or error
1406  **/
1407 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1408                     u8 *hdr_len, u64 *cd_type_cmd_tso_mss,
1409                     u32 *cd_tunneling)
1410 {
1411         u32 cd_cmd, cd_tso_len, cd_mss;
1412         struct ipv6hdr *ipv6h;
1413         struct tcphdr *tcph;
1414         struct iphdr *iph;
1415         u32 l4len;
1416         int err;
1417
1418         if (!skb_is_gso(skb))
1419                 return 0;
1420
1421         err = skb_cow_head(skb, 0);
1422         if (err < 0)
1423                 return err;
1424
1425         iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1426         ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1427
1428         if (iph->version == 4) {
1429                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1430                 iph->tot_len = 0;
1431                 iph->check = 0;
1432                 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1433                                                  0, IPPROTO_TCP, 0);
1434         } else if (ipv6h->version == 6) {
1435                 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1436                 ipv6h->payload_len = 0;
1437                 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1438                                                0, IPPROTO_TCP, 0);
1439         }
1440
1441         l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1442         *hdr_len = (skb->encapsulation
1443                     ? (skb_inner_transport_header(skb) - skb->data)
1444                     : skb_transport_offset(skb)) + l4len;
1445
1446         /* find the field values */
1447         cd_cmd = I40E_TX_CTX_DESC_TSO;
1448         cd_tso_len = skb->len - *hdr_len;
1449         cd_mss = skb_shinfo(skb)->gso_size;
1450         *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1451                                 ((u64)cd_tso_len <<
1452                                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1453                                 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1454         return 1;
1455 }
1456
1457 /**
1458  * i40e_tx_enable_csum - Enable Tx checksum offloads
1459  * @skb: send buffer
1460  * @tx_flags: pointer to Tx flags currently set
1461  * @td_cmd: Tx descriptor command bits to set
1462  * @td_offset: Tx descriptor header offsets to set
1463  * @cd_tunneling: ptr to context desc bits
1464  **/
1465 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1466                                 u32 *td_cmd, u32 *td_offset,
1467                                 struct i40e_ring *tx_ring,
1468                                 u32 *cd_tunneling)
1469 {
1470         struct ipv6hdr *this_ipv6_hdr;
1471         unsigned int this_tcp_hdrlen;
1472         struct iphdr *this_ip_hdr;
1473         u32 network_hdr_len;
1474         u8 l4_hdr = 0;
1475         u32 l4_tunnel = 0;
1476
1477         if (skb->encapsulation) {
1478                 switch (ip_hdr(skb)->protocol) {
1479                 case IPPROTO_UDP:
1480                         l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
1481                         *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1482                         break;
1483                 default:
1484                         return;
1485                 }
1486                 network_hdr_len = skb_inner_network_header_len(skb);
1487                 this_ip_hdr = inner_ip_hdr(skb);
1488                 this_ipv6_hdr = inner_ipv6_hdr(skb);
1489                 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1490
1491                 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1492                         if (*tx_flags & I40E_TX_FLAGS_TSO) {
1493                                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1494                                 ip_hdr(skb)->check = 0;
1495                         } else {
1496                                 *cd_tunneling |=
1497                                          I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1498                         }
1499                 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1500                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1501                         if (*tx_flags & I40E_TX_FLAGS_TSO)
1502                                 ip_hdr(skb)->check = 0;
1503                 }
1504
1505                 /* Now set the ctx descriptor fields */
1506                 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1507                                    I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT      |
1508                                    l4_tunnel                             |
1509                                    ((skb_inner_network_offset(skb) -
1510                                         skb_transport_offset(skb)) >> 1) <<
1511                                    I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1512                 if (this_ip_hdr->version == 6) {
1513                         *tx_flags &= ~I40E_TX_FLAGS_IPV4;
1514                         *tx_flags |= I40E_TX_FLAGS_IPV6;
1515                 }
1516
1517
1518         } else {
1519                 network_hdr_len = skb_network_header_len(skb);
1520                 this_ip_hdr = ip_hdr(skb);
1521                 this_ipv6_hdr = ipv6_hdr(skb);
1522                 this_tcp_hdrlen = tcp_hdrlen(skb);
1523         }
1524
1525         /* Enable IP checksum offloads */
1526         if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1527                 l4_hdr = this_ip_hdr->protocol;
1528                 /* the stack computes the IP header already, the only time we
1529                  * need the hardware to recompute it is in the case of TSO.
1530                  */
1531                 if (*tx_flags & I40E_TX_FLAGS_TSO) {
1532                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1533                         this_ip_hdr->check = 0;
1534                 } else {
1535                         *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1536                 }
1537                 /* Now set the td_offset for IP header length */
1538                 *td_offset = (network_hdr_len >> 2) <<
1539                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1540         } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1541                 l4_hdr = this_ipv6_hdr->nexthdr;
1542                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1543                 /* Now set the td_offset for IP header length */
1544                 *td_offset = (network_hdr_len >> 2) <<
1545                               I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1546         }
1547         /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1548         *td_offset |= (skb_network_offset(skb) >> 1) <<
1549                        I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1550
1551         /* Enable L4 checksum offloads */
1552         switch (l4_hdr) {
1553         case IPPROTO_TCP:
1554                 /* enable checksum offloads */
1555                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1556                 *td_offset |= (this_tcp_hdrlen >> 2) <<
1557                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1558                 break;
1559         case IPPROTO_SCTP:
1560                 /* enable SCTP checksum offload */
1561                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1562                 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1563                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1564                 break;
1565         case IPPROTO_UDP:
1566                 /* enable UDP checksum offload */
1567                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1568                 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1569                                I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1570                 break;
1571         default:
1572                 break;
1573         }
1574 }
1575
1576 /**
1577  * i40e_create_tx_ctx Build the Tx context descriptor
1578  * @tx_ring:  ring to create the descriptor on
1579  * @cd_type_cmd_tso_mss: Quad Word 1
1580  * @cd_tunneling: Quad Word 0 - bits 0-31
1581  * @cd_l2tag2: Quad Word 0 - bits 32-63
1582  **/
1583 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1584                                const u64 cd_type_cmd_tso_mss,
1585                                const u32 cd_tunneling, const u32 cd_l2tag2)
1586 {
1587         struct i40e_tx_context_desc *context_desc;
1588         int i = tx_ring->next_to_use;
1589
1590         if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1591             !cd_tunneling && !cd_l2tag2)
1592                 return;
1593
1594         /* grab the next descriptor */
1595         context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1596
1597         i++;
1598         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1599
1600         /* cpu_to_le32 and assign to struct fields */
1601         context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1602         context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1603         context_desc->rsvd = cpu_to_le16(0);
1604         context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1605 }
1606
1607  /**
1608  * i40e_chk_linearize - Check if there are more than 8 fragments per packet
1609  * @skb:      send buffer
1610  * @tx_flags: collected send information
1611  *
1612  * Note: Our HW can't scatter-gather more than 8 fragments to build
1613  * a packet on the wire and so we need to figure out the cases where we
1614  * need to linearize the skb.
1615  **/
1616 static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
1617 {
1618         struct skb_frag_struct *frag;
1619         bool linearize = false;
1620         unsigned int size = 0;
1621         u16 num_frags;
1622         u16 gso_segs;
1623
1624         num_frags = skb_shinfo(skb)->nr_frags;
1625         gso_segs = skb_shinfo(skb)->gso_segs;
1626
1627         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
1628                 u16 j = 0;
1629
1630                 if (num_frags < (I40E_MAX_BUFFER_TXD))
1631                         goto linearize_chk_done;
1632                 /* try the simple math, if we have too many frags per segment */
1633                 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
1634                     I40E_MAX_BUFFER_TXD) {
1635                         linearize = true;
1636                         goto linearize_chk_done;
1637                 }
1638                 frag = &skb_shinfo(skb)->frags[0];
1639                 /* we might still have more fragments per segment */
1640                 do {
1641                         size += skb_frag_size(frag);
1642                         frag++; j++;
1643                         if ((size >= skb_shinfo(skb)->gso_size) &&
1644                             (j < I40E_MAX_BUFFER_TXD)) {
1645                                 size = (size % skb_shinfo(skb)->gso_size);
1646                                 j = (size) ? 1 : 0;
1647                         }
1648                         if (j == I40E_MAX_BUFFER_TXD) {
1649                                 linearize = true;
1650                                 break;
1651                         }
1652                         num_frags--;
1653                 } while (num_frags);
1654         } else {
1655                 if (num_frags >= I40E_MAX_BUFFER_TXD)
1656                         linearize = true;
1657         }
1658
1659 linearize_chk_done:
1660         return linearize;
1661 }
1662
1663 /**
1664  * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1665  * @tx_ring: the ring to be checked
1666  * @size:    the size buffer we want to assure is available
1667  *
1668  * Returns -EBUSY if a stop is needed, else 0
1669  **/
1670 static inline int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1671 {
1672         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1673         /* Memory barrier before checking head and tail */
1674         smp_mb();
1675
1676         /* Check again in a case another CPU has just made room available. */
1677         if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1678                 return -EBUSY;
1679
1680         /* A reprieve! - use start_queue because it doesn't call schedule */
1681         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1682         ++tx_ring->tx_stats.restart_queue;
1683         return 0;
1684 }
1685
1686 /**
1687  * i40evf_maybe_stop_tx - 1st level check for tx stop conditions
1688  * @tx_ring: the ring to be checked
1689  * @size:    the size buffer we want to assure is available
1690  *
1691  * Returns 0 if stop is not needed
1692  **/
1693 static inline int i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1694 {
1695         if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1696                 return 0;
1697         return __i40evf_maybe_stop_tx(tx_ring, size);
1698 }
1699
1700 /**
1701  * i40evf_tx_map - Build the Tx descriptor
1702  * @tx_ring:  ring to send buffer on
1703  * @skb:      send buffer
1704  * @first:    first buffer info buffer to use
1705  * @tx_flags: collected send information
1706  * @hdr_len:  size of the packet header
1707  * @td_cmd:   the command field in the descriptor
1708  * @td_offset: offset for checksum or crc
1709  **/
1710 static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1711                                  struct i40e_tx_buffer *first, u32 tx_flags,
1712                                  const u8 hdr_len, u32 td_cmd, u32 td_offset)
1713 {
1714         unsigned int data_len = skb->data_len;
1715         unsigned int size = skb_headlen(skb);
1716         struct skb_frag_struct *frag;
1717         struct i40e_tx_buffer *tx_bi;
1718         struct i40e_tx_desc *tx_desc;
1719         u16 i = tx_ring->next_to_use;
1720         u32 td_tag = 0;
1721         dma_addr_t dma;
1722         u16 gso_segs;
1723
1724         if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1725                 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1726                 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1727                          I40E_TX_FLAGS_VLAN_SHIFT;
1728         }
1729
1730         if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1731                 gso_segs = skb_shinfo(skb)->gso_segs;
1732         else
1733                 gso_segs = 1;
1734
1735         /* multiply data chunks by size of headers */
1736         first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1737         first->gso_segs = gso_segs;
1738         first->skb = skb;
1739         first->tx_flags = tx_flags;
1740
1741         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1742
1743         tx_desc = I40E_TX_DESC(tx_ring, i);
1744         tx_bi = first;
1745
1746         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1747                 if (dma_mapping_error(tx_ring->dev, dma))
1748                         goto dma_error;
1749
1750                 /* record length, and DMA address */
1751                 dma_unmap_len_set(tx_bi, len, size);
1752                 dma_unmap_addr_set(tx_bi, dma, dma);
1753
1754                 tx_desc->buffer_addr = cpu_to_le64(dma);
1755
1756                 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1757                         tx_desc->cmd_type_offset_bsz =
1758                                 build_ctob(td_cmd, td_offset,
1759                                            I40E_MAX_DATA_PER_TXD, td_tag);
1760
1761                         tx_desc++;
1762                         i++;
1763                         if (i == tx_ring->count) {
1764                                 tx_desc = I40E_TX_DESC(tx_ring, 0);
1765                                 i = 0;
1766                         }
1767
1768                         dma += I40E_MAX_DATA_PER_TXD;
1769                         size -= I40E_MAX_DATA_PER_TXD;
1770
1771                         tx_desc->buffer_addr = cpu_to_le64(dma);
1772                 }
1773
1774                 if (likely(!data_len))
1775                         break;
1776
1777                 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1778                                                           size, td_tag);
1779
1780                 tx_desc++;
1781                 i++;
1782                 if (i == tx_ring->count) {
1783                         tx_desc = I40E_TX_DESC(tx_ring, 0);
1784                         i = 0;
1785                 }
1786
1787                 size = skb_frag_size(frag);
1788                 data_len -= size;
1789
1790                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1791                                        DMA_TO_DEVICE);
1792
1793                 tx_bi = &tx_ring->tx_bi[i];
1794         }
1795
1796         /* Place RS bit on last descriptor of any packet that spans across the
1797          * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
1798          */
1799 #define WB_STRIDE 0x3
1800         if (((i & WB_STRIDE) != WB_STRIDE) &&
1801             (first <= &tx_ring->tx_bi[i]) &&
1802             (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
1803                 tx_desc->cmd_type_offset_bsz =
1804                         build_ctob(td_cmd, td_offset, size, td_tag) |
1805                         cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
1806                                          I40E_TXD_QW1_CMD_SHIFT);
1807         } else {
1808                 tx_desc->cmd_type_offset_bsz =
1809                         build_ctob(td_cmd, td_offset, size, td_tag) |
1810                         cpu_to_le64((u64)I40E_TXD_CMD <<
1811                                          I40E_TXD_QW1_CMD_SHIFT);
1812         }
1813
1814         netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1815                                                  tx_ring->queue_index),
1816                              first->bytecount);
1817
1818         /* Force memory writes to complete before letting h/w
1819          * know there are new descriptors to fetch.  (Only
1820          * applicable for weak-ordered memory model archs,
1821          * such as IA-64).
1822          */
1823         wmb();
1824
1825         /* set next_to_watch value indicating a packet is present */
1826         first->next_to_watch = tx_desc;
1827
1828         i++;
1829         if (i == tx_ring->count)
1830                 i = 0;
1831
1832         tx_ring->next_to_use = i;
1833
1834         i40evf_maybe_stop_tx(tx_ring, DESC_NEEDED);
1835         /* notify HW of packet */
1836         if (!skb->xmit_more ||
1837             netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
1838                                                    tx_ring->queue_index)))
1839                 writel(i, tx_ring->tail);
1840
1841         return;
1842
1843 dma_error:
1844         dev_info(tx_ring->dev, "TX DMA map failed\n");
1845
1846         /* clear dma mappings for failed tx_bi map */
1847         for (;;) {
1848                 tx_bi = &tx_ring->tx_bi[i];
1849                 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1850                 if (tx_bi == first)
1851                         break;
1852                 if (i == 0)
1853                         i = tx_ring->count;
1854                 i--;
1855         }
1856
1857         tx_ring->next_to_use = i;
1858 }
1859
1860 /**
1861  * i40evf_xmit_descriptor_count - calculate number of tx descriptors needed
1862  * @skb:     send buffer
1863  * @tx_ring: ring to send buffer on
1864  *
1865  * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1866  * there is not enough descriptors available in this ring since we need at least
1867  * one descriptor.
1868  **/
1869 static inline int i40evf_xmit_descriptor_count(struct sk_buff *skb,
1870                                                struct i40e_ring *tx_ring)
1871 {
1872         unsigned int f;
1873         int count = 0;
1874
1875         /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1876          *       + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1877          *       + 4 desc gap to avoid the cache line where head is,
1878          *       + 1 desc for context descriptor,
1879          * otherwise try next time
1880          */
1881         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1882                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1883
1884         count += TXD_USE_COUNT(skb_headlen(skb));
1885         if (i40evf_maybe_stop_tx(tx_ring, count + 4 + 1)) {
1886                 tx_ring->tx_stats.tx_busy++;
1887                 return 0;
1888         }
1889         return count;
1890 }
1891
1892 /**
1893  * i40e_xmit_frame_ring - Sends buffer on Tx ring
1894  * @skb:     send buffer
1895  * @tx_ring: ring to send buffer on
1896  *
1897  * Returns NETDEV_TX_OK if sent, else an error code
1898  **/
1899 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1900                                         struct i40e_ring *tx_ring)
1901 {
1902         u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1903         u32 cd_tunneling = 0, cd_l2tag2 = 0;
1904         struct i40e_tx_buffer *first;
1905         u32 td_offset = 0;
1906         u32 tx_flags = 0;
1907         __be16 protocol;
1908         u32 td_cmd = 0;
1909         u8 hdr_len = 0;
1910         int tso;
1911         if (0 == i40evf_xmit_descriptor_count(skb, tx_ring))
1912                 return NETDEV_TX_BUSY;
1913
1914         /* prepare the xmit flags */
1915         if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
1916                 goto out_drop;
1917
1918         /* obtain protocol of skb */
1919         protocol = vlan_get_protocol(skb);
1920
1921         /* record the location of the first descriptor for this packet */
1922         first = &tx_ring->tx_bi[tx_ring->next_to_use];
1923
1924         /* setup IPv4/IPv6 offloads */
1925         if (protocol == htons(ETH_P_IP))
1926                 tx_flags |= I40E_TX_FLAGS_IPV4;
1927         else if (protocol == htons(ETH_P_IPV6))
1928                 tx_flags |= I40E_TX_FLAGS_IPV6;
1929
1930         tso = i40e_tso(tx_ring, skb, &hdr_len,
1931                        &cd_type_cmd_tso_mss, &cd_tunneling);
1932
1933         if (tso < 0)
1934                 goto out_drop;
1935         else if (tso)
1936                 tx_flags |= I40E_TX_FLAGS_TSO;
1937
1938         if (i40e_chk_linearize(skb, tx_flags))
1939                 if (skb_linearize(skb))
1940                         goto out_drop;
1941
1942         skb_tx_timestamp(skb);
1943
1944         /* always enable CRC insertion offload */
1945         td_cmd |= I40E_TX_DESC_CMD_ICRC;
1946
1947         /* Always offload the checksum, since it's in the data descriptor */
1948         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1949                 tx_flags |= I40E_TX_FLAGS_CSUM;
1950
1951                 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
1952                                     tx_ring, &cd_tunneling);
1953         }
1954
1955         i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
1956                            cd_tunneling, cd_l2tag2);
1957
1958         i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
1959                       td_cmd, td_offset);
1960
1961         return NETDEV_TX_OK;
1962
1963 out_drop:
1964         dev_kfree_skb_any(skb);
1965         return NETDEV_TX_OK;
1966 }
1967
1968 /**
1969  * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1970  * @skb:    send buffer
1971  * @netdev: network interface device structure
1972  *
1973  * Returns NETDEV_TX_OK if sent, else an error code
1974  **/
1975 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1976 {
1977         struct i40evf_adapter *adapter = netdev_priv(netdev);
1978         struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
1979
1980         /* hardware can't handle really short frames, hardware padding works
1981          * beyond this point
1982          */
1983         if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
1984                 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
1985                         return NETDEV_TX_OK;
1986                 skb->len = I40E_MIN_TX_LEN;
1987                 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
1988         }
1989
1990         return i40e_xmit_frame_ring(skb, tx_ring);
1991 }