1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2016 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include <linux/prefetch.h>
28 #include <net/busy_poll.h>
31 #include "i40e_prototype.h"
33 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
36 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
37 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
38 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
39 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
40 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
46 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
47 * @ring: the ring that owns the buffer
48 * @tx_buffer: the buffer to free
50 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
51 struct i40e_tx_buffer *tx_buffer)
54 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
55 kfree(tx_buffer->raw_buf);
57 dev_kfree_skb_any(tx_buffer->skb);
58 if (dma_unmap_len(tx_buffer, len))
59 dma_unmap_single(ring->dev,
60 dma_unmap_addr(tx_buffer, dma),
61 dma_unmap_len(tx_buffer, len),
63 } else if (dma_unmap_len(tx_buffer, len)) {
64 dma_unmap_page(ring->dev,
65 dma_unmap_addr(tx_buffer, dma),
66 dma_unmap_len(tx_buffer, len),
70 tx_buffer->next_to_watch = NULL;
71 tx_buffer->skb = NULL;
72 dma_unmap_len_set(tx_buffer, len, 0);
73 /* tx_buffer must be completely set up in the transmit path */
77 * i40evf_clean_tx_ring - Free any empty Tx buffers
78 * @tx_ring: ring to be cleaned
80 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
82 unsigned long bi_size;
85 /* ring already cleared, nothing to do */
89 /* Free all the Tx ring sk_buffs */
90 for (i = 0; i < tx_ring->count; i++)
91 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
93 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
94 memset(tx_ring->tx_bi, 0, bi_size);
96 /* Zero out the descriptor ring */
97 memset(tx_ring->desc, 0, tx_ring->size);
99 tx_ring->next_to_use = 0;
100 tx_ring->next_to_clean = 0;
102 if (!tx_ring->netdev)
105 /* cleanup Tx queue statistics */
106 netdev_tx_reset_queue(txring_txq(tx_ring));
110 * i40evf_free_tx_resources - Free Tx resources per queue
111 * @tx_ring: Tx descriptor ring for a specific queue
113 * Free all transmit software resources
115 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
117 i40evf_clean_tx_ring(tx_ring);
118 kfree(tx_ring->tx_bi);
119 tx_ring->tx_bi = NULL;
122 dma_free_coherent(tx_ring->dev, tx_ring->size,
123 tx_ring->desc, tx_ring->dma);
124 tx_ring->desc = NULL;
129 * i40evf_get_tx_pending - how many Tx descriptors not processed
130 * @tx_ring: the ring of descriptors
131 * @in_sw: is tx_pending being checked in SW or HW
133 * Since there is no access to the ring head register
134 * in XL710, we need to use our local copies
136 u32 i40evf_get_tx_pending(struct i40e_ring *ring, bool in_sw)
141 head = i40e_get_head(ring);
143 head = ring->next_to_clean;
144 tail = readl(ring->tail);
147 return (head < tail) ?
148 tail - head : (tail + ring->count - head);
153 #define WB_STRIDE 0x3
156 * i40e_clean_tx_irq - Reclaim resources after transmit completes
157 * @vsi: the VSI we care about
158 * @tx_ring: Tx ring to clean
159 * @napi_budget: Used to determine if we are in netpoll
161 * Returns true if there's any budget left (e.g. the clean is finished)
163 static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,
164 struct i40e_ring *tx_ring, int napi_budget)
166 u16 i = tx_ring->next_to_clean;
167 struct i40e_tx_buffer *tx_buf;
168 struct i40e_tx_desc *tx_head;
169 struct i40e_tx_desc *tx_desc;
170 unsigned int total_bytes = 0, total_packets = 0;
171 unsigned int budget = vsi->work_limit;
173 tx_buf = &tx_ring->tx_bi[i];
174 tx_desc = I40E_TX_DESC(tx_ring, i);
177 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
180 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
182 /* if next_to_watch is not set then there is no work pending */
186 /* prevent any other reads prior to eop_desc */
187 read_barrier_depends();
189 /* we have caught up to head, no work left to do */
190 if (tx_head == tx_desc)
193 /* clear next_to_watch to prevent false hangs */
194 tx_buf->next_to_watch = NULL;
196 /* update the statistics for this packet */
197 total_bytes += tx_buf->bytecount;
198 total_packets += tx_buf->gso_segs;
201 napi_consume_skb(tx_buf->skb, napi_budget);
203 /* unmap skb header data */
204 dma_unmap_single(tx_ring->dev,
205 dma_unmap_addr(tx_buf, dma),
206 dma_unmap_len(tx_buf, len),
209 /* clear tx_buffer data */
211 dma_unmap_len_set(tx_buf, len, 0);
213 /* unmap remaining buffers */
214 while (tx_desc != eop_desc) {
221 tx_buf = tx_ring->tx_bi;
222 tx_desc = I40E_TX_DESC(tx_ring, 0);
225 /* unmap any remaining paged data */
226 if (dma_unmap_len(tx_buf, len)) {
227 dma_unmap_page(tx_ring->dev,
228 dma_unmap_addr(tx_buf, dma),
229 dma_unmap_len(tx_buf, len),
231 dma_unmap_len_set(tx_buf, len, 0);
235 /* move us one more past the eop_desc for start of next pkt */
241 tx_buf = tx_ring->tx_bi;
242 tx_desc = I40E_TX_DESC(tx_ring, 0);
247 /* update budget accounting */
249 } while (likely(budget));
252 tx_ring->next_to_clean = i;
253 u64_stats_update_begin(&tx_ring->syncp);
254 tx_ring->stats.bytes += total_bytes;
255 tx_ring->stats.packets += total_packets;
256 u64_stats_update_end(&tx_ring->syncp);
257 tx_ring->q_vector->tx.total_bytes += total_bytes;
258 tx_ring->q_vector->tx.total_packets += total_packets;
260 if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
261 /* check to see if there are < 4 descriptors
262 * waiting to be written back, then kick the hardware to force
263 * them to be written back in case we stay in NAPI.
264 * In this mode on X722 we do not enable Interrupt.
266 unsigned int j = i40evf_get_tx_pending(tx_ring, false);
269 ((j / (WB_STRIDE + 1)) == 0) && (j > 0) &&
270 !test_bit(__I40E_DOWN, &vsi->state) &&
271 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
272 tx_ring->arm_wb = true;
275 /* notify netdev of completed buffers */
276 netdev_tx_completed_queue(txring_txq(tx_ring),
277 total_packets, total_bytes);
279 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
280 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
281 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
282 /* Make sure that anybody stopping the queue after this
283 * sees the new next_to_clean.
286 if (__netif_subqueue_stopped(tx_ring->netdev,
287 tx_ring->queue_index) &&
288 !test_bit(__I40E_DOWN, &vsi->state)) {
289 netif_wake_subqueue(tx_ring->netdev,
290 tx_ring->queue_index);
291 ++tx_ring->tx_stats.restart_queue;
299 * i40evf_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
300 * @vsi: the VSI we care about
301 * @q_vector: the vector on which to enable writeback
304 static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
305 struct i40e_q_vector *q_vector)
307 u16 flags = q_vector->tx.ring[0].flags;
310 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
313 if (q_vector->arm_wb_state)
316 val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK |
317 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */
320 I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
321 vsi->base_vector - 1), val);
322 q_vector->arm_wb_state = true;
326 * i40evf_force_wb - Issue SW Interrupt so HW does a wb
327 * @vsi: the VSI we care about
328 * @q_vector: the vector on which to force writeback
331 void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
333 u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
334 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
335 I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
336 I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK
337 /* allow 00 to be written to the index */;
340 I40E_VFINT_DYN_CTLN1(q_vector->v_idx + vsi->base_vector - 1),
345 * i40e_set_new_dynamic_itr - Find new ITR level
346 * @rc: structure containing ring performance data
348 * Returns true if ITR changed, false if not
350 * Stores a new ITR value based on packets and byte counts during
351 * the last interrupt. The advantage of per interrupt computation
352 * is faster updates and more accurate ITR for the current traffic
353 * pattern. Constants in this function were computed based on
354 * theoretical maximum wire speed and thresholds were set based on
355 * testing data as well as attempting to minimize response time
356 * while increasing bulk throughput.
358 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
360 enum i40e_latency_range new_latency_range = rc->latency_range;
361 struct i40e_q_vector *qv = rc->ring->q_vector;
362 u32 new_itr = rc->itr;
366 if (rc->total_packets == 0 || !rc->itr)
369 /* simple throttlerate management
370 * 0-10MB/s lowest (50000 ints/s)
371 * 10-20MB/s low (20000 ints/s)
372 * 20-1249MB/s bulk (18000 ints/s)
373 * > 40000 Rx packets per second (8000 ints/s)
375 * The math works out because the divisor is in 10^(-6) which
376 * turns the bytes/us input value into MB/s values, but
377 * make sure to use usecs, as the register values written
378 * are in 2 usec increments in the ITR registers, and make sure
379 * to use the smoothed values that the countdown timer gives us.
381 usecs = (rc->itr << 1) * ITR_COUNTDOWN_START;
382 bytes_per_int = rc->total_bytes / usecs;
384 switch (new_latency_range) {
385 case I40E_LOWEST_LATENCY:
386 if (bytes_per_int > 10)
387 new_latency_range = I40E_LOW_LATENCY;
389 case I40E_LOW_LATENCY:
390 if (bytes_per_int > 20)
391 new_latency_range = I40E_BULK_LATENCY;
392 else if (bytes_per_int <= 10)
393 new_latency_range = I40E_LOWEST_LATENCY;
395 case I40E_BULK_LATENCY:
396 case I40E_ULTRA_LATENCY:
398 if (bytes_per_int <= 20)
399 new_latency_range = I40E_LOW_LATENCY;
403 /* this is to adjust RX more aggressively when streaming small
404 * packets. The value of 40000 was picked as it is just beyond
405 * what the hardware can receive per second if in low latency
408 #define RX_ULTRA_PACKET_RATE 40000
410 if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) &&
412 new_latency_range = I40E_ULTRA_LATENCY;
414 rc->latency_range = new_latency_range;
416 switch (new_latency_range) {
417 case I40E_LOWEST_LATENCY:
418 new_itr = I40E_ITR_50K;
420 case I40E_LOW_LATENCY:
421 new_itr = I40E_ITR_20K;
423 case I40E_BULK_LATENCY:
424 new_itr = I40E_ITR_18K;
426 case I40E_ULTRA_LATENCY:
427 new_itr = I40E_ITR_8K;
434 rc->total_packets = 0;
436 if (new_itr != rc->itr) {
445 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
446 * @tx_ring: the tx ring to set up
448 * Return 0 on success, negative on error
450 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
452 struct device *dev = tx_ring->dev;
458 /* warn if we are about to overwrite the pointer */
459 WARN_ON(tx_ring->tx_bi);
460 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
461 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
465 /* round up to nearest 4K */
466 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
467 /* add u32 for head writeback, align after this takes care of
468 * guaranteeing this is at least one cache line in size
470 tx_ring->size += sizeof(u32);
471 tx_ring->size = ALIGN(tx_ring->size, 4096);
472 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
473 &tx_ring->dma, GFP_KERNEL);
474 if (!tx_ring->desc) {
475 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
480 tx_ring->next_to_use = 0;
481 tx_ring->next_to_clean = 0;
485 kfree(tx_ring->tx_bi);
486 tx_ring->tx_bi = NULL;
491 * i40evf_clean_rx_ring - Free Rx buffers
492 * @rx_ring: ring to be cleaned
494 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
496 struct device *dev = rx_ring->dev;
497 unsigned long bi_size;
500 /* ring already cleared, nothing to do */
504 /* Free all the Rx ring sk_buffs */
505 for (i = 0; i < rx_ring->count; i++) {
506 struct i40e_rx_buffer *rx_bi = &rx_ring->rx_bi[i];
509 dev_kfree_skb(rx_bi->skb);
515 dma_unmap_page(dev, rx_bi->dma, PAGE_SIZE, DMA_FROM_DEVICE);
516 __free_pages(rx_bi->page, 0);
519 rx_bi->page_offset = 0;
522 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
523 memset(rx_ring->rx_bi, 0, bi_size);
525 /* Zero out the descriptor ring */
526 memset(rx_ring->desc, 0, rx_ring->size);
528 rx_ring->next_to_alloc = 0;
529 rx_ring->next_to_clean = 0;
530 rx_ring->next_to_use = 0;
534 * i40evf_free_rx_resources - Free Rx resources
535 * @rx_ring: ring to clean the resources from
537 * Free all receive software resources
539 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
541 i40evf_clean_rx_ring(rx_ring);
542 kfree(rx_ring->rx_bi);
543 rx_ring->rx_bi = NULL;
546 dma_free_coherent(rx_ring->dev, rx_ring->size,
547 rx_ring->desc, rx_ring->dma);
548 rx_ring->desc = NULL;
553 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
554 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
556 * Returns 0 on success, negative on failure
558 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
560 struct device *dev = rx_ring->dev;
563 /* warn if we are about to overwrite the pointer */
564 WARN_ON(rx_ring->rx_bi);
565 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
566 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
570 u64_stats_init(&rx_ring->syncp);
572 /* Round up to nearest 4K */
573 rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc);
574 rx_ring->size = ALIGN(rx_ring->size, 4096);
575 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
576 &rx_ring->dma, GFP_KERNEL);
578 if (!rx_ring->desc) {
579 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
584 rx_ring->next_to_alloc = 0;
585 rx_ring->next_to_clean = 0;
586 rx_ring->next_to_use = 0;
590 kfree(rx_ring->rx_bi);
591 rx_ring->rx_bi = NULL;
596 * i40e_release_rx_desc - Store the new tail and head values
597 * @rx_ring: ring to bump
598 * @val: new head index
600 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
602 rx_ring->next_to_use = val;
604 /* update next to alloc since we have filled the ring */
605 rx_ring->next_to_alloc = val;
607 /* Force memory writes to complete before letting h/w
608 * know there are new descriptors to fetch. (Only
609 * applicable for weak-ordered memory model archs,
613 writel(val, rx_ring->tail);
617 * i40e_alloc_mapped_page - recycle or make a new page
618 * @rx_ring: ring to use
619 * @bi: rx_buffer struct to modify
621 * Returns true if the page was successfully allocated or
624 static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring,
625 struct i40e_rx_buffer *bi)
627 struct page *page = bi->page;
630 /* since we are recycling buffers we should seldom need to alloc */
632 rx_ring->rx_stats.page_reuse_count++;
636 /* alloc new page for storage */
637 page = dev_alloc_page();
638 if (unlikely(!page)) {
639 rx_ring->rx_stats.alloc_page_failed++;
643 /* map page for use */
644 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
646 /* if mapping failed free memory back to system since
647 * there isn't much point in holding memory we can't use
649 if (dma_mapping_error(rx_ring->dev, dma)) {
650 __free_pages(page, 0);
651 rx_ring->rx_stats.alloc_page_failed++;
663 * i40e_receive_skb - Send a completed packet up the stack
664 * @rx_ring: rx ring in play
665 * @skb: packet to send up
666 * @vlan_tag: vlan tag for packet
668 static void i40e_receive_skb(struct i40e_ring *rx_ring,
669 struct sk_buff *skb, u16 vlan_tag)
671 struct i40e_q_vector *q_vector = rx_ring->q_vector;
673 if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
674 (vlan_tag & VLAN_VID_MASK))
675 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
677 napi_gro_receive(&q_vector->napi, skb);
681 * i40evf_alloc_rx_buffers - Replace used receive buffers
682 * @rx_ring: ring to place buffers on
683 * @cleaned_count: number of buffers to replace
685 * Returns false if all allocations were successful, true if any fail
687 bool i40evf_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
689 u16 ntu = rx_ring->next_to_use;
690 union i40e_rx_desc *rx_desc;
691 struct i40e_rx_buffer *bi;
693 /* do nothing if no valid netdev defined */
694 if (!rx_ring->netdev || !cleaned_count)
697 rx_desc = I40E_RX_DESC(rx_ring, ntu);
698 bi = &rx_ring->rx_bi[ntu];
701 if (!i40e_alloc_mapped_page(rx_ring, bi))
704 /* Refresh the desc even if buffer_addrs didn't change
705 * because each write-back erases this info.
707 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
708 rx_desc->read.hdr_addr = 0;
713 if (unlikely(ntu == rx_ring->count)) {
714 rx_desc = I40E_RX_DESC(rx_ring, 0);
719 /* clear the status bits for the next_to_use descriptor */
720 rx_desc->wb.qword1.status_error_len = 0;
723 } while (cleaned_count);
725 if (rx_ring->next_to_use != ntu)
726 i40e_release_rx_desc(rx_ring, ntu);
731 if (rx_ring->next_to_use != ntu)
732 i40e_release_rx_desc(rx_ring, ntu);
734 /* make sure to come back via polling to try again after
741 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
742 * @vsi: the VSI we care about
743 * @skb: skb currently being received and modified
744 * @rx_desc: the receive descriptor
746 * skb->protocol must be set before this function is called
748 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
750 union i40e_rx_desc *rx_desc)
752 struct i40e_rx_ptype_decoded decoded;
753 u32 rx_error, rx_status;
758 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
759 ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT;
760 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
761 I40E_RXD_QW1_ERROR_SHIFT;
762 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
763 I40E_RXD_QW1_STATUS_SHIFT;
764 decoded = decode_rx_desc_ptype(ptype);
766 skb->ip_summed = CHECKSUM_NONE;
768 skb_checksum_none_assert(skb);
770 /* Rx csum enabled and ip headers found? */
771 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
774 /* did the hardware decode the packet and checksum? */
775 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
778 /* both known and outer_ip must be set for the below code to work */
779 if (!(decoded.known && decoded.outer_ip))
782 ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
783 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4);
784 ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
785 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6);
788 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
789 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
792 /* likely incorrect csum if alternate IP extension headers found */
794 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
795 /* don't increment checksum err here, non-fatal err */
798 /* there was some L4 error, count error and punt packet to the stack */
799 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
802 /* handle packets that were not able to be checksummed due
803 * to arrival speed, in this case the stack can compute
806 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
809 /* If there is an outer header present that might contain a checksum
810 * we need to bump the checksum level by 1 to reflect the fact that
811 * we are indicating we validated the inner checksum.
813 if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT)
816 /* Only report checksum unnecessary for TCP, UDP, or SCTP */
817 switch (decoded.inner_prot) {
818 case I40E_RX_PTYPE_INNER_PROT_TCP:
819 case I40E_RX_PTYPE_INNER_PROT_UDP:
820 case I40E_RX_PTYPE_INNER_PROT_SCTP:
821 skb->ip_summed = CHECKSUM_UNNECESSARY;
830 vsi->back->hw_csum_rx_error++;
834 * i40e_ptype_to_htype - get a hash type
835 * @ptype: the ptype value from the descriptor
837 * Returns a hash type to be used by skb_set_hash
839 static inline int i40e_ptype_to_htype(u8 ptype)
841 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
844 return PKT_HASH_TYPE_NONE;
846 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
847 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
848 return PKT_HASH_TYPE_L4;
849 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
850 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
851 return PKT_HASH_TYPE_L3;
853 return PKT_HASH_TYPE_L2;
857 * i40e_rx_hash - set the hash value in the skb
858 * @ring: descriptor ring
859 * @rx_desc: specific descriptor
861 static inline void i40e_rx_hash(struct i40e_ring *ring,
862 union i40e_rx_desc *rx_desc,
867 const __le64 rss_mask =
868 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
869 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
871 if (ring->netdev->features & NETIF_F_RXHASH)
874 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
875 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
876 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
881 * i40evf_process_skb_fields - Populate skb header fields from Rx descriptor
882 * @rx_ring: rx descriptor ring packet is being transacted on
883 * @rx_desc: pointer to the EOP Rx descriptor
884 * @skb: pointer to current skb being populated
885 * @rx_ptype: the packet type decoded by hardware
887 * This function checks the ring, descriptor, and packet information in
888 * order to populate the hash, checksum, VLAN, protocol, and
889 * other fields within the skb.
892 void i40evf_process_skb_fields(struct i40e_ring *rx_ring,
893 union i40e_rx_desc *rx_desc, struct sk_buff *skb,
896 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
898 /* modifies the skb - consumes the enet header */
899 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
901 i40e_rx_checksum(rx_ring->vsi, skb, rx_desc);
903 skb_record_rx_queue(skb, rx_ring->queue_index);
907 * i40e_pull_tail - i40e specific version of skb_pull_tail
908 * @rx_ring: rx descriptor ring packet is being transacted on
909 * @skb: pointer to current skb being adjusted
911 * This function is an i40e specific version of __pskb_pull_tail. The
912 * main difference between this version and the original function is that
913 * this function can make several assumptions about the state of things
914 * that allow for significant optimizations versus the standard function.
915 * As a result we can do things like drop a frag and maintain an accurate
916 * truesize for the skb.
918 static void i40e_pull_tail(struct i40e_ring *rx_ring, struct sk_buff *skb)
920 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
922 unsigned int pull_len;
924 /* it is valid to use page_address instead of kmap since we are
925 * working with pages allocated out of the lomem pool per
926 * alloc_page(GFP_ATOMIC)
928 va = skb_frag_address(frag);
930 /* we need the header to contain the greater of either ETH_HLEN or
931 * 60 bytes if the skb->len is less than 60 for skb_pad.
933 pull_len = eth_get_headlen(va, I40E_RX_HDR_SIZE);
935 /* align pull length to size of long to optimize memcpy performance */
936 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
938 /* update all of the pointers */
939 skb_frag_size_sub(frag, pull_len);
940 frag->page_offset += pull_len;
941 skb->data_len -= pull_len;
942 skb->tail += pull_len;
946 * i40e_cleanup_headers - Correct empty headers
947 * @rx_ring: rx descriptor ring packet is being transacted on
948 * @skb: pointer to current skb being fixed
950 * Also address the case where we are pulling data in on pages only
951 * and as such no data is present in the skb header.
953 * In addition if skb is not at least 60 bytes we need to pad it so that
954 * it is large enough to qualify as a valid Ethernet frame.
956 * Returns true if an error was encountered and skb was freed.
958 static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb)
960 /* place header in linear portion of buffer */
961 if (skb_is_nonlinear(skb))
962 i40e_pull_tail(rx_ring, skb);
964 /* if eth_skb_pad returns an error the skb was freed */
965 if (eth_skb_pad(skb))
972 * i40e_reuse_rx_page - page flip buffer and store it back on the ring
973 * @rx_ring: rx descriptor ring to store buffers on
974 * @old_buff: donor buffer to have page reused
976 * Synchronizes page for reuse by the adapter
978 static void i40e_reuse_rx_page(struct i40e_ring *rx_ring,
979 struct i40e_rx_buffer *old_buff)
981 struct i40e_rx_buffer *new_buff;
982 u16 nta = rx_ring->next_to_alloc;
984 new_buff = &rx_ring->rx_bi[nta];
986 /* update, and store next to alloc */
988 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
990 /* transfer page from old buffer to new buffer */
991 *new_buff = *old_buff;
995 * i40e_page_is_reserved - check if reuse is possible
996 * @page: page struct to check
998 static inline bool i40e_page_is_reserved(struct page *page)
1000 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
1004 * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff
1005 * @rx_ring: rx descriptor ring to transact packets on
1006 * @rx_buffer: buffer containing page to add
1007 * @rx_desc: descriptor containing length of buffer written by hardware
1008 * @skb: sk_buff to place the data into
1010 * This function will add the data contained in rx_buffer->page to the skb.
1011 * This is done either through a direct copy if the data in the buffer is
1012 * less than the skb header size, otherwise it will just attach the page as
1013 * a frag to the skb.
1015 * The function will then update the page offset if necessary and return
1016 * true if the buffer can be reused by the adapter.
1018 static bool i40e_add_rx_frag(struct i40e_ring *rx_ring,
1019 struct i40e_rx_buffer *rx_buffer,
1020 union i40e_rx_desc *rx_desc,
1021 struct sk_buff *skb)
1023 struct page *page = rx_buffer->page;
1024 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1025 unsigned int size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1026 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1027 #if (PAGE_SIZE < 8192)
1028 unsigned int truesize = I40E_RXBUFFER_2048;
1030 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1031 unsigned int last_offset = PAGE_SIZE - I40E_RXBUFFER_2048;
1034 /* will the data fit in the skb we allocated? if so, just
1035 * copy it as it is pretty small anyway
1037 if ((size <= I40E_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1038 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1040 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1042 /* page is not reserved, we can reuse buffer as-is */
1043 if (likely(!i40e_page_is_reserved(page)))
1046 /* this page cannot be reused so discard it */
1047 __free_pages(page, 0);
1051 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1052 rx_buffer->page_offset, size, truesize);
1054 /* avoid re-using remote pages */
1055 if (unlikely(i40e_page_is_reserved(page)))
1058 #if (PAGE_SIZE < 8192)
1059 /* if we are only owner of page we can reuse it */
1060 if (unlikely(page_count(page) != 1))
1063 /* flip page offset to other buffer */
1064 rx_buffer->page_offset ^= truesize;
1066 /* move offset up to the next cache line */
1067 rx_buffer->page_offset += truesize;
1069 if (rx_buffer->page_offset > last_offset)
1073 /* Even if we own the page, we are not allowed to use atomic_set()
1074 * This would break get_page_unless_zero() users.
1076 get_page(rx_buffer->page);
1082 * i40evf_fetch_rx_buffer - Allocate skb and populate it
1083 * @rx_ring: rx descriptor ring to transact packets on
1084 * @rx_desc: descriptor containing info written by hardware
1086 * This function allocates an skb on the fly, and populates it with the page
1087 * data from the current receive descriptor, taking care to set up the skb
1088 * correctly, as well as handling calling the page recycle function if
1092 struct sk_buff *i40evf_fetch_rx_buffer(struct i40e_ring *rx_ring,
1093 union i40e_rx_desc *rx_desc)
1095 struct i40e_rx_buffer *rx_buffer;
1096 struct sk_buff *skb;
1099 rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean];
1100 page = rx_buffer->page;
1103 skb = rx_buffer->skb;
1106 void *page_addr = page_address(page) + rx_buffer->page_offset;
1108 /* prefetch first cache line of first page */
1109 prefetch(page_addr);
1110 #if L1_CACHE_BYTES < 128
1111 prefetch(page_addr + L1_CACHE_BYTES);
1114 /* allocate a skb to store the frags */
1115 skb = __napi_alloc_skb(&rx_ring->q_vector->napi,
1117 GFP_ATOMIC | __GFP_NOWARN);
1118 if (unlikely(!skb)) {
1119 rx_ring->rx_stats.alloc_buff_failed++;
1123 /* we will be copying header into skb->data in
1124 * pskb_may_pull so it is in our interest to prefetch
1125 * it now to avoid a possible cache miss
1127 prefetchw(skb->data);
1129 rx_buffer->skb = NULL;
1132 /* we are reusing so sync this buffer for CPU use */
1133 dma_sync_single_range_for_cpu(rx_ring->dev,
1135 rx_buffer->page_offset,
1139 /* pull page into skb */
1140 if (i40e_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1141 /* hand second half of page back to the ring */
1142 i40e_reuse_rx_page(rx_ring, rx_buffer);
1143 rx_ring->rx_stats.page_reuse_count++;
1145 /* we are not reusing the buffer so unmap it */
1146 dma_unmap_page(rx_ring->dev, rx_buffer->dma, PAGE_SIZE,
1150 /* clear contents of buffer_info */
1151 rx_buffer->page = NULL;
1157 * i40e_is_non_eop - process handling of non-EOP buffers
1158 * @rx_ring: Rx ring being processed
1159 * @rx_desc: Rx descriptor for current buffer
1160 * @skb: Current socket buffer containing buffer in progress
1162 * This function updates next to clean. If the buffer is an EOP buffer
1163 * this function exits returning false, otherwise it will place the
1164 * sk_buff in the next buffer to be chained and return true indicating
1165 * that this is in fact a non-EOP buffer.
1167 static bool i40e_is_non_eop(struct i40e_ring *rx_ring,
1168 union i40e_rx_desc *rx_desc,
1169 struct sk_buff *skb)
1171 u32 ntc = rx_ring->next_to_clean + 1;
1173 /* fetch, update, and store next to clean */
1174 ntc = (ntc < rx_ring->count) ? ntc : 0;
1175 rx_ring->next_to_clean = ntc;
1177 prefetch(I40E_RX_DESC(rx_ring, ntc));
1179 /* if we are the last buffer then there is nothing else to do */
1180 #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)
1181 if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF)))
1184 /* place skb in next buffer to be received */
1185 rx_ring->rx_bi[ntc].skb = skb;
1186 rx_ring->rx_stats.non_eop_descs++;
1192 * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1193 * @rx_ring: rx descriptor ring to transact packets on
1194 * @budget: Total limit on number of packets to process
1196 * This function provides a "bounce buffer" approach to Rx interrupt
1197 * processing. The advantage to this is that on systems that have
1198 * expensive overhead for IOMMU access this provides a means of avoiding
1199 * it by maintaining the mapping of the page to the system.
1201 * Returns amount of work completed
1203 static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
1205 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1206 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1207 bool failure = false;
1209 while (likely(total_rx_packets < budget)) {
1210 union i40e_rx_desc *rx_desc;
1211 struct sk_buff *skb;
1217 /* return some buffers to hardware, one at a time is too slow */
1218 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1219 failure = failure ||
1220 i40evf_alloc_rx_buffers(rx_ring, cleaned_count);
1224 rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean);
1226 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1227 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1228 I40E_RXD_QW1_PTYPE_SHIFT;
1229 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1230 I40E_RXD_QW1_STATUS_SHIFT;
1232 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1235 /* status_error_len will always be zero for unused descriptors
1236 * because it's cleared in cleanup, and overlaps with hdr_addr
1237 * which is always zero because packet split isn't used, if the
1238 * hardware wrote DD then it will be non-zero
1240 if (!rx_desc->wb.qword1.status_error_len)
1243 /* This memory barrier is needed to keep us from reading
1244 * any other fields out of the rx_desc until we know the
1249 skb = i40evf_fetch_rx_buffer(rx_ring, rx_desc);
1255 if (i40e_is_non_eop(rx_ring, rx_desc, skb))
1258 /* ERR_MASK will only have valid bits if EOP set, and
1259 * what we are doing here is actually checking
1260 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in
1263 if (unlikely(i40e_test_staterr(rx_desc, BIT(I40E_RXD_QW1_ERROR_SHIFT)))) {
1264 dev_kfree_skb_any(skb);
1268 if (i40e_cleanup_headers(rx_ring, skb))
1271 /* probably a little skewed due to removing CRC */
1272 total_rx_bytes += skb->len;
1274 /* populate checksum, VLAN, and protocol */
1275 i40evf_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype);
1278 vlan_tag = (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?
1279 le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) : 0;
1281 i40e_receive_skb(rx_ring, skb, vlan_tag);
1283 /* update budget accounting */
1287 u64_stats_update_begin(&rx_ring->syncp);
1288 rx_ring->stats.packets += total_rx_packets;
1289 rx_ring->stats.bytes += total_rx_bytes;
1290 u64_stats_update_end(&rx_ring->syncp);
1291 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1292 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1294 /* guarantee a trip back through this routine if there was a failure */
1295 return failure ? budget : total_rx_packets;
1298 static u32 i40e_buildreg_itr(const int type, const u16 itr)
1302 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1303 /* Don't clear PBA because that can cause lost interrupts that
1304 * came in while we were cleaning/polling
1306 (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1307 (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1312 /* a small macro to shorten up some long lines */
1313 #define INTREG I40E_VFINT_DYN_CTLN1
1314 static inline int get_rx_itr_enabled(struct i40e_vsi *vsi, int idx)
1316 struct i40evf_adapter *adapter = vsi->back;
1318 return !!(adapter->rx_rings[idx].rx_itr_setting);
1321 static inline int get_tx_itr_enabled(struct i40e_vsi *vsi, int idx)
1323 struct i40evf_adapter *adapter = vsi->back;
1325 return !!(adapter->tx_rings[idx].tx_itr_setting);
1329 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1330 * @vsi: the VSI we care about
1331 * @q_vector: q_vector for which itr is being updated and interrupt enabled
1334 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1335 struct i40e_q_vector *q_vector)
1337 struct i40e_hw *hw = &vsi->back->hw;
1338 bool rx = false, tx = false;
1341 int idx = q_vector->v_idx;
1342 int rx_itr_setting, tx_itr_setting;
1344 vector = (q_vector->v_idx + vsi->base_vector);
1346 /* avoid dynamic calculation if in countdown mode OR if
1347 * all dynamic is disabled
1349 rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1351 rx_itr_setting = get_rx_itr_enabled(vsi, idx);
1352 tx_itr_setting = get_tx_itr_enabled(vsi, idx);
1354 if (q_vector->itr_countdown > 0 ||
1355 (!ITR_IS_DYNAMIC(rx_itr_setting) &&
1356 !ITR_IS_DYNAMIC(tx_itr_setting))) {
1360 if (ITR_IS_DYNAMIC(rx_itr_setting)) {
1361 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1362 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
1365 if (ITR_IS_DYNAMIC(tx_itr_setting)) {
1366 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1367 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1371 /* get the higher of the two ITR adjustments and
1372 * use the same value for both ITR registers
1373 * when in adaptive mode (Rx and/or Tx)
1375 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1377 q_vector->tx.itr = q_vector->rx.itr = itr;
1378 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1380 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1384 /* only need to enable the interrupt once, but need
1385 * to possibly update both ITR values
1388 /* set the INTENA_MSK_MASK so that this first write
1389 * won't actually enable the interrupt, instead just
1390 * updating the ITR (it's bit 31 PF and VF)
1393 /* don't check _DOWN because interrupt isn't being enabled */
1394 wr32(hw, INTREG(vector - 1), rxval);
1398 if (!test_bit(__I40E_DOWN, &vsi->state))
1399 wr32(hw, INTREG(vector - 1), txval);
1401 if (q_vector->itr_countdown)
1402 q_vector->itr_countdown--;
1404 q_vector->itr_countdown = ITR_COUNTDOWN_START;
1408 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1409 * @napi: napi struct with our devices info in it
1410 * @budget: amount of work driver is allowed to do this pass, in packets
1412 * This function will clean all queues associated with a q_vector.
1414 * Returns the amount of work done
1416 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1418 struct i40e_q_vector *q_vector =
1419 container_of(napi, struct i40e_q_vector, napi);
1420 struct i40e_vsi *vsi = q_vector->vsi;
1421 struct i40e_ring *ring;
1422 bool clean_complete = true;
1423 bool arm_wb = false;
1424 int budget_per_ring;
1427 if (test_bit(__I40E_DOWN, &vsi->state)) {
1428 napi_complete(napi);
1432 /* Since the actual Tx work is minimal, we can give the Tx a larger
1433 * budget and be more aggressive about cleaning up the Tx descriptors.
1435 i40e_for_each_ring(ring, q_vector->tx) {
1436 if (!i40e_clean_tx_irq(vsi, ring, budget)) {
1437 clean_complete = false;
1440 arm_wb |= ring->arm_wb;
1441 ring->arm_wb = false;
1444 /* Handle case where we are called by netpoll with a budget of 0 */
1448 /* We attempt to distribute budget to each Rx queue fairly, but don't
1449 * allow the budget to go below 1 because that would exit polling early.
1451 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1453 i40e_for_each_ring(ring, q_vector->rx) {
1454 int cleaned = i40e_clean_rx_irq(ring, budget_per_ring);
1456 work_done += cleaned;
1457 /* if we clean as many as budgeted, we must not be done */
1458 if (cleaned >= budget_per_ring)
1459 clean_complete = false;
1462 /* If work not completed, return budget and polling will return */
1463 if (!clean_complete) {
1466 q_vector->tx.ring[0].tx_stats.tx_force_wb++;
1467 i40e_enable_wb_on_itr(vsi, q_vector);
1472 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1473 q_vector->arm_wb_state = false;
1475 /* Work is done so exit the polling mode and re-enable the interrupt */
1476 napi_complete_done(napi, work_done);
1477 i40e_update_enable_itr(vsi, q_vector);
1482 * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1484 * @tx_ring: ring to send buffer on
1485 * @flags: the tx flags to be set
1487 * Checks the skb and set up correspondingly several generic transmit flags
1488 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1490 * Returns error code indicate the frame should be dropped upon error and the
1491 * otherwise returns 0 to indicate the flags has been set properly.
1493 static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1494 struct i40e_ring *tx_ring,
1497 __be16 protocol = skb->protocol;
1500 if (protocol == htons(ETH_P_8021Q) &&
1501 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1502 /* When HW VLAN acceleration is turned off by the user the
1503 * stack sets the protocol to 8021q so that the driver
1504 * can take any steps required to support the SW only
1505 * VLAN handling. In our case the driver doesn't need
1506 * to take any further steps so just set the protocol
1507 * to the encapsulated ethertype.
1509 skb->protocol = vlan_get_protocol(skb);
1513 /* if we have a HW VLAN tag being added, default to the HW one */
1514 if (skb_vlan_tag_present(skb)) {
1515 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1516 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1517 /* else if it is a SW VLAN, check the next protocol and store the tag */
1518 } else if (protocol == htons(ETH_P_8021Q)) {
1519 struct vlan_hdr *vhdr, _vhdr;
1521 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1525 protocol = vhdr->h_vlan_encapsulated_proto;
1526 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1527 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1536 * i40e_tso - set up the tso context descriptor
1537 * @skb: ptr to the skb we're sending
1538 * @hdr_len: ptr to the size of the packet header
1539 * @cd_type_cmd_tso_mss: Quad Word 1
1541 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1543 static int i40e_tso(struct sk_buff *skb, u8 *hdr_len, u64 *cd_type_cmd_tso_mss)
1545 u64 cd_cmd, cd_tso_len, cd_mss;
1556 u32 paylen, l4_offset;
1559 if (skb->ip_summed != CHECKSUM_PARTIAL)
1562 if (!skb_is_gso(skb))
1565 err = skb_cow_head(skb, 0);
1569 ip.hdr = skb_network_header(skb);
1570 l4.hdr = skb_transport_header(skb);
1572 /* initialize outer IP header fields */
1573 if (ip.v4->version == 4) {
1577 ip.v6->payload_len = 0;
1580 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1584 SKB_GSO_UDP_TUNNEL |
1585 SKB_GSO_UDP_TUNNEL_CSUM)) {
1586 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
1587 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) {
1590 /* determine offset of outer transport header */
1591 l4_offset = l4.hdr - skb->data;
1593 /* remove payload length from outer checksum */
1594 paylen = skb->len - l4_offset;
1595 csum_replace_by_diff(&l4.udp->check, htonl(paylen));
1598 /* reset pointers to inner headers */
1599 ip.hdr = skb_inner_network_header(skb);
1600 l4.hdr = skb_inner_transport_header(skb);
1602 /* initialize inner IP header fields */
1603 if (ip.v4->version == 4) {
1607 ip.v6->payload_len = 0;
1611 /* determine offset of inner transport header */
1612 l4_offset = l4.hdr - skb->data;
1614 /* remove payload length from inner checksum */
1615 paylen = skb->len - l4_offset;
1616 csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
1618 /* compute length of segmentation header */
1619 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
1621 /* find the field values */
1622 cd_cmd = I40E_TX_CTX_DESC_TSO;
1623 cd_tso_len = skb->len - *hdr_len;
1624 cd_mss = skb_shinfo(skb)->gso_size;
1625 *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1626 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1627 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1632 * i40e_tx_enable_csum - Enable Tx checksum offloads
1634 * @tx_flags: pointer to Tx flags currently set
1635 * @td_cmd: Tx descriptor command bits to set
1636 * @td_offset: Tx descriptor header offsets to set
1637 * @tx_ring: Tx descriptor ring
1638 * @cd_tunneling: ptr to context desc bits
1640 static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1641 u32 *td_cmd, u32 *td_offset,
1642 struct i40e_ring *tx_ring,
1655 unsigned char *exthdr;
1656 u32 offset, cmd = 0;
1660 if (skb->ip_summed != CHECKSUM_PARTIAL)
1663 ip.hdr = skb_network_header(skb);
1664 l4.hdr = skb_transport_header(skb);
1666 /* compute outer L2 header size */
1667 offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1669 if (skb->encapsulation) {
1671 /* define outer network header type */
1672 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1673 tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
1674 I40E_TX_CTX_EXT_IP_IPV4 :
1675 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1677 l4_proto = ip.v4->protocol;
1678 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1679 tunnel |= I40E_TX_CTX_EXT_IP_IPV6;
1681 exthdr = ip.hdr + sizeof(*ip.v6);
1682 l4_proto = ip.v6->nexthdr;
1683 if (l4.hdr != exthdr)
1684 ipv6_skip_exthdr(skb, exthdr - skb->data,
1685 &l4_proto, &frag_off);
1688 /* define outer transport */
1691 tunnel |= I40E_TXD_CTX_UDP_TUNNELING;
1692 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1695 tunnel |= I40E_TXD_CTX_GRE_TUNNELING;
1696 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1700 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1701 l4.hdr = skb_inner_network_header(skb);
1704 if (*tx_flags & I40E_TX_FLAGS_TSO)
1707 skb_checksum_help(skb);
1711 /* compute outer L3 header size */
1712 tunnel |= ((l4.hdr - ip.hdr) / 4) <<
1713 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
1715 /* switch IP header pointer from outer to inner header */
1716 ip.hdr = skb_inner_network_header(skb);
1718 /* compute tunnel header size */
1719 tunnel |= ((ip.hdr - l4.hdr) / 2) <<
1720 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1722 /* indicate if we need to offload outer UDP header */
1723 if ((*tx_flags & I40E_TX_FLAGS_TSO) &&
1724 !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
1725 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
1726 tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1728 /* record tunnel offload values */
1729 *cd_tunneling |= tunnel;
1731 /* switch L4 header pointer from outer to inner */
1732 l4.hdr = skb_inner_transport_header(skb);
1735 /* reset type as we transition from outer to inner headers */
1736 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6);
1737 if (ip.v4->version == 4)
1738 *tx_flags |= I40E_TX_FLAGS_IPV4;
1739 if (ip.v6->version == 6)
1740 *tx_flags |= I40E_TX_FLAGS_IPV6;
1743 /* Enable IP checksum offloads */
1744 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1745 l4_proto = ip.v4->protocol;
1746 /* the stack computes the IP header already, the only time we
1747 * need the hardware to recompute it is in the case of TSO.
1749 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
1750 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM :
1751 I40E_TX_DESC_CMD_IIPT_IPV4;
1752 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1753 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1755 exthdr = ip.hdr + sizeof(*ip.v6);
1756 l4_proto = ip.v6->nexthdr;
1757 if (l4.hdr != exthdr)
1758 ipv6_skip_exthdr(skb, exthdr - skb->data,
1759 &l4_proto, &frag_off);
1762 /* compute inner L3 header size */
1763 offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1765 /* Enable L4 checksum offloads */
1768 /* enable checksum offloads */
1769 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1770 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1773 /* enable SCTP checksum offload */
1774 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1775 offset |= (sizeof(struct sctphdr) >> 2) <<
1776 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1779 /* enable UDP checksum offload */
1780 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1781 offset |= (sizeof(struct udphdr) >> 2) <<
1782 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1785 if (*tx_flags & I40E_TX_FLAGS_TSO)
1787 skb_checksum_help(skb);
1792 *td_offset |= offset;
1798 * i40e_create_tx_ctx Build the Tx context descriptor
1799 * @tx_ring: ring to create the descriptor on
1800 * @cd_type_cmd_tso_mss: Quad Word 1
1801 * @cd_tunneling: Quad Word 0 - bits 0-31
1802 * @cd_l2tag2: Quad Word 0 - bits 32-63
1804 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1805 const u64 cd_type_cmd_tso_mss,
1806 const u32 cd_tunneling, const u32 cd_l2tag2)
1808 struct i40e_tx_context_desc *context_desc;
1809 int i = tx_ring->next_to_use;
1811 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1812 !cd_tunneling && !cd_l2tag2)
1815 /* grab the next descriptor */
1816 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1819 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1821 /* cpu_to_le32 and assign to struct fields */
1822 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1823 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1824 context_desc->rsvd = cpu_to_le16(0);
1825 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1829 * __i40evf_chk_linearize - Check if there are more than 8 buffers per packet
1832 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
1833 * and so we need to figure out the cases where we need to linearize the skb.
1835 * For TSO we need to count the TSO header and segment payload separately.
1836 * As such we need to check cases where we have 7 fragments or more as we
1837 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
1838 * the segment payload in the first descriptor, and another 7 for the
1841 bool __i40evf_chk_linearize(struct sk_buff *skb)
1843 const struct skb_frag_struct *frag, *stale;
1846 /* no need to check if number of frags is less than 7 */
1847 nr_frags = skb_shinfo(skb)->nr_frags;
1848 if (nr_frags < (I40E_MAX_BUFFER_TXD - 1))
1851 /* We need to walk through the list and validate that each group
1852 * of 6 fragments totals at least gso_size.
1854 nr_frags -= I40E_MAX_BUFFER_TXD - 2;
1855 frag = &skb_shinfo(skb)->frags[0];
1857 /* Initialize size to the negative value of gso_size minus 1. We
1858 * use this as the worst case scenerio in which the frag ahead
1859 * of us only provides one byte which is why we are limited to 6
1860 * descriptors for a single transmit as the header and previous
1861 * fragment are already consuming 2 descriptors.
1863 sum = 1 - skb_shinfo(skb)->gso_size;
1865 /* Add size of frags 0 through 4 to create our initial sum */
1866 sum += skb_frag_size(frag++);
1867 sum += skb_frag_size(frag++);
1868 sum += skb_frag_size(frag++);
1869 sum += skb_frag_size(frag++);
1870 sum += skb_frag_size(frag++);
1872 /* Walk through fragments adding latest fragment, testing it, and
1873 * then removing stale fragments from the sum.
1875 stale = &skb_shinfo(skb)->frags[0];
1877 sum += skb_frag_size(frag++);
1879 /* if sum is negative we failed to make sufficient progress */
1886 sum -= skb_frag_size(stale++);
1893 * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1894 * @tx_ring: the ring to be checked
1895 * @size: the size buffer we want to assure is available
1897 * Returns -EBUSY if a stop is needed, else 0
1899 int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1901 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1902 /* Memory barrier before checking head and tail */
1905 /* Check again in a case another CPU has just made room available. */
1906 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1909 /* A reprieve! - use start_queue because it doesn't call schedule */
1910 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1911 ++tx_ring->tx_stats.restart_queue;
1916 * i40evf_tx_map - Build the Tx descriptor
1917 * @tx_ring: ring to send buffer on
1919 * @first: first buffer info buffer to use
1920 * @tx_flags: collected send information
1921 * @hdr_len: size of the packet header
1922 * @td_cmd: the command field in the descriptor
1923 * @td_offset: offset for checksum or crc
1925 static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1926 struct i40e_tx_buffer *first, u32 tx_flags,
1927 const u8 hdr_len, u32 td_cmd, u32 td_offset)
1929 unsigned int data_len = skb->data_len;
1930 unsigned int size = skb_headlen(skb);
1931 struct skb_frag_struct *frag;
1932 struct i40e_tx_buffer *tx_bi;
1933 struct i40e_tx_desc *tx_desc;
1934 u16 i = tx_ring->next_to_use;
1939 bool tail_bump = true;
1942 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1943 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1944 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1945 I40E_TX_FLAGS_VLAN_SHIFT;
1948 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1949 gso_segs = skb_shinfo(skb)->gso_segs;
1953 /* multiply data chunks by size of headers */
1954 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1955 first->gso_segs = gso_segs;
1957 first->tx_flags = tx_flags;
1959 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1961 tx_desc = I40E_TX_DESC(tx_ring, i);
1964 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1965 unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
1967 if (dma_mapping_error(tx_ring->dev, dma))
1970 /* record length, and DMA address */
1971 dma_unmap_len_set(tx_bi, len, size);
1972 dma_unmap_addr_set(tx_bi, dma, dma);
1974 /* align size to end of page */
1975 max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1);
1976 tx_desc->buffer_addr = cpu_to_le64(dma);
1978 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1979 tx_desc->cmd_type_offset_bsz =
1980 build_ctob(td_cmd, td_offset,
1987 if (i == tx_ring->count) {
1988 tx_desc = I40E_TX_DESC(tx_ring, 0);
1995 max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
1996 tx_desc->buffer_addr = cpu_to_le64(dma);
1999 if (likely(!data_len))
2002 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
2009 if (i == tx_ring->count) {
2010 tx_desc = I40E_TX_DESC(tx_ring, 0);
2014 size = skb_frag_size(frag);
2017 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
2020 tx_bi = &tx_ring->tx_bi[i];
2023 /* set next_to_watch value indicating a packet is present */
2024 first->next_to_watch = tx_desc;
2027 if (i == tx_ring->count)
2030 tx_ring->next_to_use = i;
2032 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
2033 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
2035 /* Algorithm to optimize tail and RS bit setting:
2036 * if xmit_more is supported
2037 * if xmit_more is true
2038 * do not update tail and do not mark RS bit.
2039 * if xmit_more is false and last xmit_more was false
2040 * if every packet spanned less than 4 desc
2041 * then set RS bit on 4th packet and update tail
2044 * update tail and set RS bit on every packet.
2045 * if xmit_more is false and last_xmit_more was true
2046 * update tail and set RS bit.
2048 * Optimization: wmb to be issued only in case of tail update.
2049 * Also optimize the Descriptor WB path for RS bit with the same
2052 * Note: If there are less than 4 packets
2053 * pending and interrupts were disabled the service task will
2054 * trigger a force WB.
2056 if (skb->xmit_more &&
2057 !netif_xmit_stopped(txring_txq(tx_ring))) {
2058 tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
2060 } else if (!skb->xmit_more &&
2061 !netif_xmit_stopped(txring_txq(tx_ring)) &&
2062 (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) &&
2063 (tx_ring->packet_stride < WB_STRIDE) &&
2064 (desc_count < WB_STRIDE)) {
2065 tx_ring->packet_stride++;
2067 tx_ring->packet_stride = 0;
2068 tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
2072 tx_ring->packet_stride = 0;
2074 tx_desc->cmd_type_offset_bsz =
2075 build_ctob(td_cmd, td_offset, size, td_tag) |
2076 cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD :
2077 I40E_TX_DESC_CMD_EOP) <<
2078 I40E_TXD_QW1_CMD_SHIFT);
2080 /* notify HW of packet */
2082 prefetchw(tx_desc + 1);
2084 /* Force memory writes to complete before letting h/w
2085 * know there are new descriptors to fetch. (Only
2086 * applicable for weak-ordered memory model archs,
2090 writel(i, tx_ring->tail);
2095 dev_info(tx_ring->dev, "TX DMA map failed\n");
2097 /* clear dma mappings for failed tx_bi map */
2099 tx_bi = &tx_ring->tx_bi[i];
2100 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
2108 tx_ring->next_to_use = i;
2112 * i40e_xmit_frame_ring - Sends buffer on Tx ring
2114 * @tx_ring: ring to send buffer on
2116 * Returns NETDEV_TX_OK if sent, else an error code
2118 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2119 struct i40e_ring *tx_ring)
2121 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2122 u32 cd_tunneling = 0, cd_l2tag2 = 0;
2123 struct i40e_tx_buffer *first;
2131 /* prefetch the data, we'll need it later */
2132 prefetch(skb->data);
2134 count = i40e_xmit_descriptor_count(skb);
2135 if (i40e_chk_linearize(skb, count)) {
2136 if (__skb_linearize(skb))
2138 count = i40e_txd_use_count(skb->len);
2139 tx_ring->tx_stats.tx_linearize++;
2142 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
2143 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
2144 * + 4 desc gap to avoid the cache line where head is,
2145 * + 1 desc for context descriptor,
2146 * otherwise try next time
2148 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
2149 tx_ring->tx_stats.tx_busy++;
2150 return NETDEV_TX_BUSY;
2153 /* prepare the xmit flags */
2154 if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2157 /* obtain protocol of skb */
2158 protocol = vlan_get_protocol(skb);
2160 /* record the location of the first descriptor for this packet */
2161 first = &tx_ring->tx_bi[tx_ring->next_to_use];
2163 /* setup IPv4/IPv6 offloads */
2164 if (protocol == htons(ETH_P_IP))
2165 tx_flags |= I40E_TX_FLAGS_IPV4;
2166 else if (protocol == htons(ETH_P_IPV6))
2167 tx_flags |= I40E_TX_FLAGS_IPV6;
2169 tso = i40e_tso(skb, &hdr_len, &cd_type_cmd_tso_mss);
2174 tx_flags |= I40E_TX_FLAGS_TSO;
2176 /* Always offload the checksum, since it's in the data descriptor */
2177 tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
2178 tx_ring, &cd_tunneling);
2182 skb_tx_timestamp(skb);
2184 /* always enable CRC insertion offload */
2185 td_cmd |= I40E_TX_DESC_CMD_ICRC;
2187 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2188 cd_tunneling, cd_l2tag2);
2190 i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2193 return NETDEV_TX_OK;
2196 dev_kfree_skb_any(skb);
2197 return NETDEV_TX_OK;
2201 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2203 * @netdev: network interface device structure
2205 * Returns NETDEV_TX_OK if sent, else an error code
2207 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2209 struct i40evf_adapter *adapter = netdev_priv(netdev);
2210 struct i40e_ring *tx_ring = &adapter->tx_rings[skb->queue_mapping];
2212 /* hardware can't handle really short frames, hardware padding works
2215 if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
2216 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
2217 return NETDEV_TX_OK;
2218 skb->len = I40E_MIN_TX_LEN;
2219 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
2222 return i40e_xmit_frame_ring(skb, tx_ring);