drivers/net/ethernet/intel/i40e/i40e_nvm.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include "i40e_prototype.h"
  28
  29 /**
  30  * i40e_init_nvm_ops - Initialize NVM function pointers
  31  * @hw: pointer to the HW structure
  32  *
  33  * Setup the function pointers and the NVM info structure. Should be called
  34  * once per NVM initialization, e.g. inside the i40e_init_shared_code().
  35  * Please notice that the NVM term is used here (& in all methods covered
  36  * in this file) as an equivalent of the FLASH part mapped into the SR.
  37  * We are accessing FLASH always thru the Shadow RAM.
  38  **/
  39 i40e_status i40e_init_nvm(struct i40e_hw *hw)
  40 {
  41         struct i40e_nvm_info *nvm = &hw->nvm;
  42         i40e_status ret_code = 0;
  43         u32 fla, gens;
  44         u8 sr_size;
  45
  46         /* The SR size is stored regardless of the nvm programming mode
  47          * as the blank mode may be used in the factory line.
  48          */
  49         gens = rd32(hw, I40E_GLNVM_GENS);
  50         sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>
  51                            I40E_GLNVM_GENS_SR_SIZE_SHIFT);
  52         /* Switching to words (sr_size contains power of 2KB) */
  53         nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB;
  54
  55         /* Check if we are in the normal or blank NVM programming mode */
  56         fla = rd32(hw, I40E_GLNVM_FLA);
  57         if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */
  58                 /* Max NVM timeout */
  59                 nvm->timeout = I40E_MAX_NVM_TIMEOUT;
  60                 nvm->blank_nvm_mode = false;
  61         } else { /* Blank programming mode */
  62                 nvm->blank_nvm_mode = true;
  63                 ret_code = I40E_ERR_NVM_BLANK_MODE;
  64                 i40e_debug(hw, I40E_DEBUG_NVM, "NVM init error: unsupported blank mode.\n");
  65         }
  66
  67         return ret_code;
  68 }
  69
  70 /**
  71  * i40e_acquire_nvm - Generic request for acquiring the NVM ownership
  72  * @hw: pointer to the HW structure
  73  * @access: NVM access type (read or write)
  74  *
  75  * This function will request NVM ownership for reading
  76  * via the proper Admin Command.
  77  **/
  78 i40e_status i40e_acquire_nvm(struct i40e_hw *hw,
  79                                        enum i40e_aq_resource_access_type access)
  80 {
  81         i40e_status ret_code = 0;
  82         u64 gtime, timeout;
  83         u64 time_left = 0;
  84
  85         if (hw->nvm.blank_nvm_mode)
  86                 goto i40e_i40e_acquire_nvm_exit;
  87
  88         ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access,
  89                                             0, &time_left, NULL);
  90         /* Reading the Global Device Timer */
  91         gtime = rd32(hw, I40E_GLVFGEN_TIMER);
  92
  93         /* Store the timeout */
  94         hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime;
  95
  96         if (ret_code)
  97                 i40e_debug(hw, I40E_DEBUG_NVM,
  98                            "NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n",
  99                            access, time_left, ret_code, hw->aq.asq_last_status);
 100
 101         if (ret_code && time_left) {
 102                 /* Poll until the current NVM owner timeouts */
 103                 timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) + gtime;
 104                 while ((gtime < timeout) && time_left) {
 105                         usleep_range(10000, 20000);
 106                         gtime = rd32(hw, I40E_GLVFGEN_TIMER);
 107                         ret_code = i40e_aq_request_resource(hw,
 108                                                         I40E_NVM_RESOURCE_ID,
 109                                                         access, 0, &time_left,
 110                                                         NULL);
 111                         if (!ret_code) {
 112                                 hw->nvm.hw_semaphore_timeout =
 113                                             I40E_MS_TO_GTIME(time_left) + gtime;
 114                                 break;
 115                         }
 116                 }
 117                 if (ret_code) {
 118                         hw->nvm.hw_semaphore_timeout = 0;
 119                         i40e_debug(hw, I40E_DEBUG_NVM,
 120                                    "NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n",
 121                                    time_left, ret_code, hw->aq.asq_last_status);
 122                 }
 123         }
 124
 125 i40e_i40e_acquire_nvm_exit:
 126         return ret_code;
 127 }
 128
 129 /**
 130  * i40e_release_nvm - Generic request for releasing the NVM ownership
 131  * @hw: pointer to the HW structure
 132  *
 133  * This function will release NVM resource via the proper Admin Command.
 134  **/
 135 void i40e_release_nvm(struct i40e_hw *hw)
 136 {
 137         if (!hw->nvm.blank_nvm_mode)
 138                 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
 139 }
 140
 141 /**
 142  * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit
 143  * @hw: pointer to the HW structure
 144  *
 145  * Polls the SRCTL Shadow RAM register done bit.
 146  **/
 147 static i40e_status i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
 148 {
 149         i40e_status ret_code = I40E_ERR_TIMEOUT;
 150         u32 srctl, wait_cnt;
 151
 152         /* Poll the I40E_GLNVM_SRCTL until the done bit is set */
 153         for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) {
 154                 srctl = rd32(hw, I40E_GLNVM_SRCTL);
 155                 if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) {
 156                         ret_code = 0;
 157                         break;
 158                 }
 159                 udelay(5);
 160         }
 161         if (ret_code == I40E_ERR_TIMEOUT)
 162                 i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set");
 163         return ret_code;
 164 }
 165
 166 /**
 167  * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register
 168  * @hw: pointer to the HW structure
 169  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
 170  * @data: word read from the Shadow RAM
 171  *
 172  * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
 173  **/
 174 static i40e_status i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
 175                                             u16 *data)
 176 {
 177         i40e_status ret_code = I40E_ERR_TIMEOUT;
 178         u32 sr_reg;
 179
 180         if (offset >= hw->nvm.sr_size) {
 181                 i40e_debug(hw, I40E_DEBUG_NVM,
 182                            "NVM read error: offset %d beyond Shadow RAM limit %d\n",
 183                            offset, hw->nvm.sr_size);
 184                 ret_code = I40E_ERR_PARAM;
 185                 goto read_nvm_exit;
 186         }
 187
 188         /* Poll the done bit first */
 189         ret_code = i40e_poll_sr_srctl_done_bit(hw);
 190         if (!ret_code) {
 191                 /* Write the address and start reading */
 192                 sr_reg = ((u32)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
 193                          BIT(I40E_GLNVM_SRCTL_START_SHIFT);
 194                 wr32(hw, I40E_GLNVM_SRCTL, sr_reg);
 195
 196                 /* Poll I40E_GLNVM_SRCTL until the done bit is set */
 197                 ret_code = i40e_poll_sr_srctl_done_bit(hw);
 198                 if (!ret_code) {
 199                         sr_reg = rd32(hw, I40E_GLNVM_SRDATA);
 200                         *data = (u16)((sr_reg &
 201                                        I40E_GLNVM_SRDATA_RDDATA_MASK)
 202                                     >> I40E_GLNVM_SRDATA_RDDATA_SHIFT);
 203                 }
 204         }
 205         if (ret_code)
 206                 i40e_debug(hw, I40E_DEBUG_NVM,
 207                            "NVM read error: Couldn't access Shadow RAM address: 0x%x\n",
 208                            offset);
 209
 210 read_nvm_exit:
 211         return ret_code;
 212 }
 213
 214 /**
 215  * i40e_read_nvm_aq - Read Shadow RAM.
 216  * @hw: pointer to the HW structure.
 217  * @module_pointer: module pointer location in words from the NVM beginning
 218  * @offset: offset in words from module start
 219  * @words: number of words to write
 220  * @data: buffer with words to write to the Shadow RAM
 221  * @last_command: tells the AdminQ that this is the last command
 222  *
 223  * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
 224  **/
 225 static i40e_status i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
 226                                     u32 offset, u16 words, void *data,
 227                                     bool last_command)
 228 {
 229         i40e_status ret_code = I40E_ERR_NVM;
 230         struct i40e_asq_cmd_details cmd_details;
 231
 232         memset(&cmd_details, 0, sizeof(cmd_details));
 233
 234         /* Here we are checking the SR limit only for the flat memory model.
 235          * We cannot do it for the module-based model, as we did not acquire
 236          * the NVM resource yet (we cannot get the module pointer value).
 237          * Firmware will check the module-based model.
 238          */
 239         if ((offset + words) > hw->nvm.sr_size)
 240                 i40e_debug(hw, I40E_DEBUG_NVM,
 241                            "NVM write error: offset %d beyond Shadow RAM limit %d\n",
 242                            (offset + words), hw->nvm.sr_size);
 243         else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
 244                 /* We can write only up to 4KB (one sector), in one AQ write */
 245                 i40e_debug(hw, I40E_DEBUG_NVM,
 246                            "NVM write fail error: tried to write %d words, limit is %d.\n",
 247                            words, I40E_SR_SECTOR_SIZE_IN_WORDS);
 248         else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
 249                  != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
 250                 /* A single write cannot spread over two sectors */
 251                 i40e_debug(hw, I40E_DEBUG_NVM,
 252                            "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
 253                            offset, words);
 254         else
 255                 ret_code = i40e_aq_read_nvm(hw, module_pointer,
 256                                             2 * offset,  /*bytes*/
 257                                             2 * words,   /*bytes*/
 258                                             data, last_command, &cmd_details);
 259
 260         return ret_code;
 261 }
 262
 263 /**
 264  * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ
 265  * @hw: pointer to the HW structure
 266  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
 267  * @data: word read from the Shadow RAM
 268  *
 269  * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
 270  **/
 271 static i40e_status i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
 272                                          u16 *data)
 273 {
 274         i40e_status ret_code = I40E_ERR_TIMEOUT;
 275
 276         ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true);
 277         *data = le16_to_cpu(*(__le16 *)data);
 278
 279         return ret_code;
 280 }
 281
 282 /**
 283  * i40e_read_nvm_word - Reads Shadow RAM
 284  * @hw: pointer to the HW structure
 285  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
 286  * @data: word read from the Shadow RAM
 287  *
 288  * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
 289  **/
 290 i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
 291                                u16 *data)
 292 {
 293         enum i40e_status_code ret_code = 0;
 294
 295         if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) {
 296                 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
 297                 if (!ret_code) {
 298                         ret_code = i40e_read_nvm_word_aq(hw, offset, data);
 299                         i40e_release_nvm(hw);
 300                 }
 301         } else {
 302                 ret_code = i40e_read_nvm_word_srctl(hw, offset, data);
 303         }
 304         return ret_code;
 305 }
 306
 307 /**
 308  * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register
 309  * @hw: pointer to the HW structure
 310  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
 311  * @words: (in) number of words to read; (out) number of words actually read
 312  * @data: words read from the Shadow RAM
 313  *
 314  * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
 315  * method. The buffer read is preceded by the NVM ownership take
 316  * and followed by the release.
 317  **/
 318 static i40e_status i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
 319                                               u16 *words, u16 *data)
 320 {
 321         i40e_status ret_code = 0;
 322         u16 index, word;
 323
 324         /* Loop thru the selected region */
 325         for (word = 0; word < *words; word++) {
 326                 index = offset + word;
 327                 ret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]);
 328                 if (ret_code)
 329                         break;
 330         }
 331
 332         /* Update the number of words read from the Shadow RAM */
 333         *words = word;
 334
 335         return ret_code;
 336 }
 337
 338 /**
 339  * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ
 340  * @hw: pointer to the HW structure
 341  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
 342  * @words: (in) number of words to read; (out) number of words actually read
 343  * @data: words read from the Shadow RAM
 344  *
 345  * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq()
 346  * method. The buffer read is preceded by the NVM ownership take
 347  * and followed by the release.
 348  **/
 349 static i40e_status i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
 350                                            u16 *words, u16 *data)
 351 {
 352         i40e_status ret_code;
 353         u16 read_size = *words;
 354         bool last_cmd = false;
 355         u16 words_read = 0;
 356         u16 i = 0;
 357
 358         do {
 359                 /* Calculate number of bytes we should read in this step.
 360                  * FVL AQ do not allow to read more than one page at a time or
 361                  * to cross page boundaries.
 362                  */
 363                 if (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)
 364                         read_size = min(*words,
 365                                         (u16)(I40E_SR_SECTOR_SIZE_IN_WORDS -
 366                                       (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)));
 367                 else
 368                         read_size = min((*words - words_read),
 369                                         I40E_SR_SECTOR_SIZE_IN_WORDS);
 370
 371                 /* Check if this is last command, if so set proper flag */
 372                 if ((words_read + read_size) >= *words)
 373                         last_cmd = true;
 374
 375                 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size,
 376                                             data + words_read, last_cmd);
 377                 if (ret_code)
 378                         goto read_nvm_buffer_aq_exit;
 379
 380                 /* Increment counter for words already read and move offset to
 381                  * new read location
 382                  */
 383                 words_read += read_size;
 384                 offset += read_size;
 385         } while (words_read < *words);
 386
 387         for (i = 0; i < *words; i++)
 388                 data[i] = le16_to_cpu(((__le16 *)data)[i]);
 389
 390 read_nvm_buffer_aq_exit:
 391         *words = words_read;
 392         return ret_code;
 393 }
 394
 395 /**
 396  * i40e_read_nvm_buffer - Reads Shadow RAM buffer
 397  * @hw: pointer to the HW structure
 398  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
 399  * @words: (in) number of words to read; (out) number of words actually read
 400  * @data: words read from the Shadow RAM
 401  *
 402  * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
 403  * method. The buffer read is preceded by the NVM ownership take
 404  * and followed by the release.
 405  **/
 406 i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
 407                                  u16 *words, u16 *data)
 408 {
 409         enum i40e_status_code ret_code = 0;
 410
 411         if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) {
 412                 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
 413                 if (!ret_code) {
 414                         ret_code = i40e_read_nvm_buffer_aq(hw, offset, words,
 415                                                            data);
 416                         i40e_release_nvm(hw);
 417                 }
 418         } else {
 419                 ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data);
 420         }
 421         return ret_code;
 422 }
 423
 424 /**
 425  * i40e_write_nvm_aq - Writes Shadow RAM.
 426  * @hw: pointer to the HW structure.
 427  * @module_pointer: module pointer location in words from the NVM beginning
 428  * @offset: offset in words from module start
 429  * @words: number of words to write
 430  * @data: buffer with words to write to the Shadow RAM
 431  * @last_command: tells the AdminQ that this is the last command
 432  *
 433  * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
 434  **/
 435 static i40e_status i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
 436                                      u32 offset, u16 words, void *data,
 437                                      bool last_command)
 438 {
 439         i40e_status ret_code = I40E_ERR_NVM;
 440         struct i40e_asq_cmd_details cmd_details;
 441
 442         memset(&cmd_details, 0, sizeof(cmd_details));
 443         cmd_details.wb_desc = &hw->nvm_wb_desc;
 444
 445         /* Here we are checking the SR limit only for the flat memory model.
 446          * We cannot do it for the module-based model, as we did not acquire
 447          * the NVM resource yet (we cannot get the module pointer value).
 448          * Firmware will check the module-based model.
 449          */
 450         if ((offset + words) > hw->nvm.sr_size)
 451                 i40e_debug(hw, I40E_DEBUG_NVM,
 452                            "NVM write error: offset %d beyond Shadow RAM limit %d\n",
 453                            (offset + words), hw->nvm.sr_size);
 454         else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
 455                 /* We can write only up to 4KB (one sector), in one AQ write */
 456                 i40e_debug(hw, I40E_DEBUG_NVM,
 457                            "NVM write fail error: tried to write %d words, limit is %d.\n",
 458                            words, I40E_SR_SECTOR_SIZE_IN_WORDS);
 459         else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
 460                  != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
 461                 /* A single write cannot spread over two sectors */
 462                 i40e_debug(hw, I40E_DEBUG_NVM,
 463                            "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
 464                            offset, words);
 465         else
 466                 ret_code = i40e_aq_update_nvm(hw, module_pointer,
 467                                               2 * offset,  /*bytes*/
 468                                               2 * words,   /*bytes*/
 469                                               data, last_command, &cmd_details);
 470
 471         return ret_code;
 472 }
 473
 474 /**
 475  * i40e_calc_nvm_checksum - Calculates and returns the checksum
 476  * @hw: pointer to hardware structure
 477  * @checksum: pointer to the checksum
 478  *
 479  * This function calculates SW Checksum that covers the whole 64kB shadow RAM
 480  * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
 481  * is customer specific and unknown. Therefore, this function skips all maximum
 482  * possible size of VPD (1kB).
 483  **/
 484 static i40e_status i40e_calc_nvm_checksum(struct i40e_hw *hw,
 485                                                     u16 *checksum)
 486 {
 487         i40e_status ret_code;
 488         struct i40e_virt_mem vmem;
 489         u16 pcie_alt_module = 0;
 490         u16 checksum_local = 0;
 491         u16 vpd_module = 0;
 492         u16 *data;
 493         u16 i = 0;
 494
 495         ret_code = i40e_allocate_virt_mem(hw, &vmem,
 496                                     I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16));
 497         if (ret_code)
 498                 goto i40e_calc_nvm_checksum_exit;
 499         data = (u16 *)vmem.va;
 500
 501         /* read pointer to VPD area */
 502         ret_code = i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module);
 503         if (ret_code) {
 504                 ret_code = I40E_ERR_NVM_CHECKSUM;
 505                 goto i40e_calc_nvm_checksum_exit;
 506         }
 507
 508         /* read pointer to PCIe Alt Auto-load module */
 509         ret_code = i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR,
 510                                       &pcie_alt_module);
 511         if (ret_code) {
 512                 ret_code = I40E_ERR_NVM_CHECKSUM;
 513                 goto i40e_calc_nvm_checksum_exit;
 514         }
 515
 516         /* Calculate SW checksum that covers the whole 64kB shadow RAM
 517          * except the VPD and PCIe ALT Auto-load modules
 518          */
 519         for (i = 0; i < hw->nvm.sr_size; i++) {
 520                 /* Read SR page */
 521                 if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) {
 522                         u16 words = I40E_SR_SECTOR_SIZE_IN_WORDS;
 523
 524                         ret_code = i40e_read_nvm_buffer(hw, i, &words, data);
 525                         if (ret_code) {
 526                                 ret_code = I40E_ERR_NVM_CHECKSUM;
 527                                 goto i40e_calc_nvm_checksum_exit;
 528                         }
 529                 }
 530
 531                 /* Skip Checksum word */
 532                 if (i == I40E_SR_SW_CHECKSUM_WORD)
 533                         continue;
 534                 /* Skip VPD module (convert byte size to word count) */
 535                 if ((i >= (u32)vpd_module) &&
 536                     (i < ((u32)vpd_module +
 537                      (I40E_SR_VPD_MODULE_MAX_SIZE / 2)))) {
 538                         continue;
 539                 }
 540                 /* Skip PCIe ALT module (convert byte size to word count) */
 541                 if ((i >= (u32)pcie_alt_module) &&
 542                     (i < ((u32)pcie_alt_module +
 543                      (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2)))) {
 544                         continue;
 545                 }
 546
 547                 checksum_local += data[i % I40E_SR_SECTOR_SIZE_IN_WORDS];
 548         }
 549
 550         *checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local;
 551
 552 i40e_calc_nvm_checksum_exit:
 553         i40e_free_virt_mem(hw, &vmem);
 554         return ret_code;
 555 }
 556
 557 /**
 558  * i40e_update_nvm_checksum - Updates the NVM checksum
 559  * @hw: pointer to hardware structure
 560  *
 561  * NVM ownership must be acquired before calling this function and released
 562  * on ARQ completion event reception by caller.
 563  * This function will commit SR to NVM.
 564  **/
 565 i40e_status i40e_update_nvm_checksum(struct i40e_hw *hw)
 566 {
 567         i40e_status ret_code;
 568         u16 checksum;
 569         __le16 le_sum;
 570
 571         ret_code = i40e_calc_nvm_checksum(hw, &checksum);
 572         if (!ret_code) {
 573                 le_sum = cpu_to_le16(checksum);
 574                 ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
 575                                              1, &le_sum, true);
 576         }
 577
 578         return ret_code;
 579 }
 580
 581 /**
 582  * i40e_validate_nvm_checksum - Validate EEPROM checksum
 583  * @hw: pointer to hardware structure
 584  * @checksum: calculated checksum
 585  *
 586  * Performs checksum calculation and validates the NVM SW checksum. If the
 587  * caller does not need checksum, the value can be NULL.
 588  **/
 589 i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw,
 590                                                  u16 *checksum)
 591 {
 592         i40e_status ret_code = 0;
 593         u16 checksum_sr = 0;
 594         u16 checksum_local = 0;
 595
 596         ret_code = i40e_calc_nvm_checksum(hw, &checksum_local);
 597         if (ret_code)
 598                 goto i40e_validate_nvm_checksum_exit;
 599
 600         /* Do not use i40e_read_nvm_word() because we do not want to take
 601          * the synchronization semaphores twice here.
 602          */
 603         i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr);
 604
 605         /* Verify read checksum from EEPROM is the same as
 606          * calculated checksum
 607          */
 608         if (checksum_local != checksum_sr)
 609                 ret_code = I40E_ERR_NVM_CHECKSUM;
 610
 611         /* If the user cares, return the calculated checksum */
 612         if (checksum)
 613                 *checksum = checksum_local;
 614
 615 i40e_validate_nvm_checksum_exit:
 616         return ret_code;
 617 }
 618
 619 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw,
 620                                           struct i40e_nvm_access *cmd,
 621                                           u8 *bytes, int *perrno);
 622 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw,
 623                                              struct i40e_nvm_access *cmd,
 624                                              u8 *bytes, int *perrno);
 625 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw,
 626                                              struct i40e_nvm_access *cmd,
 627                                              u8 *bytes, int *errno);
 628 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
 629                                                 struct i40e_nvm_access *cmd,
 630                                                 int *perrno);
 631 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
 632                                          struct i40e_nvm_access *cmd,
 633                                          int *perrno);
 634 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw,
 635                                          struct i40e_nvm_access *cmd,
 636                                          u8 *bytes, int *perrno);
 637 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw,
 638                                         struct i40e_nvm_access *cmd,
 639                                         u8 *bytes, int *perrno);
 640 static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw,
 641                                        struct i40e_nvm_access *cmd,
 642                                        u8 *bytes, int *perrno);
 643 static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
 644                                              struct i40e_nvm_access *cmd,
 645                                              u8 *bytes, int *perrno);
 646 static inline u8 i40e_nvmupd_get_module(u32 val)
 647 {
 648         return (u8)(val & I40E_NVM_MOD_PNT_MASK);
 649 }
 650 static inline u8 i40e_nvmupd_get_transaction(u32 val)
 651 {
 652         return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT);
 653 }
 654
 655 static const char * const i40e_nvm_update_state_str[] = {
 656         "I40E_NVMUPD_INVALID",
 657         "I40E_NVMUPD_READ_CON",
 658         "I40E_NVMUPD_READ_SNT",
 659         "I40E_NVMUPD_READ_LCB",
 660         "I40E_NVMUPD_READ_SA",
 661         "I40E_NVMUPD_WRITE_ERA",
 662         "I40E_NVMUPD_WRITE_CON",
 663         "I40E_NVMUPD_WRITE_SNT",
 664         "I40E_NVMUPD_WRITE_LCB",
 665         "I40E_NVMUPD_WRITE_SA",
 666         "I40E_NVMUPD_CSUM_CON",
 667         "I40E_NVMUPD_CSUM_SA",
 668         "I40E_NVMUPD_CSUM_LCB",
 669         "I40E_NVMUPD_STATUS",
 670         "I40E_NVMUPD_EXEC_AQ",
 671         "I40E_NVMUPD_GET_AQ_RESULT",
 672 };
 673
 674 /**
 675  * i40e_nvmupd_command - Process an NVM update command
 676  * @hw: pointer to hardware structure
 677  * @cmd: pointer to nvm update command
 678  * @bytes: pointer to the data buffer
 679  * @perrno: pointer to return error code
 680  *
 681  * Dispatches command depending on what update state is current
 682  **/
 683 i40e_status i40e_nvmupd_command(struct i40e_hw *hw,
 684                                 struct i40e_nvm_access *cmd,
 685                                 u8 *bytes, int *perrno)
 686 {
 687         i40e_status status;
 688         enum i40e_nvmupd_cmd upd_cmd;
 689
 690         /* assume success */
 691         *perrno = 0;
 692
 693         /* early check for status command and debug msgs */
 694         upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
 695
 696         i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d opc 0x%04x cmd 0x%08x config 0x%08x offset 0x%08x data_size 0x%08x\n",
 697                    i40e_nvm_update_state_str[upd_cmd],
 698                    hw->nvmupd_state,
 699                    hw->nvm_release_on_done, hw->nvm_wait_opcode,
 700                    cmd->command, cmd->config, cmd->offset, cmd->data_size);
 701
 702         if (upd_cmd == I40E_NVMUPD_INVALID) {
 703                 *perrno = -EFAULT;
 704                 i40e_debug(hw, I40E_DEBUG_NVM,
 705                            "i40e_nvmupd_validate_command returns %d errno %d\n",
 706                            upd_cmd, *perrno);
 707         }
 708
 709         /* a status request returns immediately rather than
 710          * going into the state machine
 711          */
 712         if (upd_cmd == I40E_NVMUPD_STATUS) {
 713                 if (!cmd->data_size) {
 714                         *perrno = -EFAULT;
 715                         return I40E_ERR_BUF_TOO_SHORT;
 716                 }
 717
 718                 bytes[0] = hw->nvmupd_state;
 719
 720                 if (cmd->data_size >= 4) {
 721                         bytes[1] = 0;
 722                         *((u16 *)&bytes[2]) = hw->nvm_wait_opcode;
 723                 }
 724
 725                 return 0;
 726         }
 727
 728         switch (hw->nvmupd_state) {
 729         case I40E_NVMUPD_STATE_INIT:
 730                 status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno);
 731                 break;
 732
 733         case I40E_NVMUPD_STATE_READING:
 734                 status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno);
 735                 break;
 736
 737         case I40E_NVMUPD_STATE_WRITING:
 738                 status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno);
 739                 break;
 740
 741         case I40E_NVMUPD_STATE_INIT_WAIT:
 742         case I40E_NVMUPD_STATE_WRITE_WAIT:
 743                 /* if we need to stop waiting for an event, clear
 744                  * the wait info and return before doing anything else
 745                  */
 746                 if (cmd->offset == 0xffff) {
 747                         i40e_nvmupd_check_wait_event(hw, hw->nvm_wait_opcode);
 748                         return 0;
 749                 }
 750
 751                 status = I40E_ERR_NOT_READY;
 752                 *perrno = -EBUSY;
 753                 break;
 754
 755         default:
 756                 /* invalid state, should never happen */
 757                 i40e_debug(hw, I40E_DEBUG_NVM,
 758                            "NVMUPD: no such state %d\n", hw->nvmupd_state);
 759                 status = I40E_NOT_SUPPORTED;
 760                 *perrno = -ESRCH;
 761                 break;
 762         }
 763         return status;
 764 }
 765
 766 /**
 767  * i40e_nvmupd_state_init - Handle NVM update state Init
 768  * @hw: pointer to hardware structure
 769  * @cmd: pointer to nvm update command buffer
 770  * @bytes: pointer to the data buffer
 771  * @perrno: pointer to return error code
 772  *
 773  * Process legitimate commands of the Init state and conditionally set next
 774  * state. Reject all other commands.
 775  **/
 776 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw,
 777                                           struct i40e_nvm_access *cmd,
 778                                           u8 *bytes, int *perrno)
 779 {
 780         i40e_status status = 0;
 781         enum i40e_nvmupd_cmd upd_cmd;
 782
 783         upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
 784
 785         switch (upd_cmd) {
 786         case I40E_NVMUPD_READ_SA:
 787                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
 788                 if (status) {
 789                         *perrno = i40e_aq_rc_to_posix(status,
 790                                                      hw->aq.asq_last_status);
 791                 } else {
 792                         status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
 793                         i40e_release_nvm(hw);
 794                 }
 795                 break;
 796
 797         case I40E_NVMUPD_READ_SNT:
 798                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
 799                 if (status) {
 800                         *perrno = i40e_aq_rc_to_posix(status,
 801                                                      hw->aq.asq_last_status);
 802                 } else {
 803                         status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
 804                         if (status)
 805                                 i40e_release_nvm(hw);
 806                         else
 807                                 hw->nvmupd_state = I40E_NVMUPD_STATE_READING;
 808                 }
 809                 break;
 810
 811         case I40E_NVMUPD_WRITE_ERA:
 812                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
 813                 if (status) {
 814                         *perrno = i40e_aq_rc_to_posix(status,
 815                                                      hw->aq.asq_last_status);
 816                 } else {
 817                         status = i40e_nvmupd_nvm_erase(hw, cmd, perrno);
 818                         if (status) {
 819                                 i40e_release_nvm(hw);
 820                         } else {
 821                                 hw->nvm_release_on_done = true;
 822                                 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_erase;
 823                                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
 824                         }
 825                 }
 826                 break;
 827
 828         case I40E_NVMUPD_WRITE_SA:
 829                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
 830                 if (status) {
 831                         *perrno = i40e_aq_rc_to_posix(status,
 832                                                      hw->aq.asq_last_status);
 833                 } else {
 834                         status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
 835                         if (status) {
 836                                 i40e_release_nvm(hw);
 837                         } else {
 838                                 hw->nvm_release_on_done = true;
 839                                 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
 840                                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
 841                         }
 842                 }
 843                 break;
 844
 845         case I40E_NVMUPD_WRITE_SNT:
 846                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
 847                 if (status) {
 848                         *perrno = i40e_aq_rc_to_posix(status,
 849                                                      hw->aq.asq_last_status);
 850                 } else {
 851                         status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
 852                         if (status) {
 853                                 i40e_release_nvm(hw);
 854                         } else {
 855                                 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
 856                                 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
 857                         }
 858                 }
 859                 break;
 860
 861         case I40E_NVMUPD_CSUM_SA:
 862                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
 863                 if (status) {
 864                         *perrno = i40e_aq_rc_to_posix(status,
 865                                                      hw->aq.asq_last_status);
 866                 } else {
 867                         status = i40e_update_nvm_checksum(hw);
 868                         if (status) {
 869                                 *perrno = hw->aq.asq_last_status ?
 870                                    i40e_aq_rc_to_posix(status,
 871                                                        hw->aq.asq_last_status) :
 872                                    -EIO;
 873                                 i40e_release_nvm(hw);
 874                         } else {
 875                                 hw->nvm_release_on_done = true;
 876                                 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
 877                                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
 878                         }
 879                 }
 880                 break;
 881
 882         case I40E_NVMUPD_EXEC_AQ:
 883                 status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno);
 884                 break;
 885
 886         case I40E_NVMUPD_GET_AQ_RESULT:
 887                 status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno);
 888                 break;
 889
 890         default:
 891                 i40e_debug(hw, I40E_DEBUG_NVM,
 892                            "NVMUPD: bad cmd %s in init state\n",
 893                            i40e_nvm_update_state_str[upd_cmd]);
 894                 status = I40E_ERR_NVM;
 895                 *perrno = -ESRCH;
 896                 break;
 897         }
 898         return status;
 899 }
 900
 901 /**
 902  * i40e_nvmupd_state_reading - Handle NVM update state Reading
 903  * @hw: pointer to hardware structure
 904  * @cmd: pointer to nvm update command buffer
 905  * @bytes: pointer to the data buffer
 906  * @perrno: pointer to return error code
 907  *
 908  * NVM ownership is already held.  Process legitimate commands and set any
 909  * change in state; reject all other commands.
 910  **/
 911 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw,
 912                                              struct i40e_nvm_access *cmd,
 913                                              u8 *bytes, int *perrno)
 914 {
 915         i40e_status status = 0;
 916         enum i40e_nvmupd_cmd upd_cmd;
 917
 918         upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
 919
 920         switch (upd_cmd) {
 921         case I40E_NVMUPD_READ_SA:
 922         case I40E_NVMUPD_READ_CON:
 923                 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
 924                 break;
 925
 926         case I40E_NVMUPD_READ_LCB:
 927                 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
 928                 i40e_release_nvm(hw);
 929                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
 930                 break;
 931
 932         default:
 933                 i40e_debug(hw, I40E_DEBUG_NVM,
 934                            "NVMUPD: bad cmd %s in reading state.\n",
 935                            i40e_nvm_update_state_str[upd_cmd]);
 936                 status = I40E_NOT_SUPPORTED;
 937                 *perrno = -ESRCH;
 938                 break;
 939         }
 940         return status;
 941 }
 942
 943 /**
 944  * i40e_nvmupd_state_writing - Handle NVM update state Writing
 945  * @hw: pointer to hardware structure
 946  * @cmd: pointer to nvm update command buffer
 947  * @bytes: pointer to the data buffer
 948  * @perrno: pointer to return error code
 949  *
 950  * NVM ownership is already held.  Process legitimate commands and set any
 951  * change in state; reject all other commands
 952  **/
 953 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw,
 954                                              struct i40e_nvm_access *cmd,
 955                                              u8 *bytes, int *perrno)
 956 {
 957         i40e_status status = 0;
 958         enum i40e_nvmupd_cmd upd_cmd;
 959         bool retry_attempt = false;
 960
 961         upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
 962
 963 retry:
 964         switch (upd_cmd) {
 965         case I40E_NVMUPD_WRITE_CON:
 966                 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
 967                 if (!status) {
 968                         hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
 969                         hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
 970                 }
 971                 break;
 972
 973         case I40E_NVMUPD_WRITE_LCB:
 974                 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
 975                 if (status) {
 976                         *perrno = hw->aq.asq_last_status ?
 977                                    i40e_aq_rc_to_posix(status,
 978                                                        hw->aq.asq_last_status) :
 979                                    -EIO;
 980                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
 981                 } else {
 982                         hw->nvm_release_on_done = true;
 983                         hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
 984                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
 985                 }
 986                 break;
 987
 988         case I40E_NVMUPD_CSUM_CON:
 989                 status = i40e_update_nvm_checksum(hw);
 990                 if (status) {
 991                         *perrno = hw->aq.asq_last_status ?
 992                                    i40e_aq_rc_to_posix(status,
 993                                                        hw->aq.asq_last_status) :
 994                                    -EIO;
 995                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
 996                 } else {
 997                         hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
 998                         hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
 999                 }
1000                 break;
1001
1002         case I40E_NVMUPD_CSUM_LCB:
1003                 status = i40e_update_nvm_checksum(hw);
1004                 if (status) {
1005                         *perrno = hw->aq.asq_last_status ?
1006                                    i40e_aq_rc_to_posix(status,
1007                                                        hw->aq.asq_last_status) :
1008                                    -EIO;
1009                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1010                 } else {
1011                         hw->nvm_release_on_done = true;
1012                         hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1013                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1014                 }
1015                 break;
1016
1017         default:
1018                 i40e_debug(hw, I40E_DEBUG_NVM,
1019                            "NVMUPD: bad cmd %s in writing state.\n",
1020                            i40e_nvm_update_state_str[upd_cmd]);
1021                 status = I40E_NOT_SUPPORTED;
1022                 *perrno = -ESRCH;
1023                 break;
1024         }
1025
1026         /* In some circumstances, a multi-write transaction takes longer
1027          * than the default 3 minute timeout on the write semaphore.  If
1028          * the write failed with an EBUSY status, this is likely the problem,
1029          * so here we try to reacquire the semaphore then retry the write.
1030          * We only do one retry, then give up.
1031          */
1032         if (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) &&
1033             !retry_attempt) {
1034                 i40e_status old_status = status;
1035                 u32 old_asq_status = hw->aq.asq_last_status;
1036                 u32 gtime;
1037
1038                 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
1039                 if (gtime >= hw->nvm.hw_semaphore_timeout) {
1040                         i40e_debug(hw, I40E_DEBUG_ALL,
1041                                    "NVMUPD: write semaphore expired (%d >= %lld), retrying\n",
1042                                    gtime, hw->nvm.hw_semaphore_timeout);
1043                         i40e_release_nvm(hw);
1044                         status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
1045                         if (status) {
1046                                 i40e_debug(hw, I40E_DEBUG_ALL,
1047                                            "NVMUPD: write semaphore reacquire failed aq_err = %d\n",
1048                                            hw->aq.asq_last_status);
1049                                 status = old_status;
1050                                 hw->aq.asq_last_status = old_asq_status;
1051                         } else {
1052                                 retry_attempt = true;
1053                                 goto retry;
1054                         }
1055                 }
1056         }
1057
1058         return status;
1059 }
1060
1061 /**
1062  * i40e_nvmupd_check_wait_event - handle NVM update operation events
1063  * @hw: pointer to the hardware structure
1064  * @opcode: the event that just happened
1065  **/
1066 void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode)
1067 {
1068         if (opcode == hw->nvm_wait_opcode) {
1069                 i40e_debug(hw, I40E_DEBUG_NVM,
1070                            "NVMUPD: clearing wait on opcode 0x%04x\n", opcode);
1071                 if (hw->nvm_release_on_done) {
1072                         i40e_release_nvm(hw);
1073                         hw->nvm_release_on_done = false;
1074                 }
1075                 hw->nvm_wait_opcode = 0;
1076
1077                 switch (hw->nvmupd_state) {
1078                 case I40E_NVMUPD_STATE_INIT_WAIT:
1079                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1080                         break;
1081
1082                 case I40E_NVMUPD_STATE_WRITE_WAIT:
1083                         hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING;
1084                         break;
1085
1086                 default:
1087                         break;
1088                 }
1089         }
1090 }
1091
1092 /**
1093  * i40e_nvmupd_validate_command - Validate given command
1094  * @hw: pointer to hardware structure
1095  * @cmd: pointer to nvm update command buffer
1096  * @perrno: pointer to return error code
1097  *
1098  * Return one of the valid command types or I40E_NVMUPD_INVALID
1099  **/
1100 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
1101                                                  struct i40e_nvm_access *cmd,
1102                                                  int *perrno)
1103 {
1104         enum i40e_nvmupd_cmd upd_cmd;
1105         u8 module, transaction;
1106
1107         /* anything that doesn't match a recognized case is an error */
1108         upd_cmd = I40E_NVMUPD_INVALID;
1109
1110         transaction = i40e_nvmupd_get_transaction(cmd->config);
1111         module = i40e_nvmupd_get_module(cmd->config);
1112
1113         /* limits on data size */
1114         if ((cmd->data_size < 1) ||
1115             (cmd->data_size > I40E_NVMUPD_MAX_DATA)) {
1116                 i40e_debug(hw, I40E_DEBUG_NVM,
1117                            "i40e_nvmupd_validate_command data_size %d\n",
1118                            cmd->data_size);
1119                 *perrno = -EFAULT;
1120                 return I40E_NVMUPD_INVALID;
1121         }
1122
1123         switch (cmd->command) {
1124         case I40E_NVM_READ:
1125                 switch (transaction) {
1126                 case I40E_NVM_CON:
1127                         upd_cmd = I40E_NVMUPD_READ_CON;
1128                         break;
1129                 case I40E_NVM_SNT:
1130                         upd_cmd = I40E_NVMUPD_READ_SNT;
1131                         break;
1132                 case I40E_NVM_LCB:
1133                         upd_cmd = I40E_NVMUPD_READ_LCB;
1134                         break;
1135                 case I40E_NVM_SA:
1136                         upd_cmd = I40E_NVMUPD_READ_SA;
1137                         break;
1138                 case I40E_NVM_EXEC:
1139                         if (module == 0xf)
1140                                 upd_cmd = I40E_NVMUPD_STATUS;
1141                         else if (module == 0)
1142                                 upd_cmd = I40E_NVMUPD_GET_AQ_RESULT;
1143                         break;
1144                 }
1145                 break;
1146
1147         case I40E_NVM_WRITE:
1148                 switch (transaction) {
1149                 case I40E_NVM_CON:
1150                         upd_cmd = I40E_NVMUPD_WRITE_CON;
1151                         break;
1152                 case I40E_NVM_SNT:
1153                         upd_cmd = I40E_NVMUPD_WRITE_SNT;
1154                         break;
1155                 case I40E_NVM_LCB:
1156                         upd_cmd = I40E_NVMUPD_WRITE_LCB;
1157                         break;
1158                 case I40E_NVM_SA:
1159                         upd_cmd = I40E_NVMUPD_WRITE_SA;
1160                         break;
1161                 case I40E_NVM_ERA:
1162                         upd_cmd = I40E_NVMUPD_WRITE_ERA;
1163                         break;
1164                 case I40E_NVM_CSUM:
1165                         upd_cmd = I40E_NVMUPD_CSUM_CON;
1166                         break;
1167                 case (I40E_NVM_CSUM|I40E_NVM_SA):
1168                         upd_cmd = I40E_NVMUPD_CSUM_SA;
1169                         break;
1170                 case (I40E_NVM_CSUM|I40E_NVM_LCB):
1171                         upd_cmd = I40E_NVMUPD_CSUM_LCB;
1172                         break;
1173                 case I40E_NVM_EXEC:
1174                         if (module == 0)
1175                                 upd_cmd = I40E_NVMUPD_EXEC_AQ;
1176                         break;
1177                 }
1178                 break;
1179         }
1180
1181         return upd_cmd;
1182 }
1183
1184 /**
1185  * i40e_nvmupd_exec_aq - Run an AQ command
1186  * @hw: pointer to hardware structure
1187  * @cmd: pointer to nvm update command buffer
1188  * @bytes: pointer to the data buffer
1189  * @perrno: pointer to return error code
1190  *
1191  * cmd structure contains identifiers and data buffer
1192  **/
1193 static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw,
1194                                        struct i40e_nvm_access *cmd,
1195                                        u8 *bytes, int *perrno)
1196 {
1197         struct i40e_asq_cmd_details cmd_details;
1198         i40e_status status;
1199         struct i40e_aq_desc *aq_desc;
1200         u32 buff_size = 0;
1201         u8 *buff = NULL;
1202         u32 aq_desc_len;
1203         u32 aq_data_len;
1204
1205         i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1206         memset(&cmd_details, 0, sizeof(cmd_details));
1207         cmd_details.wb_desc = &hw->nvm_wb_desc;
1208
1209         aq_desc_len = sizeof(struct i40e_aq_desc);
1210         memset(&hw->nvm_wb_desc, 0, aq_desc_len);
1211
1212         /* get the aq descriptor */
1213         if (cmd->data_size < aq_desc_len) {
1214                 i40e_debug(hw, I40E_DEBUG_NVM,
1215                            "NVMUPD: not enough aq desc bytes for exec, size %d < %d\n",
1216                            cmd->data_size, aq_desc_len);
1217                 *perrno = -EINVAL;
1218                 return I40E_ERR_PARAM;
1219         }
1220         aq_desc = (struct i40e_aq_desc *)bytes;
1221
1222         /* if data buffer needed, make sure it's ready */
1223         aq_data_len = cmd->data_size - aq_desc_len;
1224         buff_size = max_t(u32, aq_data_len, le16_to_cpu(aq_desc->datalen));
1225         if (buff_size) {
1226                 if (!hw->nvm_buff.va) {
1227                         status = i40e_allocate_virt_mem(hw, &hw->nvm_buff,
1228                                                         hw->aq.asq_buf_size);
1229                         if (status)
1230                                 i40e_debug(hw, I40E_DEBUG_NVM,
1231                                            "NVMUPD: i40e_allocate_virt_mem for exec buff failed, %d\n",
1232                                            status);
1233                 }
1234
1235                 if (hw->nvm_buff.va) {
1236                         buff = hw->nvm_buff.va;
1237                         memcpy(buff, &bytes[aq_desc_len], aq_data_len);
1238                 }
1239         }
1240
1241         /* and away we go! */
1242         status = i40e_asq_send_command(hw, aq_desc, buff,
1243                                        buff_size, &cmd_details);
1244         if (status) {
1245                 i40e_debug(hw, I40E_DEBUG_NVM,
1246                            "i40e_nvmupd_exec_aq err %s aq_err %s\n",
1247                            i40e_stat_str(hw, status),
1248                            i40e_aq_str(hw, hw->aq.asq_last_status));
1249                 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1250         }
1251
1252         /* should we wait for a followup event? */
1253         if (cmd->offset) {
1254                 hw->nvm_wait_opcode = cmd->offset;
1255                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1256         }
1257
1258         return status;
1259 }
1260
1261 /**
1262  * i40e_nvmupd_get_aq_result - Get the results from the previous exec_aq
1263  * @hw: pointer to hardware structure
1264  * @cmd: pointer to nvm update command buffer
1265  * @bytes: pointer to the data buffer
1266  * @perrno: pointer to return error code
1267  *
1268  * cmd structure contains identifiers and data buffer
1269  **/
1270 static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
1271                                              struct i40e_nvm_access *cmd,
1272                                              u8 *bytes, int *perrno)
1273 {
1274         u32 aq_total_len;
1275         u32 aq_desc_len;
1276         int remainder;
1277         u8 *buff;
1278
1279         i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1280
1281         aq_desc_len = sizeof(struct i40e_aq_desc);
1282         aq_total_len = aq_desc_len + le16_to_cpu(hw->nvm_wb_desc.datalen);
1283
1284         /* check offset range */
1285         if (cmd->offset > aq_total_len) {
1286                 i40e_debug(hw, I40E_DEBUG_NVM, "%s: offset too big %d > %d\n",
1287                            __func__, cmd->offset, aq_total_len);
1288                 *perrno = -EINVAL;
1289                 return I40E_ERR_PARAM;
1290         }
1291
1292         /* check copylength range */
1293         if (cmd->data_size > (aq_total_len - cmd->offset)) {
1294                 int new_len = aq_total_len - cmd->offset;
1295
1296                 i40e_debug(hw, I40E_DEBUG_NVM, "%s: copy length %d too big, trimming to %d\n",
1297                            __func__, cmd->data_size, new_len);
1298                 cmd->data_size = new_len;
1299         }
1300
1301         remainder = cmd->data_size;
1302         if (cmd->offset < aq_desc_len) {
1303                 u32 len = aq_desc_len - cmd->offset;
1304
1305                 len = min(len, cmd->data_size);
1306                 i40e_debug(hw, I40E_DEBUG_NVM, "%s: aq_desc bytes %d to %d\n",
1307                            __func__, cmd->offset, cmd->offset + len);
1308
1309                 buff = ((u8 *)&hw->nvm_wb_desc) + cmd->offset;
1310                 memcpy(bytes, buff, len);
1311
1312                 bytes += len;
1313                 remainder -= len;
1314                 buff = hw->nvm_buff.va;
1315         } else {
1316                 buff = hw->nvm_buff.va + (cmd->offset - aq_desc_len);
1317         }
1318
1319         if (remainder > 0) {
1320                 int start_byte = buff - (u8 *)hw->nvm_buff.va;
1321
1322                 i40e_debug(hw, I40E_DEBUG_NVM, "%s: databuf bytes %d to %d\n",
1323                            __func__, start_byte, start_byte + remainder);
1324                 memcpy(bytes, buff, remainder);
1325         }
1326
1327         return 0;
1328 }
1329
1330 /**
1331  * i40e_nvmupd_nvm_read - Read NVM
1332  * @hw: pointer to hardware structure
1333  * @cmd: pointer to nvm update command buffer
1334  * @bytes: pointer to the data buffer
1335  * @perrno: pointer to return error code
1336  *
1337  * cmd structure contains identifiers and data buffer
1338  **/
1339 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw,
1340                                         struct i40e_nvm_access *cmd,
1341                                         u8 *bytes, int *perrno)
1342 {
1343         struct i40e_asq_cmd_details cmd_details;
1344         i40e_status status;
1345         u8 module, transaction;
1346         bool last;
1347
1348         transaction = i40e_nvmupd_get_transaction(cmd->config);
1349         module = i40e_nvmupd_get_module(cmd->config);
1350         last = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA);
1351
1352         memset(&cmd_details, 0, sizeof(cmd_details));
1353         cmd_details.wb_desc = &hw->nvm_wb_desc;
1354
1355         status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
1356                                   bytes, last, &cmd_details);
1357         if (status) {
1358                 i40e_debug(hw, I40E_DEBUG_NVM,
1359                            "i40e_nvmupd_nvm_read mod 0x%x  off 0x%x  len 0x%x\n",
1360                            module, cmd->offset, cmd->data_size);
1361                 i40e_debug(hw, I40E_DEBUG_NVM,
1362                            "i40e_nvmupd_nvm_read status %d aq %d\n",
1363                            status, hw->aq.asq_last_status);
1364                 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1365         }
1366
1367         return status;
1368 }
1369
1370 /**
1371  * i40e_nvmupd_nvm_erase - Erase an NVM module
1372  * @hw: pointer to hardware structure
1373  * @cmd: pointer to nvm update command buffer
1374  * @perrno: pointer to return error code
1375  *
1376  * module, offset, data_size and data are in cmd structure
1377  **/
1378 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
1379                                          struct i40e_nvm_access *cmd,
1380                                          int *perrno)
1381 {
1382         i40e_status status = 0;
1383         struct i40e_asq_cmd_details cmd_details;
1384         u8 module, transaction;
1385         bool last;
1386
1387         transaction = i40e_nvmupd_get_transaction(cmd->config);
1388         module = i40e_nvmupd_get_module(cmd->config);
1389         last = (transaction & I40E_NVM_LCB);
1390
1391         memset(&cmd_details, 0, sizeof(cmd_details));
1392         cmd_details.wb_desc = &hw->nvm_wb_desc;
1393
1394         status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
1395                                    last, &cmd_details);
1396         if (status) {
1397                 i40e_debug(hw, I40E_DEBUG_NVM,
1398                            "i40e_nvmupd_nvm_erase mod 0x%x  off 0x%x len 0x%x\n",
1399                            module, cmd->offset, cmd->data_size);
1400                 i40e_debug(hw, I40E_DEBUG_NVM,
1401                            "i40e_nvmupd_nvm_erase status %d aq %d\n",
1402                            status, hw->aq.asq_last_status);
1403                 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1404         }
1405
1406         return status;
1407 }
1408
1409 /**
1410  * i40e_nvmupd_nvm_write - Write NVM
1411  * @hw: pointer to hardware structure
1412  * @cmd: pointer to nvm update command buffer
1413  * @bytes: pointer to the data buffer
1414  * @perrno: pointer to return error code
1415  *
1416  * module, offset, data_size and data are in cmd structure
1417  **/
1418 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw,
1419                                          struct i40e_nvm_access *cmd,
1420                                          u8 *bytes, int *perrno)
1421 {
1422         i40e_status status = 0;
1423         struct i40e_asq_cmd_details cmd_details;
1424         u8 module, transaction;
1425         bool last;
1426
1427         transaction = i40e_nvmupd_get_transaction(cmd->config);
1428         module = i40e_nvmupd_get_module(cmd->config);
1429         last = (transaction & I40E_NVM_LCB);
1430
1431         memset(&cmd_details, 0, sizeof(cmd_details));
1432         cmd_details.wb_desc = &hw->nvm_wb_desc;
1433
1434         status = i40e_aq_update_nvm(hw, module, cmd->offset,
1435                                     (u16)cmd->data_size, bytes, last,
1436                                     &cmd_details);
1437         if (status) {
1438                 i40e_debug(hw, I40E_DEBUG_NVM,
1439                            "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n",
1440                            module, cmd->offset, cmd->data_size);
1441                 i40e_debug(hw, I40E_DEBUG_NVM,
1442                            "i40e_nvmupd_nvm_write status %d aq %d\n",
1443                            status, hw->aq.asq_last_status);
1444                 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1445         }
1446
1447         return status;
1448 }