drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  * 82579LM Gigabit Network Connection
  56  * 82579V Gigabit Network Connection
  57  */
  58
  59 #include "e1000.h"
  60
  61 #define ICH_FLASH_GFPREG                0x0000
  62 #define ICH_FLASH_HSFSTS                0x0004
  63 #define ICH_FLASH_HSFCTL                0x0006
  64 #define ICH_FLASH_FADDR                 0x0008
  65 #define ICH_FLASH_FDATA0                0x0010
  66 #define ICH_FLASH_PR0                   0x0074
  67
  68 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  71 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  72 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  73
  74 #define ICH_CYCLE_READ                  0
  75 #define ICH_CYCLE_WRITE                 2
  76 #define ICH_CYCLE_ERASE                 3
  77
  78 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  79 #define FLASH_SECTOR_ADDR_SHIFT         12
  80
  81 #define ICH_FLASH_SEG_SIZE_256          256
  82 #define ICH_FLASH_SEG_SIZE_4K           4096
  83 #define ICH_FLASH_SEG_SIZE_8K           8192
  84 #define ICH_FLASH_SEG_SIZE_64K          65536
  85
  86
  87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  88 /* FW established a valid mode */
  89 #define E1000_ICH_FWSM_FW_VALID         0x00008000
  90
  91 #define E1000_ICH_MNG_IAMT_MODE         0x2
  92
  93 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  94                                  (ID_LED_DEF1_OFF2 <<  8) | \
  95                                  (ID_LED_DEF1_ON2  <<  4) | \
  96                                  (ID_LED_DEF1_DEF2))
  97
  98 #define E1000_ICH_NVM_SIG_WORD          0x13
  99 #define E1000_ICH_NVM_SIG_MASK          0xC000
 100 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 101 #define E1000_ICH_NVM_SIG_VALUE         0x80
 102
 103 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 104
 105 #define E1000_FEXTNVM_SW_CONFIG         1
 106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 107
 108 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK    0x0C000000
 109 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC  0x08000000
 110
 111 #define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
 112 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
 113 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
 114
 115 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 116
 117 #define E1000_ICH_RAR_ENTRIES           7
 118 #define E1000_PCH2_RAR_ENTRIES          5 /* RAR[0], SHRA[0-3] */
 119
 120 #define PHY_PAGE_SHIFT 5
 121 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 122                            ((reg) & MAX_PHY_REG_ADDRESS))
 123 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 124 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 125
 126 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 127 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 128 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 129
 130 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 131
 132 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 133
 134 /* SMBus Address Phy Register */
 135 #define HV_SMB_ADDR            PHY_REG(768, 26)
 136 #define HV_SMB_ADDR_MASK       0x007F
 137 #define HV_SMB_ADDR_PEC_EN     0x0200
 138 #define HV_SMB_ADDR_VALID      0x0080
 139
 140 /* PHY Power Management Control */
 141 #define HV_PM_CTRL              PHY_REG(770, 17)
 142 #define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA  0x100
 143
 144 /* PHY Low Power Idle Control */
 145 #define I82579_LPI_CTRL                         PHY_REG(772, 20)
 146 #define I82579_LPI_CTRL_ENABLE_MASK             0x6000
 147 #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT    0x80
 148
 149 /* EMI Registers */
 150 #define I82579_EMI_ADDR         0x10
 151 #define I82579_EMI_DATA         0x11
 152 #define I82579_LPI_UPDATE_TIMER 0x4805  /* in 40ns units + 40 ns base value */
 153 #define I82579_MSE_THRESHOLD    0x084F  /* Mean Square Error Threshold */
 154 #define I82579_MSE_LINK_DOWN    0x2411  /* MSE count before dropping link */
 155
 156 /* Strapping Option Register - RO */
 157 #define E1000_STRAP                     0x0000C
 158 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 159 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 160
 161 /* OEM Bits Phy Register */
 162 #define HV_OEM_BITS            PHY_REG(768, 25)
 163 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 164 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 165 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 166
 167 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 168 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 169
 170 /* KMRN Mode Control */
 171 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
 172 #define HV_KMRN_MDIO_SLOW      0x0400
 173
 174 /* KMRN FIFO Control and Status */
 175 #define HV_KMRN_FIFO_CTRLSTA                  PHY_REG(770, 16)
 176 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK    0x7000
 177 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT   12
 178
 179 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 180 /* Offset 04h HSFSTS */
 181 union ich8_hws_flash_status {
 182         struct ich8_hsfsts {
 183                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 184                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 185                 u16 dael       :1; /* bit 2 Direct Access error Log */
 186                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 187                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 188                 u16 reserved1  :2; /* bit 13:6 Reserved */
 189                 u16 reserved2  :6; /* bit 13:6 Reserved */
 190                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 191                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 192         } hsf_status;
 193         u16 regval;
 194 };
 195
 196 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 197 /* Offset 06h FLCTL */
 198 union ich8_hws_flash_ctrl {
 199         struct ich8_hsflctl {
 200                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 201                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 202                 u16 reserved   :5;   /* 7:3 Reserved  */
 203                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 204                 u16 flockdn    :6;   /* 15:10 Reserved */
 205         } hsf_ctrl;
 206         u16 regval;
 207 };
 208
 209 /* ICH Flash Region Access Permissions */
 210 union ich8_hws_flash_regacc {
 211         struct ich8_flracc {
 212                 u32 grra      :8; /* 0:7 GbE region Read Access */
 213                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 214                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 215                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 216         } hsf_flregacc;
 217         u16 regval;
 218 };
 219
 220 /* ICH Flash Protected Region */
 221 union ich8_flash_protected_range {
 222         struct ich8_pr {
 223                 u32 base:13;     /* 0:12 Protected Range Base */
 224                 u32 reserved1:2; /* 13:14 Reserved */
 225                 u32 rpe:1;       /* 15 Read Protection Enable */
 226                 u32 limit:13;    /* 16:28 Protected Range Limit */
 227                 u32 reserved2:2; /* 29:30 Reserved */
 228                 u32 wpe:1;       /* 31 Write Protection Enable */
 229         } range;
 230         u32 regval;
 231 };
 232
 233 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 234 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 235 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 236 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 237 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 238                                                 u32 offset, u8 byte);
 239 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 240                                          u8 *data);
 241 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 242                                          u16 *data);
 243 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 244                                          u8 size, u16 *data);
 245 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 246 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 247 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 248 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 249 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 250 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 251 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 252 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 253 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 254 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 255 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 256 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 257 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 258 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 259 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 260 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 261 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 262 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 263 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 264 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 265 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 266
 267 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 268 {
 269         return readw(hw->flash_address + reg);
 270 }
 271
 272 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 273 {
 274         return readl(hw->flash_address + reg);
 275 }
 276
 277 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 278 {
 279         writew(val, hw->flash_address + reg);
 280 }
 281
 282 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 283 {
 284         writel(val, hw->flash_address + reg);
 285 }
 286
 287 #define er16flash(reg)          __er16flash(hw, (reg))
 288 #define er32flash(reg)          __er32flash(hw, (reg))
 289 #define ew16flash(reg, val)     __ew16flash(hw, (reg), (val))
 290 #define ew32flash(reg, val)     __ew32flash(hw, (reg), (val))
 291
 292 /**
 293  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 294  *  @hw: pointer to the HW structure
 295  *
 296  *  Test access to the PHY registers by reading the PHY ID registers.  If
 297  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 298  *  otherwise assume the read PHY ID is correct if it is valid.
 299  *
 300  *  Assumes the sw/fw/hw semaphore is already acquired.
 301  **/
 302 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 303 {
 304         u16 phy_reg;
 305         u32 phy_id;
 306
 307         hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
 308         phy_id = (u32)(phy_reg << 16);
 309         hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
 310         phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 311
 312         if (hw->phy.id) {
 313                 if (hw->phy.id == phy_id)
 314                         return true;
 315         } else {
 316                 if ((phy_id != 0) && (phy_id != PHY_REVISION_MASK))
 317                         hw->phy.id = phy_id;
 318                 return true;
 319         }
 320
 321         return false;
 322 }
 323
 324 /**
 325  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 326  *  @hw: pointer to the HW structure
 327  *
 328  *  Workarounds/flow necessary for PHY initialization during driver load
 329  *  and resume paths.
 330  **/
 331 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 332 {
 333         u32 mac_reg, fwsm = er32(FWSM);
 334         s32 ret_val;
 335
 336         ret_val = hw->phy.ops.acquire(hw);
 337         if (ret_val) {
 338                 e_dbg("Failed to initialize PHY flow\n");
 339                 return ret_val;
 340         }
 341
 342         /*
 343          * The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 344          * inaccessible and resetting the PHY is not blocked, toggle the
 345          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 346          */
 347         switch (hw->mac.type) {
 348         case e1000_pch2lan:
 349                 /*
 350                  * Gate automatic PHY configuration by hardware on
 351                  * non-managed 82579
 352                  */
 353                 if (!(fwsm & E1000_ICH_FWSM_FW_VALID))
 354                         e1000_gate_hw_phy_config_ich8lan(hw, true);
 355
 356                 if (e1000_phy_is_accessible_pchlan(hw))
 357                         break;
 358
 359                 /* fall-through */
 360         case e1000_pchlan:
 361                 if ((hw->mac.type == e1000_pchlan) &&
 362                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 363                         break;
 364
 365                 if (hw->phy.ops.check_reset_block(hw)) {
 366                         e_dbg("Required LANPHYPC toggle blocked by ME\n");
 367                         break;
 368                 }
 369
 370                 e_dbg("Toggling LANPHYPC\n");
 371
 372                 /* Set Phy Config Counter to 50msec */
 373                 mac_reg = er32(FEXTNVM3);
 374                 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 375                 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 376                 ew32(FEXTNVM3, mac_reg);
 377
 378                 /* Toggle LANPHYPC Value bit */
 379                 mac_reg = er32(CTRL);
 380                 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 381                 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 382                 ew32(CTRL, mac_reg);
 383                 e1e_flush();
 384                 udelay(10);
 385                 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 386                 ew32(CTRL, mac_reg);
 387                 e1e_flush();
 388                 msleep(50);
 389                 break;
 390         default:
 391                 break;
 392         }
 393
 394         hw->phy.ops.release(hw);
 395
 396         /*
 397          * Reset the PHY before any access to it.  Doing so, ensures
 398          * that the PHY is in a known good state before we read/write
 399          * PHY registers.  The generic reset is sufficient here,
 400          * because we haven't determined the PHY type yet.
 401          */
 402         ret_val = e1000e_phy_hw_reset_generic(hw);
 403
 404         /* Ungate automatic PHY configuration on non-managed 82579 */
 405         if ((hw->mac.type == e1000_pch2lan) &&
 406             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 407                 usleep_range(10000, 20000);
 408                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 409         }
 410
 411         return ret_val;
 412 }
 413
 414 /**
 415  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 416  *  @hw: pointer to the HW structure
 417  *
 418  *  Initialize family-specific PHY parameters and function pointers.
 419  **/
 420 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 421 {
 422         struct e1000_phy_info *phy = &hw->phy;
 423         s32 ret_val = 0;
 424
 425         phy->addr                     = 1;
 426         phy->reset_delay_us           = 100;
 427
 428         phy->ops.set_page             = e1000_set_page_igp;
 429         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 430         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 431         phy->ops.read_reg_page        = e1000_read_phy_reg_page_hv;
 432         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 433         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 434         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 435         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 436         phy->ops.write_reg_page       = e1000_write_phy_reg_page_hv;
 437         phy->ops.power_up             = e1000_power_up_phy_copper;
 438         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 439         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 440
 441         phy->id = e1000_phy_unknown;
 442
 443         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 444         if (ret_val)
 445                 return ret_val;
 446
 447         if (phy->id == e1000_phy_unknown)
 448                 switch (hw->mac.type) {
 449                 default:
 450                         ret_val = e1000e_get_phy_id(hw);
 451                         if (ret_val)
 452                                 return ret_val;
 453                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 454                                 break;
 455                         /* fall-through */
 456                 case e1000_pch2lan:
 457                         /*
 458                          * In case the PHY needs to be in mdio slow mode,
 459                          * set slow mode and try to get the PHY id again.
 460                          */
 461                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 462                         if (ret_val)
 463                                 return ret_val;
 464                         ret_val = e1000e_get_phy_id(hw);
 465                         if (ret_val)
 466                                 return ret_val;
 467                         break;
 468                 }
 469         phy->type = e1000e_get_phy_type_from_id(phy->id);
 470
 471         switch (phy->type) {
 472         case e1000_phy_82577:
 473         case e1000_phy_82579:
 474                 phy->ops.check_polarity = e1000_check_polarity_82577;
 475                 phy->ops.force_speed_duplex =
 476                     e1000_phy_force_speed_duplex_82577;
 477                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 478                 phy->ops.get_info = e1000_get_phy_info_82577;
 479                 phy->ops.commit = e1000e_phy_sw_reset;
 480                 break;
 481         case e1000_phy_82578:
 482                 phy->ops.check_polarity = e1000_check_polarity_m88;
 483                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 484                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 485                 phy->ops.get_info = e1000e_get_phy_info_m88;
 486                 break;
 487         default:
 488                 ret_val = -E1000_ERR_PHY;
 489                 break;
 490         }
 491
 492         return ret_val;
 493 }
 494
 495 /**
 496  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 497  *  @hw: pointer to the HW structure
 498  *
 499  *  Initialize family-specific PHY parameters and function pointers.
 500  **/
 501 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 502 {
 503         struct e1000_phy_info *phy = &hw->phy;
 504         s32 ret_val;
 505         u16 i = 0;
 506
 507         phy->addr                       = 1;
 508         phy->reset_delay_us             = 100;
 509
 510         phy->ops.power_up               = e1000_power_up_phy_copper;
 511         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 512
 513         /*
 514          * We may need to do this twice - once for IGP and if that fails,
 515          * we'll set BM func pointers and try again
 516          */
 517         ret_val = e1000e_determine_phy_address(hw);
 518         if (ret_val) {
 519                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 520                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 521                 ret_val = e1000e_determine_phy_address(hw);
 522                 if (ret_val) {
 523                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 524                         return ret_val;
 525                 }
 526         }
 527
 528         phy->id = 0;
 529         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 530                (i++ < 100)) {
 531                 usleep_range(1000, 2000);
 532                 ret_val = e1000e_get_phy_id(hw);
 533                 if (ret_val)
 534                         return ret_val;
 535         }
 536
 537         /* Verify phy id */
 538         switch (phy->id) {
 539         case IGP03E1000_E_PHY_ID:
 540                 phy->type = e1000_phy_igp_3;
 541                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 542                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 543                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 544                 phy->ops.get_info = e1000e_get_phy_info_igp;
 545                 phy->ops.check_polarity = e1000_check_polarity_igp;
 546                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 547                 break;
 548         case IFE_E_PHY_ID:
 549         case IFE_PLUS_E_PHY_ID:
 550         case IFE_C_E_PHY_ID:
 551                 phy->type = e1000_phy_ife;
 552                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 553                 phy->ops.get_info = e1000_get_phy_info_ife;
 554                 phy->ops.check_polarity = e1000_check_polarity_ife;
 555                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 556                 break;
 557         case BME1000_E_PHY_ID:
 558                 phy->type = e1000_phy_bm;
 559                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 560                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 561                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 562                 phy->ops.commit = e1000e_phy_sw_reset;
 563                 phy->ops.get_info = e1000e_get_phy_info_m88;
 564                 phy->ops.check_polarity = e1000_check_polarity_m88;
 565                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 566                 break;
 567         default:
 568                 return -E1000_ERR_PHY;
 569                 break;
 570         }
 571
 572         return 0;
 573 }
 574
 575 /**
 576  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 577  *  @hw: pointer to the HW structure
 578  *
 579  *  Initialize family-specific NVM parameters and function
 580  *  pointers.
 581  **/
 582 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 583 {
 584         struct e1000_nvm_info *nvm = &hw->nvm;
 585         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 586         u32 gfpreg, sector_base_addr, sector_end_addr;
 587         u16 i;
 588
 589         /* Can't read flash registers if the register set isn't mapped. */
 590         if (!hw->flash_address) {
 591                 e_dbg("ERROR: Flash registers not mapped\n");
 592                 return -E1000_ERR_CONFIG;
 593         }
 594
 595         nvm->type = e1000_nvm_flash_sw;
 596
 597         gfpreg = er32flash(ICH_FLASH_GFPREG);
 598
 599         /*
 600          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 601          * Add 1 to sector_end_addr since this sector is included in
 602          * the overall size.
 603          */
 604         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 605         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 606
 607         /* flash_base_addr is byte-aligned */
 608         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 609
 610         /*
 611          * find total size of the NVM, then cut in half since the total
 612          * size represents two separate NVM banks.
 613          */
 614         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 615                                 << FLASH_SECTOR_ADDR_SHIFT;
 616         nvm->flash_bank_size /= 2;
 617         /* Adjust to word count */
 618         nvm->flash_bank_size /= sizeof(u16);
 619
 620         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 621
 622         /* Clear shadow ram */
 623         for (i = 0; i < nvm->word_size; i++) {
 624                 dev_spec->shadow_ram[i].modified = false;
 625                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 626         }
 627
 628         return 0;
 629 }
 630
 631 /**
 632  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 633  *  @hw: pointer to the HW structure
 634  *
 635  *  Initialize family-specific MAC parameters and function
 636  *  pointers.
 637  **/
 638 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 639 {
 640         struct e1000_mac_info *mac = &hw->mac;
 641
 642         /* Set media type function pointer */
 643         hw->phy.media_type = e1000_media_type_copper;
 644
 645         /* Set mta register count */
 646         mac->mta_reg_count = 32;
 647         /* Set rar entry count */
 648         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 649         if (mac->type == e1000_ich8lan)
 650                 mac->rar_entry_count--;
 651         /* FWSM register */
 652         mac->has_fwsm = true;
 653         /* ARC subsystem not supported */
 654         mac->arc_subsystem_valid = false;
 655         /* Adaptive IFS supported */
 656         mac->adaptive_ifs = true;
 657
 658         /* LED operations */
 659         switch (mac->type) {
 660         case e1000_ich8lan:
 661         case e1000_ich9lan:
 662         case e1000_ich10lan:
 663                 /* check management mode */
 664                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 665                 /* ID LED init */
 666                 mac->ops.id_led_init = e1000e_id_led_init_generic;
 667                 /* blink LED */
 668                 mac->ops.blink_led = e1000e_blink_led_generic;
 669                 /* setup LED */
 670                 mac->ops.setup_led = e1000e_setup_led_generic;
 671                 /* cleanup LED */
 672                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 673                 /* turn on/off LED */
 674                 mac->ops.led_on = e1000_led_on_ich8lan;
 675                 mac->ops.led_off = e1000_led_off_ich8lan;
 676                 break;
 677         case e1000_pch2lan:
 678                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 679                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 680                 /* fall-through */
 681         case e1000_pchlan:
 682                 /* check management mode */
 683                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 684                 /* ID LED init */
 685                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 686                 /* setup LED */
 687                 mac->ops.setup_led = e1000_setup_led_pchlan;
 688                 /* cleanup LED */
 689                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 690                 /* turn on/off LED */
 691                 mac->ops.led_on = e1000_led_on_pchlan;
 692                 mac->ops.led_off = e1000_led_off_pchlan;
 693                 break;
 694         default:
 695                 break;
 696         }
 697
 698         /* Enable PCS Lock-loss workaround for ICH8 */
 699         if (mac->type == e1000_ich8lan)
 700                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 701
 702         /* Gate automatic PHY configuration by hardware on managed 82579 */
 703         if ((mac->type == e1000_pch2lan) &&
 704             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 705                 e1000_gate_hw_phy_config_ich8lan(hw, true);
 706
 707         return 0;
 708 }
 709
 710 /**
 711  *  e1000_set_eee_pchlan - Enable/disable EEE support
 712  *  @hw: pointer to the HW structure
 713  *
 714  *  Enable/disable EEE based on setting in dev_spec structure.  The bits in
 715  *  the LPI Control register will remain set only if/when link is up.
 716  **/
 717 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 718 {
 719         s32 ret_val = 0;
 720         u16 phy_reg;
 721
 722         if (hw->phy.type != e1000_phy_82579)
 723                 return 0;
 724
 725         ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
 726         if (ret_val)
 727                 return ret_val;
 728
 729         if (hw->dev_spec.ich8lan.eee_disable)
 730                 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
 731         else
 732                 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
 733
 734         return e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
 735 }
 736
 737 /**
 738  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 739  *  @hw: pointer to the HW structure
 740  *
 741  *  Checks to see of the link status of the hardware has changed.  If a
 742  *  change in link status has been detected, then we read the PHY registers
 743  *  to get the current speed/duplex if link exists.
 744  **/
 745 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 746 {
 747         struct e1000_mac_info *mac = &hw->mac;
 748         s32 ret_val;
 749         bool link;
 750         u16 phy_reg;
 751
 752         /*
 753          * We only want to go out to the PHY registers to see if Auto-Neg
 754          * has completed and/or if our link status has changed.  The
 755          * get_link_status flag is set upon receiving a Link Status
 756          * Change or Rx Sequence Error interrupt.
 757          */
 758         if (!mac->get_link_status)
 759                 return 0;
 760
 761         /*
 762          * First we want to see if the MII Status Register reports
 763          * link.  If so, then we want to get the current speed/duplex
 764          * of the PHY.
 765          */
 766         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 767         if (ret_val)
 768                 return ret_val;
 769
 770         if (hw->mac.type == e1000_pchlan) {
 771                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 772                 if (ret_val)
 773                         return ret_val;
 774         }
 775
 776         if (!link)
 777                 return 0; /* No link detected */
 778
 779         mac->get_link_status = false;
 780
 781         switch (hw->mac.type) {
 782         case e1000_pch2lan:
 783                 ret_val = e1000_k1_workaround_lv(hw);
 784                 if (ret_val)
 785                         return ret_val;
 786                 /* fall-thru */
 787         case e1000_pchlan:
 788                 if (hw->phy.type == e1000_phy_82578) {
 789                         ret_val = e1000_link_stall_workaround_hv(hw);
 790                         if (ret_val)
 791                                 return ret_val;
 792                 }
 793
 794                 /*
 795                  * Workaround for PCHx parts in half-duplex:
 796                  * Set the number of preambles removed from the packet
 797                  * when it is passed from the PHY to the MAC to prevent
 798                  * the MAC from misinterpreting the packet type.
 799                  */
 800                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
 801                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
 802
 803                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
 804                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
 805
 806                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
 807                 break;
 808         default:
 809                 break;
 810         }
 811
 812         /*
 813          * Check if there was DownShift, must be checked
 814          * immediately after link-up
 815          */
 816         e1000e_check_downshift(hw);
 817
 818         /* Enable/Disable EEE after link up */
 819         ret_val = e1000_set_eee_pchlan(hw);
 820         if (ret_val)
 821                 return ret_val;
 822
 823         /*
 824          * If we are forcing speed/duplex, then we simply return since
 825          * we have already determined whether we have link or not.
 826          */
 827         if (!mac->autoneg)
 828                 return -E1000_ERR_CONFIG;
 829
 830         /*
 831          * Auto-Neg is enabled.  Auto Speed Detection takes care
 832          * of MAC speed/duplex configuration.  So we only need to
 833          * configure Collision Distance in the MAC.
 834          */
 835         mac->ops.config_collision_dist(hw);
 836
 837         /*
 838          * Configure Flow Control now that Auto-Neg has completed.
 839          * First, we need to restore the desired flow control
 840          * settings because we may have had to re-autoneg with a
 841          * different link partner.
 842          */
 843         ret_val = e1000e_config_fc_after_link_up(hw);
 844         if (ret_val)
 845                 e_dbg("Error configuring flow control\n");
 846
 847         return ret_val;
 848 }
 849
 850 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 851 {
 852         struct e1000_hw *hw = &adapter->hw;
 853         s32 rc;
 854
 855         rc = e1000_init_mac_params_ich8lan(hw);
 856         if (rc)
 857                 return rc;
 858
 859         rc = e1000_init_nvm_params_ich8lan(hw);
 860         if (rc)
 861                 return rc;
 862
 863         switch (hw->mac.type) {
 864         case e1000_ich8lan:
 865         case e1000_ich9lan:
 866         case e1000_ich10lan:
 867                 rc = e1000_init_phy_params_ich8lan(hw);
 868                 break;
 869         case e1000_pchlan:
 870         case e1000_pch2lan:
 871                 rc = e1000_init_phy_params_pchlan(hw);
 872                 break;
 873         default:
 874                 break;
 875         }
 876         if (rc)
 877                 return rc;
 878
 879         /*
 880          * Disable Jumbo Frame support on parts with Intel 10/100 PHY or
 881          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
 882          */
 883         if ((adapter->hw.phy.type == e1000_phy_ife) ||
 884             ((adapter->hw.mac.type >= e1000_pch2lan) &&
 885              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
 886                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 887                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 888
 889                 hw->mac.ops.blink_led = NULL;
 890         }
 891
 892         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 893             (adapter->hw.phy.type != e1000_phy_ife))
 894                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 895
 896         /* Enable workaround for 82579 w/ ME enabled */
 897         if ((adapter->hw.mac.type == e1000_pch2lan) &&
 898             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 899                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
 900
 901         /* Disable EEE by default until IEEE802.3az spec is finalized */
 902         if (adapter->flags2 & FLAG2_HAS_EEE)
 903                 adapter->hw.dev_spec.ich8lan.eee_disable = true;
 904
 905         return 0;
 906 }
 907
 908 static DEFINE_MUTEX(nvm_mutex);
 909
 910 /**
 911  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 912  *  @hw: pointer to the HW structure
 913  *
 914  *  Acquires the mutex for performing NVM operations.
 915  **/
 916 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 917 {
 918         mutex_lock(&nvm_mutex);
 919
 920         return 0;
 921 }
 922
 923 /**
 924  *  e1000_release_nvm_ich8lan - Release NVM mutex
 925  *  @hw: pointer to the HW structure
 926  *
 927  *  Releases the mutex used while performing NVM operations.
 928  **/
 929 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 930 {
 931         mutex_unlock(&nvm_mutex);
 932 }
 933
 934 /**
 935  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 936  *  @hw: pointer to the HW structure
 937  *
 938  *  Acquires the software control flag for performing PHY and select
 939  *  MAC CSR accesses.
 940  **/
 941 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 942 {
 943         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 944         s32 ret_val = 0;
 945
 946         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
 947                              &hw->adapter->state)) {
 948                 e_dbg("contention for Phy access\n");
 949                 return -E1000_ERR_PHY;
 950         }
 951
 952         while (timeout) {
 953                 extcnf_ctrl = er32(EXTCNF_CTRL);
 954                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 955                         break;
 956
 957                 mdelay(1);
 958                 timeout--;
 959         }
 960
 961         if (!timeout) {
 962                 e_dbg("SW has already locked the resource.\n");
 963                 ret_val = -E1000_ERR_CONFIG;
 964                 goto out;
 965         }
 966
 967         timeout = SW_FLAG_TIMEOUT;
 968
 969         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 970         ew32(EXTCNF_CTRL, extcnf_ctrl);
 971
 972         while (timeout) {
 973                 extcnf_ctrl = er32(EXTCNF_CTRL);
 974                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 975                         break;
 976
 977                 mdelay(1);
 978                 timeout--;
 979         }
 980
 981         if (!timeout) {
 982                 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
 983                       er32(FWSM), extcnf_ctrl);
 984                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 985                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 986                 ret_val = -E1000_ERR_CONFIG;
 987                 goto out;
 988         }
 989
 990 out:
 991         if (ret_val)
 992                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
 993
 994         return ret_val;
 995 }
 996
 997 /**
 998  *  e1000_release_swflag_ich8lan - Release software control flag
 999  *  @hw: pointer to the HW structure
1000  *
1001  *  Releases the software control flag for performing PHY and select
1002  *  MAC CSR accesses.
1003  **/
1004 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1005 {
1006         u32 extcnf_ctrl;
1007
1008         extcnf_ctrl = er32(EXTCNF_CTRL);
1009
1010         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1011                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1012                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1013         } else {
1014                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1015         }
1016
1017         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1018 }
1019
1020 /**
1021  *  e1000_check_mng_mode_ich8lan - Checks management mode
1022  *  @hw: pointer to the HW structure
1023  *
1024  *  This checks if the adapter has any manageability enabled.
1025  *  This is a function pointer entry point only called by read/write
1026  *  routines for the PHY and NVM parts.
1027  **/
1028 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1029 {
1030         u32 fwsm;
1031
1032         fwsm = er32(FWSM);
1033         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1034                ((fwsm & E1000_FWSM_MODE_MASK) ==
1035                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1036 }
1037
1038 /**
1039  *  e1000_check_mng_mode_pchlan - Checks management mode
1040  *  @hw: pointer to the HW structure
1041  *
1042  *  This checks if the adapter has iAMT enabled.
1043  *  This is a function pointer entry point only called by read/write
1044  *  routines for the PHY and NVM parts.
1045  **/
1046 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1047 {
1048         u32 fwsm;
1049
1050         fwsm = er32(FWSM);
1051         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1052                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1053 }
1054
1055 /**
1056  *  e1000_rar_set_pch2lan - Set receive address register
1057  *  @hw: pointer to the HW structure
1058  *  @addr: pointer to the receive address
1059  *  @index: receive address array register
1060  *
1061  *  Sets the receive address array register at index to the address passed
1062  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1063  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1064  *  Use SHRA[0-3] in place of those reserved for ME.
1065  **/
1066 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1067 {
1068         u32 rar_low, rar_high;
1069
1070         /*
1071          * HW expects these in little endian so we reverse the byte order
1072          * from network order (big endian) to little endian
1073          */
1074         rar_low = ((u32)addr[0] |
1075                    ((u32)addr[1] << 8) |
1076                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1077
1078         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1079
1080         /* If MAC address zero, no need to set the AV bit */
1081         if (rar_low || rar_high)
1082                 rar_high |= E1000_RAH_AV;
1083
1084         if (index == 0) {
1085                 ew32(RAL(index), rar_low);
1086                 e1e_flush();
1087                 ew32(RAH(index), rar_high);
1088                 e1e_flush();
1089                 return;
1090         }
1091
1092         if (index < hw->mac.rar_entry_count) {
1093                 s32 ret_val;
1094
1095                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1096                 if (ret_val)
1097                         goto out;
1098
1099                 ew32(SHRAL(index - 1), rar_low);
1100                 e1e_flush();
1101                 ew32(SHRAH(index - 1), rar_high);
1102                 e1e_flush();
1103
1104                 e1000_release_swflag_ich8lan(hw);
1105
1106                 /* verify the register updates */
1107                 if ((er32(SHRAL(index - 1)) == rar_low) &&
1108                     (er32(SHRAH(index - 1)) == rar_high))
1109                         return;
1110
1111                 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1112                       (index - 1), er32(FWSM));
1113         }
1114
1115 out:
1116         e_dbg("Failed to write receive address at index %d\n", index);
1117 }
1118
1119 /**
1120  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1121  *  @hw: pointer to the HW structure
1122  *
1123  *  Checks if firmware is blocking the reset of the PHY.
1124  *  This is a function pointer entry point only called by
1125  *  reset routines.
1126  **/
1127 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1128 {
1129         u32 fwsm;
1130
1131         fwsm = er32(FWSM);
1132
1133         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
1134 }
1135
1136 /**
1137  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1138  *  @hw: pointer to the HW structure
1139  *
1140  *  Assumes semaphore already acquired.
1141  *
1142  **/
1143 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1144 {
1145         u16 phy_data;
1146         u32 strap = er32(STRAP);
1147         s32 ret_val = 0;
1148
1149         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1150
1151         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1152         if (ret_val)
1153                 return ret_val;
1154
1155         phy_data &= ~HV_SMB_ADDR_MASK;
1156         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1157         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1158
1159         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1160 }
1161
1162 /**
1163  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1164  *  @hw:   pointer to the HW structure
1165  *
1166  *  SW should configure the LCD from the NVM extended configuration region
1167  *  as a workaround for certain parts.
1168  **/
1169 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1170 {
1171         struct e1000_phy_info *phy = &hw->phy;
1172         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1173         s32 ret_val = 0;
1174         u16 word_addr, reg_data, reg_addr, phy_page = 0;
1175
1176         /*
1177          * Initialize the PHY from the NVM on ICH platforms.  This
1178          * is needed due to an issue where the NVM configuration is
1179          * not properly autoloaded after power transitions.
1180          * Therefore, after each PHY reset, we will load the
1181          * configuration data out of the NVM manually.
1182          */
1183         switch (hw->mac.type) {
1184         case e1000_ich8lan:
1185                 if (phy->type != e1000_phy_igp_3)
1186                         return ret_val;
1187
1188                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1189                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1190                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1191                         break;
1192                 }
1193                 /* Fall-thru */
1194         case e1000_pchlan:
1195         case e1000_pch2lan:
1196                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1197                 break;
1198         default:
1199                 return ret_val;
1200         }
1201
1202         ret_val = hw->phy.ops.acquire(hw);
1203         if (ret_val)
1204                 return ret_val;
1205
1206         data = er32(FEXTNVM);
1207         if (!(data & sw_cfg_mask))
1208                 goto release;
1209
1210         /*
1211          * Make sure HW does not configure LCD from PHY
1212          * extended configuration before SW configuration
1213          */
1214         data = er32(EXTCNF_CTRL);
1215         if (!(hw->mac.type == e1000_pch2lan)) {
1216                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
1217                         goto release;
1218         }
1219
1220         cnf_size = er32(EXTCNF_SIZE);
1221         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1222         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1223         if (!cnf_size)
1224                 goto release;
1225
1226         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1227         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1228
1229         if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1230             (hw->mac.type == e1000_pchlan)) ||
1231              (hw->mac.type == e1000_pch2lan)) {
1232                 /*
1233                  * HW configures the SMBus address and LEDs when the
1234                  * OEM and LCD Write Enable bits are set in the NVM.
1235                  * When both NVM bits are cleared, SW will configure
1236                  * them instead.
1237                  */
1238                 ret_val = e1000_write_smbus_addr(hw);
1239                 if (ret_val)
1240                         goto release;
1241
1242                 data = er32(LEDCTL);
1243                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1244                                                         (u16)data);
1245                 if (ret_val)
1246                         goto release;
1247         }
1248
1249         /* Configure LCD from extended configuration region. */
1250
1251         /* cnf_base_addr is in DWORD */
1252         word_addr = (u16)(cnf_base_addr << 1);
1253
1254         for (i = 0; i < cnf_size; i++) {
1255                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1256                                          &reg_data);
1257                 if (ret_val)
1258                         goto release;
1259
1260                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1261                                          1, &reg_addr);
1262                 if (ret_val)
1263                         goto release;
1264
1265                 /* Save off the PHY page for future writes. */
1266                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1267                         phy_page = reg_data;
1268                         continue;
1269                 }
1270
1271                 reg_addr &= PHY_REG_MASK;
1272                 reg_addr |= phy_page;
1273
1274                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1275                                                     reg_data);
1276                 if (ret_val)
1277                         goto release;
1278         }
1279
1280 release:
1281         hw->phy.ops.release(hw);
1282         return ret_val;
1283 }
1284
1285 /**
1286  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1287  *  @hw:   pointer to the HW structure
1288  *  @link: link up bool flag
1289  *
1290  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1291  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1292  *  If link is down, the function will restore the default K1 setting located
1293  *  in the NVM.
1294  **/
1295 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1296 {
1297         s32 ret_val = 0;
1298         u16 status_reg = 0;
1299         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1300
1301         if (hw->mac.type != e1000_pchlan)
1302                 return 0;
1303
1304         /* Wrap the whole flow with the sw flag */
1305         ret_val = hw->phy.ops.acquire(hw);
1306         if (ret_val)
1307                 return ret_val;
1308
1309         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1310         if (link) {
1311                 if (hw->phy.type == e1000_phy_82578) {
1312                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1313                                                                   &status_reg);
1314                         if (ret_val)
1315                                 goto release;
1316
1317                         status_reg &= BM_CS_STATUS_LINK_UP |
1318                                       BM_CS_STATUS_RESOLVED |
1319                                       BM_CS_STATUS_SPEED_MASK;
1320
1321                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1322                                            BM_CS_STATUS_RESOLVED |
1323                                            BM_CS_STATUS_SPEED_1000))
1324                                 k1_enable = false;
1325                 }
1326
1327                 if (hw->phy.type == e1000_phy_82577) {
1328                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1329                                                                   &status_reg);
1330                         if (ret_val)
1331                                 goto release;
1332
1333                         status_reg &= HV_M_STATUS_LINK_UP |
1334                                       HV_M_STATUS_AUTONEG_COMPLETE |
1335                                       HV_M_STATUS_SPEED_MASK;
1336
1337                         if (status_reg == (HV_M_STATUS_LINK_UP |
1338                                            HV_M_STATUS_AUTONEG_COMPLETE |
1339                                            HV_M_STATUS_SPEED_1000))
1340                                 k1_enable = false;
1341                 }
1342
1343                 /* Link stall fix for link up */
1344                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1345                                                            0x0100);
1346                 if (ret_val)
1347                         goto release;
1348
1349         } else {
1350                 /* Link stall fix for link down */
1351                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1352                                                            0x4100);
1353                 if (ret_val)
1354                         goto release;
1355         }
1356
1357         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1358
1359 release:
1360         hw->phy.ops.release(hw);
1361
1362         return ret_val;
1363 }
1364
1365 /**
1366  *  e1000_configure_k1_ich8lan - Configure K1 power state
1367  *  @hw: pointer to the HW structure
1368  *  @enable: K1 state to configure
1369  *
1370  *  Configure the K1 power state based on the provided parameter.
1371  *  Assumes semaphore already acquired.
1372  *
1373  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1374  **/
1375 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1376 {
1377         s32 ret_val = 0;
1378         u32 ctrl_reg = 0;
1379         u32 ctrl_ext = 0;
1380         u32 reg = 0;
1381         u16 kmrn_reg = 0;
1382
1383         ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1384                                               &kmrn_reg);
1385         if (ret_val)
1386                 return ret_val;
1387
1388         if (k1_enable)
1389                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1390         else
1391                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1392
1393         ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1394                                                kmrn_reg);
1395         if (ret_val)
1396                 return ret_val;
1397
1398         udelay(20);
1399         ctrl_ext = er32(CTRL_EXT);
1400         ctrl_reg = er32(CTRL);
1401
1402         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1403         reg |= E1000_CTRL_FRCSPD;
1404         ew32(CTRL, reg);
1405
1406         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1407         e1e_flush();
1408         udelay(20);
1409         ew32(CTRL, ctrl_reg);
1410         ew32(CTRL_EXT, ctrl_ext);
1411         e1e_flush();
1412         udelay(20);
1413
1414         return 0;
1415 }
1416
1417 /**
1418  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1419  *  @hw:       pointer to the HW structure
1420  *  @d0_state: boolean if entering d0 or d3 device state
1421  *
1422  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1423  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1424  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1425  **/
1426 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1427 {
1428         s32 ret_val = 0;
1429         u32 mac_reg;
1430         u16 oem_reg;
1431
1432         if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1433                 return ret_val;
1434
1435         ret_val = hw->phy.ops.acquire(hw);
1436         if (ret_val)
1437                 return ret_val;
1438
1439         if (!(hw->mac.type == e1000_pch2lan)) {
1440                 mac_reg = er32(EXTCNF_CTRL);
1441                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1442                         goto release;
1443         }
1444
1445         mac_reg = er32(FEXTNVM);
1446         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1447                 goto release;
1448
1449         mac_reg = er32(PHY_CTRL);
1450
1451         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1452         if (ret_val)
1453                 goto release;
1454
1455         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1456
1457         if (d0_state) {
1458                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1459                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1460
1461                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1462                         oem_reg |= HV_OEM_BITS_LPLU;
1463         } else {
1464                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1465                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
1466                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1467
1468                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1469                                E1000_PHY_CTRL_NOND0A_LPLU))
1470                         oem_reg |= HV_OEM_BITS_LPLU;
1471         }
1472
1473         /* Set Restart auto-neg to activate the bits */
1474         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
1475             !hw->phy.ops.check_reset_block(hw))
1476                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1477
1478         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1479
1480 release:
1481         hw->phy.ops.release(hw);
1482
1483         return ret_val;
1484 }
1485
1486
1487 /**
1488  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1489  *  @hw:   pointer to the HW structure
1490  **/
1491 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1492 {
1493         s32 ret_val;
1494         u16 data;
1495
1496         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1497         if (ret_val)
1498                 return ret_val;
1499
1500         data |= HV_KMRN_MDIO_SLOW;
1501
1502         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1503
1504         return ret_val;
1505 }
1506
1507 /**
1508  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1509  *  done after every PHY reset.
1510  **/
1511 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1512 {
1513         s32 ret_val = 0;
1514         u16 phy_data;
1515
1516         if (hw->mac.type != e1000_pchlan)
1517                 return 0;
1518
1519         /* Set MDIO slow mode before any other MDIO access */
1520         if (hw->phy.type == e1000_phy_82577) {
1521                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1522                 if (ret_val)
1523                         return ret_val;
1524         }
1525
1526         if (((hw->phy.type == e1000_phy_82577) &&
1527              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1528             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1529                 /* Disable generation of early preamble */
1530                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1531                 if (ret_val)
1532                         return ret_val;
1533
1534                 /* Preamble tuning for SSC */
1535                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
1536                 if (ret_val)
1537                         return ret_val;
1538         }
1539
1540         if (hw->phy.type == e1000_phy_82578) {
1541                 /*
1542                  * Return registers to default by doing a soft reset then
1543                  * writing 0x3140 to the control register.
1544                  */
1545                 if (hw->phy.revision < 2) {
1546                         e1000e_phy_sw_reset(hw);
1547                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1548                 }
1549         }
1550
1551         /* Select page 0 */
1552         ret_val = hw->phy.ops.acquire(hw);
1553         if (ret_val)
1554                 return ret_val;
1555
1556         hw->phy.addr = 1;
1557         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1558         hw->phy.ops.release(hw);
1559         if (ret_val)
1560                 return ret_val;
1561
1562         /*
1563          * Configure the K1 Si workaround during phy reset assuming there is
1564          * link so that it disables K1 if link is in 1Gbps.
1565          */
1566         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1567         if (ret_val)
1568                 return ret_val;
1569
1570         /* Workaround for link disconnects on a busy hub in half duplex */
1571         ret_val = hw->phy.ops.acquire(hw);
1572         if (ret_val)
1573                 return ret_val;
1574         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1575         if (ret_val)
1576                 goto release;
1577         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
1578                                                phy_data & 0x00FF);
1579 release:
1580         hw->phy.ops.release(hw);
1581
1582         return ret_val;
1583 }
1584
1585 /**
1586  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1587  *  @hw:   pointer to the HW structure
1588  **/
1589 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1590 {
1591         u32 mac_reg;
1592         u16 i, phy_reg = 0;
1593         s32 ret_val;
1594
1595         ret_val = hw->phy.ops.acquire(hw);
1596         if (ret_val)
1597                 return;
1598         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1599         if (ret_val)
1600                 goto release;
1601
1602         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1603         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1604                 mac_reg = er32(RAL(i));
1605                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1606                                            (u16)(mac_reg & 0xFFFF));
1607                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1608                                            (u16)((mac_reg >> 16) & 0xFFFF));
1609
1610                 mac_reg = er32(RAH(i));
1611                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1612                                            (u16)(mac_reg & 0xFFFF));
1613                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1614                                            (u16)((mac_reg & E1000_RAH_AV)
1615                                                  >> 16));
1616         }
1617
1618         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1619
1620 release:
1621         hw->phy.ops.release(hw);
1622 }
1623
1624 /**
1625  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1626  *  with 82579 PHY
1627  *  @hw: pointer to the HW structure
1628  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1629  **/
1630 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1631 {
1632         s32 ret_val = 0;
1633         u16 phy_reg, data;
1634         u32 mac_reg;
1635         u16 i;
1636
1637         if (hw->mac.type != e1000_pch2lan)
1638                 return 0;
1639
1640         /* disable Rx path while enabling/disabling workaround */
1641         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1642         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1643         if (ret_val)
1644                 return ret_val;
1645
1646         if (enable) {
1647                 /*
1648                  * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1649                  * SHRAL/H) and initial CRC values to the MAC
1650                  */
1651                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1652                         u8 mac_addr[ETH_ALEN] = {0};
1653                         u32 addr_high, addr_low;
1654
1655                         addr_high = er32(RAH(i));
1656                         if (!(addr_high & E1000_RAH_AV))
1657                                 continue;
1658                         addr_low = er32(RAL(i));
1659                         mac_addr[0] = (addr_low & 0xFF);
1660                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1661                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1662                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1663                         mac_addr[4] = (addr_high & 0xFF);
1664                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1665
1666                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1667                 }
1668
1669                 /* Write Rx addresses to the PHY */
1670                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1671
1672                 /* Enable jumbo frame workaround in the MAC */
1673                 mac_reg = er32(FFLT_DBG);
1674                 mac_reg &= ~(1 << 14);
1675                 mac_reg |= (7 << 15);
1676                 ew32(FFLT_DBG, mac_reg);
1677
1678                 mac_reg = er32(RCTL);
1679                 mac_reg |= E1000_RCTL_SECRC;
1680                 ew32(RCTL, mac_reg);
1681
1682                 ret_val = e1000e_read_kmrn_reg(hw,
1683                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1684                                                 &data);
1685                 if (ret_val)
1686                         return ret_val;
1687                 ret_val = e1000e_write_kmrn_reg(hw,
1688                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1689                                                 data | (1 << 0));
1690                 if (ret_val)
1691                         return ret_val;
1692                 ret_val = e1000e_read_kmrn_reg(hw,
1693                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1694                                                 &data);
1695                 if (ret_val)
1696                         return ret_val;
1697                 data &= ~(0xF << 8);
1698                 data |= (0xB << 8);
1699                 ret_val = e1000e_write_kmrn_reg(hw,
1700                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1701                                                 data);
1702                 if (ret_val)
1703                         return ret_val;
1704
1705                 /* Enable jumbo frame workaround in the PHY */
1706                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1707                 data &= ~(0x7F << 5);
1708                 data |= (0x37 << 5);
1709                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1710                 if (ret_val)
1711                         return ret_val;
1712                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1713                 data &= ~(1 << 13);
1714                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1715                 if (ret_val)
1716                         return ret_val;
1717                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1718                 data &= ~(0x3FF << 2);
1719                 data |= (0x1A << 2);
1720                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1721                 if (ret_val)
1722                         return ret_val;
1723                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
1724                 if (ret_val)
1725                         return ret_val;
1726                 e1e_rphy(hw, HV_PM_CTRL, &data);
1727                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1728                 if (ret_val)
1729                         return ret_val;
1730         } else {
1731                 /* Write MAC register values back to h/w defaults */
1732                 mac_reg = er32(FFLT_DBG);
1733                 mac_reg &= ~(0xF << 14);
1734                 ew32(FFLT_DBG, mac_reg);
1735
1736                 mac_reg = er32(RCTL);
1737                 mac_reg &= ~E1000_RCTL_SECRC;
1738                 ew32(RCTL, mac_reg);
1739
1740                 ret_val = e1000e_read_kmrn_reg(hw,
1741                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1742                                                 &data);
1743                 if (ret_val)
1744                         return ret_val;
1745                 ret_val = e1000e_write_kmrn_reg(hw,
1746                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1747                                                 data & ~(1 << 0));
1748                 if (ret_val)
1749                         return ret_val;
1750                 ret_val = e1000e_read_kmrn_reg(hw,
1751                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1752                                                 &data);
1753                 if (ret_val)
1754                         return ret_val;
1755                 data &= ~(0xF << 8);
1756                 data |= (0xB << 8);
1757                 ret_val = e1000e_write_kmrn_reg(hw,
1758                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1759                                                 data);
1760                 if (ret_val)
1761                         return ret_val;
1762
1763                 /* Write PHY register values back to h/w defaults */
1764                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1765                 data &= ~(0x7F << 5);
1766                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1767                 if (ret_val)
1768                         return ret_val;
1769                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1770                 data |= (1 << 13);
1771                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1772                 if (ret_val)
1773                         return ret_val;
1774                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1775                 data &= ~(0x3FF << 2);
1776                 data |= (0x8 << 2);
1777                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1778                 if (ret_val)
1779                         return ret_val;
1780                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1781                 if (ret_val)
1782                         return ret_val;
1783                 e1e_rphy(hw, HV_PM_CTRL, &data);
1784                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1785                 if (ret_val)
1786                         return ret_val;
1787         }
1788
1789         /* re-enable Rx path after enabling/disabling workaround */
1790         return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1791 }
1792
1793 /**
1794  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1795  *  done after every PHY reset.
1796  **/
1797 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1798 {
1799         s32 ret_val = 0;
1800
1801         if (hw->mac.type != e1000_pch2lan)
1802                 return 0;
1803
1804         /* Set MDIO slow mode before any other MDIO access */
1805         ret_val = e1000_set_mdio_slow_mode_hv(hw);
1806
1807         ret_val = hw->phy.ops.acquire(hw);
1808         if (ret_val)
1809                 return ret_val;
1810         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1811                                                I82579_MSE_THRESHOLD);
1812         if (ret_val)
1813                 goto release;
1814         /* set MSE higher to enable link to stay up when noise is high */
1815         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 0x0034);
1816         if (ret_val)
1817                 goto release;
1818         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1819                                                I82579_MSE_LINK_DOWN);
1820         if (ret_val)
1821                 goto release;
1822         /* drop link after 5 times MSE threshold was reached */
1823         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 0x0005);
1824 release:
1825         hw->phy.ops.release(hw);
1826
1827         return ret_val;
1828 }
1829
1830 /**
1831  *  e1000_k1_gig_workaround_lv - K1 Si workaround
1832  *  @hw:   pointer to the HW structure
1833  *
1834  *  Workaround to set the K1 beacon duration for 82579 parts
1835  **/
1836 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1837 {
1838         s32 ret_val = 0;
1839         u16 status_reg = 0;
1840         u32 mac_reg;
1841         u16 phy_reg;
1842
1843         if (hw->mac.type != e1000_pch2lan)
1844                 return 0;
1845
1846         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1847         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1848         if (ret_val)
1849                 return ret_val;
1850
1851         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1852             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1853                 mac_reg = er32(FEXTNVM4);
1854                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1855
1856                 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
1857                 if (ret_val)
1858                         return ret_val;
1859
1860                 if (status_reg & HV_M_STATUS_SPEED_1000) {
1861                         u16 pm_phy_reg;
1862
1863                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1864                         phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1865                         /* LV 1G Packet drop issue wa  */
1866                         ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
1867                         if (ret_val)
1868                                 return ret_val;
1869                         pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
1870                         ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
1871                         if (ret_val)
1872                                 return ret_val;
1873                 } else {
1874                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1875                         phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1876                 }
1877                 ew32(FEXTNVM4, mac_reg);
1878                 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
1879         }
1880
1881         return ret_val;
1882 }
1883
1884 /**
1885  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1886  *  @hw:   pointer to the HW structure
1887  *  @gate: boolean set to true to gate, false to ungate
1888  *
1889  *  Gate/ungate the automatic PHY configuration via hardware; perform
1890  *  the configuration via software instead.
1891  **/
1892 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1893 {
1894         u32 extcnf_ctrl;
1895
1896         if (hw->mac.type != e1000_pch2lan)
1897                 return;
1898
1899         extcnf_ctrl = er32(EXTCNF_CTRL);
1900
1901         if (gate)
1902                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1903         else
1904                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1905
1906         ew32(EXTCNF_CTRL, extcnf_ctrl);
1907 }
1908
1909 /**
1910  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1911  *  @hw: pointer to the HW structure
1912  *
1913  *  Check the appropriate indication the MAC has finished configuring the
1914  *  PHY after a software reset.
1915  **/
1916 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1917 {
1918         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1919
1920         /* Wait for basic configuration completes before proceeding */
1921         do {
1922                 data = er32(STATUS);
1923                 data &= E1000_STATUS_LAN_INIT_DONE;
1924                 udelay(100);
1925         } while ((!data) && --loop);
1926
1927         /*
1928          * If basic configuration is incomplete before the above loop
1929          * count reaches 0, loading the configuration from NVM will
1930          * leave the PHY in a bad state possibly resulting in no link.
1931          */
1932         if (loop == 0)
1933                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1934
1935         /* Clear the Init Done bit for the next init event */
1936         data = er32(STATUS);
1937         data &= ~E1000_STATUS_LAN_INIT_DONE;
1938         ew32(STATUS, data);
1939 }
1940
1941 /**
1942  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1943  *  @hw: pointer to the HW structure
1944  **/
1945 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1946 {
1947         s32 ret_val = 0;
1948         u16 reg;
1949
1950         if (hw->phy.ops.check_reset_block(hw))
1951                 return 0;
1952
1953         /* Allow time for h/w to get to quiescent state after reset */
1954         usleep_range(10000, 20000);
1955
1956         /* Perform any necessary post-reset workarounds */
1957         switch (hw->mac.type) {
1958         case e1000_pchlan:
1959                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1960                 if (ret_val)
1961                         return ret_val;
1962                 break;
1963         case e1000_pch2lan:
1964                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1965                 if (ret_val)
1966                         return ret_val;
1967                 break;
1968         default:
1969                 break;
1970         }
1971
1972         /* Clear the host wakeup bit after lcd reset */
1973         if (hw->mac.type >= e1000_pchlan) {
1974                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
1975                 reg &= ~BM_WUC_HOST_WU_BIT;
1976                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
1977         }
1978
1979         /* Configure the LCD with the extended configuration region in NVM */
1980         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1981         if (ret_val)
1982                 return ret_val;
1983
1984         /* Configure the LCD with the OEM bits in NVM */
1985         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1986
1987         if (hw->mac.type == e1000_pch2lan) {
1988                 /* Ungate automatic PHY configuration on non-managed 82579 */
1989                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1990                         usleep_range(10000, 20000);
1991                         e1000_gate_hw_phy_config_ich8lan(hw, false);
1992                 }
1993
1994                 /* Set EEE LPI Update Timer to 200usec */
1995                 ret_val = hw->phy.ops.acquire(hw);
1996                 if (ret_val)
1997                         return ret_val;
1998                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1999                                                        I82579_LPI_UPDATE_TIMER);
2000                 if (!ret_val)
2001                         ret_val = hw->phy.ops.write_reg_locked(hw,
2002                                                                I82579_EMI_DATA,
2003                                                                0x1387);
2004                 hw->phy.ops.release(hw);
2005         }
2006
2007         return ret_val;
2008 }
2009
2010 /**
2011  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2012  *  @hw: pointer to the HW structure
2013  *
2014  *  Resets the PHY
2015  *  This is a function pointer entry point called by drivers
2016  *  or other shared routines.
2017  **/
2018 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2019 {
2020         s32 ret_val = 0;
2021
2022         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2023         if ((hw->mac.type == e1000_pch2lan) &&
2024             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2025                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2026
2027         ret_val = e1000e_phy_hw_reset_generic(hw);
2028         if (ret_val)
2029                 return ret_val;
2030
2031         return e1000_post_phy_reset_ich8lan(hw);
2032 }
2033
2034 /**
2035  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2036  *  @hw: pointer to the HW structure
2037  *  @active: true to enable LPLU, false to disable
2038  *
2039  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2040  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2041  *  the phy speed. This function will manually set the LPLU bit and restart
2042  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2043  *  since it configures the same bit.
2044  **/
2045 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2046 {
2047         s32 ret_val = 0;
2048         u16 oem_reg;
2049
2050         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2051         if (ret_val)
2052                 return ret_val;
2053
2054         if (active)
2055                 oem_reg |= HV_OEM_BITS_LPLU;
2056         else
2057                 oem_reg &= ~HV_OEM_BITS_LPLU;
2058
2059         if (!hw->phy.ops.check_reset_block(hw))
2060                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2061
2062         return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2063 }
2064
2065 /**
2066  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2067  *  @hw: pointer to the HW structure
2068  *  @active: true to enable LPLU, false to disable
2069  *
2070  *  Sets the LPLU D0 state according to the active flag.  When
2071  *  activating LPLU this function also disables smart speed
2072  *  and vice versa.  LPLU will not be activated unless the
2073  *  device autonegotiation advertisement meets standards of
2074  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2075  *  This is a function pointer entry point only called by
2076  *  PHY setup routines.
2077  **/
2078 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2079 {
2080         struct e1000_phy_info *phy = &hw->phy;
2081         u32 phy_ctrl;
2082         s32 ret_val = 0;
2083         u16 data;
2084
2085         if (phy->type == e1000_phy_ife)
2086                 return 0;
2087
2088         phy_ctrl = er32(PHY_CTRL);
2089
2090         if (active) {
2091                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2092                 ew32(PHY_CTRL, phy_ctrl);
2093
2094                 if (phy->type != e1000_phy_igp_3)
2095                         return 0;
2096
2097                 /*
2098                  * Call gig speed drop workaround on LPLU before accessing
2099                  * any PHY registers
2100                  */
2101                 if (hw->mac.type == e1000_ich8lan)
2102                         e1000e_gig_downshift_workaround_ich8lan(hw);
2103
2104                 /* When LPLU is enabled, we should disable SmartSpeed */
2105                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2106                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2107                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2108                 if (ret_val)
2109                         return ret_val;
2110         } else {
2111                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2112                 ew32(PHY_CTRL, phy_ctrl);
2113
2114                 if (phy->type != e1000_phy_igp_3)
2115                         return 0;
2116
2117                 /*
2118                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2119                  * during Dx states where the power conservation is most
2120                  * important.  During driver activity we should enable
2121                  * SmartSpeed, so performance is maintained.
2122                  */
2123                 if (phy->smart_speed == e1000_smart_speed_on) {
2124                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2125                                            &data);
2126                         if (ret_val)
2127                                 return ret_val;
2128
2129                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2130                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2131                                            data);
2132                         if (ret_val)
2133                                 return ret_val;
2134                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2135                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2136                                            &data);
2137                         if (ret_val)
2138                                 return ret_val;
2139
2140                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2141                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2142                                            data);
2143                         if (ret_val)
2144                                 return ret_val;
2145                 }
2146         }
2147
2148         return 0;
2149 }
2150
2151 /**
2152  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2153  *  @hw: pointer to the HW structure
2154  *  @active: true to enable LPLU, false to disable
2155  *
2156  *  Sets the LPLU D3 state according to the active flag.  When
2157  *  activating LPLU this function also disables smart speed
2158  *  and vice versa.  LPLU will not be activated unless the
2159  *  device autonegotiation advertisement meets standards of
2160  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2161  *  This is a function pointer entry point only called by
2162  *  PHY setup routines.
2163  **/
2164 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2165 {
2166         struct e1000_phy_info *phy = &hw->phy;
2167         u32 phy_ctrl;
2168         s32 ret_val = 0;
2169         u16 data;
2170
2171         phy_ctrl = er32(PHY_CTRL);
2172
2173         if (!active) {
2174                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2175                 ew32(PHY_CTRL, phy_ctrl);
2176
2177                 if (phy->type != e1000_phy_igp_3)
2178                         return 0;
2179
2180                 /*
2181                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2182                  * during Dx states where the power conservation is most
2183                  * important.  During driver activity we should enable
2184                  * SmartSpeed, so performance is maintained.
2185                  */
2186                 if (phy->smart_speed == e1000_smart_speed_on) {
2187                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2188                                            &data);
2189                         if (ret_val)
2190                                 return ret_val;
2191
2192                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2193                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2194                                            data);
2195                         if (ret_val)
2196                                 return ret_val;
2197                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2198                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2199                                            &data);
2200                         if (ret_val)
2201                                 return ret_val;
2202
2203                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2204                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2205                                            data);
2206                         if (ret_val)
2207                                 return ret_val;
2208                 }
2209         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2210                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2211                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2212                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2213                 ew32(PHY_CTRL, phy_ctrl);
2214
2215                 if (phy->type != e1000_phy_igp_3)
2216                         return 0;
2217
2218                 /*
2219                  * Call gig speed drop workaround on LPLU before accessing
2220                  * any PHY registers
2221                  */
2222                 if (hw->mac.type == e1000_ich8lan)
2223                         e1000e_gig_downshift_workaround_ich8lan(hw);
2224
2225                 /* When LPLU is enabled, we should disable SmartSpeed */
2226                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2227                 if (ret_val)
2228                         return ret_val;
2229
2230                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2231                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2232         }
2233
2234         return ret_val;
2235 }
2236
2237 /**
2238  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2239  *  @hw: pointer to the HW structure
2240  *  @bank:  pointer to the variable that returns the active bank
2241  *
2242  *  Reads signature byte from the NVM using the flash access registers.
2243  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2244  **/
2245 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2246 {
2247         u32 eecd;
2248         struct e1000_nvm_info *nvm = &hw->nvm;
2249         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2250         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2251         u8 sig_byte = 0;
2252         s32 ret_val;
2253
2254         switch (hw->mac.type) {
2255         case e1000_ich8lan:
2256         case e1000_ich9lan:
2257                 eecd = er32(EECD);
2258                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2259                     E1000_EECD_SEC1VAL_VALID_MASK) {
2260                         if (eecd & E1000_EECD_SEC1VAL)
2261                                 *bank = 1;
2262                         else
2263                                 *bank = 0;
2264
2265                         return 0;
2266                 }
2267                 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2268                 /* fall-thru */
2269         default:
2270                 /* set bank to 0 in case flash read fails */
2271                 *bank = 0;
2272
2273                 /* Check bank 0 */
2274                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2275                                                         &sig_byte);
2276                 if (ret_val)
2277                         return ret_val;
2278                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2279                     E1000_ICH_NVM_SIG_VALUE) {
2280                         *bank = 0;
2281                         return 0;
2282                 }
2283
2284                 /* Check bank 1 */
2285                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2286                                                         bank1_offset,
2287                                                         &sig_byte);
2288                 if (ret_val)
2289                         return ret_val;
2290                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2291                     E1000_ICH_NVM_SIG_VALUE) {
2292                         *bank = 1;
2293                         return 0;
2294                 }
2295
2296                 e_dbg("ERROR: No valid NVM bank present\n");
2297                 return -E1000_ERR_NVM;
2298         }
2299 }
2300
2301 /**
2302  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2303  *  @hw: pointer to the HW structure
2304  *  @offset: The offset (in bytes) of the word(s) to read.
2305  *  @words: Size of data to read in words
2306  *  @data: Pointer to the word(s) to read at offset.
2307  *
2308  *  Reads a word(s) from the NVM using the flash access registers.
2309  **/
2310 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2311                                   u16 *data)
2312 {
2313         struct e1000_nvm_info *nvm = &hw->nvm;
2314         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2315         u32 act_offset;
2316         s32 ret_val = 0;
2317         u32 bank = 0;
2318         u16 i, word;
2319
2320         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2321             (words == 0)) {
2322                 e_dbg("nvm parameter(s) out of bounds\n");
2323                 ret_val = -E1000_ERR_NVM;
2324                 goto out;
2325         }
2326
2327         nvm->ops.acquire(hw);
2328
2329         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2330         if (ret_val) {
2331                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2332                 bank = 0;
2333         }
2334
2335         act_offset = (bank) ? nvm->flash_bank_size : 0;
2336         act_offset += offset;
2337
2338         ret_val = 0;
2339         for (i = 0; i < words; i++) {
2340                 if (dev_spec->shadow_ram[offset+i].modified) {
2341                         data[i] = dev_spec->shadow_ram[offset+i].value;
2342                 } else {
2343                         ret_val = e1000_read_flash_word_ich8lan(hw,
2344                                                                 act_offset + i,
2345                                                                 &word);
2346                         if (ret_val)
2347                                 break;
2348                         data[i] = word;
2349                 }
2350         }
2351
2352         nvm->ops.release(hw);
2353
2354 out:
2355         if (ret_val)
2356                 e_dbg("NVM read error: %d\n", ret_val);
2357
2358         return ret_val;
2359 }
2360
2361 /**
2362  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2363  *  @hw: pointer to the HW structure
2364  *
2365  *  This function does initial flash setup so that a new read/write/erase cycle
2366  *  can be started.
2367  **/
2368 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2369 {
2370         union ich8_hws_flash_status hsfsts;
2371         s32 ret_val = -E1000_ERR_NVM;
2372
2373         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2374
2375         /* Check if the flash descriptor is valid */
2376         if (!hsfsts.hsf_status.fldesvalid) {
2377                 e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
2378                 return -E1000_ERR_NVM;
2379         }
2380
2381         /* Clear FCERR and DAEL in hw status by writing 1 */
2382         hsfsts.hsf_status.flcerr = 1;
2383         hsfsts.hsf_status.dael = 1;
2384
2385         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2386
2387         /*
2388          * Either we should have a hardware SPI cycle in progress
2389          * bit to check against, in order to start a new cycle or
2390          * FDONE bit should be changed in the hardware so that it
2391          * is 1 after hardware reset, which can then be used as an
2392          * indication whether a cycle is in progress or has been
2393          * completed.
2394          */
2395
2396         if (!hsfsts.hsf_status.flcinprog) {
2397                 /*
2398                  * There is no cycle running at present,
2399                  * so we can start a cycle.
2400                  * Begin by setting Flash Cycle Done.
2401                  */
2402                 hsfsts.hsf_status.flcdone = 1;
2403                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2404                 ret_val = 0;
2405         } else {
2406                 s32 i;
2407
2408                 /*
2409                  * Otherwise poll for sometime so the current
2410                  * cycle has a chance to end before giving up.
2411                  */
2412                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2413                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2414                         if (!hsfsts.hsf_status.flcinprog) {
2415                                 ret_val = 0;
2416                                 break;
2417                         }
2418                         udelay(1);
2419                 }
2420                 if (!ret_val) {
2421                         /*
2422                          * Successful in waiting for previous cycle to timeout,
2423                          * now set the Flash Cycle Done.
2424                          */
2425                         hsfsts.hsf_status.flcdone = 1;
2426                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2427                 } else {
2428                         e_dbg("Flash controller busy, cannot get access\n");
2429                 }
2430         }
2431
2432         return ret_val;
2433 }
2434
2435 /**
2436  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2437  *  @hw: pointer to the HW structure
2438  *  @timeout: maximum time to wait for completion
2439  *
2440  *  This function starts a flash cycle and waits for its completion.
2441  **/
2442 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2443 {
2444         union ich8_hws_flash_ctrl hsflctl;
2445         union ich8_hws_flash_status hsfsts;
2446         u32 i = 0;
2447
2448         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2449         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2450         hsflctl.hsf_ctrl.flcgo = 1;
2451         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2452
2453         /* wait till FDONE bit is set to 1 */
2454         do {
2455                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2456                 if (hsfsts.hsf_status.flcdone)
2457                         break;
2458                 udelay(1);
2459         } while (i++ < timeout);
2460
2461         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
2462                 return 0;
2463
2464         return -E1000_ERR_NVM;
2465 }
2466
2467 /**
2468  *  e1000_read_flash_word_ich8lan - Read word from flash
2469  *  @hw: pointer to the HW structure
2470  *  @offset: offset to data location
2471  *  @data: pointer to the location for storing the data
2472  *
2473  *  Reads the flash word at offset into data.  Offset is converted
2474  *  to bytes before read.
2475  **/
2476 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2477                                          u16 *data)
2478 {
2479         /* Must convert offset into bytes. */
2480         offset <<= 1;
2481
2482         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2483 }
2484
2485 /**
2486  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2487  *  @hw: pointer to the HW structure
2488  *  @offset: The offset of the byte to read.
2489  *  @data: Pointer to a byte to store the value read.
2490  *
2491  *  Reads a single byte from the NVM using the flash access registers.
2492  **/
2493 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2494                                          u8 *data)
2495 {
2496         s32 ret_val;
2497         u16 word = 0;
2498
2499         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2500         if (ret_val)
2501                 return ret_val;
2502
2503         *data = (u8)word;
2504
2505         return 0;
2506 }
2507
2508 /**
2509  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2510  *  @hw: pointer to the HW structure
2511  *  @offset: The offset (in bytes) of the byte or word to read.
2512  *  @size: Size of data to read, 1=byte 2=word
2513  *  @data: Pointer to the word to store the value read.
2514  *
2515  *  Reads a byte or word from the NVM using the flash access registers.
2516  **/
2517 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2518                                          u8 size, u16 *data)
2519 {
2520         union ich8_hws_flash_status hsfsts;
2521         union ich8_hws_flash_ctrl hsflctl;
2522         u32 flash_linear_addr;
2523         u32 flash_data = 0;
2524         s32 ret_val = -E1000_ERR_NVM;
2525         u8 count = 0;
2526
2527         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2528                 return -E1000_ERR_NVM;
2529
2530         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2531                             hw->nvm.flash_base_addr;
2532
2533         do {
2534                 udelay(1);
2535                 /* Steps */
2536                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2537                 if (ret_val)
2538                         break;
2539
2540                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2541                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2542                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2543                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2544                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2545
2546                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2547
2548                 ret_val = e1000_flash_cycle_ich8lan(hw,
2549                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
2550
2551                 /*
2552                  * Check if FCERR is set to 1, if set to 1, clear it
2553                  * and try the whole sequence a few more times, else
2554                  * read in (shift in) the Flash Data0, the order is
2555                  * least significant byte first msb to lsb
2556                  */
2557                 if (!ret_val) {
2558                         flash_data = er32flash(ICH_FLASH_FDATA0);
2559                         if (size == 1)
2560                                 *data = (u8)(flash_data & 0x000000FF);
2561                         else if (size == 2)
2562                                 *data = (u16)(flash_data & 0x0000FFFF);
2563                         break;
2564                 } else {
2565                         /*
2566                          * If we've gotten here, then things are probably
2567                          * completely hosed, but if the error condition is
2568                          * detected, it won't hurt to give it another try...
2569                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2570                          */
2571                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2572                         if (hsfsts.hsf_status.flcerr) {
2573                                 /* Repeat for some time before giving up. */
2574                                 continue;
2575                         } else if (!hsfsts.hsf_status.flcdone) {
2576                                 e_dbg("Timeout error - flash cycle did not complete.\n");
2577                                 break;
2578                         }
2579                 }
2580         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2581
2582         return ret_val;
2583 }
2584
2585 /**
2586  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2587  *  @hw: pointer to the HW structure
2588  *  @offset: The offset (in bytes) of the word(s) to write.
2589  *  @words: Size of data to write in words
2590  *  @data: Pointer to the word(s) to write at offset.
2591  *
2592  *  Writes a byte or word to the NVM using the flash access registers.
2593  **/
2594 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2595                                    u16 *data)
2596 {
2597         struct e1000_nvm_info *nvm = &hw->nvm;
2598         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2599         u16 i;
2600
2601         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2602             (words == 0)) {
2603                 e_dbg("nvm parameter(s) out of bounds\n");
2604                 return -E1000_ERR_NVM;
2605         }
2606
2607         nvm->ops.acquire(hw);
2608
2609         for (i = 0; i < words; i++) {
2610                 dev_spec->shadow_ram[offset+i].modified = true;
2611                 dev_spec->shadow_ram[offset+i].value = data[i];
2612         }
2613
2614         nvm->ops.release(hw);
2615
2616         return 0;
2617 }
2618
2619 /**
2620  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2621  *  @hw: pointer to the HW structure
2622  *
2623  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2624  *  which writes the checksum to the shadow ram.  The changes in the shadow
2625  *  ram are then committed to the EEPROM by processing each bank at a time
2626  *  checking for the modified bit and writing only the pending changes.
2627  *  After a successful commit, the shadow ram is cleared and is ready for
2628  *  future writes.
2629  **/
2630 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2631 {
2632         struct e1000_nvm_info *nvm = &hw->nvm;
2633         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2634         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2635         s32 ret_val;
2636         u16 data;
2637
2638         ret_val = e1000e_update_nvm_checksum_generic(hw);
2639         if (ret_val)
2640                 goto out;
2641
2642         if (nvm->type != e1000_nvm_flash_sw)
2643                 goto out;
2644
2645         nvm->ops.acquire(hw);
2646
2647         /*
2648          * We're writing to the opposite bank so if we're on bank 1,
2649          * write to bank 0 etc.  We also need to erase the segment that
2650          * is going to be written
2651          */
2652         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2653         if (ret_val) {
2654                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2655                 bank = 0;
2656         }
2657
2658         if (bank == 0) {
2659                 new_bank_offset = nvm->flash_bank_size;
2660                 old_bank_offset = 0;
2661                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2662                 if (ret_val)
2663                         goto release;
2664         } else {
2665                 old_bank_offset = nvm->flash_bank_size;
2666                 new_bank_offset = 0;
2667                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2668                 if (ret_val)
2669                         goto release;
2670         }
2671
2672         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2673                 /*
2674                  * Determine whether to write the value stored
2675                  * in the other NVM bank or a modified value stored
2676                  * in the shadow RAM
2677                  */
2678                 if (dev_spec->shadow_ram[i].modified) {
2679                         data = dev_spec->shadow_ram[i].value;
2680                 } else {
2681                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2682                                                                 old_bank_offset,
2683                                                                 &data);
2684                         if (ret_val)
2685                                 break;
2686                 }
2687
2688                 /*
2689                  * If the word is 0x13, then make sure the signature bits
2690                  * (15:14) are 11b until the commit has completed.
2691                  * This will allow us to write 10b which indicates the
2692                  * signature is valid.  We want to do this after the write
2693                  * has completed so that we don't mark the segment valid
2694                  * while the write is still in progress
2695                  */
2696                 if (i == E1000_ICH_NVM_SIG_WORD)
2697                         data |= E1000_ICH_NVM_SIG_MASK;
2698
2699                 /* Convert offset to bytes. */
2700                 act_offset = (i + new_bank_offset) << 1;
2701
2702                 udelay(100);
2703                 /* Write the bytes to the new bank. */
2704                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2705                                                                act_offset,
2706                                                                (u8)data);
2707                 if (ret_val)
2708                         break;
2709
2710                 udelay(100);
2711                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2712                                                           act_offset + 1,
2713                                                           (u8)(data >> 8));
2714                 if (ret_val)
2715                         break;
2716         }
2717
2718         /*
2719          * Don't bother writing the segment valid bits if sector
2720          * programming failed.
2721          */
2722         if (ret_val) {
2723                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2724                 e_dbg("Flash commit failed.\n");
2725                 goto release;
2726         }
2727
2728         /*
2729          * Finally validate the new segment by setting bit 15:14
2730          * to 10b in word 0x13 , this can be done without an
2731          * erase as well since these bits are 11 to start with
2732          * and we need to change bit 14 to 0b
2733          */
2734         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2735         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2736         if (ret_val)
2737                 goto release;
2738
2739         data &= 0xBFFF;
2740         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2741                                                        act_offset * 2 + 1,
2742                                                        (u8)(data >> 8));
2743         if (ret_val)
2744                 goto release;
2745
2746         /*
2747          * And invalidate the previously valid segment by setting
2748          * its signature word (0x13) high_byte to 0b. This can be
2749          * done without an erase because flash erase sets all bits
2750          * to 1's. We can write 1's to 0's without an erase
2751          */
2752         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2753         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2754         if (ret_val)
2755                 goto release;
2756
2757         /* Great!  Everything worked, we can now clear the cached entries. */
2758         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2759                 dev_spec->shadow_ram[i].modified = false;
2760                 dev_spec->shadow_ram[i].value = 0xFFFF;
2761         }
2762
2763 release:
2764         nvm->ops.release(hw);
2765
2766         /*
2767          * Reload the EEPROM, or else modifications will not appear
2768          * until after the next adapter reset.
2769          */
2770         if (!ret_val) {
2771                 nvm->ops.reload(hw);
2772                 usleep_range(10000, 20000);
2773         }
2774
2775 out:
2776         if (ret_val)
2777                 e_dbg("NVM update error: %d\n", ret_val);
2778
2779         return ret_val;
2780 }
2781
2782 /**
2783  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2784  *  @hw: pointer to the HW structure
2785  *
2786  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2787  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2788  *  calculated, in which case we need to calculate the checksum and set bit 6.
2789  **/
2790 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2791 {
2792         s32 ret_val;
2793         u16 data;
2794
2795         /*
2796          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2797          * needs to be fixed.  This bit is an indication that the NVM
2798          * was prepared by OEM software and did not calculate the
2799          * checksum...a likely scenario.
2800          */
2801         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2802         if (ret_val)
2803                 return ret_val;
2804
2805         if (!(data & 0x40)) {
2806                 data |= 0x40;
2807                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2808                 if (ret_val)
2809                         return ret_val;
2810                 ret_val = e1000e_update_nvm_checksum(hw);
2811                 if (ret_val)
2812                         return ret_val;
2813         }
2814
2815         return e1000e_validate_nvm_checksum_generic(hw);
2816 }
2817
2818 /**
2819  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2820  *  @hw: pointer to the HW structure
2821  *
2822  *  To prevent malicious write/erase of the NVM, set it to be read-only
2823  *  so that the hardware ignores all write/erase cycles of the NVM via
2824  *  the flash control registers.  The shadow-ram copy of the NVM will
2825  *  still be updated, however any updates to this copy will not stick
2826  *  across driver reloads.
2827  **/
2828 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2829 {
2830         struct e1000_nvm_info *nvm = &hw->nvm;
2831         union ich8_flash_protected_range pr0;
2832         union ich8_hws_flash_status hsfsts;
2833         u32 gfpreg;
2834
2835         nvm->ops.acquire(hw);
2836
2837         gfpreg = er32flash(ICH_FLASH_GFPREG);
2838
2839         /* Write-protect GbE Sector of NVM */
2840         pr0.regval = er32flash(ICH_FLASH_PR0);
2841         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2842         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2843         pr0.range.wpe = true;
2844         ew32flash(ICH_FLASH_PR0, pr0.regval);
2845
2846         /*
2847          * Lock down a subset of GbE Flash Control Registers, e.g.
2848          * PR0 to prevent the write-protection from being lifted.
2849          * Once FLOCKDN is set, the registers protected by it cannot
2850          * be written until FLOCKDN is cleared by a hardware reset.
2851          */
2852         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2853         hsfsts.hsf_status.flockdn = true;
2854         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2855
2856         nvm->ops.release(hw);
2857 }
2858
2859 /**
2860  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2861  *  @hw: pointer to the HW structure
2862  *  @offset: The offset (in bytes) of the byte/word to read.
2863  *  @size: Size of data to read, 1=byte 2=word
2864  *  @data: The byte(s) to write to the NVM.
2865  *
2866  *  Writes one/two bytes to the NVM using the flash access registers.
2867  **/
2868 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2869                                           u8 size, u16 data)
2870 {
2871         union ich8_hws_flash_status hsfsts;
2872         union ich8_hws_flash_ctrl hsflctl;
2873         u32 flash_linear_addr;
2874         u32 flash_data = 0;
2875         s32 ret_val;
2876         u8 count = 0;
2877
2878         if (size < 1 || size > 2 || data > size * 0xff ||
2879             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2880                 return -E1000_ERR_NVM;
2881
2882         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2883                             hw->nvm.flash_base_addr;
2884
2885         do {
2886                 udelay(1);
2887                 /* Steps */
2888                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2889                 if (ret_val)
2890                         break;
2891
2892                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2893                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2894                 hsflctl.hsf_ctrl.fldbcount = size -1;
2895                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2896                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2897
2898                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2899
2900                 if (size == 1)
2901                         flash_data = (u32)data & 0x00FF;
2902                 else
2903                         flash_data = (u32)data;
2904
2905                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2906
2907                 /*
2908                  * check if FCERR is set to 1 , if set to 1, clear it
2909                  * and try the whole sequence a few more times else done
2910                  */
2911                 ret_val = e1000_flash_cycle_ich8lan(hw,
2912                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2913                 if (!ret_val)
2914                         break;
2915
2916                 /*
2917                  * If we're here, then things are most likely
2918                  * completely hosed, but if the error condition
2919                  * is detected, it won't hurt to give it another
2920                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2921                  */
2922                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2923                 if (hsfsts.hsf_status.flcerr)
2924                         /* Repeat for some time before giving up. */
2925                         continue;
2926                 if (!hsfsts.hsf_status.flcdone) {
2927                         e_dbg("Timeout error - flash cycle did not complete.\n");
2928                         break;
2929                 }
2930         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2931
2932         return ret_val;
2933 }
2934
2935 /**
2936  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2937  *  @hw: pointer to the HW structure
2938  *  @offset: The index of the byte to read.
2939  *  @data: The byte to write to the NVM.
2940  *
2941  *  Writes a single byte to the NVM using the flash access registers.
2942  **/
2943 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2944                                           u8 data)
2945 {
2946         u16 word = (u16)data;
2947
2948         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2949 }
2950
2951 /**
2952  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2953  *  @hw: pointer to the HW structure
2954  *  @offset: The offset of the byte to write.
2955  *  @byte: The byte to write to the NVM.
2956  *
2957  *  Writes a single byte to the NVM using the flash access registers.
2958  *  Goes through a retry algorithm before giving up.
2959  **/
2960 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2961                                                 u32 offset, u8 byte)
2962 {
2963         s32 ret_val;
2964         u16 program_retries;
2965
2966         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2967         if (!ret_val)
2968                 return ret_val;
2969
2970         for (program_retries = 0; program_retries < 100; program_retries++) {
2971                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2972                 udelay(100);
2973                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2974                 if (!ret_val)
2975                         break;
2976         }
2977         if (program_retries == 100)
2978                 return -E1000_ERR_NVM;
2979
2980         return 0;
2981 }
2982
2983 /**
2984  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2985  *  @hw: pointer to the HW structure
2986  *  @bank: 0 for first bank, 1 for second bank, etc.
2987  *
2988  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2989  *  bank N is 4096 * N + flash_reg_addr.
2990  **/
2991 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2992 {
2993         struct e1000_nvm_info *nvm = &hw->nvm;
2994         union ich8_hws_flash_status hsfsts;
2995         union ich8_hws_flash_ctrl hsflctl;
2996         u32 flash_linear_addr;
2997         /* bank size is in 16bit words - adjust to bytes */
2998         u32 flash_bank_size = nvm->flash_bank_size * 2;
2999         s32 ret_val;
3000         s32 count = 0;
3001         s32 j, iteration, sector_size;
3002
3003         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3004
3005         /*
3006          * Determine HW Sector size: Read BERASE bits of hw flash status
3007          * register
3008          * 00: The Hw sector is 256 bytes, hence we need to erase 16
3009          *     consecutive sectors.  The start index for the nth Hw sector
3010          *     can be calculated as = bank * 4096 + n * 256
3011          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3012          *     The start index for the nth Hw sector can be calculated
3013          *     as = bank * 4096
3014          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3015          *     (ich9 only, otherwise error condition)
3016          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3017          */
3018         switch (hsfsts.hsf_status.berasesz) {
3019         case 0:
3020                 /* Hw sector size 256 */
3021                 sector_size = ICH_FLASH_SEG_SIZE_256;
3022                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3023                 break;
3024         case 1:
3025                 sector_size = ICH_FLASH_SEG_SIZE_4K;
3026                 iteration = 1;
3027                 break;
3028         case 2:
3029                 sector_size = ICH_FLASH_SEG_SIZE_8K;
3030                 iteration = 1;
3031                 break;
3032         case 3:
3033                 sector_size = ICH_FLASH_SEG_SIZE_64K;
3034                 iteration = 1;
3035                 break;
3036         default:
3037                 return -E1000_ERR_NVM;
3038         }
3039
3040         /* Start with the base address, then add the sector offset. */
3041         flash_linear_addr = hw->nvm.flash_base_addr;
3042         flash_linear_addr += (bank) ? flash_bank_size : 0;
3043
3044         for (j = 0; j < iteration ; j++) {
3045                 do {
3046                         /* Steps */
3047                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
3048                         if (ret_val)
3049                                 return ret_val;
3050
3051                         /*
3052                          * Write a value 11 (block Erase) in Flash
3053                          * Cycle field in hw flash control
3054                          */
3055                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3056                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3057                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3058
3059                         /*
3060                          * Write the last 24 bits of an index within the
3061                          * block into Flash Linear address field in Flash
3062                          * Address.
3063                          */
3064                         flash_linear_addr += (j * sector_size);
3065                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3066
3067                         ret_val = e1000_flash_cycle_ich8lan(hw,
3068                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
3069                         if (!ret_val)
3070                                 break;
3071
3072                         /*
3073                          * Check if FCERR is set to 1.  If 1,
3074                          * clear it and try the whole sequence
3075                          * a few more times else Done
3076                          */
3077                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3078                         if (hsfsts.hsf_status.flcerr)
3079                                 /* repeat for some time before giving up */
3080                                 continue;
3081                         else if (!hsfsts.hsf_status.flcdone)
3082                                 return ret_val;
3083                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3084         }
3085
3086         return 0;
3087 }
3088
3089 /**
3090  *  e1000_valid_led_default_ich8lan - Set the default LED settings
3091  *  @hw: pointer to the HW structure
3092  *  @data: Pointer to the LED settings
3093  *
3094  *  Reads the LED default settings from the NVM to data.  If the NVM LED
3095  *  settings is all 0's or F's, set the LED default to a valid LED default
3096  *  setting.
3097  **/
3098 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3099 {
3100         s32 ret_val;
3101
3102         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
3103         if (ret_val) {
3104                 e_dbg("NVM Read Error\n");
3105                 return ret_val;
3106         }
3107
3108         if (*data == ID_LED_RESERVED_0000 ||
3109             *data == ID_LED_RESERVED_FFFF)
3110                 *data = ID_LED_DEFAULT_ICH8LAN;
3111
3112         return 0;
3113 }
3114
3115 /**
3116  *  e1000_id_led_init_pchlan - store LED configurations
3117  *  @hw: pointer to the HW structure
3118  *
3119  *  PCH does not control LEDs via the LEDCTL register, rather it uses
3120  *  the PHY LED configuration register.
3121  *
3122  *  PCH also does not have an "always on" or "always off" mode which
3123  *  complicates the ID feature.  Instead of using the "on" mode to indicate
3124  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
3125  *  use "link_up" mode.  The LEDs will still ID on request if there is no
3126  *  link based on logic in e1000_led_[on|off]_pchlan().
3127  **/
3128 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3129 {
3130         struct e1000_mac_info *mac = &hw->mac;
3131         s32 ret_val;
3132         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3133         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3134         u16 data, i, temp, shift;
3135
3136         /* Get default ID LED modes */
3137         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3138         if (ret_val)
3139                 return ret_val;
3140
3141         mac->ledctl_default = er32(LEDCTL);
3142         mac->ledctl_mode1 = mac->ledctl_default;
3143         mac->ledctl_mode2 = mac->ledctl_default;
3144
3145         for (i = 0; i < 4; i++) {
3146                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3147                 shift = (i * 5);
3148                 switch (temp) {
3149                 case ID_LED_ON1_DEF2:
3150                 case ID_LED_ON1_ON2:
3151                 case ID_LED_ON1_OFF2:
3152                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3153                         mac->ledctl_mode1 |= (ledctl_on << shift);
3154                         break;
3155                 case ID_LED_OFF1_DEF2:
3156                 case ID_LED_OFF1_ON2:
3157                 case ID_LED_OFF1_OFF2:
3158                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3159                         mac->ledctl_mode1 |= (ledctl_off << shift);
3160                         break;
3161                 default:
3162                         /* Do nothing */
3163                         break;
3164                 }
3165                 switch (temp) {
3166                 case ID_LED_DEF1_ON2:
3167                 case ID_LED_ON1_ON2:
3168                 case ID_LED_OFF1_ON2:
3169                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3170                         mac->ledctl_mode2 |= (ledctl_on << shift);
3171                         break;
3172                 case ID_LED_DEF1_OFF2:
3173                 case ID_LED_ON1_OFF2:
3174                 case ID_LED_OFF1_OFF2:
3175                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3176                         mac->ledctl_mode2 |= (ledctl_off << shift);
3177                         break;
3178                 default:
3179                         /* Do nothing */
3180                         break;
3181                 }
3182         }
3183
3184         return 0;
3185 }
3186
3187 /**
3188  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3189  *  @hw: pointer to the HW structure
3190  *
3191  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3192  *  register, so the the bus width is hard coded.
3193  **/
3194 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3195 {
3196         struct e1000_bus_info *bus = &hw->bus;
3197         s32 ret_val;
3198
3199         ret_val = e1000e_get_bus_info_pcie(hw);
3200
3201         /*
3202          * ICH devices are "PCI Express"-ish.  They have
3203          * a configuration space, but do not contain
3204          * PCI Express Capability registers, so bus width
3205          * must be hardcoded.
3206          */
3207         if (bus->width == e1000_bus_width_unknown)
3208                 bus->width = e1000_bus_width_pcie_x1;
3209
3210         return ret_val;
3211 }
3212
3213 /**
3214  *  e1000_reset_hw_ich8lan - Reset the hardware
3215  *  @hw: pointer to the HW structure
3216  *
3217  *  Does a full reset of the hardware which includes a reset of the PHY and
3218  *  MAC.
3219  **/
3220 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3221 {
3222         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3223         u16 kum_cfg;
3224         u32 ctrl, reg;
3225         s32 ret_val;
3226
3227         /*
3228          * Prevent the PCI-E bus from sticking if there is no TLP connection
3229          * on the last TLP read/write transaction when MAC is reset.
3230          */
3231         ret_val = e1000e_disable_pcie_master(hw);
3232         if (ret_val)
3233                 e_dbg("PCI-E Master disable polling has failed.\n");
3234
3235         e_dbg("Masking off all interrupts\n");
3236         ew32(IMC, 0xffffffff);
3237
3238         /*
3239          * Disable the Transmit and Receive units.  Then delay to allow
3240          * any pending transactions to complete before we hit the MAC
3241          * with the global reset.
3242          */
3243         ew32(RCTL, 0);
3244         ew32(TCTL, E1000_TCTL_PSP);
3245         e1e_flush();
3246
3247         usleep_range(10000, 20000);
3248
3249         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3250         if (hw->mac.type == e1000_ich8lan) {
3251                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3252                 ew32(PBA, E1000_PBA_8K);
3253                 /* Set Packet Buffer Size to 16k. */
3254                 ew32(PBS, E1000_PBS_16K);
3255         }
3256
3257         if (hw->mac.type == e1000_pchlan) {
3258                 /* Save the NVM K1 bit setting */
3259                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
3260                 if (ret_val)
3261                         return ret_val;
3262
3263                 if (kum_cfg & E1000_NVM_K1_ENABLE)
3264                         dev_spec->nvm_k1_enabled = true;
3265                 else
3266                         dev_spec->nvm_k1_enabled = false;
3267         }
3268
3269         ctrl = er32(CTRL);
3270
3271         if (!hw->phy.ops.check_reset_block(hw)) {
3272                 /*
3273                  * Full-chip reset requires MAC and PHY reset at the same
3274                  * time to make sure the interface between MAC and the
3275                  * external PHY is reset.
3276                  */
3277                 ctrl |= E1000_CTRL_PHY_RST;
3278
3279                 /*
3280                  * Gate automatic PHY configuration by hardware on
3281                  * non-managed 82579
3282                  */
3283                 if ((hw->mac.type == e1000_pch2lan) &&
3284                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3285                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3286         }
3287         ret_val = e1000_acquire_swflag_ich8lan(hw);
3288         e_dbg("Issuing a global reset to ich8lan\n");
3289         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3290         /* cannot issue a flush here because it hangs the hardware */
3291         msleep(20);
3292
3293         /* Set Phy Config Counter to 50msec */
3294         if (hw->mac.type == e1000_pch2lan) {
3295                 reg = er32(FEXTNVM3);
3296                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
3297                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
3298                 ew32(FEXTNVM3, reg);
3299         }
3300
3301         if (!ret_val)
3302                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
3303
3304         if (ctrl & E1000_CTRL_PHY_RST) {
3305                 ret_val = hw->phy.ops.get_cfg_done(hw);
3306                 if (ret_val)
3307                         return ret_val;
3308
3309                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3310                 if (ret_val)
3311                         return ret_val;
3312         }
3313
3314         /*
3315          * For PCH, this write will make sure that any noise
3316          * will be detected as a CRC error and be dropped rather than show up
3317          * as a bad packet to the DMA engine.
3318          */
3319         if (hw->mac.type == e1000_pchlan)
3320                 ew32(CRC_OFFSET, 0x65656565);
3321
3322         ew32(IMC, 0xffffffff);
3323         er32(ICR);
3324
3325         reg = er32(KABGTXD);
3326         reg |= E1000_KABGTXD_BGSQLBIAS;
3327         ew32(KABGTXD, reg);
3328
3329         return 0;
3330 }
3331
3332 /**
3333  *  e1000_init_hw_ich8lan - Initialize the hardware
3334  *  @hw: pointer to the HW structure
3335  *
3336  *  Prepares the hardware for transmit and receive by doing the following:
3337  *   - initialize hardware bits
3338  *   - initialize LED identification
3339  *   - setup receive address registers
3340  *   - setup flow control
3341  *   - setup transmit descriptors
3342  *   - clear statistics
3343  **/
3344 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3345 {
3346         struct e1000_mac_info *mac = &hw->mac;
3347         u32 ctrl_ext, txdctl, snoop;
3348         s32 ret_val;
3349         u16 i;
3350
3351         e1000_initialize_hw_bits_ich8lan(hw);
3352
3353         /* Initialize identification LED */
3354         ret_val = mac->ops.id_led_init(hw);
3355         if (ret_val)
3356                 e_dbg("Error initializing identification LED\n");
3357                 /* This is not fatal and we should not stop init due to this */
3358
3359         /* Setup the receive address. */
3360         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3361
3362         /* Zero out the Multicast HASH table */
3363         e_dbg("Zeroing the MTA\n");
3364         for (i = 0; i < mac->mta_reg_count; i++)
3365                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3366
3367         /*
3368          * The 82578 Rx buffer will stall if wakeup is enabled in host and
3369          * the ME.  Disable wakeup by clearing the host wakeup bit.
3370          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3371          */
3372         if (hw->phy.type == e1000_phy_82578) {
3373                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3374                 i &= ~BM_WUC_HOST_WU_BIT;
3375                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
3376                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3377                 if (ret_val)
3378                         return ret_val;
3379         }
3380
3381         /* Setup link and flow control */
3382         ret_val = mac->ops.setup_link(hw);
3383
3384         /* Set the transmit descriptor write-back policy for both queues */
3385         txdctl = er32(TXDCTL(0));
3386         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3387                  E1000_TXDCTL_FULL_TX_DESC_WB;
3388         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3389                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3390         ew32(TXDCTL(0), txdctl);
3391         txdctl = er32(TXDCTL(1));
3392         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3393                  E1000_TXDCTL_FULL_TX_DESC_WB;
3394         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3395                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3396         ew32(TXDCTL(1), txdctl);
3397
3398         /*
3399          * ICH8 has opposite polarity of no_snoop bits.
3400          * By default, we should use snoop behavior.
3401          */
3402         if (mac->type == e1000_ich8lan)
3403                 snoop = PCIE_ICH8_SNOOP_ALL;
3404         else
3405                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3406         e1000e_set_pcie_no_snoop(hw, snoop);
3407
3408         ctrl_ext = er32(CTRL_EXT);
3409         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3410         ew32(CTRL_EXT, ctrl_ext);
3411
3412         /*
3413          * Clear all of the statistics registers (clear on read).  It is
3414          * important that we do this after we have tried to establish link
3415          * because the symbol error count will increment wildly if there
3416          * is no link.
3417          */
3418         e1000_clear_hw_cntrs_ich8lan(hw);
3419
3420         return ret_val;
3421 }
3422 /**
3423  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3424  *  @hw: pointer to the HW structure
3425  *
3426  *  Sets/Clears required hardware bits necessary for correctly setting up the
3427  *  hardware for transmit and receive.
3428  **/
3429 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3430 {
3431         u32 reg;
3432
3433         /* Extended Device Control */
3434         reg = er32(CTRL_EXT);
3435         reg |= (1 << 22);
3436         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3437         if (hw->mac.type >= e1000_pchlan)
3438                 reg |= E1000_CTRL_EXT_PHYPDEN;
3439         ew32(CTRL_EXT, reg);
3440
3441         /* Transmit Descriptor Control 0 */
3442         reg = er32(TXDCTL(0));
3443         reg |= (1 << 22);
3444         ew32(TXDCTL(0), reg);
3445
3446         /* Transmit Descriptor Control 1 */
3447         reg = er32(TXDCTL(1));
3448         reg |= (1 << 22);
3449         ew32(TXDCTL(1), reg);
3450
3451         /* Transmit Arbitration Control 0 */
3452         reg = er32(TARC(0));
3453         if (hw->mac.type == e1000_ich8lan)
3454                 reg |= (1 << 28) | (1 << 29);
3455         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3456         ew32(TARC(0), reg);
3457
3458         /* Transmit Arbitration Control 1 */
3459         reg = er32(TARC(1));
3460         if (er32(TCTL) & E1000_TCTL_MULR)
3461                 reg &= ~(1 << 28);
3462         else
3463                 reg |= (1 << 28);
3464         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3465         ew32(TARC(1), reg);
3466
3467         /* Device Status */
3468         if (hw->mac.type == e1000_ich8lan) {
3469                 reg = er32(STATUS);
3470                 reg &= ~(1 << 31);
3471                 ew32(STATUS, reg);
3472         }
3473
3474         /*
3475          * work-around descriptor data corruption issue during nfs v2 udp
3476          * traffic, just disable the nfs filtering capability
3477          */
3478         reg = er32(RFCTL);
3479         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3480         ew32(RFCTL, reg);
3481 }
3482
3483 /**
3484  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3485  *  @hw: pointer to the HW structure
3486  *
3487  *  Determines which flow control settings to use, then configures flow
3488  *  control.  Calls the appropriate media-specific link configuration
3489  *  function.  Assuming the adapter has a valid link partner, a valid link
3490  *  should be established.  Assumes the hardware has previously been reset
3491  *  and the transmitter and receiver are not enabled.
3492  **/
3493 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3494 {
3495         s32 ret_val;
3496
3497         if (hw->phy.ops.check_reset_block(hw))
3498                 return 0;
3499
3500         /*
3501          * ICH parts do not have a word in the NVM to determine
3502          * the default flow control setting, so we explicitly
3503          * set it to full.
3504          */
3505         if (hw->fc.requested_mode == e1000_fc_default) {
3506                 /* Workaround h/w hang when Tx flow control enabled */
3507                 if (hw->mac.type == e1000_pchlan)
3508                         hw->fc.requested_mode = e1000_fc_rx_pause;
3509                 else
3510                         hw->fc.requested_mode = e1000_fc_full;
3511         }
3512
3513         /*
3514          * Save off the requested flow control mode for use later.  Depending
3515          * on the link partner's capabilities, we may or may not use this mode.
3516          */
3517         hw->fc.current_mode = hw->fc.requested_mode;
3518
3519         e_dbg("After fix-ups FlowControl is now = %x\n",
3520                 hw->fc.current_mode);
3521
3522         /* Continue to configure the copper link. */
3523         ret_val = hw->mac.ops.setup_physical_interface(hw);
3524         if (ret_val)
3525                 return ret_val;
3526
3527         ew32(FCTTV, hw->fc.pause_time);
3528         if ((hw->phy.type == e1000_phy_82578) ||
3529             (hw->phy.type == e1000_phy_82579) ||
3530             (hw->phy.type == e1000_phy_82577)) {
3531                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3532
3533                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3534                                    hw->fc.pause_time);
3535                 if (ret_val)
3536                         return ret_val;
3537         }
3538
3539         return e1000e_set_fc_watermarks(hw);
3540 }
3541
3542 /**
3543  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3544  *  @hw: pointer to the HW structure
3545  *
3546  *  Configures the kumeran interface to the PHY to wait the appropriate time
3547  *  when polling the PHY, then call the generic setup_copper_link to finish
3548  *  configuring the copper link.
3549  **/
3550 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3551 {
3552         u32 ctrl;
3553         s32 ret_val;
3554         u16 reg_data;
3555
3556         ctrl = er32(CTRL);
3557         ctrl |= E1000_CTRL_SLU;
3558         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3559         ew32(CTRL, ctrl);
3560
3561         /*
3562          * Set the mac to wait the maximum time between each iteration
3563          * and increase the max iterations when polling the phy;
3564          * this fixes erroneous timeouts at 10Mbps.
3565          */
3566         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3567         if (ret_val)
3568                 return ret_val;
3569         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3570                                        &reg_data);
3571         if (ret_val)
3572                 return ret_val;
3573         reg_data |= 0x3F;
3574         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3575                                         reg_data);
3576         if (ret_val)
3577                 return ret_val;
3578
3579         switch (hw->phy.type) {
3580         case e1000_phy_igp_3:
3581                 ret_val = e1000e_copper_link_setup_igp(hw);
3582                 if (ret_val)
3583                         return ret_val;
3584                 break;
3585         case e1000_phy_bm:
3586         case e1000_phy_82578:
3587                 ret_val = e1000e_copper_link_setup_m88(hw);
3588                 if (ret_val)
3589                         return ret_val;
3590                 break;
3591         case e1000_phy_82577:
3592         case e1000_phy_82579:
3593                 ret_val = e1000_copper_link_setup_82577(hw);
3594                 if (ret_val)
3595                         return ret_val;
3596                 break;
3597         case e1000_phy_ife:
3598                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3599                 if (ret_val)
3600                         return ret_val;
3601
3602                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3603
3604                 switch (hw->phy.mdix) {
3605                 case 1:
3606                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3607                         break;
3608                 case 2:
3609                         reg_data |= IFE_PMC_FORCE_MDIX;
3610                         break;
3611                 case 0:
3612                 default:
3613                         reg_data |= IFE_PMC_AUTO_MDIX;
3614                         break;
3615                 }
3616                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3617                 if (ret_val)
3618                         return ret_val;
3619                 break;
3620         default:
3621                 break;
3622         }
3623
3624         return e1000e_setup_copper_link(hw);
3625 }
3626
3627 /**
3628  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3629  *  @hw: pointer to the HW structure
3630  *  @speed: pointer to store current link speed
3631  *  @duplex: pointer to store the current link duplex
3632  *
3633  *  Calls the generic get_speed_and_duplex to retrieve the current link
3634  *  information and then calls the Kumeran lock loss workaround for links at
3635  *  gigabit speeds.
3636  **/
3637 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3638                                           u16 *duplex)
3639 {
3640         s32 ret_val;
3641
3642         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3643         if (ret_val)
3644                 return ret_val;
3645
3646         if ((hw->mac.type == e1000_ich8lan) &&
3647             (hw->phy.type == e1000_phy_igp_3) &&
3648             (*speed == SPEED_1000)) {
3649                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3650         }
3651
3652         return ret_val;
3653 }
3654
3655 /**
3656  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3657  *  @hw: pointer to the HW structure
3658  *
3659  *  Work-around for 82566 Kumeran PCS lock loss:
3660  *  On link status change (i.e. PCI reset, speed change) and link is up and
3661  *  speed is gigabit-
3662  *    0) if workaround is optionally disabled do nothing
3663  *    1) wait 1ms for Kumeran link to come up
3664  *    2) check Kumeran Diagnostic register PCS lock loss bit
3665  *    3) if not set the link is locked (all is good), otherwise...
3666  *    4) reset the PHY
3667  *    5) repeat up to 10 times
3668  *  Note: this is only called for IGP3 copper when speed is 1gb.
3669  **/
3670 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3671 {
3672         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3673         u32 phy_ctrl;
3674         s32 ret_val;
3675         u16 i, data;
3676         bool link;
3677
3678         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3679                 return 0;
3680
3681         /*
3682          * Make sure link is up before proceeding.  If not just return.
3683          * Attempting this while link is negotiating fouled up link
3684          * stability
3685          */
3686         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3687         if (!link)
3688                 return 0;
3689
3690         for (i = 0; i < 10; i++) {
3691                 /* read once to clear */
3692                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3693                 if (ret_val)
3694                         return ret_val;
3695                 /* and again to get new status */
3696                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3697                 if (ret_val)
3698                         return ret_val;
3699
3700                 /* check for PCS lock */
3701                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3702                         return 0;
3703
3704                 /* Issue PHY reset */
3705                 e1000_phy_hw_reset(hw);
3706                 mdelay(5);
3707         }
3708         /* Disable GigE link negotiation */
3709         phy_ctrl = er32(PHY_CTRL);
3710         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3711                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3712         ew32(PHY_CTRL, phy_ctrl);
3713
3714         /*
3715          * Call gig speed drop workaround on Gig disable before accessing
3716          * any PHY registers
3717          */
3718         e1000e_gig_downshift_workaround_ich8lan(hw);
3719
3720         /* unable to acquire PCS lock */
3721         return -E1000_ERR_PHY;
3722 }
3723
3724 /**
3725  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3726  *  @hw: pointer to the HW structure
3727  *  @state: boolean value used to set the current Kumeran workaround state
3728  *
3729  *  If ICH8, set the current Kumeran workaround state (enabled - true
3730  *  /disabled - false).
3731  **/
3732 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3733                                                  bool state)
3734 {
3735         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3736
3737         if (hw->mac.type != e1000_ich8lan) {
3738                 e_dbg("Workaround applies to ICH8 only.\n");
3739                 return;
3740         }
3741
3742         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3743 }
3744
3745 /**
3746  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3747  *  @hw: pointer to the HW structure
3748  *
3749  *  Workaround for 82566 power-down on D3 entry:
3750  *    1) disable gigabit link
3751  *    2) write VR power-down enable
3752  *    3) read it back
3753  *  Continue if successful, else issue LCD reset and repeat
3754  **/
3755 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3756 {
3757         u32 reg;
3758         u16 data;
3759         u8  retry = 0;
3760
3761         if (hw->phy.type != e1000_phy_igp_3)
3762                 return;
3763
3764         /* Try the workaround twice (if needed) */
3765         do {
3766                 /* Disable link */
3767                 reg = er32(PHY_CTRL);
3768                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3769                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3770                 ew32(PHY_CTRL, reg);
3771
3772                 /*
3773                  * Call gig speed drop workaround on Gig disable before
3774                  * accessing any PHY registers
3775                  */
3776                 if (hw->mac.type == e1000_ich8lan)
3777                         e1000e_gig_downshift_workaround_ich8lan(hw);
3778
3779                 /* Write VR power-down enable */
3780                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3781                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3782                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3783
3784                 /* Read it back and test */
3785                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3786                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3787                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3788                         break;
3789
3790                 /* Issue PHY reset and repeat at most one more time */
3791                 reg = er32(CTRL);
3792                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3793                 retry++;
3794         } while (retry);
3795 }
3796
3797 /**
3798  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3799  *  @hw: pointer to the HW structure
3800  *
3801  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3802  *  LPLU, Gig disable, MDIC PHY reset):
3803  *    1) Set Kumeran Near-end loopback
3804  *    2) Clear Kumeran Near-end loopback
3805  *  Should only be called for ICH8[m] devices with any 1G Phy.
3806  **/
3807 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3808 {
3809         s32 ret_val;
3810         u16 reg_data;
3811
3812         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
3813                 return;
3814
3815         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3816                                       &reg_data);
3817         if (ret_val)
3818                 return;
3819         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3820         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3821                                        reg_data);
3822         if (ret_val)
3823                 return;
3824         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3825         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3826                                        reg_data);
3827 }
3828
3829 /**
3830  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
3831  *  @hw: pointer to the HW structure
3832  *
3833  *  During S0 to Sx transition, it is possible the link remains at gig
3834  *  instead of negotiating to a lower speed.  Before going to Sx, set
3835  *  'Gig Disable' to force link speed negotiation to a lower speed based on
3836  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
3837  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
3838  *  needs to be written.
3839  **/
3840 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
3841 {
3842         u32 phy_ctrl;
3843         s32 ret_val;
3844
3845         phy_ctrl = er32(PHY_CTRL);
3846         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
3847         ew32(PHY_CTRL, phy_ctrl);
3848
3849         if (hw->mac.type == e1000_ich8lan)
3850                 e1000e_gig_downshift_workaround_ich8lan(hw);
3851
3852         if (hw->mac.type >= e1000_pchlan) {
3853                 e1000_oem_bits_config_ich8lan(hw, false);
3854
3855                 /* Reset PHY to activate OEM bits on 82577/8 */
3856                 if (hw->mac.type == e1000_pchlan)
3857                         e1000e_phy_hw_reset_generic(hw);
3858
3859                 ret_val = hw->phy.ops.acquire(hw);
3860                 if (ret_val)
3861                         return;
3862                 e1000_write_smbus_addr(hw);
3863                 hw->phy.ops.release(hw);
3864         }
3865 }
3866
3867 /**
3868  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
3869  *  @hw: pointer to the HW structure
3870  *
3871  *  During Sx to S0 transitions on non-managed devices or managed devices
3872  *  on which PHY resets are not blocked, if the PHY registers cannot be
3873  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
3874  *  the PHY.
3875  **/
3876 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
3877 {
3878         s32 ret_val;
3879
3880         if (hw->mac.type < e1000_pch2lan)
3881                 return;
3882
3883         ret_val = e1000_init_phy_workarounds_pchlan(hw);
3884         if (ret_val) {
3885                 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
3886                 return;
3887         }
3888 }
3889
3890 /**
3891  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3892  *  @hw: pointer to the HW structure
3893  *
3894  *  Return the LED back to the default configuration.
3895  **/
3896 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3897 {
3898         if (hw->phy.type == e1000_phy_ife)
3899                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3900
3901         ew32(LEDCTL, hw->mac.ledctl_default);
3902         return 0;
3903 }
3904
3905 /**
3906  *  e1000_led_on_ich8lan - Turn LEDs on
3907  *  @hw: pointer to the HW structure
3908  *
3909  *  Turn on the LEDs.
3910  **/
3911 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3912 {
3913         if (hw->phy.type == e1000_phy_ife)
3914                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3915                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3916
3917         ew32(LEDCTL, hw->mac.ledctl_mode2);
3918         return 0;
3919 }
3920
3921 /**
3922  *  e1000_led_off_ich8lan - Turn LEDs off
3923  *  @hw: pointer to the HW structure
3924  *
3925  *  Turn off the LEDs.
3926  **/
3927 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3928 {
3929         if (hw->phy.type == e1000_phy_ife)
3930                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3931                                 (IFE_PSCL_PROBE_MODE |
3932                                  IFE_PSCL_PROBE_LEDS_OFF));
3933
3934         ew32(LEDCTL, hw->mac.ledctl_mode1);
3935         return 0;
3936 }
3937
3938 /**
3939  *  e1000_setup_led_pchlan - Configures SW controllable LED
3940  *  @hw: pointer to the HW structure
3941  *
3942  *  This prepares the SW controllable LED for use.
3943  **/
3944 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3945 {
3946         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
3947 }
3948
3949 /**
3950  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3951  *  @hw: pointer to the HW structure
3952  *
3953  *  Return the LED back to the default configuration.
3954  **/
3955 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3956 {
3957         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
3958 }
3959
3960 /**
3961  *  e1000_led_on_pchlan - Turn LEDs on
3962  *  @hw: pointer to the HW structure
3963  *
3964  *  Turn on the LEDs.
3965  **/
3966 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3967 {
3968         u16 data = (u16)hw->mac.ledctl_mode2;
3969         u32 i, led;
3970
3971         /*
3972          * If no link, then turn LED on by setting the invert bit
3973          * for each LED that's mode is "link_up" in ledctl_mode2.
3974          */
3975         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3976                 for (i = 0; i < 3; i++) {
3977                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3978                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3979                             E1000_LEDCTL_MODE_LINK_UP)
3980                                 continue;
3981                         if (led & E1000_PHY_LED0_IVRT)
3982                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3983                         else
3984                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3985                 }
3986         }
3987
3988         return e1e_wphy(hw, HV_LED_CONFIG, data);
3989 }
3990
3991 /**
3992  *  e1000_led_off_pchlan - Turn LEDs off
3993  *  @hw: pointer to the HW structure
3994  *
3995  *  Turn off the LEDs.
3996  **/
3997 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3998 {
3999         u16 data = (u16)hw->mac.ledctl_mode1;
4000         u32 i, led;
4001
4002         /*
4003          * If no link, then turn LED off by clearing the invert bit
4004          * for each LED that's mode is "link_up" in ledctl_mode1.
4005          */
4006         if (!(er32(STATUS) & E1000_STATUS_LU)) {
4007                 for (i = 0; i < 3; i++) {
4008                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4009                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4010                             E1000_LEDCTL_MODE_LINK_UP)
4011                                 continue;
4012                         if (led & E1000_PHY_LED0_IVRT)
4013                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4014                         else
4015                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4016                 }
4017         }
4018
4019         return e1e_wphy(hw, HV_LED_CONFIG, data);
4020 }
4021
4022 /**
4023  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
4024  *  @hw: pointer to the HW structure
4025  *
4026  *  Read appropriate register for the config done bit for completion status
4027  *  and configure the PHY through s/w for EEPROM-less parts.
4028  *
4029  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
4030  *  config done bit, so only an error is logged and continues.  If we were
4031  *  to return with error, EEPROM-less silicon would not be able to be reset
4032  *  or change link.
4033  **/
4034 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4035 {
4036         s32 ret_val = 0;
4037         u32 bank = 0;
4038         u32 status;
4039
4040         e1000e_get_cfg_done(hw);
4041
4042         /* Wait for indication from h/w that it has completed basic config */
4043         if (hw->mac.type >= e1000_ich10lan) {
4044                 e1000_lan_init_done_ich8lan(hw);
4045         } else {
4046                 ret_val = e1000e_get_auto_rd_done(hw);
4047                 if (ret_val) {
4048                         /*
4049                          * When auto config read does not complete, do not
4050                          * return with an error. This can happen in situations
4051                          * where there is no eeprom and prevents getting link.
4052                          */
4053                         e_dbg("Auto Read Done did not complete\n");
4054                         ret_val = 0;
4055                 }
4056         }
4057
4058         /* Clear PHY Reset Asserted bit */
4059         status = er32(STATUS);
4060         if (status & E1000_STATUS_PHYRA)
4061                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
4062         else
4063                 e_dbg("PHY Reset Asserted not set - needs delay\n");
4064
4065         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
4066         if (hw->mac.type <= e1000_ich9lan) {
4067                 if (!(er32(EECD) & E1000_EECD_PRES) &&
4068                     (hw->phy.type == e1000_phy_igp_3)) {
4069                         e1000e_phy_init_script_igp3(hw);
4070                 }
4071         } else {
4072                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
4073                         /* Maybe we should do a basic PHY config */
4074                         e_dbg("EEPROM not present\n");
4075                         ret_val = -E1000_ERR_CONFIG;
4076                 }
4077         }
4078
4079         return ret_val;
4080 }
4081
4082 /**
4083  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4084  * @hw: pointer to the HW structure
4085  *
4086  * In the case of a PHY power down to save power, or to turn off link during a
4087  * driver unload, or wake on lan is not enabled, remove the link.
4088  **/
4089 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
4090 {
4091         /* If the management interface is not enabled, then power down */
4092         if (!(hw->mac.ops.check_mng_mode(hw) ||
4093               hw->phy.ops.check_reset_block(hw)))
4094                 e1000_power_down_phy_copper(hw);
4095 }
4096
4097 /**
4098  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4099  *  @hw: pointer to the HW structure
4100  *
4101  *  Clears hardware counters specific to the silicon family and calls
4102  *  clear_hw_cntrs_generic to clear all general purpose counters.
4103  **/
4104 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4105 {
4106         u16 phy_data;
4107         s32 ret_val;
4108
4109         e1000e_clear_hw_cntrs_base(hw);
4110
4111         er32(ALGNERRC);
4112         er32(RXERRC);
4113         er32(TNCRS);
4114         er32(CEXTERR);
4115         er32(TSCTC);
4116         er32(TSCTFC);
4117
4118         er32(MGTPRC);
4119         er32(MGTPDC);
4120         er32(MGTPTC);
4121
4122         er32(IAC);
4123         er32(ICRXOC);
4124
4125         /* Clear PHY statistics registers */
4126         if ((hw->phy.type == e1000_phy_82578) ||
4127             (hw->phy.type == e1000_phy_82579) ||
4128             (hw->phy.type == e1000_phy_82577)) {
4129                 ret_val = hw->phy.ops.acquire(hw);
4130                 if (ret_val)
4131                         return;
4132                 ret_val = hw->phy.ops.set_page(hw,
4133                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
4134                 if (ret_val)
4135                         goto release;
4136                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4137                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4138                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4139                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4140                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4141                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4142                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4143                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4144                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4145                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4146                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4147                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4148                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4149                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4150 release:
4151                 hw->phy.ops.release(hw);
4152         }
4153 }
4154
4155 static const struct e1000_mac_operations ich8_mac_ops = {
4156         /* check_mng_mode dependent on mac type */
4157         .check_for_link         = e1000_check_for_copper_link_ich8lan,
4158         /* cleanup_led dependent on mac type */
4159         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
4160         .get_bus_info           = e1000_get_bus_info_ich8lan,
4161         .set_lan_id             = e1000_set_lan_id_single_port,
4162         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
4163         /* led_on dependent on mac type */
4164         /* led_off dependent on mac type */
4165         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
4166         .reset_hw               = e1000_reset_hw_ich8lan,
4167         .init_hw                = e1000_init_hw_ich8lan,
4168         .setup_link             = e1000_setup_link_ich8lan,
4169         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
4170         /* id_led_init dependent on mac type */
4171         .config_collision_dist  = e1000e_config_collision_dist_generic,
4172         .rar_set                = e1000e_rar_set_generic,
4173 };
4174
4175 static const struct e1000_phy_operations ich8_phy_ops = {
4176         .acquire                = e1000_acquire_swflag_ich8lan,
4177         .check_reset_block      = e1000_check_reset_block_ich8lan,
4178         .commit                 = NULL,
4179         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
4180         .get_cable_length       = e1000e_get_cable_length_igp_2,
4181         .read_reg               = e1000e_read_phy_reg_igp,
4182         .release                = e1000_release_swflag_ich8lan,
4183         .reset                  = e1000_phy_hw_reset_ich8lan,
4184         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
4185         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
4186         .write_reg              = e1000e_write_phy_reg_igp,
4187 };
4188
4189 static const struct e1000_nvm_operations ich8_nvm_ops = {
4190         .acquire                = e1000_acquire_nvm_ich8lan,
4191         .read                   = e1000_read_nvm_ich8lan,
4192         .release                = e1000_release_nvm_ich8lan,
4193         .reload                 = e1000e_reload_nvm_generic,
4194         .update                 = e1000_update_nvm_checksum_ich8lan,
4195         .valid_led_default      = e1000_valid_led_default_ich8lan,
4196         .validate               = e1000_validate_nvm_checksum_ich8lan,
4197         .write                  = e1000_write_nvm_ich8lan,
4198 };
4199
4200 const struct e1000_info e1000_ich8_info = {
4201         .mac                    = e1000_ich8lan,
4202         .flags                  = FLAG_HAS_WOL
4203                                   | FLAG_IS_ICH
4204                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4205                                   | FLAG_HAS_AMT
4206                                   | FLAG_HAS_FLASH
4207                                   | FLAG_APME_IN_WUC,
4208         .pba                    = 8,
4209         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
4210         .get_variants           = e1000_get_variants_ich8lan,
4211         .mac_ops                = &ich8_mac_ops,
4212         .phy_ops                = &ich8_phy_ops,
4213         .nvm_ops                = &ich8_nvm_ops,
4214 };
4215
4216 const struct e1000_info e1000_ich9_info = {
4217         .mac                    = e1000_ich9lan,
4218         .flags                  = FLAG_HAS_JUMBO_FRAMES
4219                                   | FLAG_IS_ICH
4220                                   | FLAG_HAS_WOL
4221                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4222                                   | FLAG_HAS_AMT
4223                                   | FLAG_HAS_FLASH
4224                                   | FLAG_APME_IN_WUC,
4225         .pba                    = 18,
4226         .max_hw_frame_size      = DEFAULT_JUMBO,
4227         .get_variants           = e1000_get_variants_ich8lan,
4228         .mac_ops                = &ich8_mac_ops,
4229         .phy_ops                = &ich8_phy_ops,
4230         .nvm_ops                = &ich8_nvm_ops,
4231 };
4232
4233 const struct e1000_info e1000_ich10_info = {
4234         .mac                    = e1000_ich10lan,
4235         .flags                  = FLAG_HAS_JUMBO_FRAMES
4236                                   | FLAG_IS_ICH
4237                                   | FLAG_HAS_WOL
4238                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4239                                   | FLAG_HAS_AMT
4240                                   | FLAG_HAS_FLASH
4241                                   | FLAG_APME_IN_WUC,
4242         .pba                    = 18,
4243         .max_hw_frame_size      = DEFAULT_JUMBO,
4244         .get_variants           = e1000_get_variants_ich8lan,
4245         .mac_ops                = &ich8_mac_ops,
4246         .phy_ops                = &ich8_phy_ops,
4247         .nvm_ops                = &ich8_nvm_ops,
4248 };
4249
4250 const struct e1000_info e1000_pch_info = {
4251         .mac                    = e1000_pchlan,
4252         .flags                  = FLAG_IS_ICH
4253                                   | FLAG_HAS_WOL
4254                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4255                                   | FLAG_HAS_AMT
4256                                   | FLAG_HAS_FLASH
4257                                   | FLAG_HAS_JUMBO_FRAMES
4258                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4259                                   | FLAG_APME_IN_WUC,
4260         .flags2                 = FLAG2_HAS_PHY_STATS,
4261         .pba                    = 26,
4262         .max_hw_frame_size      = 4096,
4263         .get_variants           = e1000_get_variants_ich8lan,
4264         .mac_ops                = &ich8_mac_ops,
4265         .phy_ops                = &ich8_phy_ops,
4266         .nvm_ops                = &ich8_nvm_ops,
4267 };
4268
4269 const struct e1000_info e1000_pch2_info = {
4270         .mac                    = e1000_pch2lan,
4271         .flags                  = FLAG_IS_ICH
4272                                   | FLAG_HAS_WOL
4273                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4274                                   | FLAG_HAS_AMT
4275                                   | FLAG_HAS_FLASH
4276                                   | FLAG_HAS_JUMBO_FRAMES
4277                                   | FLAG_APME_IN_WUC,
4278         .flags2                 = FLAG2_HAS_PHY_STATS
4279                                   | FLAG2_HAS_EEE,
4280         .pba                    = 26,
4281         .max_hw_frame_size      = DEFAULT_JUMBO,
4282         .get_variants           = e1000_get_variants_ich8lan,
4283         .mac_ops                = &ich8_mac_ops,
4284         .phy_ops                = &ich8_phy_ops,
4285         .nvm_ops                = &ich8_nvm_ops,
4286 };