drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 /* Intel PRO/1000 Linux driver
   2  * Copyright(c) 1999 - 2014 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * The full GNU General Public License is included in this distribution in
  14  * the file called "COPYING".
  15  *
  16  * Contact Information:
  17  * Linux NICS <linux.nics@intel.com>
  18  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  19  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  20  */
  21
  22 /* 82562G 10/100 Network Connection
  23  * 82562G-2 10/100 Network Connection
  24  * 82562GT 10/100 Network Connection
  25  * 82562GT-2 10/100 Network Connection
  26  * 82562V 10/100 Network Connection
  27  * 82562V-2 10/100 Network Connection
  28  * 82566DC-2 Gigabit Network Connection
  29  * 82566DC Gigabit Network Connection
  30  * 82566DM-2 Gigabit Network Connection
  31  * 82566DM Gigabit Network Connection
  32  * 82566MC Gigabit Network Connection
  33  * 82566MM Gigabit Network Connection
  34  * 82567LM Gigabit Network Connection
  35  * 82567LF Gigabit Network Connection
  36  * 82567V Gigabit Network Connection
  37  * 82567LM-2 Gigabit Network Connection
  38  * 82567LF-2 Gigabit Network Connection
  39  * 82567V-2 Gigabit Network Connection
  40  * 82567LF-3 Gigabit Network Connection
  41  * 82567LM-3 Gigabit Network Connection
  42  * 82567LM-4 Gigabit Network Connection
  43  * 82577LM Gigabit Network Connection
  44  * 82577LC Gigabit Network Connection
  45  * 82578DM Gigabit Network Connection
  46  * 82578DC Gigabit Network Connection
  47  * 82579LM Gigabit Network Connection
  48  * 82579V Gigabit Network Connection
  49  * Ethernet Connection I217-LM
  50  * Ethernet Connection I217-V
  51  * Ethernet Connection I218-V
  52  * Ethernet Connection I218-LM
  53  * Ethernet Connection (2) I218-LM
  54  * Ethernet Connection (2) I218-V
  55  * Ethernet Connection (3) I218-LM
  56  * Ethernet Connection (3) I218-V
  57  */
  58
  59 #include "e1000.h"
  60
  61 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
  62 /* Offset 04h HSFSTS */
  63 union ich8_hws_flash_status {
  64         struct ich8_hsfsts {
  65                 u16 flcdone:1;  /* bit 0 Flash Cycle Done */
  66                 u16 flcerr:1;   /* bit 1 Flash Cycle Error */
  67                 u16 dael:1;     /* bit 2 Direct Access error Log */
  68                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
  69                 u16 flcinprog:1;        /* bit 5 flash cycle in Progress */
  70                 u16 reserved1:2;        /* bit 13:6 Reserved */
  71                 u16 reserved2:6;        /* bit 13:6 Reserved */
  72                 u16 fldesvalid:1;       /* bit 14 Flash Descriptor Valid */
  73                 u16 flockdn:1;  /* bit 15 Flash Config Lock-Down */
  74         } hsf_status;
  75         u16 regval;
  76 };
  77
  78 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
  79 /* Offset 06h FLCTL */
  80 union ich8_hws_flash_ctrl {
  81         struct ich8_hsflctl {
  82                 u16 flcgo:1;    /* 0 Flash Cycle Go */
  83                 u16 flcycle:2;  /* 2:1 Flash Cycle */
  84                 u16 reserved:5; /* 7:3 Reserved  */
  85                 u16 fldbcount:2;        /* 9:8 Flash Data Byte Count */
  86                 u16 flockdn:6;  /* 15:10 Reserved */
  87         } hsf_ctrl;
  88         u16 regval;
  89 };
  90
  91 /* ICH Flash Region Access Permissions */
  92 union ich8_hws_flash_regacc {
  93         struct ich8_flracc {
  94                 u32 grra:8;     /* 0:7 GbE region Read Access */
  95                 u32 grwa:8;     /* 8:15 GbE region Write Access */
  96                 u32 gmrag:8;    /* 23:16 GbE Master Read Access Grant */
  97                 u32 gmwag:8;    /* 31:24 GbE Master Write Access Grant */
  98         } hsf_flregacc;
  99         u16 regval;
 100 };
 101
 102 /* ICH Flash Protected Region */
 103 union ich8_flash_protected_range {
 104         struct ich8_pr {
 105                 u32 base:13;    /* 0:12 Protected Range Base */
 106                 u32 reserved1:2;        /* 13:14 Reserved */
 107                 u32 rpe:1;      /* 15 Read Protection Enable */
 108                 u32 limit:13;   /* 16:28 Protected Range Limit */
 109                 u32 reserved2:2;        /* 29:30 Reserved */
 110                 u32 wpe:1;      /* 31 Write Protection Enable */
 111         } range;
 112         u32 regval;
 113 };
 114
 115 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 116 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 117 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 118 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 119                                                 u32 offset, u8 byte);
 120 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 121                                          u8 *data);
 122 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 123                                          u16 *data);
 124 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 125                                          u8 size, u16 *data);
 126 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 127 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 128 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 129 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 130 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 131 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 132 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 133 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 134 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 135 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 136 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 137 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 138 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 139 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 140 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 141 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 142 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 143 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
 144 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 145 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 146 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
 147 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 148 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
 149
 150 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 151 {
 152         return readw(hw->flash_address + reg);
 153 }
 154
 155 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 156 {
 157         return readl(hw->flash_address + reg);
 158 }
 159
 160 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 161 {
 162         writew(val, hw->flash_address + reg);
 163 }
 164
 165 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 166 {
 167         writel(val, hw->flash_address + reg);
 168 }
 169
 170 #define er16flash(reg)          __er16flash(hw, (reg))
 171 #define er32flash(reg)          __er32flash(hw, (reg))
 172 #define ew16flash(reg, val)     __ew16flash(hw, (reg), (val))
 173 #define ew32flash(reg, val)     __ew32flash(hw, (reg), (val))
 174
 175 /**
 176  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 177  *  @hw: pointer to the HW structure
 178  *
 179  *  Test access to the PHY registers by reading the PHY ID registers.  If
 180  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 181  *  otherwise assume the read PHY ID is correct if it is valid.
 182  *
 183  *  Assumes the sw/fw/hw semaphore is already acquired.
 184  **/
 185 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 186 {
 187         u16 phy_reg = 0;
 188         u32 phy_id = 0;
 189         s32 ret_val;
 190         u16 retry_count;
 191         u32 mac_reg = 0;
 192
 193         for (retry_count = 0; retry_count < 2; retry_count++) {
 194                 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
 195                 if (ret_val || (phy_reg == 0xFFFF))
 196                         continue;
 197                 phy_id = (u32)(phy_reg << 16);
 198
 199                 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
 200                 if (ret_val || (phy_reg == 0xFFFF)) {
 201                         phy_id = 0;
 202                         continue;
 203                 }
 204                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 205                 break;
 206         }
 207
 208         if (hw->phy.id) {
 209                 if (hw->phy.id == phy_id)
 210                         goto out;
 211         } else if (phy_id) {
 212                 hw->phy.id = phy_id;
 213                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 214                 goto out;
 215         }
 216
 217         /* In case the PHY needs to be in mdio slow mode,
 218          * set slow mode and try to get the PHY id again.
 219          */
 220         hw->phy.ops.release(hw);
 221         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 222         if (!ret_val)
 223                 ret_val = e1000e_get_phy_id(hw);
 224         hw->phy.ops.acquire(hw);
 225
 226         if (ret_val)
 227                 return false;
 228 out:
 229         if (hw->mac.type == e1000_pch_lpt) {
 230                 /* Unforce SMBus mode in PHY */
 231                 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
 232                 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 233                 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
 234
 235                 /* Unforce SMBus mode in MAC */
 236                 mac_reg = er32(CTRL_EXT);
 237                 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 238                 ew32(CTRL_EXT, mac_reg);
 239         }
 240
 241         return true;
 242 }
 243
 244 /**
 245  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 246  *  @hw: pointer to the HW structure
 247  *
 248  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 249  *  used to reset the PHY to a quiescent state when necessary.
 250  **/
 251 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 252 {
 253         u32 mac_reg;
 254
 255         /* Set Phy Config Counter to 50msec */
 256         mac_reg = er32(FEXTNVM3);
 257         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 258         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 259         ew32(FEXTNVM3, mac_reg);
 260
 261         /* Toggle LANPHYPC Value bit */
 262         mac_reg = er32(CTRL);
 263         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 264         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 265         ew32(CTRL, mac_reg);
 266         e1e_flush();
 267         usleep_range(10, 20);
 268         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 269         ew32(CTRL, mac_reg);
 270         e1e_flush();
 271
 272         if (hw->mac.type < e1000_pch_lpt) {
 273                 msleep(50);
 274         } else {
 275                 u16 count = 20;
 276
 277                 do {
 278                         usleep_range(5000, 10000);
 279                 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
 280
 281                 msleep(30);
 282         }
 283 }
 284
 285 /**
 286  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 287  *  @hw: pointer to the HW structure
 288  *
 289  *  Workarounds/flow necessary for PHY initialization during driver load
 290  *  and resume paths.
 291  **/
 292 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 293 {
 294         struct e1000_adapter *adapter = hw->adapter;
 295         u32 mac_reg, fwsm = er32(FWSM);
 296         s32 ret_val;
 297
 298         /* Gate automatic PHY configuration by hardware on managed and
 299          * non-managed 82579 and newer adapters.
 300          */
 301         e1000_gate_hw_phy_config_ich8lan(hw, true);
 302
 303         /* It is not possible to be certain of the current state of ULP
 304          * so forcibly disable it.
 305          */
 306         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 307         e1000_disable_ulp_lpt_lp(hw, true);
 308
 309         ret_val = hw->phy.ops.acquire(hw);
 310         if (ret_val) {
 311                 e_dbg("Failed to initialize PHY flow\n");
 312                 goto out;
 313         }
 314
 315         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 316          * inaccessible and resetting the PHY is not blocked, toggle the
 317          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 318          */
 319         switch (hw->mac.type) {
 320         case e1000_pch_lpt:
 321                 if (e1000_phy_is_accessible_pchlan(hw))
 322                         break;
 323
 324                 /* Before toggling LANPHYPC, see if PHY is accessible by
 325                  * forcing MAC to SMBus mode first.
 326                  */
 327                 mac_reg = er32(CTRL_EXT);
 328                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 329                 ew32(CTRL_EXT, mac_reg);
 330
 331                 /* Wait 50 milliseconds for MAC to finish any retries
 332                  * that it might be trying to perform from previous
 333                  * attempts to acknowledge any phy read requests.
 334                  */
 335                 msleep(50);
 336
 337                 /* fall-through */
 338         case e1000_pch2lan:
 339                 if (e1000_phy_is_accessible_pchlan(hw))
 340                         break;
 341
 342                 /* fall-through */
 343         case e1000_pchlan:
 344                 if ((hw->mac.type == e1000_pchlan) &&
 345                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 346                         break;
 347
 348                 if (hw->phy.ops.check_reset_block(hw)) {
 349                         e_dbg("Required LANPHYPC toggle blocked by ME\n");
 350                         ret_val = -E1000_ERR_PHY;
 351                         break;
 352                 }
 353
 354                 /* Toggle LANPHYPC Value bit */
 355                 e1000_toggle_lanphypc_pch_lpt(hw);
 356                 if (hw->mac.type >= e1000_pch_lpt) {
 357                         if (e1000_phy_is_accessible_pchlan(hw))
 358                                 break;
 359
 360                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 361                          * so ensure that the MAC is also out of SMBus mode
 362                          */
 363                         mac_reg = er32(CTRL_EXT);
 364                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 365                         ew32(CTRL_EXT, mac_reg);
 366
 367                         if (e1000_phy_is_accessible_pchlan(hw))
 368                                 break;
 369
 370                         ret_val = -E1000_ERR_PHY;
 371                 }
 372                 break;
 373         default:
 374                 break;
 375         }
 376
 377         hw->phy.ops.release(hw);
 378         if (!ret_val) {
 379
 380                 /* Check to see if able to reset PHY.  Print error if not */
 381                 if (hw->phy.ops.check_reset_block(hw)) {
 382                         e_err("Reset blocked by ME\n");
 383                         goto out;
 384                 }
 385
 386                 /* Reset the PHY before any access to it.  Doing so, ensures
 387                  * that the PHY is in a known good state before we read/write
 388                  * PHY registers.  The generic reset is sufficient here,
 389                  * because we haven't determined the PHY type yet.
 390                  */
 391                 ret_val = e1000e_phy_hw_reset_generic(hw);
 392                 if (ret_val)
 393                         goto out;
 394
 395                 /* On a successful reset, possibly need to wait for the PHY
 396                  * to quiesce to an accessible state before returning control
 397                  * to the calling function.  If the PHY does not quiesce, then
 398                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 399                  *  the PHY is in.
 400                  */
 401                 ret_val = hw->phy.ops.check_reset_block(hw);
 402                 if (ret_val)
 403                         e_err("ME blocked access to PHY after reset\n");
 404         }
 405
 406 out:
 407         /* Ungate automatic PHY configuration on non-managed 82579 */
 408         if ((hw->mac.type == e1000_pch2lan) &&
 409             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 410                 usleep_range(10000, 20000);
 411                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 412         }
 413
 414         return ret_val;
 415 }
 416
 417 /**
 418  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 419  *  @hw: pointer to the HW structure
 420  *
 421  *  Initialize family-specific PHY parameters and function pointers.
 422  **/
 423 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 424 {
 425         struct e1000_phy_info *phy = &hw->phy;
 426         s32 ret_val;
 427
 428         phy->addr = 1;
 429         phy->reset_delay_us = 100;
 430
 431         phy->ops.set_page = e1000_set_page_igp;
 432         phy->ops.read_reg = e1000_read_phy_reg_hv;
 433         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 434         phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
 435         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 436         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 437         phy->ops.write_reg = e1000_write_phy_reg_hv;
 438         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 439         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 440         phy->ops.power_up = e1000_power_up_phy_copper;
 441         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 442         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 443
 444         phy->id = e1000_phy_unknown;
 445
 446         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 447         if (ret_val)
 448                 return ret_val;
 449
 450         if (phy->id == e1000_phy_unknown)
 451                 switch (hw->mac.type) {
 452                 default:
 453                         ret_val = e1000e_get_phy_id(hw);
 454                         if (ret_val)
 455                                 return ret_val;
 456                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 457                                 break;
 458                         /* fall-through */
 459                 case e1000_pch2lan:
 460                 case e1000_pch_lpt:
 461                         /* In case the PHY needs to be in mdio slow mode,
 462                          * set slow mode and try to get the PHY id again.
 463                          */
 464                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 465                         if (ret_val)
 466                                 return ret_val;
 467                         ret_val = e1000e_get_phy_id(hw);
 468                         if (ret_val)
 469                                 return ret_val;
 470                         break;
 471                 }
 472         phy->type = e1000e_get_phy_type_from_id(phy->id);
 473
 474         switch (phy->type) {
 475         case e1000_phy_82577:
 476         case e1000_phy_82579:
 477         case e1000_phy_i217:
 478                 phy->ops.check_polarity = e1000_check_polarity_82577;
 479                 phy->ops.force_speed_duplex =
 480                     e1000_phy_force_speed_duplex_82577;
 481                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 482                 phy->ops.get_info = e1000_get_phy_info_82577;
 483                 phy->ops.commit = e1000e_phy_sw_reset;
 484                 break;
 485         case e1000_phy_82578:
 486                 phy->ops.check_polarity = e1000_check_polarity_m88;
 487                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 488                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 489                 phy->ops.get_info = e1000e_get_phy_info_m88;
 490                 break;
 491         default:
 492                 ret_val = -E1000_ERR_PHY;
 493                 break;
 494         }
 495
 496         return ret_val;
 497 }
 498
 499 /**
 500  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 501  *  @hw: pointer to the HW structure
 502  *
 503  *  Initialize family-specific PHY parameters and function pointers.
 504  **/
 505 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 506 {
 507         struct e1000_phy_info *phy = &hw->phy;
 508         s32 ret_val;
 509         u16 i = 0;
 510
 511         phy->addr = 1;
 512         phy->reset_delay_us = 100;
 513
 514         phy->ops.power_up = e1000_power_up_phy_copper;
 515         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 516
 517         /* We may need to do this twice - once for IGP and if that fails,
 518          * we'll set BM func pointers and try again
 519          */
 520         ret_val = e1000e_determine_phy_address(hw);
 521         if (ret_val) {
 522                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 523                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 524                 ret_val = e1000e_determine_phy_address(hw);
 525                 if (ret_val) {
 526                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 527                         return ret_val;
 528                 }
 529         }
 530
 531         phy->id = 0;
 532         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 533                (i++ < 100)) {
 534                 usleep_range(1000, 2000);
 535                 ret_val = e1000e_get_phy_id(hw);
 536                 if (ret_val)
 537                         return ret_val;
 538         }
 539
 540         /* Verify phy id */
 541         switch (phy->id) {
 542         case IGP03E1000_E_PHY_ID:
 543                 phy->type = e1000_phy_igp_3;
 544                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 545                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 546                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 547                 phy->ops.get_info = e1000e_get_phy_info_igp;
 548                 phy->ops.check_polarity = e1000_check_polarity_igp;
 549                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 550                 break;
 551         case IFE_E_PHY_ID:
 552         case IFE_PLUS_E_PHY_ID:
 553         case IFE_C_E_PHY_ID:
 554                 phy->type = e1000_phy_ife;
 555                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 556                 phy->ops.get_info = e1000_get_phy_info_ife;
 557                 phy->ops.check_polarity = e1000_check_polarity_ife;
 558                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 559                 break;
 560         case BME1000_E_PHY_ID:
 561                 phy->type = e1000_phy_bm;
 562                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 563                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 564                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 565                 phy->ops.commit = e1000e_phy_sw_reset;
 566                 phy->ops.get_info = e1000e_get_phy_info_m88;
 567                 phy->ops.check_polarity = e1000_check_polarity_m88;
 568                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 569                 break;
 570         default:
 571                 return -E1000_ERR_PHY;
 572                 break;
 573         }
 574
 575         return 0;
 576 }
 577
 578 /**
 579  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 580  *  @hw: pointer to the HW structure
 581  *
 582  *  Initialize family-specific NVM parameters and function
 583  *  pointers.
 584  **/
 585 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 586 {
 587         struct e1000_nvm_info *nvm = &hw->nvm;
 588         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 589         u32 gfpreg, sector_base_addr, sector_end_addr;
 590         u16 i;
 591
 592         /* Can't read flash registers if the register set isn't mapped. */
 593         if (!hw->flash_address) {
 594                 e_dbg("ERROR: Flash registers not mapped\n");
 595                 return -E1000_ERR_CONFIG;
 596         }
 597
 598         nvm->type = e1000_nvm_flash_sw;
 599
 600         gfpreg = er32flash(ICH_FLASH_GFPREG);
 601
 602         /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 603          * Add 1 to sector_end_addr since this sector is included in
 604          * the overall size.
 605          */
 606         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 607         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 608
 609         /* flash_base_addr is byte-aligned */
 610         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 611
 612         /* find total size of the NVM, then cut in half since the total
 613          * size represents two separate NVM banks.
 614          */
 615         nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 616                                 << FLASH_SECTOR_ADDR_SHIFT);
 617         nvm->flash_bank_size /= 2;
 618         /* Adjust to word count */
 619         nvm->flash_bank_size /= sizeof(u16);
 620
 621         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 622
 623         /* Clear shadow ram */
 624         for (i = 0; i < nvm->word_size; i++) {
 625                 dev_spec->shadow_ram[i].modified = false;
 626                 dev_spec->shadow_ram[i].value = 0xFFFF;
 627         }
 628
 629         return 0;
 630 }
 631
 632 /**
 633  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 634  *  @hw: pointer to the HW structure
 635  *
 636  *  Initialize family-specific MAC parameters and function
 637  *  pointers.
 638  **/
 639 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 640 {
 641         struct e1000_mac_info *mac = &hw->mac;
 642
 643         /* Set media type function pointer */
 644         hw->phy.media_type = e1000_media_type_copper;
 645
 646         /* Set mta register count */
 647         mac->mta_reg_count = 32;
 648         /* Set rar entry count */
 649         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 650         if (mac->type == e1000_ich8lan)
 651                 mac->rar_entry_count--;
 652         /* FWSM register */
 653         mac->has_fwsm = true;
 654         /* ARC subsystem not supported */
 655         mac->arc_subsystem_valid = false;
 656         /* Adaptive IFS supported */
 657         mac->adaptive_ifs = true;
 658
 659         /* LED and other operations */
 660         switch (mac->type) {
 661         case e1000_ich8lan:
 662         case e1000_ich9lan:
 663         case e1000_ich10lan:
 664                 /* check management mode */
 665                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 666                 /* ID LED init */
 667                 mac->ops.id_led_init = e1000e_id_led_init_generic;
 668                 /* blink LED */
 669                 mac->ops.blink_led = e1000e_blink_led_generic;
 670                 /* setup LED */
 671                 mac->ops.setup_led = e1000e_setup_led_generic;
 672                 /* cleanup LED */
 673                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 674                 /* turn on/off LED */
 675                 mac->ops.led_on = e1000_led_on_ich8lan;
 676                 mac->ops.led_off = e1000_led_off_ich8lan;
 677                 break;
 678         case e1000_pch2lan:
 679                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 680                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 681                 /* fall-through */
 682         case e1000_pch_lpt:
 683         case e1000_pchlan:
 684                 /* check management mode */
 685                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 686                 /* ID LED init */
 687                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 688                 /* setup LED */
 689                 mac->ops.setup_led = e1000_setup_led_pchlan;
 690                 /* cleanup LED */
 691                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 692                 /* turn on/off LED */
 693                 mac->ops.led_on = e1000_led_on_pchlan;
 694                 mac->ops.led_off = e1000_led_off_pchlan;
 695                 break;
 696         default:
 697                 break;
 698         }
 699
 700         if (mac->type == e1000_pch_lpt) {
 701                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 702                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 703                 mac->ops.setup_physical_interface =
 704                     e1000_setup_copper_link_pch_lpt;
 705         }
 706
 707         /* Enable PCS Lock-loss workaround for ICH8 */
 708         if (mac->type == e1000_ich8lan)
 709                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 710
 711         return 0;
 712 }
 713
 714 /**
 715  *  __e1000_access_emi_reg_locked - Read/write EMI register
 716  *  @hw: pointer to the HW structure
 717  *  @addr: EMI address to program
 718  *  @data: pointer to value to read/write from/to the EMI address
 719  *  @read: boolean flag to indicate read or write
 720  *
 721  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 722  **/
 723 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 724                                          u16 *data, bool read)
 725 {
 726         s32 ret_val;
 727
 728         ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
 729         if (ret_val)
 730                 return ret_val;
 731
 732         if (read)
 733                 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
 734         else
 735                 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
 736
 737         return ret_val;
 738 }
 739
 740 /**
 741  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 742  *  @hw: pointer to the HW structure
 743  *  @addr: EMI address to program
 744  *  @data: value to be read from the EMI address
 745  *
 746  *  Assumes the SW/FW/HW Semaphore is already acquired.
 747  **/
 748 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 749 {
 750         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 751 }
 752
 753 /**
 754  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 755  *  @hw: pointer to the HW structure
 756  *  @addr: EMI address to program
 757  *  @data: value to be written to the EMI address
 758  *
 759  *  Assumes the SW/FW/HW Semaphore is already acquired.
 760  **/
 761 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 762 {
 763         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 764 }
 765
 766 /**
 767  *  e1000_set_eee_pchlan - Enable/disable EEE support
 768  *  @hw: pointer to the HW structure
 769  *
 770  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 771  *  the link and the EEE capabilities of the link partner.  The LPI Control
 772  *  register bits will remain set only if/when link is up.
 773  *
 774  *  EEE LPI must not be asserted earlier than one second after link is up.
 775  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 776  *  can be link issues with some switches.  Other devices can have EEE LPI
 777  *  enabled immediately upon link up since they have a timer in hardware which
 778  *  prevents LPI from being asserted too early.
 779  **/
 780 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 781 {
 782         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 783         s32 ret_val;
 784         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 785
 786         switch (hw->phy.type) {
 787         case e1000_phy_82579:
 788                 lpa = I82579_EEE_LP_ABILITY;
 789                 pcs_status = I82579_EEE_PCS_STATUS;
 790                 adv_addr = I82579_EEE_ADVERTISEMENT;
 791                 break;
 792         case e1000_phy_i217:
 793                 lpa = I217_EEE_LP_ABILITY;
 794                 pcs_status = I217_EEE_PCS_STATUS;
 795                 adv_addr = I217_EEE_ADVERTISEMENT;
 796                 break;
 797         default:
 798                 return 0;
 799         }
 800
 801         ret_val = hw->phy.ops.acquire(hw);
 802         if (ret_val)
 803                 return ret_val;
 804
 805         ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 806         if (ret_val)
 807                 goto release;
 808
 809         /* Clear bits that enable EEE in various speeds */
 810         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 811
 812         /* Enable EEE if not disabled by user */
 813         if (!dev_spec->eee_disable) {
 814                 /* Save off link partner's EEE ability */
 815                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 816                                                     &dev_spec->eee_lp_ability);
 817                 if (ret_val)
 818                         goto release;
 819
 820                 /* Read EEE advertisement */
 821                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 822                 if (ret_val)
 823                         goto release;
 824
 825                 /* Enable EEE only for speeds in which the link partner is
 826                  * EEE capable and for which we advertise EEE.
 827                  */
 828                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 829                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 830
 831                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 832                         e1e_rphy_locked(hw, MII_LPA, &data);
 833                         if (data & LPA_100FULL)
 834                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 835                         else
 836                                 /* EEE is not supported in 100Half, so ignore
 837                                  * partner's EEE in 100 ability if full-duplex
 838                                  * is not advertised.
 839                                  */
 840                                 dev_spec->eee_lp_ability &=
 841                                     ~I82579_EEE_100_SUPPORTED;
 842                 }
 843         }
 844
 845         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 846         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 847         if (ret_val)
 848                 goto release;
 849
 850         ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 851 release:
 852         hw->phy.ops.release(hw);
 853
 854         return ret_val;
 855 }
 856
 857 /**
 858  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 859  *  @hw:   pointer to the HW structure
 860  *  @link: link up bool flag
 861  *
 862  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 863  *  preventing further DMA write requests.  Workaround the issue by disabling
 864  *  the de-assertion of the clock request when in 1Gpbs mode.
 865  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 866  *  speeds in order to avoid Tx hangs.
 867  **/
 868 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 869 {
 870         u32 fextnvm6 = er32(FEXTNVM6);
 871         u32 status = er32(STATUS);
 872         s32 ret_val = 0;
 873         u16 reg;
 874
 875         if (link && (status & E1000_STATUS_SPEED_1000)) {
 876                 ret_val = hw->phy.ops.acquire(hw);
 877                 if (ret_val)
 878                         return ret_val;
 879
 880                 ret_val =
 881                     e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 882                                                 &reg);
 883                 if (ret_val)
 884                         goto release;
 885
 886                 ret_val =
 887                     e1000e_write_kmrn_reg_locked(hw,
 888                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 889                                                  reg &
 890                                                  ~E1000_KMRNCTRLSTA_K1_ENABLE);
 891                 if (ret_val)
 892                         goto release;
 893
 894                 usleep_range(10, 20);
 895
 896                 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
 897
 898                 ret_val =
 899                     e1000e_write_kmrn_reg_locked(hw,
 900                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 901                                                  reg);
 902 release:
 903                 hw->phy.ops.release(hw);
 904         } else {
 905                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
 906                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
 907
 908                 if (!link || ((status & E1000_STATUS_SPEED_100) &&
 909                               (status & E1000_STATUS_FD)))
 910                         goto update_fextnvm6;
 911
 912                 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
 913                 if (ret_val)
 914                         return ret_val;
 915
 916                 /* Clear link status transmit timeout */
 917                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
 918
 919                 if (status & E1000_STATUS_SPEED_100) {
 920                         /* Set inband Tx timeout to 5x10us for 100Half */
 921                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 922
 923                         /* Do not extend the K1 entry latency for 100Half */
 924                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 925                 } else {
 926                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
 927                         reg |= 50 <<
 928                             I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 929
 930                         /* Extend the K1 entry latency for 10 Mbps */
 931                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 932                 }
 933
 934                 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
 935                 if (ret_val)
 936                         return ret_val;
 937
 938 update_fextnvm6:
 939                 ew32(FEXTNVM6, fextnvm6);
 940         }
 941
 942         return ret_val;
 943 }
 944
 945 /**
 946  *  e1000_platform_pm_pch_lpt - Set platform power management values
 947  *  @hw: pointer to the HW structure
 948  *  @link: bool indicating link status
 949  *
 950  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
 951  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
 952  *  when link is up (which must not exceed the maximum latency supported
 953  *  by the platform), otherwise specify there is no LTR requirement.
 954  *  Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
 955  *  latencies in the LTR Extended Capability Structure in the PCIe Extended
 956  *  Capability register set, on this device LTR is set by writing the
 957  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
 958  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
 959  *  message to the PMC.
 960  **/
 961 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
 962 {
 963         u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
 964             link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
 965         u16 lat_enc = 0;        /* latency encoded */
 966
 967         if (link) {
 968                 u16 speed, duplex, scale = 0;
 969                 u16 max_snoop, max_nosnoop;
 970                 u16 max_ltr_enc;        /* max LTR latency encoded */
 971                 s64 lat_ns;     /* latency (ns) */
 972                 s64 value;
 973                 u32 rxa;
 974
 975                 if (!hw->adapter->max_frame_size) {
 976                         e_dbg("max_frame_size not set.\n");
 977                         return -E1000_ERR_CONFIG;
 978                 }
 979
 980                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
 981                 if (!speed) {
 982                         e_dbg("Speed not set.\n");
 983                         return -E1000_ERR_CONFIG;
 984                 }
 985
 986                 /* Rx Packet Buffer Allocation size (KB) */
 987                 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
 988
 989                 /* Determine the maximum latency tolerated by the device.
 990                  *
 991                  * Per the PCIe spec, the tolerated latencies are encoded as
 992                  * a 3-bit encoded scale (only 0-5 are valid) multiplied by
 993                  * a 10-bit value (0-1023) to provide a range from 1 ns to
 994                  * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
 995                  * 1=2^5ns, 2=2^10ns,...5=2^25ns.
 996                  */
 997                 lat_ns = ((s64)rxa * 1024 -
 998                           (2 * (s64)hw->adapter->max_frame_size)) * 8 * 1000;
 999                 if (lat_ns < 0)
1000                         lat_ns = 0;
1001                 else
1002                         do_div(lat_ns, speed);
1003
1004                 value = lat_ns;
1005                 while (value > PCI_LTR_VALUE_MASK) {
1006                         scale++;
1007                         value = DIV_ROUND_UP(value, (1 << 5));
1008                 }
1009                 if (scale > E1000_LTRV_SCALE_MAX) {
1010                         e_dbg("Invalid LTR latency scale %d\n", scale);
1011                         return -E1000_ERR_CONFIG;
1012                 }
1013                 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1014
1015                 /* Determine the maximum latency tolerated by the platform */
1016                 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1017                                      &max_snoop);
1018                 pci_read_config_word(hw->adapter->pdev,
1019                                      E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1020                 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1021
1022                 if (lat_enc > max_ltr_enc)
1023                         lat_enc = max_ltr_enc;
1024         }
1025
1026         /* Set Snoop and No-Snoop latencies the same */
1027         reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1028         ew32(LTRV, reg);
1029
1030         return 0;
1031 }
1032
1033 /**
1034  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1035  *  @hw: pointer to the HW structure
1036  *  @to_sx: boolean indicating a system power state transition to Sx
1037  *
1038  *  When link is down, configure ULP mode to significantly reduce the power
1039  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1040  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1041  *  system, configure the ULP mode by software.
1042  */
1043 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1044 {
1045         u32 mac_reg;
1046         s32 ret_val = 0;
1047         u16 phy_reg;
1048
1049         if ((hw->mac.type < e1000_pch_lpt) ||
1050             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1051             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1052             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1053             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1054             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1055                 return 0;
1056
1057         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1058                 /* Request ME configure ULP mode in the PHY */
1059                 mac_reg = er32(H2ME);
1060                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1061                 ew32(H2ME, mac_reg);
1062
1063                 goto out;
1064         }
1065
1066         if (!to_sx) {
1067                 int i = 0;
1068
1069                 /* Poll up to 5 seconds for Cable Disconnected indication */
1070                 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1071                         /* Bail if link is re-acquired */
1072                         if (er32(STATUS) & E1000_STATUS_LU)
1073                                 return -E1000_ERR_PHY;
1074
1075                         if (i++ == 100)
1076                                 break;
1077
1078                         msleep(50);
1079                 }
1080                 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1081                       (er32(FEXT) &
1082                        E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1083         }
1084
1085         ret_val = hw->phy.ops.acquire(hw);
1086         if (ret_val)
1087                 goto out;
1088
1089         /* Force SMBus mode in PHY */
1090         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1091         if (ret_val)
1092                 goto release;
1093         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1094         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1095
1096         /* Force SMBus mode in MAC */
1097         mac_reg = er32(CTRL_EXT);
1098         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1099         ew32(CTRL_EXT, mac_reg);
1100
1101         /* Set Inband ULP Exit, Reset to SMBus mode and
1102          * Disable SMBus Release on PERST# in PHY
1103          */
1104         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1105         if (ret_val)
1106                 goto release;
1107         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1108                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1109         if (to_sx) {
1110                 if (er32(WUFC) & E1000_WUFC_LNKC)
1111                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1112
1113                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1114         } else {
1115                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1116         }
1117         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1118
1119         /* Set Disable SMBus Release on PERST# in MAC */
1120         mac_reg = er32(FEXTNVM7);
1121         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1122         ew32(FEXTNVM7, mac_reg);
1123
1124         /* Commit ULP changes in PHY by starting auto ULP configuration */
1125         phy_reg |= I218_ULP_CONFIG1_START;
1126         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1127 release:
1128         hw->phy.ops.release(hw);
1129 out:
1130         if (ret_val)
1131                 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1132         else
1133                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1134
1135         return ret_val;
1136 }
1137
1138 /**
1139  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1140  *  @hw: pointer to the HW structure
1141  *  @force: boolean indicating whether or not to force disabling ULP
1142  *
1143  *  Un-configure ULP mode when link is up, the system is transitioned from
1144  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1145  *  system, poll for an indication from ME that ULP has been un-configured.
1146  *  If not on an ME enabled system, un-configure the ULP mode by software.
1147  *
1148  *  During nominal operation, this function is called when link is acquired
1149  *  to disable ULP mode (force=false); otherwise, for example when unloading
1150  *  the driver or during Sx->S0 transitions, this is called with force=true
1151  *  to forcibly disable ULP.
1152  */
1153 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1154 {
1155         s32 ret_val = 0;
1156         u32 mac_reg;
1157         u16 phy_reg;
1158         int i = 0;
1159
1160         if ((hw->mac.type < e1000_pch_lpt) ||
1161             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1162             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1163             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1164             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1165             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1166                 return 0;
1167
1168         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1169                 if (force) {
1170                         /* Request ME un-configure ULP mode in the PHY */
1171                         mac_reg = er32(H2ME);
1172                         mac_reg &= ~E1000_H2ME_ULP;
1173                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1174                         ew32(H2ME, mac_reg);
1175                 }
1176
1177                 /* Poll up to 100msec for ME to clear ULP_CFG_DONE */
1178                 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1179                         if (i++ == 10) {
1180                                 ret_val = -E1000_ERR_PHY;
1181                                 goto out;
1182                         }
1183
1184                         usleep_range(10000, 20000);
1185                 }
1186                 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1187
1188                 if (force) {
1189                         mac_reg = er32(H2ME);
1190                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1191                         ew32(H2ME, mac_reg);
1192                 } else {
1193                         /* Clear H2ME.ULP after ME ULP configuration */
1194                         mac_reg = er32(H2ME);
1195                         mac_reg &= ~E1000_H2ME_ULP;
1196                         ew32(H2ME, mac_reg);
1197                 }
1198
1199                 goto out;
1200         }
1201
1202         ret_val = hw->phy.ops.acquire(hw);
1203         if (ret_val)
1204                 goto out;
1205
1206         if (force)
1207                 /* Toggle LANPHYPC Value bit */
1208                 e1000_toggle_lanphypc_pch_lpt(hw);
1209
1210         /* Unforce SMBus mode in PHY */
1211         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1212         if (ret_val) {
1213                 /* The MAC might be in PCIe mode, so temporarily force to
1214                  * SMBus mode in order to access the PHY.
1215                  */
1216                 mac_reg = er32(CTRL_EXT);
1217                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1218                 ew32(CTRL_EXT, mac_reg);
1219
1220                 msleep(50);
1221
1222                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1223                                                        &phy_reg);
1224                 if (ret_val)
1225                         goto release;
1226         }
1227         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1228         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1229
1230         /* Unforce SMBus mode in MAC */
1231         mac_reg = er32(CTRL_EXT);
1232         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1233         ew32(CTRL_EXT, mac_reg);
1234
1235         /* When ULP mode was previously entered, K1 was disabled by the
1236          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1237          */
1238         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1239         if (ret_val)
1240                 goto release;
1241         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1242         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1243
1244         /* Clear ULP enabled configuration */
1245         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1246         if (ret_val)
1247                 goto release;
1248         phy_reg &= ~(I218_ULP_CONFIG1_IND |
1249                      I218_ULP_CONFIG1_STICKY_ULP |
1250                      I218_ULP_CONFIG1_RESET_TO_SMBUS |
1251                      I218_ULP_CONFIG1_WOL_HOST |
1252                      I218_ULP_CONFIG1_INBAND_EXIT |
1253                      I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1254         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1255
1256         /* Commit ULP changes by starting auto ULP configuration */
1257         phy_reg |= I218_ULP_CONFIG1_START;
1258         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1259
1260         /* Clear Disable SMBus Release on PERST# in MAC */
1261         mac_reg = er32(FEXTNVM7);
1262         mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1263         ew32(FEXTNVM7, mac_reg);
1264
1265 release:
1266         hw->phy.ops.release(hw);
1267         if (force) {
1268                 e1000_phy_hw_reset(hw);
1269                 msleep(50);
1270         }
1271 out:
1272         if (ret_val)
1273                 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1274         else
1275                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1276
1277         return ret_val;
1278 }
1279
1280 /**
1281  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1282  *  @hw: pointer to the HW structure
1283  *
1284  *  Checks to see of the link status of the hardware has changed.  If a
1285  *  change in link status has been detected, then we read the PHY registers
1286  *  to get the current speed/duplex if link exists.
1287  **/
1288 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1289 {
1290         struct e1000_mac_info *mac = &hw->mac;
1291         s32 ret_val;
1292         bool link;
1293         u16 phy_reg;
1294
1295         /* We only want to go out to the PHY registers to see if Auto-Neg
1296          * has completed and/or if our link status has changed.  The
1297          * get_link_status flag is set upon receiving a Link Status
1298          * Change or Rx Sequence Error interrupt.
1299          */
1300         if (!mac->get_link_status)
1301                 return 0;
1302
1303         /* First we want to see if the MII Status Register reports
1304          * link.  If so, then we want to get the current speed/duplex
1305          * of the PHY.
1306          */
1307         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1308         if (ret_val)
1309                 return ret_val;
1310
1311         if (hw->mac.type == e1000_pchlan) {
1312                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1313                 if (ret_val)
1314                         return ret_val;
1315         }
1316
1317         /* When connected at 10Mbps half-duplex, 82579 parts are excessively
1318          * aggressive resulting in many collisions. To avoid this, increase
1319          * the IPG and reduce Rx latency in the PHY.
1320          */
1321         if ((hw->mac.type == e1000_pch2lan) && link) {
1322                 u32 reg;
1323
1324                 reg = er32(STATUS);
1325                 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1326                         reg = er32(TIPG);
1327                         reg &= ~E1000_TIPG_IPGT_MASK;
1328                         reg |= 0xFF;
1329                         ew32(TIPG, reg);
1330
1331                         /* Reduce Rx latency in analog PHY */
1332                         ret_val = hw->phy.ops.acquire(hw);
1333                         if (ret_val)
1334                                 return ret_val;
1335
1336                         ret_val =
1337                             e1000_write_emi_reg_locked(hw, I82579_RX_CONFIG, 0);
1338
1339                         hw->phy.ops.release(hw);
1340
1341                         if (ret_val)
1342                                 return ret_val;
1343                 }
1344         }
1345
1346         /* Work-around I218 hang issue */
1347         if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1348             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1349             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1350             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1351                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1352                 if (ret_val)
1353                         return ret_val;
1354         }
1355
1356         if (hw->mac.type == e1000_pch_lpt) {
1357                 /* Set platform power management values for
1358                  * Latency Tolerance Reporting (LTR)
1359                  */
1360                 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1361                 if (ret_val)
1362                         return ret_val;
1363         }
1364
1365         /* Clear link partner's EEE ability */
1366         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1367
1368         if (!link)
1369                 return 0;       /* No link detected */
1370
1371         mac->get_link_status = false;
1372
1373         switch (hw->mac.type) {
1374         case e1000_pch2lan:
1375                 ret_val = e1000_k1_workaround_lv(hw);
1376                 if (ret_val)
1377                         return ret_val;
1378                 /* fall-thru */
1379         case e1000_pchlan:
1380                 if (hw->phy.type == e1000_phy_82578) {
1381                         ret_val = e1000_link_stall_workaround_hv(hw);
1382                         if (ret_val)
1383                                 return ret_val;
1384                 }
1385
1386                 /* Workaround for PCHx parts in half-duplex:
1387                  * Set the number of preambles removed from the packet
1388                  * when it is passed from the PHY to the MAC to prevent
1389                  * the MAC from misinterpreting the packet type.
1390                  */
1391                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1392                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1393
1394                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1395                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1396
1397                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1398                 break;
1399         default:
1400                 break;
1401         }
1402
1403         /* Check if there was DownShift, must be checked
1404          * immediately after link-up
1405          */
1406         e1000e_check_downshift(hw);
1407
1408         /* Enable/Disable EEE after link up */
1409         if (hw->phy.type > e1000_phy_82579) {
1410                 ret_val = e1000_set_eee_pchlan(hw);
1411                 if (ret_val)
1412                         return ret_val;
1413         }
1414
1415         /* If we are forcing speed/duplex, then we simply return since
1416          * we have already determined whether we have link or not.
1417          */
1418         if (!mac->autoneg)
1419                 return -E1000_ERR_CONFIG;
1420
1421         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1422          * of MAC speed/duplex configuration.  So we only need to
1423          * configure Collision Distance in the MAC.
1424          */
1425         mac->ops.config_collision_dist(hw);
1426
1427         /* Configure Flow Control now that Auto-Neg has completed.
1428          * First, we need to restore the desired flow control
1429          * settings because we may have had to re-autoneg with a
1430          * different link partner.
1431          */
1432         ret_val = e1000e_config_fc_after_link_up(hw);
1433         if (ret_val)
1434                 e_dbg("Error configuring flow control\n");
1435
1436         return ret_val;
1437 }
1438
1439 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1440 {
1441         struct e1000_hw *hw = &adapter->hw;
1442         s32 rc;
1443
1444         rc = e1000_init_mac_params_ich8lan(hw);
1445         if (rc)
1446                 return rc;
1447
1448         rc = e1000_init_nvm_params_ich8lan(hw);
1449         if (rc)
1450                 return rc;
1451
1452         switch (hw->mac.type) {
1453         case e1000_ich8lan:
1454         case e1000_ich9lan:
1455         case e1000_ich10lan:
1456                 rc = e1000_init_phy_params_ich8lan(hw);
1457                 break;
1458         case e1000_pchlan:
1459         case e1000_pch2lan:
1460         case e1000_pch_lpt:
1461                 rc = e1000_init_phy_params_pchlan(hw);
1462                 break;
1463         default:
1464                 break;
1465         }
1466         if (rc)
1467                 return rc;
1468
1469         /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1470          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1471          */
1472         if ((adapter->hw.phy.type == e1000_phy_ife) ||
1473             ((adapter->hw.mac.type >= e1000_pch2lan) &&
1474              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1475                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1476                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
1477
1478                 hw->mac.ops.blink_led = NULL;
1479         }
1480
1481         if ((adapter->hw.mac.type == e1000_ich8lan) &&
1482             (adapter->hw.phy.type != e1000_phy_ife))
1483                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1484
1485         /* Enable workaround for 82579 w/ ME enabled */
1486         if ((adapter->hw.mac.type == e1000_pch2lan) &&
1487             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1488                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1489
1490         return 0;
1491 }
1492
1493 static DEFINE_MUTEX(nvm_mutex);
1494
1495 /**
1496  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1497  *  @hw: pointer to the HW structure
1498  *
1499  *  Acquires the mutex for performing NVM operations.
1500  **/
1501 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1502 {
1503         mutex_lock(&nvm_mutex);
1504
1505         return 0;
1506 }
1507
1508 /**
1509  *  e1000_release_nvm_ich8lan - Release NVM mutex
1510  *  @hw: pointer to the HW structure
1511  *
1512  *  Releases the mutex used while performing NVM operations.
1513  **/
1514 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1515 {
1516         mutex_unlock(&nvm_mutex);
1517 }
1518
1519 /**
1520  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1521  *  @hw: pointer to the HW structure
1522  *
1523  *  Acquires the software control flag for performing PHY and select
1524  *  MAC CSR accesses.
1525  **/
1526 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1527 {
1528         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1529         s32 ret_val = 0;
1530
1531         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1532                              &hw->adapter->state)) {
1533                 e_dbg("contention for Phy access\n");
1534                 return -E1000_ERR_PHY;
1535         }
1536
1537         while (timeout) {
1538                 extcnf_ctrl = er32(EXTCNF_CTRL);
1539                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1540                         break;
1541
1542                 mdelay(1);
1543                 timeout--;
1544         }
1545
1546         if (!timeout) {
1547                 e_dbg("SW has already locked the resource.\n");
1548                 ret_val = -E1000_ERR_CONFIG;
1549                 goto out;
1550         }
1551
1552         timeout = SW_FLAG_TIMEOUT;
1553
1554         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1555         ew32(EXTCNF_CTRL, extcnf_ctrl);
1556
1557         while (timeout) {
1558                 extcnf_ctrl = er32(EXTCNF_CTRL);
1559                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1560                         break;
1561
1562                 mdelay(1);
1563                 timeout--;
1564         }
1565
1566         if (!timeout) {
1567                 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1568                       er32(FWSM), extcnf_ctrl);
1569                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1570                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1571                 ret_val = -E1000_ERR_CONFIG;
1572                 goto out;
1573         }
1574
1575 out:
1576         if (ret_val)
1577                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1578
1579         return ret_val;
1580 }
1581
1582 /**
1583  *  e1000_release_swflag_ich8lan - Release software control flag
1584  *  @hw: pointer to the HW structure
1585  *
1586  *  Releases the software control flag for performing PHY and select
1587  *  MAC CSR accesses.
1588  **/
1589 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1590 {
1591         u32 extcnf_ctrl;
1592
1593         extcnf_ctrl = er32(EXTCNF_CTRL);
1594
1595         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1596                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1597                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1598         } else {
1599                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1600         }
1601
1602         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1603 }
1604
1605 /**
1606  *  e1000_check_mng_mode_ich8lan - Checks management mode
1607  *  @hw: pointer to the HW structure
1608  *
1609  *  This checks if the adapter has any manageability enabled.
1610  *  This is a function pointer entry point only called by read/write
1611  *  routines for the PHY and NVM parts.
1612  **/
1613 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1614 {
1615         u32 fwsm;
1616
1617         fwsm = er32(FWSM);
1618         return ((fwsm & E1000_ICH_FWSM_FW_VALID) &&
1619                 ((fwsm & E1000_FWSM_MODE_MASK) ==
1620                  (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)));
1621 }
1622
1623 /**
1624  *  e1000_check_mng_mode_pchlan - Checks management mode
1625  *  @hw: pointer to the HW structure
1626  *
1627  *  This checks if the adapter has iAMT enabled.
1628  *  This is a function pointer entry point only called by read/write
1629  *  routines for the PHY and NVM parts.
1630  **/
1631 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1632 {
1633         u32 fwsm;
1634
1635         fwsm = er32(FWSM);
1636         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1637             (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1638 }
1639
1640 /**
1641  *  e1000_rar_set_pch2lan - Set receive address register
1642  *  @hw: pointer to the HW structure
1643  *  @addr: pointer to the receive address
1644  *  @index: receive address array register
1645  *
1646  *  Sets the receive address array register at index to the address passed
1647  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1648  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1649  *  Use SHRA[0-3] in place of those reserved for ME.
1650  **/
1651 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1652 {
1653         u32 rar_low, rar_high;
1654
1655         /* HW expects these in little endian so we reverse the byte order
1656          * from network order (big endian) to little endian
1657          */
1658         rar_low = ((u32)addr[0] |
1659                    ((u32)addr[1] << 8) |
1660                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1661
1662         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1663
1664         /* If MAC address zero, no need to set the AV bit */
1665         if (rar_low || rar_high)
1666                 rar_high |= E1000_RAH_AV;
1667
1668         if (index == 0) {
1669                 ew32(RAL(index), rar_low);
1670                 e1e_flush();
1671                 ew32(RAH(index), rar_high);
1672                 e1e_flush();
1673                 return;
1674         }
1675
1676         /* RAR[1-6] are owned by manageability.  Skip those and program the
1677          * next address into the SHRA register array.
1678          */
1679         if (index < (u32)(hw->mac.rar_entry_count)) {
1680                 s32 ret_val;
1681
1682                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1683                 if (ret_val)
1684                         goto out;
1685
1686                 ew32(SHRAL(index - 1), rar_low);
1687                 e1e_flush();
1688                 ew32(SHRAH(index - 1), rar_high);
1689                 e1e_flush();
1690
1691                 e1000_release_swflag_ich8lan(hw);
1692
1693                 /* verify the register updates */
1694                 if ((er32(SHRAL(index - 1)) == rar_low) &&
1695                     (er32(SHRAH(index - 1)) == rar_high))
1696                         return;
1697
1698                 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1699                       (index - 1), er32(FWSM));
1700         }
1701
1702 out:
1703         e_dbg("Failed to write receive address at index %d\n", index);
1704 }
1705
1706 /**
1707  *  e1000_rar_set_pch_lpt - Set receive address registers
1708  *  @hw: pointer to the HW structure
1709  *  @addr: pointer to the receive address
1710  *  @index: receive address array register
1711  *
1712  *  Sets the receive address register array at index to the address passed
1713  *  in by addr. For LPT, RAR[0] is the base address register that is to
1714  *  contain the MAC address. SHRA[0-10] are the shared receive address
1715  *  registers that are shared between the Host and manageability engine (ME).
1716  **/
1717 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1718 {
1719         u32 rar_low, rar_high;
1720         u32 wlock_mac;
1721
1722         /* HW expects these in little endian so we reverse the byte order
1723          * from network order (big endian) to little endian
1724          */
1725         rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1726                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1727
1728         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1729
1730         /* If MAC address zero, no need to set the AV bit */
1731         if (rar_low || rar_high)
1732                 rar_high |= E1000_RAH_AV;
1733
1734         if (index == 0) {
1735                 ew32(RAL(index), rar_low);
1736                 e1e_flush();
1737                 ew32(RAH(index), rar_high);
1738                 e1e_flush();
1739                 return;
1740         }
1741
1742         /* The manageability engine (ME) can lock certain SHRAR registers that
1743          * it is using - those registers are unavailable for use.
1744          */
1745         if (index < hw->mac.rar_entry_count) {
1746                 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1747                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1748
1749                 /* Check if all SHRAR registers are locked */
1750                 if (wlock_mac == 1)
1751                         goto out;
1752
1753                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1754                         s32 ret_val;
1755
1756                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1757
1758                         if (ret_val)
1759                                 goto out;
1760
1761                         ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1762                         e1e_flush();
1763                         ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1764                         e1e_flush();
1765
1766                         e1000_release_swflag_ich8lan(hw);
1767
1768                         /* verify the register updates */
1769                         if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1770                             (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1771                                 return;
1772                 }
1773         }
1774
1775 out:
1776         e_dbg("Failed to write receive address at index %d\n", index);
1777 }
1778
1779 /**
1780  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1781  *  @hw: pointer to the HW structure
1782  *
1783  *  Checks if firmware is blocking the reset of the PHY.
1784  *  This is a function pointer entry point only called by
1785  *  reset routines.
1786  **/
1787 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1788 {
1789         bool blocked = false;
1790         int i = 0;
1791
1792         while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
1793                (i++ < 10))
1794                 usleep_range(10000, 20000);
1795         return blocked ? E1000_BLK_PHY_RESET : 0;
1796 }
1797
1798 /**
1799  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1800  *  @hw: pointer to the HW structure
1801  *
1802  *  Assumes semaphore already acquired.
1803  *
1804  **/
1805 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1806 {
1807         u16 phy_data;
1808         u32 strap = er32(STRAP);
1809         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1810             E1000_STRAP_SMT_FREQ_SHIFT;
1811         s32 ret_val;
1812
1813         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1814
1815         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1816         if (ret_val)
1817                 return ret_val;
1818
1819         phy_data &= ~HV_SMB_ADDR_MASK;
1820         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1821         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1822
1823         if (hw->phy.type == e1000_phy_i217) {
1824                 /* Restore SMBus frequency */
1825                 if (freq--) {
1826                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1827                         phy_data |= (freq & (1 << 0)) <<
1828                             HV_SMB_ADDR_FREQ_LOW_SHIFT;
1829                         phy_data |= (freq & (1 << 1)) <<
1830                             (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1831                 } else {
1832                         e_dbg("Unsupported SMB frequency in PHY\n");
1833                 }
1834         }
1835
1836         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1837 }
1838
1839 /**
1840  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1841  *  @hw:   pointer to the HW structure
1842  *
1843  *  SW should configure the LCD from the NVM extended configuration region
1844  *  as a workaround for certain parts.
1845  **/
1846 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1847 {
1848         struct e1000_phy_info *phy = &hw->phy;
1849         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1850         s32 ret_val = 0;
1851         u16 word_addr, reg_data, reg_addr, phy_page = 0;
1852
1853         /* Initialize the PHY from the NVM on ICH platforms.  This
1854          * is needed due to an issue where the NVM configuration is
1855          * not properly autoloaded after power transitions.
1856          * Therefore, after each PHY reset, we will load the
1857          * configuration data out of the NVM manually.
1858          */
1859         switch (hw->mac.type) {
1860         case e1000_ich8lan:
1861                 if (phy->type != e1000_phy_igp_3)
1862                         return ret_val;
1863
1864                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1865                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1866                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1867                         break;
1868                 }
1869                 /* Fall-thru */
1870         case e1000_pchlan:
1871         case e1000_pch2lan:
1872         case e1000_pch_lpt:
1873                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1874                 break;
1875         default:
1876                 return ret_val;
1877         }
1878
1879         ret_val = hw->phy.ops.acquire(hw);
1880         if (ret_val)
1881                 return ret_val;
1882
1883         data = er32(FEXTNVM);
1884         if (!(data & sw_cfg_mask))
1885                 goto release;
1886
1887         /* Make sure HW does not configure LCD from PHY
1888          * extended configuration before SW configuration
1889          */
1890         data = er32(EXTCNF_CTRL);
1891         if ((hw->mac.type < e1000_pch2lan) &&
1892             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
1893                 goto release;
1894
1895         cnf_size = er32(EXTCNF_SIZE);
1896         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1897         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1898         if (!cnf_size)
1899                 goto release;
1900
1901         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1902         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1903
1904         if (((hw->mac.type == e1000_pchlan) &&
1905              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
1906             (hw->mac.type > e1000_pchlan)) {
1907                 /* HW configures the SMBus address and LEDs when the
1908                  * OEM and LCD Write Enable bits are set in the NVM.
1909                  * When both NVM bits are cleared, SW will configure
1910                  * them instead.
1911                  */
1912                 ret_val = e1000_write_smbus_addr(hw);
1913                 if (ret_val)
1914                         goto release;
1915
1916                 data = er32(LEDCTL);
1917                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1918                                                         (u16)data);
1919                 if (ret_val)
1920                         goto release;
1921         }
1922
1923         /* Configure LCD from extended configuration region. */
1924
1925         /* cnf_base_addr is in DWORD */
1926         word_addr = (u16)(cnf_base_addr << 1);
1927
1928         for (i = 0; i < cnf_size; i++) {
1929                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
1930                 if (ret_val)
1931                         goto release;
1932
1933                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1934                                          1, &reg_addr);
1935                 if (ret_val)
1936                         goto release;
1937
1938                 /* Save off the PHY page for future writes. */
1939                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1940                         phy_page = reg_data;
1941                         continue;
1942                 }
1943
1944                 reg_addr &= PHY_REG_MASK;
1945                 reg_addr |= phy_page;
1946
1947                 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
1948                 if (ret_val)
1949                         goto release;
1950         }
1951
1952 release:
1953         hw->phy.ops.release(hw);
1954         return ret_val;
1955 }
1956
1957 /**
1958  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1959  *  @hw:   pointer to the HW structure
1960  *  @link: link up bool flag
1961  *
1962  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1963  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1964  *  If link is down, the function will restore the default K1 setting located
1965  *  in the NVM.
1966  **/
1967 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1968 {
1969         s32 ret_val = 0;
1970         u16 status_reg = 0;
1971         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1972
1973         if (hw->mac.type != e1000_pchlan)
1974                 return 0;
1975
1976         /* Wrap the whole flow with the sw flag */
1977         ret_val = hw->phy.ops.acquire(hw);
1978         if (ret_val)
1979                 return ret_val;
1980
1981         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1982         if (link) {
1983                 if (hw->phy.type == e1000_phy_82578) {
1984                         ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
1985                                                   &status_reg);
1986                         if (ret_val)
1987                                 goto release;
1988
1989                         status_reg &= (BM_CS_STATUS_LINK_UP |
1990                                        BM_CS_STATUS_RESOLVED |
1991                                        BM_CS_STATUS_SPEED_MASK);
1992
1993                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1994                                            BM_CS_STATUS_RESOLVED |
1995                                            BM_CS_STATUS_SPEED_1000))
1996                                 k1_enable = false;
1997                 }
1998
1999                 if (hw->phy.type == e1000_phy_82577) {
2000                         ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2001                         if (ret_val)
2002                                 goto release;
2003
2004                         status_reg &= (HV_M_STATUS_LINK_UP |
2005                                        HV_M_STATUS_AUTONEG_COMPLETE |
2006                                        HV_M_STATUS_SPEED_MASK);
2007
2008                         if (status_reg == (HV_M_STATUS_LINK_UP |
2009                                            HV_M_STATUS_AUTONEG_COMPLETE |
2010                                            HV_M_STATUS_SPEED_1000))
2011                                 k1_enable = false;
2012                 }
2013
2014                 /* Link stall fix for link up */
2015                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2016                 if (ret_val)
2017                         goto release;
2018
2019         } else {
2020                 /* Link stall fix for link down */
2021                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2022                 if (ret_val)
2023                         goto release;
2024         }
2025
2026         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2027
2028 release:
2029         hw->phy.ops.release(hw);
2030
2031         return ret_val;
2032 }
2033
2034 /**
2035  *  e1000_configure_k1_ich8lan - Configure K1 power state
2036  *  @hw: pointer to the HW structure
2037  *  @enable: K1 state to configure
2038  *
2039  *  Configure the K1 power state based on the provided parameter.
2040  *  Assumes semaphore already acquired.
2041  *
2042  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2043  **/
2044 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2045 {
2046         s32 ret_val;
2047         u32 ctrl_reg = 0;
2048         u32 ctrl_ext = 0;
2049         u32 reg = 0;
2050         u16 kmrn_reg = 0;
2051
2052         ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2053                                               &kmrn_reg);
2054         if (ret_val)
2055                 return ret_val;
2056
2057         if (k1_enable)
2058                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2059         else
2060                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2061
2062         ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2063                                                kmrn_reg);
2064         if (ret_val)
2065                 return ret_val;
2066
2067         usleep_range(20, 40);
2068         ctrl_ext = er32(CTRL_EXT);
2069         ctrl_reg = er32(CTRL);
2070
2071         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2072         reg |= E1000_CTRL_FRCSPD;
2073         ew32(CTRL, reg);
2074
2075         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2076         e1e_flush();
2077         usleep_range(20, 40);
2078         ew32(CTRL, ctrl_reg);
2079         ew32(CTRL_EXT, ctrl_ext);
2080         e1e_flush();
2081         usleep_range(20, 40);
2082
2083         return 0;
2084 }
2085
2086 /**
2087  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2088  *  @hw:       pointer to the HW structure
2089  *  @d0_state: boolean if entering d0 or d3 device state
2090  *
2091  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2092  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2093  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2094  **/
2095 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2096 {
2097         s32 ret_val = 0;
2098         u32 mac_reg;
2099         u16 oem_reg;
2100
2101         if (hw->mac.type < e1000_pchlan)
2102                 return ret_val;
2103
2104         ret_val = hw->phy.ops.acquire(hw);
2105         if (ret_val)
2106                 return ret_val;
2107
2108         if (hw->mac.type == e1000_pchlan) {
2109                 mac_reg = er32(EXTCNF_CTRL);
2110                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2111                         goto release;
2112         }
2113
2114         mac_reg = er32(FEXTNVM);
2115         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2116                 goto release;
2117
2118         mac_reg = er32(PHY_CTRL);
2119
2120         ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2121         if (ret_val)
2122                 goto release;
2123
2124         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2125
2126         if (d0_state) {
2127                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2128                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2129
2130                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2131                         oem_reg |= HV_OEM_BITS_LPLU;
2132         } else {
2133                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2134                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2135                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2136
2137                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2138                                E1000_PHY_CTRL_NOND0A_LPLU))
2139                         oem_reg |= HV_OEM_BITS_LPLU;
2140         }
2141
2142         /* Set Restart auto-neg to activate the bits */
2143         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2144             !hw->phy.ops.check_reset_block(hw))
2145                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2146
2147         ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2148
2149 release:
2150         hw->phy.ops.release(hw);
2151
2152         return ret_val;
2153 }
2154
2155 /**
2156  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2157  *  @hw:   pointer to the HW structure
2158  **/
2159 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2160 {
2161         s32 ret_val;
2162         u16 data;
2163
2164         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2165         if (ret_val)
2166                 return ret_val;
2167
2168         data |= HV_KMRN_MDIO_SLOW;
2169
2170         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2171
2172         return ret_val;
2173 }
2174
2175 /**
2176  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2177  *  done after every PHY reset.
2178  **/
2179 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2180 {
2181         s32 ret_val = 0;
2182         u16 phy_data;
2183
2184         if (hw->mac.type != e1000_pchlan)
2185                 return 0;
2186
2187         /* Set MDIO slow mode before any other MDIO access */
2188         if (hw->phy.type == e1000_phy_82577) {
2189                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2190                 if (ret_val)
2191                         return ret_val;
2192         }
2193
2194         if (((hw->phy.type == e1000_phy_82577) &&
2195              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2196             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2197                 /* Disable generation of early preamble */
2198                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2199                 if (ret_val)
2200                         return ret_val;
2201
2202                 /* Preamble tuning for SSC */
2203                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2204                 if (ret_val)
2205                         return ret_val;
2206         }
2207
2208         if (hw->phy.type == e1000_phy_82578) {
2209                 /* Return registers to default by doing a soft reset then
2210                  * writing 0x3140 to the control register.
2211                  */
2212                 if (hw->phy.revision < 2) {
2213                         e1000e_phy_sw_reset(hw);
2214                         ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2215                 }
2216         }
2217
2218         /* Select page 0 */
2219         ret_val = hw->phy.ops.acquire(hw);
2220         if (ret_val)
2221                 return ret_val;
2222
2223         hw->phy.addr = 1;
2224         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2225         hw->phy.ops.release(hw);
2226         if (ret_val)
2227                 return ret_val;
2228
2229         /* Configure the K1 Si workaround during phy reset assuming there is
2230          * link so that it disables K1 if link is in 1Gbps.
2231          */
2232         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2233         if (ret_val)
2234                 return ret_val;
2235
2236         /* Workaround for link disconnects on a busy hub in half duplex */
2237         ret_val = hw->phy.ops.acquire(hw);
2238         if (ret_val)
2239                 return ret_val;
2240         ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2241         if (ret_val)
2242                 goto release;
2243         ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2244         if (ret_val)
2245                 goto release;
2246
2247         /* set MSE higher to enable link to stay up when noise is high */
2248         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2249 release:
2250         hw->phy.ops.release(hw);
2251
2252         return ret_val;
2253 }
2254
2255 /**
2256  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2257  *  @hw:   pointer to the HW structure
2258  **/
2259 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2260 {
2261         u32 mac_reg;
2262         u16 i, phy_reg = 0;
2263         s32 ret_val;
2264
2265         ret_val = hw->phy.ops.acquire(hw);
2266         if (ret_val)
2267                 return;
2268         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2269         if (ret_val)
2270                 goto release;
2271
2272         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2273         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2274                 mac_reg = er32(RAL(i));
2275                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2276                                            (u16)(mac_reg & 0xFFFF));
2277                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2278                                            (u16)((mac_reg >> 16) & 0xFFFF));
2279
2280                 mac_reg = er32(RAH(i));
2281                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2282                                            (u16)(mac_reg & 0xFFFF));
2283                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2284                                            (u16)((mac_reg & E1000_RAH_AV)
2285                                                  >> 16));
2286         }
2287
2288         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2289
2290 release:
2291         hw->phy.ops.release(hw);
2292 }
2293
2294 /**
2295  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2296  *  with 82579 PHY
2297  *  @hw: pointer to the HW structure
2298  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2299  **/
2300 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2301 {
2302         s32 ret_val = 0;
2303         u16 phy_reg, data;
2304         u32 mac_reg;
2305         u16 i;
2306
2307         if (hw->mac.type < e1000_pch2lan)
2308                 return 0;
2309
2310         /* disable Rx path while enabling/disabling workaround */
2311         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2312         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
2313         if (ret_val)
2314                 return ret_val;
2315
2316         if (enable) {
2317                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2318                  * SHRAL/H) and initial CRC values to the MAC
2319                  */
2320                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2321                         u8 mac_addr[ETH_ALEN] = { 0 };
2322                         u32 addr_high, addr_low;
2323
2324                         addr_high = er32(RAH(i));
2325                         if (!(addr_high & E1000_RAH_AV))
2326                                 continue;
2327                         addr_low = er32(RAL(i));
2328                         mac_addr[0] = (addr_low & 0xFF);
2329                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2330                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2331                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2332                         mac_addr[4] = (addr_high & 0xFF);
2333                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2334
2335                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2336                 }
2337
2338                 /* Write Rx addresses to the PHY */
2339                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2340
2341                 /* Enable jumbo frame workaround in the MAC */
2342                 mac_reg = er32(FFLT_DBG);
2343                 mac_reg &= ~(1 << 14);
2344                 mac_reg |= (7 << 15);
2345                 ew32(FFLT_DBG, mac_reg);
2346
2347                 mac_reg = er32(RCTL);
2348                 mac_reg |= E1000_RCTL_SECRC;
2349                 ew32(RCTL, mac_reg);
2350
2351                 ret_val = e1000e_read_kmrn_reg(hw,
2352                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2353                                                &data);
2354                 if (ret_val)
2355                         return ret_val;
2356                 ret_val = e1000e_write_kmrn_reg(hw,
2357                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2358                                                 data | (1 << 0));
2359                 if (ret_val)
2360                         return ret_val;
2361                 ret_val = e1000e_read_kmrn_reg(hw,
2362                                                E1000_KMRNCTRLSTA_HD_CTRL,
2363                                                &data);
2364                 if (ret_val)
2365                         return ret_val;
2366                 data &= ~(0xF << 8);
2367                 data |= (0xB << 8);
2368                 ret_val = e1000e_write_kmrn_reg(hw,
2369                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2370                                                 data);
2371                 if (ret_val)
2372                         return ret_val;
2373
2374                 /* Enable jumbo frame workaround in the PHY */
2375                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2376                 data &= ~(0x7F << 5);
2377                 data |= (0x37 << 5);
2378                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2379                 if (ret_val)
2380                         return ret_val;
2381                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2382                 data &= ~(1 << 13);
2383                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2384                 if (ret_val)
2385                         return ret_val;
2386                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2387                 data &= ~(0x3FF << 2);
2388                 data |= (0x1A << 2);
2389                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2390                 if (ret_val)
2391                         return ret_val;
2392                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2393                 if (ret_val)
2394                         return ret_val;
2395                 e1e_rphy(hw, HV_PM_CTRL, &data);
2396                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
2397                 if (ret_val)
2398                         return ret_val;
2399         } else {
2400                 /* Write MAC register values back to h/w defaults */
2401                 mac_reg = er32(FFLT_DBG);
2402                 mac_reg &= ~(0xF << 14);
2403                 ew32(FFLT_DBG, mac_reg);
2404
2405                 mac_reg = er32(RCTL);
2406                 mac_reg &= ~E1000_RCTL_SECRC;
2407                 ew32(RCTL, mac_reg);
2408
2409                 ret_val = e1000e_read_kmrn_reg(hw,
2410                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2411                                                &data);
2412                 if (ret_val)
2413                         return ret_val;
2414                 ret_val = e1000e_write_kmrn_reg(hw,
2415                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2416                                                 data & ~(1 << 0));
2417                 if (ret_val)
2418                         return ret_val;
2419                 ret_val = e1000e_read_kmrn_reg(hw,
2420                                                E1000_KMRNCTRLSTA_HD_CTRL,
2421                                                &data);
2422                 if (ret_val)
2423                         return ret_val;
2424                 data &= ~(0xF << 8);
2425                 data |= (0xB << 8);
2426                 ret_val = e1000e_write_kmrn_reg(hw,
2427                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2428                                                 data);
2429                 if (ret_val)
2430                         return ret_val;
2431
2432                 /* Write PHY register values back to h/w defaults */
2433                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2434                 data &= ~(0x7F << 5);
2435                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2436                 if (ret_val)
2437                         return ret_val;
2438                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2439                 data |= (1 << 13);
2440                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2441                 if (ret_val)
2442                         return ret_val;
2443                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2444                 data &= ~(0x3FF << 2);
2445                 data |= (0x8 << 2);
2446                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2447                 if (ret_val)
2448                         return ret_val;
2449                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2450                 if (ret_val)
2451                         return ret_val;
2452                 e1e_rphy(hw, HV_PM_CTRL, &data);
2453                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
2454                 if (ret_val)
2455                         return ret_val;
2456         }
2457
2458         /* re-enable Rx path after enabling/disabling workaround */
2459         return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
2460 }
2461
2462 /**
2463  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2464  *  done after every PHY reset.
2465  **/
2466 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2467 {
2468         s32 ret_val = 0;
2469
2470         if (hw->mac.type != e1000_pch2lan)
2471                 return 0;
2472
2473         /* Set MDIO slow mode before any other MDIO access */
2474         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2475         if (ret_val)
2476                 return ret_val;
2477
2478         ret_val = hw->phy.ops.acquire(hw);
2479         if (ret_val)
2480                 return ret_val;
2481         /* set MSE higher to enable link to stay up when noise is high */
2482         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2483         if (ret_val)
2484                 goto release;
2485         /* drop link after 5 times MSE threshold was reached */
2486         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2487 release:
2488         hw->phy.ops.release(hw);
2489
2490         return ret_val;
2491 }
2492
2493 /**
2494  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2495  *  @hw:   pointer to the HW structure
2496  *
2497  *  Workaround to set the K1 beacon duration for 82579 parts
2498  **/
2499 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2500 {
2501         s32 ret_val = 0;
2502         u16 status_reg = 0;
2503         u32 mac_reg;
2504         u16 phy_reg;
2505
2506         if (hw->mac.type != e1000_pch2lan)
2507                 return 0;
2508
2509         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
2510         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2511         if (ret_val)
2512                 return ret_val;
2513
2514         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2515             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2516                 mac_reg = er32(FEXTNVM4);
2517                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2518
2519                 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
2520                 if (ret_val)
2521                         return ret_val;
2522
2523                 if (status_reg & HV_M_STATUS_SPEED_1000) {
2524                         u16 pm_phy_reg;
2525
2526                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
2527                         phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2528                         /* LV 1G Packet drop issue wa  */
2529                         ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2530                         if (ret_val)
2531                                 return ret_val;
2532                         pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
2533                         ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2534                         if (ret_val)
2535                                 return ret_val;
2536                 } else {
2537                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2538                         phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2539                 }
2540                 ew32(FEXTNVM4, mac_reg);
2541                 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
2542         }
2543
2544         return ret_val;
2545 }
2546
2547 /**
2548  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2549  *  @hw:   pointer to the HW structure
2550  *  @gate: boolean set to true to gate, false to ungate
2551  *
2552  *  Gate/ungate the automatic PHY configuration via hardware; perform
2553  *  the configuration via software instead.
2554  **/
2555 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2556 {
2557         u32 extcnf_ctrl;
2558
2559         if (hw->mac.type < e1000_pch2lan)
2560                 return;
2561
2562         extcnf_ctrl = er32(EXTCNF_CTRL);
2563
2564         if (gate)
2565                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2566         else
2567                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2568
2569         ew32(EXTCNF_CTRL, extcnf_ctrl);
2570 }
2571
2572 /**
2573  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2574  *  @hw: pointer to the HW structure
2575  *
2576  *  Check the appropriate indication the MAC has finished configuring the
2577  *  PHY after a software reset.
2578  **/
2579 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2580 {
2581         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2582
2583         /* Wait for basic configuration completes before proceeding */
2584         do {
2585                 data = er32(STATUS);
2586                 data &= E1000_STATUS_LAN_INIT_DONE;
2587                 usleep_range(100, 200);
2588         } while ((!data) && --loop);
2589
2590         /* If basic configuration is incomplete before the above loop
2591          * count reaches 0, loading the configuration from NVM will
2592          * leave the PHY in a bad state possibly resulting in no link.
2593          */
2594         if (loop == 0)
2595                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2596
2597         /* Clear the Init Done bit for the next init event */
2598         data = er32(STATUS);
2599         data &= ~E1000_STATUS_LAN_INIT_DONE;
2600         ew32(STATUS, data);
2601 }
2602
2603 /**
2604  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2605  *  @hw: pointer to the HW structure
2606  **/
2607 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2608 {
2609         s32 ret_val = 0;
2610         u16 reg;
2611
2612         if (hw->phy.ops.check_reset_block(hw))
2613                 return 0;
2614
2615         /* Allow time for h/w to get to quiescent state after reset */
2616         usleep_range(10000, 20000);
2617
2618         /* Perform any necessary post-reset workarounds */
2619         switch (hw->mac.type) {
2620         case e1000_pchlan:
2621                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2622                 if (ret_val)
2623                         return ret_val;
2624                 break;
2625         case e1000_pch2lan:
2626                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2627                 if (ret_val)
2628                         return ret_val;
2629                 break;
2630         default:
2631                 break;
2632         }
2633
2634         /* Clear the host wakeup bit after lcd reset */
2635         if (hw->mac.type >= e1000_pchlan) {
2636                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2637                 reg &= ~BM_WUC_HOST_WU_BIT;
2638                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2639         }
2640
2641         /* Configure the LCD with the extended configuration region in NVM */
2642         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2643         if (ret_val)
2644                 return ret_val;
2645
2646         /* Configure the LCD with the OEM bits in NVM */
2647         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2648
2649         if (hw->mac.type == e1000_pch2lan) {
2650                 /* Ungate automatic PHY configuration on non-managed 82579 */
2651                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2652                         usleep_range(10000, 20000);
2653                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2654                 }
2655
2656                 /* Set EEE LPI Update Timer to 200usec */
2657                 ret_val = hw->phy.ops.acquire(hw);
2658                 if (ret_val)
2659                         return ret_val;
2660                 ret_val = e1000_write_emi_reg_locked(hw,
2661                                                      I82579_LPI_UPDATE_TIMER,
2662                                                      0x1387);
2663                 hw->phy.ops.release(hw);
2664         }
2665
2666         return ret_val;
2667 }
2668
2669 /**
2670  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2671  *  @hw: pointer to the HW structure
2672  *
2673  *  Resets the PHY
2674  *  This is a function pointer entry point called by drivers
2675  *  or other shared routines.
2676  **/
2677 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2678 {
2679         s32 ret_val = 0;
2680
2681         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2682         if ((hw->mac.type == e1000_pch2lan) &&
2683             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2684                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2685
2686         ret_val = e1000e_phy_hw_reset_generic(hw);
2687         if (ret_val)
2688                 return ret_val;
2689
2690         return e1000_post_phy_reset_ich8lan(hw);
2691 }
2692
2693 /**
2694  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2695  *  @hw: pointer to the HW structure
2696  *  @active: true to enable LPLU, false to disable
2697  *
2698  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2699  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2700  *  the phy speed. This function will manually set the LPLU bit and restart
2701  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2702  *  since it configures the same bit.
2703  **/
2704 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2705 {
2706         s32 ret_val;
2707         u16 oem_reg;
2708
2709         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2710         if (ret_val)
2711                 return ret_val;
2712
2713         if (active)
2714                 oem_reg |= HV_OEM_BITS_LPLU;
2715         else
2716                 oem_reg &= ~HV_OEM_BITS_LPLU;
2717
2718         if (!hw->phy.ops.check_reset_block(hw))
2719                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2720
2721         return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2722 }
2723
2724 /**
2725  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2726  *  @hw: pointer to the HW structure
2727  *  @active: true to enable LPLU, false to disable
2728  *
2729  *  Sets the LPLU D0 state according to the active flag.  When
2730  *  activating LPLU this function also disables smart speed
2731  *  and vice versa.  LPLU will not be activated unless the
2732  *  device autonegotiation advertisement meets standards of
2733  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2734  *  This is a function pointer entry point only called by
2735  *  PHY setup routines.
2736  **/
2737 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2738 {
2739         struct e1000_phy_info *phy = &hw->phy;
2740         u32 phy_ctrl;
2741         s32 ret_val = 0;
2742         u16 data;
2743
2744         if (phy->type == e1000_phy_ife)
2745                 return 0;
2746
2747         phy_ctrl = er32(PHY_CTRL);
2748
2749         if (active) {
2750                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2751                 ew32(PHY_CTRL, phy_ctrl);
2752
2753                 if (phy->type != e1000_phy_igp_3)
2754                         return 0;
2755
2756                 /* Call gig speed drop workaround on LPLU before accessing
2757                  * any PHY registers
2758                  */
2759                 if (hw->mac.type == e1000_ich8lan)
2760                         e1000e_gig_downshift_workaround_ich8lan(hw);
2761
2762                 /* When LPLU is enabled, we should disable SmartSpeed */
2763                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2764                 if (ret_val)
2765                         return ret_val;
2766                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2767                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2768                 if (ret_val)
2769                         return ret_val;
2770         } else {
2771                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2772                 ew32(PHY_CTRL, phy_ctrl);
2773
2774                 if (phy->type != e1000_phy_igp_3)
2775                         return 0;
2776
2777                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2778                  * during Dx states where the power conservation is most
2779                  * important.  During driver activity we should enable
2780                  * SmartSpeed, so performance is maintained.
2781                  */
2782                 if (phy->smart_speed == e1000_smart_speed_on) {
2783                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2784                                            &data);
2785                         if (ret_val)
2786                                 return ret_val;
2787
2788                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2789                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2790                                            data);
2791                         if (ret_val)
2792                                 return ret_val;
2793                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2794                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2795                                            &data);
2796                         if (ret_val)
2797                                 return ret_val;
2798
2799                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2800                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2801                                            data);
2802                         if (ret_val)
2803                                 return ret_val;
2804                 }
2805         }
2806
2807         return 0;
2808 }
2809
2810 /**
2811  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2812  *  @hw: pointer to the HW structure
2813  *  @active: true to enable LPLU, false to disable
2814  *
2815  *  Sets the LPLU D3 state according to the active flag.  When
2816  *  activating LPLU this function also disables smart speed
2817  *  and vice versa.  LPLU will not be activated unless the
2818  *  device autonegotiation advertisement meets standards of
2819  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2820  *  This is a function pointer entry point only called by
2821  *  PHY setup routines.
2822  **/
2823 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2824 {
2825         struct e1000_phy_info *phy = &hw->phy;
2826         u32 phy_ctrl;
2827         s32 ret_val = 0;
2828         u16 data;
2829
2830         phy_ctrl = er32(PHY_CTRL);
2831
2832         if (!active) {
2833                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2834                 ew32(PHY_CTRL, phy_ctrl);
2835
2836                 if (phy->type != e1000_phy_igp_3)
2837                         return 0;
2838
2839                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2840                  * during Dx states where the power conservation is most
2841                  * important.  During driver activity we should enable
2842                  * SmartSpeed, so performance is maintained.
2843                  */
2844                 if (phy->smart_speed == e1000_smart_speed_on) {
2845                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2846                                            &data);
2847                         if (ret_val)
2848                                 return ret_val;
2849
2850                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2851                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2852                                            data);
2853                         if (ret_val)
2854                                 return ret_val;
2855                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2856                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2857                                            &data);
2858                         if (ret_val)
2859                                 return ret_val;
2860
2861                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2862                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2863                                            data);
2864                         if (ret_val)
2865                                 return ret_val;
2866                 }
2867         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2868                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2869                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2870                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2871                 ew32(PHY_CTRL, phy_ctrl);
2872
2873                 if (phy->type != e1000_phy_igp_3)
2874                         return 0;
2875
2876                 /* Call gig speed drop workaround on LPLU before accessing
2877                  * any PHY registers
2878                  */
2879                 if (hw->mac.type == e1000_ich8lan)
2880                         e1000e_gig_downshift_workaround_ich8lan(hw);
2881
2882                 /* When LPLU is enabled, we should disable SmartSpeed */
2883                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2884                 if (ret_val)
2885                         return ret_val;
2886
2887                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2888                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2889         }
2890
2891         return ret_val;
2892 }
2893
2894 /**
2895  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2896  *  @hw: pointer to the HW structure
2897  *  @bank:  pointer to the variable that returns the active bank
2898  *
2899  *  Reads signature byte from the NVM using the flash access registers.
2900  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2901  **/
2902 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2903 {
2904         u32 eecd;
2905         struct e1000_nvm_info *nvm = &hw->nvm;
2906         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2907         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2908         u8 sig_byte = 0;
2909         s32 ret_val;
2910
2911         switch (hw->mac.type) {
2912         case e1000_ich8lan:
2913         case e1000_ich9lan:
2914                 eecd = er32(EECD);
2915                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2916                     E1000_EECD_SEC1VAL_VALID_MASK) {
2917                         if (eecd & E1000_EECD_SEC1VAL)
2918                                 *bank = 1;
2919                         else
2920                                 *bank = 0;
2921
2922                         return 0;
2923                 }
2924                 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2925                 /* fall-thru */
2926         default:
2927                 /* set bank to 0 in case flash read fails */
2928                 *bank = 0;
2929
2930                 /* Check bank 0 */
2931                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2932                                                         &sig_byte);
2933                 if (ret_val)
2934                         return ret_val;
2935                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2936                     E1000_ICH_NVM_SIG_VALUE) {
2937                         *bank = 0;
2938                         return 0;
2939                 }
2940
2941                 /* Check bank 1 */
2942                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2943                                                         bank1_offset,
2944                                                         &sig_byte);
2945                 if (ret_val)
2946                         return ret_val;
2947                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2948                     E1000_ICH_NVM_SIG_VALUE) {
2949                         *bank = 1;
2950                         return 0;
2951                 }
2952
2953                 e_dbg("ERROR: No valid NVM bank present\n");
2954                 return -E1000_ERR_NVM;
2955         }
2956 }
2957
2958 /**
2959  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2960  *  @hw: pointer to the HW structure
2961  *  @offset: The offset (in bytes) of the word(s) to read.
2962  *  @words: Size of data to read in words
2963  *  @data: Pointer to the word(s) to read at offset.
2964  *
2965  *  Reads a word(s) from the NVM using the flash access registers.
2966  **/
2967 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2968                                   u16 *data)
2969 {
2970         struct e1000_nvm_info *nvm = &hw->nvm;
2971         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2972         u32 act_offset;
2973         s32 ret_val = 0;
2974         u32 bank = 0;
2975         u16 i, word;
2976
2977         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2978             (words == 0)) {
2979                 e_dbg("nvm parameter(s) out of bounds\n");
2980                 ret_val = -E1000_ERR_NVM;
2981                 goto out;
2982         }
2983
2984         nvm->ops.acquire(hw);
2985
2986         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2987         if (ret_val) {
2988                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2989                 bank = 0;
2990         }
2991
2992         act_offset = (bank) ? nvm->flash_bank_size : 0;
2993         act_offset += offset;
2994
2995         ret_val = 0;
2996         for (i = 0; i < words; i++) {
2997                 if (dev_spec->shadow_ram[offset + i].modified) {
2998                         data[i] = dev_spec->shadow_ram[offset + i].value;
2999                 } else {
3000                         ret_val = e1000_read_flash_word_ich8lan(hw,
3001                                                                 act_offset + i,
3002                                                                 &word);
3003                         if (ret_val)
3004                                 break;
3005                         data[i] = word;
3006                 }
3007         }
3008
3009         nvm->ops.release(hw);
3010
3011 out:
3012         if (ret_val)
3013                 e_dbg("NVM read error: %d\n", ret_val);
3014
3015         return ret_val;
3016 }
3017
3018 /**
3019  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3020  *  @hw: pointer to the HW structure
3021  *
3022  *  This function does initial flash setup so that a new read/write/erase cycle
3023  *  can be started.
3024  **/
3025 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3026 {
3027         union ich8_hws_flash_status hsfsts;
3028         s32 ret_val = -E1000_ERR_NVM;
3029
3030         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3031
3032         /* Check if the flash descriptor is valid */
3033         if (!hsfsts.hsf_status.fldesvalid) {
3034                 e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
3035                 return -E1000_ERR_NVM;
3036         }
3037
3038         /* Clear FCERR and DAEL in hw status by writing 1 */
3039         hsfsts.hsf_status.flcerr = 1;
3040         hsfsts.hsf_status.dael = 1;
3041
3042         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3043
3044         /* Either we should have a hardware SPI cycle in progress
3045          * bit to check against, in order to start a new cycle or
3046          * FDONE bit should be changed in the hardware so that it
3047          * is 1 after hardware reset, which can then be used as an
3048          * indication whether a cycle is in progress or has been
3049          * completed.
3050          */
3051
3052         if (!hsfsts.hsf_status.flcinprog) {
3053                 /* There is no cycle running at present,
3054                  * so we can start a cycle.
3055                  * Begin by setting Flash Cycle Done.
3056                  */
3057                 hsfsts.hsf_status.flcdone = 1;
3058                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3059                 ret_val = 0;
3060         } else {
3061                 s32 i;
3062
3063                 /* Otherwise poll for sometime so the current
3064                  * cycle has a chance to end before giving up.
3065                  */
3066                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3067                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3068                         if (!hsfsts.hsf_status.flcinprog) {
3069                                 ret_val = 0;
3070                                 break;
3071                         }
3072                         udelay(1);
3073                 }
3074                 if (!ret_val) {
3075                         /* Successful in waiting for previous cycle to timeout,
3076                          * now set the Flash Cycle Done.
3077                          */
3078                         hsfsts.hsf_status.flcdone = 1;
3079                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3080                 } else {
3081                         e_dbg("Flash controller busy, cannot get access\n");
3082                 }
3083         }
3084
3085         return ret_val;
3086 }
3087
3088 /**
3089  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3090  *  @hw: pointer to the HW structure
3091  *  @timeout: maximum time to wait for completion
3092  *
3093  *  This function starts a flash cycle and waits for its completion.
3094  **/
3095 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3096 {
3097         union ich8_hws_flash_ctrl hsflctl;
3098         union ich8_hws_flash_status hsfsts;
3099         u32 i = 0;
3100
3101         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3102         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3103         hsflctl.hsf_ctrl.flcgo = 1;
3104         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3105
3106         /* wait till FDONE bit is set to 1 */
3107         do {
3108                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3109                 if (hsfsts.hsf_status.flcdone)
3110                         break;
3111                 udelay(1);
3112         } while (i++ < timeout);
3113
3114         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3115                 return 0;
3116
3117         return -E1000_ERR_NVM;
3118 }
3119
3120 /**
3121  *  e1000_read_flash_word_ich8lan - Read word from flash
3122  *  @hw: pointer to the HW structure
3123  *  @offset: offset to data location
3124  *  @data: pointer to the location for storing the data
3125  *
3126  *  Reads the flash word at offset into data.  Offset is converted
3127  *  to bytes before read.
3128  **/
3129 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3130                                          u16 *data)
3131 {
3132         /* Must convert offset into bytes. */
3133         offset <<= 1;
3134
3135         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3136 }
3137
3138 /**
3139  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3140  *  @hw: pointer to the HW structure
3141  *  @offset: The offset of the byte to read.
3142  *  @data: Pointer to a byte to store the value read.
3143  *
3144  *  Reads a single byte from the NVM using the flash access registers.
3145  **/
3146 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3147                                          u8 *data)
3148 {
3149         s32 ret_val;
3150         u16 word = 0;
3151
3152         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3153         if (ret_val)
3154                 return ret_val;
3155
3156         *data = (u8)word;
3157
3158         return 0;
3159 }
3160
3161 /**
3162  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3163  *  @hw: pointer to the HW structure
3164  *  @offset: The offset (in bytes) of the byte or word to read.
3165  *  @size: Size of data to read, 1=byte 2=word
3166  *  @data: Pointer to the word to store the value read.
3167  *
3168  *  Reads a byte or word from the NVM using the flash access registers.
3169  **/
3170 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3171                                          u8 size, u16 *data)
3172 {
3173         union ich8_hws_flash_status hsfsts;
3174         union ich8_hws_flash_ctrl hsflctl;
3175         u32 flash_linear_addr;
3176         u32 flash_data = 0;
3177         s32 ret_val = -E1000_ERR_NVM;
3178         u8 count = 0;
3179
3180         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3181                 return -E1000_ERR_NVM;
3182
3183         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3184                              hw->nvm.flash_base_addr);
3185
3186         do {
3187                 udelay(1);
3188                 /* Steps */
3189                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3190                 if (ret_val)
3191                         break;
3192
3193                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3194                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3195                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3196                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3197                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3198
3199                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3200
3201                 ret_val =
3202                     e1000_flash_cycle_ich8lan(hw,
3203                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
3204
3205                 /* Check if FCERR is set to 1, if set to 1, clear it
3206                  * and try the whole sequence a few more times, else
3207                  * read in (shift in) the Flash Data0, the order is
3208                  * least significant byte first msb to lsb
3209                  */
3210                 if (!ret_val) {
3211                         flash_data = er32flash(ICH_FLASH_FDATA0);
3212                         if (size == 1)
3213                                 *data = (u8)(flash_data & 0x000000FF);
3214                         else if (size == 2)
3215                                 *data = (u16)(flash_data & 0x0000FFFF);
3216                         break;
3217                 } else {
3218                         /* If we've gotten here, then things are probably
3219                          * completely hosed, but if the error condition is
3220                          * detected, it won't hurt to give it another try...
3221                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3222                          */
3223                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3224                         if (hsfsts.hsf_status.flcerr) {
3225                                 /* Repeat for some time before giving up. */
3226                                 continue;
3227                         } else if (!hsfsts.hsf_status.flcdone) {
3228                                 e_dbg("Timeout error - flash cycle did not complete.\n");
3229                                 break;
3230                         }
3231                 }
3232         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3233
3234         return ret_val;
3235 }
3236
3237 /**
3238  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3239  *  @hw: pointer to the HW structure
3240  *  @offset: The offset (in bytes) of the word(s) to write.
3241  *  @words: Size of data to write in words
3242  *  @data: Pointer to the word(s) to write at offset.
3243  *
3244  *  Writes a byte or word to the NVM using the flash access registers.
3245  **/
3246 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3247                                    u16 *data)
3248 {
3249         struct e1000_nvm_info *nvm = &hw->nvm;
3250         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3251         u16 i;
3252
3253         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3254             (words == 0)) {
3255                 e_dbg("nvm parameter(s) out of bounds\n");
3256                 return -E1000_ERR_NVM;
3257         }
3258
3259         nvm->ops.acquire(hw);
3260
3261         for (i = 0; i < words; i++) {
3262                 dev_spec->shadow_ram[offset + i].modified = true;
3263                 dev_spec->shadow_ram[offset + i].value = data[i];
3264         }
3265
3266         nvm->ops.release(hw);
3267
3268         return 0;
3269 }
3270
3271 /**
3272  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3273  *  @hw: pointer to the HW structure
3274  *
3275  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3276  *  which writes the checksum to the shadow ram.  The changes in the shadow
3277  *  ram are then committed to the EEPROM by processing each bank at a time
3278  *  checking for the modified bit and writing only the pending changes.
3279  *  After a successful commit, the shadow ram is cleared and is ready for
3280  *  future writes.
3281  **/
3282 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3283 {
3284         struct e1000_nvm_info *nvm = &hw->nvm;
3285         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3286         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3287         s32 ret_val;
3288         u16 data;
3289
3290         ret_val = e1000e_update_nvm_checksum_generic(hw);
3291         if (ret_val)
3292                 goto out;
3293
3294         if (nvm->type != e1000_nvm_flash_sw)
3295                 goto out;
3296
3297         nvm->ops.acquire(hw);
3298
3299         /* We're writing to the opposite bank so if we're on bank 1,
3300          * write to bank 0 etc.  We also need to erase the segment that
3301          * is going to be written
3302          */
3303         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3304         if (ret_val) {
3305                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3306                 bank = 0;
3307         }
3308
3309         if (bank == 0) {
3310                 new_bank_offset = nvm->flash_bank_size;
3311                 old_bank_offset = 0;
3312                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3313                 if (ret_val)
3314                         goto release;
3315         } else {
3316                 old_bank_offset = nvm->flash_bank_size;
3317                 new_bank_offset = 0;
3318                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3319                 if (ret_val)
3320                         goto release;
3321         }
3322
3323         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3324                 /* Determine whether to write the value stored
3325                  * in the other NVM bank or a modified value stored
3326                  * in the shadow RAM
3327                  */
3328                 if (dev_spec->shadow_ram[i].modified) {
3329                         data = dev_spec->shadow_ram[i].value;
3330                 } else {
3331                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
3332                                                                 old_bank_offset,
3333                                                                 &data);
3334                         if (ret_val)
3335                                 break;
3336                 }
3337
3338                 /* If the word is 0x13, then make sure the signature bits
3339                  * (15:14) are 11b until the commit has completed.
3340                  * This will allow us to write 10b which indicates the
3341                  * signature is valid.  We want to do this after the write
3342                  * has completed so that we don't mark the segment valid
3343                  * while the write is still in progress
3344                  */
3345                 if (i == E1000_ICH_NVM_SIG_WORD)
3346                         data |= E1000_ICH_NVM_SIG_MASK;
3347
3348                 /* Convert offset to bytes. */
3349                 act_offset = (i + new_bank_offset) << 1;
3350
3351                 usleep_range(100, 200);
3352                 /* Write the bytes to the new bank. */
3353                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3354                                                                act_offset,
3355                                                                (u8)data);
3356                 if (ret_val)
3357                         break;
3358
3359                 usleep_range(100, 200);
3360                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3361                                                                act_offset + 1,
3362                                                                (u8)(data >> 8));
3363                 if (ret_val)
3364                         break;
3365         }
3366
3367         /* Don't bother writing the segment valid bits if sector
3368          * programming failed.
3369          */
3370         if (ret_val) {
3371                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3372                 e_dbg("Flash commit failed.\n");
3373                 goto release;
3374         }
3375
3376         /* Finally validate the new segment by setting bit 15:14
3377          * to 10b in word 0x13 , this can be done without an
3378          * erase as well since these bits are 11 to start with
3379          * and we need to change bit 14 to 0b
3380          */
3381         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3382         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3383         if (ret_val)
3384                 goto release;
3385
3386         data &= 0xBFFF;
3387         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3388                                                        act_offset * 2 + 1,
3389                                                        (u8)(data >> 8));
3390         if (ret_val)
3391                 goto release;
3392
3393         /* And invalidate the previously valid segment by setting
3394          * its signature word (0x13) high_byte to 0b. This can be
3395          * done without an erase because flash erase sets all bits
3396          * to 1's. We can write 1's to 0's without an erase
3397          */
3398         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3399         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3400         if (ret_val)
3401                 goto release;
3402
3403         /* Great!  Everything worked, we can now clear the cached entries. */
3404         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3405                 dev_spec->shadow_ram[i].modified = false;
3406                 dev_spec->shadow_ram[i].value = 0xFFFF;
3407         }
3408
3409 release:
3410         nvm->ops.release(hw);
3411
3412         /* Reload the EEPROM, or else modifications will not appear
3413          * until after the next adapter reset.
3414          */
3415         if (!ret_val) {
3416                 nvm->ops.reload(hw);
3417                 usleep_range(10000, 20000);
3418         }
3419
3420 out:
3421         if (ret_val)
3422                 e_dbg("NVM update error: %d\n", ret_val);
3423
3424         return ret_val;
3425 }
3426
3427 /**
3428  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3429  *  @hw: pointer to the HW structure
3430  *
3431  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3432  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
3433  *  calculated, in which case we need to calculate the checksum and set bit 6.
3434  **/
3435 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3436 {
3437         s32 ret_val;
3438         u16 data;
3439         u16 word;
3440         u16 valid_csum_mask;
3441
3442         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
3443          * the checksum needs to be fixed.  This bit is an indication that
3444          * the NVM was prepared by OEM software and did not calculate
3445          * the checksum...a likely scenario.
3446          */
3447         switch (hw->mac.type) {
3448         case e1000_pch_lpt:
3449                 word = NVM_COMPAT;
3450                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3451                 break;
3452         default:
3453                 word = NVM_FUTURE_INIT_WORD1;
3454                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3455                 break;
3456         }
3457
3458         ret_val = e1000_read_nvm(hw, word, 1, &data);
3459         if (ret_val)
3460                 return ret_val;
3461
3462         if (!(data & valid_csum_mask)) {
3463                 data |= valid_csum_mask;
3464                 ret_val = e1000_write_nvm(hw, word, 1, &data);
3465                 if (ret_val)
3466                         return ret_val;
3467                 ret_val = e1000e_update_nvm_checksum(hw);
3468                 if (ret_val)
3469                         return ret_val;
3470         }
3471
3472         return e1000e_validate_nvm_checksum_generic(hw);
3473 }
3474
3475 /**
3476  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
3477  *  @hw: pointer to the HW structure
3478  *
3479  *  To prevent malicious write/erase of the NVM, set it to be read-only
3480  *  so that the hardware ignores all write/erase cycles of the NVM via
3481  *  the flash control registers.  The shadow-ram copy of the NVM will
3482  *  still be updated, however any updates to this copy will not stick
3483  *  across driver reloads.
3484  **/
3485 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
3486 {
3487         struct e1000_nvm_info *nvm = &hw->nvm;
3488         union ich8_flash_protected_range pr0;
3489         union ich8_hws_flash_status hsfsts;
3490         u32 gfpreg;
3491
3492         nvm->ops.acquire(hw);
3493
3494         gfpreg = er32flash(ICH_FLASH_GFPREG);
3495
3496         /* Write-protect GbE Sector of NVM */
3497         pr0.regval = er32flash(ICH_FLASH_PR0);
3498         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
3499         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
3500         pr0.range.wpe = true;
3501         ew32flash(ICH_FLASH_PR0, pr0.regval);
3502
3503         /* Lock down a subset of GbE Flash Control Registers, e.g.
3504          * PR0 to prevent the write-protection from being lifted.
3505          * Once FLOCKDN is set, the registers protected by it cannot
3506          * be written until FLOCKDN is cleared by a hardware reset.
3507          */
3508         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3509         hsfsts.hsf_status.flockdn = true;
3510         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3511
3512         nvm->ops.release(hw);
3513 }
3514
3515 /**
3516  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3517  *  @hw: pointer to the HW structure
3518  *  @offset: The offset (in bytes) of the byte/word to read.
3519  *  @size: Size of data to read, 1=byte 2=word
3520  *  @data: The byte(s) to write to the NVM.
3521  *
3522  *  Writes one/two bytes to the NVM using the flash access registers.
3523  **/
3524 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3525                                           u8 size, u16 data)
3526 {
3527         union ich8_hws_flash_status hsfsts;
3528         union ich8_hws_flash_ctrl hsflctl;
3529         u32 flash_linear_addr;
3530         u32 flash_data = 0;
3531         s32 ret_val;
3532         u8 count = 0;
3533
3534         if (size < 1 || size > 2 || data > size * 0xff ||
3535             offset > ICH_FLASH_LINEAR_ADDR_MASK)
3536                 return -E1000_ERR_NVM;
3537
3538         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3539                              hw->nvm.flash_base_addr);
3540
3541         do {
3542                 udelay(1);
3543                 /* Steps */
3544                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3545                 if (ret_val)
3546                         break;
3547
3548                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3549                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3550                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3551                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3552                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3553
3554                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3555
3556                 if (size == 1)
3557                         flash_data = (u32)data & 0x00FF;
3558                 else
3559                         flash_data = (u32)data;
3560
3561                 ew32flash(ICH_FLASH_FDATA0, flash_data);
3562
3563                 /* check if FCERR is set to 1 , if set to 1, clear it
3564                  * and try the whole sequence a few more times else done
3565                  */
3566                 ret_val =
3567                     e1000_flash_cycle_ich8lan(hw,
3568                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3569                 if (!ret_val)
3570                         break;
3571
3572                 /* If we're here, then things are most likely
3573                  * completely hosed, but if the error condition
3574                  * is detected, it won't hurt to give it another
3575                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3576                  */
3577                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3578                 if (hsfsts.hsf_status.flcerr)
3579                         /* Repeat for some time before giving up. */
3580                         continue;
3581                 if (!hsfsts.hsf_status.flcdone) {
3582                         e_dbg("Timeout error - flash cycle did not complete.\n");
3583                         break;
3584                 }
3585         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3586
3587         return ret_val;
3588 }
3589
3590 /**
3591  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3592  *  @hw: pointer to the HW structure
3593  *  @offset: The index of the byte to read.
3594  *  @data: The byte to write to the NVM.
3595  *
3596  *  Writes a single byte to the NVM using the flash access registers.
3597  **/
3598 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3599                                           u8 data)
3600 {
3601         u16 word = (u16)data;
3602
3603         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3604 }
3605
3606 /**
3607  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3608  *  @hw: pointer to the HW structure
3609  *  @offset: The offset of the byte to write.
3610  *  @byte: The byte to write to the NVM.
3611  *
3612  *  Writes a single byte to the NVM using the flash access registers.
3613  *  Goes through a retry algorithm before giving up.
3614  **/
3615 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3616                                                 u32 offset, u8 byte)
3617 {
3618         s32 ret_val;
3619         u16 program_retries;
3620
3621         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3622         if (!ret_val)
3623                 return ret_val;
3624
3625         for (program_retries = 0; program_retries < 100; program_retries++) {
3626                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
3627                 usleep_range(100, 200);
3628                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3629                 if (!ret_val)
3630                         break;
3631         }
3632         if (program_retries == 100)
3633                 return -E1000_ERR_NVM;
3634
3635         return 0;
3636 }
3637
3638 /**
3639  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3640  *  @hw: pointer to the HW structure
3641  *  @bank: 0 for first bank, 1 for second bank, etc.
3642  *
3643  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3644  *  bank N is 4096 * N + flash_reg_addr.
3645  **/
3646 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3647 {
3648         struct e1000_nvm_info *nvm = &hw->nvm;
3649         union ich8_hws_flash_status hsfsts;
3650         union ich8_hws_flash_ctrl hsflctl;
3651         u32 flash_linear_addr;
3652         /* bank size is in 16bit words - adjust to bytes */
3653         u32 flash_bank_size = nvm->flash_bank_size * 2;
3654         s32 ret_val;
3655         s32 count = 0;
3656         s32 j, iteration, sector_size;
3657
3658         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3659
3660         /* Determine HW Sector size: Read BERASE bits of hw flash status
3661          * register
3662          * 00: The Hw sector is 256 bytes, hence we need to erase 16
3663          *     consecutive sectors.  The start index for the nth Hw sector
3664          *     can be calculated as = bank * 4096 + n * 256
3665          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3666          *     The start index for the nth Hw sector can be calculated
3667          *     as = bank * 4096
3668          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3669          *     (ich9 only, otherwise error condition)
3670          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3671          */
3672         switch (hsfsts.hsf_status.berasesz) {
3673         case 0:
3674                 /* Hw sector size 256 */
3675                 sector_size = ICH_FLASH_SEG_SIZE_256;
3676                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3677                 break;
3678         case 1:
3679                 sector_size = ICH_FLASH_SEG_SIZE_4K;
3680                 iteration = 1;
3681                 break;
3682         case 2:
3683                 sector_size = ICH_FLASH_SEG_SIZE_8K;
3684                 iteration = 1;
3685                 break;
3686         case 3:
3687                 sector_size = ICH_FLASH_SEG_SIZE_64K;
3688                 iteration = 1;
3689                 break;
3690         default:
3691                 return -E1000_ERR_NVM;
3692         }
3693
3694         /* Start with the base address, then add the sector offset. */
3695         flash_linear_addr = hw->nvm.flash_base_addr;
3696         flash_linear_addr += (bank) ? flash_bank_size : 0;
3697
3698         for (j = 0; j < iteration; j++) {
3699                 do {
3700                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3701
3702                         /* Steps */
3703                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
3704                         if (ret_val)
3705                                 return ret_val;
3706
3707                         /* Write a value 11 (block Erase) in Flash
3708                          * Cycle field in hw flash control
3709                          */
3710                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3711                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3712                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3713
3714                         /* Write the last 24 bits of an index within the
3715                          * block into Flash Linear address field in Flash
3716                          * Address.
3717                          */
3718                         flash_linear_addr += (j * sector_size);
3719                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3720
3721                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
3722                         if (!ret_val)
3723                                 break;
3724
3725                         /* Check if FCERR is set to 1.  If 1,
3726                          * clear it and try the whole sequence
3727                          * a few more times else Done
3728                          */
3729                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3730                         if (hsfsts.hsf_status.flcerr)
3731                                 /* repeat for some time before giving up */
3732                                 continue;
3733                         else if (!hsfsts.hsf_status.flcdone)
3734                                 return ret_val;
3735                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3736         }
3737
3738         return 0;
3739 }
3740
3741 /**
3742  *  e1000_valid_led_default_ich8lan - Set the default LED settings
3743  *  @hw: pointer to the HW structure
3744  *  @data: Pointer to the LED settings
3745  *
3746  *  Reads the LED default settings from the NVM to data.  If the NVM LED
3747  *  settings is all 0's or F's, set the LED default to a valid LED default
3748  *  setting.
3749  **/
3750 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3751 {
3752         s32 ret_val;
3753
3754         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
3755         if (ret_val) {
3756                 e_dbg("NVM Read Error\n");
3757                 return ret_val;
3758         }
3759
3760         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
3761                 *data = ID_LED_DEFAULT_ICH8LAN;
3762
3763         return 0;
3764 }
3765
3766 /**
3767  *  e1000_id_led_init_pchlan - store LED configurations
3768  *  @hw: pointer to the HW structure
3769  *
3770  *  PCH does not control LEDs via the LEDCTL register, rather it uses
3771  *  the PHY LED configuration register.
3772  *
3773  *  PCH also does not have an "always on" or "always off" mode which
3774  *  complicates the ID feature.  Instead of using the "on" mode to indicate
3775  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
3776  *  use "link_up" mode.  The LEDs will still ID on request if there is no
3777  *  link based on logic in e1000_led_[on|off]_pchlan().
3778  **/
3779 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3780 {
3781         struct e1000_mac_info *mac = &hw->mac;
3782         s32 ret_val;
3783         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3784         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3785         u16 data, i, temp, shift;
3786
3787         /* Get default ID LED modes */
3788         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3789         if (ret_val)
3790                 return ret_val;
3791
3792         mac->ledctl_default = er32(LEDCTL);
3793         mac->ledctl_mode1 = mac->ledctl_default;
3794         mac->ledctl_mode2 = mac->ledctl_default;
3795
3796         for (i = 0; i < 4; i++) {
3797                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3798                 shift = (i * 5);
3799                 switch (temp) {
3800                 case ID_LED_ON1_DEF2:
3801                 case ID_LED_ON1_ON2:
3802                 case ID_LED_ON1_OFF2:
3803                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3804                         mac->ledctl_mode1 |= (ledctl_on << shift);
3805                         break;
3806                 case ID_LED_OFF1_DEF2:
3807                 case ID_LED_OFF1_ON2:
3808                 case ID_LED_OFF1_OFF2:
3809                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3810                         mac->ledctl_mode1 |= (ledctl_off << shift);
3811                         break;
3812                 default:
3813                         /* Do nothing */
3814                         break;
3815                 }
3816                 switch (temp) {
3817                 case ID_LED_DEF1_ON2:
3818                 case ID_LED_ON1_ON2:
3819                 case ID_LED_OFF1_ON2:
3820                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3821                         mac->ledctl_mode2 |= (ledctl_on << shift);
3822                         break;
3823                 case ID_LED_DEF1_OFF2:
3824                 case ID_LED_ON1_OFF2:
3825                 case ID_LED_OFF1_OFF2:
3826                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3827                         mac->ledctl_mode2 |= (ledctl_off << shift);
3828                         break;
3829                 default:
3830                         /* Do nothing */
3831                         break;
3832                 }
3833         }
3834
3835         return 0;
3836 }
3837
3838 /**
3839  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3840  *  @hw: pointer to the HW structure
3841  *
3842  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3843  *  register, so the the bus width is hard coded.
3844  **/
3845 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3846 {
3847         struct e1000_bus_info *bus = &hw->bus;
3848         s32 ret_val;
3849
3850         ret_val = e1000e_get_bus_info_pcie(hw);
3851
3852         /* ICH devices are "PCI Express"-ish.  They have
3853          * a configuration space, but do not contain
3854          * PCI Express Capability registers, so bus width
3855          * must be hardcoded.
3856          */
3857         if (bus->width == e1000_bus_width_unknown)
3858                 bus->width = e1000_bus_width_pcie_x1;
3859
3860         return ret_val;
3861 }
3862
3863 /**
3864  *  e1000_reset_hw_ich8lan - Reset the hardware
3865  *  @hw: pointer to the HW structure
3866  *
3867  *  Does a full reset of the hardware which includes a reset of the PHY and
3868  *  MAC.
3869  **/
3870 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3871 {
3872         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3873         u16 kum_cfg;
3874         u32 ctrl, reg;
3875         s32 ret_val;
3876
3877         /* Prevent the PCI-E bus from sticking if there is no TLP connection
3878          * on the last TLP read/write transaction when MAC is reset.
3879          */
3880         ret_val = e1000e_disable_pcie_master(hw);
3881         if (ret_val)
3882                 e_dbg("PCI-E Master disable polling has failed.\n");
3883
3884         e_dbg("Masking off all interrupts\n");
3885         ew32(IMC, 0xffffffff);
3886
3887         /* Disable the Transmit and Receive units.  Then delay to allow
3888          * any pending transactions to complete before we hit the MAC
3889          * with the global reset.
3890          */
3891         ew32(RCTL, 0);
3892         ew32(TCTL, E1000_TCTL_PSP);
3893         e1e_flush();
3894
3895         usleep_range(10000, 20000);
3896
3897         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3898         if (hw->mac.type == e1000_ich8lan) {
3899                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3900                 ew32(PBA, E1000_PBA_8K);
3901                 /* Set Packet Buffer Size to 16k. */
3902                 ew32(PBS, E1000_PBS_16K);
3903         }
3904
3905         if (hw->mac.type == e1000_pchlan) {
3906                 /* Save the NVM K1 bit setting */
3907                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
3908                 if (ret_val)
3909                         return ret_val;
3910
3911                 if (kum_cfg & E1000_NVM_K1_ENABLE)
3912                         dev_spec->nvm_k1_enabled = true;
3913                 else
3914                         dev_spec->nvm_k1_enabled = false;
3915         }
3916
3917         ctrl = er32(CTRL);
3918
3919         if (!hw->phy.ops.check_reset_block(hw)) {
3920                 /* Full-chip reset requires MAC and PHY reset at the same
3921                  * time to make sure the interface between MAC and the
3922                  * external PHY is reset.
3923                  */
3924                 ctrl |= E1000_CTRL_PHY_RST;
3925
3926                 /* Gate automatic PHY configuration by hardware on
3927                  * non-managed 82579
3928                  */
3929                 if ((hw->mac.type == e1000_pch2lan) &&
3930                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3931                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3932         }
3933         ret_val = e1000_acquire_swflag_ich8lan(hw);
3934         e_dbg("Issuing a global reset to ich8lan\n");
3935         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3936         /* cannot issue a flush here because it hangs the hardware */
3937         msleep(20);
3938
3939         /* Set Phy Config Counter to 50msec */
3940         if (hw->mac.type == e1000_pch2lan) {
3941                 reg = er32(FEXTNVM3);
3942                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
3943                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
3944                 ew32(FEXTNVM3, reg);
3945         }
3946
3947         if (!ret_val)
3948                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
3949
3950         if (ctrl & E1000_CTRL_PHY_RST) {
3951                 ret_val = hw->phy.ops.get_cfg_done(hw);
3952                 if (ret_val)
3953                         return ret_val;
3954
3955                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3956                 if (ret_val)
3957                         return ret_val;
3958         }
3959
3960         /* For PCH, this write will make sure that any noise
3961          * will be detected as a CRC error and be dropped rather than show up
3962          * as a bad packet to the DMA engine.
3963          */
3964         if (hw->mac.type == e1000_pchlan)
3965                 ew32(CRC_OFFSET, 0x65656565);
3966
3967         ew32(IMC, 0xffffffff);
3968         er32(ICR);
3969
3970         reg = er32(KABGTXD);
3971         reg |= E1000_KABGTXD_BGSQLBIAS;
3972         ew32(KABGTXD, reg);
3973
3974         return 0;
3975 }
3976
3977 /**
3978  *  e1000_init_hw_ich8lan - Initialize the hardware
3979  *  @hw: pointer to the HW structure
3980  *
3981  *  Prepares the hardware for transmit and receive by doing the following:
3982  *   - initialize hardware bits
3983  *   - initialize LED identification
3984  *   - setup receive address registers
3985  *   - setup flow control
3986  *   - setup transmit descriptors
3987  *   - clear statistics
3988  **/
3989 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3990 {
3991         struct e1000_mac_info *mac = &hw->mac;
3992         u32 ctrl_ext, txdctl, snoop;
3993         s32 ret_val;
3994         u16 i;
3995
3996         e1000_initialize_hw_bits_ich8lan(hw);
3997
3998         /* Initialize identification LED */
3999         ret_val = mac->ops.id_led_init(hw);
4000         /* An error is not fatal and we should not stop init due to this */
4001         if (ret_val)
4002                 e_dbg("Error initializing identification LED\n");
4003
4004         /* Setup the receive address. */
4005         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4006
4007         /* Zero out the Multicast HASH table */
4008         e_dbg("Zeroing the MTA\n");
4009         for (i = 0; i < mac->mta_reg_count; i++)
4010                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4011
4012         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4013          * the ME.  Disable wakeup by clearing the host wakeup bit.
4014          * Reset the phy after disabling host wakeup to reset the Rx buffer.
4015          */
4016         if (hw->phy.type == e1000_phy_82578) {
4017                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4018                 i &= ~BM_WUC_HOST_WU_BIT;
4019                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4020                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4021                 if (ret_val)
4022                         return ret_val;
4023         }
4024
4025         /* Setup link and flow control */
4026         ret_val = mac->ops.setup_link(hw);
4027
4028         /* Set the transmit descriptor write-back policy for both queues */
4029         txdctl = er32(TXDCTL(0));
4030         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4031                   E1000_TXDCTL_FULL_TX_DESC_WB);
4032         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4033                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4034         ew32(TXDCTL(0), txdctl);
4035         txdctl = er32(TXDCTL(1));
4036         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4037                   E1000_TXDCTL_FULL_TX_DESC_WB);
4038         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4039                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4040         ew32(TXDCTL(1), txdctl);
4041
4042         /* ICH8 has opposite polarity of no_snoop bits.
4043          * By default, we should use snoop behavior.
4044          */
4045         if (mac->type == e1000_ich8lan)
4046                 snoop = PCIE_ICH8_SNOOP_ALL;
4047         else
4048                 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4049         e1000e_set_pcie_no_snoop(hw, snoop);
4050
4051         ctrl_ext = er32(CTRL_EXT);
4052         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4053         ew32(CTRL_EXT, ctrl_ext);
4054
4055         /* Clear all of the statistics registers (clear on read).  It is
4056          * important that we do this after we have tried to establish link
4057          * because the symbol error count will increment wildly if there
4058          * is no link.
4059          */
4060         e1000_clear_hw_cntrs_ich8lan(hw);
4061
4062         return ret_val;
4063 }
4064
4065 /**
4066  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4067  *  @hw: pointer to the HW structure
4068  *
4069  *  Sets/Clears required hardware bits necessary for correctly setting up the
4070  *  hardware for transmit and receive.
4071  **/
4072 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4073 {
4074         u32 reg;
4075
4076         /* Extended Device Control */
4077         reg = er32(CTRL_EXT);
4078         reg |= (1 << 22);
4079         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4080         if (hw->mac.type >= e1000_pchlan)
4081                 reg |= E1000_CTRL_EXT_PHYPDEN;
4082         ew32(CTRL_EXT, reg);
4083
4084         /* Transmit Descriptor Control 0 */
4085         reg = er32(TXDCTL(0));
4086         reg |= (1 << 22);
4087         ew32(TXDCTL(0), reg);
4088
4089         /* Transmit Descriptor Control 1 */
4090         reg = er32(TXDCTL(1));
4091         reg |= (1 << 22);
4092         ew32(TXDCTL(1), reg);
4093
4094         /* Transmit Arbitration Control 0 */
4095         reg = er32(TARC(0));
4096         if (hw->mac.type == e1000_ich8lan)
4097                 reg |= (1 << 28) | (1 << 29);
4098         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
4099         ew32(TARC(0), reg);
4100
4101         /* Transmit Arbitration Control 1 */
4102         reg = er32(TARC(1));
4103         if (er32(TCTL) & E1000_TCTL_MULR)
4104                 reg &= ~(1 << 28);
4105         else
4106                 reg |= (1 << 28);
4107         reg |= (1 << 24) | (1 << 26) | (1 << 30);
4108         ew32(TARC(1), reg);
4109
4110         /* Device Status */
4111         if (hw->mac.type == e1000_ich8lan) {
4112                 reg = er32(STATUS);
4113                 reg &= ~(1 << 31);
4114                 ew32(STATUS, reg);
4115         }
4116
4117         /* work-around descriptor data corruption issue during nfs v2 udp
4118          * traffic, just disable the nfs filtering capability
4119          */
4120         reg = er32(RFCTL);
4121         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4122
4123         /* Disable IPv6 extension header parsing because some malformed
4124          * IPv6 headers can hang the Rx.
4125          */
4126         if (hw->mac.type == e1000_ich8lan)
4127                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4128         ew32(RFCTL, reg);
4129
4130         /* Enable ECC on Lynxpoint */
4131         if (hw->mac.type == e1000_pch_lpt) {
4132                 reg = er32(PBECCSTS);
4133                 reg |= E1000_PBECCSTS_ECC_ENABLE;
4134                 ew32(PBECCSTS, reg);
4135
4136                 reg = er32(CTRL);
4137                 reg |= E1000_CTRL_MEHE;
4138                 ew32(CTRL, reg);
4139         }
4140 }
4141
4142 /**
4143  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4144  *  @hw: pointer to the HW structure
4145  *
4146  *  Determines which flow control settings to use, then configures flow
4147  *  control.  Calls the appropriate media-specific link configuration
4148  *  function.  Assuming the adapter has a valid link partner, a valid link
4149  *  should be established.  Assumes the hardware has previously been reset
4150  *  and the transmitter and receiver are not enabled.
4151  **/
4152 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4153 {
4154         s32 ret_val;
4155
4156         if (hw->phy.ops.check_reset_block(hw))
4157                 return 0;
4158
4159         /* ICH parts do not have a word in the NVM to determine
4160          * the default flow control setting, so we explicitly
4161          * set it to full.
4162          */
4163         if (hw->fc.requested_mode == e1000_fc_default) {
4164                 /* Workaround h/w hang when Tx flow control enabled */
4165                 if (hw->mac.type == e1000_pchlan)
4166                         hw->fc.requested_mode = e1000_fc_rx_pause;
4167                 else
4168                         hw->fc.requested_mode = e1000_fc_full;
4169         }
4170
4171         /* Save off the requested flow control mode for use later.  Depending
4172          * on the link partner's capabilities, we may or may not use this mode.
4173          */
4174         hw->fc.current_mode = hw->fc.requested_mode;
4175
4176         e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
4177
4178         /* Continue to configure the copper link. */
4179         ret_val = hw->mac.ops.setup_physical_interface(hw);
4180         if (ret_val)
4181                 return ret_val;
4182
4183         ew32(FCTTV, hw->fc.pause_time);
4184         if ((hw->phy.type == e1000_phy_82578) ||
4185             (hw->phy.type == e1000_phy_82579) ||
4186             (hw->phy.type == e1000_phy_i217) ||
4187             (hw->phy.type == e1000_phy_82577)) {
4188                 ew32(FCRTV_PCH, hw->fc.refresh_time);
4189
4190                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
4191                                    hw->fc.pause_time);
4192                 if (ret_val)
4193                         return ret_val;
4194         }
4195
4196         return e1000e_set_fc_watermarks(hw);
4197 }
4198
4199 /**
4200  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4201  *  @hw: pointer to the HW structure
4202  *
4203  *  Configures the kumeran interface to the PHY to wait the appropriate time
4204  *  when polling the PHY, then call the generic setup_copper_link to finish
4205  *  configuring the copper link.
4206  **/
4207 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4208 {
4209         u32 ctrl;
4210         s32 ret_val;
4211         u16 reg_data;
4212
4213         ctrl = er32(CTRL);
4214         ctrl |= E1000_CTRL_SLU;
4215         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4216         ew32(CTRL, ctrl);
4217
4218         /* Set the mac to wait the maximum time between each iteration
4219          * and increase the max iterations when polling the phy;
4220          * this fixes erroneous timeouts at 10Mbps.
4221          */
4222         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
4223         if (ret_val)
4224                 return ret_val;
4225         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
4226                                        &reg_data);
4227         if (ret_val)
4228                 return ret_val;
4229         reg_data |= 0x3F;
4230         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
4231                                         reg_data);
4232         if (ret_val)
4233                 return ret_val;
4234
4235         switch (hw->phy.type) {
4236         case e1000_phy_igp_3:
4237                 ret_val = e1000e_copper_link_setup_igp(hw);
4238                 if (ret_val)
4239                         return ret_val;
4240                 break;
4241         case e1000_phy_bm:
4242         case e1000_phy_82578:
4243                 ret_val = e1000e_copper_link_setup_m88(hw);
4244                 if (ret_val)
4245                         return ret_val;
4246                 break;
4247         case e1000_phy_82577:
4248         case e1000_phy_82579:
4249                 ret_val = e1000_copper_link_setup_82577(hw);
4250                 if (ret_val)
4251                         return ret_val;
4252                 break;
4253         case e1000_phy_ife:
4254                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
4255                 if (ret_val)
4256                         return ret_val;
4257
4258                 reg_data &= ~IFE_PMC_AUTO_MDIX;
4259
4260                 switch (hw->phy.mdix) {
4261                 case 1:
4262                         reg_data &= ~IFE_PMC_FORCE_MDIX;
4263                         break;
4264                 case 2:
4265                         reg_data |= IFE_PMC_FORCE_MDIX;
4266                         break;
4267                 case 0:
4268                 default:
4269                         reg_data |= IFE_PMC_AUTO_MDIX;
4270                         break;
4271                 }
4272                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
4273                 if (ret_val)
4274                         return ret_val;
4275                 break;
4276         default:
4277                 break;
4278         }
4279
4280         return e1000e_setup_copper_link(hw);
4281 }
4282
4283 /**
4284  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
4285  *  @hw: pointer to the HW structure
4286  *
4287  *  Calls the PHY specific link setup function and then calls the
4288  *  generic setup_copper_link to finish configuring the link for
4289  *  Lynxpoint PCH devices
4290  **/
4291 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
4292 {
4293         u32 ctrl;
4294         s32 ret_val;
4295
4296         ctrl = er32(CTRL);
4297         ctrl |= E1000_CTRL_SLU;
4298         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4299         ew32(CTRL, ctrl);
4300
4301         ret_val = e1000_copper_link_setup_82577(hw);
4302         if (ret_val)
4303                 return ret_val;
4304
4305         return e1000e_setup_copper_link(hw);
4306 }
4307
4308 /**
4309  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4310  *  @hw: pointer to the HW structure
4311  *  @speed: pointer to store current link speed
4312  *  @duplex: pointer to store the current link duplex
4313  *
4314  *  Calls the generic get_speed_and_duplex to retrieve the current link
4315  *  information and then calls the Kumeran lock loss workaround for links at
4316  *  gigabit speeds.
4317  **/
4318 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4319                                           u16 *duplex)
4320 {
4321         s32 ret_val;
4322
4323         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
4324         if (ret_val)
4325                 return ret_val;
4326
4327         if ((hw->mac.type == e1000_ich8lan) &&
4328             (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
4329                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4330         }
4331
4332         return ret_val;
4333 }
4334
4335 /**
4336  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4337  *  @hw: pointer to the HW structure
4338  *
4339  *  Work-around for 82566 Kumeran PCS lock loss:
4340  *  On link status change (i.e. PCI reset, speed change) and link is up and
4341  *  speed is gigabit-
4342  *    0) if workaround is optionally disabled do nothing
4343  *    1) wait 1ms for Kumeran link to come up
4344  *    2) check Kumeran Diagnostic register PCS lock loss bit
4345  *    3) if not set the link is locked (all is good), otherwise...
4346  *    4) reset the PHY
4347  *    5) repeat up to 10 times
4348  *  Note: this is only called for IGP3 copper when speed is 1gb.
4349  **/
4350 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4351 {
4352         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4353         u32 phy_ctrl;
4354         s32 ret_val;
4355         u16 i, data;
4356         bool link;
4357
4358         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4359                 return 0;
4360
4361         /* Make sure link is up before proceeding.  If not just return.
4362          * Attempting this while link is negotiating fouled up link
4363          * stability
4364          */
4365         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
4366         if (!link)
4367                 return 0;
4368
4369         for (i = 0; i < 10; i++) {
4370                 /* read once to clear */
4371                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
4372                 if (ret_val)
4373                         return ret_val;
4374                 /* and again to get new status */
4375                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
4376                 if (ret_val)
4377                         return ret_val;
4378
4379                 /* check for PCS lock */
4380                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4381                         return 0;
4382
4383                 /* Issue PHY reset */
4384                 e1000_phy_hw_reset(hw);
4385                 mdelay(5);
4386         }
4387         /* Disable GigE link negotiation */
4388         phy_ctrl = er32(PHY_CTRL);
4389         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4390                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4391         ew32(PHY_CTRL, phy_ctrl);
4392
4393         /* Call gig speed drop workaround on Gig disable before accessing
4394          * any PHY registers
4395          */
4396         e1000e_gig_downshift_workaround_ich8lan(hw);
4397
4398         /* unable to acquire PCS lock */
4399         return -E1000_ERR_PHY;
4400 }
4401
4402 /**
4403  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4404  *  @hw: pointer to the HW structure
4405  *  @state: boolean value used to set the current Kumeran workaround state
4406  *
4407  *  If ICH8, set the current Kumeran workaround state (enabled - true
4408  *  /disabled - false).
4409  **/
4410 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4411                                                   bool state)
4412 {
4413         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4414
4415         if (hw->mac.type != e1000_ich8lan) {
4416                 e_dbg("Workaround applies to ICH8 only.\n");
4417                 return;
4418         }
4419
4420         dev_spec->kmrn_lock_loss_workaround_enabled = state;
4421 }
4422
4423 /**
4424  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4425  *  @hw: pointer to the HW structure
4426  *
4427  *  Workaround for 82566 power-down on D3 entry:
4428  *    1) disable gigabit link
4429  *    2) write VR power-down enable
4430  *    3) read it back
4431  *  Continue if successful, else issue LCD reset and repeat
4432  **/
4433 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4434 {
4435         u32 reg;
4436         u16 data;
4437         u8 retry = 0;
4438
4439         if (hw->phy.type != e1000_phy_igp_3)
4440                 return;
4441
4442         /* Try the workaround twice (if needed) */
4443         do {
4444                 /* Disable link */
4445                 reg = er32(PHY_CTRL);
4446                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4447                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4448                 ew32(PHY_CTRL, reg);
4449
4450                 /* Call gig speed drop workaround on Gig disable before
4451                  * accessing any PHY registers
4452                  */
4453                 if (hw->mac.type == e1000_ich8lan)
4454                         e1000e_gig_downshift_workaround_ich8lan(hw);
4455
4456                 /* Write VR power-down enable */
4457                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4458                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4459                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4460
4461                 /* Read it back and test */
4462                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4463                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4464                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4465                         break;
4466
4467                 /* Issue PHY reset and repeat at most one more time */
4468                 reg = er32(CTRL);
4469                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
4470                 retry++;
4471         } while (retry);
4472 }
4473
4474 /**
4475  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4476  *  @hw: pointer to the HW structure
4477  *
4478  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4479  *  LPLU, Gig disable, MDIC PHY reset):
4480  *    1) Set Kumeran Near-end loopback
4481  *    2) Clear Kumeran Near-end loopback
4482  *  Should only be called for ICH8[m] devices with any 1G Phy.
4483  **/
4484 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4485 {
4486         s32 ret_val;
4487         u16 reg_data;
4488
4489         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
4490                 return;
4491
4492         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4493                                        &reg_data);
4494         if (ret_val)
4495                 return;
4496         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4497         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4498                                         reg_data);
4499         if (ret_val)
4500                 return;
4501         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4502         e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
4503 }
4504
4505 /**
4506  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4507  *  @hw: pointer to the HW structure
4508  *
4509  *  During S0 to Sx transition, it is possible the link remains at gig
4510  *  instead of negotiating to a lower speed.  Before going to Sx, set
4511  *  'Gig Disable' to force link speed negotiation to a lower speed based on
4512  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
4513  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4514  *  needs to be written.
4515  *  Parts that support (and are linked to a partner which support) EEE in
4516  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4517  *  than 10Mbps w/o EEE.
4518  **/
4519 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4520 {
4521         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4522         u32 phy_ctrl;
4523         s32 ret_val;
4524
4525         phy_ctrl = er32(PHY_CTRL);
4526         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4527
4528         if (hw->phy.type == e1000_phy_i217) {
4529                 u16 phy_reg, device_id = hw->adapter->pdev->device;
4530
4531                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4532                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4533                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4534                     (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4535                         u32 fextnvm6 = er32(FEXTNVM6);
4536
4537                         ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4538                 }
4539
4540                 ret_val = hw->phy.ops.acquire(hw);
4541                 if (ret_val)
4542                         goto out;
4543
4544                 if (!dev_spec->eee_disable) {
4545                         u16 eee_advert;
4546
4547                         ret_val =
4548                             e1000_read_emi_reg_locked(hw,
4549                                                       I217_EEE_ADVERTISEMENT,
4550                                                       &eee_advert);
4551                         if (ret_val)
4552                                 goto release;
4553
4554                         /* Disable LPLU if both link partners support 100BaseT
4555                          * EEE and 100Full is advertised on both ends of the
4556                          * link.
4557                          */
4558                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4559                             (dev_spec->eee_lp_ability &
4560                              I82579_EEE_100_SUPPORTED) &&
4561                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
4562                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4563                                               E1000_PHY_CTRL_NOND0A_LPLU);
4564                 }
4565
4566                 /* For i217 Intel Rapid Start Technology support,
4567                  * when the system is going into Sx and no manageability engine
4568                  * is present, the driver must configure proxy to reset only on
4569                  * power good.  LPI (Low Power Idle) state must also reset only
4570                  * on power good, as well as the MTA (Multicast table array).
4571                  * The SMBus release must also be disabled on LCD reset.
4572                  */
4573                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4574                         /* Enable proxy to reset only on power good. */
4575                         e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
4576                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4577                         e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
4578
4579                         /* Set bit enable LPI (EEE) to reset only on
4580                          * power good.
4581                          */
4582                         e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
4583                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4584                         e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
4585
4586                         /* Disable the SMB release on LCD reset. */
4587                         e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4588                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4589                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4590                 }
4591
4592                 /* Enable MTA to reset for Intel Rapid Start Technology
4593                  * Support
4594                  */
4595                 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4596                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4597                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4598
4599 release:
4600                 hw->phy.ops.release(hw);
4601         }
4602 out:
4603         ew32(PHY_CTRL, phy_ctrl);
4604
4605         if (hw->mac.type == e1000_ich8lan)
4606                 e1000e_gig_downshift_workaround_ich8lan(hw);
4607
4608         if (hw->mac.type >= e1000_pchlan) {
4609                 e1000_oem_bits_config_ich8lan(hw, false);
4610
4611                 /* Reset PHY to activate OEM bits on 82577/8 */
4612                 if (hw->mac.type == e1000_pchlan)
4613                         e1000e_phy_hw_reset_generic(hw);
4614
4615                 ret_val = hw->phy.ops.acquire(hw);
4616                 if (ret_val)
4617                         return;
4618                 e1000_write_smbus_addr(hw);
4619                 hw->phy.ops.release(hw);
4620         }
4621 }
4622
4623 /**
4624  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4625  *  @hw: pointer to the HW structure
4626  *
4627  *  During Sx to S0 transitions on non-managed devices or managed devices
4628  *  on which PHY resets are not blocked, if the PHY registers cannot be
4629  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
4630  *  the PHY.
4631  *  On i217, setup Intel Rapid Start Technology.
4632  **/
4633 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4634 {
4635         s32 ret_val;
4636
4637         if (hw->mac.type < e1000_pch2lan)
4638                 return;
4639
4640         ret_val = e1000_init_phy_workarounds_pchlan(hw);
4641         if (ret_val) {
4642                 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
4643                 return;
4644         }
4645
4646         /* For i217 Intel Rapid Start Technology support when the system
4647          * is transitioning from Sx and no manageability engine is present
4648          * configure SMBus to restore on reset, disable proxy, and enable
4649          * the reset on MTA (Multicast table array).
4650          */
4651         if (hw->phy.type == e1000_phy_i217) {
4652                 u16 phy_reg;
4653
4654                 ret_val = hw->phy.ops.acquire(hw);
4655                 if (ret_val) {
4656                         e_dbg("Failed to setup iRST\n");
4657                         return;
4658                 }
4659
4660                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4661                         /* Restore clear on SMB if no manageability engine
4662                          * is present
4663                          */
4664                         ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4665                         if (ret_val)
4666                                 goto release;
4667                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
4668                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4669
4670                         /* Disable Proxy */
4671                         e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
4672                 }
4673                 /* Enable reset on MTA */
4674                 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4675                 if (ret_val)
4676                         goto release;
4677                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
4678                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4679 release:
4680                 if (ret_val)
4681                         e_dbg("Error %d in resume workarounds\n", ret_val);
4682                 hw->phy.ops.release(hw);
4683         }
4684 }
4685
4686 /**
4687  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
4688  *  @hw: pointer to the HW structure
4689  *
4690  *  Return the LED back to the default configuration.
4691  **/
4692 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4693 {
4694         if (hw->phy.type == e1000_phy_ife)
4695                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
4696
4697         ew32(LEDCTL, hw->mac.ledctl_default);
4698         return 0;
4699 }
4700
4701 /**
4702  *  e1000_led_on_ich8lan - Turn LEDs on
4703  *  @hw: pointer to the HW structure
4704  *
4705  *  Turn on the LEDs.
4706  **/
4707 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
4708 {
4709         if (hw->phy.type == e1000_phy_ife)
4710                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4711                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
4712
4713         ew32(LEDCTL, hw->mac.ledctl_mode2);
4714         return 0;
4715 }
4716
4717 /**
4718  *  e1000_led_off_ich8lan - Turn LEDs off
4719  *  @hw: pointer to the HW structure
4720  *
4721  *  Turn off the LEDs.
4722  **/
4723 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
4724 {
4725         if (hw->phy.type == e1000_phy_ife)
4726                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4727                                 (IFE_PSCL_PROBE_MODE |
4728                                  IFE_PSCL_PROBE_LEDS_OFF));
4729
4730         ew32(LEDCTL, hw->mac.ledctl_mode1);
4731         return 0;
4732 }
4733
4734 /**
4735  *  e1000_setup_led_pchlan - Configures SW controllable LED
4736  *  @hw: pointer to the HW structure
4737  *
4738  *  This prepares the SW controllable LED for use.
4739  **/
4740 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
4741 {
4742         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
4743 }
4744
4745 /**
4746  *  e1000_cleanup_led_pchlan - Restore the default LED operation
4747  *  @hw: pointer to the HW structure
4748  *
4749  *  Return the LED back to the default configuration.
4750  **/
4751 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4752 {
4753         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
4754 }
4755
4756 /**
4757  *  e1000_led_on_pchlan - Turn LEDs on
4758  *  @hw: pointer to the HW structure
4759  *
4760  *  Turn on the LEDs.
4761  **/
4762 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
4763 {
4764         u16 data = (u16)hw->mac.ledctl_mode2;
4765         u32 i, led;
4766
4767         /* If no link, then turn LED on by setting the invert bit
4768          * for each LED that's mode is "link_up" in ledctl_mode2.
4769          */
4770         if (!(er32(STATUS) & E1000_STATUS_LU)) {
4771                 for (i = 0; i < 3; i++) {
4772                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4773                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4774                             E1000_LEDCTL_MODE_LINK_UP)
4775                                 continue;
4776                         if (led & E1000_PHY_LED0_IVRT)
4777                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4778                         else
4779                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4780                 }
4781         }
4782
4783         return e1e_wphy(hw, HV_LED_CONFIG, data);
4784 }
4785
4786 /**
4787  *  e1000_led_off_pchlan - Turn LEDs off
4788  *  @hw: pointer to the HW structure
4789  *
4790  *  Turn off the LEDs.
4791  **/
4792 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
4793 {
4794         u16 data = (u16)hw->mac.ledctl_mode1;
4795         u32 i, led;
4796
4797         /* If no link, then turn LED off by clearing the invert bit
4798          * for each LED that's mode is "link_up" in ledctl_mode1.
4799          */
4800         if (!(er32(STATUS) & E1000_STATUS_LU)) {
4801                 for (i = 0; i < 3; i++) {
4802                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4803                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4804                             E1000_LEDCTL_MODE_LINK_UP)
4805                                 continue;
4806                         if (led & E1000_PHY_LED0_IVRT)
4807                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4808                         else
4809                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4810                 }
4811         }
4812
4813         return e1e_wphy(hw, HV_LED_CONFIG, data);
4814 }
4815
4816 /**
4817  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
4818  *  @hw: pointer to the HW structure
4819  *
4820  *  Read appropriate register for the config done bit for completion status
4821  *  and configure the PHY through s/w for EEPROM-less parts.
4822  *
4823  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
4824  *  config done bit, so only an error is logged and continues.  If we were
4825  *  to return with error, EEPROM-less silicon would not be able to be reset
4826  *  or change link.
4827  **/
4828 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4829 {
4830         s32 ret_val = 0;
4831         u32 bank = 0;
4832         u32 status;
4833
4834         e1000e_get_cfg_done_generic(hw);
4835
4836         /* Wait for indication from h/w that it has completed basic config */
4837         if (hw->mac.type >= e1000_ich10lan) {
4838                 e1000_lan_init_done_ich8lan(hw);
4839         } else {
4840                 ret_val = e1000e_get_auto_rd_done(hw);
4841                 if (ret_val) {
4842                         /* When auto config read does not complete, do not
4843                          * return with an error. This can happen in situations
4844                          * where there is no eeprom and prevents getting link.
4845                          */
4846                         e_dbg("Auto Read Done did not complete\n");
4847                         ret_val = 0;
4848                 }
4849         }
4850
4851         /* Clear PHY Reset Asserted bit */
4852         status = er32(STATUS);
4853         if (status & E1000_STATUS_PHYRA)
4854                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
4855         else
4856                 e_dbg("PHY Reset Asserted not set - needs delay\n");
4857
4858         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
4859         if (hw->mac.type <= e1000_ich9lan) {
4860                 if (!(er32(EECD) & E1000_EECD_PRES) &&
4861                     (hw->phy.type == e1000_phy_igp_3)) {
4862                         e1000e_phy_init_script_igp3(hw);
4863                 }
4864         } else {
4865                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
4866                         /* Maybe we should do a basic PHY config */
4867                         e_dbg("EEPROM not present\n");
4868                         ret_val = -E1000_ERR_CONFIG;
4869                 }
4870         }
4871
4872         return ret_val;
4873 }
4874
4875 /**
4876  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4877  * @hw: pointer to the HW structure
4878  *
4879  * In the case of a PHY power down to save power, or to turn off link during a
4880  * driver unload, or wake on lan is not enabled, remove the link.
4881  **/
4882 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
4883 {
4884         /* If the management interface is not enabled, then power down */
4885         if (!(hw->mac.ops.check_mng_mode(hw) ||
4886               hw->phy.ops.check_reset_block(hw)))
4887                 e1000_power_down_phy_copper(hw);
4888 }
4889
4890 /**
4891  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4892  *  @hw: pointer to the HW structure
4893  *
4894  *  Clears hardware counters specific to the silicon family and calls
4895  *  clear_hw_cntrs_generic to clear all general purpose counters.
4896  **/
4897 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4898 {
4899         u16 phy_data;
4900         s32 ret_val;
4901
4902         e1000e_clear_hw_cntrs_base(hw);
4903
4904         er32(ALGNERRC);
4905         er32(RXERRC);
4906         er32(TNCRS);
4907         er32(CEXTERR);
4908         er32(TSCTC);
4909         er32(TSCTFC);
4910
4911         er32(MGTPRC);
4912         er32(MGTPDC);
4913         er32(MGTPTC);
4914
4915         er32(IAC);
4916         er32(ICRXOC);
4917
4918         /* Clear PHY statistics registers */
4919         if ((hw->phy.type == e1000_phy_82578) ||
4920             (hw->phy.type == e1000_phy_82579) ||
4921             (hw->phy.type == e1000_phy_i217) ||
4922             (hw->phy.type == e1000_phy_82577)) {
4923                 ret_val = hw->phy.ops.acquire(hw);
4924                 if (ret_val)
4925                         return;
4926                 ret_val = hw->phy.ops.set_page(hw,
4927                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
4928                 if (ret_val)
4929                         goto release;
4930                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4931                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4932                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4933                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4934                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4935                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4936                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4937                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4938                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4939                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4940                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4941                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4942                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4943                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4944 release:
4945                 hw->phy.ops.release(hw);
4946         }
4947 }
4948
4949 static const struct e1000_mac_operations ich8_mac_ops = {
4950         /* check_mng_mode dependent on mac type */
4951         .check_for_link         = e1000_check_for_copper_link_ich8lan,
4952         /* cleanup_led dependent on mac type */
4953         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
4954         .get_bus_info           = e1000_get_bus_info_ich8lan,
4955         .set_lan_id             = e1000_set_lan_id_single_port,
4956         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
4957         /* led_on dependent on mac type */
4958         /* led_off dependent on mac type */
4959         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
4960         .reset_hw               = e1000_reset_hw_ich8lan,
4961         .init_hw                = e1000_init_hw_ich8lan,
4962         .setup_link             = e1000_setup_link_ich8lan,
4963         .setup_physical_interface = e1000_setup_copper_link_ich8lan,
4964         /* id_led_init dependent on mac type */
4965         .config_collision_dist  = e1000e_config_collision_dist_generic,
4966         .rar_set                = e1000e_rar_set_generic,
4967 };
4968
4969 static const struct e1000_phy_operations ich8_phy_ops = {
4970         .acquire                = e1000_acquire_swflag_ich8lan,
4971         .check_reset_block      = e1000_check_reset_block_ich8lan,
4972         .commit                 = NULL,
4973         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
4974         .get_cable_length       = e1000e_get_cable_length_igp_2,
4975         .read_reg               = e1000e_read_phy_reg_igp,
4976         .release                = e1000_release_swflag_ich8lan,
4977         .reset                  = e1000_phy_hw_reset_ich8lan,
4978         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
4979         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
4980         .write_reg              = e1000e_write_phy_reg_igp,
4981 };
4982
4983 static const struct e1000_nvm_operations ich8_nvm_ops = {
4984         .acquire                = e1000_acquire_nvm_ich8lan,
4985         .read                   = e1000_read_nvm_ich8lan,
4986         .release                = e1000_release_nvm_ich8lan,
4987         .reload                 = e1000e_reload_nvm_generic,
4988         .update                 = e1000_update_nvm_checksum_ich8lan,
4989         .valid_led_default      = e1000_valid_led_default_ich8lan,
4990         .validate               = e1000_validate_nvm_checksum_ich8lan,
4991         .write                  = e1000_write_nvm_ich8lan,
4992 };
4993
4994 const struct e1000_info e1000_ich8_info = {
4995         .mac                    = e1000_ich8lan,
4996         .flags                  = FLAG_HAS_WOL
4997                                   | FLAG_IS_ICH
4998                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4999                                   | FLAG_HAS_AMT
5000                                   | FLAG_HAS_FLASH
5001                                   | FLAG_APME_IN_WUC,
5002         .pba                    = 8,
5003         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
5004         .get_variants           = e1000_get_variants_ich8lan,
5005         .mac_ops                = &ich8_mac_ops,
5006         .phy_ops                = &ich8_phy_ops,
5007         .nvm_ops                = &ich8_nvm_ops,
5008 };
5009
5010 const struct e1000_info e1000_ich9_info = {
5011         .mac                    = e1000_ich9lan,
5012         .flags                  = FLAG_HAS_JUMBO_FRAMES
5013                                   | FLAG_IS_ICH
5014                                   | FLAG_HAS_WOL
5015                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5016                                   | FLAG_HAS_AMT
5017                                   | FLAG_HAS_FLASH
5018                                   | FLAG_APME_IN_WUC,
5019         .pba                    = 18,
5020         .max_hw_frame_size      = DEFAULT_JUMBO,
5021         .get_variants           = e1000_get_variants_ich8lan,
5022         .mac_ops                = &ich8_mac_ops,
5023         .phy_ops                = &ich8_phy_ops,
5024         .nvm_ops                = &ich8_nvm_ops,
5025 };
5026
5027 const struct e1000_info e1000_ich10_info = {
5028         .mac                    = e1000_ich10lan,
5029         .flags                  = FLAG_HAS_JUMBO_FRAMES
5030                                   | FLAG_IS_ICH
5031                                   | FLAG_HAS_WOL
5032                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5033                                   | FLAG_HAS_AMT
5034                                   | FLAG_HAS_FLASH
5035                                   | FLAG_APME_IN_WUC,
5036         .pba                    = 18,
5037         .max_hw_frame_size      = DEFAULT_JUMBO,
5038         .get_variants           = e1000_get_variants_ich8lan,
5039         .mac_ops                = &ich8_mac_ops,
5040         .phy_ops                = &ich8_phy_ops,
5041         .nvm_ops                = &ich8_nvm_ops,
5042 };
5043
5044 const struct e1000_info e1000_pch_info = {
5045         .mac                    = e1000_pchlan,
5046         .flags                  = FLAG_IS_ICH
5047                                   | FLAG_HAS_WOL
5048                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5049                                   | FLAG_HAS_AMT
5050                                   | FLAG_HAS_FLASH
5051                                   | FLAG_HAS_JUMBO_FRAMES
5052                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5053                                   | FLAG_APME_IN_WUC,
5054         .flags2                 = FLAG2_HAS_PHY_STATS,
5055         .pba                    = 26,
5056         .max_hw_frame_size      = 4096,
5057         .get_variants           = e1000_get_variants_ich8lan,
5058         .mac_ops                = &ich8_mac_ops,
5059         .phy_ops                = &ich8_phy_ops,
5060         .nvm_ops                = &ich8_nvm_ops,
5061 };
5062
5063 const struct e1000_info e1000_pch2_info = {
5064         .mac                    = e1000_pch2lan,
5065         .flags                  = FLAG_IS_ICH
5066                                   | FLAG_HAS_WOL
5067                                   | FLAG_HAS_HW_TIMESTAMP
5068                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5069                                   | FLAG_HAS_AMT
5070                                   | FLAG_HAS_FLASH
5071                                   | FLAG_HAS_JUMBO_FRAMES
5072                                   | FLAG_APME_IN_WUC,
5073         .flags2                 = FLAG2_HAS_PHY_STATS
5074                                   | FLAG2_HAS_EEE,
5075         .pba                    = 26,
5076         .max_hw_frame_size      = 9018,
5077         .get_variants           = e1000_get_variants_ich8lan,
5078         .mac_ops                = &ich8_mac_ops,
5079         .phy_ops                = &ich8_phy_ops,
5080         .nvm_ops                = &ich8_nvm_ops,
5081 };
5082
5083 const struct e1000_info e1000_pch_lpt_info = {
5084         .mac                    = e1000_pch_lpt,
5085         .flags                  = FLAG_IS_ICH
5086                                   | FLAG_HAS_WOL
5087                                   | FLAG_HAS_HW_TIMESTAMP
5088                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5089                                   | FLAG_HAS_AMT
5090                                   | FLAG_HAS_FLASH
5091                                   | FLAG_HAS_JUMBO_FRAMES
5092                                   | FLAG_APME_IN_WUC,
5093         .flags2                 = FLAG2_HAS_PHY_STATS
5094                                   | FLAG2_HAS_EEE,
5095         .pba                    = 26,
5096         .max_hw_frame_size      = 9018,
5097         .get_variants           = e1000_get_variants_ich8lan,
5098         .mac_ops                = &ich8_mac_ops,
5099         .phy_ops                = &ich8_phy_ops,
5100         .nvm_ops                = &ich8_nvm_ops,
5101 };