drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 /* Intel PRO/1000 Linux driver
   2  * Copyright(c) 1999 - 2014 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * The full GNU General Public License is included in this distribution in
  14  * the file called "COPYING".
  15  *
  16  * Contact Information:
  17  * Linux NICS <linux.nics@intel.com>
  18  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  19  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  20  */
  21
  22 /* 82562G 10/100 Network Connection
  23  * 82562G-2 10/100 Network Connection
  24  * 82562GT 10/100 Network Connection
  25  * 82562GT-2 10/100 Network Connection
  26  * 82562V 10/100 Network Connection
  27  * 82562V-2 10/100 Network Connection
  28  * 82566DC-2 Gigabit Network Connection
  29  * 82566DC Gigabit Network Connection
  30  * 82566DM-2 Gigabit Network Connection
  31  * 82566DM Gigabit Network Connection
  32  * 82566MC Gigabit Network Connection
  33  * 82566MM Gigabit Network Connection
  34  * 82567LM Gigabit Network Connection
  35  * 82567LF Gigabit Network Connection
  36  * 82567V Gigabit Network Connection
  37  * 82567LM-2 Gigabit Network Connection
  38  * 82567LF-2 Gigabit Network Connection
  39  * 82567V-2 Gigabit Network Connection
  40  * 82567LF-3 Gigabit Network Connection
  41  * 82567LM-3 Gigabit Network Connection
  42  * 82567LM-4 Gigabit Network Connection
  43  * 82577LM Gigabit Network Connection
  44  * 82577LC Gigabit Network Connection
  45  * 82578DM Gigabit Network Connection
  46  * 82578DC Gigabit Network Connection
  47  * 82579LM Gigabit Network Connection
  48  * 82579V Gigabit Network Connection
  49  */
  50
  51 #include "e1000.h"
  52
  53 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
  54 /* Offset 04h HSFSTS */
  55 union ich8_hws_flash_status {
  56         struct ich8_hsfsts {
  57                 u16 flcdone:1;  /* bit 0 Flash Cycle Done */
  58                 u16 flcerr:1;   /* bit 1 Flash Cycle Error */
  59                 u16 dael:1;     /* bit 2 Direct Access error Log */
  60                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
  61                 u16 flcinprog:1;        /* bit 5 flash cycle in Progress */
  62                 u16 reserved1:2;        /* bit 13:6 Reserved */
  63                 u16 reserved2:6;        /* bit 13:6 Reserved */
  64                 u16 fldesvalid:1;       /* bit 14 Flash Descriptor Valid */
  65                 u16 flockdn:1;  /* bit 15 Flash Config Lock-Down */
  66         } hsf_status;
  67         u16 regval;
  68 };
  69
  70 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
  71 /* Offset 06h FLCTL */
  72 union ich8_hws_flash_ctrl {
  73         struct ich8_hsflctl {
  74                 u16 flcgo:1;    /* 0 Flash Cycle Go */
  75                 u16 flcycle:2;  /* 2:1 Flash Cycle */
  76                 u16 reserved:5; /* 7:3 Reserved  */
  77                 u16 fldbcount:2;        /* 9:8 Flash Data Byte Count */
  78                 u16 flockdn:6;  /* 15:10 Reserved */
  79         } hsf_ctrl;
  80         u16 regval;
  81 };
  82
  83 /* ICH Flash Region Access Permissions */
  84 union ich8_hws_flash_regacc {
  85         struct ich8_flracc {
  86                 u32 grra:8;     /* 0:7 GbE region Read Access */
  87                 u32 grwa:8;     /* 8:15 GbE region Write Access */
  88                 u32 gmrag:8;    /* 23:16 GbE Master Read Access Grant */
  89                 u32 gmwag:8;    /* 31:24 GbE Master Write Access Grant */
  90         } hsf_flregacc;
  91         u16 regval;
  92 };
  93
  94 /* ICH Flash Protected Region */
  95 union ich8_flash_protected_range {
  96         struct ich8_pr {
  97                 u32 base:13;    /* 0:12 Protected Range Base */
  98                 u32 reserved1:2;        /* 13:14 Reserved */
  99                 u32 rpe:1;      /* 15 Read Protection Enable */
 100                 u32 limit:13;   /* 16:28 Protected Range Limit */
 101                 u32 reserved2:2;        /* 29:30 Reserved */
 102                 u32 wpe:1;      /* 31 Write Protection Enable */
 103         } range;
 104         u32 regval;
 105 };
 106
 107 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 108 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 109 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 110 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 111                                                 u32 offset, u8 byte);
 112 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 113                                          u8 *data);
 114 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 115                                          u16 *data);
 116 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 117                                          u8 size, u16 *data);
 118 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 119 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 120 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 121 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 122 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 123 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 124 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 125 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 126 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 127 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 128 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 129 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 130 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 131 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 132 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 133 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 134 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 135 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
 136 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 137 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 139
 140 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 141 {
 142         return readw(hw->flash_address + reg);
 143 }
 144
 145 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 146 {
 147         return readl(hw->flash_address + reg);
 148 }
 149
 150 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 151 {
 152         writew(val, hw->flash_address + reg);
 153 }
 154
 155 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 156 {
 157         writel(val, hw->flash_address + reg);
 158 }
 159
 160 #define er16flash(reg)          __er16flash(hw, (reg))
 161 #define er32flash(reg)          __er32flash(hw, (reg))
 162 #define ew16flash(reg, val)     __ew16flash(hw, (reg), (val))
 163 #define ew32flash(reg, val)     __ew32flash(hw, (reg), (val))
 164
 165 /**
 166  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 167  *  @hw: pointer to the HW structure
 168  *
 169  *  Test access to the PHY registers by reading the PHY ID registers.  If
 170  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 171  *  otherwise assume the read PHY ID is correct if it is valid.
 172  *
 173  *  Assumes the sw/fw/hw semaphore is already acquired.
 174  **/
 175 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 176 {
 177         u16 phy_reg = 0;
 178         u32 phy_id = 0;
 179         s32 ret_val;
 180         u16 retry_count;
 181         u32 mac_reg = 0;
 182
 183         for (retry_count = 0; retry_count < 2; retry_count++) {
 184                 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
 185                 if (ret_val || (phy_reg == 0xFFFF))
 186                         continue;
 187                 phy_id = (u32)(phy_reg << 16);
 188
 189                 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
 190                 if (ret_val || (phy_reg == 0xFFFF)) {
 191                         phy_id = 0;
 192                         continue;
 193                 }
 194                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 195                 break;
 196         }
 197
 198         if (hw->phy.id) {
 199                 if (hw->phy.id == phy_id)
 200                         goto out;
 201         } else if (phy_id) {
 202                 hw->phy.id = phy_id;
 203                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 204                 goto out;
 205         }
 206
 207         /* In case the PHY needs to be in mdio slow mode,
 208          * set slow mode and try to get the PHY id again.
 209          */
 210         hw->phy.ops.release(hw);
 211         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 212         if (!ret_val)
 213                 ret_val = e1000e_get_phy_id(hw);
 214         hw->phy.ops.acquire(hw);
 215
 216         if (ret_val)
 217                 return false;
 218 out:
 219         if (hw->mac.type == e1000_pch_lpt) {
 220                 /* Unforce SMBus mode in PHY */
 221                 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
 222                 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 223                 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
 224
 225                 /* Unforce SMBus mode in MAC */
 226                 mac_reg = er32(CTRL_EXT);
 227                 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 228                 ew32(CTRL_EXT, mac_reg);
 229         }
 230
 231         return true;
 232 }
 233
 234 /**
 235  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 236  *  @hw: pointer to the HW structure
 237  *
 238  *  Workarounds/flow necessary for PHY initialization during driver load
 239  *  and resume paths.
 240  **/
 241 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 242 {
 243         struct e1000_adapter *adapter = hw->adapter;
 244         u32 mac_reg, fwsm = er32(FWSM);
 245         s32 ret_val;
 246
 247         /* Gate automatic PHY configuration by hardware on managed and
 248          * non-managed 82579 and newer adapters.
 249          */
 250         e1000_gate_hw_phy_config_ich8lan(hw, true);
 251
 252         ret_val = hw->phy.ops.acquire(hw);
 253         if (ret_val) {
 254                 e_dbg("Failed to initialize PHY flow\n");
 255                 goto out;
 256         }
 257
 258         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 259          * inaccessible and resetting the PHY is not blocked, toggle the
 260          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 261          */
 262         switch (hw->mac.type) {
 263         case e1000_pch_lpt:
 264                 if (e1000_phy_is_accessible_pchlan(hw))
 265                         break;
 266
 267                 /* Before toggling LANPHYPC, see if PHY is accessible by
 268                  * forcing MAC to SMBus mode first.
 269                  */
 270                 mac_reg = er32(CTRL_EXT);
 271                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 272                 ew32(CTRL_EXT, mac_reg);
 273
 274                 /* Wait 50 milliseconds for MAC to finish any retries
 275                  * that it might be trying to perform from previous
 276                  * attempts to acknowledge any phy read requests.
 277                  */
 278                 msleep(50);
 279
 280                 /* fall-through */
 281         case e1000_pch2lan:
 282                 if (e1000_phy_is_accessible_pchlan(hw))
 283                         break;
 284
 285                 /* fall-through */
 286         case e1000_pchlan:
 287                 if ((hw->mac.type == e1000_pchlan) &&
 288                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 289                         break;
 290
 291                 if (hw->phy.ops.check_reset_block(hw)) {
 292                         e_dbg("Required LANPHYPC toggle blocked by ME\n");
 293                         ret_val = -E1000_ERR_PHY;
 294                         break;
 295                 }
 296
 297                 e_dbg("Toggling LANPHYPC\n");
 298
 299                 /* Set Phy Config Counter to 50msec */
 300                 mac_reg = er32(FEXTNVM3);
 301                 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 302                 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 303                 ew32(FEXTNVM3, mac_reg);
 304
 305                 /* Toggle LANPHYPC Value bit */
 306                 mac_reg = er32(CTRL);
 307                 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 308                 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 309                 ew32(CTRL, mac_reg);
 310                 e1e_flush();
 311                 usleep_range(10, 20);
 312                 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 313                 ew32(CTRL, mac_reg);
 314                 e1e_flush();
 315                 if (hw->mac.type < e1000_pch_lpt) {
 316                         msleep(50);
 317                 } else {
 318                         u16 count = 20;
 319                         do {
 320                                 usleep_range(5000, 10000);
 321                         } while (!(er32(CTRL_EXT) &
 322                                    E1000_CTRL_EXT_LPCD) && count--);
 323                         usleep_range(30000, 60000);
 324                         if (e1000_phy_is_accessible_pchlan(hw))
 325                                 break;
 326
 327                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 328                          * so ensure that the MAC is also out of SMBus mode
 329                          */
 330                         mac_reg = er32(CTRL_EXT);
 331                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 332                         ew32(CTRL_EXT, mac_reg);
 333
 334                         if (e1000_phy_is_accessible_pchlan(hw))
 335                                 break;
 336
 337                         ret_val = -E1000_ERR_PHY;
 338                 }
 339                 break;
 340         default:
 341                 break;
 342         }
 343
 344         hw->phy.ops.release(hw);
 345         if (!ret_val) {
 346
 347                 /* Check to see if able to reset PHY.  Print error if not */
 348                 if (hw->phy.ops.check_reset_block(hw)) {
 349                         e_err("Reset blocked by ME\n");
 350                         goto out;
 351                 }
 352
 353                 /* Reset the PHY before any access to it.  Doing so, ensures
 354                  * that the PHY is in a known good state before we read/write
 355                  * PHY registers.  The generic reset is sufficient here,
 356                  * because we haven't determined the PHY type yet.
 357                  */
 358                 ret_val = e1000e_phy_hw_reset_generic(hw);
 359                 if (ret_val)
 360                         goto out;
 361
 362                 /* On a successful reset, possibly need to wait for the PHY
 363                  * to quiesce to an accessible state before returning control
 364                  * to the calling function.  If the PHY does not quiesce, then
 365                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 366                  *  the PHY is in.
 367                  */
 368                 ret_val = hw->phy.ops.check_reset_block(hw);
 369                 if (ret_val)
 370                         e_err("ME blocked access to PHY after reset\n");
 371         }
 372
 373 out:
 374         /* Ungate automatic PHY configuration on non-managed 82579 */
 375         if ((hw->mac.type == e1000_pch2lan) &&
 376             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 377                 usleep_range(10000, 20000);
 378                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 379         }
 380
 381         return ret_val;
 382 }
 383
 384 /**
 385  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 386  *  @hw: pointer to the HW structure
 387  *
 388  *  Initialize family-specific PHY parameters and function pointers.
 389  **/
 390 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 391 {
 392         struct e1000_phy_info *phy = &hw->phy;
 393         s32 ret_val;
 394
 395         phy->addr = 1;
 396         phy->reset_delay_us = 100;
 397
 398         phy->ops.set_page = e1000_set_page_igp;
 399         phy->ops.read_reg = e1000_read_phy_reg_hv;
 400         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 401         phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
 402         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 403         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 404         phy->ops.write_reg = e1000_write_phy_reg_hv;
 405         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 406         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 407         phy->ops.power_up = e1000_power_up_phy_copper;
 408         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 409         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 410
 411         phy->id = e1000_phy_unknown;
 412
 413         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 414         if (ret_val)
 415                 return ret_val;
 416
 417         if (phy->id == e1000_phy_unknown)
 418                 switch (hw->mac.type) {
 419                 default:
 420                         ret_val = e1000e_get_phy_id(hw);
 421                         if (ret_val)
 422                                 return ret_val;
 423                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 424                                 break;
 425                         /* fall-through */
 426                 case e1000_pch2lan:
 427                 case e1000_pch_lpt:
 428                         /* In case the PHY needs to be in mdio slow mode,
 429                          * set slow mode and try to get the PHY id again.
 430                          */
 431                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 432                         if (ret_val)
 433                                 return ret_val;
 434                         ret_val = e1000e_get_phy_id(hw);
 435                         if (ret_val)
 436                                 return ret_val;
 437                         break;
 438                 }
 439         phy->type = e1000e_get_phy_type_from_id(phy->id);
 440
 441         switch (phy->type) {
 442         case e1000_phy_82577:
 443         case e1000_phy_82579:
 444         case e1000_phy_i217:
 445                 phy->ops.check_polarity = e1000_check_polarity_82577;
 446                 phy->ops.force_speed_duplex =
 447                     e1000_phy_force_speed_duplex_82577;
 448                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 449                 phy->ops.get_info = e1000_get_phy_info_82577;
 450                 phy->ops.commit = e1000e_phy_sw_reset;
 451                 break;
 452         case e1000_phy_82578:
 453                 phy->ops.check_polarity = e1000_check_polarity_m88;
 454                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 455                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 456                 phy->ops.get_info = e1000e_get_phy_info_m88;
 457                 break;
 458         default:
 459                 ret_val = -E1000_ERR_PHY;
 460                 break;
 461         }
 462
 463         return ret_val;
 464 }
 465
 466 /**
 467  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 468  *  @hw: pointer to the HW structure
 469  *
 470  *  Initialize family-specific PHY parameters and function pointers.
 471  **/
 472 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 473 {
 474         struct e1000_phy_info *phy = &hw->phy;
 475         s32 ret_val;
 476         u16 i = 0;
 477
 478         phy->addr = 1;
 479         phy->reset_delay_us = 100;
 480
 481         phy->ops.power_up = e1000_power_up_phy_copper;
 482         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 483
 484         /* We may need to do this twice - once for IGP and if that fails,
 485          * we'll set BM func pointers and try again
 486          */
 487         ret_val = e1000e_determine_phy_address(hw);
 488         if (ret_val) {
 489                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 490                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 491                 ret_val = e1000e_determine_phy_address(hw);
 492                 if (ret_val) {
 493                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 494                         return ret_val;
 495                 }
 496         }
 497
 498         phy->id = 0;
 499         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 500                (i++ < 100)) {
 501                 usleep_range(1000, 2000);
 502                 ret_val = e1000e_get_phy_id(hw);
 503                 if (ret_val)
 504                         return ret_val;
 505         }
 506
 507         /* Verify phy id */
 508         switch (phy->id) {
 509         case IGP03E1000_E_PHY_ID:
 510                 phy->type = e1000_phy_igp_3;
 511                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 512                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 513                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 514                 phy->ops.get_info = e1000e_get_phy_info_igp;
 515                 phy->ops.check_polarity = e1000_check_polarity_igp;
 516                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 517                 break;
 518         case IFE_E_PHY_ID:
 519         case IFE_PLUS_E_PHY_ID:
 520         case IFE_C_E_PHY_ID:
 521                 phy->type = e1000_phy_ife;
 522                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 523                 phy->ops.get_info = e1000_get_phy_info_ife;
 524                 phy->ops.check_polarity = e1000_check_polarity_ife;
 525                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 526                 break;
 527         case BME1000_E_PHY_ID:
 528                 phy->type = e1000_phy_bm;
 529                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 530                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 531                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 532                 phy->ops.commit = e1000e_phy_sw_reset;
 533                 phy->ops.get_info = e1000e_get_phy_info_m88;
 534                 phy->ops.check_polarity = e1000_check_polarity_m88;
 535                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 536                 break;
 537         default:
 538                 return -E1000_ERR_PHY;
 539                 break;
 540         }
 541
 542         return 0;
 543 }
 544
 545 /**
 546  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 547  *  @hw: pointer to the HW structure
 548  *
 549  *  Initialize family-specific NVM parameters and function
 550  *  pointers.
 551  **/
 552 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 553 {
 554         struct e1000_nvm_info *nvm = &hw->nvm;
 555         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 556         u32 gfpreg, sector_base_addr, sector_end_addr;
 557         u16 i;
 558
 559         /* Can't read flash registers if the register set isn't mapped. */
 560         if (!hw->flash_address) {
 561                 e_dbg("ERROR: Flash registers not mapped\n");
 562                 return -E1000_ERR_CONFIG;
 563         }
 564
 565         nvm->type = e1000_nvm_flash_sw;
 566
 567         gfpreg = er32flash(ICH_FLASH_GFPREG);
 568
 569         /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 570          * Add 1 to sector_end_addr since this sector is included in
 571          * the overall size.
 572          */
 573         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 574         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 575
 576         /* flash_base_addr is byte-aligned */
 577         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 578
 579         /* find total size of the NVM, then cut in half since the total
 580          * size represents two separate NVM banks.
 581          */
 582         nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 583                                 << FLASH_SECTOR_ADDR_SHIFT);
 584         nvm->flash_bank_size /= 2;
 585         /* Adjust to word count */
 586         nvm->flash_bank_size /= sizeof(u16);
 587
 588         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 589
 590         /* Clear shadow ram */
 591         for (i = 0; i < nvm->word_size; i++) {
 592                 dev_spec->shadow_ram[i].modified = false;
 593                 dev_spec->shadow_ram[i].value = 0xFFFF;
 594         }
 595
 596         return 0;
 597 }
 598
 599 /**
 600  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 601  *  @hw: pointer to the HW structure
 602  *
 603  *  Initialize family-specific MAC parameters and function
 604  *  pointers.
 605  **/
 606 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 607 {
 608         struct e1000_mac_info *mac = &hw->mac;
 609
 610         /* Set media type function pointer */
 611         hw->phy.media_type = e1000_media_type_copper;
 612
 613         /* Set mta register count */
 614         mac->mta_reg_count = 32;
 615         /* Set rar entry count */
 616         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 617         if (mac->type == e1000_ich8lan)
 618                 mac->rar_entry_count--;
 619         /* FWSM register */
 620         mac->has_fwsm = true;
 621         /* ARC subsystem not supported */
 622         mac->arc_subsystem_valid = false;
 623         /* Adaptive IFS supported */
 624         mac->adaptive_ifs = true;
 625
 626         /* LED and other operations */
 627         switch (mac->type) {
 628         case e1000_ich8lan:
 629         case e1000_ich9lan:
 630         case e1000_ich10lan:
 631                 /* check management mode */
 632                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 633                 /* ID LED init */
 634                 mac->ops.id_led_init = e1000e_id_led_init_generic;
 635                 /* blink LED */
 636                 mac->ops.blink_led = e1000e_blink_led_generic;
 637                 /* setup LED */
 638                 mac->ops.setup_led = e1000e_setup_led_generic;
 639                 /* cleanup LED */
 640                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 641                 /* turn on/off LED */
 642                 mac->ops.led_on = e1000_led_on_ich8lan;
 643                 mac->ops.led_off = e1000_led_off_ich8lan;
 644                 break;
 645         case e1000_pch2lan:
 646                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 647                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 648                 /* fall-through */
 649         case e1000_pch_lpt:
 650         case e1000_pchlan:
 651                 /* check management mode */
 652                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 653                 /* ID LED init */
 654                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 655                 /* setup LED */
 656                 mac->ops.setup_led = e1000_setup_led_pchlan;
 657                 /* cleanup LED */
 658                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 659                 /* turn on/off LED */
 660                 mac->ops.led_on = e1000_led_on_pchlan;
 661                 mac->ops.led_off = e1000_led_off_pchlan;
 662                 break;
 663         default:
 664                 break;
 665         }
 666
 667         if (mac->type == e1000_pch_lpt) {
 668                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 669                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 670                 mac->ops.setup_physical_interface =
 671                     e1000_setup_copper_link_pch_lpt;
 672         }
 673
 674         /* Enable PCS Lock-loss workaround for ICH8 */
 675         if (mac->type == e1000_ich8lan)
 676                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 677
 678         return 0;
 679 }
 680
 681 /**
 682  *  __e1000_access_emi_reg_locked - Read/write EMI register
 683  *  @hw: pointer to the HW structure
 684  *  @addr: EMI address to program
 685  *  @data: pointer to value to read/write from/to the EMI address
 686  *  @read: boolean flag to indicate read or write
 687  *
 688  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 689  **/
 690 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 691                                          u16 *data, bool read)
 692 {
 693         s32 ret_val;
 694
 695         ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
 696         if (ret_val)
 697                 return ret_val;
 698
 699         if (read)
 700                 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
 701         else
 702                 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
 703
 704         return ret_val;
 705 }
 706
 707 /**
 708  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 709  *  @hw: pointer to the HW structure
 710  *  @addr: EMI address to program
 711  *  @data: value to be read from the EMI address
 712  *
 713  *  Assumes the SW/FW/HW Semaphore is already acquired.
 714  **/
 715 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 716 {
 717         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 718 }
 719
 720 /**
 721  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 722  *  @hw: pointer to the HW structure
 723  *  @addr: EMI address to program
 724  *  @data: value to be written to the EMI address
 725  *
 726  *  Assumes the SW/FW/HW Semaphore is already acquired.
 727  **/
 728 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 729 {
 730         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 731 }
 732
 733 /**
 734  *  e1000_set_eee_pchlan - Enable/disable EEE support
 735  *  @hw: pointer to the HW structure
 736  *
 737  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 738  *  the link and the EEE capabilities of the link partner.  The LPI Control
 739  *  register bits will remain set only if/when link is up.
 740  *
 741  *  EEE LPI must not be asserted earlier than one second after link is up.
 742  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 743  *  can be link issues with some switches.  Other devices can have EEE LPI
 744  *  enabled immediately upon link up since they have a timer in hardware which
 745  *  prevents LPI from being asserted too early.
 746  **/
 747 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 748 {
 749         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 750         s32 ret_val;
 751         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 752
 753         switch (hw->phy.type) {
 754         case e1000_phy_82579:
 755                 lpa = I82579_EEE_LP_ABILITY;
 756                 pcs_status = I82579_EEE_PCS_STATUS;
 757                 adv_addr = I82579_EEE_ADVERTISEMENT;
 758                 break;
 759         case e1000_phy_i217:
 760                 lpa = I217_EEE_LP_ABILITY;
 761                 pcs_status = I217_EEE_PCS_STATUS;
 762                 adv_addr = I217_EEE_ADVERTISEMENT;
 763                 break;
 764         default:
 765                 return 0;
 766         }
 767
 768         ret_val = hw->phy.ops.acquire(hw);
 769         if (ret_val)
 770                 return ret_val;
 771
 772         ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 773         if (ret_val)
 774                 goto release;
 775
 776         /* Clear bits that enable EEE in various speeds */
 777         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 778
 779         /* Enable EEE if not disabled by user */
 780         if (!dev_spec->eee_disable) {
 781                 /* Save off link partner's EEE ability */
 782                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 783                                                     &dev_spec->eee_lp_ability);
 784                 if (ret_val)
 785                         goto release;
 786
 787                 /* Read EEE advertisement */
 788                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 789                 if (ret_val)
 790                         goto release;
 791
 792                 /* Enable EEE only for speeds in which the link partner is
 793                  * EEE capable and for which we advertise EEE.
 794                  */
 795                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 796                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 797
 798                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 799                         e1e_rphy_locked(hw, MII_LPA, &data);
 800                         if (data & LPA_100FULL)
 801                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 802                         else
 803                                 /* EEE is not supported in 100Half, so ignore
 804                                  * partner's EEE in 100 ability if full-duplex
 805                                  * is not advertised.
 806                                  */
 807                                 dev_spec->eee_lp_ability &=
 808                                     ~I82579_EEE_100_SUPPORTED;
 809                 }
 810         }
 811
 812         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 813         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 814         if (ret_val)
 815                 goto release;
 816
 817         ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 818 release:
 819         hw->phy.ops.release(hw);
 820
 821         return ret_val;
 822 }
 823
 824 /**
 825  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 826  *  @hw:   pointer to the HW structure
 827  *  @link: link up bool flag
 828  *
 829  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 830  *  preventing further DMA write requests.  Workaround the issue by disabling
 831  *  the de-assertion of the clock request when in 1Gpbs mode.
 832  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 833  *  speeds in order to avoid Tx hangs.
 834  **/
 835 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 836 {
 837         u32 fextnvm6 = er32(FEXTNVM6);
 838         u32 status = er32(STATUS);
 839         s32 ret_val = 0;
 840         u16 reg;
 841
 842         if (link && (status & E1000_STATUS_SPEED_1000)) {
 843                 ret_val = hw->phy.ops.acquire(hw);
 844                 if (ret_val)
 845                         return ret_val;
 846
 847                 ret_val =
 848                     e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 849                                                 &reg);
 850                 if (ret_val)
 851                         goto release;
 852
 853                 ret_val =
 854                     e1000e_write_kmrn_reg_locked(hw,
 855                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 856                                                  reg &
 857                                                  ~E1000_KMRNCTRLSTA_K1_ENABLE);
 858                 if (ret_val)
 859                         goto release;
 860
 861                 usleep_range(10, 20);
 862
 863                 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
 864
 865                 ret_val =
 866                     e1000e_write_kmrn_reg_locked(hw,
 867                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 868                                                  reg);
 869 release:
 870                 hw->phy.ops.release(hw);
 871         } else {
 872                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
 873                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
 874
 875                 if (!link || ((status & E1000_STATUS_SPEED_100) &&
 876                               (status & E1000_STATUS_FD)))
 877                         goto update_fextnvm6;
 878
 879                 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
 880                 if (ret_val)
 881                         return ret_val;
 882
 883                 /* Clear link status transmit timeout */
 884                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
 885
 886                 if (status & E1000_STATUS_SPEED_100) {
 887                         /* Set inband Tx timeout to 5x10us for 100Half */
 888                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 889
 890                         /* Do not extend the K1 entry latency for 100Half */
 891                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 892                 } else {
 893                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
 894                         reg |= 50 <<
 895                             I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 896
 897                         /* Extend the K1 entry latency for 10 Mbps */
 898                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 899                 }
 900
 901                 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
 902                 if (ret_val)
 903                         return ret_val;
 904
 905 update_fextnvm6:
 906                 ew32(FEXTNVM6, fextnvm6);
 907         }
 908
 909         return ret_val;
 910 }
 911
 912 /**
 913  *  e1000_platform_pm_pch_lpt - Set platform power management values
 914  *  @hw: pointer to the HW structure
 915  *  @link: bool indicating link status
 916  *
 917  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
 918  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
 919  *  when link is up (which must not exceed the maximum latency supported
 920  *  by the platform), otherwise specify there is no LTR requirement.
 921  *  Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
 922  *  latencies in the LTR Extended Capability Structure in the PCIe Extended
 923  *  Capability register set, on this device LTR is set by writing the
 924  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
 925  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
 926  *  message to the PMC.
 927  **/
 928 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
 929 {
 930         u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
 931             link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
 932         u16 lat_enc = 0;        /* latency encoded */
 933
 934         if (link) {
 935                 u16 speed, duplex, scale = 0;
 936                 u16 max_snoop, max_nosnoop;
 937                 u16 max_ltr_enc;        /* max LTR latency encoded */
 938                 s64 lat_ns;     /* latency (ns) */
 939                 s64 value;
 940                 u32 rxa;
 941
 942                 if (!hw->adapter->max_frame_size) {
 943                         e_dbg("max_frame_size not set.\n");
 944                         return -E1000_ERR_CONFIG;
 945                 }
 946
 947                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
 948                 if (!speed) {
 949                         e_dbg("Speed not set.\n");
 950                         return -E1000_ERR_CONFIG;
 951                 }
 952
 953                 /* Rx Packet Buffer Allocation size (KB) */
 954                 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
 955
 956                 /* Determine the maximum latency tolerated by the device.
 957                  *
 958                  * Per the PCIe spec, the tolerated latencies are encoded as
 959                  * a 3-bit encoded scale (only 0-5 are valid) multiplied by
 960                  * a 10-bit value (0-1023) to provide a range from 1 ns to
 961                  * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
 962                  * 1=2^5ns, 2=2^10ns,...5=2^25ns.
 963                  */
 964                 lat_ns = ((s64)rxa * 1024 -
 965                           (2 * (s64)hw->adapter->max_frame_size)) * 8 * 1000;
 966                 if (lat_ns < 0)
 967                         lat_ns = 0;
 968                 else
 969                         do_div(lat_ns, speed);
 970
 971                 value = lat_ns;
 972                 while (value > PCI_LTR_VALUE_MASK) {
 973                         scale++;
 974                         value = DIV_ROUND_UP(value, (1 << 5));
 975                 }
 976                 if (scale > E1000_LTRV_SCALE_MAX) {
 977                         e_dbg("Invalid LTR latency scale %d\n", scale);
 978                         return -E1000_ERR_CONFIG;
 979                 }
 980                 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
 981
 982                 /* Determine the maximum latency tolerated by the platform */
 983                 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
 984                                      &max_snoop);
 985                 pci_read_config_word(hw->adapter->pdev,
 986                                      E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
 987                 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
 988
 989                 if (lat_enc > max_ltr_enc)
 990                         lat_enc = max_ltr_enc;
 991         }
 992
 993         /* Set Snoop and No-Snoop latencies the same */
 994         reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
 995         ew32(LTRV, reg);
 996
 997         return 0;
 998 }
 999
1000 /**
1001  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1002  *  @hw: pointer to the HW structure
1003  *
1004  *  Checks to see of the link status of the hardware has changed.  If a
1005  *  change in link status has been detected, then we read the PHY registers
1006  *  to get the current speed/duplex if link exists.
1007  **/
1008 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1009 {
1010         struct e1000_mac_info *mac = &hw->mac;
1011         s32 ret_val;
1012         bool link;
1013         u16 phy_reg;
1014
1015         /* We only want to go out to the PHY registers to see if Auto-Neg
1016          * has completed and/or if our link status has changed.  The
1017          * get_link_status flag is set upon receiving a Link Status
1018          * Change or Rx Sequence Error interrupt.
1019          */
1020         if (!mac->get_link_status)
1021                 return 0;
1022
1023         /* First we want to see if the MII Status Register reports
1024          * link.  If so, then we want to get the current speed/duplex
1025          * of the PHY.
1026          */
1027         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1028         if (ret_val)
1029                 return ret_val;
1030
1031         if (hw->mac.type == e1000_pchlan) {
1032                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1033                 if (ret_val)
1034                         return ret_val;
1035         }
1036
1037         /* When connected at 10Mbps half-duplex, 82579 parts are excessively
1038          * aggressive resulting in many collisions. To avoid this, increase
1039          * the IPG and reduce Rx latency in the PHY.
1040          */
1041         if ((hw->mac.type == e1000_pch2lan) && link) {
1042                 u32 reg;
1043                 reg = er32(STATUS);
1044                 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1045                         reg = er32(TIPG);
1046                         reg &= ~E1000_TIPG_IPGT_MASK;
1047                         reg |= 0xFF;
1048                         ew32(TIPG, reg);
1049
1050                         /* Reduce Rx latency in analog PHY */
1051                         ret_val = hw->phy.ops.acquire(hw);
1052                         if (ret_val)
1053                                 return ret_val;
1054
1055                         ret_val =
1056                             e1000_write_emi_reg_locked(hw, I82579_RX_CONFIG, 0);
1057
1058                         hw->phy.ops.release(hw);
1059
1060                         if (ret_val)
1061                                 return ret_val;
1062                 }
1063         }
1064
1065         /* Work-around I218 hang issue */
1066         if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1067             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1068             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1069             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1070                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1071                 if (ret_val)
1072                         return ret_val;
1073         }
1074
1075         if (hw->mac.type == e1000_pch_lpt) {
1076                 /* Set platform power management values for
1077                  * Latency Tolerance Reporting (LTR)
1078                  */
1079                 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1080                 if (ret_val)
1081                         return ret_val;
1082         }
1083
1084         /* Clear link partner's EEE ability */
1085         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1086
1087         if (!link)
1088                 return 0;       /* No link detected */
1089
1090         mac->get_link_status = false;
1091
1092         switch (hw->mac.type) {
1093         case e1000_pch2lan:
1094                 ret_val = e1000_k1_workaround_lv(hw);
1095                 if (ret_val)
1096                         return ret_val;
1097                 /* fall-thru */
1098         case e1000_pchlan:
1099                 if (hw->phy.type == e1000_phy_82578) {
1100                         ret_val = e1000_link_stall_workaround_hv(hw);
1101                         if (ret_val)
1102                                 return ret_val;
1103                 }
1104
1105                 /* Workaround for PCHx parts in half-duplex:
1106                  * Set the number of preambles removed from the packet
1107                  * when it is passed from the PHY to the MAC to prevent
1108                  * the MAC from misinterpreting the packet type.
1109                  */
1110                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1111                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1112
1113                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1114                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1115
1116                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1117                 break;
1118         default:
1119                 break;
1120         }
1121
1122         /* Check if there was DownShift, must be checked
1123          * immediately after link-up
1124          */
1125         e1000e_check_downshift(hw);
1126
1127         /* Enable/Disable EEE after link up */
1128         if (hw->phy.type > e1000_phy_82579) {
1129                 ret_val = e1000_set_eee_pchlan(hw);
1130                 if (ret_val)
1131                         return ret_val;
1132         }
1133
1134         /* If we are forcing speed/duplex, then we simply return since
1135          * we have already determined whether we have link or not.
1136          */
1137         if (!mac->autoneg)
1138                 return -E1000_ERR_CONFIG;
1139
1140         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1141          * of MAC speed/duplex configuration.  So we only need to
1142          * configure Collision Distance in the MAC.
1143          */
1144         mac->ops.config_collision_dist(hw);
1145
1146         /* Configure Flow Control now that Auto-Neg has completed.
1147          * First, we need to restore the desired flow control
1148          * settings because we may have had to re-autoneg with a
1149          * different link partner.
1150          */
1151         ret_val = e1000e_config_fc_after_link_up(hw);
1152         if (ret_val)
1153                 e_dbg("Error configuring flow control\n");
1154
1155         return ret_val;
1156 }
1157
1158 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1159 {
1160         struct e1000_hw *hw = &adapter->hw;
1161         s32 rc;
1162
1163         rc = e1000_init_mac_params_ich8lan(hw);
1164         if (rc)
1165                 return rc;
1166
1167         rc = e1000_init_nvm_params_ich8lan(hw);
1168         if (rc)
1169                 return rc;
1170
1171         switch (hw->mac.type) {
1172         case e1000_ich8lan:
1173         case e1000_ich9lan:
1174         case e1000_ich10lan:
1175                 rc = e1000_init_phy_params_ich8lan(hw);
1176                 break;
1177         case e1000_pchlan:
1178         case e1000_pch2lan:
1179         case e1000_pch_lpt:
1180                 rc = e1000_init_phy_params_pchlan(hw);
1181                 break;
1182         default:
1183                 break;
1184         }
1185         if (rc)
1186                 return rc;
1187
1188         /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1189          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1190          */
1191         if ((adapter->hw.phy.type == e1000_phy_ife) ||
1192             ((adapter->hw.mac.type >= e1000_pch2lan) &&
1193              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1194                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1195                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
1196
1197                 hw->mac.ops.blink_led = NULL;
1198         }
1199
1200         if ((adapter->hw.mac.type == e1000_ich8lan) &&
1201             (adapter->hw.phy.type != e1000_phy_ife))
1202                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1203
1204         /* Enable workaround for 82579 w/ ME enabled */
1205         if ((adapter->hw.mac.type == e1000_pch2lan) &&
1206             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1207                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1208
1209         return 0;
1210 }
1211
1212 static DEFINE_MUTEX(nvm_mutex);
1213
1214 /**
1215  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1216  *  @hw: pointer to the HW structure
1217  *
1218  *  Acquires the mutex for performing NVM operations.
1219  **/
1220 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1221 {
1222         mutex_lock(&nvm_mutex);
1223
1224         return 0;
1225 }
1226
1227 /**
1228  *  e1000_release_nvm_ich8lan - Release NVM mutex
1229  *  @hw: pointer to the HW structure
1230  *
1231  *  Releases the mutex used while performing NVM operations.
1232  **/
1233 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1234 {
1235         mutex_unlock(&nvm_mutex);
1236 }
1237
1238 /**
1239  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1240  *  @hw: pointer to the HW structure
1241  *
1242  *  Acquires the software control flag for performing PHY and select
1243  *  MAC CSR accesses.
1244  **/
1245 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1246 {
1247         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1248         s32 ret_val = 0;
1249
1250         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1251                              &hw->adapter->state)) {
1252                 e_dbg("contention for Phy access\n");
1253                 return -E1000_ERR_PHY;
1254         }
1255
1256         while (timeout) {
1257                 extcnf_ctrl = er32(EXTCNF_CTRL);
1258                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1259                         break;
1260
1261                 mdelay(1);
1262                 timeout--;
1263         }
1264
1265         if (!timeout) {
1266                 e_dbg("SW has already locked the resource.\n");
1267                 ret_val = -E1000_ERR_CONFIG;
1268                 goto out;
1269         }
1270
1271         timeout = SW_FLAG_TIMEOUT;
1272
1273         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1274         ew32(EXTCNF_CTRL, extcnf_ctrl);
1275
1276         while (timeout) {
1277                 extcnf_ctrl = er32(EXTCNF_CTRL);
1278                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1279                         break;
1280
1281                 mdelay(1);
1282                 timeout--;
1283         }
1284
1285         if (!timeout) {
1286                 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1287                       er32(FWSM), extcnf_ctrl);
1288                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1289                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1290                 ret_val = -E1000_ERR_CONFIG;
1291                 goto out;
1292         }
1293
1294 out:
1295         if (ret_val)
1296                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1297
1298         return ret_val;
1299 }
1300
1301 /**
1302  *  e1000_release_swflag_ich8lan - Release software control flag
1303  *  @hw: pointer to the HW structure
1304  *
1305  *  Releases the software control flag for performing PHY and select
1306  *  MAC CSR accesses.
1307  **/
1308 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1309 {
1310         u32 extcnf_ctrl;
1311
1312         extcnf_ctrl = er32(EXTCNF_CTRL);
1313
1314         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1315                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1316                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1317         } else {
1318                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1319         }
1320
1321         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1322 }
1323
1324 /**
1325  *  e1000_check_mng_mode_ich8lan - Checks management mode
1326  *  @hw: pointer to the HW structure
1327  *
1328  *  This checks if the adapter has any manageability enabled.
1329  *  This is a function pointer entry point only called by read/write
1330  *  routines for the PHY and NVM parts.
1331  **/
1332 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1333 {
1334         u32 fwsm;
1335
1336         fwsm = er32(FWSM);
1337         return ((fwsm & E1000_ICH_FWSM_FW_VALID) &&
1338                 ((fwsm & E1000_FWSM_MODE_MASK) ==
1339                  (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)));
1340 }
1341
1342 /**
1343  *  e1000_check_mng_mode_pchlan - Checks management mode
1344  *  @hw: pointer to the HW structure
1345  *
1346  *  This checks if the adapter has iAMT enabled.
1347  *  This is a function pointer entry point only called by read/write
1348  *  routines for the PHY and NVM parts.
1349  **/
1350 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1351 {
1352         u32 fwsm;
1353
1354         fwsm = er32(FWSM);
1355         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1356             (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1357 }
1358
1359 /**
1360  *  e1000_rar_set_pch2lan - Set receive address register
1361  *  @hw: pointer to the HW structure
1362  *  @addr: pointer to the receive address
1363  *  @index: receive address array register
1364  *
1365  *  Sets the receive address array register at index to the address passed
1366  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1367  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1368  *  Use SHRA[0-3] in place of those reserved for ME.
1369  **/
1370 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1371 {
1372         u32 rar_low, rar_high;
1373
1374         /* HW expects these in little endian so we reverse the byte order
1375          * from network order (big endian) to little endian
1376          */
1377         rar_low = ((u32)addr[0] |
1378                    ((u32)addr[1] << 8) |
1379                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1380
1381         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1382
1383         /* If MAC address zero, no need to set the AV bit */
1384         if (rar_low || rar_high)
1385                 rar_high |= E1000_RAH_AV;
1386
1387         if (index == 0) {
1388                 ew32(RAL(index), rar_low);
1389                 e1e_flush();
1390                 ew32(RAH(index), rar_high);
1391                 e1e_flush();
1392                 return;
1393         }
1394
1395         /* RAR[1-6] are owned by manageability.  Skip those and program the
1396          * next address into the SHRA register array.
1397          */
1398         if (index < (u32)(hw->mac.rar_entry_count - 6)) {
1399                 s32 ret_val;
1400
1401                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1402                 if (ret_val)
1403                         goto out;
1404
1405                 ew32(SHRAL(index - 1), rar_low);
1406                 e1e_flush();
1407                 ew32(SHRAH(index - 1), rar_high);
1408                 e1e_flush();
1409
1410                 e1000_release_swflag_ich8lan(hw);
1411
1412                 /* verify the register updates */
1413                 if ((er32(SHRAL(index - 1)) == rar_low) &&
1414                     (er32(SHRAH(index - 1)) == rar_high))
1415                         return;
1416
1417                 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1418                       (index - 1), er32(FWSM));
1419         }
1420
1421 out:
1422         e_dbg("Failed to write receive address at index %d\n", index);
1423 }
1424
1425 /**
1426  *  e1000_rar_set_pch_lpt - Set receive address registers
1427  *  @hw: pointer to the HW structure
1428  *  @addr: pointer to the receive address
1429  *  @index: receive address array register
1430  *
1431  *  Sets the receive address register array at index to the address passed
1432  *  in by addr. For LPT, RAR[0] is the base address register that is to
1433  *  contain the MAC address. SHRA[0-10] are the shared receive address
1434  *  registers that are shared between the Host and manageability engine (ME).
1435  **/
1436 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1437 {
1438         u32 rar_low, rar_high;
1439         u32 wlock_mac;
1440
1441         /* HW expects these in little endian so we reverse the byte order
1442          * from network order (big endian) to little endian
1443          */
1444         rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1445                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1446
1447         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1448
1449         /* If MAC address zero, no need to set the AV bit */
1450         if (rar_low || rar_high)
1451                 rar_high |= E1000_RAH_AV;
1452
1453         if (index == 0) {
1454                 ew32(RAL(index), rar_low);
1455                 e1e_flush();
1456                 ew32(RAH(index), rar_high);
1457                 e1e_flush();
1458                 return;
1459         }
1460
1461         /* The manageability engine (ME) can lock certain SHRAR registers that
1462          * it is using - those registers are unavailable for use.
1463          */
1464         if (index < hw->mac.rar_entry_count) {
1465                 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1466                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1467
1468                 /* Check if all SHRAR registers are locked */
1469                 if (wlock_mac == 1)
1470                         goto out;
1471
1472                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1473                         s32 ret_val;
1474
1475                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1476
1477                         if (ret_val)
1478                                 goto out;
1479
1480                         ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1481                         e1e_flush();
1482                         ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1483                         e1e_flush();
1484
1485                         e1000_release_swflag_ich8lan(hw);
1486
1487                         /* verify the register updates */
1488                         if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1489                             (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1490                                 return;
1491                 }
1492         }
1493
1494 out:
1495         e_dbg("Failed to write receive address at index %d\n", index);
1496 }
1497
1498 /**
1499  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1500  *  @hw: pointer to the HW structure
1501  *
1502  *  Checks if firmware is blocking the reset of the PHY.
1503  *  This is a function pointer entry point only called by
1504  *  reset routines.
1505  **/
1506 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1507 {
1508         bool blocked = false;
1509         int i = 0;
1510
1511         while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
1512                (i++ < 10))
1513                 usleep_range(10000, 20000);
1514         return blocked ? E1000_BLK_PHY_RESET : 0;
1515 }
1516
1517 /**
1518  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1519  *  @hw: pointer to the HW structure
1520  *
1521  *  Assumes semaphore already acquired.
1522  *
1523  **/
1524 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1525 {
1526         u16 phy_data;
1527         u32 strap = er32(STRAP);
1528         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1529             E1000_STRAP_SMT_FREQ_SHIFT;
1530         s32 ret_val;
1531
1532         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1533
1534         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1535         if (ret_val)
1536                 return ret_val;
1537
1538         phy_data &= ~HV_SMB_ADDR_MASK;
1539         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1540         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1541
1542         if (hw->phy.type == e1000_phy_i217) {
1543                 /* Restore SMBus frequency */
1544                 if (freq--) {
1545                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1546                         phy_data |= (freq & (1 << 0)) <<
1547                             HV_SMB_ADDR_FREQ_LOW_SHIFT;
1548                         phy_data |= (freq & (1 << 1)) <<
1549                             (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1550                 } else {
1551                         e_dbg("Unsupported SMB frequency in PHY\n");
1552                 }
1553         }
1554
1555         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1556 }
1557
1558 /**
1559  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1560  *  @hw:   pointer to the HW structure
1561  *
1562  *  SW should configure the LCD from the NVM extended configuration region
1563  *  as a workaround for certain parts.
1564  **/
1565 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1566 {
1567         struct e1000_phy_info *phy = &hw->phy;
1568         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1569         s32 ret_val = 0;
1570         u16 word_addr, reg_data, reg_addr, phy_page = 0;
1571
1572         /* Initialize the PHY from the NVM on ICH platforms.  This
1573          * is needed due to an issue where the NVM configuration is
1574          * not properly autoloaded after power transitions.
1575          * Therefore, after each PHY reset, we will load the
1576          * configuration data out of the NVM manually.
1577          */
1578         switch (hw->mac.type) {
1579         case e1000_ich8lan:
1580                 if (phy->type != e1000_phy_igp_3)
1581                         return ret_val;
1582
1583                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1584                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1585                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1586                         break;
1587                 }
1588                 /* Fall-thru */
1589         case e1000_pchlan:
1590         case e1000_pch2lan:
1591         case e1000_pch_lpt:
1592                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1593                 break;
1594         default:
1595                 return ret_val;
1596         }
1597
1598         ret_val = hw->phy.ops.acquire(hw);
1599         if (ret_val)
1600                 return ret_val;
1601
1602         data = er32(FEXTNVM);
1603         if (!(data & sw_cfg_mask))
1604                 goto release;
1605
1606         /* Make sure HW does not configure LCD from PHY
1607          * extended configuration before SW configuration
1608          */
1609         data = er32(EXTCNF_CTRL);
1610         if ((hw->mac.type < e1000_pch2lan) &&
1611             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
1612                 goto release;
1613
1614         cnf_size = er32(EXTCNF_SIZE);
1615         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1616         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1617         if (!cnf_size)
1618                 goto release;
1619
1620         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1621         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1622
1623         if (((hw->mac.type == e1000_pchlan) &&
1624              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
1625             (hw->mac.type > e1000_pchlan)) {
1626                 /* HW configures the SMBus address and LEDs when the
1627                  * OEM and LCD Write Enable bits are set in the NVM.
1628                  * When both NVM bits are cleared, SW will configure
1629                  * them instead.
1630                  */
1631                 ret_val = e1000_write_smbus_addr(hw);
1632                 if (ret_val)
1633                         goto release;
1634
1635                 data = er32(LEDCTL);
1636                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1637                                                         (u16)data);
1638                 if (ret_val)
1639                         goto release;
1640         }
1641
1642         /* Configure LCD from extended configuration region. */
1643
1644         /* cnf_base_addr is in DWORD */
1645         word_addr = (u16)(cnf_base_addr << 1);
1646
1647         for (i = 0; i < cnf_size; i++) {
1648                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
1649                 if (ret_val)
1650                         goto release;
1651
1652                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1653                                          1, &reg_addr);
1654                 if (ret_val)
1655                         goto release;
1656
1657                 /* Save off the PHY page for future writes. */
1658                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1659                         phy_page = reg_data;
1660                         continue;
1661                 }
1662
1663                 reg_addr &= PHY_REG_MASK;
1664                 reg_addr |= phy_page;
1665
1666                 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
1667                 if (ret_val)
1668                         goto release;
1669         }
1670
1671 release:
1672         hw->phy.ops.release(hw);
1673         return ret_val;
1674 }
1675
1676 /**
1677  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1678  *  @hw:   pointer to the HW structure
1679  *  @link: link up bool flag
1680  *
1681  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1682  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1683  *  If link is down, the function will restore the default K1 setting located
1684  *  in the NVM.
1685  **/
1686 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1687 {
1688         s32 ret_val = 0;
1689         u16 status_reg = 0;
1690         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1691
1692         if (hw->mac.type != e1000_pchlan)
1693                 return 0;
1694
1695         /* Wrap the whole flow with the sw flag */
1696         ret_val = hw->phy.ops.acquire(hw);
1697         if (ret_val)
1698                 return ret_val;
1699
1700         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1701         if (link) {
1702                 if (hw->phy.type == e1000_phy_82578) {
1703                         ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
1704                                                   &status_reg);
1705                         if (ret_val)
1706                                 goto release;
1707
1708                         status_reg &= (BM_CS_STATUS_LINK_UP |
1709                                        BM_CS_STATUS_RESOLVED |
1710                                        BM_CS_STATUS_SPEED_MASK);
1711
1712                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1713                                            BM_CS_STATUS_RESOLVED |
1714                                            BM_CS_STATUS_SPEED_1000))
1715                                 k1_enable = false;
1716                 }
1717
1718                 if (hw->phy.type == e1000_phy_82577) {
1719                         ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
1720                         if (ret_val)
1721                                 goto release;
1722
1723                         status_reg &= (HV_M_STATUS_LINK_UP |
1724                                        HV_M_STATUS_AUTONEG_COMPLETE |
1725                                        HV_M_STATUS_SPEED_MASK);
1726
1727                         if (status_reg == (HV_M_STATUS_LINK_UP |
1728                                            HV_M_STATUS_AUTONEG_COMPLETE |
1729                                            HV_M_STATUS_SPEED_1000))
1730                                 k1_enable = false;
1731                 }
1732
1733                 /* Link stall fix for link up */
1734                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
1735                 if (ret_val)
1736                         goto release;
1737
1738         } else {
1739                 /* Link stall fix for link down */
1740                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
1741                 if (ret_val)
1742                         goto release;
1743         }
1744
1745         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1746
1747 release:
1748         hw->phy.ops.release(hw);
1749
1750         return ret_val;
1751 }
1752
1753 /**
1754  *  e1000_configure_k1_ich8lan - Configure K1 power state
1755  *  @hw: pointer to the HW structure
1756  *  @enable: K1 state to configure
1757  *
1758  *  Configure the K1 power state based on the provided parameter.
1759  *  Assumes semaphore already acquired.
1760  *
1761  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1762  **/
1763 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1764 {
1765         s32 ret_val;
1766         u32 ctrl_reg = 0;
1767         u32 ctrl_ext = 0;
1768         u32 reg = 0;
1769         u16 kmrn_reg = 0;
1770
1771         ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1772                                               &kmrn_reg);
1773         if (ret_val)
1774                 return ret_val;
1775
1776         if (k1_enable)
1777                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1778         else
1779                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1780
1781         ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1782                                                kmrn_reg);
1783         if (ret_val)
1784                 return ret_val;
1785
1786         usleep_range(20, 40);
1787         ctrl_ext = er32(CTRL_EXT);
1788         ctrl_reg = er32(CTRL);
1789
1790         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1791         reg |= E1000_CTRL_FRCSPD;
1792         ew32(CTRL, reg);
1793
1794         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1795         e1e_flush();
1796         usleep_range(20, 40);
1797         ew32(CTRL, ctrl_reg);
1798         ew32(CTRL_EXT, ctrl_ext);
1799         e1e_flush();
1800         usleep_range(20, 40);
1801
1802         return 0;
1803 }
1804
1805 /**
1806  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1807  *  @hw:       pointer to the HW structure
1808  *  @d0_state: boolean if entering d0 or d3 device state
1809  *
1810  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1811  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1812  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1813  **/
1814 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1815 {
1816         s32 ret_val = 0;
1817         u32 mac_reg;
1818         u16 oem_reg;
1819
1820         if (hw->mac.type < e1000_pchlan)
1821                 return ret_val;
1822
1823         ret_val = hw->phy.ops.acquire(hw);
1824         if (ret_val)
1825                 return ret_val;
1826
1827         if (hw->mac.type == e1000_pchlan) {
1828                 mac_reg = er32(EXTCNF_CTRL);
1829                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1830                         goto release;
1831         }
1832
1833         mac_reg = er32(FEXTNVM);
1834         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1835                 goto release;
1836
1837         mac_reg = er32(PHY_CTRL);
1838
1839         ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
1840         if (ret_val)
1841                 goto release;
1842
1843         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1844
1845         if (d0_state) {
1846                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1847                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1848
1849                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1850                         oem_reg |= HV_OEM_BITS_LPLU;
1851         } else {
1852                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1853                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
1854                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1855
1856                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1857                                E1000_PHY_CTRL_NOND0A_LPLU))
1858                         oem_reg |= HV_OEM_BITS_LPLU;
1859         }
1860
1861         /* Set Restart auto-neg to activate the bits */
1862         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
1863             !hw->phy.ops.check_reset_block(hw))
1864                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1865
1866         ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
1867
1868 release:
1869         hw->phy.ops.release(hw);
1870
1871         return ret_val;
1872 }
1873
1874 /**
1875  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1876  *  @hw:   pointer to the HW structure
1877  **/
1878 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1879 {
1880         s32 ret_val;
1881         u16 data;
1882
1883         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1884         if (ret_val)
1885                 return ret_val;
1886
1887         data |= HV_KMRN_MDIO_SLOW;
1888
1889         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1890
1891         return ret_val;
1892 }
1893
1894 /**
1895  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1896  *  done after every PHY reset.
1897  **/
1898 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1899 {
1900         s32 ret_val = 0;
1901         u16 phy_data;
1902
1903         if (hw->mac.type != e1000_pchlan)
1904                 return 0;
1905
1906         /* Set MDIO slow mode before any other MDIO access */
1907         if (hw->phy.type == e1000_phy_82577) {
1908                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1909                 if (ret_val)
1910                         return ret_val;
1911         }
1912
1913         if (((hw->phy.type == e1000_phy_82577) &&
1914              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1915             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1916                 /* Disable generation of early preamble */
1917                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1918                 if (ret_val)
1919                         return ret_val;
1920
1921                 /* Preamble tuning for SSC */
1922                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
1923                 if (ret_val)
1924                         return ret_val;
1925         }
1926
1927         if (hw->phy.type == e1000_phy_82578) {
1928                 /* Return registers to default by doing a soft reset then
1929                  * writing 0x3140 to the control register.
1930                  */
1931                 if (hw->phy.revision < 2) {
1932                         e1000e_phy_sw_reset(hw);
1933                         ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
1934                 }
1935         }
1936
1937         /* Select page 0 */
1938         ret_val = hw->phy.ops.acquire(hw);
1939         if (ret_val)
1940                 return ret_val;
1941
1942         hw->phy.addr = 1;
1943         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1944         hw->phy.ops.release(hw);
1945         if (ret_val)
1946                 return ret_val;
1947
1948         /* Configure the K1 Si workaround during phy reset assuming there is
1949          * link so that it disables K1 if link is in 1Gbps.
1950          */
1951         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1952         if (ret_val)
1953                 return ret_val;
1954
1955         /* Workaround for link disconnects on a busy hub in half duplex */
1956         ret_val = hw->phy.ops.acquire(hw);
1957         if (ret_val)
1958                 return ret_val;
1959         ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1960         if (ret_val)
1961                 goto release;
1962         ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
1963         if (ret_val)
1964                 goto release;
1965
1966         /* set MSE higher to enable link to stay up when noise is high */
1967         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
1968 release:
1969         hw->phy.ops.release(hw);
1970
1971         return ret_val;
1972 }
1973
1974 /**
1975  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1976  *  @hw:   pointer to the HW structure
1977  **/
1978 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1979 {
1980         u32 mac_reg;
1981         u16 i, phy_reg = 0;
1982         s32 ret_val;
1983
1984         ret_val = hw->phy.ops.acquire(hw);
1985         if (ret_val)
1986                 return;
1987         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1988         if (ret_val)
1989                 goto release;
1990
1991         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
1992         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
1993                 mac_reg = er32(RAL(i));
1994                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1995                                            (u16)(mac_reg & 0xFFFF));
1996                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1997                                            (u16)((mac_reg >> 16) & 0xFFFF));
1998
1999                 mac_reg = er32(RAH(i));
2000                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2001                                            (u16)(mac_reg & 0xFFFF));
2002                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2003                                            (u16)((mac_reg & E1000_RAH_AV)
2004                                                  >> 16));
2005         }
2006
2007         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2008
2009 release:
2010         hw->phy.ops.release(hw);
2011 }
2012
2013 /**
2014  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2015  *  with 82579 PHY
2016  *  @hw: pointer to the HW structure
2017  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2018  **/
2019 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2020 {
2021         s32 ret_val = 0;
2022         u16 phy_reg, data;
2023         u32 mac_reg;
2024         u16 i;
2025
2026         if (hw->mac.type < e1000_pch2lan)
2027                 return 0;
2028
2029         /* disable Rx path while enabling/disabling workaround */
2030         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2031         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
2032         if (ret_val)
2033                 return ret_val;
2034
2035         if (enable) {
2036                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2037                  * SHRAL/H) and initial CRC values to the MAC
2038                  */
2039                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2040                         u8 mac_addr[ETH_ALEN] = { 0 };
2041                         u32 addr_high, addr_low;
2042
2043                         addr_high = er32(RAH(i));
2044                         if (!(addr_high & E1000_RAH_AV))
2045                                 continue;
2046                         addr_low = er32(RAL(i));
2047                         mac_addr[0] = (addr_low & 0xFF);
2048                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2049                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2050                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2051                         mac_addr[4] = (addr_high & 0xFF);
2052                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2053
2054                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2055                 }
2056
2057                 /* Write Rx addresses to the PHY */
2058                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2059
2060                 /* Enable jumbo frame workaround in the MAC */
2061                 mac_reg = er32(FFLT_DBG);
2062                 mac_reg &= ~(1 << 14);
2063                 mac_reg |= (7 << 15);
2064                 ew32(FFLT_DBG, mac_reg);
2065
2066                 mac_reg = er32(RCTL);
2067                 mac_reg |= E1000_RCTL_SECRC;
2068                 ew32(RCTL, mac_reg);
2069
2070                 ret_val = e1000e_read_kmrn_reg(hw,
2071                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2072                                                &data);
2073                 if (ret_val)
2074                         return ret_val;
2075                 ret_val = e1000e_write_kmrn_reg(hw,
2076                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2077                                                 data | (1 << 0));
2078                 if (ret_val)
2079                         return ret_val;
2080                 ret_val = e1000e_read_kmrn_reg(hw,
2081                                                E1000_KMRNCTRLSTA_HD_CTRL,
2082                                                &data);
2083                 if (ret_val)
2084                         return ret_val;
2085                 data &= ~(0xF << 8);
2086                 data |= (0xB << 8);
2087                 ret_val = e1000e_write_kmrn_reg(hw,
2088                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2089                                                 data);
2090                 if (ret_val)
2091                         return ret_val;
2092
2093                 /* Enable jumbo frame workaround in the PHY */
2094                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2095                 data &= ~(0x7F << 5);
2096                 data |= (0x37 << 5);
2097                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2098                 if (ret_val)
2099                         return ret_val;
2100                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2101                 data &= ~(1 << 13);
2102                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2103                 if (ret_val)
2104                         return ret_val;
2105                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2106                 data &= ~(0x3FF << 2);
2107                 data |= (0x1A << 2);
2108                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2109                 if (ret_val)
2110                         return ret_val;
2111                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2112                 if (ret_val)
2113                         return ret_val;
2114                 e1e_rphy(hw, HV_PM_CTRL, &data);
2115                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
2116                 if (ret_val)
2117                         return ret_val;
2118         } else {
2119                 /* Write MAC register values back to h/w defaults */
2120                 mac_reg = er32(FFLT_DBG);
2121                 mac_reg &= ~(0xF << 14);
2122                 ew32(FFLT_DBG, mac_reg);
2123
2124                 mac_reg = er32(RCTL);
2125                 mac_reg &= ~E1000_RCTL_SECRC;
2126                 ew32(RCTL, mac_reg);
2127
2128                 ret_val = e1000e_read_kmrn_reg(hw,
2129                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2130                                                &data);
2131                 if (ret_val)
2132                         return ret_val;
2133                 ret_val = e1000e_write_kmrn_reg(hw,
2134                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2135                                                 data & ~(1 << 0));
2136                 if (ret_val)
2137                         return ret_val;
2138                 ret_val = e1000e_read_kmrn_reg(hw,
2139                                                E1000_KMRNCTRLSTA_HD_CTRL,
2140                                                &data);
2141                 if (ret_val)
2142                         return ret_val;
2143                 data &= ~(0xF << 8);
2144                 data |= (0xB << 8);
2145                 ret_val = e1000e_write_kmrn_reg(hw,
2146                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2147                                                 data);
2148                 if (ret_val)
2149                         return ret_val;
2150
2151                 /* Write PHY register values back to h/w defaults */
2152                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2153                 data &= ~(0x7F << 5);
2154                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2155                 if (ret_val)
2156                         return ret_val;
2157                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2158                 data |= (1 << 13);
2159                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2160                 if (ret_val)
2161                         return ret_val;
2162                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2163                 data &= ~(0x3FF << 2);
2164                 data |= (0x8 << 2);
2165                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2166                 if (ret_val)
2167                         return ret_val;
2168                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2169                 if (ret_val)
2170                         return ret_val;
2171                 e1e_rphy(hw, HV_PM_CTRL, &data);
2172                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
2173                 if (ret_val)
2174                         return ret_val;
2175         }
2176
2177         /* re-enable Rx path after enabling/disabling workaround */
2178         return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
2179 }
2180
2181 /**
2182  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2183  *  done after every PHY reset.
2184  **/
2185 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2186 {
2187         s32 ret_val = 0;
2188
2189         if (hw->mac.type != e1000_pch2lan)
2190                 return 0;
2191
2192         /* Set MDIO slow mode before any other MDIO access */
2193         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2194         if (ret_val)
2195                 return ret_val;
2196
2197         ret_val = hw->phy.ops.acquire(hw);
2198         if (ret_val)
2199                 return ret_val;
2200         /* set MSE higher to enable link to stay up when noise is high */
2201         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2202         if (ret_val)
2203                 goto release;
2204         /* drop link after 5 times MSE threshold was reached */
2205         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2206 release:
2207         hw->phy.ops.release(hw);
2208
2209         return ret_val;
2210 }
2211
2212 /**
2213  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2214  *  @hw:   pointer to the HW structure
2215  *
2216  *  Workaround to set the K1 beacon duration for 82579 parts
2217  **/
2218 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2219 {
2220         s32 ret_val = 0;
2221         u16 status_reg = 0;
2222         u32 mac_reg;
2223         u16 phy_reg;
2224
2225         if (hw->mac.type != e1000_pch2lan)
2226                 return 0;
2227
2228         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
2229         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2230         if (ret_val)
2231                 return ret_val;
2232
2233         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2234             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2235                 mac_reg = er32(FEXTNVM4);
2236                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2237
2238                 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
2239                 if (ret_val)
2240                         return ret_val;
2241
2242                 if (status_reg & HV_M_STATUS_SPEED_1000) {
2243                         u16 pm_phy_reg;
2244
2245                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
2246                         phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2247                         /* LV 1G Packet drop issue wa  */
2248                         ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2249                         if (ret_val)
2250                                 return ret_val;
2251                         pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
2252                         ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2253                         if (ret_val)
2254                                 return ret_val;
2255                 } else {
2256                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2257                         phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2258                 }
2259                 ew32(FEXTNVM4, mac_reg);
2260                 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
2261         }
2262
2263         return ret_val;
2264 }
2265
2266 /**
2267  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2268  *  @hw:   pointer to the HW structure
2269  *  @gate: boolean set to true to gate, false to ungate
2270  *
2271  *  Gate/ungate the automatic PHY configuration via hardware; perform
2272  *  the configuration via software instead.
2273  **/
2274 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2275 {
2276         u32 extcnf_ctrl;
2277
2278         if (hw->mac.type < e1000_pch2lan)
2279                 return;
2280
2281         extcnf_ctrl = er32(EXTCNF_CTRL);
2282
2283         if (gate)
2284                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2285         else
2286                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2287
2288         ew32(EXTCNF_CTRL, extcnf_ctrl);
2289 }
2290
2291 /**
2292  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2293  *  @hw: pointer to the HW structure
2294  *
2295  *  Check the appropriate indication the MAC has finished configuring the
2296  *  PHY after a software reset.
2297  **/
2298 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2299 {
2300         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2301
2302         /* Wait for basic configuration completes before proceeding */
2303         do {
2304                 data = er32(STATUS);
2305                 data &= E1000_STATUS_LAN_INIT_DONE;
2306                 usleep_range(100, 200);
2307         } while ((!data) && --loop);
2308
2309         /* If basic configuration is incomplete before the above loop
2310          * count reaches 0, loading the configuration from NVM will
2311          * leave the PHY in a bad state possibly resulting in no link.
2312          */
2313         if (loop == 0)
2314                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2315
2316         /* Clear the Init Done bit for the next init event */
2317         data = er32(STATUS);
2318         data &= ~E1000_STATUS_LAN_INIT_DONE;
2319         ew32(STATUS, data);
2320 }
2321
2322 /**
2323  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2324  *  @hw: pointer to the HW structure
2325  **/
2326 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2327 {
2328         s32 ret_val = 0;
2329         u16 reg;
2330
2331         if (hw->phy.ops.check_reset_block(hw))
2332                 return 0;
2333
2334         /* Allow time for h/w to get to quiescent state after reset */
2335         usleep_range(10000, 20000);
2336
2337         /* Perform any necessary post-reset workarounds */
2338         switch (hw->mac.type) {
2339         case e1000_pchlan:
2340                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2341                 if (ret_val)
2342                         return ret_val;
2343                 break;
2344         case e1000_pch2lan:
2345                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2346                 if (ret_val)
2347                         return ret_val;
2348                 break;
2349         default:
2350                 break;
2351         }
2352
2353         /* Clear the host wakeup bit after lcd reset */
2354         if (hw->mac.type >= e1000_pchlan) {
2355                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2356                 reg &= ~BM_WUC_HOST_WU_BIT;
2357                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2358         }
2359
2360         /* Configure the LCD with the extended configuration region in NVM */
2361         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2362         if (ret_val)
2363                 return ret_val;
2364
2365         /* Configure the LCD with the OEM bits in NVM */
2366         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2367
2368         if (hw->mac.type == e1000_pch2lan) {
2369                 /* Ungate automatic PHY configuration on non-managed 82579 */
2370                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2371                         usleep_range(10000, 20000);
2372                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2373                 }
2374
2375                 /* Set EEE LPI Update Timer to 200usec */
2376                 ret_val = hw->phy.ops.acquire(hw);
2377                 if (ret_val)
2378                         return ret_val;
2379                 ret_val = e1000_write_emi_reg_locked(hw,
2380                                                      I82579_LPI_UPDATE_TIMER,
2381                                                      0x1387);
2382                 hw->phy.ops.release(hw);
2383         }
2384
2385         return ret_val;
2386 }
2387
2388 /**
2389  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2390  *  @hw: pointer to the HW structure
2391  *
2392  *  Resets the PHY
2393  *  This is a function pointer entry point called by drivers
2394  *  or other shared routines.
2395  **/
2396 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2397 {
2398         s32 ret_val = 0;
2399
2400         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2401         if ((hw->mac.type == e1000_pch2lan) &&
2402             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2403                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2404
2405         ret_val = e1000e_phy_hw_reset_generic(hw);
2406         if (ret_val)
2407                 return ret_val;
2408
2409         return e1000_post_phy_reset_ich8lan(hw);
2410 }
2411
2412 /**
2413  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2414  *  @hw: pointer to the HW structure
2415  *  @active: true to enable LPLU, false to disable
2416  *
2417  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2418  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2419  *  the phy speed. This function will manually set the LPLU bit and restart
2420  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2421  *  since it configures the same bit.
2422  **/
2423 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2424 {
2425         s32 ret_val;
2426         u16 oem_reg;
2427
2428         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2429         if (ret_val)
2430                 return ret_val;
2431
2432         if (active)
2433                 oem_reg |= HV_OEM_BITS_LPLU;
2434         else
2435                 oem_reg &= ~HV_OEM_BITS_LPLU;
2436
2437         if (!hw->phy.ops.check_reset_block(hw))
2438                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2439
2440         return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2441 }
2442
2443 /**
2444  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2445  *  @hw: pointer to the HW structure
2446  *  @active: true to enable LPLU, false to disable
2447  *
2448  *  Sets the LPLU D0 state according to the active flag.  When
2449  *  activating LPLU this function also disables smart speed
2450  *  and vice versa.  LPLU will not be activated unless the
2451  *  device autonegotiation advertisement meets standards of
2452  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2453  *  This is a function pointer entry point only called by
2454  *  PHY setup routines.
2455  **/
2456 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2457 {
2458         struct e1000_phy_info *phy = &hw->phy;
2459         u32 phy_ctrl;
2460         s32 ret_val = 0;
2461         u16 data;
2462
2463         if (phy->type == e1000_phy_ife)
2464                 return 0;
2465
2466         phy_ctrl = er32(PHY_CTRL);
2467
2468         if (active) {
2469                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2470                 ew32(PHY_CTRL, phy_ctrl);
2471
2472                 if (phy->type != e1000_phy_igp_3)
2473                         return 0;
2474
2475                 /* Call gig speed drop workaround on LPLU before accessing
2476                  * any PHY registers
2477                  */
2478                 if (hw->mac.type == e1000_ich8lan)
2479                         e1000e_gig_downshift_workaround_ich8lan(hw);
2480
2481                 /* When LPLU is enabled, we should disable SmartSpeed */
2482                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2483                 if (ret_val)
2484                         return ret_val;
2485                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2486                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2487                 if (ret_val)
2488                         return ret_val;
2489         } else {
2490                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2491                 ew32(PHY_CTRL, phy_ctrl);
2492
2493                 if (phy->type != e1000_phy_igp_3)
2494                         return 0;
2495
2496                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2497                  * during Dx states where the power conservation is most
2498                  * important.  During driver activity we should enable
2499                  * SmartSpeed, so performance is maintained.
2500                  */
2501                 if (phy->smart_speed == e1000_smart_speed_on) {
2502                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2503                                            &data);
2504                         if (ret_val)
2505                                 return ret_val;
2506
2507                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2508                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2509                                            data);
2510                         if (ret_val)
2511                                 return ret_val;
2512                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2513                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2514                                            &data);
2515                         if (ret_val)
2516                                 return ret_val;
2517
2518                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2519                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2520                                            data);
2521                         if (ret_val)
2522                                 return ret_val;
2523                 }
2524         }
2525
2526         return 0;
2527 }
2528
2529 /**
2530  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2531  *  @hw: pointer to the HW structure
2532  *  @active: true to enable LPLU, false to disable
2533  *
2534  *  Sets the LPLU D3 state according to the active flag.  When
2535  *  activating LPLU this function also disables smart speed
2536  *  and vice versa.  LPLU will not be activated unless the
2537  *  device autonegotiation advertisement meets standards of
2538  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2539  *  This is a function pointer entry point only called by
2540  *  PHY setup routines.
2541  **/
2542 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2543 {
2544         struct e1000_phy_info *phy = &hw->phy;
2545         u32 phy_ctrl;
2546         s32 ret_val = 0;
2547         u16 data;
2548
2549         phy_ctrl = er32(PHY_CTRL);
2550
2551         if (!active) {
2552                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2553                 ew32(PHY_CTRL, phy_ctrl);
2554
2555                 if (phy->type != e1000_phy_igp_3)
2556                         return 0;
2557
2558                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2559                  * during Dx states where the power conservation is most
2560                  * important.  During driver activity we should enable
2561                  * SmartSpeed, so performance is maintained.
2562                  */
2563                 if (phy->smart_speed == e1000_smart_speed_on) {
2564                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2565                                            &data);
2566                         if (ret_val)
2567                                 return ret_val;
2568
2569                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2570                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2571                                            data);
2572                         if (ret_val)
2573                                 return ret_val;
2574                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2575                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2576                                            &data);
2577                         if (ret_val)
2578                                 return ret_val;
2579
2580                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2581                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2582                                            data);
2583                         if (ret_val)
2584                                 return ret_val;
2585                 }
2586         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2587                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2588                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2589                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2590                 ew32(PHY_CTRL, phy_ctrl);
2591
2592                 if (phy->type != e1000_phy_igp_3)
2593                         return 0;
2594
2595                 /* Call gig speed drop workaround on LPLU before accessing
2596                  * any PHY registers
2597                  */
2598                 if (hw->mac.type == e1000_ich8lan)
2599                         e1000e_gig_downshift_workaround_ich8lan(hw);
2600
2601                 /* When LPLU is enabled, we should disable SmartSpeed */
2602                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2603                 if (ret_val)
2604                         return ret_val;
2605
2606                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2607                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2608         }
2609
2610         return ret_val;
2611 }
2612
2613 /**
2614  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2615  *  @hw: pointer to the HW structure
2616  *  @bank:  pointer to the variable that returns the active bank
2617  *
2618  *  Reads signature byte from the NVM using the flash access registers.
2619  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2620  **/
2621 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2622 {
2623         u32 eecd;
2624         struct e1000_nvm_info *nvm = &hw->nvm;
2625         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2626         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2627         u8 sig_byte = 0;
2628         s32 ret_val;
2629
2630         switch (hw->mac.type) {
2631         case e1000_ich8lan:
2632         case e1000_ich9lan:
2633                 eecd = er32(EECD);
2634                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2635                     E1000_EECD_SEC1VAL_VALID_MASK) {
2636                         if (eecd & E1000_EECD_SEC1VAL)
2637                                 *bank = 1;
2638                         else
2639                                 *bank = 0;
2640
2641                         return 0;
2642                 }
2643                 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2644                 /* fall-thru */
2645         default:
2646                 /* set bank to 0 in case flash read fails */
2647                 *bank = 0;
2648
2649                 /* Check bank 0 */
2650                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2651                                                         &sig_byte);
2652                 if (ret_val)
2653                         return ret_val;
2654                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2655                     E1000_ICH_NVM_SIG_VALUE) {
2656                         *bank = 0;
2657                         return 0;
2658                 }
2659
2660                 /* Check bank 1 */
2661                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2662                                                         bank1_offset,
2663                                                         &sig_byte);
2664                 if (ret_val)
2665                         return ret_val;
2666                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2667                     E1000_ICH_NVM_SIG_VALUE) {
2668                         *bank = 1;
2669                         return 0;
2670                 }
2671
2672                 e_dbg("ERROR: No valid NVM bank present\n");
2673                 return -E1000_ERR_NVM;
2674         }
2675 }
2676
2677 /**
2678  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2679  *  @hw: pointer to the HW structure
2680  *  @offset: The offset (in bytes) of the word(s) to read.
2681  *  @words: Size of data to read in words
2682  *  @data: Pointer to the word(s) to read at offset.
2683  *
2684  *  Reads a word(s) from the NVM using the flash access registers.
2685  **/
2686 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2687                                   u16 *data)
2688 {
2689         struct e1000_nvm_info *nvm = &hw->nvm;
2690         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2691         u32 act_offset;
2692         s32 ret_val = 0;
2693         u32 bank = 0;
2694         u16 i, word;
2695
2696         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2697             (words == 0)) {
2698                 e_dbg("nvm parameter(s) out of bounds\n");
2699                 ret_val = -E1000_ERR_NVM;
2700                 goto out;
2701         }
2702
2703         nvm->ops.acquire(hw);
2704
2705         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2706         if (ret_val) {
2707                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2708                 bank = 0;
2709         }
2710
2711         act_offset = (bank) ? nvm->flash_bank_size : 0;
2712         act_offset += offset;
2713
2714         ret_val = 0;
2715         for (i = 0; i < words; i++) {
2716                 if (dev_spec->shadow_ram[offset + i].modified) {
2717                         data[i] = dev_spec->shadow_ram[offset + i].value;
2718                 } else {
2719                         ret_val = e1000_read_flash_word_ich8lan(hw,
2720                                                                 act_offset + i,
2721                                                                 &word);
2722                         if (ret_val)
2723                                 break;
2724                         data[i] = word;
2725                 }
2726         }
2727
2728         nvm->ops.release(hw);
2729
2730 out:
2731         if (ret_val)
2732                 e_dbg("NVM read error: %d\n", ret_val);
2733
2734         return ret_val;
2735 }
2736
2737 /**
2738  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2739  *  @hw: pointer to the HW structure
2740  *
2741  *  This function does initial flash setup so that a new read/write/erase cycle
2742  *  can be started.
2743  **/
2744 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2745 {
2746         union ich8_hws_flash_status hsfsts;
2747         s32 ret_val = -E1000_ERR_NVM;
2748
2749         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2750
2751         /* Check if the flash descriptor is valid */
2752         if (!hsfsts.hsf_status.fldesvalid) {
2753                 e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
2754                 return -E1000_ERR_NVM;
2755         }
2756
2757         /* Clear FCERR and DAEL in hw status by writing 1 */
2758         hsfsts.hsf_status.flcerr = 1;
2759         hsfsts.hsf_status.dael = 1;
2760
2761         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2762
2763         /* Either we should have a hardware SPI cycle in progress
2764          * bit to check against, in order to start a new cycle or
2765          * FDONE bit should be changed in the hardware so that it
2766          * is 1 after hardware reset, which can then be used as an
2767          * indication whether a cycle is in progress or has been
2768          * completed.
2769          */
2770
2771         if (!hsfsts.hsf_status.flcinprog) {
2772                 /* There is no cycle running at present,
2773                  * so we can start a cycle.
2774                  * Begin by setting Flash Cycle Done.
2775                  */
2776                 hsfsts.hsf_status.flcdone = 1;
2777                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2778                 ret_val = 0;
2779         } else {
2780                 s32 i;
2781
2782                 /* Otherwise poll for sometime so the current
2783                  * cycle has a chance to end before giving up.
2784                  */
2785                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2786                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2787                         if (!hsfsts.hsf_status.flcinprog) {
2788                                 ret_val = 0;
2789                                 break;
2790                         }
2791                         udelay(1);
2792                 }
2793                 if (!ret_val) {
2794                         /* Successful in waiting for previous cycle to timeout,
2795                          * now set the Flash Cycle Done.
2796                          */
2797                         hsfsts.hsf_status.flcdone = 1;
2798                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2799                 } else {
2800                         e_dbg("Flash controller busy, cannot get access\n");
2801                 }
2802         }
2803
2804         return ret_val;
2805 }
2806
2807 /**
2808  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2809  *  @hw: pointer to the HW structure
2810  *  @timeout: maximum time to wait for completion
2811  *
2812  *  This function starts a flash cycle and waits for its completion.
2813  **/
2814 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2815 {
2816         union ich8_hws_flash_ctrl hsflctl;
2817         union ich8_hws_flash_status hsfsts;
2818         u32 i = 0;
2819
2820         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2821         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2822         hsflctl.hsf_ctrl.flcgo = 1;
2823         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2824
2825         /* wait till FDONE bit is set to 1 */
2826         do {
2827                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2828                 if (hsfsts.hsf_status.flcdone)
2829                         break;
2830                 udelay(1);
2831         } while (i++ < timeout);
2832
2833         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
2834                 return 0;
2835
2836         return -E1000_ERR_NVM;
2837 }
2838
2839 /**
2840  *  e1000_read_flash_word_ich8lan - Read word from flash
2841  *  @hw: pointer to the HW structure
2842  *  @offset: offset to data location
2843  *  @data: pointer to the location for storing the data
2844  *
2845  *  Reads the flash word at offset into data.  Offset is converted
2846  *  to bytes before read.
2847  **/
2848 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2849                                          u16 *data)
2850 {
2851         /* Must convert offset into bytes. */
2852         offset <<= 1;
2853
2854         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2855 }
2856
2857 /**
2858  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2859  *  @hw: pointer to the HW structure
2860  *  @offset: The offset of the byte to read.
2861  *  @data: Pointer to a byte to store the value read.
2862  *
2863  *  Reads a single byte from the NVM using the flash access registers.
2864  **/
2865 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2866                                          u8 *data)
2867 {
2868         s32 ret_val;
2869         u16 word = 0;
2870
2871         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2872         if (ret_val)
2873                 return ret_val;
2874
2875         *data = (u8)word;
2876
2877         return 0;
2878 }
2879
2880 /**
2881  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2882  *  @hw: pointer to the HW structure
2883  *  @offset: The offset (in bytes) of the byte or word to read.
2884  *  @size: Size of data to read, 1=byte 2=word
2885  *  @data: Pointer to the word to store the value read.
2886  *
2887  *  Reads a byte or word from the NVM using the flash access registers.
2888  **/
2889 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2890                                          u8 size, u16 *data)
2891 {
2892         union ich8_hws_flash_status hsfsts;
2893         union ich8_hws_flash_ctrl hsflctl;
2894         u32 flash_linear_addr;
2895         u32 flash_data = 0;
2896         s32 ret_val = -E1000_ERR_NVM;
2897         u8 count = 0;
2898
2899         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2900                 return -E1000_ERR_NVM;
2901
2902         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2903                              hw->nvm.flash_base_addr);
2904
2905         do {
2906                 udelay(1);
2907                 /* Steps */
2908                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2909                 if (ret_val)
2910                         break;
2911
2912                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2913                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2914                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2915                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2916                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2917
2918                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2919
2920                 ret_val =
2921                     e1000_flash_cycle_ich8lan(hw,
2922                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
2923
2924                 /* Check if FCERR is set to 1, if set to 1, clear it
2925                  * and try the whole sequence a few more times, else
2926                  * read in (shift in) the Flash Data0, the order is
2927                  * least significant byte first msb to lsb
2928                  */
2929                 if (!ret_val) {
2930                         flash_data = er32flash(ICH_FLASH_FDATA0);
2931                         if (size == 1)
2932                                 *data = (u8)(flash_data & 0x000000FF);
2933                         else if (size == 2)
2934                                 *data = (u16)(flash_data & 0x0000FFFF);
2935                         break;
2936                 } else {
2937                         /* If we've gotten here, then things are probably
2938                          * completely hosed, but if the error condition is
2939                          * detected, it won't hurt to give it another try...
2940                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2941                          */
2942                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2943                         if (hsfsts.hsf_status.flcerr) {
2944                                 /* Repeat for some time before giving up. */
2945                                 continue;
2946                         } else if (!hsfsts.hsf_status.flcdone) {
2947                                 e_dbg("Timeout error - flash cycle did not complete.\n");
2948                                 break;
2949                         }
2950                 }
2951         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2952
2953         return ret_val;
2954 }
2955
2956 /**
2957  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2958  *  @hw: pointer to the HW structure
2959  *  @offset: The offset (in bytes) of the word(s) to write.
2960  *  @words: Size of data to write in words
2961  *  @data: Pointer to the word(s) to write at offset.
2962  *
2963  *  Writes a byte or word to the NVM using the flash access registers.
2964  **/
2965 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2966                                    u16 *data)
2967 {
2968         struct e1000_nvm_info *nvm = &hw->nvm;
2969         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2970         u16 i;
2971
2972         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2973             (words == 0)) {
2974                 e_dbg("nvm parameter(s) out of bounds\n");
2975                 return -E1000_ERR_NVM;
2976         }
2977
2978         nvm->ops.acquire(hw);
2979
2980         for (i = 0; i < words; i++) {
2981                 dev_spec->shadow_ram[offset + i].modified = true;
2982                 dev_spec->shadow_ram[offset + i].value = data[i];
2983         }
2984
2985         nvm->ops.release(hw);
2986
2987         return 0;
2988 }
2989
2990 /**
2991  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2992  *  @hw: pointer to the HW structure
2993  *
2994  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2995  *  which writes the checksum to the shadow ram.  The changes in the shadow
2996  *  ram are then committed to the EEPROM by processing each bank at a time
2997  *  checking for the modified bit and writing only the pending changes.
2998  *  After a successful commit, the shadow ram is cleared and is ready for
2999  *  future writes.
3000  **/
3001 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3002 {
3003         struct e1000_nvm_info *nvm = &hw->nvm;
3004         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3005         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3006         s32 ret_val;
3007         u16 data;
3008
3009         ret_val = e1000e_update_nvm_checksum_generic(hw);
3010         if (ret_val)
3011                 goto out;
3012
3013         if (nvm->type != e1000_nvm_flash_sw)
3014                 goto out;
3015
3016         nvm->ops.acquire(hw);
3017
3018         /* We're writing to the opposite bank so if we're on bank 1,
3019          * write to bank 0 etc.  We also need to erase the segment that
3020          * is going to be written
3021          */
3022         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3023         if (ret_val) {
3024                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3025                 bank = 0;
3026         }
3027
3028         if (bank == 0) {
3029                 new_bank_offset = nvm->flash_bank_size;
3030                 old_bank_offset = 0;
3031                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3032                 if (ret_val)
3033                         goto release;
3034         } else {
3035                 old_bank_offset = nvm->flash_bank_size;
3036                 new_bank_offset = 0;
3037                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3038                 if (ret_val)
3039                         goto release;
3040         }
3041
3042         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3043                 /* Determine whether to write the value stored
3044                  * in the other NVM bank or a modified value stored
3045                  * in the shadow RAM
3046                  */
3047                 if (dev_spec->shadow_ram[i].modified) {
3048                         data = dev_spec->shadow_ram[i].value;
3049                 } else {
3050                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
3051                                                                 old_bank_offset,
3052                                                                 &data);
3053                         if (ret_val)
3054                                 break;
3055                 }
3056
3057                 /* If the word is 0x13, then make sure the signature bits
3058                  * (15:14) are 11b until the commit has completed.
3059                  * This will allow us to write 10b which indicates the
3060                  * signature is valid.  We want to do this after the write
3061                  * has completed so that we don't mark the segment valid
3062                  * while the write is still in progress
3063                  */
3064                 if (i == E1000_ICH_NVM_SIG_WORD)
3065                         data |= E1000_ICH_NVM_SIG_MASK;
3066
3067                 /* Convert offset to bytes. */
3068                 act_offset = (i + new_bank_offset) << 1;
3069
3070                 usleep_range(100, 200);
3071                 /* Write the bytes to the new bank. */
3072                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3073                                                                act_offset,
3074                                                                (u8)data);
3075                 if (ret_val)
3076                         break;
3077
3078                 usleep_range(100, 200);
3079                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3080                                                                act_offset + 1,
3081                                                                (u8)(data >> 8));
3082                 if (ret_val)
3083                         break;
3084         }
3085
3086         /* Don't bother writing the segment valid bits if sector
3087          * programming failed.
3088          */
3089         if (ret_val) {
3090                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3091                 e_dbg("Flash commit failed.\n");
3092                 goto release;
3093         }
3094
3095         /* Finally validate the new segment by setting bit 15:14
3096          * to 10b in word 0x13 , this can be done without an
3097          * erase as well since these bits are 11 to start with
3098          * and we need to change bit 14 to 0b
3099          */
3100         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3101         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3102         if (ret_val)
3103                 goto release;
3104
3105         data &= 0xBFFF;
3106         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3107                                                        act_offset * 2 + 1,
3108                                                        (u8)(data >> 8));
3109         if (ret_val)
3110                 goto release;
3111
3112         /* And invalidate the previously valid segment by setting
3113          * its signature word (0x13) high_byte to 0b. This can be
3114          * done without an erase because flash erase sets all bits
3115          * to 1's. We can write 1's to 0's without an erase
3116          */
3117         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3118         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3119         if (ret_val)
3120                 goto release;
3121
3122         /* Great!  Everything worked, we can now clear the cached entries. */
3123         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3124                 dev_spec->shadow_ram[i].modified = false;
3125                 dev_spec->shadow_ram[i].value = 0xFFFF;
3126         }
3127
3128 release:
3129         nvm->ops.release(hw);
3130
3131         /* Reload the EEPROM, or else modifications will not appear
3132          * until after the next adapter reset.
3133          */
3134         if (!ret_val) {
3135                 nvm->ops.reload(hw);
3136                 usleep_range(10000, 20000);
3137         }
3138
3139 out:
3140         if (ret_val)
3141                 e_dbg("NVM update error: %d\n", ret_val);
3142
3143         return ret_val;
3144 }
3145
3146 /**
3147  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3148  *  @hw: pointer to the HW structure
3149  *
3150  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3151  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
3152  *  calculated, in which case we need to calculate the checksum and set bit 6.
3153  **/
3154 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3155 {
3156         s32 ret_val;
3157         u16 data;
3158         u16 word;
3159         u16 valid_csum_mask;
3160
3161         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
3162          * the checksum needs to be fixed.  This bit is an indication that
3163          * the NVM was prepared by OEM software and did not calculate
3164          * the checksum...a likely scenario.
3165          */
3166         switch (hw->mac.type) {
3167         case e1000_pch_lpt:
3168                 word = NVM_COMPAT;
3169                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3170                 break;
3171         default:
3172                 word = NVM_FUTURE_INIT_WORD1;
3173                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3174                 break;
3175         }
3176
3177         ret_val = e1000_read_nvm(hw, word, 1, &data);
3178         if (ret_val)
3179                 return ret_val;
3180
3181         if (!(data & valid_csum_mask)) {
3182                 data |= valid_csum_mask;
3183                 ret_val = e1000_write_nvm(hw, word, 1, &data);
3184                 if (ret_val)
3185                         return ret_val;
3186                 ret_val = e1000e_update_nvm_checksum(hw);
3187                 if (ret_val)
3188                         return ret_val;
3189         }
3190
3191         return e1000e_validate_nvm_checksum_generic(hw);
3192 }
3193
3194 /**
3195  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
3196  *  @hw: pointer to the HW structure
3197  *
3198  *  To prevent malicious write/erase of the NVM, set it to be read-only
3199  *  so that the hardware ignores all write/erase cycles of the NVM via
3200  *  the flash control registers.  The shadow-ram copy of the NVM will
3201  *  still be updated, however any updates to this copy will not stick
3202  *  across driver reloads.
3203  **/
3204 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
3205 {
3206         struct e1000_nvm_info *nvm = &hw->nvm;
3207         union ich8_flash_protected_range pr0;
3208         union ich8_hws_flash_status hsfsts;
3209         u32 gfpreg;
3210
3211         nvm->ops.acquire(hw);
3212
3213         gfpreg = er32flash(ICH_FLASH_GFPREG);
3214
3215         /* Write-protect GbE Sector of NVM */
3216         pr0.regval = er32flash(ICH_FLASH_PR0);
3217         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
3218         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
3219         pr0.range.wpe = true;
3220         ew32flash(ICH_FLASH_PR0, pr0.regval);
3221
3222         /* Lock down a subset of GbE Flash Control Registers, e.g.
3223          * PR0 to prevent the write-protection from being lifted.
3224          * Once FLOCKDN is set, the registers protected by it cannot
3225          * be written until FLOCKDN is cleared by a hardware reset.
3226          */
3227         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3228         hsfsts.hsf_status.flockdn = true;
3229         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3230
3231         nvm->ops.release(hw);
3232 }
3233
3234 /**
3235  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3236  *  @hw: pointer to the HW structure
3237  *  @offset: The offset (in bytes) of the byte/word to read.
3238  *  @size: Size of data to read, 1=byte 2=word
3239  *  @data: The byte(s) to write to the NVM.
3240  *
3241  *  Writes one/two bytes to the NVM using the flash access registers.
3242  **/
3243 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3244                                           u8 size, u16 data)
3245 {
3246         union ich8_hws_flash_status hsfsts;
3247         union ich8_hws_flash_ctrl hsflctl;
3248         u32 flash_linear_addr;
3249         u32 flash_data = 0;
3250         s32 ret_val;
3251         u8 count = 0;
3252
3253         if (size < 1 || size > 2 || data > size * 0xff ||
3254             offset > ICH_FLASH_LINEAR_ADDR_MASK)
3255                 return -E1000_ERR_NVM;
3256
3257         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3258                              hw->nvm.flash_base_addr);
3259
3260         do {
3261                 udelay(1);
3262                 /* Steps */
3263                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3264                 if (ret_val)
3265                         break;
3266
3267                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3268                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3269                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3270                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3271                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3272
3273                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3274
3275                 if (size == 1)
3276                         flash_data = (u32)data & 0x00FF;
3277                 else
3278                         flash_data = (u32)data;
3279
3280                 ew32flash(ICH_FLASH_FDATA0, flash_data);
3281
3282                 /* check if FCERR is set to 1 , if set to 1, clear it
3283                  * and try the whole sequence a few more times else done
3284                  */
3285                 ret_val =
3286                     e1000_flash_cycle_ich8lan(hw,
3287                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3288                 if (!ret_val)
3289                         break;
3290
3291                 /* If we're here, then things are most likely
3292                  * completely hosed, but if the error condition
3293                  * is detected, it won't hurt to give it another
3294                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3295                  */
3296                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3297                 if (hsfsts.hsf_status.flcerr)
3298                         /* Repeat for some time before giving up. */
3299                         continue;
3300                 if (!hsfsts.hsf_status.flcdone) {
3301                         e_dbg("Timeout error - flash cycle did not complete.\n");
3302                         break;
3303                 }
3304         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3305
3306         return ret_val;
3307 }
3308
3309 /**
3310  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3311  *  @hw: pointer to the HW structure
3312  *  @offset: The index of the byte to read.
3313  *  @data: The byte to write to the NVM.
3314  *
3315  *  Writes a single byte to the NVM using the flash access registers.
3316  **/
3317 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3318                                           u8 data)
3319 {
3320         u16 word = (u16)data;
3321
3322         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3323 }
3324
3325 /**
3326  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3327  *  @hw: pointer to the HW structure
3328  *  @offset: The offset of the byte to write.
3329  *  @byte: The byte to write to the NVM.
3330  *
3331  *  Writes a single byte to the NVM using the flash access registers.
3332  *  Goes through a retry algorithm before giving up.
3333  **/
3334 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3335                                                 u32 offset, u8 byte)
3336 {
3337         s32 ret_val;
3338         u16 program_retries;
3339
3340         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3341         if (!ret_val)
3342                 return ret_val;
3343
3344         for (program_retries = 0; program_retries < 100; program_retries++) {
3345                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
3346                 usleep_range(100, 200);
3347                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3348                 if (!ret_val)
3349                         break;
3350         }
3351         if (program_retries == 100)
3352                 return -E1000_ERR_NVM;
3353
3354         return 0;
3355 }
3356
3357 /**
3358  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3359  *  @hw: pointer to the HW structure
3360  *  @bank: 0 for first bank, 1 for second bank, etc.
3361  *
3362  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3363  *  bank N is 4096 * N + flash_reg_addr.
3364  **/
3365 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3366 {
3367         struct e1000_nvm_info *nvm = &hw->nvm;
3368         union ich8_hws_flash_status hsfsts;
3369         union ich8_hws_flash_ctrl hsflctl;
3370         u32 flash_linear_addr;
3371         /* bank size is in 16bit words - adjust to bytes */
3372         u32 flash_bank_size = nvm->flash_bank_size * 2;
3373         s32 ret_val;
3374         s32 count = 0;
3375         s32 j, iteration, sector_size;
3376
3377         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3378
3379         /* Determine HW Sector size: Read BERASE bits of hw flash status
3380          * register
3381          * 00: The Hw sector is 256 bytes, hence we need to erase 16
3382          *     consecutive sectors.  The start index for the nth Hw sector
3383          *     can be calculated as = bank * 4096 + n * 256
3384          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3385          *     The start index for the nth Hw sector can be calculated
3386          *     as = bank * 4096
3387          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3388          *     (ich9 only, otherwise error condition)
3389          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3390          */
3391         switch (hsfsts.hsf_status.berasesz) {
3392         case 0:
3393                 /* Hw sector size 256 */
3394                 sector_size = ICH_FLASH_SEG_SIZE_256;
3395                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3396                 break;
3397         case 1:
3398                 sector_size = ICH_FLASH_SEG_SIZE_4K;
3399                 iteration = 1;
3400                 break;
3401         case 2:
3402                 sector_size = ICH_FLASH_SEG_SIZE_8K;
3403                 iteration = 1;
3404                 break;
3405         case 3:
3406                 sector_size = ICH_FLASH_SEG_SIZE_64K;
3407                 iteration = 1;
3408                 break;
3409         default:
3410                 return -E1000_ERR_NVM;
3411         }
3412
3413         /* Start with the base address, then add the sector offset. */
3414         flash_linear_addr = hw->nvm.flash_base_addr;
3415         flash_linear_addr += (bank) ? flash_bank_size : 0;
3416
3417         for (j = 0; j < iteration; j++) {
3418                 do {
3419                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3420
3421                         /* Steps */
3422                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
3423                         if (ret_val)
3424                                 return ret_val;
3425
3426                         /* Write a value 11 (block Erase) in Flash
3427                          * Cycle field in hw flash control
3428                          */
3429                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3430                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3431                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3432
3433                         /* Write the last 24 bits of an index within the
3434                          * block into Flash Linear address field in Flash
3435                          * Address.
3436                          */
3437                         flash_linear_addr += (j * sector_size);
3438                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3439
3440                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
3441                         if (!ret_val)
3442                                 break;
3443
3444                         /* Check if FCERR is set to 1.  If 1,
3445                          * clear it and try the whole sequence
3446                          * a few more times else Done
3447                          */
3448                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3449                         if (hsfsts.hsf_status.flcerr)
3450                                 /* repeat for some time before giving up */
3451                                 continue;
3452                         else if (!hsfsts.hsf_status.flcdone)
3453                                 return ret_val;
3454                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3455         }
3456
3457         return 0;
3458 }
3459
3460 /**
3461  *  e1000_valid_led_default_ich8lan - Set the default LED settings
3462  *  @hw: pointer to the HW structure
3463  *  @data: Pointer to the LED settings
3464  *
3465  *  Reads the LED default settings from the NVM to data.  If the NVM LED
3466  *  settings is all 0's or F's, set the LED default to a valid LED default
3467  *  setting.
3468  **/
3469 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3470 {
3471         s32 ret_val;
3472
3473         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
3474         if (ret_val) {
3475                 e_dbg("NVM Read Error\n");
3476                 return ret_val;
3477         }
3478
3479         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
3480                 *data = ID_LED_DEFAULT_ICH8LAN;
3481
3482         return 0;
3483 }
3484
3485 /**
3486  *  e1000_id_led_init_pchlan - store LED configurations
3487  *  @hw: pointer to the HW structure
3488  *
3489  *  PCH does not control LEDs via the LEDCTL register, rather it uses
3490  *  the PHY LED configuration register.
3491  *
3492  *  PCH also does not have an "always on" or "always off" mode which
3493  *  complicates the ID feature.  Instead of using the "on" mode to indicate
3494  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
3495  *  use "link_up" mode.  The LEDs will still ID on request if there is no
3496  *  link based on logic in e1000_led_[on|off]_pchlan().
3497  **/
3498 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3499 {
3500         struct e1000_mac_info *mac = &hw->mac;
3501         s32 ret_val;
3502         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3503         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3504         u16 data, i, temp, shift;
3505
3506         /* Get default ID LED modes */
3507         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3508         if (ret_val)
3509                 return ret_val;
3510
3511         mac->ledctl_default = er32(LEDCTL);
3512         mac->ledctl_mode1 = mac->ledctl_default;
3513         mac->ledctl_mode2 = mac->ledctl_default;
3514
3515         for (i = 0; i < 4; i++) {
3516                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3517                 shift = (i * 5);
3518                 switch (temp) {
3519                 case ID_LED_ON1_DEF2:
3520                 case ID_LED_ON1_ON2:
3521                 case ID_LED_ON1_OFF2:
3522                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3523                         mac->ledctl_mode1 |= (ledctl_on << shift);
3524                         break;
3525                 case ID_LED_OFF1_DEF2:
3526                 case ID_LED_OFF1_ON2:
3527                 case ID_LED_OFF1_OFF2:
3528                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3529                         mac->ledctl_mode1 |= (ledctl_off << shift);
3530                         break;
3531                 default:
3532                         /* Do nothing */
3533                         break;
3534                 }
3535                 switch (temp) {
3536                 case ID_LED_DEF1_ON2:
3537                 case ID_LED_ON1_ON2:
3538                 case ID_LED_OFF1_ON2:
3539                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3540                         mac->ledctl_mode2 |= (ledctl_on << shift);
3541                         break;
3542                 case ID_LED_DEF1_OFF2:
3543                 case ID_LED_ON1_OFF2:
3544                 case ID_LED_OFF1_OFF2:
3545                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3546                         mac->ledctl_mode2 |= (ledctl_off << shift);
3547                         break;
3548                 default:
3549                         /* Do nothing */
3550                         break;
3551                 }
3552         }
3553
3554         return 0;
3555 }
3556
3557 /**
3558  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3559  *  @hw: pointer to the HW structure
3560  *
3561  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3562  *  register, so the the bus width is hard coded.
3563  **/
3564 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3565 {
3566         struct e1000_bus_info *bus = &hw->bus;
3567         s32 ret_val;
3568
3569         ret_val = e1000e_get_bus_info_pcie(hw);
3570
3571         /* ICH devices are "PCI Express"-ish.  They have
3572          * a configuration space, but do not contain
3573          * PCI Express Capability registers, so bus width
3574          * must be hardcoded.
3575          */
3576         if (bus->width == e1000_bus_width_unknown)
3577                 bus->width = e1000_bus_width_pcie_x1;
3578
3579         return ret_val;
3580 }
3581
3582 /**
3583  *  e1000_reset_hw_ich8lan - Reset the hardware
3584  *  @hw: pointer to the HW structure
3585  *
3586  *  Does a full reset of the hardware which includes a reset of the PHY and
3587  *  MAC.
3588  **/
3589 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3590 {
3591         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3592         u16 kum_cfg;
3593         u32 ctrl, reg;
3594         s32 ret_val;
3595
3596         /* Prevent the PCI-E bus from sticking if there is no TLP connection
3597          * on the last TLP read/write transaction when MAC is reset.
3598          */
3599         ret_val = e1000e_disable_pcie_master(hw);
3600         if (ret_val)
3601                 e_dbg("PCI-E Master disable polling has failed.\n");
3602
3603         e_dbg("Masking off all interrupts\n");
3604         ew32(IMC, 0xffffffff);
3605
3606         /* Disable the Transmit and Receive units.  Then delay to allow
3607          * any pending transactions to complete before we hit the MAC
3608          * with the global reset.
3609          */
3610         ew32(RCTL, 0);
3611         ew32(TCTL, E1000_TCTL_PSP);
3612         e1e_flush();
3613
3614         usleep_range(10000, 20000);
3615
3616         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3617         if (hw->mac.type == e1000_ich8lan) {
3618                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3619                 ew32(PBA, E1000_PBA_8K);
3620                 /* Set Packet Buffer Size to 16k. */
3621                 ew32(PBS, E1000_PBS_16K);
3622         }
3623
3624         if (hw->mac.type == e1000_pchlan) {
3625                 /* Save the NVM K1 bit setting */
3626                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
3627                 if (ret_val)
3628                         return ret_val;
3629
3630                 if (kum_cfg & E1000_NVM_K1_ENABLE)
3631                         dev_spec->nvm_k1_enabled = true;
3632                 else
3633                         dev_spec->nvm_k1_enabled = false;
3634         }
3635
3636         ctrl = er32(CTRL);
3637
3638         if (!hw->phy.ops.check_reset_block(hw)) {
3639                 /* Full-chip reset requires MAC and PHY reset at the same
3640                  * time to make sure the interface between MAC and the
3641                  * external PHY is reset.
3642                  */
3643                 ctrl |= E1000_CTRL_PHY_RST;
3644
3645                 /* Gate automatic PHY configuration by hardware on
3646                  * non-managed 82579
3647                  */
3648                 if ((hw->mac.type == e1000_pch2lan) &&
3649                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3650                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3651         }
3652         ret_val = e1000_acquire_swflag_ich8lan(hw);
3653         e_dbg("Issuing a global reset to ich8lan\n");
3654         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3655         /* cannot issue a flush here because it hangs the hardware */
3656         msleep(20);
3657
3658         /* Set Phy Config Counter to 50msec */
3659         if (hw->mac.type == e1000_pch2lan) {
3660                 reg = er32(FEXTNVM3);
3661                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
3662                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
3663                 ew32(FEXTNVM3, reg);
3664         }
3665
3666         if (!ret_val)
3667                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
3668
3669         if (ctrl & E1000_CTRL_PHY_RST) {
3670                 ret_val = hw->phy.ops.get_cfg_done(hw);
3671                 if (ret_val)
3672                         return ret_val;
3673
3674                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3675                 if (ret_val)
3676                         return ret_val;
3677         }
3678
3679         /* For PCH, this write will make sure that any noise
3680          * will be detected as a CRC error and be dropped rather than show up
3681          * as a bad packet to the DMA engine.
3682          */
3683         if (hw->mac.type == e1000_pchlan)
3684                 ew32(CRC_OFFSET, 0x65656565);
3685
3686         ew32(IMC, 0xffffffff);
3687         er32(ICR);
3688
3689         reg = er32(KABGTXD);
3690         reg |= E1000_KABGTXD_BGSQLBIAS;
3691         ew32(KABGTXD, reg);
3692
3693         return 0;
3694 }
3695
3696 /**
3697  *  e1000_init_hw_ich8lan - Initialize the hardware
3698  *  @hw: pointer to the HW structure
3699  *
3700  *  Prepares the hardware for transmit and receive by doing the following:
3701  *   - initialize hardware bits
3702  *   - initialize LED identification
3703  *   - setup receive address registers
3704  *   - setup flow control
3705  *   - setup transmit descriptors
3706  *   - clear statistics
3707  **/
3708 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3709 {
3710         struct e1000_mac_info *mac = &hw->mac;
3711         u32 ctrl_ext, txdctl, snoop;
3712         s32 ret_val;
3713         u16 i;
3714
3715         e1000_initialize_hw_bits_ich8lan(hw);
3716
3717         /* Initialize identification LED */
3718         ret_val = mac->ops.id_led_init(hw);
3719         /* An error is not fatal and we should not stop init due to this */
3720         if (ret_val)
3721                 e_dbg("Error initializing identification LED\n");
3722
3723         /* Setup the receive address. */
3724         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3725
3726         /* Zero out the Multicast HASH table */
3727         e_dbg("Zeroing the MTA\n");
3728         for (i = 0; i < mac->mta_reg_count; i++)
3729                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3730
3731         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
3732          * the ME.  Disable wakeup by clearing the host wakeup bit.
3733          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3734          */
3735         if (hw->phy.type == e1000_phy_82578) {
3736                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3737                 i &= ~BM_WUC_HOST_WU_BIT;
3738                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
3739                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3740                 if (ret_val)
3741                         return ret_val;
3742         }
3743
3744         /* Setup link and flow control */
3745         ret_val = mac->ops.setup_link(hw);
3746
3747         /* Set the transmit descriptor write-back policy for both queues */
3748         txdctl = er32(TXDCTL(0));
3749         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
3750                   E1000_TXDCTL_FULL_TX_DESC_WB);
3751         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
3752                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
3753         ew32(TXDCTL(0), txdctl);
3754         txdctl = er32(TXDCTL(1));
3755         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
3756                   E1000_TXDCTL_FULL_TX_DESC_WB);
3757         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
3758                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
3759         ew32(TXDCTL(1), txdctl);
3760
3761         /* ICH8 has opposite polarity of no_snoop bits.
3762          * By default, we should use snoop behavior.
3763          */
3764         if (mac->type == e1000_ich8lan)
3765                 snoop = PCIE_ICH8_SNOOP_ALL;
3766         else
3767                 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
3768         e1000e_set_pcie_no_snoop(hw, snoop);
3769
3770         ctrl_ext = er32(CTRL_EXT);
3771         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3772         ew32(CTRL_EXT, ctrl_ext);
3773
3774         /* Clear all of the statistics registers (clear on read).  It is
3775          * important that we do this after we have tried to establish link
3776          * because the symbol error count will increment wildly if there
3777          * is no link.
3778          */
3779         e1000_clear_hw_cntrs_ich8lan(hw);
3780
3781         return ret_val;
3782 }
3783
3784 /**
3785  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3786  *  @hw: pointer to the HW structure
3787  *
3788  *  Sets/Clears required hardware bits necessary for correctly setting up the
3789  *  hardware for transmit and receive.
3790  **/
3791 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3792 {
3793         u32 reg;
3794
3795         /* Extended Device Control */
3796         reg = er32(CTRL_EXT);
3797         reg |= (1 << 22);
3798         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3799         if (hw->mac.type >= e1000_pchlan)
3800                 reg |= E1000_CTRL_EXT_PHYPDEN;
3801         ew32(CTRL_EXT, reg);
3802
3803         /* Transmit Descriptor Control 0 */
3804         reg = er32(TXDCTL(0));
3805         reg |= (1 << 22);
3806         ew32(TXDCTL(0), reg);
3807
3808         /* Transmit Descriptor Control 1 */
3809         reg = er32(TXDCTL(1));
3810         reg |= (1 << 22);
3811         ew32(TXDCTL(1), reg);
3812
3813         /* Transmit Arbitration Control 0 */
3814         reg = er32(TARC(0));
3815         if (hw->mac.type == e1000_ich8lan)
3816                 reg |= (1 << 28) | (1 << 29);
3817         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3818         ew32(TARC(0), reg);
3819
3820         /* Transmit Arbitration Control 1 */
3821         reg = er32(TARC(1));
3822         if (er32(TCTL) & E1000_TCTL_MULR)
3823                 reg &= ~(1 << 28);
3824         else
3825                 reg |= (1 << 28);
3826         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3827         ew32(TARC(1), reg);
3828
3829         /* Device Status */
3830         if (hw->mac.type == e1000_ich8lan) {
3831                 reg = er32(STATUS);
3832                 reg &= ~(1 << 31);
3833                 ew32(STATUS, reg);
3834         }
3835
3836         /* work-around descriptor data corruption issue during nfs v2 udp
3837          * traffic, just disable the nfs filtering capability
3838          */
3839         reg = er32(RFCTL);
3840         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3841
3842         /* Disable IPv6 extension header parsing because some malformed
3843          * IPv6 headers can hang the Rx.
3844          */
3845         if (hw->mac.type == e1000_ich8lan)
3846                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
3847         ew32(RFCTL, reg);
3848
3849         /* Enable ECC on Lynxpoint */
3850         if (hw->mac.type == e1000_pch_lpt) {
3851                 reg = er32(PBECCSTS);
3852                 reg |= E1000_PBECCSTS_ECC_ENABLE;
3853                 ew32(PBECCSTS, reg);
3854
3855                 reg = er32(CTRL);
3856                 reg |= E1000_CTRL_MEHE;
3857                 ew32(CTRL, reg);
3858         }
3859 }
3860
3861 /**
3862  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3863  *  @hw: pointer to the HW structure
3864  *
3865  *  Determines which flow control settings to use, then configures flow
3866  *  control.  Calls the appropriate media-specific link configuration
3867  *  function.  Assuming the adapter has a valid link partner, a valid link
3868  *  should be established.  Assumes the hardware has previously been reset
3869  *  and the transmitter and receiver are not enabled.
3870  **/
3871 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3872 {
3873         s32 ret_val;
3874
3875         if (hw->phy.ops.check_reset_block(hw))
3876                 return 0;
3877
3878         /* ICH parts do not have a word in the NVM to determine
3879          * the default flow control setting, so we explicitly
3880          * set it to full.
3881          */
3882         if (hw->fc.requested_mode == e1000_fc_default) {
3883                 /* Workaround h/w hang when Tx flow control enabled */
3884                 if (hw->mac.type == e1000_pchlan)
3885                         hw->fc.requested_mode = e1000_fc_rx_pause;
3886                 else
3887                         hw->fc.requested_mode = e1000_fc_full;
3888         }
3889
3890         /* Save off the requested flow control mode for use later.  Depending
3891          * on the link partner's capabilities, we may or may not use this mode.
3892          */
3893         hw->fc.current_mode = hw->fc.requested_mode;
3894
3895         e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
3896
3897         /* Continue to configure the copper link. */
3898         ret_val = hw->mac.ops.setup_physical_interface(hw);
3899         if (ret_val)
3900                 return ret_val;
3901
3902         ew32(FCTTV, hw->fc.pause_time);
3903         if ((hw->phy.type == e1000_phy_82578) ||
3904             (hw->phy.type == e1000_phy_82579) ||
3905             (hw->phy.type == e1000_phy_i217) ||
3906             (hw->phy.type == e1000_phy_82577)) {
3907                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3908
3909                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3910                                    hw->fc.pause_time);
3911                 if (ret_val)
3912                         return ret_val;
3913         }
3914
3915         return e1000e_set_fc_watermarks(hw);
3916 }
3917
3918 /**
3919  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3920  *  @hw: pointer to the HW structure
3921  *
3922  *  Configures the kumeran interface to the PHY to wait the appropriate time
3923  *  when polling the PHY, then call the generic setup_copper_link to finish
3924  *  configuring the copper link.
3925  **/
3926 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3927 {
3928         u32 ctrl;
3929         s32 ret_val;
3930         u16 reg_data;
3931
3932         ctrl = er32(CTRL);
3933         ctrl |= E1000_CTRL_SLU;
3934         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3935         ew32(CTRL, ctrl);
3936
3937         /* Set the mac to wait the maximum time between each iteration
3938          * and increase the max iterations when polling the phy;
3939          * this fixes erroneous timeouts at 10Mbps.
3940          */
3941         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3942         if (ret_val)
3943                 return ret_val;
3944         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3945                                        &reg_data);
3946         if (ret_val)
3947                 return ret_val;
3948         reg_data |= 0x3F;
3949         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3950                                         reg_data);
3951         if (ret_val)
3952                 return ret_val;
3953
3954         switch (hw->phy.type) {
3955         case e1000_phy_igp_3:
3956                 ret_val = e1000e_copper_link_setup_igp(hw);
3957                 if (ret_val)
3958                         return ret_val;
3959                 break;
3960         case e1000_phy_bm:
3961         case e1000_phy_82578:
3962                 ret_val = e1000e_copper_link_setup_m88(hw);
3963                 if (ret_val)
3964                         return ret_val;
3965                 break;
3966         case e1000_phy_82577:
3967         case e1000_phy_82579:
3968                 ret_val = e1000_copper_link_setup_82577(hw);
3969                 if (ret_val)
3970                         return ret_val;
3971                 break;
3972         case e1000_phy_ife:
3973                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3974                 if (ret_val)
3975                         return ret_val;
3976
3977                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3978
3979                 switch (hw->phy.mdix) {
3980                 case 1:
3981                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3982                         break;
3983                 case 2:
3984                         reg_data |= IFE_PMC_FORCE_MDIX;
3985                         break;
3986                 case 0:
3987                 default:
3988                         reg_data |= IFE_PMC_AUTO_MDIX;
3989                         break;
3990                 }
3991                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3992                 if (ret_val)
3993                         return ret_val;
3994                 break;
3995         default:
3996                 break;
3997         }
3998
3999         return e1000e_setup_copper_link(hw);
4000 }
4001
4002 /**
4003  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
4004  *  @hw: pointer to the HW structure
4005  *
4006  *  Calls the PHY specific link setup function and then calls the
4007  *  generic setup_copper_link to finish configuring the link for
4008  *  Lynxpoint PCH devices
4009  **/
4010 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
4011 {
4012         u32 ctrl;
4013         s32 ret_val;
4014
4015         ctrl = er32(CTRL);
4016         ctrl |= E1000_CTRL_SLU;
4017         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4018         ew32(CTRL, ctrl);
4019
4020         ret_val = e1000_copper_link_setup_82577(hw);
4021         if (ret_val)
4022                 return ret_val;
4023
4024         return e1000e_setup_copper_link(hw);
4025 }
4026
4027 /**
4028  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4029  *  @hw: pointer to the HW structure
4030  *  @speed: pointer to store current link speed
4031  *  @duplex: pointer to store the current link duplex
4032  *
4033  *  Calls the generic get_speed_and_duplex to retrieve the current link
4034  *  information and then calls the Kumeran lock loss workaround for links at
4035  *  gigabit speeds.
4036  **/
4037 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4038                                           u16 *duplex)
4039 {
4040         s32 ret_val;
4041
4042         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
4043         if (ret_val)
4044                 return ret_val;
4045
4046         if ((hw->mac.type == e1000_ich8lan) &&
4047             (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
4048                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4049         }
4050
4051         return ret_val;
4052 }
4053
4054 /**
4055  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4056  *  @hw: pointer to the HW structure
4057  *
4058  *  Work-around for 82566 Kumeran PCS lock loss:
4059  *  On link status change (i.e. PCI reset, speed change) and link is up and
4060  *  speed is gigabit-
4061  *    0) if workaround is optionally disabled do nothing
4062  *    1) wait 1ms for Kumeran link to come up
4063  *    2) check Kumeran Diagnostic register PCS lock loss bit
4064  *    3) if not set the link is locked (all is good), otherwise...
4065  *    4) reset the PHY
4066  *    5) repeat up to 10 times
4067  *  Note: this is only called for IGP3 copper when speed is 1gb.
4068  **/
4069 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4070 {
4071         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4072         u32 phy_ctrl;
4073         s32 ret_val;
4074         u16 i, data;
4075         bool link;
4076
4077         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4078                 return 0;
4079
4080         /* Make sure link is up before proceeding.  If not just return.
4081          * Attempting this while link is negotiating fouled up link
4082          * stability
4083          */
4084         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
4085         if (!link)
4086                 return 0;
4087
4088         for (i = 0; i < 10; i++) {
4089                 /* read once to clear */
4090                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
4091                 if (ret_val)
4092                         return ret_val;
4093                 /* and again to get new status */
4094                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
4095                 if (ret_val)
4096                         return ret_val;
4097
4098                 /* check for PCS lock */
4099                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4100                         return 0;
4101
4102                 /* Issue PHY reset */
4103                 e1000_phy_hw_reset(hw);
4104                 mdelay(5);
4105         }
4106         /* Disable GigE link negotiation */
4107         phy_ctrl = er32(PHY_CTRL);
4108         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4109                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4110         ew32(PHY_CTRL, phy_ctrl);
4111
4112         /* Call gig speed drop workaround on Gig disable before accessing
4113          * any PHY registers
4114          */
4115         e1000e_gig_downshift_workaround_ich8lan(hw);
4116
4117         /* unable to acquire PCS lock */
4118         return -E1000_ERR_PHY;
4119 }
4120
4121 /**
4122  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4123  *  @hw: pointer to the HW structure
4124  *  @state: boolean value used to set the current Kumeran workaround state
4125  *
4126  *  If ICH8, set the current Kumeran workaround state (enabled - true
4127  *  /disabled - false).
4128  **/
4129 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4130                                                   bool state)
4131 {
4132         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4133
4134         if (hw->mac.type != e1000_ich8lan) {
4135                 e_dbg("Workaround applies to ICH8 only.\n");
4136                 return;
4137         }
4138
4139         dev_spec->kmrn_lock_loss_workaround_enabled = state;
4140 }
4141
4142 /**
4143  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4144  *  @hw: pointer to the HW structure
4145  *
4146  *  Workaround for 82566 power-down on D3 entry:
4147  *    1) disable gigabit link
4148  *    2) write VR power-down enable
4149  *    3) read it back
4150  *  Continue if successful, else issue LCD reset and repeat
4151  **/
4152 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4153 {
4154         u32 reg;
4155         u16 data;
4156         u8 retry = 0;
4157
4158         if (hw->phy.type != e1000_phy_igp_3)
4159                 return;
4160
4161         /* Try the workaround twice (if needed) */
4162         do {
4163                 /* Disable link */
4164                 reg = er32(PHY_CTRL);
4165                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4166                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4167                 ew32(PHY_CTRL, reg);
4168
4169                 /* Call gig speed drop workaround on Gig disable before
4170                  * accessing any PHY registers
4171                  */
4172                 if (hw->mac.type == e1000_ich8lan)
4173                         e1000e_gig_downshift_workaround_ich8lan(hw);
4174
4175                 /* Write VR power-down enable */
4176                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4177                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4178                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4179
4180                 /* Read it back and test */
4181                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4182                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4183                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4184                         break;
4185
4186                 /* Issue PHY reset and repeat at most one more time */
4187                 reg = er32(CTRL);
4188                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
4189                 retry++;
4190         } while (retry);
4191 }
4192
4193 /**
4194  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4195  *  @hw: pointer to the HW structure
4196  *
4197  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4198  *  LPLU, Gig disable, MDIC PHY reset):
4199  *    1) Set Kumeran Near-end loopback
4200  *    2) Clear Kumeran Near-end loopback
4201  *  Should only be called for ICH8[m] devices with any 1G Phy.
4202  **/
4203 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4204 {
4205         s32 ret_val;
4206         u16 reg_data;
4207
4208         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
4209                 return;
4210
4211         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4212                                        &reg_data);
4213         if (ret_val)
4214                 return;
4215         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4216         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4217                                         reg_data);
4218         if (ret_val)
4219                 return;
4220         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4221         e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
4222 }
4223
4224 /**
4225  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4226  *  @hw: pointer to the HW structure
4227  *
4228  *  During S0 to Sx transition, it is possible the link remains at gig
4229  *  instead of negotiating to a lower speed.  Before going to Sx, set
4230  *  'Gig Disable' to force link speed negotiation to a lower speed based on
4231  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
4232  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4233  *  needs to be written.
4234  *  Parts that support (and are linked to a partner which support) EEE in
4235  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4236  *  than 10Mbps w/o EEE.
4237  **/
4238 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4239 {
4240         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4241         u32 phy_ctrl;
4242         s32 ret_val;
4243
4244         phy_ctrl = er32(PHY_CTRL);
4245         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4246
4247         if (hw->phy.type == e1000_phy_i217) {
4248                 u16 phy_reg, device_id = hw->adapter->pdev->device;
4249
4250                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4251                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4252                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4253                     (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4254                         u32 fextnvm6 = er32(FEXTNVM6);
4255
4256                         ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4257                 }
4258
4259                 ret_val = hw->phy.ops.acquire(hw);
4260                 if (ret_val)
4261                         goto out;
4262
4263                 if (!dev_spec->eee_disable) {
4264                         u16 eee_advert;
4265
4266                         ret_val =
4267                             e1000_read_emi_reg_locked(hw,
4268                                                       I217_EEE_ADVERTISEMENT,
4269                                                       &eee_advert);
4270                         if (ret_val)
4271                                 goto release;
4272
4273                         /* Disable LPLU if both link partners support 100BaseT
4274                          * EEE and 100Full is advertised on both ends of the
4275                          * link.
4276                          */
4277                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4278                             (dev_spec->eee_lp_ability &
4279                              I82579_EEE_100_SUPPORTED) &&
4280                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
4281                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4282                                               E1000_PHY_CTRL_NOND0A_LPLU);
4283                 }
4284
4285                 /* For i217 Intel Rapid Start Technology support,
4286                  * when the system is going into Sx and no manageability engine
4287                  * is present, the driver must configure proxy to reset only on
4288                  * power good.  LPI (Low Power Idle) state must also reset only
4289                  * on power good, as well as the MTA (Multicast table array).
4290                  * The SMBus release must also be disabled on LCD reset.
4291                  */
4292                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4293                         /* Enable proxy to reset only on power good. */
4294                         e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
4295                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4296                         e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
4297
4298                         /* Set bit enable LPI (EEE) to reset only on
4299                          * power good.
4300                          */
4301                         e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
4302                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4303                         e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
4304
4305                         /* Disable the SMB release on LCD reset. */
4306                         e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4307                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4308                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4309                 }
4310
4311                 /* Enable MTA to reset for Intel Rapid Start Technology
4312                  * Support
4313                  */
4314                 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4315                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4316                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4317
4318 release:
4319                 hw->phy.ops.release(hw);
4320         }
4321 out:
4322         ew32(PHY_CTRL, phy_ctrl);
4323
4324         if (hw->mac.type == e1000_ich8lan)
4325                 e1000e_gig_downshift_workaround_ich8lan(hw);
4326
4327         if (hw->mac.type >= e1000_pchlan) {
4328                 e1000_oem_bits_config_ich8lan(hw, false);
4329
4330                 /* Reset PHY to activate OEM bits on 82577/8 */
4331                 if (hw->mac.type == e1000_pchlan)
4332                         e1000e_phy_hw_reset_generic(hw);
4333
4334                 ret_val = hw->phy.ops.acquire(hw);
4335                 if (ret_val)
4336                         return;
4337                 e1000_write_smbus_addr(hw);
4338                 hw->phy.ops.release(hw);
4339         }
4340 }
4341
4342 /**
4343  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4344  *  @hw: pointer to the HW structure
4345  *
4346  *  During Sx to S0 transitions on non-managed devices or managed devices
4347  *  on which PHY resets are not blocked, if the PHY registers cannot be
4348  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
4349  *  the PHY.
4350  *  On i217, setup Intel Rapid Start Technology.
4351  **/
4352 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4353 {
4354         s32 ret_val;
4355
4356         if (hw->mac.type < e1000_pch2lan)
4357                 return;
4358
4359         ret_val = e1000_init_phy_workarounds_pchlan(hw);
4360         if (ret_val) {
4361                 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
4362                 return;
4363         }
4364
4365         /* For i217 Intel Rapid Start Technology support when the system
4366          * is transitioning from Sx and no manageability engine is present
4367          * configure SMBus to restore on reset, disable proxy, and enable
4368          * the reset on MTA (Multicast table array).
4369          */
4370         if (hw->phy.type == e1000_phy_i217) {
4371                 u16 phy_reg;
4372
4373                 ret_val = hw->phy.ops.acquire(hw);
4374                 if (ret_val) {
4375                         e_dbg("Failed to setup iRST\n");
4376                         return;
4377                 }
4378
4379                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4380                         /* Restore clear on SMB if no manageability engine
4381                          * is present
4382                          */
4383                         ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4384                         if (ret_val)
4385                                 goto release;
4386                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
4387                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4388
4389                         /* Disable Proxy */
4390                         e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
4391                 }
4392                 /* Enable reset on MTA */
4393                 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4394                 if (ret_val)
4395                         goto release;
4396                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
4397                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4398 release:
4399                 if (ret_val)
4400                         e_dbg("Error %d in resume workarounds\n", ret_val);
4401                 hw->phy.ops.release(hw);
4402         }
4403 }
4404
4405 /**
4406  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
4407  *  @hw: pointer to the HW structure
4408  *
4409  *  Return the LED back to the default configuration.
4410  **/
4411 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4412 {
4413         if (hw->phy.type == e1000_phy_ife)
4414                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
4415
4416         ew32(LEDCTL, hw->mac.ledctl_default);
4417         return 0;
4418 }
4419
4420 /**
4421  *  e1000_led_on_ich8lan - Turn LEDs on
4422  *  @hw: pointer to the HW structure
4423  *
4424  *  Turn on the LEDs.
4425  **/
4426 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
4427 {
4428         if (hw->phy.type == e1000_phy_ife)
4429                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4430                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
4431
4432         ew32(LEDCTL, hw->mac.ledctl_mode2);
4433         return 0;
4434 }
4435
4436 /**
4437  *  e1000_led_off_ich8lan - Turn LEDs off
4438  *  @hw: pointer to the HW structure
4439  *
4440  *  Turn off the LEDs.
4441  **/
4442 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
4443 {
4444         if (hw->phy.type == e1000_phy_ife)
4445                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4446                                 (IFE_PSCL_PROBE_MODE |
4447                                  IFE_PSCL_PROBE_LEDS_OFF));
4448
4449         ew32(LEDCTL, hw->mac.ledctl_mode1);
4450         return 0;
4451 }
4452
4453 /**
4454  *  e1000_setup_led_pchlan - Configures SW controllable LED
4455  *  @hw: pointer to the HW structure
4456  *
4457  *  This prepares the SW controllable LED for use.
4458  **/
4459 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
4460 {
4461         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
4462 }
4463
4464 /**
4465  *  e1000_cleanup_led_pchlan - Restore the default LED operation
4466  *  @hw: pointer to the HW structure
4467  *
4468  *  Return the LED back to the default configuration.
4469  **/
4470 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4471 {
4472         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
4473 }
4474
4475 /**
4476  *  e1000_led_on_pchlan - Turn LEDs on
4477  *  @hw: pointer to the HW structure
4478  *
4479  *  Turn on the LEDs.
4480  **/
4481 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
4482 {
4483         u16 data = (u16)hw->mac.ledctl_mode2;
4484         u32 i, led;
4485
4486         /* If no link, then turn LED on by setting the invert bit
4487          * for each LED that's mode is "link_up" in ledctl_mode2.
4488          */
4489         if (!(er32(STATUS) & E1000_STATUS_LU)) {
4490                 for (i = 0; i < 3; i++) {
4491                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4492                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4493                             E1000_LEDCTL_MODE_LINK_UP)
4494                                 continue;
4495                         if (led & E1000_PHY_LED0_IVRT)
4496                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4497                         else
4498                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4499                 }
4500         }
4501
4502         return e1e_wphy(hw, HV_LED_CONFIG, data);
4503 }
4504
4505 /**
4506  *  e1000_led_off_pchlan - Turn LEDs off
4507  *  @hw: pointer to the HW structure
4508  *
4509  *  Turn off the LEDs.
4510  **/
4511 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
4512 {
4513         u16 data = (u16)hw->mac.ledctl_mode1;
4514         u32 i, led;
4515
4516         /* If no link, then turn LED off by clearing the invert bit
4517          * for each LED that's mode is "link_up" in ledctl_mode1.
4518          */
4519         if (!(er32(STATUS) & E1000_STATUS_LU)) {
4520                 for (i = 0; i < 3; i++) {
4521                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4522                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4523                             E1000_LEDCTL_MODE_LINK_UP)
4524                                 continue;
4525                         if (led & E1000_PHY_LED0_IVRT)
4526                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4527                         else
4528                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4529                 }
4530         }
4531
4532         return e1e_wphy(hw, HV_LED_CONFIG, data);
4533 }
4534
4535 /**
4536  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
4537  *  @hw: pointer to the HW structure
4538  *
4539  *  Read appropriate register for the config done bit for completion status
4540  *  and configure the PHY through s/w for EEPROM-less parts.
4541  *
4542  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
4543  *  config done bit, so only an error is logged and continues.  If we were
4544  *  to return with error, EEPROM-less silicon would not be able to be reset
4545  *  or change link.
4546  **/
4547 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4548 {
4549         s32 ret_val = 0;
4550         u32 bank = 0;
4551         u32 status;
4552
4553         e1000e_get_cfg_done_generic(hw);
4554
4555         /* Wait for indication from h/w that it has completed basic config */
4556         if (hw->mac.type >= e1000_ich10lan) {
4557                 e1000_lan_init_done_ich8lan(hw);
4558         } else {
4559                 ret_val = e1000e_get_auto_rd_done(hw);
4560                 if (ret_val) {
4561                         /* When auto config read does not complete, do not
4562                          * return with an error. This can happen in situations
4563                          * where there is no eeprom and prevents getting link.
4564                          */
4565                         e_dbg("Auto Read Done did not complete\n");
4566                         ret_val = 0;
4567                 }
4568         }
4569
4570         /* Clear PHY Reset Asserted bit */
4571         status = er32(STATUS);
4572         if (status & E1000_STATUS_PHYRA)
4573                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
4574         else
4575                 e_dbg("PHY Reset Asserted not set - needs delay\n");
4576
4577         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
4578         if (hw->mac.type <= e1000_ich9lan) {
4579                 if (!(er32(EECD) & E1000_EECD_PRES) &&
4580                     (hw->phy.type == e1000_phy_igp_3)) {
4581                         e1000e_phy_init_script_igp3(hw);
4582                 }
4583         } else {
4584                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
4585                         /* Maybe we should do a basic PHY config */
4586                         e_dbg("EEPROM not present\n");
4587                         ret_val = -E1000_ERR_CONFIG;
4588                 }
4589         }
4590
4591         return ret_val;
4592 }
4593
4594 /**
4595  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4596  * @hw: pointer to the HW structure
4597  *
4598  * In the case of a PHY power down to save power, or to turn off link during a
4599  * driver unload, or wake on lan is not enabled, remove the link.
4600  **/
4601 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
4602 {
4603         /* If the management interface is not enabled, then power down */
4604         if (!(hw->mac.ops.check_mng_mode(hw) ||
4605               hw->phy.ops.check_reset_block(hw)))
4606                 e1000_power_down_phy_copper(hw);
4607 }
4608
4609 /**
4610  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4611  *  @hw: pointer to the HW structure
4612  *
4613  *  Clears hardware counters specific to the silicon family and calls
4614  *  clear_hw_cntrs_generic to clear all general purpose counters.
4615  **/
4616 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4617 {
4618         u16 phy_data;
4619         s32 ret_val;
4620
4621         e1000e_clear_hw_cntrs_base(hw);
4622
4623         er32(ALGNERRC);
4624         er32(RXERRC);
4625         er32(TNCRS);
4626         er32(CEXTERR);
4627         er32(TSCTC);
4628         er32(TSCTFC);
4629
4630         er32(MGTPRC);
4631         er32(MGTPDC);
4632         er32(MGTPTC);
4633
4634         er32(IAC);
4635         er32(ICRXOC);
4636
4637         /* Clear PHY statistics registers */
4638         if ((hw->phy.type == e1000_phy_82578) ||
4639             (hw->phy.type == e1000_phy_82579) ||
4640             (hw->phy.type == e1000_phy_i217) ||
4641             (hw->phy.type == e1000_phy_82577)) {
4642                 ret_val = hw->phy.ops.acquire(hw);
4643                 if (ret_val)
4644                         return;
4645                 ret_val = hw->phy.ops.set_page(hw,
4646                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
4647                 if (ret_val)
4648                         goto release;
4649                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4650                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4651                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4652                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4653                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4654                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4655                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4656                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4657                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4658                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4659                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4660                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4661                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4662                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4663 release:
4664                 hw->phy.ops.release(hw);
4665         }
4666 }
4667
4668 static const struct e1000_mac_operations ich8_mac_ops = {
4669         /* check_mng_mode dependent on mac type */
4670         .check_for_link         = e1000_check_for_copper_link_ich8lan,
4671         /* cleanup_led dependent on mac type */
4672         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
4673         .get_bus_info           = e1000_get_bus_info_ich8lan,
4674         .set_lan_id             = e1000_set_lan_id_single_port,
4675         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
4676         /* led_on dependent on mac type */
4677         /* led_off dependent on mac type */
4678         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
4679         .reset_hw               = e1000_reset_hw_ich8lan,
4680         .init_hw                = e1000_init_hw_ich8lan,
4681         .setup_link             = e1000_setup_link_ich8lan,
4682         .setup_physical_interface = e1000_setup_copper_link_ich8lan,
4683         /* id_led_init dependent on mac type */
4684         .config_collision_dist  = e1000e_config_collision_dist_generic,
4685         .rar_set                = e1000e_rar_set_generic,
4686 };
4687
4688 static const struct e1000_phy_operations ich8_phy_ops = {
4689         .acquire                = e1000_acquire_swflag_ich8lan,
4690         .check_reset_block      = e1000_check_reset_block_ich8lan,
4691         .commit                 = NULL,
4692         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
4693         .get_cable_length       = e1000e_get_cable_length_igp_2,
4694         .read_reg               = e1000e_read_phy_reg_igp,
4695         .release                = e1000_release_swflag_ich8lan,
4696         .reset                  = e1000_phy_hw_reset_ich8lan,
4697         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
4698         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
4699         .write_reg              = e1000e_write_phy_reg_igp,
4700 };
4701
4702 static const struct e1000_nvm_operations ich8_nvm_ops = {
4703         .acquire                = e1000_acquire_nvm_ich8lan,
4704         .read                   = e1000_read_nvm_ich8lan,
4705         .release                = e1000_release_nvm_ich8lan,
4706         .reload                 = e1000e_reload_nvm_generic,
4707         .update                 = e1000_update_nvm_checksum_ich8lan,
4708         .valid_led_default      = e1000_valid_led_default_ich8lan,
4709         .validate               = e1000_validate_nvm_checksum_ich8lan,
4710         .write                  = e1000_write_nvm_ich8lan,
4711 };
4712
4713 const struct e1000_info e1000_ich8_info = {
4714         .mac                    = e1000_ich8lan,
4715         .flags                  = FLAG_HAS_WOL
4716                                   | FLAG_IS_ICH
4717                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4718                                   | FLAG_HAS_AMT
4719                                   | FLAG_HAS_FLASH
4720                                   | FLAG_APME_IN_WUC,
4721         .pba                    = 8,
4722         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
4723         .get_variants           = e1000_get_variants_ich8lan,
4724         .mac_ops                = &ich8_mac_ops,
4725         .phy_ops                = &ich8_phy_ops,
4726         .nvm_ops                = &ich8_nvm_ops,
4727 };
4728
4729 const struct e1000_info e1000_ich9_info = {
4730         .mac                    = e1000_ich9lan,
4731         .flags                  = FLAG_HAS_JUMBO_FRAMES
4732                                   | FLAG_IS_ICH
4733                                   | FLAG_HAS_WOL
4734                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4735                                   | FLAG_HAS_AMT
4736                                   | FLAG_HAS_FLASH
4737                                   | FLAG_APME_IN_WUC,
4738         .pba                    = 18,
4739         .max_hw_frame_size      = DEFAULT_JUMBO,
4740         .get_variants           = e1000_get_variants_ich8lan,
4741         .mac_ops                = &ich8_mac_ops,
4742         .phy_ops                = &ich8_phy_ops,
4743         .nvm_ops                = &ich8_nvm_ops,
4744 };
4745
4746 const struct e1000_info e1000_ich10_info = {
4747         .mac                    = e1000_ich10lan,
4748         .flags                  = FLAG_HAS_JUMBO_FRAMES
4749                                   | FLAG_IS_ICH
4750                                   | FLAG_HAS_WOL
4751                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4752                                   | FLAG_HAS_AMT
4753                                   | FLAG_HAS_FLASH
4754                                   | FLAG_APME_IN_WUC,
4755         .pba                    = 18,
4756         .max_hw_frame_size      = DEFAULT_JUMBO,
4757         .get_variants           = e1000_get_variants_ich8lan,
4758         .mac_ops                = &ich8_mac_ops,
4759         .phy_ops                = &ich8_phy_ops,
4760         .nvm_ops                = &ich8_nvm_ops,
4761 };
4762
4763 const struct e1000_info e1000_pch_info = {
4764         .mac                    = e1000_pchlan,
4765         .flags                  = FLAG_IS_ICH
4766                                   | FLAG_HAS_WOL
4767                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4768                                   | FLAG_HAS_AMT
4769                                   | FLAG_HAS_FLASH
4770                                   | FLAG_HAS_JUMBO_FRAMES
4771                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4772                                   | FLAG_APME_IN_WUC,
4773         .flags2                 = FLAG2_HAS_PHY_STATS,
4774         .pba                    = 26,
4775         .max_hw_frame_size      = 4096,
4776         .get_variants           = e1000_get_variants_ich8lan,
4777         .mac_ops                = &ich8_mac_ops,
4778         .phy_ops                = &ich8_phy_ops,
4779         .nvm_ops                = &ich8_nvm_ops,
4780 };
4781
4782 const struct e1000_info e1000_pch2_info = {
4783         .mac                    = e1000_pch2lan,
4784         .flags                  = FLAG_IS_ICH
4785                                   | FLAG_HAS_WOL
4786                                   | FLAG_HAS_HW_TIMESTAMP
4787                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4788                                   | FLAG_HAS_AMT
4789                                   | FLAG_HAS_FLASH
4790                                   | FLAG_HAS_JUMBO_FRAMES
4791                                   | FLAG_APME_IN_WUC,
4792         .flags2                 = FLAG2_HAS_PHY_STATS
4793                                   | FLAG2_HAS_EEE,
4794         .pba                    = 26,
4795         .max_hw_frame_size      = 9018,
4796         .get_variants           = e1000_get_variants_ich8lan,
4797         .mac_ops                = &ich8_mac_ops,
4798         .phy_ops                = &ich8_phy_ops,
4799         .nvm_ops                = &ich8_nvm_ops,
4800 };
4801
4802 const struct e1000_info e1000_pch_lpt_info = {
4803         .mac                    = e1000_pch_lpt,
4804         .flags                  = FLAG_IS_ICH
4805                                   | FLAG_HAS_WOL
4806                                   | FLAG_HAS_HW_TIMESTAMP
4807                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4808                                   | FLAG_HAS_AMT
4809                                   | FLAG_HAS_FLASH
4810                                   | FLAG_HAS_JUMBO_FRAMES
4811                                   | FLAG_APME_IN_WUC,
4812         .flags2                 = FLAG2_HAS_PHY_STATS
4813                                   | FLAG2_HAS_EEE,
4814         .pba                    = 26,
4815         .max_hw_frame_size      = 9018,
4816         .get_variants           = e1000_get_variants_ich8lan,
4817         .mac_ops                = &ich8_mac_ops,
4818         .phy_ops                = &ich8_phy_ops,
4819         .nvm_ops                = &ich8_nvm_ops,
4820 };