drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /* 82562G 10/100 Network Connection
  30  * 82562G-2 10/100 Network Connection
  31  * 82562GT 10/100 Network Connection
  32  * 82562GT-2 10/100 Network Connection
  33  * 82562V 10/100 Network Connection
  34  * 82562V-2 10/100 Network Connection
  35  * 82566DC-2 Gigabit Network Connection
  36  * 82566DC Gigabit Network Connection
  37  * 82566DM-2 Gigabit Network Connection
  38  * 82566DM Gigabit Network Connection
  39  * 82566MC Gigabit Network Connection
  40  * 82566MM Gigabit Network Connection
  41  * 82567LM Gigabit Network Connection
  42  * 82567LF Gigabit Network Connection
  43  * 82567V Gigabit Network Connection
  44  * 82567LM-2 Gigabit Network Connection
  45  * 82567LF-2 Gigabit Network Connection
  46  * 82567V-2 Gigabit Network Connection
  47  * 82567LF-3 Gigabit Network Connection
  48  * 82567LM-3 Gigabit Network Connection
  49  * 82567LM-4 Gigabit Network Connection
  50  * 82577LM Gigabit Network Connection
  51  * 82577LC Gigabit Network Connection
  52  * 82578DM Gigabit Network Connection
  53  * 82578DC Gigabit Network Connection
  54  * 82579LM Gigabit Network Connection
  55  * 82579V Gigabit Network Connection
  56  */
  57
  58 #include "e1000.h"
  59
  60 #define ICH_FLASH_GFPREG                0x0000
  61 #define ICH_FLASH_HSFSTS                0x0004
  62 #define ICH_FLASH_HSFCTL                0x0006
  63 #define ICH_FLASH_FADDR                 0x0008
  64 #define ICH_FLASH_FDATA0                0x0010
  65 #define ICH_FLASH_PR0                   0x0074
  66
  67 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  68 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  69 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  70 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  71 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  72
  73 #define ICH_CYCLE_READ                  0
  74 #define ICH_CYCLE_WRITE                 2
  75 #define ICH_CYCLE_ERASE                 3
  76
  77 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  78 #define FLASH_SECTOR_ADDR_SHIFT         12
  79
  80 #define ICH_FLASH_SEG_SIZE_256          256
  81 #define ICH_FLASH_SEG_SIZE_4K           4096
  82 #define ICH_FLASH_SEG_SIZE_8K           8192
  83 #define ICH_FLASH_SEG_SIZE_64K          65536
  84
  85
  86 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  87 /* FW established a valid mode */
  88 #define E1000_ICH_FWSM_FW_VALID         0x00008000
  89
  90 #define E1000_ICH_MNG_IAMT_MODE         0x2
  91
  92 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  93                                  (ID_LED_DEF1_OFF2 <<  8) | \
  94                                  (ID_LED_DEF1_ON2  <<  4) | \
  95                                  (ID_LED_DEF1_DEF2))
  96
  97 #define E1000_ICH_NVM_SIG_WORD          0x13
  98 #define E1000_ICH_NVM_SIG_MASK          0xC000
  99 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 100 #define E1000_ICH_NVM_SIG_VALUE         0x80
 101
 102 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 103
 104 #define E1000_FEXTNVM_SW_CONFIG         1
 105 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 106
 107 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK    0x0C000000
 108 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC  0x08000000
 109
 110 #define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
 111 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
 112 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
 113
 114 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 115
 116 #define E1000_ICH_RAR_ENTRIES           7
 117 #define E1000_PCH2_RAR_ENTRIES          5 /* RAR[0], SHRA[0-3] */
 118 #define E1000_PCH_LPT_RAR_ENTRIES       12 /* RAR[0], SHRA[0-10] */
 119
 120 #define PHY_PAGE_SHIFT 5
 121 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 122                            ((reg) & MAX_PHY_REG_ADDRESS))
 123 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 124 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 125
 126 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 127 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 128 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 129
 130 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 131
 132 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 133
 134 /* SMBus Control Phy Register */
 135 #define CV_SMB_CTRL             PHY_REG(769, 23)
 136 #define CV_SMB_CTRL_FORCE_SMBUS 0x0001
 137
 138 /* SMBus Address Phy Register */
 139 #define HV_SMB_ADDR            PHY_REG(768, 26)
 140 #define HV_SMB_ADDR_MASK       0x007F
 141 #define HV_SMB_ADDR_PEC_EN     0x0200
 142 #define HV_SMB_ADDR_VALID      0x0080
 143 #define HV_SMB_ADDR_FREQ_MASK           0x1100
 144 #define HV_SMB_ADDR_FREQ_LOW_SHIFT      8
 145 #define HV_SMB_ADDR_FREQ_HIGH_SHIFT     12
 146
 147 /* PHY Power Management Control */
 148 #define HV_PM_CTRL              PHY_REG(770, 17)
 149 #define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA  0x100
 150
 151 /* Intel Rapid Start Technology Support */
 152 #define I217_PROXY_CTRL                 BM_PHY_REG(BM_WUC_PAGE, 70)
 153 #define I217_PROXY_CTRL_AUTO_DISABLE    0x0080
 154 #define I217_SxCTRL                     PHY_REG(BM_PORT_CTRL_PAGE, 28)
 155 #define I217_SxCTRL_ENABLE_LPI_RESET    0x1000
 156 #define I217_CGFREG                     PHY_REG(772, 29)
 157 #define I217_CGFREG_ENABLE_MTA_RESET    0x0002
 158 #define I217_MEMPWR                     PHY_REG(772, 26)
 159 #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010
 160
 161 /* Strapping Option Register - RO */
 162 #define E1000_STRAP                     0x0000C
 163 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 164 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 165 #define E1000_STRAP_SMT_FREQ_MASK       0x00003000
 166 #define E1000_STRAP_SMT_FREQ_SHIFT      12
 167
 168 /* OEM Bits Phy Register */
 169 #define HV_OEM_BITS            PHY_REG(768, 25)
 170 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 171 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 172 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 173
 174 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 175 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 176
 177 /* KMRN Mode Control */
 178 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
 179 #define HV_KMRN_MDIO_SLOW      0x0400
 180
 181 /* KMRN FIFO Control and Status */
 182 #define HV_KMRN_FIFO_CTRLSTA                  PHY_REG(770, 16)
 183 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK    0x7000
 184 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT   12
 185
 186 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 187 /* Offset 04h HSFSTS */
 188 union ich8_hws_flash_status {
 189         struct ich8_hsfsts {
 190                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 191                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 192                 u16 dael       :1; /* bit 2 Direct Access error Log */
 193                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 194                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 195                 u16 reserved1  :2; /* bit 13:6 Reserved */
 196                 u16 reserved2  :6; /* bit 13:6 Reserved */
 197                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 198                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 199         } hsf_status;
 200         u16 regval;
 201 };
 202
 203 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 204 /* Offset 06h FLCTL */
 205 union ich8_hws_flash_ctrl {
 206         struct ich8_hsflctl {
 207                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 208                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 209                 u16 reserved   :5;   /* 7:3 Reserved  */
 210                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 211                 u16 flockdn    :6;   /* 15:10 Reserved */
 212         } hsf_ctrl;
 213         u16 regval;
 214 };
 215
 216 /* ICH Flash Region Access Permissions */
 217 union ich8_hws_flash_regacc {
 218         struct ich8_flracc {
 219                 u32 grra      :8; /* 0:7 GbE region Read Access */
 220                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 221                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 222                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 223         } hsf_flregacc;
 224         u16 regval;
 225 };
 226
 227 /* ICH Flash Protected Region */
 228 union ich8_flash_protected_range {
 229         struct ich8_pr {
 230                 u32 base:13;     /* 0:12 Protected Range Base */
 231                 u32 reserved1:2; /* 13:14 Reserved */
 232                 u32 rpe:1;       /* 15 Read Protection Enable */
 233                 u32 limit:13;    /* 16:28 Protected Range Limit */
 234                 u32 reserved2:2; /* 29:30 Reserved */
 235                 u32 wpe:1;       /* 31 Write Protection Enable */
 236         } range;
 237         u32 regval;
 238 };
 239
 240 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 241 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 242 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 243 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 244 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 245                                                 u32 offset, u8 byte);
 246 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 247                                          u8 *data);
 248 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 249                                          u16 *data);
 250 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 251                                          u8 size, u16 *data);
 252 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 253 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 254 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 255 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 256 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 257 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 258 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 259 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 260 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 261 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 262 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 263 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 264 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 265 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 266 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 267 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 268 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 269 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 270 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 271 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
 272 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 273 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 274
 275 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 276 {
 277         return readw(hw->flash_address + reg);
 278 }
 279
 280 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 281 {
 282         return readl(hw->flash_address + reg);
 283 }
 284
 285 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 286 {
 287         writew(val, hw->flash_address + reg);
 288 }
 289
 290 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 291 {
 292         writel(val, hw->flash_address + reg);
 293 }
 294
 295 #define er16flash(reg)          __er16flash(hw, (reg))
 296 #define er32flash(reg)          __er32flash(hw, (reg))
 297 #define ew16flash(reg, val)     __ew16flash(hw, (reg), (val))
 298 #define ew32flash(reg, val)     __ew32flash(hw, (reg), (val))
 299
 300 /**
 301  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 302  *  @hw: pointer to the HW structure
 303  *
 304  *  Test access to the PHY registers by reading the PHY ID registers.  If
 305  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 306  *  otherwise assume the read PHY ID is correct if it is valid.
 307  *
 308  *  Assumes the sw/fw/hw semaphore is already acquired.
 309  **/
 310 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 311 {
 312         u16 phy_reg = 0;
 313         u32 phy_id = 0;
 314         s32 ret_val;
 315         u16 retry_count;
 316
 317         for (retry_count = 0; retry_count < 2; retry_count++) {
 318                 ret_val = e1e_rphy_locked(hw, PHY_ID1, &phy_reg);
 319                 if (ret_val || (phy_reg == 0xFFFF))
 320                         continue;
 321                 phy_id = (u32)(phy_reg << 16);
 322
 323                 ret_val = e1e_rphy_locked(hw, PHY_ID2, &phy_reg);
 324                 if (ret_val || (phy_reg == 0xFFFF)) {
 325                         phy_id = 0;
 326                         continue;
 327                 }
 328                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 329                 break;
 330         }
 331
 332         if (hw->phy.id) {
 333                 if (hw->phy.id == phy_id)
 334                         return true;
 335         } else if (phy_id) {
 336                 hw->phy.id = phy_id;
 337                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 338                 return true;
 339         }
 340
 341         /* In case the PHY needs to be in mdio slow mode,
 342          * set slow mode and try to get the PHY id again.
 343          */
 344         hw->phy.ops.release(hw);
 345         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 346         if (!ret_val)
 347                 ret_val = e1000e_get_phy_id(hw);
 348         hw->phy.ops.acquire(hw);
 349
 350         return !ret_val;
 351 }
 352
 353 /**
 354  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 355  *  @hw: pointer to the HW structure
 356  *
 357  *  Workarounds/flow necessary for PHY initialization during driver load
 358  *  and resume paths.
 359  **/
 360 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 361 {
 362         u32 mac_reg, fwsm = er32(FWSM);
 363         s32 ret_val;
 364         u16 phy_reg;
 365
 366         ret_val = hw->phy.ops.acquire(hw);
 367         if (ret_val) {
 368                 e_dbg("Failed to initialize PHY flow\n");
 369                 return ret_val;
 370         }
 371
 372         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 373          * inaccessible and resetting the PHY is not blocked, toggle the
 374          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 375          */
 376         switch (hw->mac.type) {
 377         case e1000_pch_lpt:
 378                 if (e1000_phy_is_accessible_pchlan(hw))
 379                         break;
 380
 381                 /* Before toggling LANPHYPC, see if PHY is accessible by
 382                  * forcing MAC to SMBus mode first.
 383                  */
 384                 mac_reg = er32(CTRL_EXT);
 385                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 386                 ew32(CTRL_EXT, mac_reg);
 387
 388                 /* fall-through */
 389         case e1000_pch2lan:
 390                 /* Gate automatic PHY configuration by hardware on
 391                  * non-managed 82579
 392                  */
 393                 if ((hw->mac.type == e1000_pch2lan) &&
 394                     !(fwsm & E1000_ICH_FWSM_FW_VALID))
 395                         e1000_gate_hw_phy_config_ich8lan(hw, true);
 396
 397                 if (e1000_phy_is_accessible_pchlan(hw)) {
 398                         if (hw->mac.type == e1000_pch_lpt) {
 399                                 /* Unforce SMBus mode in PHY */
 400                                 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
 401                                 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 402                                 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
 403
 404                                 /* Unforce SMBus mode in MAC */
 405                                 mac_reg = er32(CTRL_EXT);
 406                                 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 407                                 ew32(CTRL_EXT, mac_reg);
 408                         }
 409                         break;
 410                 }
 411
 412                 /* fall-through */
 413         case e1000_pchlan:
 414                 if ((hw->mac.type == e1000_pchlan) &&
 415                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 416                         break;
 417
 418                 if (hw->phy.ops.check_reset_block(hw)) {
 419                         e_dbg("Required LANPHYPC toggle blocked by ME\n");
 420                         break;
 421                 }
 422
 423                 e_dbg("Toggling LANPHYPC\n");
 424
 425                 /* Set Phy Config Counter to 50msec */
 426                 mac_reg = er32(FEXTNVM3);
 427                 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 428                 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 429                 ew32(FEXTNVM3, mac_reg);
 430
 431                 /* Toggle LANPHYPC Value bit */
 432                 mac_reg = er32(CTRL);
 433                 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 434                 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 435                 ew32(CTRL, mac_reg);
 436                 e1e_flush();
 437                 udelay(10);
 438                 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 439                 ew32(CTRL, mac_reg);
 440                 e1e_flush();
 441                 if (hw->mac.type < e1000_pch_lpt) {
 442                         msleep(50);
 443                 } else {
 444                         u16 count = 20;
 445                         do {
 446                                 usleep_range(5000, 10000);
 447                         } while (!(er32(CTRL_EXT) &
 448                                    E1000_CTRL_EXT_LPCD) && count--);
 449                 }
 450                 break;
 451         default:
 452                 break;
 453         }
 454
 455         hw->phy.ops.release(hw);
 456
 457         /* Reset the PHY before any access to it.  Doing so, ensures
 458          * that the PHY is in a known good state before we read/write
 459          * PHY registers.  The generic reset is sufficient here,
 460          * because we haven't determined the PHY type yet.
 461          */
 462         ret_val = e1000e_phy_hw_reset_generic(hw);
 463
 464         /* Ungate automatic PHY configuration on non-managed 82579 */
 465         if ((hw->mac.type == e1000_pch2lan) &&
 466             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 467                 usleep_range(10000, 20000);
 468                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 469         }
 470
 471         return ret_val;
 472 }
 473
 474 /**
 475  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 476  *  @hw: pointer to the HW structure
 477  *
 478  *  Initialize family-specific PHY parameters and function pointers.
 479  **/
 480 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 481 {
 482         struct e1000_phy_info *phy = &hw->phy;
 483         s32 ret_val = 0;
 484
 485         phy->addr                     = 1;
 486         phy->reset_delay_us           = 100;
 487
 488         phy->ops.set_page             = e1000_set_page_igp;
 489         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 490         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 491         phy->ops.read_reg_page        = e1000_read_phy_reg_page_hv;
 492         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 493         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 494         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 495         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 496         phy->ops.write_reg_page       = e1000_write_phy_reg_page_hv;
 497         phy->ops.power_up             = e1000_power_up_phy_copper;
 498         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 499         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 500
 501         phy->id = e1000_phy_unknown;
 502
 503         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 504         if (ret_val)
 505                 return ret_val;
 506
 507         if (phy->id == e1000_phy_unknown)
 508                 switch (hw->mac.type) {
 509                 default:
 510                         ret_val = e1000e_get_phy_id(hw);
 511                         if (ret_val)
 512                                 return ret_val;
 513                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 514                                 break;
 515                         /* fall-through */
 516                 case e1000_pch2lan:
 517                 case e1000_pch_lpt:
 518                         /* In case the PHY needs to be in mdio slow mode,
 519                          * set slow mode and try to get the PHY id again.
 520                          */
 521                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 522                         if (ret_val)
 523                                 return ret_val;
 524                         ret_val = e1000e_get_phy_id(hw);
 525                         if (ret_val)
 526                                 return ret_val;
 527                         break;
 528                 }
 529         phy->type = e1000e_get_phy_type_from_id(phy->id);
 530
 531         switch (phy->type) {
 532         case e1000_phy_82577:
 533         case e1000_phy_82579:
 534         case e1000_phy_i217:
 535                 phy->ops.check_polarity = e1000_check_polarity_82577;
 536                 phy->ops.force_speed_duplex =
 537                     e1000_phy_force_speed_duplex_82577;
 538                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 539                 phy->ops.get_info = e1000_get_phy_info_82577;
 540                 phy->ops.commit = e1000e_phy_sw_reset;
 541                 break;
 542         case e1000_phy_82578:
 543                 phy->ops.check_polarity = e1000_check_polarity_m88;
 544                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 545                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 546                 phy->ops.get_info = e1000e_get_phy_info_m88;
 547                 break;
 548         default:
 549                 ret_val = -E1000_ERR_PHY;
 550                 break;
 551         }
 552
 553         return ret_val;
 554 }
 555
 556 /**
 557  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 558  *  @hw: pointer to the HW structure
 559  *
 560  *  Initialize family-specific PHY parameters and function pointers.
 561  **/
 562 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 563 {
 564         struct e1000_phy_info *phy = &hw->phy;
 565         s32 ret_val;
 566         u16 i = 0;
 567
 568         phy->addr                       = 1;
 569         phy->reset_delay_us             = 100;
 570
 571         phy->ops.power_up               = e1000_power_up_phy_copper;
 572         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 573
 574         /* We may need to do this twice - once for IGP and if that fails,
 575          * we'll set BM func pointers and try again
 576          */
 577         ret_val = e1000e_determine_phy_address(hw);
 578         if (ret_val) {
 579                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 580                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 581                 ret_val = e1000e_determine_phy_address(hw);
 582                 if (ret_val) {
 583                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 584                         return ret_val;
 585                 }
 586         }
 587
 588         phy->id = 0;
 589         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 590                (i++ < 100)) {
 591                 usleep_range(1000, 2000);
 592                 ret_val = e1000e_get_phy_id(hw);
 593                 if (ret_val)
 594                         return ret_val;
 595         }
 596
 597         /* Verify phy id */
 598         switch (phy->id) {
 599         case IGP03E1000_E_PHY_ID:
 600                 phy->type = e1000_phy_igp_3;
 601                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 602                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 603                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 604                 phy->ops.get_info = e1000e_get_phy_info_igp;
 605                 phy->ops.check_polarity = e1000_check_polarity_igp;
 606                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 607                 break;
 608         case IFE_E_PHY_ID:
 609         case IFE_PLUS_E_PHY_ID:
 610         case IFE_C_E_PHY_ID:
 611                 phy->type = e1000_phy_ife;
 612                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 613                 phy->ops.get_info = e1000_get_phy_info_ife;
 614                 phy->ops.check_polarity = e1000_check_polarity_ife;
 615                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 616                 break;
 617         case BME1000_E_PHY_ID:
 618                 phy->type = e1000_phy_bm;
 619                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 620                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 621                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 622                 phy->ops.commit = e1000e_phy_sw_reset;
 623                 phy->ops.get_info = e1000e_get_phy_info_m88;
 624                 phy->ops.check_polarity = e1000_check_polarity_m88;
 625                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 626                 break;
 627         default:
 628                 return -E1000_ERR_PHY;
 629                 break;
 630         }
 631
 632         return 0;
 633 }
 634
 635 /**
 636  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 637  *  @hw: pointer to the HW structure
 638  *
 639  *  Initialize family-specific NVM parameters and function
 640  *  pointers.
 641  **/
 642 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 643 {
 644         struct e1000_nvm_info *nvm = &hw->nvm;
 645         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 646         u32 gfpreg, sector_base_addr, sector_end_addr;
 647         u16 i;
 648
 649         /* Can't read flash registers if the register set isn't mapped. */
 650         if (!hw->flash_address) {
 651                 e_dbg("ERROR: Flash registers not mapped\n");
 652                 return -E1000_ERR_CONFIG;
 653         }
 654
 655         nvm->type = e1000_nvm_flash_sw;
 656
 657         gfpreg = er32flash(ICH_FLASH_GFPREG);
 658
 659         /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 660          * Add 1 to sector_end_addr since this sector is included in
 661          * the overall size.
 662          */
 663         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 664         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 665
 666         /* flash_base_addr is byte-aligned */
 667         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 668
 669         /* find total size of the NVM, then cut in half since the total
 670          * size represents two separate NVM banks.
 671          */
 672         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 673                                 << FLASH_SECTOR_ADDR_SHIFT;
 674         nvm->flash_bank_size /= 2;
 675         /* Adjust to word count */
 676         nvm->flash_bank_size /= sizeof(u16);
 677
 678         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 679
 680         /* Clear shadow ram */
 681         for (i = 0; i < nvm->word_size; i++) {
 682                 dev_spec->shadow_ram[i].modified = false;
 683                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 684         }
 685
 686         return 0;
 687 }
 688
 689 /**
 690  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 691  *  @hw: pointer to the HW structure
 692  *
 693  *  Initialize family-specific MAC parameters and function
 694  *  pointers.
 695  **/
 696 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 697 {
 698         struct e1000_mac_info *mac = &hw->mac;
 699
 700         /* Set media type function pointer */
 701         hw->phy.media_type = e1000_media_type_copper;
 702
 703         /* Set mta register count */
 704         mac->mta_reg_count = 32;
 705         /* Set rar entry count */
 706         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 707         if (mac->type == e1000_ich8lan)
 708                 mac->rar_entry_count--;
 709         /* FWSM register */
 710         mac->has_fwsm = true;
 711         /* ARC subsystem not supported */
 712         mac->arc_subsystem_valid = false;
 713         /* Adaptive IFS supported */
 714         mac->adaptive_ifs = true;
 715
 716         /* LED and other operations */
 717         switch (mac->type) {
 718         case e1000_ich8lan:
 719         case e1000_ich9lan:
 720         case e1000_ich10lan:
 721                 /* check management mode */
 722                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 723                 /* ID LED init */
 724                 mac->ops.id_led_init = e1000e_id_led_init_generic;
 725                 /* blink LED */
 726                 mac->ops.blink_led = e1000e_blink_led_generic;
 727                 /* setup LED */
 728                 mac->ops.setup_led = e1000e_setup_led_generic;
 729                 /* cleanup LED */
 730                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 731                 /* turn on/off LED */
 732                 mac->ops.led_on = e1000_led_on_ich8lan;
 733                 mac->ops.led_off = e1000_led_off_ich8lan;
 734                 break;
 735         case e1000_pch2lan:
 736                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 737                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 738                 /* fall-through */
 739         case e1000_pch_lpt:
 740         case e1000_pchlan:
 741                 /* check management mode */
 742                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 743                 /* ID LED init */
 744                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 745                 /* setup LED */
 746                 mac->ops.setup_led = e1000_setup_led_pchlan;
 747                 /* cleanup LED */
 748                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 749                 /* turn on/off LED */
 750                 mac->ops.led_on = e1000_led_on_pchlan;
 751                 mac->ops.led_off = e1000_led_off_pchlan;
 752                 break;
 753         default:
 754                 break;
 755         }
 756
 757         if (mac->type == e1000_pch_lpt) {
 758                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 759                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 760         }
 761
 762         /* Enable PCS Lock-loss workaround for ICH8 */
 763         if (mac->type == e1000_ich8lan)
 764                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 765
 766         /* Gate automatic PHY configuration by hardware on managed
 767          * 82579 and i217
 768          */
 769         if ((mac->type == e1000_pch2lan || mac->type == e1000_pch_lpt) &&
 770             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 771                 e1000_gate_hw_phy_config_ich8lan(hw, true);
 772
 773         return 0;
 774 }
 775
 776 /**
 777  *  __e1000_access_emi_reg_locked - Read/write EMI register
 778  *  @hw: pointer to the HW structure
 779  *  @addr: EMI address to program
 780  *  @data: pointer to value to read/write from/to the EMI address
 781  *  @read: boolean flag to indicate read or write
 782  *
 783  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 784  **/
 785 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 786                                          u16 *data, bool read)
 787 {
 788         s32 ret_val = 0;
 789
 790         ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
 791         if (ret_val)
 792                 return ret_val;
 793
 794         if (read)
 795                 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
 796         else
 797                 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
 798
 799         return ret_val;
 800 }
 801
 802 /**
 803  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 804  *  @hw: pointer to the HW structure
 805  *  @addr: EMI address to program
 806  *  @data: value to be read from the EMI address
 807  *
 808  *  Assumes the SW/FW/HW Semaphore is already acquired.
 809  **/
 810 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 811 {
 812         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 813 }
 814
 815 /**
 816  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 817  *  @hw: pointer to the HW structure
 818  *  @addr: EMI address to program
 819  *  @data: value to be written to the EMI address
 820  *
 821  *  Assumes the SW/FW/HW Semaphore is already acquired.
 822  **/
 823 static s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 824 {
 825         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 826 }
 827
 828 /**
 829  *  e1000_set_eee_pchlan - Enable/disable EEE support
 830  *  @hw: pointer to the HW structure
 831  *
 832  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 833  *  the link and the EEE capabilities of the link partner.  The LPI Control
 834  *  register bits will remain set only if/when link is up.
 835  **/
 836 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 837 {
 838         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 839         s32 ret_val;
 840         u16 lpi_ctrl;
 841
 842         if ((hw->phy.type != e1000_phy_82579) &&
 843             (hw->phy.type != e1000_phy_i217))
 844                 return 0;
 845
 846         ret_val = hw->phy.ops.acquire(hw);
 847         if (ret_val)
 848                 return ret_val;
 849
 850         ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 851         if (ret_val)
 852                 goto release;
 853
 854         /* Clear bits that enable EEE in various speeds */
 855         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 856
 857         /* Enable EEE if not disabled by user */
 858         if (!dev_spec->eee_disable) {
 859                 u16 lpa, pcs_status, data;
 860
 861                 /* Save off link partner's EEE ability */
 862                 switch (hw->phy.type) {
 863                 case e1000_phy_82579:
 864                         lpa = I82579_EEE_LP_ABILITY;
 865                         pcs_status = I82579_EEE_PCS_STATUS;
 866                         break;
 867                 case e1000_phy_i217:
 868                         lpa = I217_EEE_LP_ABILITY;
 869                         pcs_status = I217_EEE_PCS_STATUS;
 870                         break;
 871                 default:
 872                         ret_val = -E1000_ERR_PHY;
 873                         goto release;
 874                 }
 875                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 876                                                     &dev_spec->eee_lp_ability);
 877                 if (ret_val)
 878                         goto release;
 879
 880                 /* Enable EEE only for speeds in which the link partner is
 881                  * EEE capable.
 882                  */
 883                 if (dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 884                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 885
 886                 if (dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 887                         e1e_rphy_locked(hw, PHY_LP_ABILITY, &data);
 888                         if (data & NWAY_LPAR_100TX_FD_CAPS)
 889                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 890                         else
 891                                 /* EEE is not supported in 100Half, so ignore
 892                                  * partner's EEE in 100 ability if full-duplex
 893                                  * is not advertised.
 894                                  */
 895                                 dev_spec->eee_lp_ability &=
 896                                     ~I82579_EEE_100_SUPPORTED;
 897                 }
 898
 899                 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 900                 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 901                 if (ret_val)
 902                         goto release;
 903         }
 904
 905         ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 906 release:
 907         hw->phy.ops.release(hw);
 908
 909         return ret_val;
 910 }
 911
 912 /**
 913  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 914  *  @hw: pointer to the HW structure
 915  *
 916  *  Checks to see of the link status of the hardware has changed.  If a
 917  *  change in link status has been detected, then we read the PHY registers
 918  *  to get the current speed/duplex if link exists.
 919  **/
 920 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 921 {
 922         struct e1000_mac_info *mac = &hw->mac;
 923         s32 ret_val;
 924         bool link;
 925         u16 phy_reg;
 926
 927         /* We only want to go out to the PHY registers to see if Auto-Neg
 928          * has completed and/or if our link status has changed.  The
 929          * get_link_status flag is set upon receiving a Link Status
 930          * Change or Rx Sequence Error interrupt.
 931          */
 932         if (!mac->get_link_status)
 933                 return 0;
 934
 935         /* First we want to see if the MII Status Register reports
 936          * link.  If so, then we want to get the current speed/duplex
 937          * of the PHY.
 938          */
 939         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 940         if (ret_val)
 941                 return ret_val;
 942
 943         if (hw->mac.type == e1000_pchlan) {
 944                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 945                 if (ret_val)
 946                         return ret_val;
 947         }
 948
 949         /* Clear link partner's EEE ability */
 950         hw->dev_spec.ich8lan.eee_lp_ability = 0;
 951
 952         if (!link)
 953                 return 0; /* No link detected */
 954
 955         mac->get_link_status = false;
 956
 957         switch (hw->mac.type) {
 958         case e1000_pch2lan:
 959                 ret_val = e1000_k1_workaround_lv(hw);
 960                 if (ret_val)
 961                         return ret_val;
 962                 /* fall-thru */
 963         case e1000_pchlan:
 964                 if (hw->phy.type == e1000_phy_82578) {
 965                         ret_val = e1000_link_stall_workaround_hv(hw);
 966                         if (ret_val)
 967                                 return ret_val;
 968                 }
 969
 970                 /* Workaround for PCHx parts in half-duplex:
 971                  * Set the number of preambles removed from the packet
 972                  * when it is passed from the PHY to the MAC to prevent
 973                  * the MAC from misinterpreting the packet type.
 974                  */
 975                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
 976                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
 977
 978                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
 979                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
 980
 981                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
 982                 break;
 983         default:
 984                 break;
 985         }
 986
 987         /* Check if there was DownShift, must be checked
 988          * immediately after link-up
 989          */
 990         e1000e_check_downshift(hw);
 991
 992         /* Enable/Disable EEE after link up */
 993         ret_val = e1000_set_eee_pchlan(hw);
 994         if (ret_val)
 995                 return ret_val;
 996
 997         /* If we are forcing speed/duplex, then we simply return since
 998          * we have already determined whether we have link or not.
 999          */
1000         if (!mac->autoneg)
1001                 return -E1000_ERR_CONFIG;
1002
1003         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1004          * of MAC speed/duplex configuration.  So we only need to
1005          * configure Collision Distance in the MAC.
1006          */
1007         mac->ops.config_collision_dist(hw);
1008
1009         /* Configure Flow Control now that Auto-Neg has completed.
1010          * First, we need to restore the desired flow control
1011          * settings because we may have had to re-autoneg with a
1012          * different link partner.
1013          */
1014         ret_val = e1000e_config_fc_after_link_up(hw);
1015         if (ret_val)
1016                 e_dbg("Error configuring flow control\n");
1017
1018         return ret_val;
1019 }
1020
1021 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1022 {
1023         struct e1000_hw *hw = &adapter->hw;
1024         s32 rc;
1025
1026         rc = e1000_init_mac_params_ich8lan(hw);
1027         if (rc)
1028                 return rc;
1029
1030         rc = e1000_init_nvm_params_ich8lan(hw);
1031         if (rc)
1032                 return rc;
1033
1034         switch (hw->mac.type) {
1035         case e1000_ich8lan:
1036         case e1000_ich9lan:
1037         case e1000_ich10lan:
1038                 rc = e1000_init_phy_params_ich8lan(hw);
1039                 break;
1040         case e1000_pchlan:
1041         case e1000_pch2lan:
1042         case e1000_pch_lpt:
1043                 rc = e1000_init_phy_params_pchlan(hw);
1044                 break;
1045         default:
1046                 break;
1047         }
1048         if (rc)
1049                 return rc;
1050
1051         /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1052          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1053          */
1054         if ((adapter->hw.phy.type == e1000_phy_ife) ||
1055             ((adapter->hw.mac.type >= e1000_pch2lan) &&
1056              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1057                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1058                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
1059
1060                 hw->mac.ops.blink_led = NULL;
1061         }
1062
1063         if ((adapter->hw.mac.type == e1000_ich8lan) &&
1064             (adapter->hw.phy.type != e1000_phy_ife))
1065                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1066
1067         /* Enable workaround for 82579 w/ ME enabled */
1068         if ((adapter->hw.mac.type == e1000_pch2lan) &&
1069             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1070                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1071
1072         /* Disable EEE by default until IEEE802.3az spec is finalized */
1073         if (adapter->flags2 & FLAG2_HAS_EEE)
1074                 adapter->hw.dev_spec.ich8lan.eee_disable = true;
1075
1076         return 0;
1077 }
1078
1079 static DEFINE_MUTEX(nvm_mutex);
1080
1081 /**
1082  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1083  *  @hw: pointer to the HW structure
1084  *
1085  *  Acquires the mutex for performing NVM operations.
1086  **/
1087 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1088 {
1089         mutex_lock(&nvm_mutex);
1090
1091         return 0;
1092 }
1093
1094 /**
1095  *  e1000_release_nvm_ich8lan - Release NVM mutex
1096  *  @hw: pointer to the HW structure
1097  *
1098  *  Releases the mutex used while performing NVM operations.
1099  **/
1100 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1101 {
1102         mutex_unlock(&nvm_mutex);
1103 }
1104
1105 /**
1106  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1107  *  @hw: pointer to the HW structure
1108  *
1109  *  Acquires the software control flag for performing PHY and select
1110  *  MAC CSR accesses.
1111  **/
1112 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1113 {
1114         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1115         s32 ret_val = 0;
1116
1117         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1118                              &hw->adapter->state)) {
1119                 e_dbg("contention for Phy access\n");
1120                 return -E1000_ERR_PHY;
1121         }
1122
1123         while (timeout) {
1124                 extcnf_ctrl = er32(EXTCNF_CTRL);
1125                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1126                         break;
1127
1128                 mdelay(1);
1129                 timeout--;
1130         }
1131
1132         if (!timeout) {
1133                 e_dbg("SW has already locked the resource.\n");
1134                 ret_val = -E1000_ERR_CONFIG;
1135                 goto out;
1136         }
1137
1138         timeout = SW_FLAG_TIMEOUT;
1139
1140         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1141         ew32(EXTCNF_CTRL, extcnf_ctrl);
1142
1143         while (timeout) {
1144                 extcnf_ctrl = er32(EXTCNF_CTRL);
1145                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1146                         break;
1147
1148                 mdelay(1);
1149                 timeout--;
1150         }
1151
1152         if (!timeout) {
1153                 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1154                       er32(FWSM), extcnf_ctrl);
1155                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1156                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1157                 ret_val = -E1000_ERR_CONFIG;
1158                 goto out;
1159         }
1160
1161 out:
1162         if (ret_val)
1163                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1164
1165         return ret_val;
1166 }
1167
1168 /**
1169  *  e1000_release_swflag_ich8lan - Release software control flag
1170  *  @hw: pointer to the HW structure
1171  *
1172  *  Releases the software control flag for performing PHY and select
1173  *  MAC CSR accesses.
1174  **/
1175 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1176 {
1177         u32 extcnf_ctrl;
1178
1179         extcnf_ctrl = er32(EXTCNF_CTRL);
1180
1181         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1182                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1183                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1184         } else {
1185                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1186         }
1187
1188         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1189 }
1190
1191 /**
1192  *  e1000_check_mng_mode_ich8lan - Checks management mode
1193  *  @hw: pointer to the HW structure
1194  *
1195  *  This checks if the adapter has any manageability enabled.
1196  *  This is a function pointer entry point only called by read/write
1197  *  routines for the PHY and NVM parts.
1198  **/
1199 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1200 {
1201         u32 fwsm;
1202
1203         fwsm = er32(FWSM);
1204         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1205                ((fwsm & E1000_FWSM_MODE_MASK) ==
1206                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1207 }
1208
1209 /**
1210  *  e1000_check_mng_mode_pchlan - Checks management mode
1211  *  @hw: pointer to the HW structure
1212  *
1213  *  This checks if the adapter has iAMT enabled.
1214  *  This is a function pointer entry point only called by read/write
1215  *  routines for the PHY and NVM parts.
1216  **/
1217 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1218 {
1219         u32 fwsm;
1220
1221         fwsm = er32(FWSM);
1222         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1223                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1224 }
1225
1226 /**
1227  *  e1000_rar_set_pch2lan - Set receive address register
1228  *  @hw: pointer to the HW structure
1229  *  @addr: pointer to the receive address
1230  *  @index: receive address array register
1231  *
1232  *  Sets the receive address array register at index to the address passed
1233  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1234  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1235  *  Use SHRA[0-3] in place of those reserved for ME.
1236  **/
1237 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1238 {
1239         u32 rar_low, rar_high;
1240
1241         /* HW expects these in little endian so we reverse the byte order
1242          * from network order (big endian) to little endian
1243          */
1244         rar_low = ((u32)addr[0] |
1245                    ((u32)addr[1] << 8) |
1246                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1247
1248         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1249
1250         /* If MAC address zero, no need to set the AV bit */
1251         if (rar_low || rar_high)
1252                 rar_high |= E1000_RAH_AV;
1253
1254         if (index == 0) {
1255                 ew32(RAL(index), rar_low);
1256                 e1e_flush();
1257                 ew32(RAH(index), rar_high);
1258                 e1e_flush();
1259                 return;
1260         }
1261
1262         if (index < hw->mac.rar_entry_count) {
1263                 s32 ret_val;
1264
1265                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1266                 if (ret_val)
1267                         goto out;
1268
1269                 ew32(SHRAL(index - 1), rar_low);
1270                 e1e_flush();
1271                 ew32(SHRAH(index - 1), rar_high);
1272                 e1e_flush();
1273
1274                 e1000_release_swflag_ich8lan(hw);
1275
1276                 /* verify the register updates */
1277                 if ((er32(SHRAL(index - 1)) == rar_low) &&
1278                     (er32(SHRAH(index - 1)) == rar_high))
1279                         return;
1280
1281                 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1282                       (index - 1), er32(FWSM));
1283         }
1284
1285 out:
1286         e_dbg("Failed to write receive address at index %d\n", index);
1287 }
1288
1289 /**
1290  *  e1000_rar_set_pch_lpt - Set receive address registers
1291  *  @hw: pointer to the HW structure
1292  *  @addr: pointer to the receive address
1293  *  @index: receive address array register
1294  *
1295  *  Sets the receive address register array at index to the address passed
1296  *  in by addr. For LPT, RAR[0] is the base address register that is to
1297  *  contain the MAC address. SHRA[0-10] are the shared receive address
1298  *  registers that are shared between the Host and manageability engine (ME).
1299  **/
1300 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1301 {
1302         u32 rar_low, rar_high;
1303         u32 wlock_mac;
1304
1305         /* HW expects these in little endian so we reverse the byte order
1306          * from network order (big endian) to little endian
1307          */
1308         rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1309                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1310
1311         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1312
1313         /* If MAC address zero, no need to set the AV bit */
1314         if (rar_low || rar_high)
1315                 rar_high |= E1000_RAH_AV;
1316
1317         if (index == 0) {
1318                 ew32(RAL(index), rar_low);
1319                 e1e_flush();
1320                 ew32(RAH(index), rar_high);
1321                 e1e_flush();
1322                 return;
1323         }
1324
1325         /* The manageability engine (ME) can lock certain SHRAR registers that
1326          * it is using - those registers are unavailable for use.
1327          */
1328         if (index < hw->mac.rar_entry_count) {
1329                 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1330                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1331
1332                 /* Check if all SHRAR registers are locked */
1333                 if (wlock_mac == 1)
1334                         goto out;
1335
1336                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1337                         s32 ret_val;
1338
1339                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1340
1341                         if (ret_val)
1342                                 goto out;
1343
1344                         ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1345                         e1e_flush();
1346                         ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1347                         e1e_flush();
1348
1349                         e1000_release_swflag_ich8lan(hw);
1350
1351                         /* verify the register updates */
1352                         if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1353                             (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1354                                 return;
1355                 }
1356         }
1357
1358 out:
1359         e_dbg("Failed to write receive address at index %d\n", index);
1360 }
1361
1362 /**
1363  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1364  *  @hw: pointer to the HW structure
1365  *
1366  *  Checks if firmware is blocking the reset of the PHY.
1367  *  This is a function pointer entry point only called by
1368  *  reset routines.
1369  **/
1370 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1371 {
1372         u32 fwsm;
1373
1374         fwsm = er32(FWSM);
1375
1376         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
1377 }
1378
1379 /**
1380  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1381  *  @hw: pointer to the HW structure
1382  *
1383  *  Assumes semaphore already acquired.
1384  *
1385  **/
1386 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1387 {
1388         u16 phy_data;
1389         u32 strap = er32(STRAP);
1390         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1391             E1000_STRAP_SMT_FREQ_SHIFT;
1392         s32 ret_val = 0;
1393
1394         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1395
1396         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1397         if (ret_val)
1398                 return ret_val;
1399
1400         phy_data &= ~HV_SMB_ADDR_MASK;
1401         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1402         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1403
1404         if (hw->phy.type == e1000_phy_i217) {
1405                 /* Restore SMBus frequency */
1406                 if (freq--) {
1407                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1408                         phy_data |= (freq & (1 << 0)) <<
1409                             HV_SMB_ADDR_FREQ_LOW_SHIFT;
1410                         phy_data |= (freq & (1 << 1)) <<
1411                             (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1412                 } else {
1413                         e_dbg("Unsupported SMB frequency in PHY\n");
1414                 }
1415         }
1416
1417         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1418 }
1419
1420 /**
1421  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1422  *  @hw:   pointer to the HW structure
1423  *
1424  *  SW should configure the LCD from the NVM extended configuration region
1425  *  as a workaround for certain parts.
1426  **/
1427 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1428 {
1429         struct e1000_phy_info *phy = &hw->phy;
1430         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1431         s32 ret_val = 0;
1432         u16 word_addr, reg_data, reg_addr, phy_page = 0;
1433
1434         /* Initialize the PHY from the NVM on ICH platforms.  This
1435          * is needed due to an issue where the NVM configuration is
1436          * not properly autoloaded after power transitions.
1437          * Therefore, after each PHY reset, we will load the
1438          * configuration data out of the NVM manually.
1439          */
1440         switch (hw->mac.type) {
1441         case e1000_ich8lan:
1442                 if (phy->type != e1000_phy_igp_3)
1443                         return ret_val;
1444
1445                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1446                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1447                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1448                         break;
1449                 }
1450                 /* Fall-thru */
1451         case e1000_pchlan:
1452         case e1000_pch2lan:
1453         case e1000_pch_lpt:
1454                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1455                 break;
1456         default:
1457                 return ret_val;
1458         }
1459
1460         ret_val = hw->phy.ops.acquire(hw);
1461         if (ret_val)
1462                 return ret_val;
1463
1464         data = er32(FEXTNVM);
1465         if (!(data & sw_cfg_mask))
1466                 goto release;
1467
1468         /* Make sure HW does not configure LCD from PHY
1469          * extended configuration before SW configuration
1470          */
1471         data = er32(EXTCNF_CTRL);
1472         if ((hw->mac.type < e1000_pch2lan) &&
1473             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
1474                 goto release;
1475
1476         cnf_size = er32(EXTCNF_SIZE);
1477         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1478         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1479         if (!cnf_size)
1480                 goto release;
1481
1482         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1483         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1484
1485         if (((hw->mac.type == e1000_pchlan) &&
1486              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
1487             (hw->mac.type > e1000_pchlan)) {
1488                 /* HW configures the SMBus address and LEDs when the
1489                  * OEM and LCD Write Enable bits are set in the NVM.
1490                  * When both NVM bits are cleared, SW will configure
1491                  * them instead.
1492                  */
1493                 ret_val = e1000_write_smbus_addr(hw);
1494                 if (ret_val)
1495                         goto release;
1496
1497                 data = er32(LEDCTL);
1498                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1499                                                         (u16)data);
1500                 if (ret_val)
1501                         goto release;
1502         }
1503
1504         /* Configure LCD from extended configuration region. */
1505
1506         /* cnf_base_addr is in DWORD */
1507         word_addr = (u16)(cnf_base_addr << 1);
1508
1509         for (i = 0; i < cnf_size; i++) {
1510                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1511                                          &reg_data);
1512                 if (ret_val)
1513                         goto release;
1514
1515                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1516                                          1, &reg_addr);
1517                 if (ret_val)
1518                         goto release;
1519
1520                 /* Save off the PHY page for future writes. */
1521                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1522                         phy_page = reg_data;
1523                         continue;
1524                 }
1525
1526                 reg_addr &= PHY_REG_MASK;
1527                 reg_addr |= phy_page;
1528
1529                 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
1530                 if (ret_val)
1531                         goto release;
1532         }
1533
1534 release:
1535         hw->phy.ops.release(hw);
1536         return ret_val;
1537 }
1538
1539 /**
1540  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1541  *  @hw:   pointer to the HW structure
1542  *  @link: link up bool flag
1543  *
1544  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1545  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1546  *  If link is down, the function will restore the default K1 setting located
1547  *  in the NVM.
1548  **/
1549 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1550 {
1551         s32 ret_val = 0;
1552         u16 status_reg = 0;
1553         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1554
1555         if (hw->mac.type != e1000_pchlan)
1556                 return 0;
1557
1558         /* Wrap the whole flow with the sw flag */
1559         ret_val = hw->phy.ops.acquire(hw);
1560         if (ret_val)
1561                 return ret_val;
1562
1563         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1564         if (link) {
1565                 if (hw->phy.type == e1000_phy_82578) {
1566                         ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
1567                                                   &status_reg);
1568                         if (ret_val)
1569                                 goto release;
1570
1571                         status_reg &= BM_CS_STATUS_LINK_UP |
1572                                       BM_CS_STATUS_RESOLVED |
1573                                       BM_CS_STATUS_SPEED_MASK;
1574
1575                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1576                                            BM_CS_STATUS_RESOLVED |
1577                                            BM_CS_STATUS_SPEED_1000))
1578                                 k1_enable = false;
1579                 }
1580
1581                 if (hw->phy.type == e1000_phy_82577) {
1582                         ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
1583                         if (ret_val)
1584                                 goto release;
1585
1586                         status_reg &= HV_M_STATUS_LINK_UP |
1587                                       HV_M_STATUS_AUTONEG_COMPLETE |
1588                                       HV_M_STATUS_SPEED_MASK;
1589
1590                         if (status_reg == (HV_M_STATUS_LINK_UP |
1591                                            HV_M_STATUS_AUTONEG_COMPLETE |
1592                                            HV_M_STATUS_SPEED_1000))
1593                                 k1_enable = false;
1594                 }
1595
1596                 /* Link stall fix for link up */
1597                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
1598                 if (ret_val)
1599                         goto release;
1600
1601         } else {
1602                 /* Link stall fix for link down */
1603                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
1604                 if (ret_val)
1605                         goto release;
1606         }
1607
1608         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1609
1610 release:
1611         hw->phy.ops.release(hw);
1612
1613         return ret_val;
1614 }
1615
1616 /**
1617  *  e1000_configure_k1_ich8lan - Configure K1 power state
1618  *  @hw: pointer to the HW structure
1619  *  @enable: K1 state to configure
1620  *
1621  *  Configure the K1 power state based on the provided parameter.
1622  *  Assumes semaphore already acquired.
1623  *
1624  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1625  **/
1626 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1627 {
1628         s32 ret_val = 0;
1629         u32 ctrl_reg = 0;
1630         u32 ctrl_ext = 0;
1631         u32 reg = 0;
1632         u16 kmrn_reg = 0;
1633
1634         ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1635                                               &kmrn_reg);
1636         if (ret_val)
1637                 return ret_val;
1638
1639         if (k1_enable)
1640                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1641         else
1642                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1643
1644         ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1645                                                kmrn_reg);
1646         if (ret_val)
1647                 return ret_val;
1648
1649         udelay(20);
1650         ctrl_ext = er32(CTRL_EXT);
1651         ctrl_reg = er32(CTRL);
1652
1653         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1654         reg |= E1000_CTRL_FRCSPD;
1655         ew32(CTRL, reg);
1656
1657         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1658         e1e_flush();
1659         udelay(20);
1660         ew32(CTRL, ctrl_reg);
1661         ew32(CTRL_EXT, ctrl_ext);
1662         e1e_flush();
1663         udelay(20);
1664
1665         return 0;
1666 }
1667
1668 /**
1669  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1670  *  @hw:       pointer to the HW structure
1671  *  @d0_state: boolean if entering d0 or d3 device state
1672  *
1673  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1674  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1675  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1676  **/
1677 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1678 {
1679         s32 ret_val = 0;
1680         u32 mac_reg;
1681         u16 oem_reg;
1682
1683         if (hw->mac.type < e1000_pchlan)
1684                 return ret_val;
1685
1686         ret_val = hw->phy.ops.acquire(hw);
1687         if (ret_val)
1688                 return ret_val;
1689
1690         if (hw->mac.type == e1000_pchlan) {
1691                 mac_reg = er32(EXTCNF_CTRL);
1692                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1693                         goto release;
1694         }
1695
1696         mac_reg = er32(FEXTNVM);
1697         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1698                 goto release;
1699
1700         mac_reg = er32(PHY_CTRL);
1701
1702         ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
1703         if (ret_val)
1704                 goto release;
1705
1706         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1707
1708         if (d0_state) {
1709                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1710                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1711
1712                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1713                         oem_reg |= HV_OEM_BITS_LPLU;
1714         } else {
1715                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1716                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
1717                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1718
1719                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1720                                E1000_PHY_CTRL_NOND0A_LPLU))
1721                         oem_reg |= HV_OEM_BITS_LPLU;
1722         }
1723
1724         /* Set Restart auto-neg to activate the bits */
1725         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
1726             !hw->phy.ops.check_reset_block(hw))
1727                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1728
1729         ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
1730
1731 release:
1732         hw->phy.ops.release(hw);
1733
1734         return ret_val;
1735 }
1736
1737
1738 /**
1739  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1740  *  @hw:   pointer to the HW structure
1741  **/
1742 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1743 {
1744         s32 ret_val;
1745         u16 data;
1746
1747         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1748         if (ret_val)
1749                 return ret_val;
1750
1751         data |= HV_KMRN_MDIO_SLOW;
1752
1753         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1754
1755         return ret_val;
1756 }
1757
1758 /**
1759  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1760  *  done after every PHY reset.
1761  **/
1762 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1763 {
1764         s32 ret_val = 0;
1765         u16 phy_data;
1766
1767         if (hw->mac.type != e1000_pchlan)
1768                 return 0;
1769
1770         /* Set MDIO slow mode before any other MDIO access */
1771         if (hw->phy.type == e1000_phy_82577) {
1772                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1773                 if (ret_val)
1774                         return ret_val;
1775         }
1776
1777         if (((hw->phy.type == e1000_phy_82577) &&
1778              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1779             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1780                 /* Disable generation of early preamble */
1781                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1782                 if (ret_val)
1783                         return ret_val;
1784
1785                 /* Preamble tuning for SSC */
1786                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
1787                 if (ret_val)
1788                         return ret_val;
1789         }
1790
1791         if (hw->phy.type == e1000_phy_82578) {
1792                 /* Return registers to default by doing a soft reset then
1793                  * writing 0x3140 to the control register.
1794                  */
1795                 if (hw->phy.revision < 2) {
1796                         e1000e_phy_sw_reset(hw);
1797                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1798                 }
1799         }
1800
1801         /* Select page 0 */
1802         ret_val = hw->phy.ops.acquire(hw);
1803         if (ret_val)
1804                 return ret_val;
1805
1806         hw->phy.addr = 1;
1807         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1808         hw->phy.ops.release(hw);
1809         if (ret_val)
1810                 return ret_val;
1811
1812         /* Configure the K1 Si workaround during phy reset assuming there is
1813          * link so that it disables K1 if link is in 1Gbps.
1814          */
1815         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1816         if (ret_val)
1817                 return ret_val;
1818
1819         /* Workaround for link disconnects on a busy hub in half duplex */
1820         ret_val = hw->phy.ops.acquire(hw);
1821         if (ret_val)
1822                 return ret_val;
1823         ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1824         if (ret_val)
1825                 goto release;
1826         ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
1827         if (ret_val)
1828                 goto release;
1829
1830         /* set MSE higher to enable link to stay up when noise is high */
1831         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
1832 release:
1833         hw->phy.ops.release(hw);
1834
1835         return ret_val;
1836 }
1837
1838 /**
1839  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1840  *  @hw:   pointer to the HW structure
1841  **/
1842 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1843 {
1844         u32 mac_reg;
1845         u16 i, phy_reg = 0;
1846         s32 ret_val;
1847
1848         ret_val = hw->phy.ops.acquire(hw);
1849         if (ret_val)
1850                 return;
1851         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1852         if (ret_val)
1853                 goto release;
1854
1855         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1856         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1857                 mac_reg = er32(RAL(i));
1858                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1859                                            (u16)(mac_reg & 0xFFFF));
1860                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1861                                            (u16)((mac_reg >> 16) & 0xFFFF));
1862
1863                 mac_reg = er32(RAH(i));
1864                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1865                                            (u16)(mac_reg & 0xFFFF));
1866                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1867                                            (u16)((mac_reg & E1000_RAH_AV)
1868                                                  >> 16));
1869         }
1870
1871         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1872
1873 release:
1874         hw->phy.ops.release(hw);
1875 }
1876
1877 /**
1878  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1879  *  with 82579 PHY
1880  *  @hw: pointer to the HW structure
1881  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1882  **/
1883 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1884 {
1885         s32 ret_val = 0;
1886         u16 phy_reg, data;
1887         u32 mac_reg;
1888         u16 i;
1889
1890         if (hw->mac.type < e1000_pch2lan)
1891                 return 0;
1892
1893         /* disable Rx path while enabling/disabling workaround */
1894         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1895         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1896         if (ret_val)
1897                 return ret_val;
1898
1899         if (enable) {
1900                 /* Write Rx addresses (rar_entry_count for RAL/H, +4 for
1901                  * SHRAL/H) and initial CRC values to the MAC
1902                  */
1903                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1904                         u8 mac_addr[ETH_ALEN] = {0};
1905                         u32 addr_high, addr_low;
1906
1907                         addr_high = er32(RAH(i));
1908                         if (!(addr_high & E1000_RAH_AV))
1909                                 continue;
1910                         addr_low = er32(RAL(i));
1911                         mac_addr[0] = (addr_low & 0xFF);
1912                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1913                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1914                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1915                         mac_addr[4] = (addr_high & 0xFF);
1916                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1917
1918                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1919                 }
1920
1921                 /* Write Rx addresses to the PHY */
1922                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1923
1924                 /* Enable jumbo frame workaround in the MAC */
1925                 mac_reg = er32(FFLT_DBG);
1926                 mac_reg &= ~(1 << 14);
1927                 mac_reg |= (7 << 15);
1928                 ew32(FFLT_DBG, mac_reg);
1929
1930                 mac_reg = er32(RCTL);
1931                 mac_reg |= E1000_RCTL_SECRC;
1932                 ew32(RCTL, mac_reg);
1933
1934                 ret_val = e1000e_read_kmrn_reg(hw,
1935                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1936                                                 &data);
1937                 if (ret_val)
1938                         return ret_val;
1939                 ret_val = e1000e_write_kmrn_reg(hw,
1940                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1941                                                 data | (1 << 0));
1942                 if (ret_val)
1943                         return ret_val;
1944                 ret_val = e1000e_read_kmrn_reg(hw,
1945                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1946                                                 &data);
1947                 if (ret_val)
1948                         return ret_val;
1949                 data &= ~(0xF << 8);
1950                 data |= (0xB << 8);
1951                 ret_val = e1000e_write_kmrn_reg(hw,
1952                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1953                                                 data);
1954                 if (ret_val)
1955                         return ret_val;
1956
1957                 /* Enable jumbo frame workaround in the PHY */
1958                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1959                 data &= ~(0x7F << 5);
1960                 data |= (0x37 << 5);
1961                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1962                 if (ret_val)
1963                         return ret_val;
1964                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1965                 data &= ~(1 << 13);
1966                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1967                 if (ret_val)
1968                         return ret_val;
1969                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1970                 data &= ~(0x3FF << 2);
1971                 data |= (0x1A << 2);
1972                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1973                 if (ret_val)
1974                         return ret_val;
1975                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
1976                 if (ret_val)
1977                         return ret_val;
1978                 e1e_rphy(hw, HV_PM_CTRL, &data);
1979                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1980                 if (ret_val)
1981                         return ret_val;
1982         } else {
1983                 /* Write MAC register values back to h/w defaults */
1984                 mac_reg = er32(FFLT_DBG);
1985                 mac_reg &= ~(0xF << 14);
1986                 ew32(FFLT_DBG, mac_reg);
1987
1988                 mac_reg = er32(RCTL);
1989                 mac_reg &= ~E1000_RCTL_SECRC;
1990                 ew32(RCTL, mac_reg);
1991
1992                 ret_val = e1000e_read_kmrn_reg(hw,
1993                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1994                                                 &data);
1995                 if (ret_val)
1996                         return ret_val;
1997                 ret_val = e1000e_write_kmrn_reg(hw,
1998                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1999                                                 data & ~(1 << 0));
2000                 if (ret_val)
2001                         return ret_val;
2002                 ret_val = e1000e_read_kmrn_reg(hw,
2003                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2004                                                 &data);
2005                 if (ret_val)
2006                         return ret_val;
2007                 data &= ~(0xF << 8);
2008                 data |= (0xB << 8);
2009                 ret_val = e1000e_write_kmrn_reg(hw,
2010                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2011                                                 data);
2012                 if (ret_val)
2013                         return ret_val;
2014
2015                 /* Write PHY register values back to h/w defaults */
2016                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2017                 data &= ~(0x7F << 5);
2018                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2019                 if (ret_val)
2020                         return ret_val;
2021                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2022                 data |= (1 << 13);
2023                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2024                 if (ret_val)
2025                         return ret_val;
2026                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2027                 data &= ~(0x3FF << 2);
2028                 data |= (0x8 << 2);
2029                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2030                 if (ret_val)
2031                         return ret_val;
2032                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2033                 if (ret_val)
2034                         return ret_val;
2035                 e1e_rphy(hw, HV_PM_CTRL, &data);
2036                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
2037                 if (ret_val)
2038                         return ret_val;
2039         }
2040
2041         /* re-enable Rx path after enabling/disabling workaround */
2042         return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
2043 }
2044
2045 /**
2046  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2047  *  done after every PHY reset.
2048  **/
2049 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2050 {
2051         s32 ret_val = 0;
2052
2053         if (hw->mac.type != e1000_pch2lan)
2054                 return 0;
2055
2056         /* Set MDIO slow mode before any other MDIO access */
2057         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2058         if (ret_val)
2059                 return ret_val;
2060
2061         ret_val = hw->phy.ops.acquire(hw);
2062         if (ret_val)
2063                 return ret_val;
2064         /* set MSE higher to enable link to stay up when noise is high */
2065         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2066         if (ret_val)
2067                 goto release;
2068         /* drop link after 5 times MSE threshold was reached */
2069         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2070 release:
2071         hw->phy.ops.release(hw);
2072
2073         return ret_val;
2074 }
2075
2076 /**
2077  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2078  *  @hw:   pointer to the HW structure
2079  *
2080  *  Workaround to set the K1 beacon duration for 82579 parts
2081  **/
2082 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2083 {
2084         s32 ret_val = 0;
2085         u16 status_reg = 0;
2086         u32 mac_reg;
2087         u16 phy_reg;
2088
2089         if (hw->mac.type != e1000_pch2lan)
2090                 return 0;
2091
2092         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
2093         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2094         if (ret_val)
2095                 return ret_val;
2096
2097         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2098             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2099                 mac_reg = er32(FEXTNVM4);
2100                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2101
2102                 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
2103                 if (ret_val)
2104                         return ret_val;
2105
2106                 if (status_reg & HV_M_STATUS_SPEED_1000) {
2107                         u16 pm_phy_reg;
2108
2109                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
2110                         phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2111                         /* LV 1G Packet drop issue wa  */
2112                         ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2113                         if (ret_val)
2114                                 return ret_val;
2115                         pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
2116                         ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2117                         if (ret_val)
2118                                 return ret_val;
2119                 } else {
2120                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2121                         phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2122                 }
2123                 ew32(FEXTNVM4, mac_reg);
2124                 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
2125         }
2126
2127         return ret_val;
2128 }
2129
2130 /**
2131  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2132  *  @hw:   pointer to the HW structure
2133  *  @gate: boolean set to true to gate, false to ungate
2134  *
2135  *  Gate/ungate the automatic PHY configuration via hardware; perform
2136  *  the configuration via software instead.
2137  **/
2138 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2139 {
2140         u32 extcnf_ctrl;
2141
2142         if (hw->mac.type < e1000_pch2lan)
2143                 return;
2144
2145         extcnf_ctrl = er32(EXTCNF_CTRL);
2146
2147         if (gate)
2148                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2149         else
2150                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2151
2152         ew32(EXTCNF_CTRL, extcnf_ctrl);
2153 }
2154
2155 /**
2156  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2157  *  @hw: pointer to the HW structure
2158  *
2159  *  Check the appropriate indication the MAC has finished configuring the
2160  *  PHY after a software reset.
2161  **/
2162 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2163 {
2164         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2165
2166         /* Wait for basic configuration completes before proceeding */
2167         do {
2168                 data = er32(STATUS);
2169                 data &= E1000_STATUS_LAN_INIT_DONE;
2170                 udelay(100);
2171         } while ((!data) && --loop);
2172
2173         /* If basic configuration is incomplete before the above loop
2174          * count reaches 0, loading the configuration from NVM will
2175          * leave the PHY in a bad state possibly resulting in no link.
2176          */
2177         if (loop == 0)
2178                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2179
2180         /* Clear the Init Done bit for the next init event */
2181         data = er32(STATUS);
2182         data &= ~E1000_STATUS_LAN_INIT_DONE;
2183         ew32(STATUS, data);
2184 }
2185
2186 /**
2187  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2188  *  @hw: pointer to the HW structure
2189  **/
2190 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2191 {
2192         s32 ret_val = 0;
2193         u16 reg;
2194
2195         if (hw->phy.ops.check_reset_block(hw))
2196                 return 0;
2197
2198         /* Allow time for h/w to get to quiescent state after reset */
2199         usleep_range(10000, 20000);
2200
2201         /* Perform any necessary post-reset workarounds */
2202         switch (hw->mac.type) {
2203         case e1000_pchlan:
2204                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2205                 if (ret_val)
2206                         return ret_val;
2207                 break;
2208         case e1000_pch2lan:
2209                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2210                 if (ret_val)
2211                         return ret_val;
2212                 break;
2213         default:
2214                 break;
2215         }
2216
2217         /* Clear the host wakeup bit after lcd reset */
2218         if (hw->mac.type >= e1000_pchlan) {
2219                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2220                 reg &= ~BM_WUC_HOST_WU_BIT;
2221                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2222         }
2223
2224         /* Configure the LCD with the extended configuration region in NVM */
2225         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2226         if (ret_val)
2227                 return ret_val;
2228
2229         /* Configure the LCD with the OEM bits in NVM */
2230         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2231
2232         if (hw->mac.type == e1000_pch2lan) {
2233                 /* Ungate automatic PHY configuration on non-managed 82579 */
2234                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2235                         usleep_range(10000, 20000);
2236                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2237                 }
2238
2239                 /* Set EEE LPI Update Timer to 200usec */
2240                 ret_val = hw->phy.ops.acquire(hw);
2241                 if (ret_val)
2242                         return ret_val;
2243                 ret_val = e1000_write_emi_reg_locked(hw,
2244                                                      I82579_LPI_UPDATE_TIMER,
2245                                                      0x1387);
2246                 hw->phy.ops.release(hw);
2247         }
2248
2249         return ret_val;
2250 }
2251
2252 /**
2253  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2254  *  @hw: pointer to the HW structure
2255  *
2256  *  Resets the PHY
2257  *  This is a function pointer entry point called by drivers
2258  *  or other shared routines.
2259  **/
2260 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2261 {
2262         s32 ret_val = 0;
2263
2264         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2265         if ((hw->mac.type == e1000_pch2lan) &&
2266             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2267                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2268
2269         ret_val = e1000e_phy_hw_reset_generic(hw);
2270         if (ret_val)
2271                 return ret_val;
2272
2273         return e1000_post_phy_reset_ich8lan(hw);
2274 }
2275
2276 /**
2277  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2278  *  @hw: pointer to the HW structure
2279  *  @active: true to enable LPLU, false to disable
2280  *
2281  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2282  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2283  *  the phy speed. This function will manually set the LPLU bit and restart
2284  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2285  *  since it configures the same bit.
2286  **/
2287 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2288 {
2289         s32 ret_val = 0;
2290         u16 oem_reg;
2291
2292         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2293         if (ret_val)
2294                 return ret_val;
2295
2296         if (active)
2297                 oem_reg |= HV_OEM_BITS_LPLU;
2298         else
2299                 oem_reg &= ~HV_OEM_BITS_LPLU;
2300
2301         if (!hw->phy.ops.check_reset_block(hw))
2302                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2303
2304         return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2305 }
2306
2307 /**
2308  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2309  *  @hw: pointer to the HW structure
2310  *  @active: true to enable LPLU, false to disable
2311  *
2312  *  Sets the LPLU D0 state according to the active flag.  When
2313  *  activating LPLU this function also disables smart speed
2314  *  and vice versa.  LPLU will not be activated unless the
2315  *  device autonegotiation advertisement meets standards of
2316  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2317  *  This is a function pointer entry point only called by
2318  *  PHY setup routines.
2319  **/
2320 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2321 {
2322         struct e1000_phy_info *phy = &hw->phy;
2323         u32 phy_ctrl;
2324         s32 ret_val = 0;
2325         u16 data;
2326
2327         if (phy->type == e1000_phy_ife)
2328                 return 0;
2329
2330         phy_ctrl = er32(PHY_CTRL);
2331
2332         if (active) {
2333                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2334                 ew32(PHY_CTRL, phy_ctrl);
2335
2336                 if (phy->type != e1000_phy_igp_3)
2337                         return 0;
2338
2339                 /* Call gig speed drop workaround on LPLU before accessing
2340                  * any PHY registers
2341                  */
2342                 if (hw->mac.type == e1000_ich8lan)
2343                         e1000e_gig_downshift_workaround_ich8lan(hw);
2344
2345                 /* When LPLU is enabled, we should disable SmartSpeed */
2346                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2347                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2348                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2349                 if (ret_val)
2350                         return ret_val;
2351         } else {
2352                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2353                 ew32(PHY_CTRL, phy_ctrl);
2354
2355                 if (phy->type != e1000_phy_igp_3)
2356                         return 0;
2357
2358                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2359                  * during Dx states where the power conservation is most
2360                  * important.  During driver activity we should enable
2361                  * SmartSpeed, so performance is maintained.
2362                  */
2363                 if (phy->smart_speed == e1000_smart_speed_on) {
2364                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2365                                            &data);
2366                         if (ret_val)
2367                                 return ret_val;
2368
2369                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2370                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2371                                            data);
2372                         if (ret_val)
2373                                 return ret_val;
2374                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2375                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2376                                            &data);
2377                         if (ret_val)
2378                                 return ret_val;
2379
2380                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2381                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2382                                            data);
2383                         if (ret_val)
2384                                 return ret_val;
2385                 }
2386         }
2387
2388         return 0;
2389 }
2390
2391 /**
2392  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2393  *  @hw: pointer to the HW structure
2394  *  @active: true to enable LPLU, false to disable
2395  *
2396  *  Sets the LPLU D3 state according to the active flag.  When
2397  *  activating LPLU this function also disables smart speed
2398  *  and vice versa.  LPLU will not be activated unless the
2399  *  device autonegotiation advertisement meets standards of
2400  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2401  *  This is a function pointer entry point only called by
2402  *  PHY setup routines.
2403  **/
2404 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2405 {
2406         struct e1000_phy_info *phy = &hw->phy;
2407         u32 phy_ctrl;
2408         s32 ret_val = 0;
2409         u16 data;
2410
2411         phy_ctrl = er32(PHY_CTRL);
2412
2413         if (!active) {
2414                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2415                 ew32(PHY_CTRL, phy_ctrl);
2416
2417                 if (phy->type != e1000_phy_igp_3)
2418                         return 0;
2419
2420                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2421                  * during Dx states where the power conservation is most
2422                  * important.  During driver activity we should enable
2423                  * SmartSpeed, so performance is maintained.
2424                  */
2425                 if (phy->smart_speed == e1000_smart_speed_on) {
2426                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2427                                            &data);
2428                         if (ret_val)
2429                                 return ret_val;
2430
2431                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2432                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2433                                            data);
2434                         if (ret_val)
2435                                 return ret_val;
2436                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2437                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2438                                            &data);
2439                         if (ret_val)
2440                                 return ret_val;
2441
2442                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2443                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2444                                            data);
2445                         if (ret_val)
2446                                 return ret_val;
2447                 }
2448         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2449                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2450                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2451                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2452                 ew32(PHY_CTRL, phy_ctrl);
2453
2454                 if (phy->type != e1000_phy_igp_3)
2455                         return 0;
2456
2457                 /* Call gig speed drop workaround on LPLU before accessing
2458                  * any PHY registers
2459                  */
2460                 if (hw->mac.type == e1000_ich8lan)
2461                         e1000e_gig_downshift_workaround_ich8lan(hw);
2462
2463                 /* When LPLU is enabled, we should disable SmartSpeed */
2464                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2465                 if (ret_val)
2466                         return ret_val;
2467
2468                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2469                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2470         }
2471
2472         return ret_val;
2473 }
2474
2475 /**
2476  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2477  *  @hw: pointer to the HW structure
2478  *  @bank:  pointer to the variable that returns the active bank
2479  *
2480  *  Reads signature byte from the NVM using the flash access registers.
2481  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2482  **/
2483 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2484 {
2485         u32 eecd;
2486         struct e1000_nvm_info *nvm = &hw->nvm;
2487         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2488         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2489         u8 sig_byte = 0;
2490         s32 ret_val;
2491
2492         switch (hw->mac.type) {
2493         case e1000_ich8lan:
2494         case e1000_ich9lan:
2495                 eecd = er32(EECD);
2496                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2497                     E1000_EECD_SEC1VAL_VALID_MASK) {
2498                         if (eecd & E1000_EECD_SEC1VAL)
2499                                 *bank = 1;
2500                         else
2501                                 *bank = 0;
2502
2503                         return 0;
2504                 }
2505                 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2506                 /* fall-thru */
2507         default:
2508                 /* set bank to 0 in case flash read fails */
2509                 *bank = 0;
2510
2511                 /* Check bank 0 */
2512                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2513                                                         &sig_byte);
2514                 if (ret_val)
2515                         return ret_val;
2516                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2517                     E1000_ICH_NVM_SIG_VALUE) {
2518                         *bank = 0;
2519                         return 0;
2520                 }
2521
2522                 /* Check bank 1 */
2523                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2524                                                         bank1_offset,
2525                                                         &sig_byte);
2526                 if (ret_val)
2527                         return ret_val;
2528                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2529                     E1000_ICH_NVM_SIG_VALUE) {
2530                         *bank = 1;
2531                         return 0;
2532                 }
2533
2534                 e_dbg("ERROR: No valid NVM bank present\n");
2535                 return -E1000_ERR_NVM;
2536         }
2537 }
2538
2539 /**
2540  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2541  *  @hw: pointer to the HW structure
2542  *  @offset: The offset (in bytes) of the word(s) to read.
2543  *  @words: Size of data to read in words
2544  *  @data: Pointer to the word(s) to read at offset.
2545  *
2546  *  Reads a word(s) from the NVM using the flash access registers.
2547  **/
2548 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2549                                   u16 *data)
2550 {
2551         struct e1000_nvm_info *nvm = &hw->nvm;
2552         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2553         u32 act_offset;
2554         s32 ret_val = 0;
2555         u32 bank = 0;
2556         u16 i, word;
2557
2558         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2559             (words == 0)) {
2560                 e_dbg("nvm parameter(s) out of bounds\n");
2561                 ret_val = -E1000_ERR_NVM;
2562                 goto out;
2563         }
2564
2565         nvm->ops.acquire(hw);
2566
2567         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2568         if (ret_val) {
2569                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2570                 bank = 0;
2571         }
2572
2573         act_offset = (bank) ? nvm->flash_bank_size : 0;
2574         act_offset += offset;
2575
2576         ret_val = 0;
2577         for (i = 0; i < words; i++) {
2578                 if (dev_spec->shadow_ram[offset+i].modified) {
2579                         data[i] = dev_spec->shadow_ram[offset+i].value;
2580                 } else {
2581                         ret_val = e1000_read_flash_word_ich8lan(hw,
2582                                                                 act_offset + i,
2583                                                                 &word);
2584                         if (ret_val)
2585                                 break;
2586                         data[i] = word;
2587                 }
2588         }
2589
2590         nvm->ops.release(hw);
2591
2592 out:
2593         if (ret_val)
2594                 e_dbg("NVM read error: %d\n", ret_val);
2595
2596         return ret_val;
2597 }
2598
2599 /**
2600  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2601  *  @hw: pointer to the HW structure
2602  *
2603  *  This function does initial flash setup so that a new read/write/erase cycle
2604  *  can be started.
2605  **/
2606 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2607 {
2608         union ich8_hws_flash_status hsfsts;
2609         s32 ret_val = -E1000_ERR_NVM;
2610
2611         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2612
2613         /* Check if the flash descriptor is valid */
2614         if (!hsfsts.hsf_status.fldesvalid) {
2615                 e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
2616                 return -E1000_ERR_NVM;
2617         }
2618
2619         /* Clear FCERR and DAEL in hw status by writing 1 */
2620         hsfsts.hsf_status.flcerr = 1;
2621         hsfsts.hsf_status.dael = 1;
2622
2623         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2624
2625         /* Either we should have a hardware SPI cycle in progress
2626          * bit to check against, in order to start a new cycle or
2627          * FDONE bit should be changed in the hardware so that it
2628          * is 1 after hardware reset, which can then be used as an
2629          * indication whether a cycle is in progress or has been
2630          * completed.
2631          */
2632
2633         if (!hsfsts.hsf_status.flcinprog) {
2634                 /* There is no cycle running at present,
2635                  * so we can start a cycle.
2636                  * Begin by setting Flash Cycle Done.
2637                  */
2638                 hsfsts.hsf_status.flcdone = 1;
2639                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2640                 ret_val = 0;
2641         } else {
2642                 s32 i;
2643
2644                 /* Otherwise poll for sometime so the current
2645                  * cycle has a chance to end before giving up.
2646                  */
2647                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2648                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2649                         if (!hsfsts.hsf_status.flcinprog) {
2650                                 ret_val = 0;
2651                                 break;
2652                         }
2653                         udelay(1);
2654                 }
2655                 if (!ret_val) {
2656                         /* Successful in waiting for previous cycle to timeout,
2657                          * now set the Flash Cycle Done.
2658                          */
2659                         hsfsts.hsf_status.flcdone = 1;
2660                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2661                 } else {
2662                         e_dbg("Flash controller busy, cannot get access\n");
2663                 }
2664         }
2665
2666         return ret_val;
2667 }
2668
2669 /**
2670  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2671  *  @hw: pointer to the HW structure
2672  *  @timeout: maximum time to wait for completion
2673  *
2674  *  This function starts a flash cycle and waits for its completion.
2675  **/
2676 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2677 {
2678         union ich8_hws_flash_ctrl hsflctl;
2679         union ich8_hws_flash_status hsfsts;
2680         u32 i = 0;
2681
2682         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2683         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2684         hsflctl.hsf_ctrl.flcgo = 1;
2685         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2686
2687         /* wait till FDONE bit is set to 1 */
2688         do {
2689                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2690                 if (hsfsts.hsf_status.flcdone)
2691                         break;
2692                 udelay(1);
2693         } while (i++ < timeout);
2694
2695         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
2696                 return 0;
2697
2698         return -E1000_ERR_NVM;
2699 }
2700
2701 /**
2702  *  e1000_read_flash_word_ich8lan - Read word from flash
2703  *  @hw: pointer to the HW structure
2704  *  @offset: offset to data location
2705  *  @data: pointer to the location for storing the data
2706  *
2707  *  Reads the flash word at offset into data.  Offset is converted
2708  *  to bytes before read.
2709  **/
2710 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2711                                          u16 *data)
2712 {
2713         /* Must convert offset into bytes. */
2714         offset <<= 1;
2715
2716         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2717 }
2718
2719 /**
2720  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2721  *  @hw: pointer to the HW structure
2722  *  @offset: The offset of the byte to read.
2723  *  @data: Pointer to a byte to store the value read.
2724  *
2725  *  Reads a single byte from the NVM using the flash access registers.
2726  **/
2727 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2728                                          u8 *data)
2729 {
2730         s32 ret_val;
2731         u16 word = 0;
2732
2733         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2734         if (ret_val)
2735                 return ret_val;
2736
2737         *data = (u8)word;
2738
2739         return 0;
2740 }
2741
2742 /**
2743  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2744  *  @hw: pointer to the HW structure
2745  *  @offset: The offset (in bytes) of the byte or word to read.
2746  *  @size: Size of data to read, 1=byte 2=word
2747  *  @data: Pointer to the word to store the value read.
2748  *
2749  *  Reads a byte or word from the NVM using the flash access registers.
2750  **/
2751 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2752                                          u8 size, u16 *data)
2753 {
2754         union ich8_hws_flash_status hsfsts;
2755         union ich8_hws_flash_ctrl hsflctl;
2756         u32 flash_linear_addr;
2757         u32 flash_data = 0;
2758         s32 ret_val = -E1000_ERR_NVM;
2759         u8 count = 0;
2760
2761         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2762                 return -E1000_ERR_NVM;
2763
2764         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2765                             hw->nvm.flash_base_addr;
2766
2767         do {
2768                 udelay(1);
2769                 /* Steps */
2770                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2771                 if (ret_val)
2772                         break;
2773
2774                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2775                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2776                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2777                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2778                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2779
2780                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2781
2782                 ret_val = e1000_flash_cycle_ich8lan(hw,
2783                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
2784
2785                 /* Check if FCERR is set to 1, if set to 1, clear it
2786                  * and try the whole sequence a few more times, else
2787                  * read in (shift in) the Flash Data0, the order is
2788                  * least significant byte first msb to lsb
2789                  */
2790                 if (!ret_val) {
2791                         flash_data = er32flash(ICH_FLASH_FDATA0);
2792                         if (size == 1)
2793                                 *data = (u8)(flash_data & 0x000000FF);
2794                         else if (size == 2)
2795                                 *data = (u16)(flash_data & 0x0000FFFF);
2796                         break;
2797                 } else {
2798                         /* If we've gotten here, then things are probably
2799                          * completely hosed, but if the error condition is
2800                          * detected, it won't hurt to give it another try...
2801                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2802                          */
2803                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2804                         if (hsfsts.hsf_status.flcerr) {
2805                                 /* Repeat for some time before giving up. */
2806                                 continue;
2807                         } else if (!hsfsts.hsf_status.flcdone) {
2808                                 e_dbg("Timeout error - flash cycle did not complete.\n");
2809                                 break;
2810                         }
2811                 }
2812         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2813
2814         return ret_val;
2815 }
2816
2817 /**
2818  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2819  *  @hw: pointer to the HW structure
2820  *  @offset: The offset (in bytes) of the word(s) to write.
2821  *  @words: Size of data to write in words
2822  *  @data: Pointer to the word(s) to write at offset.
2823  *
2824  *  Writes a byte or word to the NVM using the flash access registers.
2825  **/
2826 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2827                                    u16 *data)
2828 {
2829         struct e1000_nvm_info *nvm = &hw->nvm;
2830         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2831         u16 i;
2832
2833         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2834             (words == 0)) {
2835                 e_dbg("nvm parameter(s) out of bounds\n");
2836                 return -E1000_ERR_NVM;
2837         }
2838
2839         nvm->ops.acquire(hw);
2840
2841         for (i = 0; i < words; i++) {
2842                 dev_spec->shadow_ram[offset+i].modified = true;
2843                 dev_spec->shadow_ram[offset+i].value = data[i];
2844         }
2845
2846         nvm->ops.release(hw);
2847
2848         return 0;
2849 }
2850
2851 /**
2852  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2853  *  @hw: pointer to the HW structure
2854  *
2855  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2856  *  which writes the checksum to the shadow ram.  The changes in the shadow
2857  *  ram are then committed to the EEPROM by processing each bank at a time
2858  *  checking for the modified bit and writing only the pending changes.
2859  *  After a successful commit, the shadow ram is cleared and is ready for
2860  *  future writes.
2861  **/
2862 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2863 {
2864         struct e1000_nvm_info *nvm = &hw->nvm;
2865         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2866         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2867         s32 ret_val;
2868         u16 data;
2869
2870         ret_val = e1000e_update_nvm_checksum_generic(hw);
2871         if (ret_val)
2872                 goto out;
2873
2874         if (nvm->type != e1000_nvm_flash_sw)
2875                 goto out;
2876
2877         nvm->ops.acquire(hw);
2878
2879         /* We're writing to the opposite bank so if we're on bank 1,
2880          * write to bank 0 etc.  We also need to erase the segment that
2881          * is going to be written
2882          */
2883         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2884         if (ret_val) {
2885                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2886                 bank = 0;
2887         }
2888
2889         if (bank == 0) {
2890                 new_bank_offset = nvm->flash_bank_size;
2891                 old_bank_offset = 0;
2892                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2893                 if (ret_val)
2894                         goto release;
2895         } else {
2896                 old_bank_offset = nvm->flash_bank_size;
2897                 new_bank_offset = 0;
2898                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2899                 if (ret_val)
2900                         goto release;
2901         }
2902
2903         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2904                 /* Determine whether to write the value stored
2905                  * in the other NVM bank or a modified value stored
2906                  * in the shadow RAM
2907                  */
2908                 if (dev_spec->shadow_ram[i].modified) {
2909                         data = dev_spec->shadow_ram[i].value;
2910                 } else {
2911                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2912                                                                 old_bank_offset,
2913                                                                 &data);
2914                         if (ret_val)
2915                                 break;
2916                 }
2917
2918                 /* If the word is 0x13, then make sure the signature bits
2919                  * (15:14) are 11b until the commit has completed.
2920                  * This will allow us to write 10b which indicates the
2921                  * signature is valid.  We want to do this after the write
2922                  * has completed so that we don't mark the segment valid
2923                  * while the write is still in progress
2924                  */
2925                 if (i == E1000_ICH_NVM_SIG_WORD)
2926                         data |= E1000_ICH_NVM_SIG_MASK;
2927
2928                 /* Convert offset to bytes. */
2929                 act_offset = (i + new_bank_offset) << 1;
2930
2931                 udelay(100);
2932                 /* Write the bytes to the new bank. */
2933                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2934                                                                act_offset,
2935                                                                (u8)data);
2936                 if (ret_val)
2937                         break;
2938
2939                 udelay(100);
2940                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2941                                                           act_offset + 1,
2942                                                           (u8)(data >> 8));
2943                 if (ret_val)
2944                         break;
2945         }
2946
2947         /* Don't bother writing the segment valid bits if sector
2948          * programming failed.
2949          */
2950         if (ret_val) {
2951                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2952                 e_dbg("Flash commit failed.\n");
2953                 goto release;
2954         }
2955
2956         /* Finally validate the new segment by setting bit 15:14
2957          * to 10b in word 0x13 , this can be done without an
2958          * erase as well since these bits are 11 to start with
2959          * and we need to change bit 14 to 0b
2960          */
2961         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2962         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2963         if (ret_val)
2964                 goto release;
2965
2966         data &= 0xBFFF;
2967         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2968                                                        act_offset * 2 + 1,
2969                                                        (u8)(data >> 8));
2970         if (ret_val)
2971                 goto release;
2972
2973         /* And invalidate the previously valid segment by setting
2974          * its signature word (0x13) high_byte to 0b. This can be
2975          * done without an erase because flash erase sets all bits
2976          * to 1's. We can write 1's to 0's without an erase
2977          */
2978         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2979         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2980         if (ret_val)
2981                 goto release;
2982
2983         /* Great!  Everything worked, we can now clear the cached entries. */
2984         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2985                 dev_spec->shadow_ram[i].modified = false;
2986                 dev_spec->shadow_ram[i].value = 0xFFFF;
2987         }
2988
2989 release:
2990         nvm->ops.release(hw);
2991
2992         /* Reload the EEPROM, or else modifications will not appear
2993          * until after the next adapter reset.
2994          */
2995         if (!ret_val) {
2996                 nvm->ops.reload(hw);
2997                 usleep_range(10000, 20000);
2998         }
2999
3000 out:
3001         if (ret_val)
3002                 e_dbg("NVM update error: %d\n", ret_val);
3003
3004         return ret_val;
3005 }
3006
3007 /**
3008  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3009  *  @hw: pointer to the HW structure
3010  *
3011  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3012  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
3013  *  calculated, in which case we need to calculate the checksum and set bit 6.
3014  **/
3015 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3016 {
3017         s32 ret_val;
3018         u16 data;
3019         u16 word;
3020         u16 valid_csum_mask;
3021
3022         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
3023          * the checksum needs to be fixed.  This bit is an indication that
3024          * the NVM was prepared by OEM software and did not calculate
3025          * the checksum...a likely scenario.
3026          */
3027         switch (hw->mac.type) {
3028         case e1000_pch_lpt:
3029                 word = NVM_COMPAT;
3030                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3031                 break;
3032         default:
3033                 word = NVM_FUTURE_INIT_WORD1;
3034                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3035                 break;
3036         }
3037
3038         ret_val = e1000_read_nvm(hw, word, 1, &data);
3039         if (ret_val)
3040                 return ret_val;
3041
3042         if (!(data & valid_csum_mask)) {
3043                 data |= valid_csum_mask;
3044                 ret_val = e1000_write_nvm(hw, word, 1, &data);
3045                 if (ret_val)
3046                         return ret_val;
3047                 ret_val = e1000e_update_nvm_checksum(hw);
3048                 if (ret_val)
3049                         return ret_val;
3050         }
3051
3052         return e1000e_validate_nvm_checksum_generic(hw);
3053 }
3054
3055 /**
3056  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
3057  *  @hw: pointer to the HW structure
3058  *
3059  *  To prevent malicious write/erase of the NVM, set it to be read-only
3060  *  so that the hardware ignores all write/erase cycles of the NVM via
3061  *  the flash control registers.  The shadow-ram copy of the NVM will
3062  *  still be updated, however any updates to this copy will not stick
3063  *  across driver reloads.
3064  **/
3065 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
3066 {
3067         struct e1000_nvm_info *nvm = &hw->nvm;
3068         union ich8_flash_protected_range pr0;
3069         union ich8_hws_flash_status hsfsts;
3070         u32 gfpreg;
3071
3072         nvm->ops.acquire(hw);
3073
3074         gfpreg = er32flash(ICH_FLASH_GFPREG);
3075
3076         /* Write-protect GbE Sector of NVM */
3077         pr0.regval = er32flash(ICH_FLASH_PR0);
3078         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
3079         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
3080         pr0.range.wpe = true;
3081         ew32flash(ICH_FLASH_PR0, pr0.regval);
3082
3083         /* Lock down a subset of GbE Flash Control Registers, e.g.
3084          * PR0 to prevent the write-protection from being lifted.
3085          * Once FLOCKDN is set, the registers protected by it cannot
3086          * be written until FLOCKDN is cleared by a hardware reset.
3087          */
3088         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3089         hsfsts.hsf_status.flockdn = true;
3090         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3091
3092         nvm->ops.release(hw);
3093 }
3094
3095 /**
3096  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3097  *  @hw: pointer to the HW structure
3098  *  @offset: The offset (in bytes) of the byte/word to read.
3099  *  @size: Size of data to read, 1=byte 2=word
3100  *  @data: The byte(s) to write to the NVM.
3101  *
3102  *  Writes one/two bytes to the NVM using the flash access registers.
3103  **/
3104 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3105                                           u8 size, u16 data)
3106 {
3107         union ich8_hws_flash_status hsfsts;
3108         union ich8_hws_flash_ctrl hsflctl;
3109         u32 flash_linear_addr;
3110         u32 flash_data = 0;
3111         s32 ret_val;
3112         u8 count = 0;
3113
3114         if (size < 1 || size > 2 || data > size * 0xff ||
3115             offset > ICH_FLASH_LINEAR_ADDR_MASK)
3116                 return -E1000_ERR_NVM;
3117
3118         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3119                             hw->nvm.flash_base_addr;
3120
3121         do {
3122                 udelay(1);
3123                 /* Steps */
3124                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3125                 if (ret_val)
3126                         break;
3127
3128                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3129                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3130                 hsflctl.hsf_ctrl.fldbcount = size -1;
3131                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3132                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3133
3134                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3135
3136                 if (size == 1)
3137                         flash_data = (u32)data & 0x00FF;
3138                 else
3139                         flash_data = (u32)data;
3140
3141                 ew32flash(ICH_FLASH_FDATA0, flash_data);
3142
3143                 /* check if FCERR is set to 1 , if set to 1, clear it
3144                  * and try the whole sequence a few more times else done
3145                  */
3146                 ret_val = e1000_flash_cycle_ich8lan(hw,
3147                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3148                 if (!ret_val)
3149                         break;
3150
3151                 /* If we're here, then things are most likely
3152                  * completely hosed, but if the error condition
3153                  * is detected, it won't hurt to give it another
3154                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3155                  */
3156                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3157                 if (hsfsts.hsf_status.flcerr)
3158                         /* Repeat for some time before giving up. */
3159                         continue;
3160                 if (!hsfsts.hsf_status.flcdone) {
3161                         e_dbg("Timeout error - flash cycle did not complete.\n");
3162                         break;
3163                 }
3164         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3165
3166         return ret_val;
3167 }
3168
3169 /**
3170  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3171  *  @hw: pointer to the HW structure
3172  *  @offset: The index of the byte to read.
3173  *  @data: The byte to write to the NVM.
3174  *
3175  *  Writes a single byte to the NVM using the flash access registers.
3176  **/
3177 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3178                                           u8 data)
3179 {
3180         u16 word = (u16)data;
3181
3182         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3183 }
3184
3185 /**
3186  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3187  *  @hw: pointer to the HW structure
3188  *  @offset: The offset of the byte to write.
3189  *  @byte: The byte to write to the NVM.
3190  *
3191  *  Writes a single byte to the NVM using the flash access registers.
3192  *  Goes through a retry algorithm before giving up.
3193  **/
3194 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3195                                                 u32 offset, u8 byte)
3196 {
3197         s32 ret_val;
3198         u16 program_retries;
3199
3200         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3201         if (!ret_val)
3202                 return ret_val;
3203
3204         for (program_retries = 0; program_retries < 100; program_retries++) {
3205                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
3206                 udelay(100);
3207                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3208                 if (!ret_val)
3209                         break;
3210         }
3211         if (program_retries == 100)
3212                 return -E1000_ERR_NVM;
3213
3214         return 0;
3215 }
3216
3217 /**
3218  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3219  *  @hw: pointer to the HW structure
3220  *  @bank: 0 for first bank, 1 for second bank, etc.
3221  *
3222  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3223  *  bank N is 4096 * N + flash_reg_addr.
3224  **/
3225 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3226 {
3227         struct e1000_nvm_info *nvm = &hw->nvm;
3228         union ich8_hws_flash_status hsfsts;
3229         union ich8_hws_flash_ctrl hsflctl;
3230         u32 flash_linear_addr;
3231         /* bank size is in 16bit words - adjust to bytes */
3232         u32 flash_bank_size = nvm->flash_bank_size * 2;
3233         s32 ret_val;
3234         s32 count = 0;
3235         s32 j, iteration, sector_size;
3236
3237         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3238
3239         /* Determine HW Sector size: Read BERASE bits of hw flash status
3240          * register
3241          * 00: The Hw sector is 256 bytes, hence we need to erase 16
3242          *     consecutive sectors.  The start index for the nth Hw sector
3243          *     can be calculated as = bank * 4096 + n * 256
3244          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3245          *     The start index for the nth Hw sector can be calculated
3246          *     as = bank * 4096
3247          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3248          *     (ich9 only, otherwise error condition)
3249          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3250          */
3251         switch (hsfsts.hsf_status.berasesz) {
3252         case 0:
3253                 /* Hw sector size 256 */
3254                 sector_size = ICH_FLASH_SEG_SIZE_256;
3255                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3256                 break;
3257         case 1:
3258                 sector_size = ICH_FLASH_SEG_SIZE_4K;
3259                 iteration = 1;
3260                 break;
3261         case 2:
3262                 sector_size = ICH_FLASH_SEG_SIZE_8K;
3263                 iteration = 1;
3264                 break;
3265         case 3:
3266                 sector_size = ICH_FLASH_SEG_SIZE_64K;
3267                 iteration = 1;
3268                 break;
3269         default:
3270                 return -E1000_ERR_NVM;
3271         }
3272
3273         /* Start with the base address, then add the sector offset. */
3274         flash_linear_addr = hw->nvm.flash_base_addr;
3275         flash_linear_addr += (bank) ? flash_bank_size : 0;
3276
3277         for (j = 0; j < iteration ; j++) {
3278                 do {
3279                         /* Steps */
3280                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
3281                         if (ret_val)
3282                                 return ret_val;
3283
3284                         /* Write a value 11 (block Erase) in Flash
3285                          * Cycle field in hw flash control
3286                          */
3287                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3288                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3289                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3290
3291                         /* Write the last 24 bits of an index within the
3292                          * block into Flash Linear address field in Flash
3293                          * Address.
3294                          */
3295                         flash_linear_addr += (j * sector_size);
3296                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3297
3298                         ret_val = e1000_flash_cycle_ich8lan(hw,
3299                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
3300                         if (!ret_val)
3301                                 break;
3302
3303                         /* Check if FCERR is set to 1.  If 1,
3304                          * clear it and try the whole sequence
3305                          * a few more times else Done
3306                          */
3307                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3308                         if (hsfsts.hsf_status.flcerr)
3309                                 /* repeat for some time before giving up */
3310                                 continue;
3311                         else if (!hsfsts.hsf_status.flcdone)
3312                                 return ret_val;
3313                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3314         }
3315
3316         return 0;
3317 }
3318
3319 /**
3320  *  e1000_valid_led_default_ich8lan - Set the default LED settings
3321  *  @hw: pointer to the HW structure
3322  *  @data: Pointer to the LED settings
3323  *
3324  *  Reads the LED default settings from the NVM to data.  If the NVM LED
3325  *  settings is all 0's or F's, set the LED default to a valid LED default
3326  *  setting.
3327  **/
3328 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3329 {
3330         s32 ret_val;
3331
3332         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
3333         if (ret_val) {
3334                 e_dbg("NVM Read Error\n");
3335                 return ret_val;
3336         }
3337
3338         if (*data == ID_LED_RESERVED_0000 ||
3339             *data == ID_LED_RESERVED_FFFF)
3340                 *data = ID_LED_DEFAULT_ICH8LAN;
3341
3342         return 0;
3343 }
3344
3345 /**
3346  *  e1000_id_led_init_pchlan - store LED configurations
3347  *  @hw: pointer to the HW structure
3348  *
3349  *  PCH does not control LEDs via the LEDCTL register, rather it uses
3350  *  the PHY LED configuration register.
3351  *
3352  *  PCH also does not have an "always on" or "always off" mode which
3353  *  complicates the ID feature.  Instead of using the "on" mode to indicate
3354  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
3355  *  use "link_up" mode.  The LEDs will still ID on request if there is no
3356  *  link based on logic in e1000_led_[on|off]_pchlan().
3357  **/
3358 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3359 {
3360         struct e1000_mac_info *mac = &hw->mac;
3361         s32 ret_val;
3362         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3363         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3364         u16 data, i, temp, shift;
3365
3366         /* Get default ID LED modes */
3367         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3368         if (ret_val)
3369                 return ret_val;
3370
3371         mac->ledctl_default = er32(LEDCTL);
3372         mac->ledctl_mode1 = mac->ledctl_default;
3373         mac->ledctl_mode2 = mac->ledctl_default;
3374
3375         for (i = 0; i < 4; i++) {
3376                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3377                 shift = (i * 5);
3378                 switch (temp) {
3379                 case ID_LED_ON1_DEF2:
3380                 case ID_LED_ON1_ON2:
3381                 case ID_LED_ON1_OFF2:
3382                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3383                         mac->ledctl_mode1 |= (ledctl_on << shift);
3384                         break;
3385                 case ID_LED_OFF1_DEF2:
3386                 case ID_LED_OFF1_ON2:
3387                 case ID_LED_OFF1_OFF2:
3388                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3389                         mac->ledctl_mode1 |= (ledctl_off << shift);
3390                         break;
3391                 default:
3392                         /* Do nothing */
3393                         break;
3394                 }
3395                 switch (temp) {
3396                 case ID_LED_DEF1_ON2:
3397                 case ID_LED_ON1_ON2:
3398                 case ID_LED_OFF1_ON2:
3399                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3400                         mac->ledctl_mode2 |= (ledctl_on << shift);
3401                         break;
3402                 case ID_LED_DEF1_OFF2:
3403                 case ID_LED_ON1_OFF2:
3404                 case ID_LED_OFF1_OFF2:
3405                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3406                         mac->ledctl_mode2 |= (ledctl_off << shift);
3407                         break;
3408                 default:
3409                         /* Do nothing */
3410                         break;
3411                 }
3412         }
3413
3414         return 0;
3415 }
3416
3417 /**
3418  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3419  *  @hw: pointer to the HW structure
3420  *
3421  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3422  *  register, so the the bus width is hard coded.
3423  **/
3424 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3425 {
3426         struct e1000_bus_info *bus = &hw->bus;
3427         s32 ret_val;
3428
3429         ret_val = e1000e_get_bus_info_pcie(hw);
3430
3431         /* ICH devices are "PCI Express"-ish.  They have
3432          * a configuration space, but do not contain
3433          * PCI Express Capability registers, so bus width
3434          * must be hardcoded.
3435          */
3436         if (bus->width == e1000_bus_width_unknown)
3437                 bus->width = e1000_bus_width_pcie_x1;
3438
3439         return ret_val;
3440 }
3441
3442 /**
3443  *  e1000_reset_hw_ich8lan - Reset the hardware
3444  *  @hw: pointer to the HW structure
3445  *
3446  *  Does a full reset of the hardware which includes a reset of the PHY and
3447  *  MAC.
3448  **/
3449 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3450 {
3451         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3452         u16 kum_cfg;
3453         u32 ctrl, reg;
3454         s32 ret_val;
3455
3456         /* Prevent the PCI-E bus from sticking if there is no TLP connection
3457          * on the last TLP read/write transaction when MAC is reset.
3458          */
3459         ret_val = e1000e_disable_pcie_master(hw);
3460         if (ret_val)
3461                 e_dbg("PCI-E Master disable polling has failed.\n");
3462
3463         e_dbg("Masking off all interrupts\n");
3464         ew32(IMC, 0xffffffff);
3465
3466         /* Disable the Transmit and Receive units.  Then delay to allow
3467          * any pending transactions to complete before we hit the MAC
3468          * with the global reset.
3469          */
3470         ew32(RCTL, 0);
3471         ew32(TCTL, E1000_TCTL_PSP);
3472         e1e_flush();
3473
3474         usleep_range(10000, 20000);
3475
3476         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3477         if (hw->mac.type == e1000_ich8lan) {
3478                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3479                 ew32(PBA, E1000_PBA_8K);
3480                 /* Set Packet Buffer Size to 16k. */
3481                 ew32(PBS, E1000_PBS_16K);
3482         }
3483
3484         if (hw->mac.type == e1000_pchlan) {
3485                 /* Save the NVM K1 bit setting */
3486                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
3487                 if (ret_val)
3488                         return ret_val;
3489
3490                 if (kum_cfg & E1000_NVM_K1_ENABLE)
3491                         dev_spec->nvm_k1_enabled = true;
3492                 else
3493                         dev_spec->nvm_k1_enabled = false;
3494         }
3495
3496         ctrl = er32(CTRL);
3497
3498         if (!hw->phy.ops.check_reset_block(hw)) {
3499                 /* Full-chip reset requires MAC and PHY reset at the same
3500                  * time to make sure the interface between MAC and the
3501                  * external PHY is reset.
3502                  */
3503                 ctrl |= E1000_CTRL_PHY_RST;
3504
3505                 /* Gate automatic PHY configuration by hardware on
3506                  * non-managed 82579
3507                  */
3508                 if ((hw->mac.type == e1000_pch2lan) &&
3509                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3510                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3511         }
3512         ret_val = e1000_acquire_swflag_ich8lan(hw);
3513         e_dbg("Issuing a global reset to ich8lan\n");
3514         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3515         /* cannot issue a flush here because it hangs the hardware */
3516         msleep(20);
3517
3518         /* Set Phy Config Counter to 50msec */
3519         if (hw->mac.type == e1000_pch2lan) {
3520                 reg = er32(FEXTNVM3);
3521                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
3522                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
3523                 ew32(FEXTNVM3, reg);
3524         }
3525
3526         if (!ret_val)
3527                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
3528
3529         if (ctrl & E1000_CTRL_PHY_RST) {
3530                 ret_val = hw->phy.ops.get_cfg_done(hw);
3531                 if (ret_val)
3532                         return ret_val;
3533
3534                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3535                 if (ret_val)
3536                         return ret_val;
3537         }
3538
3539         /* For PCH, this write will make sure that any noise
3540          * will be detected as a CRC error and be dropped rather than show up
3541          * as a bad packet to the DMA engine.
3542          */
3543         if (hw->mac.type == e1000_pchlan)
3544                 ew32(CRC_OFFSET, 0x65656565);
3545
3546         ew32(IMC, 0xffffffff);
3547         er32(ICR);
3548
3549         reg = er32(KABGTXD);
3550         reg |= E1000_KABGTXD_BGSQLBIAS;
3551         ew32(KABGTXD, reg);
3552
3553         return 0;
3554 }
3555
3556 /**
3557  *  e1000_init_hw_ich8lan - Initialize the hardware
3558  *  @hw: pointer to the HW structure
3559  *
3560  *  Prepares the hardware for transmit and receive by doing the following:
3561  *   - initialize hardware bits
3562  *   - initialize LED identification
3563  *   - setup receive address registers
3564  *   - setup flow control
3565  *   - setup transmit descriptors
3566  *   - clear statistics
3567  **/
3568 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3569 {
3570         struct e1000_mac_info *mac = &hw->mac;
3571         u32 ctrl_ext, txdctl, snoop;
3572         s32 ret_val;
3573         u16 i;
3574
3575         e1000_initialize_hw_bits_ich8lan(hw);
3576
3577         /* Initialize identification LED */
3578         ret_val = mac->ops.id_led_init(hw);
3579         if (ret_val)
3580                 e_dbg("Error initializing identification LED\n");
3581                 /* This is not fatal and we should not stop init due to this */
3582
3583         /* Setup the receive address. */
3584         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3585
3586         /* Zero out the Multicast HASH table */
3587         e_dbg("Zeroing the MTA\n");
3588         for (i = 0; i < mac->mta_reg_count; i++)
3589                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3590
3591         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
3592          * the ME.  Disable wakeup by clearing the host wakeup bit.
3593          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3594          */
3595         if (hw->phy.type == e1000_phy_82578) {
3596                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3597                 i &= ~BM_WUC_HOST_WU_BIT;
3598                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
3599                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3600                 if (ret_val)
3601                         return ret_val;
3602         }
3603
3604         /* Setup link and flow control */
3605         ret_val = mac->ops.setup_link(hw);
3606
3607         /* Set the transmit descriptor write-back policy for both queues */
3608         txdctl = er32(TXDCTL(0));
3609         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3610                  E1000_TXDCTL_FULL_TX_DESC_WB;
3611         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3612                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3613         ew32(TXDCTL(0), txdctl);
3614         txdctl = er32(TXDCTL(1));
3615         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3616                  E1000_TXDCTL_FULL_TX_DESC_WB;
3617         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3618                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3619         ew32(TXDCTL(1), txdctl);
3620
3621         /* ICH8 has opposite polarity of no_snoop bits.
3622          * By default, we should use snoop behavior.
3623          */
3624         if (mac->type == e1000_ich8lan)
3625                 snoop = PCIE_ICH8_SNOOP_ALL;
3626         else
3627                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3628         e1000e_set_pcie_no_snoop(hw, snoop);
3629
3630         ctrl_ext = er32(CTRL_EXT);
3631         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3632         ew32(CTRL_EXT, ctrl_ext);
3633
3634         /* Clear all of the statistics registers (clear on read).  It is
3635          * important that we do this after we have tried to establish link
3636          * because the symbol error count will increment wildly if there
3637          * is no link.
3638          */
3639         e1000_clear_hw_cntrs_ich8lan(hw);
3640
3641         return ret_val;
3642 }
3643 /**
3644  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3645  *  @hw: pointer to the HW structure
3646  *
3647  *  Sets/Clears required hardware bits necessary for correctly setting up the
3648  *  hardware for transmit and receive.
3649  **/
3650 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3651 {
3652         u32 reg;
3653
3654         /* Extended Device Control */
3655         reg = er32(CTRL_EXT);
3656         reg |= (1 << 22);
3657         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3658         if (hw->mac.type >= e1000_pchlan)
3659                 reg |= E1000_CTRL_EXT_PHYPDEN;
3660         ew32(CTRL_EXT, reg);
3661
3662         /* Transmit Descriptor Control 0 */
3663         reg = er32(TXDCTL(0));
3664         reg |= (1 << 22);
3665         ew32(TXDCTL(0), reg);
3666
3667         /* Transmit Descriptor Control 1 */
3668         reg = er32(TXDCTL(1));
3669         reg |= (1 << 22);
3670         ew32(TXDCTL(1), reg);
3671
3672         /* Transmit Arbitration Control 0 */
3673         reg = er32(TARC(0));
3674         if (hw->mac.type == e1000_ich8lan)
3675                 reg |= (1 << 28) | (1 << 29);
3676         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3677         ew32(TARC(0), reg);
3678
3679         /* Transmit Arbitration Control 1 */
3680         reg = er32(TARC(1));
3681         if (er32(TCTL) & E1000_TCTL_MULR)
3682                 reg &= ~(1 << 28);
3683         else
3684                 reg |= (1 << 28);
3685         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3686         ew32(TARC(1), reg);
3687
3688         /* Device Status */
3689         if (hw->mac.type == e1000_ich8lan) {
3690                 reg = er32(STATUS);
3691                 reg &= ~(1 << 31);
3692                 ew32(STATUS, reg);
3693         }
3694
3695         /* work-around descriptor data corruption issue during nfs v2 udp
3696          * traffic, just disable the nfs filtering capability
3697          */
3698         reg = er32(RFCTL);
3699         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3700
3701         /* Disable IPv6 extension header parsing because some malformed
3702          * IPv6 headers can hang the Rx.
3703          */
3704         if (hw->mac.type == e1000_ich8lan)
3705                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
3706         ew32(RFCTL, reg);
3707
3708         /* Enable ECC on Lynxpoint */
3709         if (hw->mac.type == e1000_pch_lpt) {
3710                 reg = er32(PBECCSTS);
3711                 reg |= E1000_PBECCSTS_ECC_ENABLE;
3712                 ew32(PBECCSTS, reg);
3713
3714                 reg = er32(CTRL);
3715                 reg |= E1000_CTRL_MEHE;
3716                 ew32(CTRL, reg);
3717         }
3718 }
3719
3720 /**
3721  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3722  *  @hw: pointer to the HW structure
3723  *
3724  *  Determines which flow control settings to use, then configures flow
3725  *  control.  Calls the appropriate media-specific link configuration
3726  *  function.  Assuming the adapter has a valid link partner, a valid link
3727  *  should be established.  Assumes the hardware has previously been reset
3728  *  and the transmitter and receiver are not enabled.
3729  **/
3730 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3731 {
3732         s32 ret_val;
3733
3734         if (hw->phy.ops.check_reset_block(hw))
3735                 return 0;
3736
3737         /* ICH parts do not have a word in the NVM to determine
3738          * the default flow control setting, so we explicitly
3739          * set it to full.
3740          */
3741         if (hw->fc.requested_mode == e1000_fc_default) {
3742                 /* Workaround h/w hang when Tx flow control enabled */
3743                 if (hw->mac.type == e1000_pchlan)
3744                         hw->fc.requested_mode = e1000_fc_rx_pause;
3745                 else
3746                         hw->fc.requested_mode = e1000_fc_full;
3747         }
3748
3749         /* Save off the requested flow control mode for use later.  Depending
3750          * on the link partner's capabilities, we may or may not use this mode.
3751          */
3752         hw->fc.current_mode = hw->fc.requested_mode;
3753
3754         e_dbg("After fix-ups FlowControl is now = %x\n",
3755                 hw->fc.current_mode);
3756
3757         /* Continue to configure the copper link. */
3758         ret_val = hw->mac.ops.setup_physical_interface(hw);
3759         if (ret_val)
3760                 return ret_val;
3761
3762         ew32(FCTTV, hw->fc.pause_time);
3763         if ((hw->phy.type == e1000_phy_82578) ||
3764             (hw->phy.type == e1000_phy_82579) ||
3765             (hw->phy.type == e1000_phy_i217) ||
3766             (hw->phy.type == e1000_phy_82577)) {
3767                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3768
3769                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3770                                    hw->fc.pause_time);
3771                 if (ret_val)
3772                         return ret_val;
3773         }
3774
3775         return e1000e_set_fc_watermarks(hw);
3776 }
3777
3778 /**
3779  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3780  *  @hw: pointer to the HW structure
3781  *
3782  *  Configures the kumeran interface to the PHY to wait the appropriate time
3783  *  when polling the PHY, then call the generic setup_copper_link to finish
3784  *  configuring the copper link.
3785  **/
3786 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3787 {
3788         u32 ctrl;
3789         s32 ret_val;
3790         u16 reg_data;
3791
3792         ctrl = er32(CTRL);
3793         ctrl |= E1000_CTRL_SLU;
3794         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3795         ew32(CTRL, ctrl);
3796
3797         /* Set the mac to wait the maximum time between each iteration
3798          * and increase the max iterations when polling the phy;
3799          * this fixes erroneous timeouts at 10Mbps.
3800          */
3801         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3802         if (ret_val)
3803                 return ret_val;
3804         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3805                                        &reg_data);
3806         if (ret_val)
3807                 return ret_val;
3808         reg_data |= 0x3F;
3809         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3810                                         reg_data);
3811         if (ret_val)
3812                 return ret_val;
3813
3814         switch (hw->phy.type) {
3815         case e1000_phy_igp_3:
3816                 ret_val = e1000e_copper_link_setup_igp(hw);
3817                 if (ret_val)
3818                         return ret_val;
3819                 break;
3820         case e1000_phy_bm:
3821         case e1000_phy_82578:
3822                 ret_val = e1000e_copper_link_setup_m88(hw);
3823                 if (ret_val)
3824                         return ret_val;
3825                 break;
3826         case e1000_phy_82577:
3827         case e1000_phy_82579:
3828         case e1000_phy_i217:
3829                 ret_val = e1000_copper_link_setup_82577(hw);
3830                 if (ret_val)
3831                         return ret_val;
3832                 break;
3833         case e1000_phy_ife:
3834                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3835                 if (ret_val)
3836                         return ret_val;
3837
3838                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3839
3840                 switch (hw->phy.mdix) {
3841                 case 1:
3842                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3843                         break;
3844                 case 2:
3845                         reg_data |= IFE_PMC_FORCE_MDIX;
3846                         break;
3847                 case 0:
3848                 default:
3849                         reg_data |= IFE_PMC_AUTO_MDIX;
3850                         break;
3851                 }
3852                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3853                 if (ret_val)
3854                         return ret_val;
3855                 break;
3856         default:
3857                 break;
3858         }
3859
3860         return e1000e_setup_copper_link(hw);
3861 }
3862
3863 /**
3864  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3865  *  @hw: pointer to the HW structure
3866  *  @speed: pointer to store current link speed
3867  *  @duplex: pointer to store the current link duplex
3868  *
3869  *  Calls the generic get_speed_and_duplex to retrieve the current link
3870  *  information and then calls the Kumeran lock loss workaround for links at
3871  *  gigabit speeds.
3872  **/
3873 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3874                                           u16 *duplex)
3875 {
3876         s32 ret_val;
3877
3878         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3879         if (ret_val)
3880                 return ret_val;
3881
3882         if ((hw->mac.type == e1000_ich8lan) &&
3883             (hw->phy.type == e1000_phy_igp_3) &&
3884             (*speed == SPEED_1000)) {
3885                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3886         }
3887
3888         return ret_val;
3889 }
3890
3891 /**
3892  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3893  *  @hw: pointer to the HW structure
3894  *
3895  *  Work-around for 82566 Kumeran PCS lock loss:
3896  *  On link status change (i.e. PCI reset, speed change) and link is up and
3897  *  speed is gigabit-
3898  *    0) if workaround is optionally disabled do nothing
3899  *    1) wait 1ms for Kumeran link to come up
3900  *    2) check Kumeran Diagnostic register PCS lock loss bit
3901  *    3) if not set the link is locked (all is good), otherwise...
3902  *    4) reset the PHY
3903  *    5) repeat up to 10 times
3904  *  Note: this is only called for IGP3 copper when speed is 1gb.
3905  **/
3906 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3907 {
3908         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3909         u32 phy_ctrl;
3910         s32 ret_val;
3911         u16 i, data;
3912         bool link;
3913
3914         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3915                 return 0;
3916
3917         /* Make sure link is up before proceeding.  If not just return.
3918          * Attempting this while link is negotiating fouled up link
3919          * stability
3920          */
3921         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3922         if (!link)
3923                 return 0;
3924
3925         for (i = 0; i < 10; i++) {
3926                 /* read once to clear */
3927                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3928                 if (ret_val)
3929                         return ret_val;
3930                 /* and again to get new status */
3931                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3932                 if (ret_val)
3933                         return ret_val;
3934
3935                 /* check for PCS lock */
3936                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3937                         return 0;
3938
3939                 /* Issue PHY reset */
3940                 e1000_phy_hw_reset(hw);
3941                 mdelay(5);
3942         }
3943         /* Disable GigE link negotiation */
3944         phy_ctrl = er32(PHY_CTRL);
3945         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3946                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3947         ew32(PHY_CTRL, phy_ctrl);
3948
3949         /* Call gig speed drop workaround on Gig disable before accessing
3950          * any PHY registers
3951          */
3952         e1000e_gig_downshift_workaround_ich8lan(hw);
3953
3954         /* unable to acquire PCS lock */
3955         return -E1000_ERR_PHY;
3956 }
3957
3958 /**
3959  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3960  *  @hw: pointer to the HW structure
3961  *  @state: boolean value used to set the current Kumeran workaround state
3962  *
3963  *  If ICH8, set the current Kumeran workaround state (enabled - true
3964  *  /disabled - false).
3965  **/
3966 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3967                                                  bool state)
3968 {
3969         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3970
3971         if (hw->mac.type != e1000_ich8lan) {
3972                 e_dbg("Workaround applies to ICH8 only.\n");
3973                 return;
3974         }
3975
3976         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3977 }
3978
3979 /**
3980  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3981  *  @hw: pointer to the HW structure
3982  *
3983  *  Workaround for 82566 power-down on D3 entry:
3984  *    1) disable gigabit link
3985  *    2) write VR power-down enable
3986  *    3) read it back
3987  *  Continue if successful, else issue LCD reset and repeat
3988  **/
3989 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3990 {
3991         u32 reg;
3992         u16 data;
3993         u8  retry = 0;
3994
3995         if (hw->phy.type != e1000_phy_igp_3)
3996                 return;
3997
3998         /* Try the workaround twice (if needed) */
3999         do {
4000                 /* Disable link */
4001                 reg = er32(PHY_CTRL);
4002                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4003                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4004                 ew32(PHY_CTRL, reg);
4005
4006                 /* Call gig speed drop workaround on Gig disable before
4007                  * accessing any PHY registers
4008                  */
4009                 if (hw->mac.type == e1000_ich8lan)
4010                         e1000e_gig_downshift_workaround_ich8lan(hw);
4011
4012                 /* Write VR power-down enable */
4013                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4014                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4015                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4016
4017                 /* Read it back and test */
4018                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4019                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4020                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4021                         break;
4022
4023                 /* Issue PHY reset and repeat at most one more time */
4024                 reg = er32(CTRL);
4025                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
4026                 retry++;
4027         } while (retry);
4028 }
4029
4030 /**
4031  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4032  *  @hw: pointer to the HW structure
4033  *
4034  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4035  *  LPLU, Gig disable, MDIC PHY reset):
4036  *    1) Set Kumeran Near-end loopback
4037  *    2) Clear Kumeran Near-end loopback
4038  *  Should only be called for ICH8[m] devices with any 1G Phy.
4039  **/
4040 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4041 {
4042         s32 ret_val;
4043         u16 reg_data;
4044
4045         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
4046                 return;
4047
4048         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4049                                       &reg_data);
4050         if (ret_val)
4051                 return;
4052         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4053         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4054                                        reg_data);
4055         if (ret_val)
4056                 return;
4057         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4058         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4059                                        reg_data);
4060 }
4061
4062 /**
4063  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4064  *  @hw: pointer to the HW structure
4065  *
4066  *  During S0 to Sx transition, it is possible the link remains at gig
4067  *  instead of negotiating to a lower speed.  Before going to Sx, set
4068  *  'Gig Disable' to force link speed negotiation to a lower speed based on
4069  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
4070  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4071  *  needs to be written.
4072  *  Parts that support (and are linked to a partner which support) EEE in
4073  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4074  *  than 10Mbps w/o EEE.
4075  **/
4076 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4077 {
4078         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4079         u32 phy_ctrl;
4080         s32 ret_val;
4081
4082         phy_ctrl = er32(PHY_CTRL);
4083         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4084         if (hw->phy.type == e1000_phy_i217) {
4085                 u16 phy_reg;
4086
4087                 ret_val = hw->phy.ops.acquire(hw);
4088                 if (ret_val)
4089                         goto out;
4090
4091                 if (!dev_spec->eee_disable) {
4092                         u16 eee_advert;
4093
4094                         ret_val =
4095                             e1000_read_emi_reg_locked(hw,
4096                                                       I217_EEE_ADVERTISEMENT,
4097                                                       &eee_advert);
4098                         if (ret_val)
4099                                 goto release;
4100
4101                         /* Disable LPLU if both link partners support 100BaseT
4102                          * EEE and 100Full is advertised on both ends of the
4103                          * link.
4104                          */
4105                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4106                             (dev_spec->eee_lp_ability &
4107                              I82579_EEE_100_SUPPORTED) &&
4108                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
4109                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4110                                               E1000_PHY_CTRL_NOND0A_LPLU);
4111                 }
4112
4113                 /* For i217 Intel Rapid Start Technology support,
4114                  * when the system is going into Sx and no manageability engine
4115                  * is present, the driver must configure proxy to reset only on
4116                  * power good.  LPI (Low Power Idle) state must also reset only
4117                  * on power good, as well as the MTA (Multicast table array).
4118                  * The SMBus release must also be disabled on LCD reset.
4119                  */
4120                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4121
4122                         /* Enable proxy to reset only on power good. */
4123                         e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
4124                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4125                         e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
4126
4127                         /* Set bit enable LPI (EEE) to reset only on
4128                          * power good.
4129                          */
4130                         e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
4131                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4132                         e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
4133
4134                         /* Disable the SMB release on LCD reset. */
4135                         e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4136                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4137                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4138                 }
4139
4140                 /* Enable MTA to reset for Intel Rapid Start Technology
4141                  * Support
4142                  */
4143                 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4144                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4145                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4146
4147 release:
4148                 hw->phy.ops.release(hw);
4149         }
4150 out:
4151         ew32(PHY_CTRL, phy_ctrl);
4152
4153         if (hw->mac.type == e1000_ich8lan)
4154                 e1000e_gig_downshift_workaround_ich8lan(hw);
4155
4156         if (hw->mac.type >= e1000_pchlan) {
4157                 e1000_oem_bits_config_ich8lan(hw, false);
4158
4159                 /* Reset PHY to activate OEM bits on 82577/8 */
4160                 if (hw->mac.type == e1000_pchlan)
4161                         e1000e_phy_hw_reset_generic(hw);
4162
4163                 ret_val = hw->phy.ops.acquire(hw);
4164                 if (ret_val)
4165                         return;
4166                 e1000_write_smbus_addr(hw);
4167                 hw->phy.ops.release(hw);
4168         }
4169 }
4170
4171 /**
4172  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4173  *  @hw: pointer to the HW structure
4174  *
4175  *  During Sx to S0 transitions on non-managed devices or managed devices
4176  *  on which PHY resets are not blocked, if the PHY registers cannot be
4177  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
4178  *  the PHY.
4179  *  On i217, setup Intel Rapid Start Technology.
4180  **/
4181 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4182 {
4183         s32 ret_val;
4184
4185         if (hw->mac.type < e1000_pch2lan)
4186                 return;
4187
4188         ret_val = e1000_init_phy_workarounds_pchlan(hw);
4189         if (ret_val) {
4190                 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
4191                 return;
4192         }
4193
4194         /* For i217 Intel Rapid Start Technology support when the system
4195          * is transitioning from Sx and no manageability engine is present
4196          * configure SMBus to restore on reset, disable proxy, and enable
4197          * the reset on MTA (Multicast table array).
4198          */
4199         if (hw->phy.type == e1000_phy_i217) {
4200                 u16 phy_reg;
4201
4202                 ret_val = hw->phy.ops.acquire(hw);
4203                 if (ret_val) {
4204                         e_dbg("Failed to setup iRST\n");
4205                         return;
4206                 }
4207
4208                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4209                         /* Restore clear on SMB if no manageability engine
4210                          * is present
4211                          */
4212                         ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4213                         if (ret_val)
4214                                 goto release;
4215                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
4216                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4217
4218                         /* Disable Proxy */
4219                         e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
4220                 }
4221                 /* Enable reset on MTA */
4222                 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4223                 if (ret_val)
4224                         goto release;
4225                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
4226                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4227 release:
4228                 if (ret_val)
4229                         e_dbg("Error %d in resume workarounds\n", ret_val);
4230                 hw->phy.ops.release(hw);
4231         }
4232 }
4233
4234 /**
4235  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
4236  *  @hw: pointer to the HW structure
4237  *
4238  *  Return the LED back to the default configuration.
4239  **/
4240 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4241 {
4242         if (hw->phy.type == e1000_phy_ife)
4243                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
4244
4245         ew32(LEDCTL, hw->mac.ledctl_default);
4246         return 0;
4247 }
4248
4249 /**
4250  *  e1000_led_on_ich8lan - Turn LEDs on
4251  *  @hw: pointer to the HW structure
4252  *
4253  *  Turn on the LEDs.
4254  **/
4255 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
4256 {
4257         if (hw->phy.type == e1000_phy_ife)
4258                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4259                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
4260
4261         ew32(LEDCTL, hw->mac.ledctl_mode2);
4262         return 0;
4263 }
4264
4265 /**
4266  *  e1000_led_off_ich8lan - Turn LEDs off
4267  *  @hw: pointer to the HW structure
4268  *
4269  *  Turn off the LEDs.
4270  **/
4271 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
4272 {
4273         if (hw->phy.type == e1000_phy_ife)
4274                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4275                                 (IFE_PSCL_PROBE_MODE |
4276                                  IFE_PSCL_PROBE_LEDS_OFF));
4277
4278         ew32(LEDCTL, hw->mac.ledctl_mode1);
4279         return 0;
4280 }
4281
4282 /**
4283  *  e1000_setup_led_pchlan - Configures SW controllable LED
4284  *  @hw: pointer to the HW structure
4285  *
4286  *  This prepares the SW controllable LED for use.
4287  **/
4288 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
4289 {
4290         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
4291 }
4292
4293 /**
4294  *  e1000_cleanup_led_pchlan - Restore the default LED operation
4295  *  @hw: pointer to the HW structure
4296  *
4297  *  Return the LED back to the default configuration.
4298  **/
4299 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4300 {
4301         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
4302 }
4303
4304 /**
4305  *  e1000_led_on_pchlan - Turn LEDs on
4306  *  @hw: pointer to the HW structure
4307  *
4308  *  Turn on the LEDs.
4309  **/
4310 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
4311 {
4312         u16 data = (u16)hw->mac.ledctl_mode2;
4313         u32 i, led;
4314
4315         /* If no link, then turn LED on by setting the invert bit
4316          * for each LED that's mode is "link_up" in ledctl_mode2.
4317          */
4318         if (!(er32(STATUS) & E1000_STATUS_LU)) {
4319                 for (i = 0; i < 3; i++) {
4320                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4321                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4322                             E1000_LEDCTL_MODE_LINK_UP)
4323                                 continue;
4324                         if (led & E1000_PHY_LED0_IVRT)
4325                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4326                         else
4327                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4328                 }
4329         }
4330
4331         return e1e_wphy(hw, HV_LED_CONFIG, data);
4332 }
4333
4334 /**
4335  *  e1000_led_off_pchlan - Turn LEDs off
4336  *  @hw: pointer to the HW structure
4337  *
4338  *  Turn off the LEDs.
4339  **/
4340 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
4341 {
4342         u16 data = (u16)hw->mac.ledctl_mode1;
4343         u32 i, led;
4344
4345         /* If no link, then turn LED off by clearing the invert bit
4346          * for each LED that's mode is "link_up" in ledctl_mode1.
4347          */
4348         if (!(er32(STATUS) & E1000_STATUS_LU)) {
4349                 for (i = 0; i < 3; i++) {
4350                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4351                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
4352                             E1000_LEDCTL_MODE_LINK_UP)
4353                                 continue;
4354                         if (led & E1000_PHY_LED0_IVRT)
4355                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4356                         else
4357                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4358                 }
4359         }
4360
4361         return e1e_wphy(hw, HV_LED_CONFIG, data);
4362 }
4363
4364 /**
4365  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
4366  *  @hw: pointer to the HW structure
4367  *
4368  *  Read appropriate register for the config done bit for completion status
4369  *  and configure the PHY through s/w for EEPROM-less parts.
4370  *
4371  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
4372  *  config done bit, so only an error is logged and continues.  If we were
4373  *  to return with error, EEPROM-less silicon would not be able to be reset
4374  *  or change link.
4375  **/
4376 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4377 {
4378         s32 ret_val = 0;
4379         u32 bank = 0;
4380         u32 status;
4381
4382         e1000e_get_cfg_done(hw);
4383
4384         /* Wait for indication from h/w that it has completed basic config */
4385         if (hw->mac.type >= e1000_ich10lan) {
4386                 e1000_lan_init_done_ich8lan(hw);
4387         } else {
4388                 ret_val = e1000e_get_auto_rd_done(hw);
4389                 if (ret_val) {
4390                         /* When auto config read does not complete, do not
4391                          * return with an error. This can happen in situations
4392                          * where there is no eeprom and prevents getting link.
4393                          */
4394                         e_dbg("Auto Read Done did not complete\n");
4395                         ret_val = 0;
4396                 }
4397         }
4398
4399         /* Clear PHY Reset Asserted bit */
4400         status = er32(STATUS);
4401         if (status & E1000_STATUS_PHYRA)
4402                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
4403         else
4404                 e_dbg("PHY Reset Asserted not set - needs delay\n");
4405
4406         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
4407         if (hw->mac.type <= e1000_ich9lan) {
4408                 if (!(er32(EECD) & E1000_EECD_PRES) &&
4409                     (hw->phy.type == e1000_phy_igp_3)) {
4410                         e1000e_phy_init_script_igp3(hw);
4411                 }
4412         } else {
4413                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
4414                         /* Maybe we should do a basic PHY config */
4415                         e_dbg("EEPROM not present\n");
4416                         ret_val = -E1000_ERR_CONFIG;
4417                 }
4418         }
4419
4420         return ret_val;
4421 }
4422
4423 /**
4424  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4425  * @hw: pointer to the HW structure
4426  *
4427  * In the case of a PHY power down to save power, or to turn off link during a
4428  * driver unload, or wake on lan is not enabled, remove the link.
4429  **/
4430 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
4431 {
4432         /* If the management interface is not enabled, then power down */
4433         if (!(hw->mac.ops.check_mng_mode(hw) ||
4434               hw->phy.ops.check_reset_block(hw)))
4435                 e1000_power_down_phy_copper(hw);
4436 }
4437
4438 /**
4439  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4440  *  @hw: pointer to the HW structure
4441  *
4442  *  Clears hardware counters specific to the silicon family and calls
4443  *  clear_hw_cntrs_generic to clear all general purpose counters.
4444  **/
4445 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4446 {
4447         u16 phy_data;
4448         s32 ret_val;
4449
4450         e1000e_clear_hw_cntrs_base(hw);
4451
4452         er32(ALGNERRC);
4453         er32(RXERRC);
4454         er32(TNCRS);
4455         er32(CEXTERR);
4456         er32(TSCTC);
4457         er32(TSCTFC);
4458
4459         er32(MGTPRC);
4460         er32(MGTPDC);
4461         er32(MGTPTC);
4462
4463         er32(IAC);
4464         er32(ICRXOC);
4465
4466         /* Clear PHY statistics registers */
4467         if ((hw->phy.type == e1000_phy_82578) ||
4468             (hw->phy.type == e1000_phy_82579) ||
4469             (hw->phy.type == e1000_phy_i217) ||
4470             (hw->phy.type == e1000_phy_82577)) {
4471                 ret_val = hw->phy.ops.acquire(hw);
4472                 if (ret_val)
4473                         return;
4474                 ret_val = hw->phy.ops.set_page(hw,
4475                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
4476                 if (ret_val)
4477                         goto release;
4478                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4479                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4480                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4481                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4482                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4483                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4484                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4485                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4486                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4487                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4488                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4489                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4490                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4491                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4492 release:
4493                 hw->phy.ops.release(hw);
4494         }
4495 }
4496
4497 static const struct e1000_mac_operations ich8_mac_ops = {
4498         /* check_mng_mode dependent on mac type */
4499         .check_for_link         = e1000_check_for_copper_link_ich8lan,
4500         /* cleanup_led dependent on mac type */
4501         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
4502         .get_bus_info           = e1000_get_bus_info_ich8lan,
4503         .set_lan_id             = e1000_set_lan_id_single_port,
4504         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
4505         /* led_on dependent on mac type */
4506         /* led_off dependent on mac type */
4507         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
4508         .reset_hw               = e1000_reset_hw_ich8lan,
4509         .init_hw                = e1000_init_hw_ich8lan,
4510         .setup_link             = e1000_setup_link_ich8lan,
4511         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
4512         /* id_led_init dependent on mac type */
4513         .config_collision_dist  = e1000e_config_collision_dist_generic,
4514         .rar_set                = e1000e_rar_set_generic,
4515 };
4516
4517 static const struct e1000_phy_operations ich8_phy_ops = {
4518         .acquire                = e1000_acquire_swflag_ich8lan,
4519         .check_reset_block      = e1000_check_reset_block_ich8lan,
4520         .commit                 = NULL,
4521         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
4522         .get_cable_length       = e1000e_get_cable_length_igp_2,
4523         .read_reg               = e1000e_read_phy_reg_igp,
4524         .release                = e1000_release_swflag_ich8lan,
4525         .reset                  = e1000_phy_hw_reset_ich8lan,
4526         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
4527         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
4528         .write_reg              = e1000e_write_phy_reg_igp,
4529 };
4530
4531 static const struct e1000_nvm_operations ich8_nvm_ops = {
4532         .acquire                = e1000_acquire_nvm_ich8lan,
4533         .read                   = e1000_read_nvm_ich8lan,
4534         .release                = e1000_release_nvm_ich8lan,
4535         .reload                 = e1000e_reload_nvm_generic,
4536         .update                 = e1000_update_nvm_checksum_ich8lan,
4537         .valid_led_default      = e1000_valid_led_default_ich8lan,
4538         .validate               = e1000_validate_nvm_checksum_ich8lan,
4539         .write                  = e1000_write_nvm_ich8lan,
4540 };
4541
4542 const struct e1000_info e1000_ich8_info = {
4543         .mac                    = e1000_ich8lan,
4544         .flags                  = FLAG_HAS_WOL
4545                                   | FLAG_IS_ICH
4546                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4547                                   | FLAG_HAS_AMT
4548                                   | FLAG_HAS_FLASH
4549                                   | FLAG_APME_IN_WUC,
4550         .pba                    = 8,
4551         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
4552         .get_variants           = e1000_get_variants_ich8lan,
4553         .mac_ops                = &ich8_mac_ops,
4554         .phy_ops                = &ich8_phy_ops,
4555         .nvm_ops                = &ich8_nvm_ops,
4556 };
4557
4558 const struct e1000_info e1000_ich9_info = {
4559         .mac                    = e1000_ich9lan,
4560         .flags                  = FLAG_HAS_JUMBO_FRAMES
4561                                   | FLAG_IS_ICH
4562                                   | FLAG_HAS_WOL
4563                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4564                                   | FLAG_HAS_AMT
4565                                   | FLAG_HAS_FLASH
4566                                   | FLAG_APME_IN_WUC,
4567         .pba                    = 18,
4568         .max_hw_frame_size      = DEFAULT_JUMBO,
4569         .get_variants           = e1000_get_variants_ich8lan,
4570         .mac_ops                = &ich8_mac_ops,
4571         .phy_ops                = &ich8_phy_ops,
4572         .nvm_ops                = &ich8_nvm_ops,
4573 };
4574
4575 const struct e1000_info e1000_ich10_info = {
4576         .mac                    = e1000_ich10lan,
4577         .flags                  = FLAG_HAS_JUMBO_FRAMES
4578                                   | FLAG_IS_ICH
4579                                   | FLAG_HAS_WOL
4580                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4581                                   | FLAG_HAS_AMT
4582                                   | FLAG_HAS_FLASH
4583                                   | FLAG_APME_IN_WUC,
4584         .pba                    = 18,
4585         .max_hw_frame_size      = DEFAULT_JUMBO,
4586         .get_variants           = e1000_get_variants_ich8lan,
4587         .mac_ops                = &ich8_mac_ops,
4588         .phy_ops                = &ich8_phy_ops,
4589         .nvm_ops                = &ich8_nvm_ops,
4590 };
4591
4592 const struct e1000_info e1000_pch_info = {
4593         .mac                    = e1000_pchlan,
4594         .flags                  = FLAG_IS_ICH
4595                                   | FLAG_HAS_WOL
4596                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4597                                   | FLAG_HAS_AMT
4598                                   | FLAG_HAS_FLASH
4599                                   | FLAG_HAS_JUMBO_FRAMES
4600                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4601                                   | FLAG_APME_IN_WUC,
4602         .flags2                 = FLAG2_HAS_PHY_STATS,
4603         .pba                    = 26,
4604         .max_hw_frame_size      = 4096,
4605         .get_variants           = e1000_get_variants_ich8lan,
4606         .mac_ops                = &ich8_mac_ops,
4607         .phy_ops                = &ich8_phy_ops,
4608         .nvm_ops                = &ich8_nvm_ops,
4609 };
4610
4611 const struct e1000_info e1000_pch2_info = {
4612         .mac                    = e1000_pch2lan,
4613         .flags                  = FLAG_IS_ICH
4614                                   | FLAG_HAS_WOL
4615                                   | FLAG_HAS_HW_TIMESTAMP
4616                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4617                                   | FLAG_HAS_AMT
4618                                   | FLAG_HAS_FLASH
4619                                   | FLAG_HAS_JUMBO_FRAMES
4620                                   | FLAG_APME_IN_WUC,
4621         .flags2                 = FLAG2_HAS_PHY_STATS
4622                                   | FLAG2_HAS_EEE,
4623         .pba                    = 26,
4624         .max_hw_frame_size      = DEFAULT_JUMBO,
4625         .get_variants           = e1000_get_variants_ich8lan,
4626         .mac_ops                = &ich8_mac_ops,
4627         .phy_ops                = &ich8_phy_ops,
4628         .nvm_ops                = &ich8_nvm_ops,
4629 };
4630
4631 const struct e1000_info e1000_pch_lpt_info = {
4632         .mac                    = e1000_pch_lpt,
4633         .flags                  = FLAG_IS_ICH
4634                                   | FLAG_HAS_WOL
4635                                   | FLAG_HAS_HW_TIMESTAMP
4636                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4637                                   | FLAG_HAS_AMT
4638                                   | FLAG_HAS_FLASH
4639                                   | FLAG_HAS_JUMBO_FRAMES
4640                                   | FLAG_APME_IN_WUC,
4641         .flags2                 = FLAG2_HAS_PHY_STATS
4642                                   | FLAG2_HAS_EEE,
4643         .pba                    = 26,
4644         .max_hw_frame_size      = DEFAULT_JUMBO,
4645         .get_variants           = e1000_get_variants_ich8lan,
4646         .mac_ops                = &ich8_mac_ops,
4647         .phy_ops                = &ich8_phy_ops,
4648         .nvm_ops                = &ich8_nvm_ops,
4649 };