1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
32 #include <linux/types.h>
40 E1000_CTRL = 0x00000, /* Device Control - RW */
41 E1000_STATUS = 0x00008, /* Device Status - RO */
42 E1000_EECD = 0x00010, /* EEPROM/Flash Control - RW */
43 E1000_EERD = 0x00014, /* EEPROM Read - RW */
44 E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
45 E1000_FLA = 0x0001C, /* Flash Access - RW */
46 E1000_MDIC = 0x00020, /* MDI Control - RW */
47 E1000_SCTL = 0x00024, /* SerDes Control - RW */
48 E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */
49 E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */
50 E1000_FEXTNVM4 = 0x00024, /* Future Extended NVM 4 - RW */
51 E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */
52 E1000_FCT = 0x00030, /* Flow Control Type - RW */
53 E1000_VET = 0x00038, /* VLAN Ether Type - RW */
54 E1000_FEXTNVM3 = 0x0003C, /* Future Extended NVM 3 - RW */
55 E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */
56 E1000_ITR = 0x000C4, /* Interrupt Throttling Rate - RW */
57 E1000_ICS = 0x000C8, /* Interrupt Cause Set - WO */
58 E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */
59 E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */
60 E1000_EIAC_82574 = 0x000DC, /* Ext. Interrupt Auto Clear - RW */
61 E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */
62 E1000_IVAR = 0x000E4, /* Interrupt Vector Allocation - RW */
63 E1000_FEXTNVM7 = 0x000E4, /* Future Extended NVM 7 - RW */
64 E1000_EITR_82574_BASE = 0x000E8, /* Interrupt Throttling - RW */
65 #define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2))
66 E1000_LPIC = 0x000FC, /* Low Power Idle Control - RW */
67 E1000_RCTL = 0x00100, /* Rx Control - RW */
68 E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */
69 E1000_TXCW = 0x00178, /* Tx Configuration Word - RW */
70 E1000_RXCW = 0x00180, /* Rx Configuration Word - RO */
71 E1000_TCTL = 0x00400, /* Tx Control - RW */
72 E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */
73 E1000_TIPG = 0x00410, /* Tx Inter-packet gap -RW */
74 E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */
75 E1000_LEDCTL = 0x00E00, /* LED Control - RW */
76 E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */
77 E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */
78 E1000_PHY_CTRL = 0x00F10, /* PHY Control Register in CSR */
79 #define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */
80 E1000_PBA = 0x01000, /* Packet Buffer Allocation - RW */
81 E1000_PBS = 0x01008, /* Packet Buffer Size */
82 E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
83 E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */
84 E1000_FLOP = 0x0103C, /* FLASH Opcode Register */
85 E1000_PBA_ECC = 0x01100, /* PBA ECC Register */
86 E1000_ERT = 0x02008, /* Early Rx Threshold - RW */
87 E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */
88 E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */
89 E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */
92 * Note: "_n" is the queue number of the register to be written to.
95 * E1000_RDBAL(current_rx_queue)
97 E1000_RDBAL_BASE = 0x02800, /* Rx Descriptor Base Address Low - RW */
98 #define E1000_RDBAL(_n) (E1000_RDBAL_BASE + (_n << 8))
99 E1000_RDBAH_BASE = 0x02804, /* Rx Descriptor Base Address High - RW */
100 #define E1000_RDBAH(_n) (E1000_RDBAH_BASE + (_n << 8))
101 E1000_RDLEN_BASE = 0x02808, /* Rx Descriptor Length - RW */
102 #define E1000_RDLEN(_n) (E1000_RDLEN_BASE + (_n << 8))
103 E1000_RDH_BASE = 0x02810, /* Rx Descriptor Head - RW */
104 #define E1000_RDH(_n) (E1000_RDH_BASE + (_n << 8))
105 E1000_RDT_BASE = 0x02818, /* Rx Descriptor Tail - RW */
106 #define E1000_RDT(_n) (E1000_RDT_BASE + (_n << 8))
107 E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */
108 E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
109 #define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8))
110 E1000_RADV = 0x0282C, /* Rx Interrupt Absolute Delay Timer - RW */
112 E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */
113 E1000_TDBAL_BASE = 0x03800, /* Tx Descriptor Base Address Low - RW */
114 #define E1000_TDBAL(_n) (E1000_TDBAL_BASE + (_n << 8))
115 E1000_TDBAH_BASE = 0x03804, /* Tx Descriptor Base Address High - RW */
116 #define E1000_TDBAH(_n) (E1000_TDBAH_BASE + (_n << 8))
117 E1000_TDLEN_BASE = 0x03808, /* Tx Descriptor Length - RW */
118 #define E1000_TDLEN(_n) (E1000_TDLEN_BASE + (_n << 8))
119 E1000_TDH_BASE = 0x03810, /* Tx Descriptor Head - RW */
120 #define E1000_TDH(_n) (E1000_TDH_BASE + (_n << 8))
121 E1000_TDT_BASE = 0x03818, /* Tx Descriptor Tail - RW */
122 #define E1000_TDT(_n) (E1000_TDT_BASE + (_n << 8))
123 E1000_TIDV = 0x03820, /* Tx Interrupt Delay Value - RW */
124 E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
125 #define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8))
126 E1000_TADV = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */
127 E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */
128 #define E1000_TARC(_n) (E1000_TARC_BASE + (_n << 8))
129 E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */
130 E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
131 E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */
132 E1000_RXERRC = 0x0400C, /* Receive Error Count - R/clr */
133 E1000_MPC = 0x04010, /* Missed Packet Count - R/clr */
134 E1000_SCC = 0x04014, /* Single Collision Count - R/clr */
135 E1000_ECOL = 0x04018, /* Excessive Collision Count - R/clr */
136 E1000_MCC = 0x0401C, /* Multiple Collision Count - R/clr */
137 E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */
138 E1000_COLC = 0x04028, /* Collision Count - R/clr */
139 E1000_DC = 0x04030, /* Defer Count - R/clr */
140 E1000_TNCRS = 0x04034, /* Tx-No CRS - R/clr */
141 E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */
142 E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */
143 E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */
144 E1000_XONRXC = 0x04048, /* XON Rx Count - R/clr */
145 E1000_XONTXC = 0x0404C, /* XON Tx Count - R/clr */
146 E1000_XOFFRXC = 0x04050, /* XOFF Rx Count - R/clr */
147 E1000_XOFFTXC = 0x04054, /* XOFF Tx Count - R/clr */
148 E1000_FCRUC = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */
149 E1000_PRC64 = 0x0405C, /* Packets Rx (64 bytes) - R/clr */
150 E1000_PRC127 = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */
151 E1000_PRC255 = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */
152 E1000_PRC511 = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */
153 E1000_PRC1023 = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */
154 E1000_PRC1522 = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */
155 E1000_GPRC = 0x04074, /* Good Packets Rx Count - R/clr */
156 E1000_BPRC = 0x04078, /* Broadcast Packets Rx Count - R/clr */
157 E1000_MPRC = 0x0407C, /* Multicast Packets Rx Count - R/clr */
158 E1000_GPTC = 0x04080, /* Good Packets Tx Count - R/clr */
159 E1000_GORCL = 0x04088, /* Good Octets Rx Count Low - R/clr */
160 E1000_GORCH = 0x0408C, /* Good Octets Rx Count High - R/clr */
161 E1000_GOTCL = 0x04090, /* Good Octets Tx Count Low - R/clr */
162 E1000_GOTCH = 0x04094, /* Good Octets Tx Count High - R/clr */
163 E1000_RNBC = 0x040A0, /* Rx No Buffers Count - R/clr */
164 E1000_RUC = 0x040A4, /* Rx Undersize Count - R/clr */
165 E1000_RFC = 0x040A8, /* Rx Fragment Count - R/clr */
166 E1000_ROC = 0x040AC, /* Rx Oversize Count - R/clr */
167 E1000_RJC = 0x040B0, /* Rx Jabber Count - R/clr */
168 E1000_MGTPRC = 0x040B4, /* Management Packets Rx Count - R/clr */
169 E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */
170 E1000_MGTPTC = 0x040BC, /* Management Packets Tx Count - R/clr */
171 E1000_TORL = 0x040C0, /* Total Octets Rx Low - R/clr */
172 E1000_TORH = 0x040C4, /* Total Octets Rx High - R/clr */
173 E1000_TOTL = 0x040C8, /* Total Octets Tx Low - R/clr */
174 E1000_TOTH = 0x040CC, /* Total Octets Tx High - R/clr */
175 E1000_TPR = 0x040D0, /* Total Packets Rx - R/clr */
176 E1000_TPT = 0x040D4, /* Total Packets Tx - R/clr */
177 E1000_PTC64 = 0x040D8, /* Packets Tx (64 bytes) - R/clr */
178 E1000_PTC127 = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */
179 E1000_PTC255 = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */
180 E1000_PTC511 = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */
181 E1000_PTC1023 = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */
182 E1000_PTC1522 = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */
183 E1000_MPTC = 0x040F0, /* Multicast Packets Tx Count - R/clr */
184 E1000_BPTC = 0x040F4, /* Broadcast Packets Tx Count - R/clr */
185 E1000_TSCTC = 0x040F8, /* TCP Segmentation Context Tx - R/clr */
186 E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */
187 E1000_IAC = 0x04100, /* Interrupt Assertion Count */
188 E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
189 E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
190 E1000_ICTXPTC = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
191 E1000_ICTXATC = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
192 E1000_ICTXQEC = 0x04118, /* Irq Cause Tx Queue Empty Count */
193 E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
194 E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
195 E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */
196 E1000_PCS_LCTL = 0x04208, /* PCS Link Control - RW */
197 E1000_PCS_LSTAT = 0x0420C, /* PCS Link Status - RO */
198 E1000_PCS_ANADV = 0x04218, /* AN advertisement - RW */
199 E1000_PCS_LPAB = 0x0421C, /* Link Partner Ability - RW */
200 E1000_RXCSUM = 0x05000, /* Rx Checksum Control - RW */
201 E1000_RFCTL = 0x05008, /* Receive Filter Control */
202 E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */
203 E1000_RAL_BASE = 0x05400, /* Receive Address Low - RW */
204 #define E1000_RAL(_n) (E1000_RAL_BASE + ((_n) * 8))
205 #define E1000_RA (E1000_RAL(0))
206 E1000_RAH_BASE = 0x05404, /* Receive Address High - RW */
207 #define E1000_RAH(_n) (E1000_RAH_BASE + ((_n) * 8))
208 E1000_SHRAL_PCH_LPT_BASE = 0x05408,
209 #define E1000_SHRAL_PCH_LPT(_n) (E1000_SHRAL_PCH_LPT_BASE + ((_n) * 8))
210 E1000_SHRAH_PCH_LTP_BASE = 0x0540C,
211 #define E1000_SHRAH_PCH_LPT(_n) (E1000_SHRAH_PCH_LTP_BASE + ((_n) * 8))
212 E1000_SHRAL_BASE = 0x05438, /* Shared Receive Address Low - RW */
213 #define E1000_SHRAL(_n) (E1000_SHRAL_BASE + ((_n) * 8))
214 E1000_SHRAH_BASE = 0x0543C, /* Shared Receive Address High - RW */
215 #define E1000_SHRAH(_n) (E1000_SHRAH_BASE + ((_n) * 8))
216 E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */
217 E1000_WUC = 0x05800, /* Wakeup Control - RW */
218 E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */
219 E1000_WUS = 0x05810, /* Wakeup Status - RO */
220 E1000_MRQC = 0x05818, /* Multiple Receive Control - RW */
221 E1000_MANC = 0x05820, /* Management Control - RW */
222 E1000_FFLT = 0x05F00, /* Flexible Filter Length Table - RW Array */
223 E1000_HOST_IF = 0x08800, /* Host Interface */
225 E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
226 E1000_MANC2H = 0x05860, /* Management Control To Host - RW */
227 E1000_MDEF_BASE = 0x05890, /* Management Decision Filters */
228 #define E1000_MDEF(_n) (E1000_MDEF_BASE + ((_n) * 4))
229 E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
230 E1000_GCR = 0x05B00, /* PCI-Ex Control */
231 E1000_GCR2 = 0x05B64, /* PCI-Ex Control #2 */
232 E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */
233 E1000_SWSM = 0x05B50, /* SW Semaphore */
234 E1000_FWSM = 0x05B54, /* FW Semaphore */
235 E1000_SWSM2 = 0x05B58, /* Driver-only SW semaphore */
236 E1000_RETA_BASE = 0x05C00, /* Redirection Table - RW */
237 #define E1000_RETA(_n) (E1000_RETA_BASE + ((_n) * 4))
238 E1000_RSSRK_BASE = 0x05C80, /* RSS Random Key - RW */
239 #define E1000_RSSRK(_n) (E1000_RSSRK_BASE + ((_n) * 4))
240 E1000_FFLT_DBG = 0x05F04, /* Debug Register */
241 E1000_PCH_RAICC_BASE = 0x05F50, /* Receive Address Initial CRC */
242 #define E1000_PCH_RAICC(_n) (E1000_PCH_RAICC_BASE + ((_n) * 4))
243 #define E1000_CRC_OFFSET E1000_PCH_RAICC_BASE
244 E1000_HICR = 0x08F00, /* Host Interface Control */
245 E1000_SYSTIML = 0x0B600, /* System time register Low - RO */
246 E1000_SYSTIMH = 0x0B604, /* System time register High - RO */
247 E1000_TIMINCA = 0x0B608, /* Increment attributes register - RW */
248 E1000_TSYNCTXCTL = 0x0B614, /* Tx Time Sync Control register - RW */
249 E1000_TXSTMPL = 0x0B618, /* Tx timestamp value Low - RO */
250 E1000_TXSTMPH = 0x0B61C, /* Tx timestamp value High - RO */
251 E1000_TSYNCRXCTL = 0x0B620, /* Rx Time Sync Control register - RW */
252 E1000_RXSTMPL = 0x0B624, /* Rx timestamp Low - RO */
253 E1000_RXSTMPH = 0x0B628, /* Rx timestamp High - RO */
254 E1000_RXMTRL = 0x0B634, /* Timesync Rx EtherType and Msg Type - RW */
255 E1000_RXUDP = 0x0B638, /* Timesync Rx UDP Port - RW */
258 #define E1000_MAX_PHY_ADDR 4
260 /* IGP01E1000 Specific Registers */
261 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
262 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
263 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
264 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
265 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
266 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
267 #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
268 #define IGP_PAGE_SHIFT 5
269 #define PHY_REG_MASK 0x1F
271 #define BM_WUC_PAGE 800
272 #define BM_WUC_ADDRESS_OPCODE 0x11
273 #define BM_WUC_DATA_OPCODE 0x12
274 #define BM_WUC_ENABLE_PAGE 769
275 #define BM_WUC_ENABLE_REG 17
276 #define BM_WUC_ENABLE_BIT (1 << 2)
277 #define BM_WUC_HOST_WU_BIT (1 << 4)
278 #define BM_WUC_ME_WU_BIT (1 << 5)
280 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
281 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
282 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
284 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
285 #define IGP01E1000_PHY_POLARITY_MASK 0x0078
287 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000
288 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
290 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080
292 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
293 #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
294 #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
296 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
298 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
299 #define IGP01E1000_PSSR_MDIX 0x0800
300 #define IGP01E1000_PSSR_SPEED_MASK 0xC000
301 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
303 #define IGP02E1000_PHY_CHANNEL_NUM 4
304 #define IGP02E1000_PHY_AGC_A 0x11B1
305 #define IGP02E1000_PHY_AGC_B 0x12B1
306 #define IGP02E1000_PHY_AGC_C 0x14B1
307 #define IGP02E1000_PHY_AGC_D 0x18B1
309 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
310 #define IGP02E1000_AGC_LENGTH_MASK 0x7F
311 #define IGP02E1000_AGC_RANGE 15
314 #define E1000_VFTA_ENTRY_SHIFT 5
315 #define E1000_VFTA_ENTRY_MASK 0x7F
316 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
318 #define E1000_HICR_EN 0x01 /* Enable bit - RO */
319 /* Driver sets this bit when done to put command in RAM */
320 #define E1000_HICR_C 0x02
321 #define E1000_HICR_FW_RESET_ENABLE 0x40
322 #define E1000_HICR_FW_RESET 0x80
324 #define E1000_FWSM_MODE_MASK 0xE
325 #define E1000_FWSM_MODE_SHIFT 1
327 #define E1000_MNG_IAMT_MODE 0x3
328 #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
329 #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
330 #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
331 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
332 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
333 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
336 #define E1000_STM_OPCODE 0xDB00
338 #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
339 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
340 #define E1000_KMRNCTRLSTA_REN 0x00200000
341 #define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */
342 #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
343 #define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
344 #define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
345 #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */
346 #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
347 #define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
348 #define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002
349 #define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */
351 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
352 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
353 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
354 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
356 /* IFE PHY Extended Status Control */
357 #define IFE_PESC_POLARITY_REVERSED 0x0100
359 /* IFE PHY Special Control */
360 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
361 #define IFE_PSC_FORCE_POLARITY 0x0020
363 /* IFE PHY Special Control and LED Control */
364 #define IFE_PSCL_PROBE_MODE 0x0020
365 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
366 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
368 /* IFE PHY MDIX Control */
369 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
370 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
371 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
373 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF
375 #define E1000_DEV_ID_82571EB_COPPER 0x105E
376 #define E1000_DEV_ID_82571EB_FIBER 0x105F
377 #define E1000_DEV_ID_82571EB_SERDES 0x1060
378 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
379 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
380 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
381 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
382 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
383 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
384 #define E1000_DEV_ID_82572EI_COPPER 0x107D
385 #define E1000_DEV_ID_82572EI_FIBER 0x107E
386 #define E1000_DEV_ID_82572EI_SERDES 0x107F
387 #define E1000_DEV_ID_82572EI 0x10B9
388 #define E1000_DEV_ID_82573E 0x108B
389 #define E1000_DEV_ID_82573E_IAMT 0x108C
390 #define E1000_DEV_ID_82573L 0x109A
391 #define E1000_DEV_ID_82574L 0x10D3
392 #define E1000_DEV_ID_82574LA 0x10F6
393 #define E1000_DEV_ID_82583V 0x150C
395 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
396 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
397 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
398 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
400 #define E1000_DEV_ID_ICH8_82567V_3 0x1501
401 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
402 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
403 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
404 #define E1000_DEV_ID_ICH8_IFE 0x104C
405 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
406 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
407 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
408 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
409 #define E1000_DEV_ID_ICH9_BM 0x10E5
410 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
411 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
412 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
413 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
414 #define E1000_DEV_ID_ICH9_IFE 0x10C0
415 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
416 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
417 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
418 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
419 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
420 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
421 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
422 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525
423 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
424 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
425 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
426 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
427 #define E1000_DEV_ID_PCH2_LV_LM 0x1502
428 #define E1000_DEV_ID_PCH2_LV_V 0x1503
429 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
430 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
431 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
432 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
434 #define E1000_REVISION_4 4
436 #define E1000_FUNC_1 1
438 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
439 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
441 enum e1000_mac_type {
456 enum e1000_media_type {
457 e1000_media_type_unknown = 0,
458 e1000_media_type_copper = 1,
459 e1000_media_type_fiber = 2,
460 e1000_media_type_internal_serdes = 3,
461 e1000_num_media_types
464 enum e1000_nvm_type {
465 e1000_nvm_unknown = 0,
467 e1000_nvm_eeprom_spi,
472 enum e1000_nvm_override {
473 e1000_nvm_override_none = 0,
474 e1000_nvm_override_spi_small,
475 e1000_nvm_override_spi_large
478 enum e1000_phy_type {
479 e1000_phy_unknown = 0,
494 enum e1000_bus_width {
495 e1000_bus_width_unknown = 0,
496 e1000_bus_width_pcie_x1,
497 e1000_bus_width_pcie_x2,
498 e1000_bus_width_pcie_x4 = 4,
501 e1000_bus_width_reserved
504 enum e1000_1000t_rx_status {
505 e1000_1000t_rx_status_not_ok = 0,
506 e1000_1000t_rx_status_ok,
507 e1000_1000t_rx_status_undefined = 0xFF
510 enum e1000_rev_polarity{
511 e1000_rev_polarity_normal = 0,
512 e1000_rev_polarity_reversed,
513 e1000_rev_polarity_undefined = 0xFF
521 e1000_fc_default = 0xFF
525 e1000_ms_hw_default = 0,
526 e1000_ms_force_master,
527 e1000_ms_force_slave,
531 enum e1000_smart_speed {
532 e1000_smart_speed_default = 0,
533 e1000_smart_speed_on,
534 e1000_smart_speed_off
537 enum e1000_serdes_link_state {
538 e1000_serdes_link_down = 0,
539 e1000_serdes_link_autoneg_progress,
540 e1000_serdes_link_autoneg_complete,
541 e1000_serdes_link_forced_up
544 /* Receive Descriptor */
545 struct e1000_rx_desc {
546 __le64 buffer_addr; /* Address of the descriptor's data buffer */
547 __le16 length; /* Length of data DMAed into data buffer */
548 __le16 csum; /* Packet checksum */
549 u8 status; /* Descriptor status */
550 u8 errors; /* Descriptor Errors */
554 /* Receive Descriptor - Extended */
555 union e1000_rx_desc_extended {
562 __le32 mrq; /* Multiple Rx Queues */
564 __le32 rss; /* RSS Hash */
566 __le16 ip_id; /* IP id */
567 __le16 csum; /* Packet Checksum */
572 __le32 status_error; /* ext status/error */
574 __le16 vlan; /* VLAN tag */
576 } wb; /* writeback */
579 #define MAX_PS_BUFFERS 4
580 /* Receive Descriptor - Packet Split */
581 union e1000_rx_desc_packet_split {
583 /* one buffer for protocol header(s), three data buffers */
584 __le64 buffer_addr[MAX_PS_BUFFERS];
588 __le32 mrq; /* Multiple Rx Queues */
590 __le32 rss; /* RSS Hash */
592 __le16 ip_id; /* IP id */
593 __le16 csum; /* Packet Checksum */
598 __le32 status_error; /* ext status/error */
599 __le16 length0; /* length of buffer 0 */
600 __le16 vlan; /* VLAN tag */
603 __le16 header_status;
604 __le16 length[3]; /* length of buffers 1-3 */
607 } wb; /* writeback */
610 /* Transmit Descriptor */
611 struct e1000_tx_desc {
612 __le64 buffer_addr; /* Address of the descriptor's data buffer */
616 __le16 length; /* Data buffer length */
617 u8 cso; /* Checksum offset */
618 u8 cmd; /* Descriptor control */
624 u8 status; /* Descriptor status */
625 u8 css; /* Checksum start */
631 /* Offload Context Descriptor */
632 struct e1000_context_desc {
636 u8 ipcss; /* IP checksum start */
637 u8 ipcso; /* IP checksum offset */
638 __le16 ipcse; /* IP checksum end */
644 u8 tucss; /* TCP checksum start */
645 u8 tucso; /* TCP checksum offset */
646 __le16 tucse; /* TCP checksum end */
649 __le32 cmd_and_length;
653 u8 status; /* Descriptor status */
654 u8 hdr_len; /* Header length */
655 __le16 mss; /* Maximum segment size */
660 /* Offload data descriptor */
661 struct e1000_data_desc {
662 __le64 buffer_addr; /* Address of the descriptor's buffer address */
666 __le16 length; /* Data buffer length */
674 u8 status; /* Descriptor status */
675 u8 popts; /* Packet Options */
676 __le16 special; /* */
681 /* Statistics counters collected by the MAC */
682 struct e1000_hw_stats {
748 struct e1000_phy_stats {
753 struct e1000_host_mng_dhcp_cookie {
764 /* Host Interface "Rev 1" */
765 struct e1000_host_command_header {
772 #define E1000_HI_MAX_DATA_LENGTH 252
773 struct e1000_host_command_info {
774 struct e1000_host_command_header command_header;
775 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
778 /* Host Interface "Rev 2" */
779 struct e1000_host_mng_command_header {
787 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
788 struct e1000_host_mng_command_info {
789 struct e1000_host_mng_command_header command_header;
790 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
793 /* Function pointers and static data for the MAC. */
794 struct e1000_mac_operations {
795 s32 (*id_led_init)(struct e1000_hw *);
796 s32 (*blink_led)(struct e1000_hw *);
797 bool (*check_mng_mode)(struct e1000_hw *);
798 s32 (*check_for_link)(struct e1000_hw *);
799 s32 (*cleanup_led)(struct e1000_hw *);
800 void (*clear_hw_cntrs)(struct e1000_hw *);
801 void (*clear_vfta)(struct e1000_hw *);
802 s32 (*get_bus_info)(struct e1000_hw *);
803 void (*set_lan_id)(struct e1000_hw *);
804 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
805 s32 (*led_on)(struct e1000_hw *);
806 s32 (*led_off)(struct e1000_hw *);
807 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
808 s32 (*reset_hw)(struct e1000_hw *);
809 s32 (*init_hw)(struct e1000_hw *);
810 s32 (*setup_link)(struct e1000_hw *);
811 s32 (*setup_physical_interface)(struct e1000_hw *);
812 s32 (*setup_led)(struct e1000_hw *);
813 void (*write_vfta)(struct e1000_hw *, u32, u32);
814 void (*config_collision_dist)(struct e1000_hw *);
815 void (*rar_set)(struct e1000_hw *, u8 *, u32);
816 s32 (*read_mac_addr)(struct e1000_hw *);
819 /* When to use various PHY register access functions:
822 * Function Does Does When to use
823 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
824 * X_reg L,P,A n/a for simple PHY reg accesses
825 * X_reg_locked P,A L for multiple accesses of different regs
827 * X_reg_page A L,P for multiple accesses of different regs
830 * Where X=[read|write], L=locking, P=sets page, A=register access
833 struct e1000_phy_operations {
834 s32 (*acquire)(struct e1000_hw *);
835 s32 (*cfg_on_link_up)(struct e1000_hw *);
836 s32 (*check_polarity)(struct e1000_hw *);
837 s32 (*check_reset_block)(struct e1000_hw *);
838 s32 (*commit)(struct e1000_hw *);
839 s32 (*force_speed_duplex)(struct e1000_hw *);
840 s32 (*get_cfg_done)(struct e1000_hw *hw);
841 s32 (*get_cable_length)(struct e1000_hw *);
842 s32 (*get_info)(struct e1000_hw *);
843 s32 (*set_page)(struct e1000_hw *, u16);
844 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
845 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
846 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
847 void (*release)(struct e1000_hw *);
848 s32 (*reset)(struct e1000_hw *);
849 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
850 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
851 s32 (*write_reg)(struct e1000_hw *, u32, u16);
852 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
853 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
854 void (*power_up)(struct e1000_hw *);
855 void (*power_down)(struct e1000_hw *);
858 /* Function pointers for the NVM. */
859 struct e1000_nvm_operations {
860 s32 (*acquire)(struct e1000_hw *);
861 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
862 void (*release)(struct e1000_hw *);
863 void (*reload)(struct e1000_hw *);
864 s32 (*update)(struct e1000_hw *);
865 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
866 s32 (*validate)(struct e1000_hw *);
867 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
870 struct e1000_mac_info {
871 struct e1000_mac_operations ops;
873 u8 perm_addr[ETH_ALEN];
875 enum e1000_mac_type type;
892 /* Maximum size of the MTA register table in all supported adapters */
893 #define MAX_MTA_REG 128
894 u32 mta_shadow[MAX_MTA_REG];
897 u8 forced_speed_duplex;
901 bool arc_subsystem_valid;
904 bool get_link_status;
906 bool serdes_has_link;
907 bool tx_pkt_filtering;
908 enum e1000_serdes_link_state serdes_link_state;
911 struct e1000_phy_info {
912 struct e1000_phy_operations ops;
914 enum e1000_phy_type type;
916 enum e1000_1000t_rx_status local_rx;
917 enum e1000_1000t_rx_status remote_rx;
918 enum e1000_ms_type ms_type;
919 enum e1000_ms_type original_ms_type;
920 enum e1000_rev_polarity cable_polarity;
921 enum e1000_smart_speed smart_speed;
925 u32 reset_delay_us; /* in usec */
928 enum e1000_media_type media_type;
930 u16 autoneg_advertised;
933 u16 max_cable_length;
934 u16 min_cable_length;
938 bool disable_polarity_correction;
940 bool polarity_correction;
941 bool speed_downgraded;
942 bool autoneg_wait_to_complete;
945 struct e1000_nvm_info {
946 struct e1000_nvm_operations ops;
948 enum e1000_nvm_type type;
949 enum e1000_nvm_override override;
961 struct e1000_bus_info {
962 enum e1000_bus_width width;
967 struct e1000_fc_info {
968 u32 high_water; /* Flow control high-water mark */
969 u32 low_water; /* Flow control low-water mark */
970 u16 pause_time; /* Flow control pause timer */
971 u16 refresh_time; /* Flow control refresh timer */
972 bool send_xon; /* Flow control send XON */
973 bool strict_ieee; /* Strict IEEE mode */
974 enum e1000_fc_mode current_mode; /* FC mode in effect */
975 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
978 struct e1000_dev_spec_82571 {
983 struct e1000_dev_spec_80003es2lan {
987 struct e1000_shadow_ram {
992 #define E1000_ICH8_SHADOW_RAM_WORDS 2048
994 struct e1000_dev_spec_ich8lan {
995 bool kmrn_lock_loss_workaround_enabled;
996 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
1003 struct e1000_adapter *adapter;
1005 void __iomem *hw_addr;
1006 void __iomem *flash_address;
1008 struct e1000_mac_info mac;
1009 struct e1000_fc_info fc;
1010 struct e1000_phy_info phy;
1011 struct e1000_nvm_info nvm;
1012 struct e1000_bus_info bus;
1013 struct e1000_host_mng_dhcp_cookie mng_cookie;
1016 struct e1000_dev_spec_82571 e82571;
1017 struct e1000_dev_spec_80003es2lan e80003es2lan;
1018 struct e1000_dev_spec_ich8lan ich8lan;