1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 /* Linux PRO/1000 Ethernet Driver main header file */
34 #include <linux/bitops.h>
35 #include <linux/types.h>
36 #include <linux/timer.h>
37 #include <linux/workqueue.h>
39 #include <linux/netdevice.h>
40 #include <linux/pci.h>
41 #include <linux/pci-aspm.h>
42 #include <linux/crc32.h>
43 #include <linux/if_vlan.h>
44 #include <linux/clocksource.h>
45 #include <linux/net_tstamp.h>
51 #define e_dbg(format, arg...) \
52 netdev_dbg(hw->adapter->netdev, format, ## arg)
53 #define e_err(format, arg...) \
54 netdev_err(adapter->netdev, format, ## arg)
55 #define e_info(format, arg...) \
56 netdev_info(adapter->netdev, format, ## arg)
57 #define e_warn(format, arg...) \
58 netdev_warn(adapter->netdev, format, ## arg)
59 #define e_notice(format, arg...) \
60 netdev_notice(adapter->netdev, format, ## arg)
63 /* Interrupt modes, as used by the IntMode parameter */
64 #define E1000E_INT_MODE_LEGACY 0
65 #define E1000E_INT_MODE_MSI 1
66 #define E1000E_INT_MODE_MSIX 2
68 /* Tx/Rx descriptor defines */
69 #define E1000_DEFAULT_TXD 256
70 #define E1000_MAX_TXD 4096
71 #define E1000_MIN_TXD 64
73 #define E1000_DEFAULT_RXD 256
74 #define E1000_MAX_RXD 4096
75 #define E1000_MIN_RXD 64
77 #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
78 #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
80 /* Early Receive defines */
81 #define E1000_ERT_2048 0x100
83 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
85 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
86 /* How many Rx Buffers do we bundle into one write to the hardware ? */
87 #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
89 #define AUTO_ALL_MODES 0
90 #define E1000_EEPROM_APME 0x0400
92 #define E1000_MNG_VLAN_NONE (-1)
94 /* Number of packet split data buffers (not including the header buffer) */
95 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
97 #define DEFAULT_JUMBO 9234
99 /* BM/HV Specific Registers */
100 #define BM_PORT_CTRL_PAGE 769
102 #define PHY_UPPER_SHIFT 21
103 #define BM_PHY_REG(page, reg) \
104 (((reg) & MAX_PHY_REG_ADDRESS) |\
105 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
106 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
108 /* PHY Wakeup Registers and defines */
109 #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
110 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
111 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
112 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
113 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
114 #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
115 #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
116 #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
117 #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
118 #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
120 #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
121 #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
122 #define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
123 #define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
124 #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
125 #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
126 #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
128 #define HV_STATS_PAGE 778
129 #define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */
130 #define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17)
131 #define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */
132 #define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19)
133 #define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */
134 #define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21)
135 #define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */
136 #define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
137 #define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */
138 #define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26)
139 #define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
140 #define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28)
141 #define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */
142 #define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30)
144 #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
146 /* BM PHY Copper Specific Status */
147 #define BM_CS_STATUS 17
148 #define BM_CS_STATUS_LINK_UP 0x0400
149 #define BM_CS_STATUS_RESOLVED 0x0800
150 #define BM_CS_STATUS_SPEED_MASK 0xC000
151 #define BM_CS_STATUS_SPEED_1000 0x8000
153 /* 82577 Mobile Phy Status Register */
154 #define HV_M_STATUS 26
155 #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
156 #define HV_M_STATUS_SPEED_MASK 0x0300
157 #define HV_M_STATUS_SPEED_1000 0x0200
158 #define HV_M_STATUS_LINK_UP 0x0040
160 #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
161 #define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000
163 /* Time to wait before putting the device into D3 if there's no link (in ms). */
164 #define LINK_TIMEOUT 100
166 /* Count for polling __E1000_RESET condition every 10-20msec.
167 * Experimentation has shown the reset can take approximately 210msec.
169 #define E1000_CHECK_RESET_COUNT 25
171 #define DEFAULT_RDTR 0
172 #define DEFAULT_RADV 8
173 #define BURST_RDTR 0x20
174 #define BURST_RADV 0x20
176 /* in the case of WTHRESH, it appears at least the 82571/2 hardware
177 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
178 * WTHRESH=4, so a setting of 5 gives the most efficient bus
179 * utilization but to avoid possible Tx stalls, set it to 1
181 #define E1000_TXDCTL_DMA_BURST_ENABLE \
182 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
183 E1000_TXDCTL_COUNT_DESC | \
184 (1 << 16) | /* wthresh must be +1 more than desired */\
185 (1 << 8) | /* hthresh */ \
188 #define E1000_RXDCTL_DMA_BURST_ENABLE \
189 (0x01000000 | /* set descriptor granularity */ \
190 (4 << 16) | /* set writeback threshold */ \
191 (4 << 8) | /* set prefetch threshold */ \
192 0x20) /* set hthresh */
194 #define E1000_TIDV_FPD (1 << 31)
195 #define E1000_RDTR_FPD (1 << 31)
212 struct e1000_ps_page {
214 u64 dma; /* must be u64 - written to hw */
217 /* wrappers around a pointer to a socket buffer,
218 * so a DMA handle can be stored along with the buffer
220 struct e1000_buffer {
226 unsigned long time_stamp;
230 unsigned int bytecount;
235 /* arrays of page information for packet split */
236 struct e1000_ps_page *ps_pages;
243 struct e1000_adapter *adapter; /* back pointer to adapter */
244 void *desc; /* pointer to ring memory */
245 dma_addr_t dma; /* phys address of ring */
246 unsigned int size; /* length of ring in bytes */
247 unsigned int count; /* number of desc. in ring */
255 /* array of buffer information structs */
256 struct e1000_buffer *buffer_info;
258 char name[IFNAMSIZ + 5];
261 void __iomem *itr_register;
264 struct sk_buff *rx_skb_top;
267 /* PHY register snapshot values */
268 struct e1000_phy_regs {
269 u16 bmcr; /* basic mode control register */
270 u16 bmsr; /* basic mode status register */
271 u16 advertise; /* auto-negotiation advertisement */
272 u16 lpa; /* link partner ability register */
273 u16 expansion; /* auto-negotiation expansion reg */
274 u16 ctrl1000; /* 1000BASE-T control register */
275 u16 stat1000; /* 1000BASE-T status register */
276 u16 estatus; /* extended status register */
279 /* board specific private data structure */
280 struct e1000_adapter {
281 struct timer_list watchdog_timer;
282 struct timer_list phy_info_timer;
283 struct timer_list blink_timer;
285 struct work_struct reset_task;
286 struct work_struct watchdog_task;
288 const struct e1000_info *ei;
290 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
298 /* track device up/down/testing state */
301 /* Interrupt Throttle Rate */
308 struct e1000_ring *tx_ring /* One per active queue */
309 ____cacheline_aligned_in_smp;
312 struct napi_struct napi;
314 unsigned int restart_queue;
318 bool tx_hang_recheck;
319 u8 tx_timeout_factor;
322 u32 tx_abs_int_delay;
324 unsigned int total_tx_bytes;
325 unsigned int total_tx_packets;
326 unsigned int total_rx_bytes;
327 unsigned int total_rx_packets;
334 u32 tx_timeout_count;
341 bool (*clean_rx) (struct e1000_ring *ring, int *work_done,
342 int work_to_do) ____cacheline_aligned_in_smp;
343 void (*alloc_rx_buf) (struct e1000_ring *ring, int cleaned_count,
345 struct e1000_ring *rx_ring;
348 u32 rx_abs_int_delay;
356 u32 alloc_rx_buff_failed;
358 u32 rx_hwtstamp_cleared;
360 unsigned int rx_ps_pages;
365 /* OS defined structs */
366 struct net_device *netdev;
367 struct pci_dev *pdev;
369 /* structs defined in e1000_hw.h */
372 spinlock_t stats64_lock;
373 struct e1000_hw_stats stats;
374 struct e1000_phy_info phy_info;
375 struct e1000_phy_stats phy_stats;
377 /* Snapshot of PHY registers */
378 struct e1000_phy_regs phy_regs;
380 struct e1000_ring test_tx_ring;
381 struct e1000_ring test_rx_ring;
385 unsigned int num_vectors;
386 struct msix_entry *msix_entries;
393 u32 max_hw_frame_size;
399 struct work_struct downshift_task;
400 struct work_struct update_phy_task;
401 struct work_struct print_hang_task;
409 struct hwtstamp_config hwtstamp_config;
410 struct delayed_work systim_overflow_work;
411 struct sk_buff *tx_hwtstamp_skb;
412 struct work_struct tx_hwtstamp_work;
413 spinlock_t systim_lock; /* protects SYSTIML/H regsters */
414 struct cyclecounter cc;
415 struct timecounter tc;
419 enum e1000_mac_type mac;
423 u32 max_hw_frame_size;
424 s32 (*get_variants)(struct e1000_adapter *);
425 const struct e1000_mac_operations *mac_ops;
426 const struct e1000_phy_operations *phy_ops;
427 const struct e1000_nvm_operations *nvm_ops;
430 /* The system time is maintained by a 64-bit counter comprised of the 32-bit
431 * SYSTIMH and SYSTIML registers. How the counter increments (and therefore
432 * its resolution) is based on the contents of the TIMINCA register - it
433 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
434 * For the best accuracy, the incperiod should be as small as possible. The
435 * incvalue is scaled by a factor as large as possible (while still fitting
436 * in bits 23:0) so that relatively small clock corrections can be made.
438 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of
439 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)
440 * bits to count nanoseconds leaving the rest for fractional nonseconds.
442 #define INCVALUE_96MHz 125
443 #define INCVALUE_SHIFT_96MHz 17
444 #define INCPERIOD_SHIFT_96MHz 2
445 #define INCPERIOD_96MHz (12 >> INCPERIOD_SHIFT_96MHz)
447 #define INCVALUE_25MHz 40
448 #define INCVALUE_SHIFT_25MHz 18
449 #define INCPERIOD_25MHz 1
451 /* Another drawback of scaling the incvalue by a large factor is the
452 * 64-bit SYSTIM register overflows more quickly. This is dealt with
453 * by simply reading the clock before it overflows.
455 * Clock ns bits Overflows after
456 * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~
457 * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs
458 * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours
460 #define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4)
462 /* hardware capability, feature, and workaround flags */
463 #define FLAG_HAS_AMT (1 << 0)
464 #define FLAG_HAS_FLASH (1 << 1)
465 #define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
466 #define FLAG_HAS_WOL (1 << 3)
468 #define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
469 #define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
470 #define FLAG_HAS_JUMBO_FRAMES (1 << 7)
471 #define FLAG_READ_ONLY_NVM (1 << 8)
472 #define FLAG_IS_ICH (1 << 9)
473 #define FLAG_HAS_MSIX (1 << 10)
474 #define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
475 #define FLAG_IS_QUAD_PORT_A (1 << 12)
476 #define FLAG_IS_QUAD_PORT (1 << 13)
477 #define FLAG_HAS_HW_TIMESTAMP (1 << 14)
478 #define FLAG_APME_IN_WUC (1 << 15)
479 #define FLAG_APME_IN_CTRL3 (1 << 16)
480 #define FLAG_APME_CHECK_PORT_B (1 << 17)
481 #define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
482 #define FLAG_NO_WAKE_UCAST (1 << 19)
483 #define FLAG_MNG_PT_ENABLED (1 << 20)
484 #define FLAG_RESET_OVERWRITES_LAA (1 << 21)
485 #define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
486 #define FLAG_TARC_SET_BIT_ZERO (1 << 23)
487 #define FLAG_RX_NEEDS_RESTART (1 << 24)
488 #define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
489 #define FLAG_SMART_POWER_DOWN (1 << 26)
490 #define FLAG_MSI_ENABLED (1 << 27)
491 /* reserved (1 << 28) */
492 #define FLAG_TSO_FORCE (1 << 29)
493 #define FLAG_RESTART_NOW (1 << 30)
494 #define FLAG_MSI_TEST_FAILED (1 << 31)
496 #define FLAG2_CRC_STRIPPING (1 << 0)
497 #define FLAG2_HAS_PHY_WAKEUP (1 << 1)
498 #define FLAG2_IS_DISCARDING (1 << 2)
499 #define FLAG2_DISABLE_ASPM_L1 (1 << 3)
500 #define FLAG2_HAS_PHY_STATS (1 << 4)
501 #define FLAG2_HAS_EEE (1 << 5)
502 #define FLAG2_DMA_BURST (1 << 6)
503 #define FLAG2_DISABLE_ASPM_L0S (1 << 7)
504 #define FLAG2_DISABLE_AIM (1 << 8)
505 #define FLAG2_CHECK_PHY_HANG (1 << 9)
506 #define FLAG2_NO_DISABLE_RX (1 << 10)
507 #define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11)
508 #define FLAG2_DFLT_CRC_STRIPPING (1 << 12)
509 #define FLAG2_CHECK_RX_HWTSTAMP (1 << 13)
511 #define E1000_RX_DESC_PS(R, i) \
512 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
513 #define E1000_RX_DESC_EXT(R, i) \
514 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
515 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
516 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
517 #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
522 __E1000_ACCESS_SHARED_RESOURCE,
530 latency_invalid = 255
533 extern char e1000e_driver_name[];
534 extern const char e1000e_driver_version[];
536 extern void e1000e_check_options(struct e1000_adapter *adapter);
537 extern void e1000e_set_ethtool_ops(struct net_device *netdev);
539 extern int e1000e_up(struct e1000_adapter *adapter);
540 extern void e1000e_down(struct e1000_adapter *adapter);
541 extern void e1000e_reinit_locked(struct e1000_adapter *adapter);
542 extern void e1000e_reset(struct e1000_adapter *adapter);
543 extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
544 extern int e1000e_setup_rx_resources(struct e1000_ring *ring);
545 extern int e1000e_setup_tx_resources(struct e1000_ring *ring);
546 extern void e1000e_free_rx_resources(struct e1000_ring *ring);
547 extern void e1000e_free_tx_resources(struct e1000_ring *ring);
548 extern struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
549 struct rtnl_link_stats64
551 extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
552 extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
553 extern void e1000e_get_hw_control(struct e1000_adapter *adapter);
554 extern void e1000e_release_hw_control(struct e1000_adapter *adapter);
555 extern void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
557 extern unsigned int copybreak;
559 extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw);
561 extern const struct e1000_info e1000_82571_info;
562 extern const struct e1000_info e1000_82572_info;
563 extern const struct e1000_info e1000_82573_info;
564 extern const struct e1000_info e1000_82574_info;
565 extern const struct e1000_info e1000_82583_info;
566 extern const struct e1000_info e1000_ich8_info;
567 extern const struct e1000_info e1000_ich9_info;
568 extern const struct e1000_info e1000_ich10_info;
569 extern const struct e1000_info e1000_pch_info;
570 extern const struct e1000_info e1000_pch2_info;
571 extern const struct e1000_info e1000_pch_lpt_info;
572 extern const struct e1000_info e1000_es2_info;
574 extern s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
577 extern s32 e1000e_commit_phy(struct e1000_hw *hw);
579 extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
581 extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
582 extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
584 extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
585 extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
587 extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
588 extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
589 extern void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
590 extern void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
591 extern s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
592 extern s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
593 extern void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
595 extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
596 extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
597 extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
598 extern s32 e1000e_setup_led_generic(struct e1000_hw *hw);
599 extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
600 extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
601 extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
602 extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
603 extern void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
604 extern void e1000_set_lan_id_single_port(struct e1000_hw *hw);
605 extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex);
606 extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex);
607 extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
608 extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
609 extern s32 e1000e_id_led_init_generic(struct e1000_hw *hw);
610 extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
611 extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
612 extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
613 extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
614 extern s32 e1000e_setup_link_generic(struct e1000_hw *hw);
615 extern void e1000_clear_vfta_generic(struct e1000_hw *hw);
616 extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
617 extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
620 extern void e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
621 extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
622 extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
623 extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
624 extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
625 extern void e1000e_config_collision_dist_generic(struct e1000_hw *hw);
626 extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
627 extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
628 extern s32 e1000e_blink_led_generic(struct e1000_hw *hw);
629 extern void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
630 extern s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
631 extern void e1000e_reset_adaptive(struct e1000_hw *hw);
632 extern void e1000e_update_adaptive(struct e1000_hw *hw);
634 extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
635 extern s32 e1000e_get_phy_id(struct e1000_hw *hw);
636 extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
637 extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
638 extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
639 extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
640 extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
641 extern s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
642 extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
643 extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
645 extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
646 extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
647 extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
648 extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
650 extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
651 extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
652 extern s32 e1000e_get_cfg_done(struct e1000_hw *hw);
653 extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
654 extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
655 extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
656 extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
657 extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
658 extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
659 extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
660 extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
661 extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
662 extern s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
664 extern s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
666 extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
667 extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
668 extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
669 extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
670 extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
672 extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
673 extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
675 extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
676 u32 usec_interval, bool *success);
677 extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
678 extern void e1000_power_up_phy_copper(struct e1000_hw *hw);
679 extern void e1000_power_down_phy_copper(struct e1000_hw *hw);
680 extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
681 extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
682 extern s32 e1000e_check_downshift(struct e1000_hw *hw);
683 extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
684 extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
686 extern s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
688 extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
689 extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
691 extern s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
693 extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
694 extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
695 extern s32 e1000_check_polarity_82577(struct e1000_hw *hw);
696 extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
697 extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
698 extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
700 extern s32 e1000_check_polarity_m88(struct e1000_hw *hw);
701 extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
702 extern s32 e1000_check_polarity_ife(struct e1000_hw *hw);
703 extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
704 extern s32 e1000_check_polarity_igp(struct e1000_hw *hw);
705 extern bool e1000_check_phy_82574(struct e1000_hw *hw);
706 extern s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
708 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
710 return hw->phy.ops.reset(hw);
713 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
715 return hw->phy.ops.read_reg(hw, offset, data);
718 static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
720 return hw->phy.ops.read_reg_locked(hw, offset, data);
723 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
725 return hw->phy.ops.write_reg(hw, offset, data);
728 static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
730 return hw->phy.ops.write_reg_locked(hw, offset, data);
733 static inline s32 e1000_get_cable_length(struct e1000_hw *hw)
735 return hw->phy.ops.get_cable_length(hw);
738 extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
739 extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
740 extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
741 extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
742 extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
743 extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
744 extern void e1000e_release_nvm(struct e1000_hw *hw);
745 extern void e1000e_reload_nvm_generic(struct e1000_hw *hw);
746 extern s32 e1000_read_mac_addr_generic(struct e1000_hw *hw);
748 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
750 if (hw->mac.ops.read_mac_addr)
751 return hw->mac.ops.read_mac_addr(hw);
753 return e1000_read_mac_addr_generic(hw);
756 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
758 return hw->nvm.ops.validate(hw);
761 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
763 return hw->nvm.ops.update(hw);
766 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
768 return hw->nvm.ops.read(hw, offset, words, data);
771 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
773 return hw->nvm.ops.write(hw, offset, words, data);
776 static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
778 return hw->phy.ops.get_info(hw);
781 extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
782 extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
783 extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
785 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
787 return readl(hw->hw_addr + reg);
790 #define er32(reg) __er32(hw, E1000_##reg)
793 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
794 * @hw: pointer to the HW structure
796 * When updating the MAC CSR registers, the Manageability Engine (ME) could
797 * be accessing the registers at the same time. Normally, this is handled in
798 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
799 * accesses later than it should which could result in the register to have
800 * an incorrect value. Workaround this by checking the FWSM register which
801 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
802 * and try again a number of times.
804 static inline s32 __ew32_prepare(struct e1000_hw *hw)
806 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
808 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
814 static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
816 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
819 writel(val, hw->hw_addr + reg);
822 #define ew32(reg, val) __ew32(hw, E1000_##reg, (val))
824 #define e1e_flush() er32(STATUS)
826 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
827 (__ew32((a), (reg + ((offset) << 2)), (value)))
829 #define E1000_READ_REG_ARRAY(a, reg, offset) \
830 (readl((a)->hw_addr + reg + ((offset) << 2)))
832 #endif /* _E1000_H_ */