drivers/net/ethernet/intel/e1000e/82571.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /* 82571EB Gigabit Ethernet Controller
  30  * 82571EB Gigabit Ethernet Controller (Copper)
  31  * 82571EB Gigabit Ethernet Controller (Fiber)
  32  * 82571EB Dual Port Gigabit Mezzanine Adapter
  33  * 82571EB Quad Port Gigabit Mezzanine Adapter
  34  * 82571PT Gigabit PT Quad Port Server ExpressModule
  35  * 82572EI Gigabit Ethernet Controller (Copper)
  36  * 82572EI Gigabit Ethernet Controller (Fiber)
  37  * 82572EI Gigabit Ethernet Controller
  38  * 82573V Gigabit Ethernet Controller (Copper)
  39  * 82573E Gigabit Ethernet Controller (Copper)
  40  * 82573L Gigabit Ethernet Controller
  41  * 82574L Gigabit Network Connection
  42  * 82583V Gigabit Network Connection
  43  */
  44
  45 #include "e1000.h"
  46
  47 #define ID_LED_RESERVED_F746 0xF746
  48 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
  49                               (ID_LED_OFF1_ON2  <<  8) | \
  50                               (ID_LED_DEF1_DEF2 <<  4) | \
  51                               (ID_LED_DEF1_DEF2))
  52
  53 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
  54 #define AN_RETRY_COUNT          5 /* Autoneg Retry Count value */
  55 #define E1000_BASE1000T_STATUS          10
  56 #define E1000_IDLE_ERROR_COUNT_MASK     0xFF
  57 #define E1000_RECEIVE_ERROR_COUNTER     21
  58 #define E1000_RECEIVE_ERROR_MAX         0xFFFF
  59
  60 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
  61
  62 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
  63 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
  64 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  65 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  66 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  67                                       u16 words, u16 *data);
  68 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  69 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  70 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
  71 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  72 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
  73 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  74 static s32 e1000_led_on_82574(struct e1000_hw *hw);
  75 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  76 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  77 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
  78 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
  79 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
  80 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);
  81 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);
  82
  83 /**
  84  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  85  *  @hw: pointer to the HW structure
  86  **/
  87 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  88 {
  89         struct e1000_phy_info *phy = &hw->phy;
  90         s32 ret_val;
  91
  92         if (hw->phy.media_type != e1000_media_type_copper) {
  93                 phy->type = e1000_phy_none;
  94                 return 0;
  95         }
  96
  97         phy->addr                        = 1;
  98         phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  99         phy->reset_delay_us              = 100;
 100
 101         phy->ops.power_up                = e1000_power_up_phy_copper;
 102         phy->ops.power_down              = e1000_power_down_phy_copper_82571;
 103
 104         switch (hw->mac.type) {
 105         case e1000_82571:
 106         case e1000_82572:
 107                 phy->type                = e1000_phy_igp_2;
 108                 break;
 109         case e1000_82573:
 110                 phy->type                = e1000_phy_m88;
 111                 break;
 112         case e1000_82574:
 113         case e1000_82583:
 114                 phy->type                = e1000_phy_bm;
 115                 phy->ops.acquire = e1000_get_hw_semaphore_82574;
 116                 phy->ops.release = e1000_put_hw_semaphore_82574;
 117                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
 118                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
 119                 break;
 120         default:
 121                 return -E1000_ERR_PHY;
 122                 break;
 123         }
 124
 125         /* This can only be done after all function pointers are setup. */
 126         ret_val = e1000_get_phy_id_82571(hw);
 127         if (ret_val) {
 128                 e_dbg("Error getting PHY ID\n");
 129                 return ret_val;
 130         }
 131
 132         /* Verify phy id */
 133         switch (hw->mac.type) {
 134         case e1000_82571:
 135         case e1000_82572:
 136                 if (phy->id != IGP01E1000_I_PHY_ID)
 137                         ret_val = -E1000_ERR_PHY;
 138                 break;
 139         case e1000_82573:
 140                 if (phy->id != M88E1111_I_PHY_ID)
 141                         ret_val = -E1000_ERR_PHY;
 142                 break;
 143         case e1000_82574:
 144         case e1000_82583:
 145                 if (phy->id != BME1000_E_PHY_ID_R2)
 146                         ret_val = -E1000_ERR_PHY;
 147                 break;
 148         default:
 149                 ret_val = -E1000_ERR_PHY;
 150                 break;
 151         }
 152
 153         if (ret_val)
 154                 e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
 155
 156         return ret_val;
 157 }
 158
 159 /**
 160  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 161  *  @hw: pointer to the HW structure
 162  **/
 163 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 164 {
 165         struct e1000_nvm_info *nvm = &hw->nvm;
 166         u32 eecd = er32(EECD);
 167         u16 size;
 168
 169         nvm->opcode_bits = 8;
 170         nvm->delay_usec = 1;
 171         switch (nvm->override) {
 172         case e1000_nvm_override_spi_large:
 173                 nvm->page_size = 32;
 174                 nvm->address_bits = 16;
 175                 break;
 176         case e1000_nvm_override_spi_small:
 177                 nvm->page_size = 8;
 178                 nvm->address_bits = 8;
 179                 break;
 180         default:
 181                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 182                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 183                 break;
 184         }
 185
 186         switch (hw->mac.type) {
 187         case e1000_82573:
 188         case e1000_82574:
 189         case e1000_82583:
 190                 if (((eecd >> 15) & 0x3) == 0x3) {
 191                         nvm->type = e1000_nvm_flash_hw;
 192                         nvm->word_size = 2048;
 193                         /* Autonomous Flash update bit must be cleared due
 194                          * to Flash update issue.
 195                          */
 196                         eecd &= ~E1000_EECD_AUPDEN;
 197                         ew32(EECD, eecd);
 198                         break;
 199                 }
 200                 /* Fall Through */
 201         default:
 202                 nvm->type = e1000_nvm_eeprom_spi;
 203                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 204                                   E1000_EECD_SIZE_EX_SHIFT);
 205                 /* Added to a constant, "size" becomes the left-shift value
 206                  * for setting word_size.
 207                  */
 208                 size += NVM_WORD_SIZE_BASE_SHIFT;
 209
 210                 /* EEPROM access above 16k is unsupported */
 211                 if (size > 14)
 212                         size = 14;
 213                 nvm->word_size  = 1 << size;
 214                 break;
 215         }
 216
 217         /* Function Pointers */
 218         switch (hw->mac.type) {
 219         case e1000_82574:
 220         case e1000_82583:
 221                 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
 222                 nvm->ops.release = e1000_put_hw_semaphore_82574;
 223                 break;
 224         default:
 225                 break;
 226         }
 227
 228         return 0;
 229 }
 230
 231 /**
 232  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 233  *  @hw: pointer to the HW structure
 234  **/
 235 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 236 {
 237         struct e1000_mac_info *mac = &hw->mac;
 238         u32 swsm = 0;
 239         u32 swsm2 = 0;
 240         bool force_clear_smbi = false;
 241
 242         /* Set media type and media-dependent function pointers */
 243         switch (hw->adapter->pdev->device) {
 244         case E1000_DEV_ID_82571EB_FIBER:
 245         case E1000_DEV_ID_82572EI_FIBER:
 246         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 247                 hw->phy.media_type = e1000_media_type_fiber;
 248                 mac->ops.setup_physical_interface =
 249                     e1000_setup_fiber_serdes_link_82571;
 250                 mac->ops.check_for_link = e1000e_check_for_fiber_link;
 251                 mac->ops.get_link_up_info =
 252                     e1000e_get_speed_and_duplex_fiber_serdes;
 253                 break;
 254         case E1000_DEV_ID_82571EB_SERDES:
 255         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 256         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 257         case E1000_DEV_ID_82572EI_SERDES:
 258                 hw->phy.media_type = e1000_media_type_internal_serdes;
 259                 mac->ops.setup_physical_interface =
 260                     e1000_setup_fiber_serdes_link_82571;
 261                 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
 262                 mac->ops.get_link_up_info =
 263                     e1000e_get_speed_and_duplex_fiber_serdes;
 264                 break;
 265         default:
 266                 hw->phy.media_type = e1000_media_type_copper;
 267                 mac->ops.setup_physical_interface =
 268                     e1000_setup_copper_link_82571;
 269                 mac->ops.check_for_link = e1000e_check_for_copper_link;
 270                 mac->ops.get_link_up_info = e1000e_get_speed_and_duplex_copper;
 271                 break;
 272         }
 273
 274         /* Set mta register count */
 275         mac->mta_reg_count = 128;
 276         /* Set rar entry count */
 277         mac->rar_entry_count = E1000_RAR_ENTRIES;
 278         /* Adaptive IFS supported */
 279         mac->adaptive_ifs = true;
 280
 281         /* MAC-specific function pointers */
 282         switch (hw->mac.type) {
 283         case e1000_82573:
 284                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 285                 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
 286                 mac->ops.led_on = e1000e_led_on_generic;
 287                 mac->ops.blink_led = e1000e_blink_led_generic;
 288
 289                 /* FWSM register */
 290                 mac->has_fwsm = true;
 291                 /* ARC supported; valid only if manageability features are
 292                  * enabled.
 293                  */
 294                 mac->arc_subsystem_valid = !!(er32(FWSM) &
 295                                               E1000_FWSM_MODE_MASK);
 296                 break;
 297         case e1000_82574:
 298         case e1000_82583:
 299                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 300                 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
 301                 mac->ops.led_on = e1000_led_on_82574;
 302                 break;
 303         default:
 304                 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
 305                 mac->ops.led_on = e1000e_led_on_generic;
 306                 mac->ops.blink_led = e1000e_blink_led_generic;
 307
 308                 /* FWSM register */
 309                 mac->has_fwsm = true;
 310                 break;
 311         }
 312
 313         /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
 314          * first NVM or PHY access. This should be done for single-port
 315          * devices, and for one port only on dual-port devices so that
 316          * for those devices we can still use the SMBI lock to synchronize
 317          * inter-port accesses to the PHY & NVM.
 318          */
 319         switch (hw->mac.type) {
 320         case e1000_82571:
 321         case e1000_82572:
 322                 swsm2 = er32(SWSM2);
 323
 324                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
 325                         /* Only do this for the first interface on this card */
 326                         ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK);
 327                         force_clear_smbi = true;
 328                 } else {
 329                         force_clear_smbi = false;
 330                 }
 331                 break;
 332         default:
 333                 force_clear_smbi = true;
 334                 break;
 335         }
 336
 337         if (force_clear_smbi) {
 338                 /* Make sure SWSM.SMBI is clear */
 339                 swsm = er32(SWSM);
 340                 if (swsm & E1000_SWSM_SMBI) {
 341                         /* This bit should not be set on a first interface, and
 342                          * indicates that the bootagent or EFI code has
 343                          * improperly left this bit enabled
 344                          */
 345                         e_dbg("Please update your 82571 Bootagent\n");
 346                 }
 347                 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
 348         }
 349
 350         /* Initialize device specific counter of SMBI acquisition timeouts. */
 351         hw->dev_spec.e82571.smb_counter = 0;
 352
 353         return 0;
 354 }
 355
 356 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
 357 {
 358         struct e1000_hw *hw = &adapter->hw;
 359         static int global_quad_port_a; /* global port a indication */
 360         struct pci_dev *pdev = adapter->pdev;
 361         int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
 362         s32 rc;
 363
 364         rc = e1000_init_mac_params_82571(hw);
 365         if (rc)
 366                 return rc;
 367
 368         rc = e1000_init_nvm_params_82571(hw);
 369         if (rc)
 370                 return rc;
 371
 372         rc = e1000_init_phy_params_82571(hw);
 373         if (rc)
 374                 return rc;
 375
 376         /* tag quad port adapters first, it's used below */
 377         switch (pdev->device) {
 378         case E1000_DEV_ID_82571EB_QUAD_COPPER:
 379         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 380         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
 381         case E1000_DEV_ID_82571PT_QUAD_COPPER:
 382                 adapter->flags |= FLAG_IS_QUAD_PORT;
 383                 /* mark the first port */
 384                 if (global_quad_port_a == 0)
 385                         adapter->flags |= FLAG_IS_QUAD_PORT_A;
 386                 /* Reset for multiple quad port adapters */
 387                 global_quad_port_a++;
 388                 if (global_quad_port_a == 4)
 389                         global_quad_port_a = 0;
 390                 break;
 391         default:
 392                 break;
 393         }
 394
 395         switch (adapter->hw.mac.type) {
 396         case e1000_82571:
 397                 /* these dual ports don't have WoL on port B at all */
 398                 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
 399                      (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
 400                      (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
 401                     (is_port_b))
 402                         adapter->flags &= ~FLAG_HAS_WOL;
 403                 /* quad ports only support WoL on port A */
 404                 if (adapter->flags & FLAG_IS_QUAD_PORT &&
 405                     (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
 406                         adapter->flags &= ~FLAG_HAS_WOL;
 407                 /* Does not support WoL on any port */
 408                 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
 409                         adapter->flags &= ~FLAG_HAS_WOL;
 410                 break;
 411         case e1000_82573:
 412                 if (pdev->device == E1000_DEV_ID_82573L) {
 413                         adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
 414                         adapter->max_hw_frame_size = DEFAULT_JUMBO;
 415                 }
 416                 break;
 417         default:
 418                 break;
 419         }
 420
 421         return 0;
 422 }
 423
 424 /**
 425  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 426  *  @hw: pointer to the HW structure
 427  *
 428  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 429  *  revision in the hardware structure.
 430  **/
 431 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 432 {
 433         struct e1000_phy_info *phy = &hw->phy;
 434         s32 ret_val;
 435         u16 phy_id = 0;
 436
 437         switch (hw->mac.type) {
 438         case e1000_82571:
 439         case e1000_82572:
 440                 /* The 82571 firmware may still be configuring the PHY.
 441                  * In this case, we cannot access the PHY until the
 442                  * configuration is done.  So we explicitly set the
 443                  * PHY ID.
 444                  */
 445                 phy->id = IGP01E1000_I_PHY_ID;
 446                 break;
 447         case e1000_82573:
 448                 return e1000e_get_phy_id(hw);
 449                 break;
 450         case e1000_82574:
 451         case e1000_82583:
 452                 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
 453                 if (ret_val)
 454                         return ret_val;
 455
 456                 phy->id = (u32)(phy_id << 16);
 457                 udelay(20);
 458                 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
 459                 if (ret_val)
 460                         return ret_val;
 461
 462                 phy->id |= (u32)(phy_id);
 463                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 464                 break;
 465         default:
 466                 return -E1000_ERR_PHY;
 467                 break;
 468         }
 469
 470         return 0;
 471 }
 472
 473 /**
 474  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 475  *  @hw: pointer to the HW structure
 476  *
 477  *  Acquire the HW semaphore to access the PHY or NVM
 478  **/
 479 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 480 {
 481         u32 swsm;
 482         s32 sw_timeout = hw->nvm.word_size + 1;
 483         s32 fw_timeout = hw->nvm.word_size + 1;
 484         s32 i = 0;
 485
 486         /* If we have timedout 3 times on trying to acquire
 487          * the inter-port SMBI semaphore, there is old code
 488          * operating on the other port, and it is not
 489          * releasing SMBI. Modify the number of times that
 490          * we try for the semaphore to interwork with this
 491          * older code.
 492          */
 493         if (hw->dev_spec.e82571.smb_counter > 2)
 494                 sw_timeout = 1;
 495
 496         /* Get the SW semaphore */
 497         while (i < sw_timeout) {
 498                 swsm = er32(SWSM);
 499                 if (!(swsm & E1000_SWSM_SMBI))
 500                         break;
 501
 502                 udelay(50);
 503                 i++;
 504         }
 505
 506         if (i == sw_timeout) {
 507                 e_dbg("Driver can't access device - SMBI bit is set.\n");
 508                 hw->dev_spec.e82571.smb_counter++;
 509         }
 510         /* Get the FW semaphore. */
 511         for (i = 0; i < fw_timeout; i++) {
 512                 swsm = er32(SWSM);
 513                 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
 514
 515                 /* Semaphore acquired if bit latched */
 516                 if (er32(SWSM) & E1000_SWSM_SWESMBI)
 517                         break;
 518
 519                 udelay(50);
 520         }
 521
 522         if (i == fw_timeout) {
 523                 /* Release semaphores */
 524                 e1000_put_hw_semaphore_82571(hw);
 525                 e_dbg("Driver can't access the NVM\n");
 526                 return -E1000_ERR_NVM;
 527         }
 528
 529         return 0;
 530 }
 531
 532 /**
 533  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 534  *  @hw: pointer to the HW structure
 535  *
 536  *  Release hardware semaphore used to access the PHY or NVM
 537  **/
 538 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 539 {
 540         u32 swsm;
 541
 542         swsm = er32(SWSM);
 543         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 544         ew32(SWSM, swsm);
 545 }
 546 /**
 547  *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
 548  *  @hw: pointer to the HW structure
 549  *
 550  *  Acquire the HW semaphore during reset.
 551  *
 552  **/
 553 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
 554 {
 555         u32 extcnf_ctrl;
 556         s32 i = 0;
 557
 558         extcnf_ctrl = er32(EXTCNF_CTRL);
 559         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 560         do {
 561                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 562                 extcnf_ctrl = er32(EXTCNF_CTRL);
 563
 564                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 565                         break;
 566
 567                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 568
 569                 usleep_range(2000, 4000);
 570                 i++;
 571         } while (i < MDIO_OWNERSHIP_TIMEOUT);
 572
 573         if (i == MDIO_OWNERSHIP_TIMEOUT) {
 574                 /* Release semaphores */
 575                 e1000_put_hw_semaphore_82573(hw);
 576                 e_dbg("Driver can't access the PHY\n");
 577                 return -E1000_ERR_PHY;
 578         }
 579
 580         return 0;
 581 }
 582
 583 /**
 584  *  e1000_put_hw_semaphore_82573 - Release hardware semaphore
 585  *  @hw: pointer to the HW structure
 586  *
 587  *  Release hardware semaphore used during reset.
 588  *
 589  **/
 590 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
 591 {
 592         u32 extcnf_ctrl;
 593
 594         extcnf_ctrl = er32(EXTCNF_CTRL);
 595         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 596         ew32(EXTCNF_CTRL, extcnf_ctrl);
 597 }
 598
 599 static DEFINE_MUTEX(swflag_mutex);
 600
 601 /**
 602  *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
 603  *  @hw: pointer to the HW structure
 604  *
 605  *  Acquire the HW semaphore to access the PHY or NVM.
 606  *
 607  **/
 608 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
 609 {
 610         s32 ret_val;
 611
 612         mutex_lock(&swflag_mutex);
 613         ret_val = e1000_get_hw_semaphore_82573(hw);
 614         if (ret_val)
 615                 mutex_unlock(&swflag_mutex);
 616         return ret_val;
 617 }
 618
 619 /**
 620  *  e1000_put_hw_semaphore_82574 - Release hardware semaphore
 621  *  @hw: pointer to the HW structure
 622  *
 623  *  Release hardware semaphore used to access the PHY or NVM
 624  *
 625  **/
 626 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
 627 {
 628         e1000_put_hw_semaphore_82573(hw);
 629         mutex_unlock(&swflag_mutex);
 630 }
 631
 632 /**
 633  *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
 634  *  @hw: pointer to the HW structure
 635  *  @active: true to enable LPLU, false to disable
 636  *
 637  *  Sets the LPLU D0 state according to the active flag.
 638  *  LPLU will not be activated unless the
 639  *  device autonegotiation advertisement meets standards of
 640  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 641  *  This is a function pointer entry point only called by
 642  *  PHY setup routines.
 643  **/
 644 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
 645 {
 646         u32 data = er32(POEMB);
 647
 648         if (active)
 649                 data |= E1000_PHY_CTRL_D0A_LPLU;
 650         else
 651                 data &= ~E1000_PHY_CTRL_D0A_LPLU;
 652
 653         ew32(POEMB, data);
 654         return 0;
 655 }
 656
 657 /**
 658  *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
 659  *  @hw: pointer to the HW structure
 660  *  @active: boolean used to enable/disable lplu
 661  *
 662  *  The low power link up (lplu) state is set to the power management level D3
 663  *  when active is true, else clear lplu for D3. LPLU
 664  *  is used during Dx states where the power conservation is most important.
 665  *  During driver activity, SmartSpeed should be enabled so performance is
 666  *  maintained.
 667  **/
 668 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
 669 {
 670         u32 data = er32(POEMB);
 671
 672         if (!active) {
 673                 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 674         } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 675                    (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
 676                    (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
 677                 data |= E1000_PHY_CTRL_NOND0A_LPLU;
 678         }
 679
 680         ew32(POEMB, data);
 681         return 0;
 682 }
 683
 684 /**
 685  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 686  *  @hw: pointer to the HW structure
 687  *
 688  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 689  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 690  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 691  *  hardware semaphore.
 692  **/
 693 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 694 {
 695         s32 ret_val;
 696
 697         ret_val = e1000_get_hw_semaphore_82571(hw);
 698         if (ret_val)
 699                 return ret_val;
 700
 701         switch (hw->mac.type) {
 702         case e1000_82573:
 703                 break;
 704         default:
 705                 ret_val = e1000e_acquire_nvm(hw);
 706                 break;
 707         }
 708
 709         if (ret_val)
 710                 e1000_put_hw_semaphore_82571(hw);
 711
 712         return ret_val;
 713 }
 714
 715 /**
 716  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 717  *  @hw: pointer to the HW structure
 718  *
 719  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 720  **/
 721 static void e1000_release_nvm_82571(struct e1000_hw *hw)
 722 {
 723         e1000e_release_nvm(hw);
 724         e1000_put_hw_semaphore_82571(hw);
 725 }
 726
 727 /**
 728  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 729  *  @hw: pointer to the HW structure
 730  *  @offset: offset within the EEPROM to be written to
 731  *  @words: number of words to write
 732  *  @data: 16 bit word(s) to be written to the EEPROM
 733  *
 734  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 735  *
 736  *  If e1000e_update_nvm_checksum is not called after this function, the
 737  *  EEPROM will most likely contain an invalid checksum.
 738  **/
 739 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 740                                  u16 *data)
 741 {
 742         s32 ret_val;
 743
 744         switch (hw->mac.type) {
 745         case e1000_82573:
 746         case e1000_82574:
 747         case e1000_82583:
 748                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 749                 break;
 750         case e1000_82571:
 751         case e1000_82572:
 752                 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
 753                 break;
 754         default:
 755                 ret_val = -E1000_ERR_NVM;
 756                 break;
 757         }
 758
 759         return ret_val;
 760 }
 761
 762 /**
 763  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 764  *  @hw: pointer to the HW structure
 765  *
 766  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 767  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 768  *  value to the EEPROM.
 769  **/
 770 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 771 {
 772         u32 eecd;
 773         s32 ret_val;
 774         u16 i;
 775
 776         ret_val = e1000e_update_nvm_checksum_generic(hw);
 777         if (ret_val)
 778                 return ret_val;
 779
 780         /* If our nvm is an EEPROM, then we're done
 781          * otherwise, commit the checksum to the flash NVM.
 782          */
 783         if (hw->nvm.type != e1000_nvm_flash_hw)
 784                 return 0;
 785
 786         /* Check for pending operations. */
 787         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 788                 usleep_range(1000, 2000);
 789                 if (!(er32(EECD) & E1000_EECD_FLUPD))
 790                         break;
 791         }
 792
 793         if (i == E1000_FLASH_UPDATES)
 794                 return -E1000_ERR_NVM;
 795
 796         /* Reset the firmware if using STM opcode. */
 797         if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 798                 /* The enabling of and the actual reset must be done
 799                  * in two write cycles.
 800                  */
 801                 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
 802                 e1e_flush();
 803                 ew32(HICR, E1000_HICR_FW_RESET);
 804         }
 805
 806         /* Commit the write to flash */
 807         eecd = er32(EECD) | E1000_EECD_FLUPD;
 808         ew32(EECD, eecd);
 809
 810         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 811                 usleep_range(1000, 2000);
 812                 if (!(er32(EECD) & E1000_EECD_FLUPD))
 813                         break;
 814         }
 815
 816         if (i == E1000_FLASH_UPDATES)
 817                 return -E1000_ERR_NVM;
 818
 819         return 0;
 820 }
 821
 822 /**
 823  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 824  *  @hw: pointer to the HW structure
 825  *
 826  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 827  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 828  **/
 829 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 830 {
 831         if (hw->nvm.type == e1000_nvm_flash_hw)
 832                 e1000_fix_nvm_checksum_82571(hw);
 833
 834         return e1000e_validate_nvm_checksum_generic(hw);
 835 }
 836
 837 /**
 838  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 839  *  @hw: pointer to the HW structure
 840  *  @offset: offset within the EEPROM to be written to
 841  *  @words: number of words to write
 842  *  @data: 16 bit word(s) to be written to the EEPROM
 843  *
 844  *  After checking for invalid values, poll the EEPROM to ensure the previous
 845  *  command has completed before trying to write the next word.  After write
 846  *  poll for completion.
 847  *
 848  *  If e1000e_update_nvm_checksum is not called after this function, the
 849  *  EEPROM will most likely contain an invalid checksum.
 850  **/
 851 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 852                                       u16 words, u16 *data)
 853 {
 854         struct e1000_nvm_info *nvm = &hw->nvm;
 855         u32 i, eewr = 0;
 856         s32 ret_val = 0;
 857
 858         /* A check for invalid values:  offset too large, too many words,
 859          * and not enough words.
 860          */
 861         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 862             (words == 0)) {
 863                 e_dbg("nvm parameter(s) out of bounds\n");
 864                 return -E1000_ERR_NVM;
 865         }
 866
 867         for (i = 0; i < words; i++) {
 868                 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
 869                        ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
 870                        E1000_NVM_RW_REG_START;
 871
 872                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 873                 if (ret_val)
 874                         break;
 875
 876                 ew32(EEWR, eewr);
 877
 878                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 879                 if (ret_val)
 880                         break;
 881         }
 882
 883         return ret_val;
 884 }
 885
 886 /**
 887  *  e1000_get_cfg_done_82571 - Poll for configuration done
 888  *  @hw: pointer to the HW structure
 889  *
 890  *  Reads the management control register for the config done bit to be set.
 891  **/
 892 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 893 {
 894         s32 timeout = PHY_CFG_TIMEOUT;
 895
 896         while (timeout) {
 897                 if (er32(EEMNGCTL) &
 898                     E1000_NVM_CFG_DONE_PORT_0)
 899                         break;
 900                 usleep_range(1000, 2000);
 901                 timeout--;
 902         }
 903         if (!timeout) {
 904                 e_dbg("MNG configuration cycle has not completed.\n");
 905                 return -E1000_ERR_RESET;
 906         }
 907
 908         return 0;
 909 }
 910
 911 /**
 912  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 913  *  @hw: pointer to the HW structure
 914  *  @active: true to enable LPLU, false to disable
 915  *
 916  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 917  *  this function also disables smart speed and vice versa.  LPLU will not be
 918  *  activated unless the device autonegotiation advertisement meets standards
 919  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 920  *  pointer entry point only called by PHY setup routines.
 921  **/
 922 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 923 {
 924         struct e1000_phy_info *phy = &hw->phy;
 925         s32 ret_val;
 926         u16 data;
 927
 928         ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 929         if (ret_val)
 930                 return ret_val;
 931
 932         if (active) {
 933                 data |= IGP02E1000_PM_D0_LPLU;
 934                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 935                 if (ret_val)
 936                         return ret_val;
 937
 938                 /* When LPLU is enabled, we should disable SmartSpeed */
 939                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 940                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 941                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 942                 if (ret_val)
 943                         return ret_val;
 944         } else {
 945                 data &= ~IGP02E1000_PM_D0_LPLU;
 946                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 947                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 948                  * during Dx states where the power conservation is most
 949                  * important.  During driver activity we should enable
 950                  * SmartSpeed, so performance is maintained.
 951                  */
 952                 if (phy->smart_speed == e1000_smart_speed_on) {
 953                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 954                                            &data);
 955                         if (ret_val)
 956                                 return ret_val;
 957
 958                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 959                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 960                                            data);
 961                         if (ret_val)
 962                                 return ret_val;
 963                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 964                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 965                                            &data);
 966                         if (ret_val)
 967                                 return ret_val;
 968
 969                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 970                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 971                                            data);
 972                         if (ret_val)
 973                                 return ret_val;
 974                 }
 975         }
 976
 977         return 0;
 978 }
 979
 980 /**
 981  *  e1000_reset_hw_82571 - Reset hardware
 982  *  @hw: pointer to the HW structure
 983  *
 984  *  This resets the hardware into a known state.
 985  **/
 986 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
 987 {
 988         u32 ctrl, ctrl_ext, eecd, tctl;
 989         s32 ret_val;
 990
 991         /* Prevent the PCI-E bus from sticking if there is no TLP connection
 992          * on the last TLP read/write transaction when MAC is reset.
 993          */
 994         ret_val = e1000e_disable_pcie_master(hw);
 995         if (ret_val)
 996                 e_dbg("PCI-E Master disable polling has failed.\n");
 997
 998         e_dbg("Masking off all interrupts\n");
 999         ew32(IMC, 0xffffffff);
1000
1001         ew32(RCTL, 0);
1002         tctl = er32(TCTL);
1003         tctl &= ~E1000_TCTL_EN;
1004         ew32(TCTL, tctl);
1005         e1e_flush();
1006
1007         usleep_range(10000, 20000);
1008
1009         /* Must acquire the MDIO ownership before MAC reset.
1010          * Ownership defaults to firmware after a reset.
1011          */
1012         switch (hw->mac.type) {
1013         case e1000_82573:
1014                 ret_val = e1000_get_hw_semaphore_82573(hw);
1015                 break;
1016         case e1000_82574:
1017         case e1000_82583:
1018                 ret_val = e1000_get_hw_semaphore_82574(hw);
1019                 break;
1020         default:
1021                 break;
1022         }
1023         if (ret_val)
1024                 e_dbg("Cannot acquire MDIO ownership\n");
1025
1026         ctrl = er32(CTRL);
1027
1028         e_dbg("Issuing a global reset to MAC\n");
1029         ew32(CTRL, ctrl | E1000_CTRL_RST);
1030
1031         /* Must release MDIO ownership and mutex after MAC reset. */
1032         switch (hw->mac.type) {
1033         case e1000_82574:
1034         case e1000_82583:
1035                 e1000_put_hw_semaphore_82574(hw);
1036                 break;
1037         default:
1038                 break;
1039         }
1040
1041         if (hw->nvm.type == e1000_nvm_flash_hw) {
1042                 udelay(10);
1043                 ctrl_ext = er32(CTRL_EXT);
1044                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1045                 ew32(CTRL_EXT, ctrl_ext);
1046                 e1e_flush();
1047         }
1048
1049         ret_val = e1000e_get_auto_rd_done(hw);
1050         if (ret_val)
1051                 /* We don't want to continue accessing MAC registers. */
1052                 return ret_val;
1053
1054         /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1055          * Need to wait for Phy configuration completion before accessing
1056          * NVM and Phy.
1057          */
1058
1059         switch (hw->mac.type) {
1060         case e1000_82571:
1061         case e1000_82572:
1062                 /* REQ and GNT bits need to be cleared when using AUTO_RD
1063                  * to access the EEPROM.
1064                  */
1065                 eecd = er32(EECD);
1066                 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1067                 ew32(EECD, eecd);
1068                 break;
1069         case e1000_82573:
1070         case e1000_82574:
1071         case e1000_82583:
1072                 msleep(25);
1073                 break;
1074         default:
1075                 break;
1076         }
1077
1078         /* Clear any pending interrupt events. */
1079         ew32(IMC, 0xffffffff);
1080         er32(ICR);
1081
1082         if (hw->mac.type == e1000_82571) {
1083                 /* Install any alternate MAC address into RAR0 */
1084                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1085                 if (ret_val)
1086                         return ret_val;
1087
1088                 e1000e_set_laa_state_82571(hw, true);
1089         }
1090
1091         /* Reinitialize the 82571 serdes link state machine */
1092         if (hw->phy.media_type == e1000_media_type_internal_serdes)
1093                 hw->mac.serdes_link_state = e1000_serdes_link_down;
1094
1095         return 0;
1096 }
1097
1098 /**
1099  *  e1000_init_hw_82571 - Initialize hardware
1100  *  @hw: pointer to the HW structure
1101  *
1102  *  This inits the hardware readying it for operation.
1103  **/
1104 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1105 {
1106         struct e1000_mac_info *mac = &hw->mac;
1107         u32 reg_data;
1108         s32 ret_val;
1109         u16 i, rar_count = mac->rar_entry_count;
1110
1111         e1000_initialize_hw_bits_82571(hw);
1112
1113         /* Initialize identification LED */
1114         ret_val = mac->ops.id_led_init(hw);
1115         if (ret_val)
1116                 e_dbg("Error initializing identification LED\n");
1117                 /* This is not fatal and we should not stop init due to this */
1118
1119         /* Disabling VLAN filtering */
1120         e_dbg("Initializing the IEEE VLAN\n");
1121         mac->ops.clear_vfta(hw);
1122
1123         /* Setup the receive address.
1124          * If, however, a locally administered address was assigned to the
1125          * 82571, we must reserve a RAR for it to work around an issue where
1126          * resetting one port will reload the MAC on the other port.
1127          */
1128         if (e1000e_get_laa_state_82571(hw))
1129                 rar_count--;
1130         e1000e_init_rx_addrs(hw, rar_count);
1131
1132         /* Zero out the Multicast HASH table */
1133         e_dbg("Zeroing the MTA\n");
1134         for (i = 0; i < mac->mta_reg_count; i++)
1135                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1136
1137         /* Setup link and flow control */
1138         ret_val = mac->ops.setup_link(hw);
1139
1140         /* Set the transmit descriptor write-back policy */
1141         reg_data = er32(TXDCTL(0));
1142         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1143                    E1000_TXDCTL_FULL_TX_DESC_WB |
1144                    E1000_TXDCTL_COUNT_DESC;
1145         ew32(TXDCTL(0), reg_data);
1146
1147         /* ...for both queues. */
1148         switch (mac->type) {
1149         case e1000_82573:
1150                 e1000e_enable_tx_pkt_filtering(hw);
1151                 /* fall through */
1152         case e1000_82574:
1153         case e1000_82583:
1154                 reg_data = er32(GCR);
1155                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1156                 ew32(GCR, reg_data);
1157                 break;
1158         default:
1159                 reg_data = er32(TXDCTL(1));
1160                 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1161                            E1000_TXDCTL_FULL_TX_DESC_WB |
1162                            E1000_TXDCTL_COUNT_DESC;
1163                 ew32(TXDCTL(1), reg_data);
1164                 break;
1165         }
1166
1167         /* Clear all of the statistics registers (clear on read).  It is
1168          * important that we do this after we have tried to establish link
1169          * because the symbol error count will increment wildly if there
1170          * is no link.
1171          */
1172         e1000_clear_hw_cntrs_82571(hw);
1173
1174         return ret_val;
1175 }
1176
1177 /**
1178  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1179  *  @hw: pointer to the HW structure
1180  *
1181  *  Initializes required hardware-dependent bits needed for normal operation.
1182  **/
1183 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1184 {
1185         u32 reg;
1186
1187         /* Transmit Descriptor Control 0 */
1188         reg = er32(TXDCTL(0));
1189         reg |= (1 << 22);
1190         ew32(TXDCTL(0), reg);
1191
1192         /* Transmit Descriptor Control 1 */
1193         reg = er32(TXDCTL(1));
1194         reg |= (1 << 22);
1195         ew32(TXDCTL(1), reg);
1196
1197         /* Transmit Arbitration Control 0 */
1198         reg = er32(TARC(0));
1199         reg &= ~(0xF << 27); /* 30:27 */
1200         switch (hw->mac.type) {
1201         case e1000_82571:
1202         case e1000_82572:
1203                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1204                 break;
1205         case e1000_82574:
1206         case e1000_82583:
1207                 reg |= (1 << 26);
1208                 break;
1209         default:
1210                 break;
1211         }
1212         ew32(TARC(0), reg);
1213
1214         /* Transmit Arbitration Control 1 */
1215         reg = er32(TARC(1));
1216         switch (hw->mac.type) {
1217         case e1000_82571:
1218         case e1000_82572:
1219                 reg &= ~((1 << 29) | (1 << 30));
1220                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1221                 if (er32(TCTL) & E1000_TCTL_MULR)
1222                         reg &= ~(1 << 28);
1223                 else
1224                         reg |= (1 << 28);
1225                 ew32(TARC(1), reg);
1226                 break;
1227         default:
1228                 break;
1229         }
1230
1231         /* Device Control */
1232         switch (hw->mac.type) {
1233         case e1000_82573:
1234         case e1000_82574:
1235         case e1000_82583:
1236                 reg = er32(CTRL);
1237                 reg &= ~(1 << 29);
1238                 ew32(CTRL, reg);
1239                 break;
1240         default:
1241                 break;
1242         }
1243
1244         /* Extended Device Control */
1245         switch (hw->mac.type) {
1246         case e1000_82573:
1247         case e1000_82574:
1248         case e1000_82583:
1249                 reg = er32(CTRL_EXT);
1250                 reg &= ~(1 << 23);
1251                 reg |= (1 << 22);
1252                 ew32(CTRL_EXT, reg);
1253                 break;
1254         default:
1255                 break;
1256         }
1257
1258         if (hw->mac.type == e1000_82571) {
1259                 reg = er32(PBA_ECC);
1260                 reg |= E1000_PBA_ECC_CORR_EN;
1261                 ew32(PBA_ECC, reg);
1262         }
1263
1264         /* Workaround for hardware errata.
1265          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1266          */
1267         if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) {
1268                 reg = er32(CTRL_EXT);
1269                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1270                 ew32(CTRL_EXT, reg);
1271         }
1272
1273         /* Disable IPv6 extension header parsing because some malformed
1274          * IPv6 headers can hang the Rx.
1275          */
1276         if (hw->mac.type <= e1000_82573) {
1277                 reg = er32(RFCTL);
1278                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1279                 ew32(RFCTL, reg);
1280         }
1281
1282         /* PCI-Ex Control Registers */
1283         switch (hw->mac.type) {
1284         case e1000_82574:
1285         case e1000_82583:
1286                 reg = er32(GCR);
1287                 reg |= (1 << 22);
1288                 ew32(GCR, reg);
1289
1290                 /* Workaround for hardware errata.
1291                  * apply workaround for hardware errata documented in errata
1292                  * docs Fixes issue where some error prone or unreliable PCIe
1293                  * completions are occurring, particularly with ASPM enabled.
1294                  * Without fix, issue can cause Tx timeouts.
1295                  */
1296                 reg = er32(GCR2);
1297                 reg |= 1;
1298                 ew32(GCR2, reg);
1299                 break;
1300         default:
1301                 break;
1302         }
1303 }
1304
1305 /**
1306  *  e1000_clear_vfta_82571 - Clear VLAN filter table
1307  *  @hw: pointer to the HW structure
1308  *
1309  *  Clears the register array which contains the VLAN filter table by
1310  *  setting all the values to 0.
1311  **/
1312 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1313 {
1314         u32 offset;
1315         u32 vfta_value = 0;
1316         u32 vfta_offset = 0;
1317         u32 vfta_bit_in_reg = 0;
1318
1319         switch (hw->mac.type) {
1320         case e1000_82573:
1321         case e1000_82574:
1322         case e1000_82583:
1323                 if (hw->mng_cookie.vlan_id != 0) {
1324                         /* The VFTA is a 4096b bit-field, each identifying
1325                          * a single VLAN ID.  The following operations
1326                          * determine which 32b entry (i.e. offset) into the
1327                          * array we want to set the VLAN ID (i.e. bit) of
1328                          * the manageability unit.
1329                          */
1330                         vfta_offset = (hw->mng_cookie.vlan_id >>
1331                                        E1000_VFTA_ENTRY_SHIFT) &
1332                                       E1000_VFTA_ENTRY_MASK;
1333                         vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1334                                                E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1335                 }
1336                 break;
1337         default:
1338                 break;
1339         }
1340         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1341                 /* If the offset we want to clear is the same offset of the
1342                  * manageability VLAN ID, then clear all bits except that of
1343                  * the manageability unit.
1344                  */
1345                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1346                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1347                 e1e_flush();
1348         }
1349 }
1350
1351 /**
1352  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1353  *  @hw: pointer to the HW structure
1354  *
1355  *  Reads the NVM Initialization Control Word 2 and returns true
1356  *  (>0) if any manageability is enabled, else false (0).
1357  **/
1358 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1359 {
1360         u16 data;
1361
1362         e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1363         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1364 }
1365
1366 /**
1367  *  e1000_led_on_82574 - Turn LED on
1368  *  @hw: pointer to the HW structure
1369  *
1370  *  Turn LED on.
1371  **/
1372 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1373 {
1374         u32 ctrl;
1375         u32 i;
1376
1377         ctrl = hw->mac.ledctl_mode2;
1378         if (!(E1000_STATUS_LU & er32(STATUS))) {
1379                 /* If no link, then turn LED on by setting the invert bit
1380                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1381                  */
1382                 for (i = 0; i < 4; i++)
1383                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1384                             E1000_LEDCTL_MODE_LED_ON)
1385                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1386         }
1387         ew32(LEDCTL, ctrl);
1388
1389         return 0;
1390 }
1391
1392 /**
1393  *  e1000_check_phy_82574 - check 82574 phy hung state
1394  *  @hw: pointer to the HW structure
1395  *
1396  *  Returns whether phy is hung or not
1397  **/
1398 bool e1000_check_phy_82574(struct e1000_hw *hw)
1399 {
1400         u16 status_1kbt = 0;
1401         u16 receive_errors = 0;
1402         s32 ret_val = 0;
1403
1404         /* Read PHY Receive Error counter first, if its is max - all F's then
1405          * read the Base1000T status register If both are max then PHY is hung.
1406          */
1407         ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);
1408         if (ret_val)
1409                 return false;
1410         if (receive_errors == E1000_RECEIVE_ERROR_MAX)  {
1411                 ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt);
1412                 if (ret_val)
1413                         return false;
1414                 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1415                     E1000_IDLE_ERROR_COUNT_MASK)
1416                         return true;
1417         }
1418
1419         return false;
1420 }
1421
1422 /**
1423  *  e1000_setup_link_82571 - Setup flow control and link settings
1424  *  @hw: pointer to the HW structure
1425  *
1426  *  Determines which flow control settings to use, then configures flow
1427  *  control.  Calls the appropriate media-specific link configuration
1428  *  function.  Assuming the adapter has a valid link partner, a valid link
1429  *  should be established.  Assumes the hardware has previously been reset
1430  *  and the transmitter and receiver are not enabled.
1431  **/
1432 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1433 {
1434         /* 82573 does not have a word in the NVM to determine
1435          * the default flow control setting, so we explicitly
1436          * set it to full.
1437          */
1438         switch (hw->mac.type) {
1439         case e1000_82573:
1440         case e1000_82574:
1441         case e1000_82583:
1442                 if (hw->fc.requested_mode == e1000_fc_default)
1443                         hw->fc.requested_mode = e1000_fc_full;
1444                 break;
1445         default:
1446                 break;
1447         }
1448
1449         return e1000e_setup_link_generic(hw);
1450 }
1451
1452 /**
1453  *  e1000_setup_copper_link_82571 - Configure copper link settings
1454  *  @hw: pointer to the HW structure
1455  *
1456  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1457  *  for link, once link is established calls to configure collision distance
1458  *  and flow control are called.
1459  **/
1460 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1461 {
1462         u32 ctrl;
1463         s32 ret_val;
1464
1465         ctrl = er32(CTRL);
1466         ctrl |= E1000_CTRL_SLU;
1467         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1468         ew32(CTRL, ctrl);
1469
1470         switch (hw->phy.type) {
1471         case e1000_phy_m88:
1472         case e1000_phy_bm:
1473                 ret_val = e1000e_copper_link_setup_m88(hw);
1474                 break;
1475         case e1000_phy_igp_2:
1476                 ret_val = e1000e_copper_link_setup_igp(hw);
1477                 break;
1478         default:
1479                 return -E1000_ERR_PHY;
1480                 break;
1481         }
1482
1483         if (ret_val)
1484                 return ret_val;
1485
1486         return e1000e_setup_copper_link(hw);
1487 }
1488
1489 /**
1490  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1491  *  @hw: pointer to the HW structure
1492  *
1493  *  Configures collision distance and flow control for fiber and serdes links.
1494  *  Upon successful setup, poll for link.
1495  **/
1496 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1497 {
1498         switch (hw->mac.type) {
1499         case e1000_82571:
1500         case e1000_82572:
1501                 /* If SerDes loopback mode is entered, there is no form
1502                  * of reset to take the adapter out of that mode.  So we
1503                  * have to explicitly take the adapter out of loopback
1504                  * mode.  This prevents drivers from twiddling their thumbs
1505                  * if another tool failed to take it out of loopback mode.
1506                  */
1507                 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1508                 break;
1509         default:
1510                 break;
1511         }
1512
1513         return e1000e_setup_fiber_serdes_link(hw);
1514 }
1515
1516 /**
1517  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1518  *  @hw: pointer to the HW structure
1519  *
1520  *  Reports the link state as up or down.
1521  *
1522  *  If autonegotiation is supported by the link partner, the link state is
1523  *  determined by the result of autonegotiation. This is the most likely case.
1524  *  If autonegotiation is not supported by the link partner, and the link
1525  *  has a valid signal, force the link up.
1526  *
1527  *  The link state is represented internally here by 4 states:
1528  *
1529  *  1) down
1530  *  2) autoneg_progress
1531  *  3) autoneg_complete (the link successfully autonegotiated)
1532  *  4) forced_up (the link has been forced up, it did not autonegotiate)
1533  *
1534  **/
1535 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1536 {
1537         struct e1000_mac_info *mac = &hw->mac;
1538         u32 rxcw;
1539         u32 ctrl;
1540         u32 status;
1541         u32 txcw;
1542         u32 i;
1543         s32 ret_val = 0;
1544
1545         ctrl = er32(CTRL);
1546         status = er32(STATUS);
1547         rxcw = er32(RXCW);
1548         /* SYNCH bit and IV bit are sticky */
1549         udelay(10);
1550         rxcw = er32(RXCW);
1551
1552         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1553
1554                 /* Receiver is synchronized with no invalid bits.  */
1555                 switch (mac->serdes_link_state) {
1556                 case e1000_serdes_link_autoneg_complete:
1557                         if (!(status & E1000_STATUS_LU)) {
1558                                 /* We have lost link, retry autoneg before
1559                                  * reporting link failure
1560                                  */
1561                                 mac->serdes_link_state =
1562                                     e1000_serdes_link_autoneg_progress;
1563                                 mac->serdes_has_link = false;
1564                                 e_dbg("AN_UP     -> AN_PROG\n");
1565                         } else {
1566                                 mac->serdes_has_link = true;
1567                         }
1568                         break;
1569
1570                 case e1000_serdes_link_forced_up:
1571                         /* If we are receiving /C/ ordered sets, re-enable
1572                          * auto-negotiation in the TXCW register and disable
1573                          * forced link in the Device Control register in an
1574                          * attempt to auto-negotiate with our link partner.
1575                          */
1576                         if (rxcw & E1000_RXCW_C) {
1577                                 /* Enable autoneg, and unforce link up */
1578                                 ew32(TXCW, mac->txcw);
1579                                 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1580                                 mac->serdes_link_state =
1581                                     e1000_serdes_link_autoneg_progress;
1582                                 mac->serdes_has_link = false;
1583                                 e_dbg("FORCED_UP -> AN_PROG\n");
1584                         } else {
1585                                 mac->serdes_has_link = true;
1586                         }
1587                         break;
1588
1589                 case e1000_serdes_link_autoneg_progress:
1590                         if (rxcw & E1000_RXCW_C) {
1591                                 /* We received /C/ ordered sets, meaning the
1592                                  * link partner has autonegotiated, and we can
1593                                  * trust the Link Up (LU) status bit.
1594                                  */
1595                                 if (status & E1000_STATUS_LU) {
1596                                         mac->serdes_link_state =
1597                                             e1000_serdes_link_autoneg_complete;
1598                                         e_dbg("AN_PROG   -> AN_UP\n");
1599                                         mac->serdes_has_link = true;
1600                                 } else {
1601                                         /* Autoneg completed, but failed. */
1602                                         mac->serdes_link_state =
1603                                             e1000_serdes_link_down;
1604                                         e_dbg("AN_PROG   -> DOWN\n");
1605                                 }
1606                         } else {
1607                                 /* The link partner did not autoneg.
1608                                  * Force link up and full duplex, and change
1609                                  * state to forced.
1610                                  */
1611                                 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1612                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1613                                 ew32(CTRL, ctrl);
1614
1615                                 /* Configure Flow Control after link up. */
1616                                 ret_val = e1000e_config_fc_after_link_up(hw);
1617                                 if (ret_val) {
1618                                         e_dbg("Error config flow control\n");
1619                                         break;
1620                                 }
1621                                 mac->serdes_link_state =
1622                                     e1000_serdes_link_forced_up;
1623                                 mac->serdes_has_link = true;
1624                                 e_dbg("AN_PROG   -> FORCED_UP\n");
1625                         }
1626                         break;
1627
1628                 case e1000_serdes_link_down:
1629                 default:
1630                         /* The link was down but the receiver has now gained
1631                          * valid sync, so lets see if we can bring the link
1632                          * up.
1633                          */
1634                         ew32(TXCW, mac->txcw);
1635                         ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1636                         mac->serdes_link_state =
1637                             e1000_serdes_link_autoneg_progress;
1638                         mac->serdes_has_link = false;
1639                         e_dbg("DOWN      -> AN_PROG\n");
1640                         break;
1641                 }
1642         } else {
1643                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1644                         mac->serdes_has_link = false;
1645                         mac->serdes_link_state = e1000_serdes_link_down;
1646                         e_dbg("ANYSTATE  -> DOWN\n");
1647                 } else {
1648                         /* Check several times, if SYNCH bit and CONFIG
1649                          * bit both are consistently 1 then simply ignore
1650                          * the IV bit and restart Autoneg
1651                          */
1652                         for (i = 0; i < AN_RETRY_COUNT; i++) {
1653                                 udelay(10);
1654                                 rxcw = er32(RXCW);
1655                                 if ((rxcw & E1000_RXCW_SYNCH) &&
1656                                     (rxcw & E1000_RXCW_C))
1657                                         continue;
1658
1659                                 if (rxcw & E1000_RXCW_IV) {
1660                                         mac->serdes_has_link = false;
1661                                         mac->serdes_link_state =
1662                                             e1000_serdes_link_down;
1663                                         e_dbg("ANYSTATE  -> DOWN\n");
1664                                         break;
1665                                 }
1666                         }
1667
1668                         if (i == AN_RETRY_COUNT) {
1669                                 txcw = er32(TXCW);
1670                                 txcw |= E1000_TXCW_ANE;
1671                                 ew32(TXCW, txcw);
1672                                 mac->serdes_link_state =
1673                                     e1000_serdes_link_autoneg_progress;
1674                                 mac->serdes_has_link = false;
1675                                 e_dbg("ANYSTATE  -> AN_PROG\n");
1676                         }
1677                 }
1678         }
1679
1680         return ret_val;
1681 }
1682
1683 /**
1684  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1685  *  @hw: pointer to the HW structure
1686  *  @data: pointer to the NVM (EEPROM)
1687  *
1688  *  Read the EEPROM for the current default LED configuration.  If the
1689  *  LED configuration is not valid, set to a valid LED configuration.
1690  **/
1691 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1692 {
1693         s32 ret_val;
1694
1695         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1696         if (ret_val) {
1697                 e_dbg("NVM Read Error\n");
1698                 return ret_val;
1699         }
1700
1701         switch (hw->mac.type) {
1702         case e1000_82573:
1703         case e1000_82574:
1704         case e1000_82583:
1705                 if (*data == ID_LED_RESERVED_F746)
1706                         *data = ID_LED_DEFAULT_82573;
1707                 break;
1708         default:
1709                 if (*data == ID_LED_RESERVED_0000 ||
1710                     *data == ID_LED_RESERVED_FFFF)
1711                         *data = ID_LED_DEFAULT;
1712                 break;
1713         }
1714
1715         return 0;
1716 }
1717
1718 /**
1719  *  e1000e_get_laa_state_82571 - Get locally administered address state
1720  *  @hw: pointer to the HW structure
1721  *
1722  *  Retrieve and return the current locally administered address state.
1723  **/
1724 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1725 {
1726         if (hw->mac.type != e1000_82571)
1727                 return false;
1728
1729         return hw->dev_spec.e82571.laa_is_present;
1730 }
1731
1732 /**
1733  *  e1000e_set_laa_state_82571 - Set locally administered address state
1734  *  @hw: pointer to the HW structure
1735  *  @state: enable/disable locally administered address
1736  *
1737  *  Enable/Disable the current locally administered address state.
1738  **/
1739 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1740 {
1741         if (hw->mac.type != e1000_82571)
1742                 return;
1743
1744         hw->dev_spec.e82571.laa_is_present = state;
1745
1746         /* If workaround is activated... */
1747         if (state)
1748                 /* Hold a copy of the LAA in RAR[14] This is done so that
1749                  * between the time RAR[0] gets clobbered and the time it
1750                  * gets fixed, the actual LAA is in one of the RARs and no
1751                  * incoming packets directed to this port are dropped.
1752                  * Eventually the LAA will be in RAR[0] and RAR[14].
1753                  */
1754                 hw->mac.ops.rar_set(hw, hw->mac.addr,
1755                                     hw->mac.rar_entry_count - 1);
1756 }
1757
1758 /**
1759  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1760  *  @hw: pointer to the HW structure
1761  *
1762  *  Verifies that the EEPROM has completed the update.  After updating the
1763  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1764  *  the checksum fix is not implemented, we need to set the bit and update
1765  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1766  *  we need to return bad checksum.
1767  **/
1768 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1769 {
1770         struct e1000_nvm_info *nvm = &hw->nvm;
1771         s32 ret_val;
1772         u16 data;
1773
1774         if (nvm->type != e1000_nvm_flash_hw)
1775                 return 0;
1776
1777         /* Check bit 4 of word 10h.  If it is 0, firmware is done updating
1778          * 10h-12h.  Checksum may need to be fixed.
1779          */
1780         ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1781         if (ret_val)
1782                 return ret_val;
1783
1784         if (!(data & 0x10)) {
1785                 /* Read 0x23 and check bit 15.  This bit is a 1
1786                  * when the checksum has already been fixed.  If
1787                  * the checksum is still wrong and this bit is a
1788                  * 1, we need to return bad checksum.  Otherwise,
1789                  * we need to set this bit to a 1 and update the
1790                  * checksum.
1791                  */
1792                 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1793                 if (ret_val)
1794                         return ret_val;
1795
1796                 if (!(data & 0x8000)) {
1797                         data |= 0x8000;
1798                         ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1799                         if (ret_val)
1800                                 return ret_val;
1801                         ret_val = e1000e_update_nvm_checksum(hw);
1802                 }
1803         }
1804
1805         return 0;
1806 }
1807
1808 /**
1809  *  e1000_read_mac_addr_82571 - Read device MAC address
1810  *  @hw: pointer to the HW structure
1811  **/
1812 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1813 {
1814         if (hw->mac.type == e1000_82571) {
1815                 s32 ret_val = 0;
1816
1817                 /* If there's an alternate MAC address place it in RAR0
1818                  * so that it will override the Si installed default perm
1819                  * address.
1820                  */
1821                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1822                 if (ret_val)
1823                         return ret_val;
1824         }
1825
1826         return e1000_read_mac_addr_generic(hw);
1827 }
1828
1829 /**
1830  * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1831  * @hw: pointer to the HW structure
1832  *
1833  * In the case of a PHY power down to save power, or to turn off link during a
1834  * driver unload, or wake on lan is not enabled, remove the link.
1835  **/
1836 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1837 {
1838         struct e1000_phy_info *phy = &hw->phy;
1839         struct e1000_mac_info *mac = &hw->mac;
1840
1841         if (!phy->ops.check_reset_block)
1842                 return;
1843
1844         /* If the management interface is not enabled, then power down */
1845         if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1846                 e1000_power_down_phy_copper(hw);
1847 }
1848
1849 /**
1850  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1851  *  @hw: pointer to the HW structure
1852  *
1853  *  Clears the hardware counters by reading the counter registers.
1854  **/
1855 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1856 {
1857         e1000e_clear_hw_cntrs_base(hw);
1858
1859         er32(PRC64);
1860         er32(PRC127);
1861         er32(PRC255);
1862         er32(PRC511);
1863         er32(PRC1023);
1864         er32(PRC1522);
1865         er32(PTC64);
1866         er32(PTC127);
1867         er32(PTC255);
1868         er32(PTC511);
1869         er32(PTC1023);
1870         er32(PTC1522);
1871
1872         er32(ALGNERRC);
1873         er32(RXERRC);
1874         er32(TNCRS);
1875         er32(CEXTERR);
1876         er32(TSCTC);
1877         er32(TSCTFC);
1878
1879         er32(MGTPRC);
1880         er32(MGTPDC);
1881         er32(MGTPTC);
1882
1883         er32(IAC);
1884         er32(ICRXOC);
1885
1886         er32(ICRXPTC);
1887         er32(ICRXATC);
1888         er32(ICTXPTC);
1889         er32(ICTXATC);
1890         er32(ICTXQEC);
1891         er32(ICTXQMTC);
1892         er32(ICRXDMTC);
1893 }
1894
1895 static const struct e1000_mac_operations e82571_mac_ops = {
1896         /* .check_mng_mode: mac type dependent */
1897         /* .check_for_link: media type dependent */
1898         .id_led_init            = e1000e_id_led_init_generic,
1899         .cleanup_led            = e1000e_cleanup_led_generic,
1900         .clear_hw_cntrs         = e1000_clear_hw_cntrs_82571,
1901         .get_bus_info           = e1000e_get_bus_info_pcie,
1902         .set_lan_id             = e1000_set_lan_id_multi_port_pcie,
1903         /* .get_link_up_info: media type dependent */
1904         /* .led_on: mac type dependent */
1905         .led_off                = e1000e_led_off_generic,
1906         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1907         .write_vfta             = e1000_write_vfta_generic,
1908         .clear_vfta             = e1000_clear_vfta_82571,
1909         .reset_hw               = e1000_reset_hw_82571,
1910         .init_hw                = e1000_init_hw_82571,
1911         .setup_link             = e1000_setup_link_82571,
1912         /* .setup_physical_interface: media type dependent */
1913         .setup_led              = e1000e_setup_led_generic,
1914         .config_collision_dist  = e1000e_config_collision_dist_generic,
1915         .read_mac_addr          = e1000_read_mac_addr_82571,
1916         .rar_set                = e1000e_rar_set_generic,
1917 };
1918
1919 static const struct e1000_phy_operations e82_phy_ops_igp = {
1920         .acquire                = e1000_get_hw_semaphore_82571,
1921         .check_polarity         = e1000_check_polarity_igp,
1922         .check_reset_block      = e1000e_check_reset_block_generic,
1923         .commit                 = NULL,
1924         .force_speed_duplex     = e1000e_phy_force_speed_duplex_igp,
1925         .get_cfg_done           = e1000_get_cfg_done_82571,
1926         .get_cable_length       = e1000e_get_cable_length_igp_2,
1927         .get_info               = e1000e_get_phy_info_igp,
1928         .read_reg               = e1000e_read_phy_reg_igp,
1929         .release                = e1000_put_hw_semaphore_82571,
1930         .reset                  = e1000e_phy_hw_reset_generic,
1931         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1932         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1933         .write_reg              = e1000e_write_phy_reg_igp,
1934         .cfg_on_link_up         = NULL,
1935 };
1936
1937 static const struct e1000_phy_operations e82_phy_ops_m88 = {
1938         .acquire                = e1000_get_hw_semaphore_82571,
1939         .check_polarity         = e1000_check_polarity_m88,
1940         .check_reset_block      = e1000e_check_reset_block_generic,
1941         .commit                 = e1000e_phy_sw_reset,
1942         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1943         .get_cfg_done           = e1000e_get_cfg_done,
1944         .get_cable_length       = e1000e_get_cable_length_m88,
1945         .get_info               = e1000e_get_phy_info_m88,
1946         .read_reg               = e1000e_read_phy_reg_m88,
1947         .release                = e1000_put_hw_semaphore_82571,
1948         .reset                  = e1000e_phy_hw_reset_generic,
1949         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1950         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1951         .write_reg              = e1000e_write_phy_reg_m88,
1952         .cfg_on_link_up         = NULL,
1953 };
1954
1955 static const struct e1000_phy_operations e82_phy_ops_bm = {
1956         .acquire                = e1000_get_hw_semaphore_82571,
1957         .check_polarity         = e1000_check_polarity_m88,
1958         .check_reset_block      = e1000e_check_reset_block_generic,
1959         .commit                 = e1000e_phy_sw_reset,
1960         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1961         .get_cfg_done           = e1000e_get_cfg_done,
1962         .get_cable_length       = e1000e_get_cable_length_m88,
1963         .get_info               = e1000e_get_phy_info_m88,
1964         .read_reg               = e1000e_read_phy_reg_bm2,
1965         .release                = e1000_put_hw_semaphore_82571,
1966         .reset                  = e1000e_phy_hw_reset_generic,
1967         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1968         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1969         .write_reg              = e1000e_write_phy_reg_bm2,
1970         .cfg_on_link_up         = NULL,
1971 };
1972
1973 static const struct e1000_nvm_operations e82571_nvm_ops = {
1974         .acquire                = e1000_acquire_nvm_82571,
1975         .read                   = e1000e_read_nvm_eerd,
1976         .release                = e1000_release_nvm_82571,
1977         .reload                 = e1000e_reload_nvm_generic,
1978         .update                 = e1000_update_nvm_checksum_82571,
1979         .valid_led_default      = e1000_valid_led_default_82571,
1980         .validate               = e1000_validate_nvm_checksum_82571,
1981         .write                  = e1000_write_nvm_82571,
1982 };
1983
1984 const struct e1000_info e1000_82571_info = {
1985         .mac                    = e1000_82571,
1986         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1987                                   | FLAG_HAS_JUMBO_FRAMES
1988                                   | FLAG_HAS_WOL
1989                                   | FLAG_APME_IN_CTRL3
1990                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1991                                   | FLAG_HAS_SMART_POWER_DOWN
1992                                   | FLAG_RESET_OVERWRITES_LAA /* errata */
1993                                   | FLAG_TARC_SPEED_MODE_BIT /* errata */
1994                                   | FLAG_APME_CHECK_PORT_B,
1995         .flags2                 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
1996                                   | FLAG2_DMA_BURST,
1997         .pba                    = 38,
1998         .max_hw_frame_size      = DEFAULT_JUMBO,
1999         .get_variants           = e1000_get_variants_82571,
2000         .mac_ops                = &e82571_mac_ops,
2001         .phy_ops                = &e82_phy_ops_igp,
2002         .nvm_ops                = &e82571_nvm_ops,
2003 };
2004
2005 const struct e1000_info e1000_82572_info = {
2006         .mac                    = e1000_82572,
2007         .flags                  = FLAG_HAS_HW_VLAN_FILTER
2008                                   | FLAG_HAS_JUMBO_FRAMES
2009                                   | FLAG_HAS_WOL
2010                                   | FLAG_APME_IN_CTRL3
2011                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2012                                   | FLAG_TARC_SPEED_MODE_BIT, /* errata */
2013         .flags2                 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */
2014                                   | FLAG2_DMA_BURST,
2015         .pba                    = 38,
2016         .max_hw_frame_size      = DEFAULT_JUMBO,
2017         .get_variants           = e1000_get_variants_82571,
2018         .mac_ops                = &e82571_mac_ops,
2019         .phy_ops                = &e82_phy_ops_igp,
2020         .nvm_ops                = &e82571_nvm_ops,
2021 };
2022
2023 const struct e1000_info e1000_82573_info = {
2024         .mac                    = e1000_82573,
2025         .flags                  = FLAG_HAS_HW_VLAN_FILTER
2026                                   | FLAG_HAS_WOL
2027                                   | FLAG_APME_IN_CTRL3
2028                                   | FLAG_HAS_SMART_POWER_DOWN
2029                                   | FLAG_HAS_AMT
2030                                   | FLAG_HAS_SWSM_ON_LOAD,
2031         .flags2                 = FLAG2_DISABLE_ASPM_L1
2032                                   | FLAG2_DISABLE_ASPM_L0S,
2033         .pba                    = 20,
2034         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
2035         .get_variants           = e1000_get_variants_82571,
2036         .mac_ops                = &e82571_mac_ops,
2037         .phy_ops                = &e82_phy_ops_m88,
2038         .nvm_ops                = &e82571_nvm_ops,
2039 };
2040
2041 const struct e1000_info e1000_82574_info = {
2042         .mac                    = e1000_82574,
2043         .flags                  = FLAG_HAS_HW_VLAN_FILTER
2044                                   | FLAG_HAS_MSIX
2045                                   | FLAG_HAS_JUMBO_FRAMES
2046                                   | FLAG_HAS_WOL
2047                                   | FLAG_APME_IN_CTRL3
2048                                   | FLAG_HAS_SMART_POWER_DOWN
2049                                   | FLAG_HAS_AMT
2050                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
2051         .flags2                  = FLAG2_CHECK_PHY_HANG
2052                                   | FLAG2_DISABLE_ASPM_L0S
2053                                   | FLAG2_DISABLE_ASPM_L1
2054                                   | FLAG2_NO_DISABLE_RX
2055                                   | FLAG2_DMA_BURST,
2056         .pba                    = 32,
2057         .max_hw_frame_size      = DEFAULT_JUMBO,
2058         .get_variants           = e1000_get_variants_82571,
2059         .mac_ops                = &e82571_mac_ops,
2060         .phy_ops                = &e82_phy_ops_bm,
2061         .nvm_ops                = &e82571_nvm_ops,
2062 };
2063
2064 const struct e1000_info e1000_82583_info = {
2065         .mac                    = e1000_82583,
2066         .flags                  = FLAG_HAS_HW_VLAN_FILTER
2067                                   | FLAG_HAS_WOL
2068                                   | FLAG_APME_IN_CTRL3
2069                                   | FLAG_HAS_SMART_POWER_DOWN
2070                                   | FLAG_HAS_AMT
2071                                   | FLAG_HAS_JUMBO_FRAMES
2072                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
2073         .flags2                 = FLAG2_DISABLE_ASPM_L0S
2074                                   | FLAG2_NO_DISABLE_RX,
2075         .pba                    = 32,
2076         .max_hw_frame_size      = DEFAULT_JUMBO,
2077         .get_variants           = e1000_get_variants_82571,
2078         .mac_ops                = &e82571_mac_ops,
2079         .phy_ops                = &e82_phy_ops_bm,
2080         .nvm_ops                = &e82571_nvm_ops,
2081 };
2082