drivers/net/ethernet/icplus/ipg.c

   1 /*
   2  * ipg.c: Device Driver for the IP1000 Gigabit Ethernet Adapter
   3  *
   4  * Copyright (C) 2003, 2007  IC Plus Corp
   5  *
   6  * Original Author:
   7  *
   8  *   Craig Rich
   9  *   Sundance Technology, Inc.
  10  *   www.sundanceti.com
  11  *   craig_rich@sundanceti.com
  12  *
  13  * Current Maintainer:
  14  *
  15  *   Sorbica Shieh.
  16  *   http://www.icplus.com.tw
  17  *   sorbica@icplus.com.tw
  18  *
  19  *   Jesse Huang
  20  *   http://www.icplus.com.tw
  21  *   jesse@icplus.com.tw
  22  */
  23
  24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  25
  26 #include <linux/crc32.h>
  27 #include <linux/ethtool.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/gfp.h>
  30 #include <linux/mii.h>
  31 #include <linux/mutex.h>
  32
  33 #include <asm/div64.h>
  34
  35 #define IPG_RX_RING_BYTES       (sizeof(struct ipg_rx) * IPG_RFDLIST_LENGTH)
  36 #define IPG_TX_RING_BYTES       (sizeof(struct ipg_tx) * IPG_TFDLIST_LENGTH)
  37 #define IPG_RESET_MASK \
  38         (IPG_AC_GLOBAL_RESET | IPG_AC_RX_RESET | IPG_AC_TX_RESET | \
  39          IPG_AC_DMA | IPG_AC_FIFO | IPG_AC_NETWORK | IPG_AC_HOST | \
  40          IPG_AC_AUTO_INIT)
  41
  42 #define ipg_w32(val32, reg)     iowrite32((val32), ioaddr + (reg))
  43 #define ipg_w16(val16, reg)     iowrite16((val16), ioaddr + (reg))
  44 #define ipg_w8(val8, reg)       iowrite8((val8), ioaddr + (reg))
  45
  46 #define ipg_r32(reg)            ioread32(ioaddr + (reg))
  47 #define ipg_r16(reg)            ioread16(ioaddr + (reg))
  48 #define ipg_r8(reg)             ioread8(ioaddr + (reg))
  49
  50 enum {
  51         netdev_io_size = 128
  52 };
  53
  54 #include "ipg.h"
  55 #define DRV_NAME        "ipg"
  56
  57 MODULE_AUTHOR("IC Plus Corp. 2003");
  58 MODULE_DESCRIPTION("IC Plus IP1000 Gigabit Ethernet Adapter Linux Driver");
  59 MODULE_LICENSE("GPL");
  60
  61 /*
  62  * Defaults
  63  */
  64 #define IPG_MAX_RXFRAME_SIZE    0x0600
  65 #define IPG_RXFRAG_SIZE         0x0600
  66 #define IPG_RXSUPPORT_SIZE      0x0600
  67 #define IPG_IS_JUMBO            false
  68
  69 /*
  70  * Variable record -- index by leading revision/length
  71  * Revision/Length(=N*4), Address1, Data1, Address2, Data2,...,AddressN,DataN
  72  */
  73 static const unsigned short DefaultPhyParam[] = {
  74         /* 11/12/03 IP1000A v1-3 rev=0x40 */
  75         /*--------------------------------------------------------------------------
  76         (0x4000|(15*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 22, 0x85bd, 24, 0xfff2,
  77                                  27, 0x0c10, 28, 0x0c10, 29, 0x2c10, 31, 0x0003, 23, 0x92f6,
  78                                  31, 0x0000, 23, 0x003d, 30, 0x00de, 20, 0x20e7,  9, 0x0700,
  79           --------------------------------------------------------------------------*/
  80         /* 12/17/03 IP1000A v1-4 rev=0x40 */
  81         (0x4000 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
  82             0x0000,
  83         30, 0x005e, 9, 0x0700,
  84         /* 01/09/04 IP1000A v1-5 rev=0x41 */
  85         (0x4100 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
  86             0x0000,
  87         30, 0x005e, 9, 0x0700,
  88         0x0000
  89 };
  90
  91 static const char * const ipg_brand_name[] = {
  92         "IC PLUS IP1000 1000/100/10 based NIC",
  93         "Sundance Technology ST2021 based NIC",
  94         "Tamarack Microelectronics TC9020/9021 based NIC",
  95         "D-Link NIC IP1000A"
  96 };
  97
  98 static DEFINE_PCI_DEVICE_TABLE(ipg_pci_tbl) = {
  99         { PCI_VDEVICE(SUNDANCE, 0x1023), 0 },
 100         { PCI_VDEVICE(SUNDANCE, 0x2021), 1 },
 101         { PCI_VDEVICE(DLINK,    0x9021), 2 },
 102         { PCI_VDEVICE(DLINK,    0x4020), 3 },
 103         { 0, }
 104 };
 105
 106 MODULE_DEVICE_TABLE(pci, ipg_pci_tbl);
 107
 108 static inline void __iomem *ipg_ioaddr(struct net_device *dev)
 109 {
 110         struct ipg_nic_private *sp = netdev_priv(dev);
 111         return sp->ioaddr;
 112 }
 113
 114 #ifdef IPG_DEBUG
 115 static void ipg_dump_rfdlist(struct net_device *dev)
 116 {
 117         struct ipg_nic_private *sp = netdev_priv(dev);
 118         void __iomem *ioaddr = sp->ioaddr;
 119         unsigned int i;
 120         u32 offset;
 121
 122         IPG_DEBUG_MSG("_dump_rfdlist\n");
 123
 124         netdev_info(dev, "rx_current = %02x\n", sp->rx_current);
 125         netdev_info(dev, "rx_dirty   = %02x\n", sp->rx_dirty);
 126         netdev_info(dev, "RFDList start address = %016lx\n",
 127                     (unsigned long)sp->rxd_map);
 128         netdev_info(dev, "RFDListPtr register   = %08x%08x\n",
 129                     ipg_r32(IPG_RFDLISTPTR1), ipg_r32(IPG_RFDLISTPTR0));
 130
 131         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
 132                 offset = (u32) &sp->rxd[i].next_desc - (u32) sp->rxd;
 133                 netdev_info(dev, "%02x %04x RFDNextPtr = %016lx\n",
 134                             i, offset, (unsigned long)sp->rxd[i].next_desc);
 135                 offset = (u32) &sp->rxd[i].rfs - (u32) sp->rxd;
 136                 netdev_info(dev, "%02x %04x RFS        = %016lx\n",
 137                             i, offset, (unsigned long)sp->rxd[i].rfs);
 138                 offset = (u32) &sp->rxd[i].frag_info - (u32) sp->rxd;
 139                 netdev_info(dev, "%02x %04x frag_info   = %016lx\n",
 140                             i, offset, (unsigned long)sp->rxd[i].frag_info);
 141         }
 142 }
 143
 144 static void ipg_dump_tfdlist(struct net_device *dev)
 145 {
 146         struct ipg_nic_private *sp = netdev_priv(dev);
 147         void __iomem *ioaddr = sp->ioaddr;
 148         unsigned int i;
 149         u32 offset;
 150
 151         IPG_DEBUG_MSG("_dump_tfdlist\n");
 152
 153         netdev_info(dev, "tx_current         = %02x\n", sp->tx_current);
 154         netdev_info(dev, "tx_dirty = %02x\n", sp->tx_dirty);
 155         netdev_info(dev, "TFDList start address = %016lx\n",
 156                     (unsigned long) sp->txd_map);
 157         netdev_info(dev, "TFDListPtr register   = %08x%08x\n",
 158                     ipg_r32(IPG_TFDLISTPTR1), ipg_r32(IPG_TFDLISTPTR0));
 159
 160         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
 161                 offset = (u32) &sp->txd[i].next_desc - (u32) sp->txd;
 162                 netdev_info(dev, "%02x %04x TFDNextPtr = %016lx\n",
 163                             i, offset, (unsigned long)sp->txd[i].next_desc);
 164
 165                 offset = (u32) &sp->txd[i].tfc - (u32) sp->txd;
 166                 netdev_info(dev, "%02x %04x TFC        = %016lx\n",
 167                             i, offset, (unsigned long) sp->txd[i].tfc);
 168                 offset = (u32) &sp->txd[i].frag_info - (u32) sp->txd;
 169                 netdev_info(dev, "%02x %04x frag_info   = %016lx\n",
 170                             i, offset, (unsigned long) sp->txd[i].frag_info);
 171         }
 172 }
 173 #endif
 174
 175 static void ipg_write_phy_ctl(void __iomem *ioaddr, u8 data)
 176 {
 177         ipg_w8(IPG_PC_RSVD_MASK & data, PHY_CTRL);
 178         ndelay(IPG_PC_PHYCTRLWAIT_NS);
 179 }
 180
 181 static void ipg_drive_phy_ctl_low_high(void __iomem *ioaddr, u8 data)
 182 {
 183         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | data);
 184         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | data);
 185 }
 186
 187 static void send_three_state(void __iomem *ioaddr, u8 phyctrlpolarity)
 188 {
 189         phyctrlpolarity |= (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR;
 190
 191         ipg_drive_phy_ctl_low_high(ioaddr, phyctrlpolarity);
 192 }
 193
 194 static void send_end(void __iomem *ioaddr, u8 phyctrlpolarity)
 195 {
 196         ipg_w8((IPG_PC_MGMTCLK_LO | (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR |
 197                 phyctrlpolarity) & IPG_PC_RSVD_MASK, PHY_CTRL);
 198 }
 199
 200 static u16 read_phy_bit(void __iomem *ioaddr, u8 phyctrlpolarity)
 201 {
 202         u16 bit_data;
 203
 204         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | phyctrlpolarity);
 205
 206         bit_data = ((ipg_r8(PHY_CTRL) & IPG_PC_MGMTDATA) >> 1) & 1;
 207
 208         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | phyctrlpolarity);
 209
 210         return bit_data;
 211 }
 212
 213 /*
 214  * Read a register from the Physical Layer device located
 215  * on the IPG NIC, using the IPG PHYCTRL register.
 216  */
 217 static int mdio_read(struct net_device *dev, int phy_id, int phy_reg)
 218 {
 219         void __iomem *ioaddr = ipg_ioaddr(dev);
 220         /*
 221          * The GMII mangement frame structure for a read is as follows:
 222          *
 223          * |Preamble|st|op|phyad|regad|ta|      data      |idle|
 224          * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z   |
 225          *
 226          * <32 1s> = 32 consecutive logic 1 values
 227          * A = bit of Physical Layer device address (MSB first)
 228          * R = bit of register address (MSB first)
 229          * z = High impedance state
 230          * D = bit of read data (MSB first)
 231          *
 232          * Transmission order is 'Preamble' field first, bits transmitted
 233          * left to right (first to last).
 234          */
 235         struct {
 236                 u32 field;
 237                 unsigned int len;
 238         } p[] = {
 239                 { GMII_PREAMBLE,        32 },   /* Preamble */
 240                 { GMII_ST,              2  },   /* ST */
 241                 { GMII_READ,            2  },   /* OP */
 242                 { phy_id,               5  },   /* PHYAD */
 243                 { phy_reg,              5  },   /* REGAD */
 244                 { 0x0000,               2  },   /* TA */
 245                 { 0x0000,               16 },   /* DATA */
 246                 { 0x0000,               1  }    /* IDLE */
 247         };
 248         unsigned int i, j;
 249         u8 polarity, data;
 250
 251         polarity  = ipg_r8(PHY_CTRL);
 252         polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
 253
 254         /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
 255         for (j = 0; j < 5; j++) {
 256                 for (i = 0; i < p[j].len; i++) {
 257                         /* For each variable length field, the MSB must be
 258                          * transmitted first. Rotate through the field bits,
 259                          * starting with the MSB, and move each bit into the
 260                          * the 1st (2^1) bit position (this is the bit position
 261                          * corresponding to the MgmtData bit of the PhyCtrl
 262                          * register for the IPG).
 263                          *
 264                          * Example: ST = 01;
 265                          *
 266                          *          First write a '0' to bit 1 of the PhyCtrl
 267                          *          register, then write a '1' to bit 1 of the
 268                          *          PhyCtrl register.
 269                          *
 270                          * To do this, right shift the MSB of ST by the value:
 271                          * [field length - 1 - #ST bits already written]
 272                          * then left shift this result by 1.
 273                          */
 274                         data  = (p[j].field >> (p[j].len - 1 - i)) << 1;
 275                         data &= IPG_PC_MGMTDATA;
 276                         data |= polarity | IPG_PC_MGMTDIR;
 277
 278                         ipg_drive_phy_ctl_low_high(ioaddr, data);
 279                 }
 280         }
 281
 282         send_three_state(ioaddr, polarity);
 283
 284         read_phy_bit(ioaddr, polarity);
 285
 286         /*
 287          * For a read cycle, the bits for the next two fields (TA and
 288          * DATA) are driven by the PHY (the IPG reads these bits).
 289          */
 290         for (i = 0; i < p[6].len; i++) {
 291                 p[6].field |=
 292                     (read_phy_bit(ioaddr, polarity) << (p[6].len - 1 - i));
 293         }
 294
 295         send_three_state(ioaddr, polarity);
 296         send_three_state(ioaddr, polarity);
 297         send_three_state(ioaddr, polarity);
 298         send_end(ioaddr, polarity);
 299
 300         /* Return the value of the DATA field. */
 301         return p[6].field;
 302 }
 303
 304 /*
 305  * Write to a register from the Physical Layer device located
 306  * on the IPG NIC, using the IPG PHYCTRL register.
 307  */
 308 static void mdio_write(struct net_device *dev, int phy_id, int phy_reg, int val)
 309 {
 310         void __iomem *ioaddr = ipg_ioaddr(dev);
 311         /*
 312          * The GMII mangement frame structure for a read is as follows:
 313          *
 314          * |Preamble|st|op|phyad|regad|ta|      data      |idle|
 315          * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z   |
 316          *
 317          * <32 1s> = 32 consecutive logic 1 values
 318          * A = bit of Physical Layer device address (MSB first)
 319          * R = bit of register address (MSB first)
 320          * z = High impedance state
 321          * D = bit of write data (MSB first)
 322          *
 323          * Transmission order is 'Preamble' field first, bits transmitted
 324          * left to right (first to last).
 325          */
 326         struct {
 327                 u32 field;
 328                 unsigned int len;
 329         } p[] = {
 330                 { GMII_PREAMBLE,        32 },   /* Preamble */
 331                 { GMII_ST,              2  },   /* ST */
 332                 { GMII_WRITE,           2  },   /* OP */
 333                 { phy_id,               5  },   /* PHYAD */
 334                 { phy_reg,              5  },   /* REGAD */
 335                 { 0x0002,               2  },   /* TA */
 336                 { val & 0xffff,         16 },   /* DATA */
 337                 { 0x0000,               1  }    /* IDLE */
 338         };
 339         unsigned int i, j;
 340         u8 polarity, data;
 341
 342         polarity  = ipg_r8(PHY_CTRL);
 343         polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
 344
 345         /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
 346         for (j = 0; j < 7; j++) {
 347                 for (i = 0; i < p[j].len; i++) {
 348                         /* For each variable length field, the MSB must be
 349                          * transmitted first. Rotate through the field bits,
 350                          * starting with the MSB, and move each bit into the
 351                          * the 1st (2^1) bit position (this is the bit position
 352                          * corresponding to the MgmtData bit of the PhyCtrl
 353                          * register for the IPG).
 354                          *
 355                          * Example: ST = 01;
 356                          *
 357                          *          First write a '0' to bit 1 of the PhyCtrl
 358                          *          register, then write a '1' to bit 1 of the
 359                          *          PhyCtrl register.
 360                          *
 361                          * To do this, right shift the MSB of ST by the value:
 362                          * [field length - 1 - #ST bits already written]
 363                          * then left shift this result by 1.
 364                          */
 365                         data  = (p[j].field >> (p[j].len - 1 - i)) << 1;
 366                         data &= IPG_PC_MGMTDATA;
 367                         data |= polarity | IPG_PC_MGMTDIR;
 368
 369                         ipg_drive_phy_ctl_low_high(ioaddr, data);
 370                 }
 371         }
 372
 373         /* The last cycle is a tri-state, so read from the PHY. */
 374         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | polarity);
 375         ipg_r8(PHY_CTRL);
 376         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | polarity);
 377 }
 378
 379 static void ipg_set_led_mode(struct net_device *dev)
 380 {
 381         struct ipg_nic_private *sp = netdev_priv(dev);
 382         void __iomem *ioaddr = sp->ioaddr;
 383         u32 mode;
 384
 385         mode = ipg_r32(ASIC_CTRL);
 386         mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
 387
 388         if ((sp->led_mode & 0x03) > 1)
 389                 mode |= IPG_AC_LED_MODE_BIT_1;  /* Write Asic Control Bit 29 */
 390
 391         if ((sp->led_mode & 0x01) == 1)
 392                 mode |= IPG_AC_LED_MODE;        /* Write Asic Control Bit 14 */
 393
 394         if ((sp->led_mode & 0x08) == 8)
 395                 mode |= IPG_AC_LED_SPEED;       /* Write Asic Control Bit 27 */
 396
 397         ipg_w32(mode, ASIC_CTRL);
 398 }
 399
 400 static void ipg_set_phy_set(struct net_device *dev)
 401 {
 402         struct ipg_nic_private *sp = netdev_priv(dev);
 403         void __iomem *ioaddr = sp->ioaddr;
 404         int physet;
 405
 406         physet = ipg_r8(PHY_SET);
 407         physet &= ~(IPG_PS_MEM_LENB9B | IPG_PS_MEM_LEN9 | IPG_PS_NON_COMPDET);
 408         physet |= ((sp->led_mode & 0x70) >> 4);
 409         ipg_w8(physet, PHY_SET);
 410 }
 411
 412 static int ipg_reset(struct net_device *dev, u32 resetflags)
 413 {
 414         /* Assert functional resets via the IPG AsicCtrl
 415          * register as specified by the 'resetflags' input
 416          * parameter.
 417          */
 418         void __iomem *ioaddr = ipg_ioaddr(dev);
 419         unsigned int timeout_count = 0;
 420
 421         IPG_DEBUG_MSG("_reset\n");
 422
 423         ipg_w32(ipg_r32(ASIC_CTRL) | resetflags, ASIC_CTRL);
 424
 425         /* Delay added to account for problem with 10Mbps reset. */
 426         mdelay(IPG_AC_RESETWAIT);
 427
 428         while (IPG_AC_RESET_BUSY & ipg_r32(ASIC_CTRL)) {
 429                 mdelay(IPG_AC_RESETWAIT);
 430                 if (++timeout_count > IPG_AC_RESET_TIMEOUT)
 431                         return -ETIME;
 432         }
 433         /* Set LED Mode in Asic Control */
 434         ipg_set_led_mode(dev);
 435
 436         /* Set PHYSet Register Value */
 437         ipg_set_phy_set(dev);
 438         return 0;
 439 }
 440
 441 /* Find the GMII PHY address. */
 442 static int ipg_find_phyaddr(struct net_device *dev)
 443 {
 444         unsigned int phyaddr, i;
 445
 446         for (i = 0; i < 32; i++) {
 447                 u32 status;
 448
 449                 /* Search for the correct PHY address among 32 possible. */
 450                 phyaddr = (IPG_NIC_PHY_ADDRESS + i) % 32;
 451
 452                 /* 10/22/03 Grace change verify from GMII_PHY_STATUS to
 453                    GMII_PHY_ID1
 454                  */
 455
 456                 status = mdio_read(dev, phyaddr, MII_BMSR);
 457
 458                 if ((status != 0xFFFF) && (status != 0))
 459                         return phyaddr;
 460         }
 461
 462         return 0x1f;
 463 }
 464
 465 /*
 466  * Configure IPG based on result of IEEE 802.3 PHY
 467  * auto-negotiation.
 468  */
 469 static int ipg_config_autoneg(struct net_device *dev)
 470 {
 471         struct ipg_nic_private *sp = netdev_priv(dev);
 472         void __iomem *ioaddr = sp->ioaddr;
 473         unsigned int txflowcontrol;
 474         unsigned int rxflowcontrol;
 475         unsigned int fullduplex;
 476         u32 mac_ctrl_val;
 477         u32 asicctrl;
 478         u8 phyctrl;
 479         const char *speed;
 480         const char *duplex;
 481         const char *tx_desc;
 482         const char *rx_desc;
 483
 484         IPG_DEBUG_MSG("_config_autoneg\n");
 485
 486         asicctrl = ipg_r32(ASIC_CTRL);
 487         phyctrl = ipg_r8(PHY_CTRL);
 488         mac_ctrl_val = ipg_r32(MAC_CTRL);
 489
 490         /* Set flags for use in resolving auto-negotiation, assuming
 491          * non-1000Mbps, half duplex, no flow control.
 492          */
 493         fullduplex = 0;
 494         txflowcontrol = 0;
 495         rxflowcontrol = 0;
 496
 497         /* To accommodate a problem in 10Mbps operation,
 498          * set a global flag if PHY running in 10Mbps mode.
 499          */
 500         sp->tenmbpsmode = 0;
 501
 502         /* Determine actual speed of operation. */
 503         switch (phyctrl & IPG_PC_LINK_SPEED) {
 504         case IPG_PC_LINK_SPEED_10MBPS:
 505                 speed = "10Mbps";
 506                 sp->tenmbpsmode = 1;
 507                 break;
 508         case IPG_PC_LINK_SPEED_100MBPS:
 509                 speed = "100Mbps";
 510                 break;
 511         case IPG_PC_LINK_SPEED_1000MBPS:
 512                 speed = "1000Mbps";
 513                 break;
 514         default:
 515                 speed = "undefined!";
 516                 return 0;
 517         }
 518
 519         netdev_info(dev, "Link speed = %s\n", speed);
 520         if (sp->tenmbpsmode == 1)
 521                 netdev_info(dev, "10Mbps operational mode enabled\n");
 522
 523         if (phyctrl & IPG_PC_DUPLEX_STATUS) {
 524                 fullduplex = 1;
 525                 txflowcontrol = 1;
 526                 rxflowcontrol = 1;
 527         }
 528
 529         /* Configure full duplex, and flow control. */
 530         if (fullduplex == 1) {
 531
 532                 /* Configure IPG for full duplex operation. */
 533
 534                 duplex = "full";
 535
 536                 mac_ctrl_val |= IPG_MC_DUPLEX_SELECT_FD;
 537
 538                 if (txflowcontrol == 1) {
 539                         tx_desc  = "";
 540                         mac_ctrl_val |= IPG_MC_TX_FLOW_CONTROL_ENABLE;
 541                 } else {
 542                         tx_desc = "no ";
 543                         mac_ctrl_val &= ~IPG_MC_TX_FLOW_CONTROL_ENABLE;
 544                 }
 545
 546                 if (rxflowcontrol == 1) {
 547                         rx_desc = "";
 548                         mac_ctrl_val |= IPG_MC_RX_FLOW_CONTROL_ENABLE;
 549                 } else {
 550                         rx_desc = "no ";
 551                         mac_ctrl_val &= ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
 552                 }
 553         } else {
 554                 duplex = "half";
 555                 tx_desc = "no ";
 556                 rx_desc = "no ";
 557                 mac_ctrl_val &= (~IPG_MC_DUPLEX_SELECT_FD &
 558                                  ~IPG_MC_TX_FLOW_CONTROL_ENABLE &
 559                                  ~IPG_MC_RX_FLOW_CONTROL_ENABLE);
 560         }
 561
 562         netdev_info(dev, "setting %s duplex, %sTX, %sRX flow control\n",
 563                     duplex, tx_desc, rx_desc);
 564         ipg_w32(mac_ctrl_val, MAC_CTRL);
 565
 566         return 0;
 567 }
 568
 569 /* Determine and configure multicast operation and set
 570  * receive mode for IPG.
 571  */
 572 static void ipg_nic_set_multicast_list(struct net_device *dev)
 573 {
 574         void __iomem *ioaddr = ipg_ioaddr(dev);
 575         struct netdev_hw_addr *ha;
 576         unsigned int hashindex;
 577         u32 hashtable[2];
 578         u8 receivemode;
 579
 580         IPG_DEBUG_MSG("_nic_set_multicast_list\n");
 581
 582         receivemode = IPG_RM_RECEIVEUNICAST | IPG_RM_RECEIVEBROADCAST;
 583
 584         if (dev->flags & IFF_PROMISC) {
 585                 /* NIC to be configured in promiscuous mode. */
 586                 receivemode = IPG_RM_RECEIVEALLFRAMES;
 587         } else if ((dev->flags & IFF_ALLMULTI) ||
 588                    ((dev->flags & IFF_MULTICAST) &&
 589                     (netdev_mc_count(dev) > IPG_MULTICAST_HASHTABLE_SIZE))) {
 590                 /* NIC to be configured to receive all multicast
 591                  * frames. */
 592                 receivemode |= IPG_RM_RECEIVEMULTICAST;
 593         } else if ((dev->flags & IFF_MULTICAST) && !netdev_mc_empty(dev)) {
 594                 /* NIC to be configured to receive selected
 595                  * multicast addresses. */
 596                 receivemode |= IPG_RM_RECEIVEMULTICASTHASH;
 597         }
 598
 599         /* Calculate the bits to set for the 64 bit, IPG HASHTABLE.
 600          * The IPG applies a cyclic-redundancy-check (the same CRC
 601          * used to calculate the frame data FCS) to the destination
 602          * address all incoming multicast frames whose destination
 603          * address has the multicast bit set. The least significant
 604          * 6 bits of the CRC result are used as an addressing index
 605          * into the hash table. If the value of the bit addressed by
 606          * this index is a 1, the frame is passed to the host system.
 607          */
 608
 609         /* Clear hashtable. */
 610         hashtable[0] = 0x00000000;
 611         hashtable[1] = 0x00000000;
 612
 613         /* Cycle through all multicast addresses to filter. */
 614         netdev_for_each_mc_addr(ha, dev) {
 615                 /* Calculate CRC result for each multicast address. */
 616                 hashindex = crc32_le(0xffffffff, ha->addr,
 617                                      ETH_ALEN);
 618
 619                 /* Use only the least significant 6 bits. */
 620                 hashindex = hashindex & 0x3F;
 621
 622                 /* Within "hashtable", set bit number "hashindex"
 623                  * to a logic 1.
 624                  */
 625                 set_bit(hashindex, (void *)hashtable);
 626         }
 627
 628         /* Write the value of the hashtable, to the 4, 16 bit
 629          * HASHTABLE IPG registers.
 630          */
 631         ipg_w32(hashtable[0], HASHTABLE_0);
 632         ipg_w32(hashtable[1], HASHTABLE_1);
 633
 634         ipg_w8(IPG_RM_RSVD_MASK & receivemode, RECEIVE_MODE);
 635
 636         IPG_DEBUG_MSG("ReceiveMode = %x\n", ipg_r8(RECEIVE_MODE));
 637 }
 638
 639 static int ipg_io_config(struct net_device *dev)
 640 {
 641         struct ipg_nic_private *sp = netdev_priv(dev);
 642         void __iomem *ioaddr = ipg_ioaddr(dev);
 643         u32 origmacctrl;
 644         u32 restoremacctrl;
 645
 646         IPG_DEBUG_MSG("_io_config\n");
 647
 648         origmacctrl = ipg_r32(MAC_CTRL);
 649
 650         restoremacctrl = origmacctrl | IPG_MC_STATISTICS_ENABLE;
 651
 652         /* Based on compilation option, determine if FCS is to be
 653          * stripped on receive frames by IPG.
 654          */
 655         if (!IPG_STRIP_FCS_ON_RX)
 656                 restoremacctrl |= IPG_MC_RCV_FCS;
 657
 658         /* Determine if transmitter and/or receiver are
 659          * enabled so we may restore MACCTRL correctly.
 660          */
 661         if (origmacctrl & IPG_MC_TX_ENABLED)
 662                 restoremacctrl |= IPG_MC_TX_ENABLE;
 663
 664         if (origmacctrl & IPG_MC_RX_ENABLED)
 665                 restoremacctrl |= IPG_MC_RX_ENABLE;
 666
 667         /* Transmitter and receiver must be disabled before setting
 668          * IFSSelect.
 669          */
 670         ipg_w32((origmacctrl & (IPG_MC_RX_DISABLE | IPG_MC_TX_DISABLE)) &
 671                 IPG_MC_RSVD_MASK, MAC_CTRL);
 672
 673         /* Now that transmitter and receiver are disabled, write
 674          * to IFSSelect.
 675          */
 676         ipg_w32((origmacctrl & IPG_MC_IFS_96BIT) & IPG_MC_RSVD_MASK, MAC_CTRL);
 677
 678         /* Set RECEIVEMODE register. */
 679         ipg_nic_set_multicast_list(dev);
 680
 681         ipg_w16(sp->max_rxframe_size, MAX_FRAME_SIZE);
 682
 683         ipg_w8(IPG_RXDMAPOLLPERIOD_VALUE,   RX_DMA_POLL_PERIOD);
 684         ipg_w8(IPG_RXDMAURGENTTHRESH_VALUE, RX_DMA_URGENT_THRESH);
 685         ipg_w8(IPG_RXDMABURSTTHRESH_VALUE,  RX_DMA_BURST_THRESH);
 686         ipg_w8(IPG_TXDMAPOLLPERIOD_VALUE,   TX_DMA_POLL_PERIOD);
 687         ipg_w8(IPG_TXDMAURGENTTHRESH_VALUE, TX_DMA_URGENT_THRESH);
 688         ipg_w8(IPG_TXDMABURSTTHRESH_VALUE,  TX_DMA_BURST_THRESH);
 689         ipg_w16((IPG_IE_HOST_ERROR | IPG_IE_TX_DMA_COMPLETE |
 690                  IPG_IE_TX_COMPLETE | IPG_IE_INT_REQUESTED |
 691                  IPG_IE_UPDATE_STATS | IPG_IE_LINK_EVENT |
 692                  IPG_IE_RX_DMA_COMPLETE | IPG_IE_RX_DMA_PRIORITY), INT_ENABLE);
 693         ipg_w16(IPG_FLOWONTHRESH_VALUE,  FLOW_ON_THRESH);
 694         ipg_w16(IPG_FLOWOFFTHRESH_VALUE, FLOW_OFF_THRESH);
 695
 696         /* IPG multi-frag frame bug workaround.
 697          * Per silicon revision B3 eratta.
 698          */
 699         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0200, DEBUG_CTRL);
 700
 701         /* IPG TX poll now bug workaround.
 702          * Per silicon revision B3 eratta.
 703          */
 704         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0010, DEBUG_CTRL);
 705
 706         /* IPG RX poll now bug workaround.
 707          * Per silicon revision B3 eratta.
 708          */
 709         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0020, DEBUG_CTRL);
 710
 711         /* Now restore MACCTRL to original setting. */
 712         ipg_w32(IPG_MC_RSVD_MASK & restoremacctrl, MAC_CTRL);
 713
 714         /* Disable unused RMON statistics. */
 715         ipg_w32(IPG_RZ_ALL, RMON_STATISTICS_MASK);
 716
 717         /* Disable unused MIB statistics. */
 718         ipg_w32(IPG_SM_MACCONTROLFRAMESXMTD | IPG_SM_MACCONTROLFRAMESRCVD |
 719                 IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK | IPG_SM_TXJUMBOFRAMES |
 720                 IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK | IPG_SM_RXJUMBOFRAMES |
 721                 IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK |
 722                 IPG_SM_UDPCHECKSUMERRORS | IPG_SM_TCPCHECKSUMERRORS |
 723                 IPG_SM_IPCHECKSUMERRORS, STATISTICS_MASK);
 724
 725         return 0;
 726 }
 727
 728 /*
 729  * Create a receive buffer within system memory and update
 730  * NIC private structure appropriately.
 731  */
 732 static int ipg_get_rxbuff(struct net_device *dev, int entry)
 733 {
 734         struct ipg_nic_private *sp = netdev_priv(dev);
 735         struct ipg_rx *rxfd = sp->rxd + entry;
 736         struct sk_buff *skb;
 737         u64 rxfragsize;
 738
 739         IPG_DEBUG_MSG("_get_rxbuff\n");
 740
 741         skb = netdev_alloc_skb_ip_align(dev, sp->rxsupport_size);
 742         if (!skb) {
 743                 sp->rx_buff[entry] = NULL;
 744                 return -ENOMEM;
 745         }
 746
 747         /* Associate the receive buffer with the IPG NIC. */
 748         skb->dev = dev;
 749
 750         /* Save the address of the sk_buff structure. */
 751         sp->rx_buff[entry] = skb;
 752
 753         rxfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
 754                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE));
 755
 756         /* Set the RFD fragment length. */
 757         rxfragsize = sp->rxfrag_size;
 758         rxfd->frag_info |= cpu_to_le64((rxfragsize << 48) & IPG_RFI_FRAGLEN);
 759
 760         return 0;
 761 }
 762
 763 static int init_rfdlist(struct net_device *dev)
 764 {
 765         struct ipg_nic_private *sp = netdev_priv(dev);
 766         void __iomem *ioaddr = sp->ioaddr;
 767         unsigned int i;
 768
 769         IPG_DEBUG_MSG("_init_rfdlist\n");
 770
 771         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
 772                 struct ipg_rx *rxfd = sp->rxd + i;
 773
 774                 if (sp->rx_buff[i]) {
 775                         pci_unmap_single(sp->pdev,
 776                                 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
 777                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
 778                         dev_kfree_skb_irq(sp->rx_buff[i]);
 779                         sp->rx_buff[i] = NULL;
 780                 }
 781
 782                 /* Clear out the RFS field. */
 783                 rxfd->rfs = 0x0000000000000000;
 784
 785                 if (ipg_get_rxbuff(dev, i) < 0) {
 786                         /*
 787                          * A receive buffer was not ready, break the
 788                          * RFD list here.
 789                          */
 790                         IPG_DEBUG_MSG("Cannot allocate Rx buffer\n");
 791
 792                         /* Just in case we cannot allocate a single RFD.
 793                          * Should not occur.
 794                          */
 795                         if (i == 0) {
 796                                 netdev_err(dev, "No memory available for RFD list\n");
 797                                 return -ENOMEM;
 798                         }
 799                 }
 800
 801                 rxfd->next_desc = cpu_to_le64(sp->rxd_map +
 802                         sizeof(struct ipg_rx)*(i + 1));
 803         }
 804         sp->rxd[i - 1].next_desc = cpu_to_le64(sp->rxd_map);
 805
 806         sp->rx_current = 0;
 807         sp->rx_dirty = 0;
 808
 809         /* Write the location of the RFDList to the IPG. */
 810         ipg_w32((u32) sp->rxd_map, RFD_LIST_PTR_0);
 811         ipg_w32(0x00000000, RFD_LIST_PTR_1);
 812
 813         return 0;
 814 }
 815
 816 static void init_tfdlist(struct net_device *dev)
 817 {
 818         struct ipg_nic_private *sp = netdev_priv(dev);
 819         void __iomem *ioaddr = sp->ioaddr;
 820         unsigned int i;
 821
 822         IPG_DEBUG_MSG("_init_tfdlist\n");
 823
 824         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
 825                 struct ipg_tx *txfd = sp->txd + i;
 826
 827                 txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
 828
 829                 if (sp->tx_buff[i]) {
 830                         dev_kfree_skb_irq(sp->tx_buff[i]);
 831                         sp->tx_buff[i] = NULL;
 832                 }
 833
 834                 txfd->next_desc = cpu_to_le64(sp->txd_map +
 835                         sizeof(struct ipg_tx)*(i + 1));
 836         }
 837         sp->txd[i - 1].next_desc = cpu_to_le64(sp->txd_map);
 838
 839         sp->tx_current = 0;
 840         sp->tx_dirty = 0;
 841
 842         /* Write the location of the TFDList to the IPG. */
 843         IPG_DDEBUG_MSG("Starting TFDListPtr = %08x\n",
 844                        (u32) sp->txd_map);
 845         ipg_w32((u32) sp->txd_map, TFD_LIST_PTR_0);
 846         ipg_w32(0x00000000, TFD_LIST_PTR_1);
 847
 848         sp->reset_current_tfd = 1;
 849 }
 850
 851 /*
 852  * Free all transmit buffers which have already been transferred
 853  * via DMA to the IPG.
 854  */
 855 static void ipg_nic_txfree(struct net_device *dev)
 856 {
 857         struct ipg_nic_private *sp = netdev_priv(dev);
 858         unsigned int released, pending, dirty;
 859
 860         IPG_DEBUG_MSG("_nic_txfree\n");
 861
 862         pending = sp->tx_current - sp->tx_dirty;
 863         dirty = sp->tx_dirty % IPG_TFDLIST_LENGTH;
 864
 865         for (released = 0; released < pending; released++) {
 866                 struct sk_buff *skb = sp->tx_buff[dirty];
 867                 struct ipg_tx *txfd = sp->txd + dirty;
 868
 869                 IPG_DEBUG_MSG("TFC = %016lx\n", (unsigned long) txfd->tfc);
 870
 871                 /* Look at each TFD's TFC field beginning
 872                  * at the last freed TFD up to the current TFD.
 873                  * If the TFDDone bit is set, free the associated
 874                  * buffer.
 875                  */
 876                 if (!(txfd->tfc & cpu_to_le64(IPG_TFC_TFDDONE)))
 877                         break;
 878
 879                 /* Free the transmit buffer. */
 880                 if (skb) {
 881                         pci_unmap_single(sp->pdev,
 882                                 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
 883                                 skb->len, PCI_DMA_TODEVICE);
 884
 885                         dev_kfree_skb_irq(skb);
 886
 887                         sp->tx_buff[dirty] = NULL;
 888                 }
 889                 dirty = (dirty + 1) % IPG_TFDLIST_LENGTH;
 890         }
 891
 892         sp->tx_dirty += released;
 893
 894         if (netif_queue_stopped(dev) &&
 895             (sp->tx_current != (sp->tx_dirty + IPG_TFDLIST_LENGTH))) {
 896                 netif_wake_queue(dev);
 897         }
 898 }
 899
 900 static void ipg_tx_timeout(struct net_device *dev)
 901 {
 902         struct ipg_nic_private *sp = netdev_priv(dev);
 903         void __iomem *ioaddr = sp->ioaddr;
 904
 905         ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA | IPG_AC_NETWORK |
 906                   IPG_AC_FIFO);
 907
 908         spin_lock_irq(&sp->lock);
 909
 910         /* Re-configure after DMA reset. */
 911         if (ipg_io_config(dev) < 0)
 912                 netdev_info(dev, "Error during re-configuration\n");
 913
 914         init_tfdlist(dev);
 915
 916         spin_unlock_irq(&sp->lock);
 917
 918         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) & IPG_MC_RSVD_MASK,
 919                 MAC_CTRL);
 920 }
 921
 922 /*
 923  * For TxComplete interrupts, free all transmit
 924  * buffers which have already been transferred via DMA
 925  * to the IPG.
 926  */
 927 static void ipg_nic_txcleanup(struct net_device *dev)
 928 {
 929         struct ipg_nic_private *sp = netdev_priv(dev);
 930         void __iomem *ioaddr = sp->ioaddr;
 931         unsigned int i;
 932
 933         IPG_DEBUG_MSG("_nic_txcleanup\n");
 934
 935         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
 936                 /* Reading the TXSTATUS register clears the
 937                  * TX_COMPLETE interrupt.
 938                  */
 939                 u32 txstatusdword = ipg_r32(TX_STATUS);
 940
 941                 IPG_DEBUG_MSG("TxStatus = %08x\n", txstatusdword);
 942
 943                 /* Check for Transmit errors. Error bits only valid if
 944                  * TX_COMPLETE bit in the TXSTATUS register is a 1.
 945                  */
 946                 if (!(txstatusdword & IPG_TS_TX_COMPLETE))
 947                         break;
 948
 949                 /* If in 10Mbps mode, indicate transmit is ready. */
 950                 if (sp->tenmbpsmode) {
 951                         netif_wake_queue(dev);
 952                 }
 953
 954                 /* Transmit error, increment stat counters. */
 955                 if (txstatusdword & IPG_TS_TX_ERROR) {
 956                         IPG_DEBUG_MSG("Transmit error\n");
 957                         sp->stats.tx_errors++;
 958                 }
 959
 960                 /* Late collision, re-enable transmitter. */
 961                 if (txstatusdword & IPG_TS_LATE_COLLISION) {
 962                         IPG_DEBUG_MSG("Late collision on transmit\n");
 963                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
 964                                 IPG_MC_RSVD_MASK, MAC_CTRL);
 965                 }
 966
 967                 /* Maximum collisions, re-enable transmitter. */
 968                 if (txstatusdword & IPG_TS_TX_MAX_COLL) {
 969                         IPG_DEBUG_MSG("Maximum collisions on transmit\n");
 970                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
 971                                 IPG_MC_RSVD_MASK, MAC_CTRL);
 972                 }
 973
 974                 /* Transmit underrun, reset and re-enable
 975                  * transmitter.
 976                  */
 977                 if (txstatusdword & IPG_TS_TX_UNDERRUN) {
 978                         IPG_DEBUG_MSG("Transmitter underrun\n");
 979                         sp->stats.tx_fifo_errors++;
 980                         ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA |
 981                                   IPG_AC_NETWORK | IPG_AC_FIFO);
 982
 983                         /* Re-configure after DMA reset. */
 984                         if (ipg_io_config(dev) < 0) {
 985                                 netdev_info(dev, "Error during re-configuration\n");
 986                         }
 987                         init_tfdlist(dev);
 988
 989                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
 990                                 IPG_MC_RSVD_MASK, MAC_CTRL);
 991                 }
 992         }
 993
 994         ipg_nic_txfree(dev);
 995 }
 996
 997 /* Provides statistical information about the IPG NIC. */
 998 static struct net_device_stats *ipg_nic_get_stats(struct net_device *dev)
 999 {
1000         struct ipg_nic_private *sp = netdev_priv(dev);
1001         void __iomem *ioaddr = sp->ioaddr;
1002         u16 temp1;
1003         u16 temp2;
1004
1005         IPG_DEBUG_MSG("_nic_get_stats\n");
1006
1007         /* Check to see if the NIC has been initialized via nic_open,
1008          * before trying to read statistic registers.
1009          */
1010         if (!test_bit(__LINK_STATE_START, &dev->state))
1011                 return &sp->stats;
1012
1013         sp->stats.rx_packets += ipg_r32(IPG_FRAMESRCVDOK);
1014         sp->stats.tx_packets += ipg_r32(IPG_FRAMESXMTDOK);
1015         sp->stats.rx_bytes += ipg_r32(IPG_OCTETRCVOK);
1016         sp->stats.tx_bytes += ipg_r32(IPG_OCTETXMTOK);
1017         temp1 = ipg_r16(IPG_FRAMESLOSTRXERRORS);
1018         sp->stats.rx_errors += temp1;
1019         sp->stats.rx_missed_errors += temp1;
1020         temp1 = ipg_r32(IPG_SINGLECOLFRAMES) + ipg_r32(IPG_MULTICOLFRAMES) +
1021                 ipg_r32(IPG_LATECOLLISIONS);
1022         temp2 = ipg_r16(IPG_CARRIERSENSEERRORS);
1023         sp->stats.collisions += temp1;
1024         sp->stats.tx_dropped += ipg_r16(IPG_FRAMESABORTXSCOLLS);
1025         sp->stats.tx_errors += ipg_r16(IPG_FRAMESWEXDEFERRAL) +
1026                 ipg_r32(IPG_FRAMESWDEFERREDXMT) + temp1 + temp2;
1027         sp->stats.multicast += ipg_r32(IPG_MCSTOCTETRCVDOK);
1028
1029         /* detailed tx_errors */
1030         sp->stats.tx_carrier_errors += temp2;
1031
1032         /* detailed rx_errors */
1033         sp->stats.rx_length_errors += ipg_r16(IPG_INRANGELENGTHERRORS) +
1034                 ipg_r16(IPG_FRAMETOOLONGERRRORS);
1035         sp->stats.rx_crc_errors += ipg_r16(IPG_FRAMECHECKSEQERRORS);
1036
1037         /* Unutilized IPG statistic registers. */
1038         ipg_r32(IPG_MCSTFRAMESRCVDOK);
1039
1040         return &sp->stats;
1041 }
1042
1043 /* Restore used receive buffers. */
1044 static int ipg_nic_rxrestore(struct net_device *dev)
1045 {
1046         struct ipg_nic_private *sp = netdev_priv(dev);
1047         const unsigned int curr = sp->rx_current;
1048         unsigned int dirty = sp->rx_dirty;
1049
1050         IPG_DEBUG_MSG("_nic_rxrestore\n");
1051
1052         for (dirty = sp->rx_dirty; curr - dirty > 0; dirty++) {
1053                 unsigned int entry = dirty % IPG_RFDLIST_LENGTH;
1054
1055                 /* rx_copybreak may poke hole here and there. */
1056                 if (sp->rx_buff[entry])
1057                         continue;
1058
1059                 /* Generate a new receive buffer to replace the
1060                  * current buffer (which will be released by the
1061                  * Linux system).
1062                  */
1063                 if (ipg_get_rxbuff(dev, entry) < 0) {
1064                         IPG_DEBUG_MSG("Cannot allocate new Rx buffer\n");
1065
1066                         break;
1067                 }
1068
1069                 /* Reset the RFS field. */
1070                 sp->rxd[entry].rfs = 0x0000000000000000;
1071         }
1072         sp->rx_dirty = dirty;
1073
1074         return 0;
1075 }
1076
1077 /* use jumboindex and jumbosize to control jumbo frame status
1078  * initial status is jumboindex=-1 and jumbosize=0
1079  * 1. jumboindex = -1 and jumbosize=0 : previous jumbo frame has been done.
1080  * 2. jumboindex != -1 and jumbosize != 0 : jumbo frame is not over size and receiving
1081  * 3. jumboindex = -1 and jumbosize != 0 : jumbo frame is over size, already dump
1082  *               previous receiving and need to continue dumping the current one
1083  */
1084 enum {
1085         NORMAL_PACKET,
1086         ERROR_PACKET
1087 };
1088
1089 enum {
1090         FRAME_NO_START_NO_END   = 0,
1091         FRAME_WITH_START                = 1,
1092         FRAME_WITH_END          = 10,
1093         FRAME_WITH_START_WITH_END = 11
1094 };
1095
1096 static void ipg_nic_rx_free_skb(struct net_device *dev)
1097 {
1098         struct ipg_nic_private *sp = netdev_priv(dev);
1099         unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1100
1101         if (sp->rx_buff[entry]) {
1102                 struct ipg_rx *rxfd = sp->rxd + entry;
1103
1104                 pci_unmap_single(sp->pdev,
1105                         le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1106                         sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1107                 dev_kfree_skb_irq(sp->rx_buff[entry]);
1108                 sp->rx_buff[entry] = NULL;
1109         }
1110 }
1111
1112 static int ipg_nic_rx_check_frame_type(struct net_device *dev)
1113 {
1114         struct ipg_nic_private *sp = netdev_priv(dev);
1115         struct ipg_rx *rxfd = sp->rxd + (sp->rx_current % IPG_RFDLIST_LENGTH);
1116         int type = FRAME_NO_START_NO_END;
1117
1118         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART)
1119                 type += FRAME_WITH_START;
1120         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND)
1121                 type += FRAME_WITH_END;
1122         return type;
1123 }
1124
1125 static int ipg_nic_rx_check_error(struct net_device *dev)
1126 {
1127         struct ipg_nic_private *sp = netdev_priv(dev);
1128         unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1129         struct ipg_rx *rxfd = sp->rxd + entry;
1130
1131         if (IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1132              (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1133               IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1134               IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR))) {
1135                 IPG_DEBUG_MSG("Rx error, RFS = %016lx\n",
1136                               (unsigned long) rxfd->rfs);
1137
1138                 /* Increment general receive error statistic. */
1139                 sp->stats.rx_errors++;
1140
1141                 /* Increment detailed receive error statistics. */
1142                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1143                         IPG_DEBUG_MSG("RX FIFO overrun occurred\n");
1144
1145                         sp->stats.rx_fifo_errors++;
1146                 }
1147
1148                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1149                         IPG_DEBUG_MSG("RX runt occurred\n");
1150                         sp->stats.rx_length_errors++;
1151                 }
1152
1153                 /* Do nothing for IPG_RFS_RXOVERSIZEDFRAME,
1154                  * error count handled by a IPG statistic register.
1155                  */
1156
1157                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1158                         IPG_DEBUG_MSG("RX alignment error occurred\n");
1159                         sp->stats.rx_frame_errors++;
1160                 }
1161
1162                 /* Do nothing for IPG_RFS_RXFCSERROR, error count
1163                  * handled by a IPG statistic register.
1164                  */
1165
1166                 /* Free the memory associated with the RX
1167                  * buffer since it is erroneous and we will
1168                  * not pass it to higher layer processes.
1169                  */
1170                 if (sp->rx_buff[entry]) {
1171                         pci_unmap_single(sp->pdev,
1172                                 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1173                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1174
1175                         dev_kfree_skb_irq(sp->rx_buff[entry]);
1176                         sp->rx_buff[entry] = NULL;
1177                 }
1178                 return ERROR_PACKET;
1179         }
1180         return NORMAL_PACKET;
1181 }
1182
1183 static void ipg_nic_rx_with_start_and_end(struct net_device *dev,
1184                                           struct ipg_nic_private *sp,
1185                                           struct ipg_rx *rxfd, unsigned entry)
1186 {
1187         struct ipg_jumbo *jumbo = &sp->jumbo;
1188         struct sk_buff *skb;
1189         int framelen;
1190
1191         if (jumbo->found_start) {
1192                 dev_kfree_skb_irq(jumbo->skb);
1193                 jumbo->found_start = 0;
1194                 jumbo->current_size = 0;
1195                 jumbo->skb = NULL;
1196         }
1197
1198         /* 1: found error, 0 no error */
1199         if (ipg_nic_rx_check_error(dev) != NORMAL_PACKET)
1200                 return;
1201
1202         skb = sp->rx_buff[entry];
1203         if (!skb)
1204                 return;
1205
1206         /* accept this frame and send to upper layer */
1207         framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1208         if (framelen > sp->rxfrag_size)
1209                 framelen = sp->rxfrag_size;
1210
1211         skb_put(skb, framelen);
1212         skb->protocol = eth_type_trans(skb, dev);
1213         skb_checksum_none_assert(skb);
1214         netif_rx(skb);
1215         sp->rx_buff[entry] = NULL;
1216 }
1217
1218 static void ipg_nic_rx_with_start(struct net_device *dev,
1219                                   struct ipg_nic_private *sp,
1220                                   struct ipg_rx *rxfd, unsigned entry)
1221 {
1222         struct ipg_jumbo *jumbo = &sp->jumbo;
1223         struct pci_dev *pdev = sp->pdev;
1224         struct sk_buff *skb;
1225
1226         /* 1: found error, 0 no error */
1227         if (ipg_nic_rx_check_error(dev) != NORMAL_PACKET)
1228                 return;
1229
1230         /* accept this frame and send to upper layer */
1231         skb = sp->rx_buff[entry];
1232         if (!skb)
1233                 return;
1234
1235         if (jumbo->found_start)
1236                 dev_kfree_skb_irq(jumbo->skb);
1237
1238         pci_unmap_single(pdev, le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1239                          sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1240
1241         skb_put(skb, sp->rxfrag_size);
1242
1243         jumbo->found_start = 1;
1244         jumbo->current_size = sp->rxfrag_size;
1245         jumbo->skb = skb;
1246
1247         sp->rx_buff[entry] = NULL;
1248 }
1249
1250 static void ipg_nic_rx_with_end(struct net_device *dev,
1251                                 struct ipg_nic_private *sp,
1252                                 struct ipg_rx *rxfd, unsigned entry)
1253 {
1254         struct ipg_jumbo *jumbo = &sp->jumbo;
1255
1256         /* 1: found error, 0 no error */
1257         if (ipg_nic_rx_check_error(dev) == NORMAL_PACKET) {
1258                 struct sk_buff *skb = sp->rx_buff[entry];
1259
1260                 if (!skb)
1261                         return;
1262
1263                 if (jumbo->found_start) {
1264                         int framelen, endframelen;
1265
1266                         framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1267
1268                         endframelen = framelen - jumbo->current_size;
1269                         if (framelen > sp->rxsupport_size)
1270                                 dev_kfree_skb_irq(jumbo->skb);
1271                         else {
1272                                 memcpy(skb_put(jumbo->skb, endframelen),
1273                                        skb->data, endframelen);
1274
1275                                 jumbo->skb->protocol =
1276                                     eth_type_trans(jumbo->skb, dev);
1277
1278                                 skb_checksum_none_assert(jumbo->skb);
1279                                 netif_rx(jumbo->skb);
1280                         }
1281                 }
1282
1283                 jumbo->found_start = 0;
1284                 jumbo->current_size = 0;
1285                 jumbo->skb = NULL;
1286
1287                 ipg_nic_rx_free_skb(dev);
1288         } else {
1289                 dev_kfree_skb_irq(jumbo->skb);
1290                 jumbo->found_start = 0;
1291                 jumbo->current_size = 0;
1292                 jumbo->skb = NULL;
1293         }
1294 }
1295
1296 static void ipg_nic_rx_no_start_no_end(struct net_device *dev,
1297                                        struct ipg_nic_private *sp,
1298                                        struct ipg_rx *rxfd, unsigned entry)
1299 {
1300         struct ipg_jumbo *jumbo = &sp->jumbo;
1301
1302         /* 1: found error, 0 no error */
1303         if (ipg_nic_rx_check_error(dev) == NORMAL_PACKET) {
1304                 struct sk_buff *skb = sp->rx_buff[entry];
1305
1306                 if (skb) {
1307                         if (jumbo->found_start) {
1308                                 jumbo->current_size += sp->rxfrag_size;
1309                                 if (jumbo->current_size <= sp->rxsupport_size) {
1310                                         memcpy(skb_put(jumbo->skb,
1311                                                        sp->rxfrag_size),
1312                                                skb->data, sp->rxfrag_size);
1313                                 }
1314                         }
1315                         ipg_nic_rx_free_skb(dev);
1316                 }
1317         } else {
1318                 dev_kfree_skb_irq(jumbo->skb);
1319                 jumbo->found_start = 0;
1320                 jumbo->current_size = 0;
1321                 jumbo->skb = NULL;
1322         }
1323 }
1324
1325 static int ipg_nic_rx_jumbo(struct net_device *dev)
1326 {
1327         struct ipg_nic_private *sp = netdev_priv(dev);
1328         unsigned int curr = sp->rx_current;
1329         void __iomem *ioaddr = sp->ioaddr;
1330         unsigned int i;
1331
1332         IPG_DEBUG_MSG("_nic_rx\n");
1333
1334         for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1335                 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1336                 struct ipg_rx *rxfd = sp->rxd + entry;
1337
1338                 if (!(rxfd->rfs & cpu_to_le64(IPG_RFS_RFDDONE)))
1339                         break;
1340
1341                 switch (ipg_nic_rx_check_frame_type(dev)) {
1342                 case FRAME_WITH_START_WITH_END:
1343                         ipg_nic_rx_with_start_and_end(dev, sp, rxfd, entry);
1344                         break;
1345                 case FRAME_WITH_START:
1346                         ipg_nic_rx_with_start(dev, sp, rxfd, entry);
1347                         break;
1348                 case FRAME_WITH_END:
1349                         ipg_nic_rx_with_end(dev, sp, rxfd, entry);
1350                         break;
1351                 case FRAME_NO_START_NO_END:
1352                         ipg_nic_rx_no_start_no_end(dev, sp, rxfd, entry);
1353                         break;
1354                 }
1355         }
1356
1357         sp->rx_current = curr;
1358
1359         if (i == IPG_MAXRFDPROCESS_COUNT) {
1360                 /* There are more RFDs to process, however the
1361                  * allocated amount of RFD processing time has
1362                  * expired. Assert Interrupt Requested to make
1363                  * sure we come back to process the remaining RFDs.
1364                  */
1365                 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1366         }
1367
1368         ipg_nic_rxrestore(dev);
1369
1370         return 0;
1371 }
1372
1373 static int ipg_nic_rx(struct net_device *dev)
1374 {
1375         /* Transfer received Ethernet frames to higher network layers. */
1376         struct ipg_nic_private *sp = netdev_priv(dev);
1377         unsigned int curr = sp->rx_current;
1378         void __iomem *ioaddr = sp->ioaddr;
1379         struct ipg_rx *rxfd;
1380         unsigned int i;
1381
1382         IPG_DEBUG_MSG("_nic_rx\n");
1383
1384 #define __RFS_MASK \
1385         cpu_to_le64(IPG_RFS_RFDDONE | IPG_RFS_FRAMESTART | IPG_RFS_FRAMEEND)
1386
1387         for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1388                 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1389                 struct sk_buff *skb = sp->rx_buff[entry];
1390                 unsigned int framelen;
1391
1392                 rxfd = sp->rxd + entry;
1393
1394                 if (((rxfd->rfs & __RFS_MASK) != __RFS_MASK) || !skb)
1395                         break;
1396
1397                 /* Get received frame length. */
1398                 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1399
1400                 /* Check for jumbo frame arrival with too small
1401                  * RXFRAG_SIZE.
1402                  */
1403                 if (framelen > sp->rxfrag_size) {
1404                         IPG_DEBUG_MSG
1405                             ("RFS FrameLen > allocated fragment size\n");
1406
1407                         framelen = sp->rxfrag_size;
1408                 }
1409
1410                 if ((IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1411                        (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1412                         IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1413                         IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR)))) {
1414
1415                         IPG_DEBUG_MSG("Rx error, RFS = %016lx\n",
1416                                       (unsigned long int) rxfd->rfs);
1417
1418                         /* Increment general receive error statistic. */
1419                         sp->stats.rx_errors++;
1420
1421                         /* Increment detailed receive error statistics. */
1422                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1423                                 IPG_DEBUG_MSG("RX FIFO overrun occurred\n");
1424                                 sp->stats.rx_fifo_errors++;
1425                         }
1426
1427                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1428                                 IPG_DEBUG_MSG("RX runt occurred\n");
1429                                 sp->stats.rx_length_errors++;
1430                         }
1431
1432                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXOVERSIZEDFRAME) ;
1433                         /* Do nothing, error count handled by a IPG
1434                          * statistic register.
1435                          */
1436
1437                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1438                                 IPG_DEBUG_MSG("RX alignment error occurred\n");
1439                                 sp->stats.rx_frame_errors++;
1440                         }
1441
1442                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFCSERROR) ;
1443                         /* Do nothing, error count handled by a IPG
1444                          * statistic register.
1445                          */
1446
1447                         /* Free the memory associated with the RX
1448                          * buffer since it is erroneous and we will
1449                          * not pass it to higher layer processes.
1450                          */
1451                         if (skb) {
1452                                 __le64 info = rxfd->frag_info;
1453
1454                                 pci_unmap_single(sp->pdev,
1455                                         le64_to_cpu(info) & ~IPG_RFI_FRAGLEN,
1456                                         sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1457
1458                                 dev_kfree_skb_irq(skb);
1459                         }
1460                 } else {
1461
1462                         /* Adjust the new buffer length to accommodate the size
1463                          * of the received frame.
1464                          */
1465                         skb_put(skb, framelen);
1466
1467                         /* Set the buffer's protocol field to Ethernet. */
1468                         skb->protocol = eth_type_trans(skb, dev);
1469
1470                         /* The IPG encountered an error with (or
1471                          * there were no) IP/TCP/UDP checksums.
1472                          * This may or may not indicate an invalid
1473                          * IP/TCP/UDP frame was received. Let the
1474                          * upper layer decide.
1475                          */
1476                         skb_checksum_none_assert(skb);
1477
1478                         /* Hand off frame for higher layer processing.
1479                          * The function netif_rx() releases the sk_buff
1480                          * when processing completes.
1481                          */
1482                         netif_rx(skb);
1483                 }
1484
1485                 /* Assure RX buffer is not reused by IPG. */
1486                 sp->rx_buff[entry] = NULL;
1487         }
1488
1489         /*
1490          * If there are more RFDs to process and the allocated amount of RFD
1491          * processing time has expired, assert Interrupt Requested to make
1492          * sure we come back to process the remaining RFDs.
1493          */
1494         if (i == IPG_MAXRFDPROCESS_COUNT)
1495                 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1496
1497 #ifdef IPG_DEBUG
1498         /* Check if the RFD list contained no receive frame data. */
1499         if (!i)
1500                 sp->EmptyRFDListCount++;
1501 #endif
1502         while ((le64_to_cpu(rxfd->rfs) & IPG_RFS_RFDDONE) &&
1503                !((le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART) &&
1504                  (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND))) {
1505                 unsigned int entry = curr++ % IPG_RFDLIST_LENGTH;
1506
1507                 rxfd = sp->rxd + entry;
1508
1509                 IPG_DEBUG_MSG("Frame requires multiple RFDs\n");
1510
1511                 /* An unexpected event, additional code needed to handle
1512                  * properly. So for the time being, just disregard the
1513                  * frame.
1514                  */
1515
1516                 /* Free the memory associated with the RX
1517                  * buffer since it is erroneous and we will
1518                  * not pass it to higher layer processes.
1519                  */
1520                 if (sp->rx_buff[entry]) {
1521                         pci_unmap_single(sp->pdev,
1522                                 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1523                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1524                         dev_kfree_skb_irq(sp->rx_buff[entry]);
1525                 }
1526
1527                 /* Assure RX buffer is not reused by IPG. */
1528                 sp->rx_buff[entry] = NULL;
1529         }
1530
1531         sp->rx_current = curr;
1532
1533         /* Check to see if there are a minimum number of used
1534          * RFDs before restoring any (should improve performance.)
1535          */
1536         if ((curr - sp->rx_dirty) >= IPG_MINUSEDRFDSTOFREE)
1537                 ipg_nic_rxrestore(dev);
1538
1539         return 0;
1540 }
1541
1542 static void ipg_reset_after_host_error(struct work_struct *work)
1543 {
1544         struct ipg_nic_private *sp =
1545                 container_of(work, struct ipg_nic_private, task.work);
1546         struct net_device *dev = sp->dev;
1547
1548         /*
1549          * Acknowledge HostError interrupt by resetting
1550          * IPG DMA and HOST.
1551          */
1552         ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1553
1554         init_rfdlist(dev);
1555         init_tfdlist(dev);
1556
1557         if (ipg_io_config(dev) < 0) {
1558                 netdev_info(dev, "Cannot recover from PCI error\n");
1559                 schedule_delayed_work(&sp->task, HZ);
1560         }
1561 }
1562
1563 static irqreturn_t ipg_interrupt_handler(int irq, void *dev_inst)
1564 {
1565         struct net_device *dev = dev_inst;
1566         struct ipg_nic_private *sp = netdev_priv(dev);
1567         void __iomem *ioaddr = sp->ioaddr;
1568         unsigned int handled = 0;
1569         u16 status;
1570
1571         IPG_DEBUG_MSG("_interrupt_handler\n");
1572
1573         if (sp->is_jumbo)
1574                 ipg_nic_rxrestore(dev);
1575
1576         spin_lock(&sp->lock);
1577
1578         /* Get interrupt source information, and acknowledge
1579          * some (i.e. TxDMAComplete, RxDMAComplete, RxEarly,
1580          * IntRequested, MacControlFrame, LinkEvent) interrupts
1581          * if issued. Also, all IPG interrupts are disabled by
1582          * reading IntStatusAck.
1583          */
1584         status = ipg_r16(INT_STATUS_ACK);
1585
1586         IPG_DEBUG_MSG("IntStatusAck = %04x\n", status);
1587
1588         /* Shared IRQ of remove event. */
1589         if (!(status & IPG_IS_RSVD_MASK))
1590                 goto out_enable;
1591
1592         handled = 1;
1593
1594         if (unlikely(!netif_running(dev)))
1595                 goto out_unlock;
1596
1597         /* If RFDListEnd interrupt, restore all used RFDs. */
1598         if (status & IPG_IS_RFD_LIST_END) {
1599                 IPG_DEBUG_MSG("RFDListEnd Interrupt\n");
1600
1601                 /* The RFD list end indicates an RFD was encountered
1602                  * with a 0 NextPtr, or with an RFDDone bit set to 1
1603                  * (indicating the RFD is not read for use by the
1604                  * IPG.) Try to restore all RFDs.
1605                  */
1606                 ipg_nic_rxrestore(dev);
1607
1608 #ifdef IPG_DEBUG
1609                 /* Increment the RFDlistendCount counter. */
1610                 sp->RFDlistendCount++;
1611 #endif
1612         }
1613
1614         /* If RFDListEnd, RxDMAPriority, RxDMAComplete, or
1615          * IntRequested interrupt, process received frames. */
1616         if ((status & IPG_IS_RX_DMA_PRIORITY) ||
1617             (status & IPG_IS_RFD_LIST_END) ||
1618             (status & IPG_IS_RX_DMA_COMPLETE) ||
1619             (status & IPG_IS_INT_REQUESTED)) {
1620 #ifdef IPG_DEBUG
1621                 /* Increment the RFD list checked counter if interrupted
1622                  * only to check the RFD list. */
1623                 if (status & (~(IPG_IS_RX_DMA_PRIORITY | IPG_IS_RFD_LIST_END |
1624                                 IPG_IS_RX_DMA_COMPLETE | IPG_IS_INT_REQUESTED) &
1625                                (IPG_IS_HOST_ERROR | IPG_IS_TX_DMA_COMPLETE |
1626                                 IPG_IS_LINK_EVENT | IPG_IS_TX_COMPLETE |
1627                                 IPG_IS_UPDATE_STATS)))
1628                         sp->RFDListCheckedCount++;
1629 #endif
1630
1631                 if (sp->is_jumbo)
1632                         ipg_nic_rx_jumbo(dev);
1633                 else
1634                         ipg_nic_rx(dev);
1635         }
1636
1637         /* If TxDMAComplete interrupt, free used TFDs. */
1638         if (status & IPG_IS_TX_DMA_COMPLETE)
1639                 ipg_nic_txfree(dev);
1640
1641         /* TxComplete interrupts indicate one of numerous actions.
1642          * Determine what action to take based on TXSTATUS register.
1643          */
1644         if (status & IPG_IS_TX_COMPLETE)
1645                 ipg_nic_txcleanup(dev);
1646
1647         /* If UpdateStats interrupt, update Linux Ethernet statistics */
1648         if (status & IPG_IS_UPDATE_STATS)
1649                 ipg_nic_get_stats(dev);
1650
1651         /* If HostError interrupt, reset IPG. */
1652         if (status & IPG_IS_HOST_ERROR) {
1653                 IPG_DDEBUG_MSG("HostError Interrupt\n");
1654
1655                 schedule_delayed_work(&sp->task, 0);
1656         }
1657
1658         /* If LinkEvent interrupt, resolve autonegotiation. */
1659         if (status & IPG_IS_LINK_EVENT) {
1660                 if (ipg_config_autoneg(dev) < 0)
1661                         netdev_info(dev, "Auto-negotiation error\n");
1662         }
1663
1664         /* If MACCtrlFrame interrupt, do nothing. */
1665         if (status & IPG_IS_MAC_CTRL_FRAME)
1666                 IPG_DEBUG_MSG("MACCtrlFrame interrupt\n");
1667
1668         /* If RxComplete interrupt, do nothing. */
1669         if (status & IPG_IS_RX_COMPLETE)
1670                 IPG_DEBUG_MSG("RxComplete interrupt\n");
1671
1672         /* If RxEarly interrupt, do nothing. */
1673         if (status & IPG_IS_RX_EARLY)
1674                 IPG_DEBUG_MSG("RxEarly interrupt\n");
1675
1676 out_enable:
1677         /* Re-enable IPG interrupts. */
1678         ipg_w16(IPG_IE_TX_DMA_COMPLETE | IPG_IE_RX_DMA_COMPLETE |
1679                 IPG_IE_HOST_ERROR | IPG_IE_INT_REQUESTED | IPG_IE_TX_COMPLETE |
1680                 IPG_IE_LINK_EVENT | IPG_IE_UPDATE_STATS, INT_ENABLE);
1681 out_unlock:
1682         spin_unlock(&sp->lock);
1683
1684         return IRQ_RETVAL(handled);
1685 }
1686
1687 static void ipg_rx_clear(struct ipg_nic_private *sp)
1688 {
1689         unsigned int i;
1690
1691         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
1692                 if (sp->rx_buff[i]) {
1693                         struct ipg_rx *rxfd = sp->rxd + i;
1694
1695                         dev_kfree_skb_irq(sp->rx_buff[i]);
1696                         sp->rx_buff[i] = NULL;
1697                         pci_unmap_single(sp->pdev,
1698                                 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1699                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1700                 }
1701         }
1702 }
1703
1704 static void ipg_tx_clear(struct ipg_nic_private *sp)
1705 {
1706         unsigned int i;
1707
1708         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
1709                 if (sp->tx_buff[i]) {
1710                         struct ipg_tx *txfd = sp->txd + i;
1711
1712                         pci_unmap_single(sp->pdev,
1713                                 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
1714                                 sp->tx_buff[i]->len, PCI_DMA_TODEVICE);
1715
1716                         dev_kfree_skb_irq(sp->tx_buff[i]);
1717
1718                         sp->tx_buff[i] = NULL;
1719                 }
1720         }
1721 }
1722
1723 static int ipg_nic_open(struct net_device *dev)
1724 {
1725         struct ipg_nic_private *sp = netdev_priv(dev);
1726         void __iomem *ioaddr = sp->ioaddr;
1727         struct pci_dev *pdev = sp->pdev;
1728         int rc;
1729
1730         IPG_DEBUG_MSG("_nic_open\n");
1731
1732         sp->rx_buf_sz = sp->rxsupport_size;
1733
1734         /* Check for interrupt line conflicts, and request interrupt
1735          * line for IPG.
1736          *
1737          * IMPORTANT: Disable IPG interrupts prior to registering
1738          *            IRQ.
1739          */
1740         ipg_w16(0x0000, INT_ENABLE);
1741
1742         /* Register the interrupt line to be used by the IPG within
1743          * the Linux system.
1744          */
1745         rc = request_irq(pdev->irq, ipg_interrupt_handler, IRQF_SHARED,
1746                          dev->name, dev);
1747         if (rc < 0) {
1748                 netdev_info(dev, "Error when requesting interrupt\n");
1749                 goto out;
1750         }
1751
1752         dev->irq = pdev->irq;
1753
1754         rc = -ENOMEM;
1755
1756         sp->rxd = dma_alloc_coherent(&pdev->dev, IPG_RX_RING_BYTES,
1757                                      &sp->rxd_map, GFP_KERNEL);
1758         if (!sp->rxd)
1759                 goto err_free_irq_0;
1760
1761         sp->txd = dma_alloc_coherent(&pdev->dev, IPG_TX_RING_BYTES,
1762                                      &sp->txd_map, GFP_KERNEL);
1763         if (!sp->txd)
1764                 goto err_free_rx_1;
1765
1766         rc = init_rfdlist(dev);
1767         if (rc < 0) {
1768                 netdev_info(dev, "Error during configuration\n");
1769                 goto err_free_tx_2;
1770         }
1771
1772         init_tfdlist(dev);
1773
1774         rc = ipg_io_config(dev);
1775         if (rc < 0) {
1776                 netdev_info(dev, "Error during configuration\n");
1777                 goto err_release_tfdlist_3;
1778         }
1779
1780         /* Resolve autonegotiation. */
1781         if (ipg_config_autoneg(dev) < 0)
1782                 netdev_info(dev, "Auto-negotiation error\n");
1783
1784         /* initialize JUMBO Frame control variable */
1785         sp->jumbo.found_start = 0;
1786         sp->jumbo.current_size = 0;
1787         sp->jumbo.skb = NULL;
1788
1789         /* Enable transmit and receive operation of the IPG. */
1790         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_RX_ENABLE | IPG_MC_TX_ENABLE) &
1791                  IPG_MC_RSVD_MASK, MAC_CTRL);
1792
1793         netif_start_queue(dev);
1794 out:
1795         return rc;
1796
1797 err_release_tfdlist_3:
1798         ipg_tx_clear(sp);
1799         ipg_rx_clear(sp);
1800 err_free_tx_2:
1801         dma_free_coherent(&pdev->dev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1802 err_free_rx_1:
1803         dma_free_coherent(&pdev->dev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1804 err_free_irq_0:
1805         free_irq(pdev->irq, dev);
1806         goto out;
1807 }
1808
1809 static int ipg_nic_stop(struct net_device *dev)
1810 {
1811         struct ipg_nic_private *sp = netdev_priv(dev);
1812         void __iomem *ioaddr = sp->ioaddr;
1813         struct pci_dev *pdev = sp->pdev;
1814
1815         IPG_DEBUG_MSG("_nic_stop\n");
1816
1817         netif_stop_queue(dev);
1818
1819         IPG_DUMPTFDLIST(dev);
1820
1821         do {
1822                 (void) ipg_r16(INT_STATUS_ACK);
1823
1824                 ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1825
1826                 synchronize_irq(pdev->irq);
1827         } while (ipg_r16(INT_ENABLE) & IPG_IE_RSVD_MASK);
1828
1829         ipg_rx_clear(sp);
1830
1831         ipg_tx_clear(sp);
1832
1833         pci_free_consistent(pdev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1834         pci_free_consistent(pdev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1835
1836         free_irq(pdev->irq, dev);
1837
1838         return 0;
1839 }
1840
1841 static netdev_tx_t ipg_nic_hard_start_xmit(struct sk_buff *skb,
1842                                            struct net_device *dev)
1843 {
1844         struct ipg_nic_private *sp = netdev_priv(dev);
1845         void __iomem *ioaddr = sp->ioaddr;
1846         unsigned int entry = sp->tx_current % IPG_TFDLIST_LENGTH;
1847         unsigned long flags;
1848         struct ipg_tx *txfd;
1849
1850         IPG_DDEBUG_MSG("_nic_hard_start_xmit\n");
1851
1852         /* If in 10Mbps mode, stop the transmit queue so
1853          * no more transmit frames are accepted.
1854          */
1855         if (sp->tenmbpsmode)
1856                 netif_stop_queue(dev);
1857
1858         if (sp->reset_current_tfd) {
1859                 sp->reset_current_tfd = 0;
1860                 entry = 0;
1861         }
1862
1863         txfd = sp->txd + entry;
1864
1865         sp->tx_buff[entry] = skb;
1866
1867         /* Clear all TFC fields, except TFDDONE. */
1868         txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
1869
1870         /* Specify the TFC field within the TFD. */
1871         txfd->tfc |= cpu_to_le64(IPG_TFC_WORDALIGNDISABLED |
1872                 (IPG_TFC_FRAMEID & sp->tx_current) |
1873                 (IPG_TFC_FRAGCOUNT & (1 << 24)));
1874         /*
1875          * 16--17 (WordAlign) <- 3 (disable),
1876          * 0--15 (FrameId) <- sp->tx_current,
1877          * 24--27 (FragCount) <- 1
1878          */
1879
1880         /* Request TxComplete interrupts at an interval defined
1881          * by the constant IPG_FRAMESBETWEENTXCOMPLETES.
1882          * Request TxComplete interrupt for every frame
1883          * if in 10Mbps mode to accommodate problem with 10Mbps
1884          * processing.
1885          */
1886         if (sp->tenmbpsmode)
1887                 txfd->tfc |= cpu_to_le64(IPG_TFC_TXINDICATE);
1888         txfd->tfc |= cpu_to_le64(IPG_TFC_TXDMAINDICATE);
1889         /* Based on compilation option, determine if FCS is to be
1890          * appended to transmit frame by IPG.
1891          */
1892         if (!(IPG_APPEND_FCS_ON_TX))
1893                 txfd->tfc |= cpu_to_le64(IPG_TFC_FCSAPPENDDISABLE);
1894
1895         /* Based on compilation option, determine if IP, TCP and/or
1896          * UDP checksums are to be added to transmit frame by IPG.
1897          */
1898         if (IPG_ADD_IPCHECKSUM_ON_TX)
1899                 txfd->tfc |= cpu_to_le64(IPG_TFC_IPCHECKSUMENABLE);
1900
1901         if (IPG_ADD_TCPCHECKSUM_ON_TX)
1902                 txfd->tfc |= cpu_to_le64(IPG_TFC_TCPCHECKSUMENABLE);
1903
1904         if (IPG_ADD_UDPCHECKSUM_ON_TX)
1905                 txfd->tfc |= cpu_to_le64(IPG_TFC_UDPCHECKSUMENABLE);
1906
1907         /* Based on compilation option, determine if VLAN tag info is to be
1908          * inserted into transmit frame by IPG.
1909          */
1910         if (IPG_INSERT_MANUAL_VLAN_TAG) {
1911                 txfd->tfc |= cpu_to_le64(IPG_TFC_VLANTAGINSERT |
1912                         ((u64) IPG_MANUAL_VLAN_VID << 32) |
1913                         ((u64) IPG_MANUAL_VLAN_CFI << 44) |
1914                         ((u64) IPG_MANUAL_VLAN_USERPRIORITY << 45));
1915         }
1916
1917         /* The fragment start location within system memory is defined
1918          * by the sk_buff structure's data field. The physical address
1919          * of this location within the system's virtual memory space
1920          * is determined using the IPG_HOST2BUS_MAP function.
1921          */
1922         txfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
1923                 skb->len, PCI_DMA_TODEVICE));
1924
1925         /* The length of the fragment within system memory is defined by
1926          * the sk_buff structure's len field.
1927          */
1928         txfd->frag_info |= cpu_to_le64(IPG_TFI_FRAGLEN &
1929                 ((u64) (skb->len & 0xffff) << 48));
1930
1931         /* Clear the TFDDone bit last to indicate the TFD is ready
1932          * for transfer to the IPG.
1933          */
1934         txfd->tfc &= cpu_to_le64(~IPG_TFC_TFDDONE);
1935
1936         spin_lock_irqsave(&sp->lock, flags);
1937
1938         sp->tx_current++;
1939
1940         mmiowb();
1941
1942         ipg_w32(IPG_DC_TX_DMA_POLL_NOW, DMA_CTRL);
1943
1944         if (sp->tx_current == (sp->tx_dirty + IPG_TFDLIST_LENGTH))
1945                 netif_stop_queue(dev);
1946
1947         spin_unlock_irqrestore(&sp->lock, flags);
1948
1949         return NETDEV_TX_OK;
1950 }
1951
1952 static void ipg_set_phy_default_param(unsigned char rev,
1953                                       struct net_device *dev, int phy_address)
1954 {
1955         unsigned short length;
1956         unsigned char revision;
1957         const unsigned short *phy_param;
1958         unsigned short address, value;
1959
1960         phy_param = &DefaultPhyParam[0];
1961         length = *phy_param & 0x00FF;
1962         revision = (unsigned char)((*phy_param) >> 8);
1963         phy_param++;
1964         while (length != 0) {
1965                 if (rev == revision) {
1966                         while (length > 1) {
1967                                 address = *phy_param;
1968                                 value = *(phy_param + 1);
1969                                 phy_param += 2;
1970                                 mdio_write(dev, phy_address, address, value);
1971                                 length -= 4;
1972                         }
1973                         break;
1974                 } else {
1975                         phy_param += length / 2;
1976                         length = *phy_param & 0x00FF;
1977                         revision = (unsigned char)((*phy_param) >> 8);
1978                         phy_param++;
1979                 }
1980         }
1981 }
1982
1983 static int read_eeprom(struct net_device *dev, int eep_addr)
1984 {
1985         void __iomem *ioaddr = ipg_ioaddr(dev);
1986         unsigned int i;
1987         int ret = 0;
1988         u16 value;
1989
1990         value = IPG_EC_EEPROM_READOPCODE | (eep_addr & 0xff);
1991         ipg_w16(value, EEPROM_CTRL);
1992
1993         for (i = 0; i < 1000; i++) {
1994                 u16 data;
1995
1996                 mdelay(10);
1997                 data = ipg_r16(EEPROM_CTRL);
1998                 if (!(data & IPG_EC_EEPROM_BUSY)) {
1999                         ret = ipg_r16(EEPROM_DATA);
2000                         break;
2001                 }
2002         }
2003         return ret;
2004 }
2005
2006 static void ipg_init_mii(struct net_device *dev)
2007 {
2008         struct ipg_nic_private *sp = netdev_priv(dev);
2009         struct mii_if_info *mii_if = &sp->mii_if;
2010         int phyaddr;
2011
2012         mii_if->dev          = dev;
2013         mii_if->mdio_read    = mdio_read;
2014         mii_if->mdio_write   = mdio_write;
2015         mii_if->phy_id_mask  = 0x1f;
2016         mii_if->reg_num_mask = 0x1f;
2017
2018         mii_if->phy_id = phyaddr = ipg_find_phyaddr(dev);
2019
2020         if (phyaddr != 0x1f) {
2021                 u16 mii_phyctrl, mii_1000cr;
2022
2023                 mii_1000cr  = mdio_read(dev, phyaddr, MII_CTRL1000);
2024                 mii_1000cr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF |
2025                         GMII_PHY_1000BASETCONTROL_PreferMaster;
2026                 mdio_write(dev, phyaddr, MII_CTRL1000, mii_1000cr);
2027
2028                 mii_phyctrl = mdio_read(dev, phyaddr, MII_BMCR);
2029
2030                 /* Set default phyparam */
2031                 ipg_set_phy_default_param(sp->pdev->revision, dev, phyaddr);
2032
2033                 /* Reset PHY */
2034                 mii_phyctrl |= BMCR_RESET | BMCR_ANRESTART;
2035                 mdio_write(dev, phyaddr, MII_BMCR, mii_phyctrl);
2036
2037         }
2038 }
2039
2040 static int ipg_hw_init(struct net_device *dev)
2041 {
2042         struct ipg_nic_private *sp = netdev_priv(dev);
2043         void __iomem *ioaddr = sp->ioaddr;
2044         unsigned int i;
2045         int rc;
2046
2047         /* Read/Write and Reset EEPROM Value */
2048         /* Read LED Mode Configuration from EEPROM */
2049         sp->led_mode = read_eeprom(dev, 6);
2050
2051         /* Reset all functions within the IPG. Do not assert
2052          * RST_OUT as not compatible with some PHYs.
2053          */
2054         rc = ipg_reset(dev, IPG_RESET_MASK);
2055         if (rc < 0)
2056                 goto out;
2057
2058         ipg_init_mii(dev);
2059
2060         /* Read MAC Address from EEPROM */
2061         for (i = 0; i < 3; i++)
2062                 sp->station_addr[i] = read_eeprom(dev, 16 + i);
2063
2064         for (i = 0; i < 3; i++)
2065                 ipg_w16(sp->station_addr[i], STATION_ADDRESS_0 + 2*i);
2066
2067         /* Set station address in ethernet_device structure. */
2068         dev->dev_addr[0] =  ipg_r16(STATION_ADDRESS_0) & 0x00ff;
2069         dev->dev_addr[1] = (ipg_r16(STATION_ADDRESS_0) & 0xff00) >> 8;
2070         dev->dev_addr[2] =  ipg_r16(STATION_ADDRESS_1) & 0x00ff;
2071         dev->dev_addr[3] = (ipg_r16(STATION_ADDRESS_1) & 0xff00) >> 8;
2072         dev->dev_addr[4] =  ipg_r16(STATION_ADDRESS_2) & 0x00ff;
2073         dev->dev_addr[5] = (ipg_r16(STATION_ADDRESS_2) & 0xff00) >> 8;
2074 out:
2075         return rc;
2076 }
2077
2078 static int ipg_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2079 {
2080         struct ipg_nic_private *sp = netdev_priv(dev);
2081         int rc;
2082
2083         mutex_lock(&sp->mii_mutex);
2084         rc = generic_mii_ioctl(&sp->mii_if, if_mii(ifr), cmd, NULL);
2085         mutex_unlock(&sp->mii_mutex);
2086
2087         return rc;
2088 }
2089
2090 static int ipg_nic_change_mtu(struct net_device *dev, int new_mtu)
2091 {
2092         struct ipg_nic_private *sp = netdev_priv(dev);
2093         int err;
2094
2095         /* Function to accommodate changes to Maximum Transfer Unit
2096          * (or MTU) of IPG NIC. Cannot use default function since
2097          * the default will not allow for MTU > 1500 bytes.
2098          */
2099
2100         IPG_DEBUG_MSG("_nic_change_mtu\n");
2101
2102         /*
2103          * Check that the new MTU value is between 68 (14 byte header, 46 byte
2104          * payload, 4 byte FCS) and 10 KB, which is the largest supported MTU.
2105          */
2106         if (new_mtu < 68 || new_mtu > 10240)
2107                 return -EINVAL;
2108
2109         err = ipg_nic_stop(dev);
2110         if (err)
2111                 return err;
2112
2113         dev->mtu = new_mtu;
2114
2115         sp->max_rxframe_size = new_mtu;
2116
2117         sp->rxfrag_size = new_mtu;
2118         if (sp->rxfrag_size > 4088)
2119                 sp->rxfrag_size = 4088;
2120
2121         sp->rxsupport_size = sp->max_rxframe_size;
2122
2123         if (new_mtu > 0x0600)
2124                 sp->is_jumbo = true;
2125         else
2126                 sp->is_jumbo = false;
2127
2128         return ipg_nic_open(dev);
2129 }
2130
2131 static int ipg_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2132 {
2133         struct ipg_nic_private *sp = netdev_priv(dev);
2134         int rc;
2135
2136         mutex_lock(&sp->mii_mutex);
2137         rc = mii_ethtool_gset(&sp->mii_if, cmd);
2138         mutex_unlock(&sp->mii_mutex);
2139
2140         return rc;
2141 }
2142
2143 static int ipg_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2144 {
2145         struct ipg_nic_private *sp = netdev_priv(dev);
2146         int rc;
2147
2148         mutex_lock(&sp->mii_mutex);
2149         rc = mii_ethtool_sset(&sp->mii_if, cmd);
2150         mutex_unlock(&sp->mii_mutex);
2151
2152         return rc;
2153 }
2154
2155 static int ipg_nway_reset(struct net_device *dev)
2156 {
2157         struct ipg_nic_private *sp = netdev_priv(dev);
2158         int rc;
2159
2160         mutex_lock(&sp->mii_mutex);
2161         rc = mii_nway_restart(&sp->mii_if);
2162         mutex_unlock(&sp->mii_mutex);
2163
2164         return rc;
2165 }
2166
2167 static const struct ethtool_ops ipg_ethtool_ops = {
2168         .get_settings = ipg_get_settings,
2169         .set_settings = ipg_set_settings,
2170         .nway_reset   = ipg_nway_reset,
2171 };
2172
2173 static void __devexit ipg_remove(struct pci_dev *pdev)
2174 {
2175         struct net_device *dev = pci_get_drvdata(pdev);
2176         struct ipg_nic_private *sp = netdev_priv(dev);
2177
2178         IPG_DEBUG_MSG("_remove\n");
2179
2180         /* Un-register Ethernet device. */
2181         unregister_netdev(dev);
2182
2183         pci_iounmap(pdev, sp->ioaddr);
2184
2185         pci_release_regions(pdev);
2186
2187         free_netdev(dev);
2188         pci_disable_device(pdev);
2189         pci_set_drvdata(pdev, NULL);
2190 }
2191
2192 static const struct net_device_ops ipg_netdev_ops = {
2193         .ndo_open               = ipg_nic_open,
2194         .ndo_stop               = ipg_nic_stop,
2195         .ndo_start_xmit         = ipg_nic_hard_start_xmit,
2196         .ndo_get_stats          = ipg_nic_get_stats,
2197         .ndo_set_rx_mode        = ipg_nic_set_multicast_list,
2198         .ndo_do_ioctl           = ipg_ioctl,
2199         .ndo_tx_timeout         = ipg_tx_timeout,
2200         .ndo_change_mtu         = ipg_nic_change_mtu,
2201         .ndo_set_mac_address    = eth_mac_addr,
2202         .ndo_validate_addr      = eth_validate_addr,
2203 };
2204
2205 static int __devinit ipg_probe(struct pci_dev *pdev,
2206                                const struct pci_device_id *id)
2207 {
2208         unsigned int i = id->driver_data;
2209         struct ipg_nic_private *sp;
2210         struct net_device *dev;
2211         void __iomem *ioaddr;
2212         int rc;
2213
2214         rc = pci_enable_device(pdev);
2215         if (rc < 0)
2216                 goto out;
2217
2218         pr_info("%s: %s\n", pci_name(pdev), ipg_brand_name[i]);
2219
2220         pci_set_master(pdev);
2221
2222         rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(40));
2223         if (rc < 0) {
2224                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2225                 if (rc < 0) {
2226                         pr_err("%s: DMA config failed\n", pci_name(pdev));
2227                         goto err_disable_0;
2228                 }
2229         }
2230
2231         /*
2232          * Initialize net device.
2233          */
2234         dev = alloc_etherdev(sizeof(struct ipg_nic_private));
2235         if (!dev) {
2236                 rc = -ENOMEM;
2237                 goto err_disable_0;
2238         }
2239
2240         sp = netdev_priv(dev);
2241         spin_lock_init(&sp->lock);
2242         mutex_init(&sp->mii_mutex);
2243
2244         sp->is_jumbo = IPG_IS_JUMBO;
2245         sp->rxfrag_size = IPG_RXFRAG_SIZE;
2246         sp->rxsupport_size = IPG_RXSUPPORT_SIZE;
2247         sp->max_rxframe_size = IPG_MAX_RXFRAME_SIZE;
2248
2249         /* Declare IPG NIC functions for Ethernet device methods.
2250          */
2251         dev->netdev_ops = &ipg_netdev_ops;
2252         SET_NETDEV_DEV(dev, &pdev->dev);
2253         SET_ETHTOOL_OPS(dev, &ipg_ethtool_ops);
2254
2255         rc = pci_request_regions(pdev, DRV_NAME);
2256         if (rc)
2257                 goto err_free_dev_1;
2258
2259         ioaddr = pci_iomap(pdev, 1, pci_resource_len(pdev, 1));
2260         if (!ioaddr) {
2261                 pr_err("%s: cannot map MMIO\n", pci_name(pdev));
2262                 rc = -EIO;
2263                 goto err_release_regions_2;
2264         }
2265
2266         /* Save the pointer to the PCI device information. */
2267         sp->ioaddr = ioaddr;
2268         sp->pdev = pdev;
2269         sp->dev = dev;
2270
2271         INIT_DELAYED_WORK(&sp->task, ipg_reset_after_host_error);
2272
2273         pci_set_drvdata(pdev, dev);
2274
2275         rc = ipg_hw_init(dev);
2276         if (rc < 0)
2277                 goto err_unmap_3;
2278
2279         rc = register_netdev(dev);
2280         if (rc < 0)
2281                 goto err_unmap_3;
2282
2283         netdev_info(dev, "Ethernet device registered\n");
2284 out:
2285         return rc;
2286
2287 err_unmap_3:
2288         pci_iounmap(pdev, ioaddr);
2289 err_release_regions_2:
2290         pci_release_regions(pdev);
2291 err_free_dev_1:
2292         free_netdev(dev);
2293 err_disable_0:
2294         pci_disable_device(pdev);
2295         goto out;
2296 }
2297
2298 static struct pci_driver ipg_pci_driver = {
2299         .name           = IPG_DRIVER_NAME,
2300         .id_table       = ipg_pci_tbl,
2301         .probe          = ipg_probe,
2302         .remove         = __devexit_p(ipg_remove),
2303 };
2304
2305 static int __init ipg_init_module(void)
2306 {
2307         return pci_register_driver(&ipg_pci_driver);
2308 }
2309
2310 static void __exit ipg_exit_module(void)
2311 {
2312         pci_unregister_driver(&ipg_pci_driver);
2313 }
2314
2315 module_init(ipg_init_module);
2316 module_exit(ipg_exit_module);