2 * Huawei HiNIC PCI Express Linux driver
3 * Copyright(c) 2017 Huawei Technologies Co., Ltd
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/pci.h>
19 #include <linux/device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/vmalloc.h>
22 #include <linux/errno.h>
23 #include <linux/sizes.h>
24 #include <linux/atomic.h>
25 #include <linux/skbuff.h>
27 #include <asm/barrier.h>
28 #include <asm/byteorder.h>
30 #include "hinic_common.h"
31 #include "hinic_hw_if.h"
32 #include "hinic_hw_wqe.h"
33 #include "hinic_hw_wq.h"
34 #include "hinic_hw_qp_ctxt.h"
35 #include "hinic_hw_qp.h"
36 #include "hinic_hw_io.h"
38 #define SQ_DB_OFF SZ_2K
40 /* The number of cache line to prefetch Until threshold state */
41 #define WQ_PREFETCH_MAX 2
42 /* The number of cache line to prefetch After threshold state */
43 #define WQ_PREFETCH_MIN 1
45 #define WQ_PREFETCH_THRESHOLD 256
47 /* sizes of the SQ/RQ ctxt */
48 #define Q_CTXT_SIZE 48
51 #define SQ_CTXT_OFFSET(max_sqs, max_rqs, q_id) \
52 (((max_rqs) + (max_sqs)) * CTXT_RSVD + (q_id) * Q_CTXT_SIZE)
54 #define RQ_CTXT_OFFSET(max_sqs, max_rqs, q_id) \
55 (((max_rqs) + (max_sqs)) * CTXT_RSVD + \
56 (max_sqs + (q_id)) * Q_CTXT_SIZE)
58 #define SIZE_16BYTES(size) (ALIGN(size, 16) >> 4)
59 #define SIZE_8BYTES(size) (ALIGN(size, 8) >> 3)
60 #define SECT_SIZE_FROM_8BYTES(size) ((size) << 3)
62 #define SQ_DB_PI_HI_SHIFT 8
63 #define SQ_DB_PI_HI(prod_idx) ((prod_idx) >> SQ_DB_PI_HI_SHIFT)
65 #define SQ_DB_PI_LOW_MASK 0xFF
66 #define SQ_DB_PI_LOW(prod_idx) ((prod_idx) & SQ_DB_PI_LOW_MASK)
68 #define SQ_DB_ADDR(sq, pi) ((u64 *)((sq)->db_base) + SQ_DB_PI_LOW(pi))
70 #define SQ_MASKED_IDX(sq, idx) ((idx) & (sq)->wq->mask)
71 #define RQ_MASKED_IDX(rq, idx) ((idx) & (rq)->wq->mask)
77 enum rq_completion_fmt {
81 void hinic_qp_prepare_header(struct hinic_qp_ctxt_header *qp_ctxt_hdr,
82 enum hinic_qp_ctxt_type ctxt_type,
83 u16 num_queues, u16 max_queues)
85 u16 max_sqs = max_queues;
86 u16 max_rqs = max_queues;
88 qp_ctxt_hdr->num_queues = num_queues;
89 qp_ctxt_hdr->queue_type = ctxt_type;
91 if (ctxt_type == HINIC_QP_CTXT_TYPE_SQ)
92 qp_ctxt_hdr->addr_offset = SQ_CTXT_OFFSET(max_sqs, max_rqs, 0);
94 qp_ctxt_hdr->addr_offset = RQ_CTXT_OFFSET(max_sqs, max_rqs, 0);
96 qp_ctxt_hdr->addr_offset = SIZE_16BYTES(qp_ctxt_hdr->addr_offset);
98 hinic_cpu_to_be32(qp_ctxt_hdr, sizeof(*qp_ctxt_hdr));
101 void hinic_sq_prepare_ctxt(struct hinic_sq_ctxt *sq_ctxt,
102 struct hinic_sq *sq, u16 global_qid)
104 u32 wq_page_pfn_hi, wq_page_pfn_lo, wq_block_pfn_hi, wq_block_pfn_lo;
105 u64 wq_page_addr, wq_page_pfn, wq_block_pfn;
106 u16 pi_start, ci_start;
110 ci_start = atomic_read(&wq->cons_idx);
111 pi_start = atomic_read(&wq->prod_idx);
113 /* Read the first page paddr from the WQ page paddr ptrs */
114 wq_page_addr = be64_to_cpu(*wq->block_vaddr);
116 wq_page_pfn = HINIC_WQ_PAGE_PFN(wq_page_addr);
117 wq_page_pfn_hi = upper_32_bits(wq_page_pfn);
118 wq_page_pfn_lo = lower_32_bits(wq_page_pfn);
120 wq_block_pfn = HINIC_WQ_BLOCK_PFN(wq->block_paddr);
121 wq_block_pfn_hi = upper_32_bits(wq_block_pfn);
122 wq_block_pfn_lo = lower_32_bits(wq_block_pfn);
124 sq_ctxt->ceq_attr = HINIC_SQ_CTXT_CEQ_ATTR_SET(global_qid,
126 HINIC_SQ_CTXT_CEQ_ATTR_SET(0, EN);
128 sq_ctxt->ci_wrapped = HINIC_SQ_CTXT_CI_SET(ci_start, IDX) |
129 HINIC_SQ_CTXT_CI_SET(1, WRAPPED);
131 sq_ctxt->wq_hi_pfn_pi =
132 HINIC_SQ_CTXT_WQ_PAGE_SET(wq_page_pfn_hi, HI_PFN) |
133 HINIC_SQ_CTXT_WQ_PAGE_SET(pi_start, PI);
135 sq_ctxt->wq_lo_pfn = wq_page_pfn_lo;
137 sq_ctxt->pref_cache =
138 HINIC_SQ_CTXT_PREF_SET(WQ_PREFETCH_MIN, CACHE_MIN) |
139 HINIC_SQ_CTXT_PREF_SET(WQ_PREFETCH_MAX, CACHE_MAX) |
140 HINIC_SQ_CTXT_PREF_SET(WQ_PREFETCH_THRESHOLD, CACHE_THRESHOLD);
142 sq_ctxt->pref_wrapped = 1;
144 sq_ctxt->pref_wq_hi_pfn_ci =
145 HINIC_SQ_CTXT_PREF_SET(ci_start, CI) |
146 HINIC_SQ_CTXT_PREF_SET(wq_page_pfn_hi, WQ_HI_PFN);
148 sq_ctxt->pref_wq_lo_pfn = wq_page_pfn_lo;
150 sq_ctxt->wq_block_hi_pfn =
151 HINIC_SQ_CTXT_WQ_BLOCK_SET(wq_block_pfn_hi, HI_PFN);
153 sq_ctxt->wq_block_lo_pfn = wq_block_pfn_lo;
155 hinic_cpu_to_be32(sq_ctxt, sizeof(*sq_ctxt));
158 void hinic_rq_prepare_ctxt(struct hinic_rq_ctxt *rq_ctxt,
159 struct hinic_rq *rq, u16 global_qid)
161 u32 wq_page_pfn_hi, wq_page_pfn_lo, wq_block_pfn_hi, wq_block_pfn_lo;
162 u64 wq_page_addr, wq_page_pfn, wq_block_pfn;
163 u16 pi_start, ci_start;
167 ci_start = atomic_read(&wq->cons_idx);
168 pi_start = atomic_read(&wq->prod_idx);
170 /* Read the first page paddr from the WQ page paddr ptrs */
171 wq_page_addr = be64_to_cpu(*wq->block_vaddr);
173 wq_page_pfn = HINIC_WQ_PAGE_PFN(wq_page_addr);
174 wq_page_pfn_hi = upper_32_bits(wq_page_pfn);
175 wq_page_pfn_lo = lower_32_bits(wq_page_pfn);
177 wq_block_pfn = HINIC_WQ_BLOCK_PFN(wq->block_paddr);
178 wq_block_pfn_hi = upper_32_bits(wq_block_pfn);
179 wq_block_pfn_lo = lower_32_bits(wq_block_pfn);
181 rq_ctxt->ceq_attr = HINIC_RQ_CTXT_CEQ_ATTR_SET(0, EN) |
182 HINIC_RQ_CTXT_CEQ_ATTR_SET(1, WRAPPED);
184 rq_ctxt->pi_intr_attr = HINIC_RQ_CTXT_PI_SET(pi_start, IDX) |
185 HINIC_RQ_CTXT_PI_SET(rq->msix_entry, INTR);
187 rq_ctxt->wq_hi_pfn_ci = HINIC_RQ_CTXT_WQ_PAGE_SET(wq_page_pfn_hi,
189 HINIC_RQ_CTXT_WQ_PAGE_SET(ci_start, CI);
191 rq_ctxt->wq_lo_pfn = wq_page_pfn_lo;
193 rq_ctxt->pref_cache =
194 HINIC_RQ_CTXT_PREF_SET(WQ_PREFETCH_MIN, CACHE_MIN) |
195 HINIC_RQ_CTXT_PREF_SET(WQ_PREFETCH_MAX, CACHE_MAX) |
196 HINIC_RQ_CTXT_PREF_SET(WQ_PREFETCH_THRESHOLD, CACHE_THRESHOLD);
198 rq_ctxt->pref_wrapped = 1;
200 rq_ctxt->pref_wq_hi_pfn_ci =
201 HINIC_RQ_CTXT_PREF_SET(wq_page_pfn_hi, WQ_HI_PFN) |
202 HINIC_RQ_CTXT_PREF_SET(ci_start, CI);
204 rq_ctxt->pref_wq_lo_pfn = wq_page_pfn_lo;
206 rq_ctxt->pi_paddr_hi = upper_32_bits(rq->pi_dma_addr);
207 rq_ctxt->pi_paddr_lo = lower_32_bits(rq->pi_dma_addr);
209 rq_ctxt->wq_block_hi_pfn =
210 HINIC_RQ_CTXT_WQ_BLOCK_SET(wq_block_pfn_hi, HI_PFN);
212 rq_ctxt->wq_block_lo_pfn = wq_block_pfn_lo;
214 hinic_cpu_to_be32(rq_ctxt, sizeof(*rq_ctxt));
218 * alloc_sq_skb_arr - allocate sq array for saved skb
221 * Return 0 - Success, negative - Failure
223 static int alloc_sq_skb_arr(struct hinic_sq *sq)
225 struct hinic_wq *wq = sq->wq;
228 skb_arr_size = wq->q_depth * sizeof(*sq->saved_skb);
229 sq->saved_skb = vzalloc(skb_arr_size);
237 * free_sq_skb_arr - free sq array for saved skb
240 static void free_sq_skb_arr(struct hinic_sq *sq)
242 vfree(sq->saved_skb);
246 * alloc_rq_skb_arr - allocate rq array for saved skb
247 * @rq: HW Receive Queue
249 * Return 0 - Success, negative - Failure
251 static int alloc_rq_skb_arr(struct hinic_rq *rq)
253 struct hinic_wq *wq = rq->wq;
256 skb_arr_size = wq->q_depth * sizeof(*rq->saved_skb);
257 rq->saved_skb = vzalloc(skb_arr_size);
265 * free_rq_skb_arr - free rq array for saved skb
266 * @rq: HW Receive Queue
268 static void free_rq_skb_arr(struct hinic_rq *rq)
270 vfree(rq->saved_skb);
274 * hinic_init_sq - Initialize HW Send Queue
276 * @hwif: HW Interface for accessing HW
277 * @wq: Work Queue for the data of the SQ
278 * @entry: msix entry for sq
279 * @ci_addr: address for reading the current HW consumer index
280 * @ci_dma_addr: dma address for reading the current HW consumer index
281 * @db_base: doorbell base address
283 * Return 0 - Success, negative - Failure
285 int hinic_init_sq(struct hinic_sq *sq, struct hinic_hwif *hwif,
286 struct hinic_wq *wq, struct msix_entry *entry,
287 void *ci_addr, dma_addr_t ci_dma_addr,
288 void __iomem *db_base)
294 sq->irq = entry->vector;
295 sq->msix_entry = entry->entry;
297 sq->hw_ci_addr = ci_addr;
298 sq->hw_ci_dma_addr = ci_dma_addr;
300 sq->db_base = db_base + SQ_DB_OFF;
302 return alloc_sq_skb_arr(sq);
306 * hinic_clean_sq - Clean HW Send Queue's Resources
309 void hinic_clean_sq(struct hinic_sq *sq)
315 * alloc_rq_cqe - allocate rq completion queue elements
316 * @rq: HW Receive Queue
318 * Return 0 - Success, negative - Failure
320 static int alloc_rq_cqe(struct hinic_rq *rq)
322 struct hinic_hwif *hwif = rq->hwif;
323 struct pci_dev *pdev = hwif->pdev;
324 size_t cqe_dma_size, cqe_size;
325 struct hinic_wq *wq = rq->wq;
328 cqe_size = wq->q_depth * sizeof(*rq->cqe);
329 rq->cqe = vzalloc(cqe_size);
333 cqe_dma_size = wq->q_depth * sizeof(*rq->cqe_dma);
334 rq->cqe_dma = vzalloc(cqe_dma_size);
336 goto err_cqe_dma_arr_alloc;
338 for (i = 0; i < wq->q_depth; i++) {
339 rq->cqe[i] = dma_zalloc_coherent(&pdev->dev,
341 &rq->cqe_dma[i], GFP_KERNEL);
349 for (j = 0; j < i; j++)
350 dma_free_coherent(&pdev->dev, sizeof(*rq->cqe[j]), rq->cqe[j],
355 err_cqe_dma_arr_alloc:
361 * free_rq_cqe - free rq completion queue elements
362 * @rq: HW Receive Queue
364 static void free_rq_cqe(struct hinic_rq *rq)
366 struct hinic_hwif *hwif = rq->hwif;
367 struct pci_dev *pdev = hwif->pdev;
368 struct hinic_wq *wq = rq->wq;
371 for (i = 0; i < wq->q_depth; i++)
372 dma_free_coherent(&pdev->dev, sizeof(*rq->cqe[i]), rq->cqe[i],
380 * hinic_init_rq - Initialize HW Receive Queue
381 * @rq: HW Receive Queue
382 * @hwif: HW Interface for accessing HW
383 * @wq: Work Queue for the data of the RQ
384 * @entry: msix entry for rq
386 * Return 0 - Success, negative - Failure
388 int hinic_init_rq(struct hinic_rq *rq, struct hinic_hwif *hwif,
389 struct hinic_wq *wq, struct msix_entry *entry)
391 struct pci_dev *pdev = hwif->pdev;
399 rq->irq = entry->vector;
400 rq->msix_entry = entry->entry;
402 rq->buf_sz = HINIC_RX_BUF_SZ;
404 err = alloc_rq_skb_arr(rq);
406 dev_err(&pdev->dev, "Failed to allocate rq priv data\n");
410 err = alloc_rq_cqe(rq);
412 dev_err(&pdev->dev, "Failed to allocate rq cqe\n");
413 goto err_alloc_rq_cqe;
416 /* HW requirements: Must be at least 32 bit */
417 pi_size = ALIGN(sizeof(*rq->pi_virt_addr), sizeof(u32));
418 rq->pi_virt_addr = dma_zalloc_coherent(&pdev->dev, pi_size,
419 &rq->pi_dma_addr, GFP_KERNEL);
420 if (!rq->pi_virt_addr) {
421 dev_err(&pdev->dev, "Failed to allocate PI address\n");
437 * hinic_clean_rq - Clean HW Receive Queue's Resources
438 * @rq: HW Receive Queue
440 void hinic_clean_rq(struct hinic_rq *rq)
442 struct hinic_hwif *hwif = rq->hwif;
443 struct pci_dev *pdev = hwif->pdev;
446 pi_size = ALIGN(sizeof(*rq->pi_virt_addr), sizeof(u32));
447 dma_free_coherent(&pdev->dev, pi_size, rq->pi_virt_addr,
455 * hinic_get_sq_free_wqebbs - return number of free wqebbs for use
458 * Return number of free wqebbs
460 int hinic_get_sq_free_wqebbs(struct hinic_sq *sq)
462 struct hinic_wq *wq = sq->wq;
464 return atomic_read(&wq->delta) - 1;
468 * hinic_get_rq_free_wqebbs - return number of free wqebbs for use
471 * Return number of free wqebbs
473 int hinic_get_rq_free_wqebbs(struct hinic_rq *rq)
475 struct hinic_wq *wq = rq->wq;
477 return atomic_read(&wq->delta) - 1;
480 static void sq_prepare_ctrl(struct hinic_sq_ctrl *ctrl, u16 prod_idx,
483 u32 ctrl_size, task_size, bufdesc_size;
485 ctrl_size = SIZE_8BYTES(sizeof(struct hinic_sq_ctrl));
486 task_size = SIZE_8BYTES(sizeof(struct hinic_sq_task));
487 bufdesc_size = nr_descs * sizeof(struct hinic_sq_bufdesc);
488 bufdesc_size = SIZE_8BYTES(bufdesc_size);
490 ctrl->ctrl_info = HINIC_SQ_CTRL_SET(bufdesc_size, BUFDESC_SECT_LEN) |
491 HINIC_SQ_CTRL_SET(task_size, TASKSECT_LEN) |
492 HINIC_SQ_CTRL_SET(SQ_NORMAL_WQE, DATA_FORMAT) |
493 HINIC_SQ_CTRL_SET(ctrl_size, LEN);
495 ctrl->queue_info = HINIC_SQ_CTRL_SET(HINIC_MSS_DEFAULT,
497 HINIC_SQ_CTRL_SET(1, QUEUE_INFO_UC);
500 static void sq_prepare_task(struct hinic_sq_task *task)
506 task->ufo_v6_identify = 0;
508 task->pkt_info4 = HINIC_SQ_TASK_INFO4_SET(HINIC_L2TYPE_ETH, L2TYPE);
513 void hinic_task_set_l2hdr(struct hinic_sq_task *task, u32 len)
515 task->pkt_info0 |= HINIC_SQ_TASK_INFO0_SET(len, L2HDR_LEN);
518 void hinic_task_set_outter_l3(struct hinic_sq_task *task,
519 enum hinic_l3_offload_type l3_type,
522 task->pkt_info2 |= HINIC_SQ_TASK_INFO2_SET(l3_type, OUTER_L3TYPE) |
523 HINIC_SQ_TASK_INFO2_SET(network_len, OUTER_L3LEN);
526 void hinic_task_set_inner_l3(struct hinic_sq_task *task,
527 enum hinic_l3_offload_type l3_type,
530 task->pkt_info0 |= HINIC_SQ_TASK_INFO0_SET(l3_type, INNER_L3TYPE);
531 task->pkt_info1 |= HINIC_SQ_TASK_INFO1_SET(network_len, INNER_L3LEN);
534 void hinic_task_set_tunnel_l4(struct hinic_sq_task *task,
535 enum hinic_l4_tunnel_type l4_type,
538 task->pkt_info2 |= HINIC_SQ_TASK_INFO2_SET(l4_type, TUNNEL_L4TYPE) |
539 HINIC_SQ_TASK_INFO2_SET(tunnel_len, TUNNEL_L4LEN);
542 void hinic_set_cs_inner_l4(struct hinic_sq_task *task, u32 *queue_info,
543 enum hinic_l4_offload_type l4_offload,
544 u32 l4_len, u32 offset)
546 u32 tcp_udp_cs = 0, sctp = 0;
547 u32 mss = HINIC_MSS_DEFAULT;
549 if (l4_offload == TCP_OFFLOAD_ENABLE ||
550 l4_offload == UDP_OFFLOAD_ENABLE)
552 else if (l4_offload == SCTP_OFFLOAD_ENABLE)
555 task->pkt_info0 |= HINIC_SQ_TASK_INFO0_SET(l4_offload, L4_OFFLOAD);
556 task->pkt_info1 |= HINIC_SQ_TASK_INFO1_SET(l4_len, INNER_L4LEN);
558 *queue_info |= HINIC_SQ_CTRL_SET(offset, QUEUE_INFO_PLDOFF) |
559 HINIC_SQ_CTRL_SET(tcp_udp_cs, QUEUE_INFO_TCPUDP_CS) |
560 HINIC_SQ_CTRL_SET(sctp, QUEUE_INFO_SCTP);
562 *queue_info = HINIC_SQ_CTRL_CLEAR(*queue_info, QUEUE_INFO_MSS);
563 *queue_info |= HINIC_SQ_CTRL_SET(mss, QUEUE_INFO_MSS);
566 void hinic_set_tso_inner_l4(struct hinic_sq_task *task, u32 *queue_info,
567 enum hinic_l4_offload_type l4_offload,
568 u32 l4_len, u32 offset, u32 ip_ident, u32 mss)
570 u32 tso = 0, ufo = 0;
572 if (l4_offload == TCP_OFFLOAD_ENABLE)
574 else if (l4_offload == UDP_OFFLOAD_ENABLE)
577 task->ufo_v6_identify = ip_ident;
579 task->pkt_info0 |= HINIC_SQ_TASK_INFO0_SET(l4_offload, L4_OFFLOAD);
580 task->pkt_info0 |= HINIC_SQ_TASK_INFO0_SET(tso || ufo, TSO_FLAG);
581 task->pkt_info1 |= HINIC_SQ_TASK_INFO1_SET(l4_len, INNER_L4LEN);
583 *queue_info |= HINIC_SQ_CTRL_SET(offset, QUEUE_INFO_PLDOFF) |
584 HINIC_SQ_CTRL_SET(tso, QUEUE_INFO_TSO) |
585 HINIC_SQ_CTRL_SET(ufo, QUEUE_INFO_UFO) |
586 HINIC_SQ_CTRL_SET(!!l4_offload, QUEUE_INFO_TCPUDP_CS);
589 *queue_info = HINIC_SQ_CTRL_CLEAR(*queue_info, QUEUE_INFO_MSS);
590 *queue_info |= HINIC_SQ_CTRL_SET(mss, QUEUE_INFO_MSS);
594 * hinic_sq_prepare_wqe - prepare wqe before insert to the queue
596 * @prod_idx: pi value
597 * @sq_wqe: wqe to prepare
598 * @sges: sges for use by the wqe for send for buf addresses
599 * @nr_sges: number of sges
601 void hinic_sq_prepare_wqe(struct hinic_sq *sq, u16 prod_idx,
602 struct hinic_sq_wqe *sq_wqe, struct hinic_sge *sges,
607 sq_prepare_ctrl(&sq_wqe->ctrl, prod_idx, nr_sges);
609 sq_prepare_task(&sq_wqe->task);
611 for (i = 0; i < nr_sges; i++)
612 sq_wqe->buf_descs[i].sge = sges[i];
616 * sq_prepare_db - prepare doorbell to write
618 * @prod_idx: pi value for the doorbell
619 * @cos: cos of the doorbell
623 static u32 sq_prepare_db(struct hinic_sq *sq, u16 prod_idx, unsigned int cos)
625 struct hinic_qp *qp = container_of(sq, struct hinic_qp, sq);
626 u8 hi_prod_idx = SQ_DB_PI_HI(SQ_MASKED_IDX(sq, prod_idx));
628 /* Data should be written to HW in Big Endian Format */
629 return cpu_to_be32(HINIC_SQ_DB_INFO_SET(hi_prod_idx, PI_HI) |
630 HINIC_SQ_DB_INFO_SET(HINIC_DB_SQ_TYPE, TYPE) |
631 HINIC_SQ_DB_INFO_SET(HINIC_DATA_PATH, PATH) |
632 HINIC_SQ_DB_INFO_SET(cos, COS) |
633 HINIC_SQ_DB_INFO_SET(qp->q_id, QID));
637 * hinic_sq_write_db- write doorbell
639 * @prod_idx: pi value for the doorbell
640 * @wqe_size: wqe size
641 * @cos: cos of the wqe
643 void hinic_sq_write_db(struct hinic_sq *sq, u16 prod_idx, unsigned int wqe_size,
646 struct hinic_wq *wq = sq->wq;
648 /* increment prod_idx to the next */
649 prod_idx += ALIGN(wqe_size, wq->wqebb_size) / wq->wqebb_size;
651 wmb(); /* Write all before the doorbell */
653 writel(sq_prepare_db(sq, prod_idx, cos), SQ_DB_ADDR(sq, prod_idx));
657 * hinic_sq_get_wqe - get wqe ptr in the current pi and update the pi
658 * @sq: sq to get wqe from
659 * @wqe_size: wqe size
660 * @prod_idx: returned pi
664 struct hinic_sq_wqe *hinic_sq_get_wqe(struct hinic_sq *sq,
665 unsigned int wqe_size, u16 *prod_idx)
667 struct hinic_hw_wqe *hw_wqe = hinic_get_wqe(sq->wq, wqe_size,
673 return &hw_wqe->sq_wqe;
677 * hinic_sq_return_wqe - return the wqe to the sq
679 * @wqe_size: the size of the wqe
681 void hinic_sq_return_wqe(struct hinic_sq *sq, unsigned int wqe_size)
683 hinic_return_wqe(sq->wq, wqe_size);
687 * hinic_sq_write_wqe - write the wqe to the sq
689 * @prod_idx: pi of the wqe
690 * @sq_wqe: the wqe to write
692 * @wqe_size: the size of the wqe
694 void hinic_sq_write_wqe(struct hinic_sq *sq, u16 prod_idx,
695 struct hinic_sq_wqe *sq_wqe,
696 struct sk_buff *skb, unsigned int wqe_size)
698 struct hinic_hw_wqe *hw_wqe = (struct hinic_hw_wqe *)sq_wqe;
700 sq->saved_skb[prod_idx] = skb;
702 /* The data in the HW should be in Big Endian Format */
703 hinic_cpu_to_be32(sq_wqe, wqe_size);
705 hinic_write_wqe(sq->wq, hw_wqe, wqe_size);
709 * hinic_sq_read_wqebb - read wqe ptr in the current ci and update the ci, the
710 * wqe only have one wqebb
712 * @skb: return skb that was saved
713 * @wqe_size: the wqe size ptr
714 * @cons_idx: consumer index of the wqe
716 * Return wqe in ci position
718 struct hinic_sq_wqe *hinic_sq_read_wqebb(struct hinic_sq *sq,
719 struct sk_buff **skb,
720 unsigned int *wqe_size, u16 *cons_idx)
722 struct hinic_hw_wqe *hw_wqe;
723 struct hinic_sq_wqe *sq_wqe;
724 struct hinic_sq_ctrl *ctrl;
725 unsigned int buf_sect_len;
728 /* read the ctrl section for getting wqe size */
729 hw_wqe = hinic_read_wqe(sq->wq, sizeof(*ctrl), cons_idx);
733 *skb = sq->saved_skb[*cons_idx];
735 sq_wqe = &hw_wqe->sq_wqe;
736 ctrl = &sq_wqe->ctrl;
737 ctrl_info = be32_to_cpu(ctrl->ctrl_info);
738 buf_sect_len = HINIC_SQ_CTRL_GET(ctrl_info, BUFDESC_SECT_LEN);
740 *wqe_size = sizeof(*ctrl) + sizeof(sq_wqe->task);
741 *wqe_size += SECT_SIZE_FROM_8BYTES(buf_sect_len);
742 *wqe_size = ALIGN(*wqe_size, sq->wq->wqebb_size);
744 return &hw_wqe->sq_wqe;
748 * hinic_sq_read_wqe - read wqe ptr in the current ci and update the ci
750 * @skb: return skb that was saved
751 * @wqe_size: the size of the wqe
752 * @cons_idx: consumer index of the wqe
754 * Return wqe in ci position
756 struct hinic_sq_wqe *hinic_sq_read_wqe(struct hinic_sq *sq,
757 struct sk_buff **skb,
758 unsigned int wqe_size, u16 *cons_idx)
760 struct hinic_hw_wqe *hw_wqe;
762 hw_wqe = hinic_read_wqe(sq->wq, wqe_size, cons_idx);
763 *skb = sq->saved_skb[*cons_idx];
765 return &hw_wqe->sq_wqe;
769 * hinic_sq_put_wqe - release the ci for new wqes
771 * @wqe_size: the size of the wqe
773 void hinic_sq_put_wqe(struct hinic_sq *sq, unsigned int wqe_size)
775 hinic_put_wqe(sq->wq, wqe_size);
779 * hinic_sq_get_sges - get sges from the wqe
780 * @sq_wqe: wqe to get the sges from its buffer addresses
781 * @sges: returned sges
782 * @nr_sges: number sges to return
784 void hinic_sq_get_sges(struct hinic_sq_wqe *sq_wqe, struct hinic_sge *sges,
789 for (i = 0; i < nr_sges && i < HINIC_MAX_SQ_BUFDESCS; i++) {
790 sges[i] = sq_wqe->buf_descs[i].sge;
791 hinic_be32_to_cpu(&sges[i], sizeof(sges[i]));
796 * hinic_rq_get_wqe - get wqe ptr in the current pi and update the pi
797 * @rq: rq to get wqe from
798 * @wqe_size: wqe size
799 * @prod_idx: returned pi
803 struct hinic_rq_wqe *hinic_rq_get_wqe(struct hinic_rq *rq,
804 unsigned int wqe_size, u16 *prod_idx)
806 struct hinic_hw_wqe *hw_wqe = hinic_get_wqe(rq->wq, wqe_size,
812 return &hw_wqe->rq_wqe;
816 * hinic_rq_write_wqe - write the wqe to the rq
818 * @prod_idx: pi of the wqe
819 * @rq_wqe: the wqe to write
822 void hinic_rq_write_wqe(struct hinic_rq *rq, u16 prod_idx,
823 struct hinic_rq_wqe *rq_wqe, struct sk_buff *skb)
825 struct hinic_hw_wqe *hw_wqe = (struct hinic_hw_wqe *)rq_wqe;
827 rq->saved_skb[prod_idx] = skb;
829 /* The data in the HW should be in Big Endian Format */
830 hinic_cpu_to_be32(rq_wqe, sizeof(*rq_wqe));
832 hinic_write_wqe(rq->wq, hw_wqe, sizeof(*rq_wqe));
836 * hinic_rq_read_wqe - read wqe ptr in the current ci and update the ci
838 * @wqe_size: the size of the wqe
839 * @skb: return saved skb
840 * @cons_idx: consumer index of the wqe
842 * Return wqe in ci position
844 struct hinic_rq_wqe *hinic_rq_read_wqe(struct hinic_rq *rq,
845 unsigned int wqe_size,
846 struct sk_buff **skb, u16 *cons_idx)
848 struct hinic_hw_wqe *hw_wqe;
849 struct hinic_rq_cqe *cqe;
853 hw_wqe = hinic_read_wqe(rq->wq, wqe_size, cons_idx);
857 cqe = rq->cqe[*cons_idx];
859 status = be32_to_cpu(cqe->status);
861 rx_done = HINIC_RQ_CQE_STATUS_GET(status, RXDONE);
865 *skb = rq->saved_skb[*cons_idx];
867 return &hw_wqe->rq_wqe;
871 * hinic_rq_read_next_wqe - increment ci and read the wqe in ci position
873 * @wqe_size: the size of the wqe
874 * @skb: return saved skb
875 * @cons_idx: consumer index in the wq
877 * Return wqe in incremented ci position
879 struct hinic_rq_wqe *hinic_rq_read_next_wqe(struct hinic_rq *rq,
880 unsigned int wqe_size,
881 struct sk_buff **skb,
884 struct hinic_wq *wq = rq->wq;
885 struct hinic_hw_wqe *hw_wqe;
886 unsigned int num_wqebbs;
888 wqe_size = ALIGN(wqe_size, wq->wqebb_size);
889 num_wqebbs = wqe_size / wq->wqebb_size;
891 *cons_idx = RQ_MASKED_IDX(rq, *cons_idx + num_wqebbs);
893 *skb = rq->saved_skb[*cons_idx];
895 hw_wqe = hinic_read_wqe_direct(wq, *cons_idx);
897 return &hw_wqe->rq_wqe;
901 * hinic_put_wqe - release the ci for new wqes
903 * @cons_idx: consumer index of the wqe
904 * @wqe_size: the size of the wqe
906 void hinic_rq_put_wqe(struct hinic_rq *rq, u16 cons_idx,
907 unsigned int wqe_size)
909 struct hinic_rq_cqe *cqe = rq->cqe[cons_idx];
910 u32 status = be32_to_cpu(cqe->status);
912 status = HINIC_RQ_CQE_STATUS_CLEAR(status, RXDONE);
914 /* Rx WQE size is 1 WQEBB, no wq shadow*/
915 cqe->status = cpu_to_be32(status);
917 wmb(); /* clear done flag */
919 hinic_put_wqe(rq->wq, wqe_size);
923 * hinic_rq_get_sge - get sge from the wqe
925 * @rq_wqe: wqe to get the sge from its buf address
926 * @cons_idx: consumer index
929 void hinic_rq_get_sge(struct hinic_rq *rq, struct hinic_rq_wqe *rq_wqe,
930 u16 cons_idx, struct hinic_sge *sge)
932 struct hinic_rq_cqe *cqe = rq->cqe[cons_idx];
933 u32 len = be32_to_cpu(cqe->len);
935 sge->hi_addr = be32_to_cpu(rq_wqe->buf_desc.hi_addr);
936 sge->lo_addr = be32_to_cpu(rq_wqe->buf_desc.lo_addr);
937 sge->len = HINIC_RQ_CQE_SGE_GET(len, LEN);
941 * hinic_rq_prepare_wqe - prepare wqe before insert to the queue
943 * @prod_idx: pi value
945 * @sge: sge for use by the wqe for recv buf address
947 void hinic_rq_prepare_wqe(struct hinic_rq *rq, u16 prod_idx,
948 struct hinic_rq_wqe *rq_wqe, struct hinic_sge *sge)
950 struct hinic_rq_cqe_sect *cqe_sect = &rq_wqe->cqe_sect;
951 struct hinic_rq_bufdesc *buf_desc = &rq_wqe->buf_desc;
952 struct hinic_rq_cqe *cqe = rq->cqe[prod_idx];
953 struct hinic_rq_ctrl *ctrl = &rq_wqe->ctrl;
954 dma_addr_t cqe_dma = rq->cqe_dma[prod_idx];
957 HINIC_RQ_CTRL_SET(SIZE_8BYTES(sizeof(*ctrl)), LEN) |
958 HINIC_RQ_CTRL_SET(SIZE_8BYTES(sizeof(*cqe_sect)),
960 HINIC_RQ_CTRL_SET(SIZE_8BYTES(sizeof(*buf_desc)),
962 HINIC_RQ_CTRL_SET(RQ_COMPLETE_SGE, COMPLETE_FORMAT);
964 hinic_set_sge(&cqe_sect->sge, cqe_dma, sizeof(*cqe));
966 buf_desc->hi_addr = sge->hi_addr;
967 buf_desc->lo_addr = sge->lo_addr;
971 * hinic_rq_update - update pi of the rq
973 * @prod_idx: pi value
975 void hinic_rq_update(struct hinic_rq *rq, u16 prod_idx)
977 *rq->pi_virt_addr = cpu_to_be16(RQ_MASKED_IDX(rq, prod_idx + 1));