1 // SPDX-License-Identifier: GPL-2.0-only
3 * Huawei HiNIC PCI Express Linux driver
4 * Copyright(c) 2017 Huawei Technologies Co., Ltd
7 #include <linux/kernel.h>
8 #include <linux/types.h>
9 #include <linux/errno.h>
10 #include <linux/pci.h>
11 #include <linux/device.h>
12 #include <linux/workqueue.h>
13 #include <linux/interrupt.h>
14 #include <linux/slab.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/log2.h>
17 #include <asm/byteorder.h>
18 #include <asm/barrier.h>
20 #include "hinic_hw_csr.h"
21 #include "hinic_hw_if.h"
22 #include "hinic_hw_eqs.h"
24 #define HINIC_EQS_WQ_NAME "hinic_eqs"
26 #define GET_EQ_NUM_PAGES(eq, pg_size) \
27 (ALIGN((eq)->q_len * (eq)->elem_size, pg_size) / (pg_size))
29 #define GET_EQ_NUM_ELEMS_IN_PG(eq, pg_size) ((pg_size) / (eq)->elem_size)
31 #define EQ_CONS_IDX_REG_ADDR(eq) (((eq)->type == HINIC_AEQ) ? \
32 HINIC_CSR_AEQ_CONS_IDX_ADDR((eq)->q_id) : \
33 HINIC_CSR_CEQ_CONS_IDX_ADDR((eq)->q_id))
35 #define EQ_PROD_IDX_REG_ADDR(eq) (((eq)->type == HINIC_AEQ) ? \
36 HINIC_CSR_AEQ_PROD_IDX_ADDR((eq)->q_id) : \
37 HINIC_CSR_CEQ_PROD_IDX_ADDR((eq)->q_id))
39 #define EQ_HI_PHYS_ADDR_REG(eq, pg_num) (((eq)->type == HINIC_AEQ) ? \
40 HINIC_CSR_AEQ_HI_PHYS_ADDR_REG((eq)->q_id, pg_num) : \
41 HINIC_CSR_CEQ_HI_PHYS_ADDR_REG((eq)->q_id, pg_num))
43 #define EQ_LO_PHYS_ADDR_REG(eq, pg_num) (((eq)->type == HINIC_AEQ) ? \
44 HINIC_CSR_AEQ_LO_PHYS_ADDR_REG((eq)->q_id, pg_num) : \
45 HINIC_CSR_CEQ_LO_PHYS_ADDR_REG((eq)->q_id, pg_num))
47 #define GET_EQ_ELEMENT(eq, idx) \
48 ((eq)->virt_addr[(idx) / (eq)->num_elem_in_pg] + \
49 (((idx) & ((eq)->num_elem_in_pg - 1)) * (eq)->elem_size))
51 #define GET_AEQ_ELEM(eq, idx) ((struct hinic_aeq_elem *) \
52 GET_EQ_ELEMENT(eq, idx))
54 #define GET_CEQ_ELEM(eq, idx) ((u32 *) \
55 GET_EQ_ELEMENT(eq, idx))
57 #define GET_CURR_AEQ_ELEM(eq) GET_AEQ_ELEM(eq, (eq)->cons_idx)
59 #define GET_CURR_CEQ_ELEM(eq) GET_CEQ_ELEM(eq, (eq)->cons_idx)
61 #define PAGE_IN_4K(page_size) ((page_size) >> 12)
62 #define EQ_SET_HW_PAGE_SIZE_VAL(eq) (ilog2(PAGE_IN_4K((eq)->page_size)))
64 #define ELEMENT_SIZE_IN_32B(eq) (((eq)->elem_size) >> 5)
65 #define EQ_SET_HW_ELEM_SIZE_VAL(eq) (ilog2(ELEMENT_SIZE_IN_32B(eq)))
67 #define EQ_MAX_PAGES 8
69 #define CEQE_TYPE_SHIFT 23
70 #define CEQE_TYPE_MASK 0x7
72 #define CEQE_TYPE(ceqe) (((ceqe) >> CEQE_TYPE_SHIFT) & \
75 #define CEQE_DATA_MASK 0x3FFFFFF
76 #define CEQE_DATA(ceqe) ((ceqe) & CEQE_DATA_MASK)
78 #define aeq_to_aeqs(eq) \
79 container_of((eq) - (eq)->q_id, struct hinic_aeqs, aeq[0])
81 #define ceq_to_ceqs(eq) \
82 container_of((eq) - (eq)->q_id, struct hinic_ceqs, ceq[0])
84 #define work_to_aeq_work(work) \
85 container_of(work, struct hinic_eq_work, work)
87 #define DMA_ATTR_AEQ_DEFAULT 0
88 #define DMA_ATTR_CEQ_DEFAULT 0
91 #define THRESH_CEQ_DEFAULT 0
104 * hinic_aeq_register_hw_cb - register AEQ callback for specific event
105 * @aeqs: pointer to Async eqs of the chip
106 * @event: aeq event to register callback for it
107 * @handle: private data will be used by the callback
108 * @hw_handler: callback function
110 void hinic_aeq_register_hw_cb(struct hinic_aeqs *aeqs,
111 enum hinic_aeq_type event, void *handle,
112 void (*hwe_handler)(void *handle, void *data,
115 struct hinic_hw_event_cb *hwe_cb = &aeqs->hwe_cb[event];
117 hwe_cb->hwe_handler = hwe_handler;
118 hwe_cb->handle = handle;
119 hwe_cb->hwe_state = HINIC_EQE_ENABLED;
123 * hinic_aeq_unregister_hw_cb - unregister the AEQ callback for specific event
124 * @aeqs: pointer to Async eqs of the chip
125 * @event: aeq event to unregister callback for it
127 void hinic_aeq_unregister_hw_cb(struct hinic_aeqs *aeqs,
128 enum hinic_aeq_type event)
130 struct hinic_hw_event_cb *hwe_cb = &aeqs->hwe_cb[event];
132 hwe_cb->hwe_state &= ~HINIC_EQE_ENABLED;
134 while (hwe_cb->hwe_state & HINIC_EQE_RUNNING)
137 hwe_cb->hwe_handler = NULL;
141 * hinic_ceq_register_cb - register CEQ callback for specific event
142 * @ceqs: pointer to Completion eqs part of the chip
143 * @event: ceq event to register callback for it
144 * @handle: private data will be used by the callback
145 * @handler: callback function
147 void hinic_ceq_register_cb(struct hinic_ceqs *ceqs,
148 enum hinic_ceq_type event, void *handle,
149 void (*handler)(void *handle, u32 ceqe_data))
151 struct hinic_ceq_cb *ceq_cb = &ceqs->ceq_cb[event];
153 ceq_cb->handler = handler;
154 ceq_cb->handle = handle;
155 ceq_cb->ceqe_state = HINIC_EQE_ENABLED;
159 * hinic_ceq_unregister_cb - unregister the CEQ callback for specific event
160 * @ceqs: pointer to Completion eqs part of the chip
161 * @event: ceq event to unregister callback for it
163 void hinic_ceq_unregister_cb(struct hinic_ceqs *ceqs,
164 enum hinic_ceq_type event)
166 struct hinic_ceq_cb *ceq_cb = &ceqs->ceq_cb[event];
168 ceq_cb->ceqe_state &= ~HINIC_EQE_ENABLED;
170 while (ceq_cb->ceqe_state & HINIC_EQE_RUNNING)
173 ceq_cb->handler = NULL;
176 static u8 eq_cons_idx_checksum_set(u32 val)
181 for (idx = 0; idx < 32; idx += 4)
182 checksum ^= ((val >> idx) & 0xF);
184 return (checksum & 0xF);
188 * eq_update_ci - update the HW cons idx of event queue
189 * @eq: the event queue to update the cons idx for
191 static void eq_update_ci(struct hinic_eq *eq)
193 u32 val, addr = EQ_CONS_IDX_REG_ADDR(eq);
195 /* Read Modify Write */
196 val = hinic_hwif_read_reg(eq->hwif, addr);
198 val = HINIC_EQ_CI_CLEAR(val, IDX) &
199 HINIC_EQ_CI_CLEAR(val, WRAPPED) &
200 HINIC_EQ_CI_CLEAR(val, INT_ARMED) &
201 HINIC_EQ_CI_CLEAR(val, XOR_CHKSUM);
203 val |= HINIC_EQ_CI_SET(eq->cons_idx, IDX) |
204 HINIC_EQ_CI_SET(eq->wrapped, WRAPPED) |
205 HINIC_EQ_CI_SET(EQ_ARMED, INT_ARMED);
207 val |= HINIC_EQ_CI_SET(eq_cons_idx_checksum_set(val), XOR_CHKSUM);
209 hinic_hwif_write_reg(eq->hwif, addr, val);
213 * aeq_irq_handler - handler for the AEQ event
214 * @eq: the Async Event Queue that received the event
216 static void aeq_irq_handler(struct hinic_eq *eq)
218 struct hinic_aeqs *aeqs = aeq_to_aeqs(eq);
219 struct hinic_hwif *hwif = aeqs->hwif;
220 struct pci_dev *pdev = hwif->pdev;
221 struct hinic_aeq_elem *aeqe_curr;
222 struct hinic_hw_event_cb *hwe_cb;
223 enum hinic_aeq_type event;
224 unsigned long eqe_state;
228 for (i = 0; i < eq->q_len; i++) {
229 aeqe_curr = GET_CURR_AEQ_ELEM(eq);
231 /* Data in HW is in Big endian Format */
232 aeqe_desc = be32_to_cpu(aeqe_curr->desc);
234 /* HW toggles the wrapped bit, when it adds eq element */
235 if (HINIC_EQ_ELEM_DESC_GET(aeqe_desc, WRAPPED) == eq->wrapped)
238 event = HINIC_EQ_ELEM_DESC_GET(aeqe_desc, TYPE);
239 if (event >= HINIC_MAX_AEQ_EVENTS) {
240 dev_err(&pdev->dev, "Unknown AEQ Event %d\n", event);
244 if (!HINIC_EQ_ELEM_DESC_GET(aeqe_desc, SRC)) {
245 hwe_cb = &aeqs->hwe_cb[event];
247 size = HINIC_EQ_ELEM_DESC_GET(aeqe_desc, SIZE);
249 eqe_state = cmpxchg(&hwe_cb->hwe_state,
253 if ((eqe_state == HINIC_EQE_ENABLED) &&
254 (hwe_cb->hwe_handler))
255 hwe_cb->hwe_handler(hwe_cb->handle,
256 aeqe_curr->data, size);
258 dev_err(&pdev->dev, "Unhandled AEQ Event %d\n",
261 hwe_cb->hwe_state &= ~HINIC_EQE_RUNNING;
266 if (eq->cons_idx == eq->q_len) {
268 eq->wrapped = !eq->wrapped;
274 * ceq_event_handler - handler for the ceq events
275 * @ceqs: ceqs part of the chip
276 * @ceqe: ceq element that describes the event
278 static void ceq_event_handler(struct hinic_ceqs *ceqs, u32 ceqe)
280 struct hinic_hwif *hwif = ceqs->hwif;
281 struct pci_dev *pdev = hwif->pdev;
282 struct hinic_ceq_cb *ceq_cb;
283 enum hinic_ceq_type event;
284 unsigned long eqe_state;
286 event = CEQE_TYPE(ceqe);
287 if (event >= HINIC_MAX_CEQ_EVENTS) {
288 dev_err(&pdev->dev, "Unknown CEQ event, event = %d\n", event);
292 ceq_cb = &ceqs->ceq_cb[event];
294 eqe_state = cmpxchg(&ceq_cb->ceqe_state,
296 HINIC_EQE_ENABLED | HINIC_EQE_RUNNING);
298 if ((eqe_state == HINIC_EQE_ENABLED) && (ceq_cb->handler))
299 ceq_cb->handler(ceq_cb->handle, CEQE_DATA(ceqe));
301 dev_err(&pdev->dev, "Unhandled CEQ Event %d\n", event);
303 ceq_cb->ceqe_state &= ~HINIC_EQE_RUNNING;
307 * ceq_irq_handler - handler for the CEQ event
308 * @eq: the Completion Event Queue that received the event
310 static void ceq_irq_handler(struct hinic_eq *eq)
312 struct hinic_ceqs *ceqs = ceq_to_ceqs(eq);
316 for (i = 0; i < eq->q_len; i++) {
317 ceqe = *(GET_CURR_CEQ_ELEM(eq));
319 /* Data in HW is in Big endian Format */
320 ceqe = be32_to_cpu(ceqe);
322 /* HW toggles the wrapped bit, when it adds eq element event */
323 if (HINIC_EQ_ELEM_DESC_GET(ceqe, WRAPPED) == eq->wrapped)
326 ceq_event_handler(ceqs, ceqe);
330 if (eq->cons_idx == eq->q_len) {
332 eq->wrapped = !eq->wrapped;
338 * eq_irq_handler - handler for the EQ event
339 * @data: the Event Queue that received the event
341 static void eq_irq_handler(void *data)
343 struct hinic_eq *eq = data;
345 if (eq->type == HINIC_AEQ)
347 else if (eq->type == HINIC_CEQ)
354 * eq_irq_work - the work of the EQ that received the event
355 * @work: the work struct that is associated with the EQ
357 static void eq_irq_work(struct work_struct *work)
359 struct hinic_eq_work *aeq_work = work_to_aeq_work(work);
360 struct hinic_eq *aeq;
362 aeq = aeq_work->data;
367 * ceq_tasklet - the tasklet of the EQ that received the event
370 static void ceq_tasklet(unsigned long ceq_data)
372 struct hinic_eq *ceq = (struct hinic_eq *)ceq_data;
378 * aeq_interrupt - aeq interrupt handler
380 * @data: the Async Event Queue that collected the event
382 static irqreturn_t aeq_interrupt(int irq, void *data)
384 struct hinic_eq_work *aeq_work;
385 struct hinic_eq *aeq = data;
386 struct hinic_aeqs *aeqs;
388 /* clear resend timer cnt register */
389 hinic_msix_attr_cnt_clear(aeq->hwif, aeq->msix_entry.entry);
391 aeq_work = &aeq->aeq_work;
392 aeq_work->data = aeq;
394 aeqs = aeq_to_aeqs(aeq);
395 queue_work(aeqs->workq, &aeq_work->work);
401 * ceq_interrupt - ceq interrupt handler
403 * @data: the Completion Event Queue that collected the event
405 static irqreturn_t ceq_interrupt(int irq, void *data)
407 struct hinic_eq *ceq = data;
409 /* clear resend timer cnt register */
410 hinic_msix_attr_cnt_clear(ceq->hwif, ceq->msix_entry.entry);
412 tasklet_schedule(&ceq->ceq_tasklet);
417 static void set_ctrl0(struct hinic_eq *eq)
419 struct msix_entry *msix_entry = &eq->msix_entry;
420 enum hinic_eq_type type = eq->type;
421 u32 addr, val, ctrl0;
423 if (type == HINIC_AEQ) {
425 addr = HINIC_CSR_AEQ_CTRL_0_ADDR(eq->q_id);
427 val = hinic_hwif_read_reg(eq->hwif, addr);
429 val = HINIC_AEQ_CTRL_0_CLEAR(val, INT_IDX) &
430 HINIC_AEQ_CTRL_0_CLEAR(val, DMA_ATTR) &
431 HINIC_AEQ_CTRL_0_CLEAR(val, PCI_INTF_IDX) &
432 HINIC_AEQ_CTRL_0_CLEAR(val, INT_MODE);
434 ctrl0 = HINIC_AEQ_CTRL_0_SET(msix_entry->entry, INT_IDX) |
435 HINIC_AEQ_CTRL_0_SET(DMA_ATTR_AEQ_DEFAULT, DMA_ATTR) |
436 HINIC_AEQ_CTRL_0_SET(HINIC_HWIF_PCI_INTF(eq->hwif),
438 HINIC_AEQ_CTRL_0_SET(EQ_INT_MODE_ARMED, INT_MODE);
442 hinic_hwif_write_reg(eq->hwif, addr, val);
443 } else if (type == HINIC_CEQ) {
445 addr = HINIC_CSR_CEQ_CTRL_0_ADDR(eq->q_id);
447 val = hinic_hwif_read_reg(eq->hwif, addr);
449 val = HINIC_CEQ_CTRL_0_CLEAR(val, INTR_IDX) &
450 HINIC_CEQ_CTRL_0_CLEAR(val, DMA_ATTR) &
451 HINIC_CEQ_CTRL_0_CLEAR(val, KICK_THRESH) &
452 HINIC_CEQ_CTRL_0_CLEAR(val, PCI_INTF_IDX) &
453 HINIC_CEQ_CTRL_0_CLEAR(val, INTR_MODE);
455 ctrl0 = HINIC_CEQ_CTRL_0_SET(msix_entry->entry, INTR_IDX) |
456 HINIC_CEQ_CTRL_0_SET(DMA_ATTR_CEQ_DEFAULT, DMA_ATTR) |
457 HINIC_CEQ_CTRL_0_SET(THRESH_CEQ_DEFAULT, KICK_THRESH) |
458 HINIC_CEQ_CTRL_0_SET(HINIC_HWIF_PCI_INTF(eq->hwif),
460 HINIC_CEQ_CTRL_0_SET(EQ_INT_MODE_ARMED, INTR_MODE);
464 hinic_hwif_write_reg(eq->hwif, addr, val);
468 static void set_ctrl1(struct hinic_eq *eq)
470 enum hinic_eq_type type = eq->type;
471 u32 page_size_val, elem_size;
472 u32 addr, val, ctrl1;
474 if (type == HINIC_AEQ) {
476 addr = HINIC_CSR_AEQ_CTRL_1_ADDR(eq->q_id);
478 page_size_val = EQ_SET_HW_PAGE_SIZE_VAL(eq);
479 elem_size = EQ_SET_HW_ELEM_SIZE_VAL(eq);
481 val = hinic_hwif_read_reg(eq->hwif, addr);
483 val = HINIC_AEQ_CTRL_1_CLEAR(val, LEN) &
484 HINIC_AEQ_CTRL_1_CLEAR(val, ELEM_SIZE) &
485 HINIC_AEQ_CTRL_1_CLEAR(val, PAGE_SIZE);
487 ctrl1 = HINIC_AEQ_CTRL_1_SET(eq->q_len, LEN) |
488 HINIC_AEQ_CTRL_1_SET(elem_size, ELEM_SIZE) |
489 HINIC_AEQ_CTRL_1_SET(page_size_val, PAGE_SIZE);
493 hinic_hwif_write_reg(eq->hwif, addr, val);
494 } else if (type == HINIC_CEQ) {
496 addr = HINIC_CSR_CEQ_CTRL_1_ADDR(eq->q_id);
498 page_size_val = EQ_SET_HW_PAGE_SIZE_VAL(eq);
500 val = hinic_hwif_read_reg(eq->hwif, addr);
502 val = HINIC_CEQ_CTRL_1_CLEAR(val, LEN) &
503 HINIC_CEQ_CTRL_1_CLEAR(val, PAGE_SIZE);
505 ctrl1 = HINIC_CEQ_CTRL_1_SET(eq->q_len, LEN) |
506 HINIC_CEQ_CTRL_1_SET(page_size_val, PAGE_SIZE);
510 hinic_hwif_write_reg(eq->hwif, addr, val);
515 * set_eq_ctrls - setting eq's ctrl registers
516 * @eq: the Event Queue for setting
518 static void set_eq_ctrls(struct hinic_eq *eq)
525 * aeq_elements_init - initialize all the elements in the aeq
526 * @eq: the Async Event Queue
527 * @init_val: value to initialize the elements with it
529 static void aeq_elements_init(struct hinic_eq *eq, u32 init_val)
531 struct hinic_aeq_elem *aeqe;
534 for (i = 0; i < eq->q_len; i++) {
535 aeqe = GET_AEQ_ELEM(eq, i);
536 aeqe->desc = cpu_to_be32(init_val);
539 wmb(); /* Write the initilzation values */
543 * ceq_elements_init - Initialize all the elements in the ceq
544 * @eq: the event queue
545 * @init_val: value to init with it the elements
547 static void ceq_elements_init(struct hinic_eq *eq, u32 init_val)
552 for (i = 0; i < eq->q_len; i++) {
553 ceqe = GET_CEQ_ELEM(eq, i);
554 *(ceqe) = cpu_to_be32(init_val);
557 wmb(); /* Write the initilzation values */
561 * alloc_eq_pages - allocate the pages for the queue
562 * @eq: the event queue
564 * Return 0 - Success, Negative - Failure
566 static int alloc_eq_pages(struct hinic_eq *eq)
568 struct hinic_hwif *hwif = eq->hwif;
569 struct pci_dev *pdev = hwif->pdev;
570 u32 init_val, addr, val;
574 addr_size = eq->num_pages * sizeof(*eq->dma_addr);
575 eq->dma_addr = devm_kzalloc(&pdev->dev, addr_size, GFP_KERNEL);
579 addr_size = eq->num_pages * sizeof(*eq->virt_addr);
580 eq->virt_addr = devm_kzalloc(&pdev->dev, addr_size, GFP_KERNEL);
581 if (!eq->virt_addr) {
583 goto err_virt_addr_alloc;
586 for (pg = 0; pg < eq->num_pages; pg++) {
587 eq->virt_addr[pg] = dma_alloc_coherent(&pdev->dev,
591 if (!eq->virt_addr[pg]) {
596 addr = EQ_HI_PHYS_ADDR_REG(eq, pg);
597 val = upper_32_bits(eq->dma_addr[pg]);
599 hinic_hwif_write_reg(hwif, addr, val);
601 addr = EQ_LO_PHYS_ADDR_REG(eq, pg);
602 val = lower_32_bits(eq->dma_addr[pg]);
604 hinic_hwif_write_reg(hwif, addr, val);
607 init_val = HINIC_EQ_ELEM_DESC_SET(eq->wrapped, WRAPPED);
609 if (eq->type == HINIC_AEQ)
610 aeq_elements_init(eq, init_val);
611 else if (eq->type == HINIC_CEQ)
612 ceq_elements_init(eq, init_val);
618 dma_free_coherent(&pdev->dev, eq->page_size,
622 devm_kfree(&pdev->dev, eq->virt_addr);
625 devm_kfree(&pdev->dev, eq->dma_addr);
630 * free_eq_pages - free the pages of the queue
631 * @eq: the Event Queue
633 static void free_eq_pages(struct hinic_eq *eq)
635 struct hinic_hwif *hwif = eq->hwif;
636 struct pci_dev *pdev = hwif->pdev;
639 for (pg = 0; pg < eq->num_pages; pg++)
640 dma_free_coherent(&pdev->dev, eq->page_size,
644 devm_kfree(&pdev->dev, eq->virt_addr);
645 devm_kfree(&pdev->dev, eq->dma_addr);
649 * init_eq - initialize Event Queue
650 * @eq: the event queue
651 * @hwif: the HW interface of a PCI function device
652 * @type: the type of the event queue, aeq or ceq
653 * @q_id: Queue id number
654 * @q_len: the number of EQ elements
655 * @page_size: the page size of the pages in the event queue
656 * @entry: msix entry associated with the event queue
658 * Return 0 - Success, Negative - Failure
660 static int init_eq(struct hinic_eq *eq, struct hinic_hwif *hwif,
661 enum hinic_eq_type type, int q_id, u32 q_len, u32 page_size,
662 struct msix_entry entry)
664 struct pci_dev *pdev = hwif->pdev;
671 eq->page_size = page_size;
673 /* Clear PI and CI, also clear the ARM bit */
674 hinic_hwif_write_reg(eq->hwif, EQ_CONS_IDX_REG_ADDR(eq), 0);
675 hinic_hwif_write_reg(eq->hwif, EQ_PROD_IDX_REG_ADDR(eq), 0);
680 if (type == HINIC_AEQ) {
681 eq->elem_size = HINIC_AEQE_SIZE;
682 } else if (type == HINIC_CEQ) {
683 eq->elem_size = HINIC_CEQE_SIZE;
685 dev_err(&pdev->dev, "Invalid EQ type\n");
689 eq->num_pages = GET_EQ_NUM_PAGES(eq, page_size);
690 eq->num_elem_in_pg = GET_EQ_NUM_ELEMS_IN_PG(eq, page_size);
692 eq->msix_entry = entry;
694 if (eq->num_elem_in_pg & (eq->num_elem_in_pg - 1)) {
695 dev_err(&pdev->dev, "num elements in eq page != power of 2\n");
699 if (eq->num_pages > EQ_MAX_PAGES) {
700 dev_err(&pdev->dev, "too many pages for eq\n");
707 err = alloc_eq_pages(eq);
709 dev_err(&pdev->dev, "Failed to allocate pages for eq\n");
713 if (type == HINIC_AEQ) {
714 struct hinic_eq_work *aeq_work = &eq->aeq_work;
716 INIT_WORK(&aeq_work->work, eq_irq_work);
717 } else if (type == HINIC_CEQ) {
718 tasklet_init(&eq->ceq_tasklet, ceq_tasklet,
722 /* set the attributes of the msix entry */
723 hinic_msix_attr_set(eq->hwif, eq->msix_entry.entry,
724 HINIC_EQ_MSIX_PENDING_LIMIT_DEFAULT,
725 HINIC_EQ_MSIX_COALESC_TIMER_DEFAULT,
726 HINIC_EQ_MSIX_LLI_TIMER_DEFAULT,
727 HINIC_EQ_MSIX_LLI_CREDIT_LIMIT_DEFAULT,
728 HINIC_EQ_MSIX_RESEND_TIMER_DEFAULT);
730 if (type == HINIC_AEQ)
731 err = request_irq(entry.vector, aeq_interrupt, 0,
733 else if (type == HINIC_CEQ)
734 err = request_irq(entry.vector, ceq_interrupt, 0,
738 dev_err(&pdev->dev, "Failed to request irq for the EQ\n");
750 * remove_eq - remove Event Queue
751 * @eq: the event queue
753 static void remove_eq(struct hinic_eq *eq)
755 struct msix_entry *entry = &eq->msix_entry;
757 free_irq(entry->vector, eq);
759 if (eq->type == HINIC_AEQ) {
760 struct hinic_eq_work *aeq_work = &eq->aeq_work;
762 cancel_work_sync(&aeq_work->work);
763 } else if (eq->type == HINIC_CEQ) {
764 tasklet_kill(&eq->ceq_tasklet);
771 * hinic_aeqs_init - initialize all the aeqs
772 * @aeqs: pointer to Async eqs of the chip
773 * @hwif: the HW interface of a PCI function device
774 * @num_aeqs: number of AEQs
775 * @q_len: number of EQ elements
776 * @page_size: the page size of the pages in the event queue
777 * @msix_entries: msix entries associated with the event queues
779 * Return 0 - Success, negative - Failure
781 int hinic_aeqs_init(struct hinic_aeqs *aeqs, struct hinic_hwif *hwif,
782 int num_aeqs, u32 q_len, u32 page_size,
783 struct msix_entry *msix_entries)
785 struct pci_dev *pdev = hwif->pdev;
788 aeqs->workq = create_singlethread_workqueue(HINIC_EQS_WQ_NAME);
793 aeqs->num_aeqs = num_aeqs;
795 for (q_id = 0; q_id < num_aeqs; q_id++) {
796 err = init_eq(&aeqs->aeq[q_id], hwif, HINIC_AEQ, q_id, q_len,
797 page_size, msix_entries[q_id]);
799 dev_err(&pdev->dev, "Failed to init aeq %d\n", q_id);
807 for (i = 0; i < q_id; i++)
808 remove_eq(&aeqs->aeq[i]);
810 destroy_workqueue(aeqs->workq);
815 * hinic_aeqs_free - free all the aeqs
816 * @aeqs: pointer to Async eqs of the chip
818 void hinic_aeqs_free(struct hinic_aeqs *aeqs)
822 for (q_id = 0; q_id < aeqs->num_aeqs ; q_id++)
823 remove_eq(&aeqs->aeq[q_id]);
825 destroy_workqueue(aeqs->workq);
829 * hinic_ceqs_init - init all the ceqs
830 * @ceqs: ceqs part of the chip
831 * @hwif: the hardware interface of a pci function device
832 * @num_ceqs: number of CEQs
833 * @q_len: number of EQ elements
834 * @page_size: the page size of the event queue
835 * @msix_entries: msix entries associated with the event queues
837 * Return 0 - Success, Negative - Failure
839 int hinic_ceqs_init(struct hinic_ceqs *ceqs, struct hinic_hwif *hwif,
840 int num_ceqs, u32 q_len, u32 page_size,
841 struct msix_entry *msix_entries)
843 struct pci_dev *pdev = hwif->pdev;
847 ceqs->num_ceqs = num_ceqs;
849 for (q_id = 0; q_id < num_ceqs; q_id++) {
850 err = init_eq(&ceqs->ceq[q_id], hwif, HINIC_CEQ, q_id, q_len,
851 page_size, msix_entries[q_id]);
853 dev_err(&pdev->dev, "Failed to init ceq %d\n", q_id);
861 for (i = 0; i < q_id; i++)
862 remove_eq(&ceqs->ceq[i]);
868 * hinic_ceqs_free - free all the ceqs
869 * @ceqs: ceqs part of the chip
871 void hinic_ceqs_free(struct hinic_ceqs *ceqs)
875 for (q_id = 0; q_id < ceqs->num_ceqs; q_id++)
876 remove_eq(&ceqs->ceq[q_id]);