1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Huawei HiNIC PCI Express Linux driver
4 * Copyright(c) 2017 Huawei Technologies Co., Ltd
10 #include <linux/pci.h>
11 #include <linux/types.h>
12 #include <linux/bitops.h>
14 #include "hinic_hw_if.h"
15 #include "hinic_hw_eqs.h"
16 #include "hinic_hw_mgmt.h"
17 #include "hinic_hw_qp.h"
18 #include "hinic_hw_io.h"
20 #define HINIC_MAX_QPS 32
22 #define HINIC_MGMT_NUM_MSG_CMD (HINIC_MGMT_MSG_CMD_MAX - \
23 HINIC_MGMT_MSG_CMD_BASE)
31 HINIC_PORT_CMD_CHANGE_MTU = 2,
33 HINIC_PORT_CMD_ADD_VLAN = 3,
34 HINIC_PORT_CMD_DEL_VLAN = 4,
36 HINIC_PORT_CMD_SET_MAC = 9,
37 HINIC_PORT_CMD_GET_MAC = 10,
38 HINIC_PORT_CMD_DEL_MAC = 11,
40 HINIC_PORT_CMD_SET_RX_MODE = 12,
42 HINIC_PORT_CMD_GET_LINK_STATE = 24,
44 HINIC_PORT_CMD_SET_RX_CSUM = 26,
46 HINIC_PORT_CMD_SET_PORT_STATE = 41,
48 HINIC_PORT_CMD_FWCTXT_INIT = 69,
50 HINIC_PORT_CMD_SET_FUNC_STATE = 93,
52 HINIC_PORT_CMD_GET_GLOBAL_QPN = 102,
54 HINIC_PORT_CMD_SET_TSO = 112,
56 HINIC_PORT_CMD_GET_CAP = 170,
59 enum hinic_mgmt_msg_cmd {
60 HINIC_MGMT_MSG_CMD_BASE = 160,
62 HINIC_MGMT_MSG_CMD_LINK_STATUS = 160,
64 HINIC_MGMT_MSG_CMD_MAX,
68 HINIC_CB_ENABLED = BIT(0),
69 HINIC_CB_RUNNING = BIT(1),
72 enum hinic_res_state {
77 struct hinic_cmd_fw_ctxt {
88 struct hinic_cmd_hw_ioctxt {
110 struct hinic_cmd_io_status {
121 struct hinic_cmd_clear_io_res {
131 struct hinic_cmd_set_res_state {
142 struct hinic_cmd_base_qpn {
151 struct hinic_cmd_hw_ci {
171 struct hinic_hwif *hwif;
172 struct msix_entry *msix_entries;
174 struct hinic_aeqs aeqs;
175 struct hinic_func_to_io func_to_io;
177 struct hinic_cap nic_cap;
180 struct hinic_nic_cb {
181 void (*handler)(void *handle, void *buf_in,
182 u16 in_size, void *buf_out,
186 unsigned long cb_state;
189 struct hinic_pfhwdev {
190 struct hinic_hwdev hwdev;
192 struct hinic_pf_to_mgmt pf_to_mgmt;
194 struct hinic_nic_cb nic_cb[HINIC_MGMT_NUM_MSG_CMD];
197 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev,
198 enum hinic_mgmt_msg_cmd cmd, void *handle,
199 void (*handler)(void *handle, void *buf_in,
200 u16 in_size, void *buf_out,
203 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev,
204 enum hinic_mgmt_msg_cmd cmd);
206 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd,
207 void *buf_in, u16 in_size, void *buf_out,
210 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev);
212 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev);
214 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev);
216 void hinic_free_hwdev(struct hinic_hwdev *hwdev);
218 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev);
220 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i);
222 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i);
224 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index);
226 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index,
227 u8 pending_limit, u8 coalesc_timer,
228 u8 lli_timer_cfg, u8 lli_credit_limit,
231 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq,
232 u8 pending_limit, u8 coalesc_timer);
234 void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index,
235 enum hinic_msix_state flag);