1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2016-2017 Hisilicon Limited.
7 #include <linux/types.h>
9 #include <linux/if_vlan.h>
10 #include <linux/kfifo.h>
12 #include "hclge_cmd.h"
15 #define HCLGE_MOD_VERSION "1.0"
16 #define HCLGE_DRIVER_NAME "hclge"
18 #define HCLGE_MAX_PF_NUM 8
20 #define HCLGE_VF_VPORT_START_NUM 1
22 #define HCLGE_RD_FIRST_STATS_NUM 2
23 #define HCLGE_RD_OTHER_STATS_NUM 4
25 #define HCLGE_INVALID_VPORT 0xffff
27 #define HCLGE_PF_CFG_BLOCK_SIZE 32
28 #define HCLGE_PF_CFG_DESC_NUM \
29 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
31 #define HCLGE_VECTOR_REG_BASE 0x20000
32 #define HCLGE_VECTOR_EXT_REG_BASE 0x30000
33 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400
35 #define HCLGE_VECTOR_REG_OFFSET 0x4
36 #define HCLGE_VECTOR_REG_OFFSET_H 0x1000
37 #define HCLGE_VECTOR_VF_OFFSET 0x100000
39 #define HCLGE_CMDQ_TX_ADDR_L_REG 0x27000
40 #define HCLGE_CMDQ_TX_ADDR_H_REG 0x27004
41 #define HCLGE_CMDQ_TX_DEPTH_REG 0x27008
42 #define HCLGE_CMDQ_TX_TAIL_REG 0x27010
43 #define HCLGE_CMDQ_TX_HEAD_REG 0x27014
44 #define HCLGE_CMDQ_RX_ADDR_L_REG 0x27018
45 #define HCLGE_CMDQ_RX_ADDR_H_REG 0x2701C
46 #define HCLGE_CMDQ_RX_DEPTH_REG 0x27020
47 #define HCLGE_CMDQ_RX_TAIL_REG 0x27024
48 #define HCLGE_CMDQ_RX_HEAD_REG 0x27028
49 #define HCLGE_CMDQ_INTR_STS_REG 0x27104
50 #define HCLGE_CMDQ_INTR_EN_REG 0x27108
51 #define HCLGE_CMDQ_INTR_GEN_REG 0x2710C
53 /* bar registers for common func */
54 #define HCLGE_VECTOR0_OTER_EN_REG 0x20600
55 #define HCLGE_GRO_EN_REG 0x28000
57 /* bar registers for rcb */
58 #define HCLGE_RING_RX_ADDR_L_REG 0x80000
59 #define HCLGE_RING_RX_ADDR_H_REG 0x80004
60 #define HCLGE_RING_RX_BD_NUM_REG 0x80008
61 #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C
62 #define HCLGE_RING_RX_MERGE_EN_REG 0x80014
63 #define HCLGE_RING_RX_TAIL_REG 0x80018
64 #define HCLGE_RING_RX_HEAD_REG 0x8001C
65 #define HCLGE_RING_RX_FBD_NUM_REG 0x80020
66 #define HCLGE_RING_RX_OFFSET_REG 0x80024
67 #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028
68 #define HCLGE_RING_RX_STASH_REG 0x80030
69 #define HCLGE_RING_RX_BD_ERR_REG 0x80034
70 #define HCLGE_RING_TX_ADDR_L_REG 0x80040
71 #define HCLGE_RING_TX_ADDR_H_REG 0x80044
72 #define HCLGE_RING_TX_BD_NUM_REG 0x80048
73 #define HCLGE_RING_TX_PRIORITY_REG 0x8004C
74 #define HCLGE_RING_TX_TC_REG 0x80050
75 #define HCLGE_RING_TX_MERGE_EN_REG 0x80054
76 #define HCLGE_RING_TX_TAIL_REG 0x80058
77 #define HCLGE_RING_TX_HEAD_REG 0x8005C
78 #define HCLGE_RING_TX_FBD_NUM_REG 0x80060
79 #define HCLGE_RING_TX_OFFSET_REG 0x80064
80 #define HCLGE_RING_TX_EBD_NUM_REG 0x80068
81 #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070
82 #define HCLGE_RING_TX_BD_ERR_REG 0x80074
83 #define HCLGE_RING_EN_REG 0x80090
85 /* bar registers for tqp interrupt */
86 #define HCLGE_TQP_INTR_CTRL_REG 0x20000
87 #define HCLGE_TQP_INTR_GL0_REG 0x20100
88 #define HCLGE_TQP_INTR_GL1_REG 0x20200
89 #define HCLGE_TQP_INTR_GL2_REG 0x20300
90 #define HCLGE_TQP_INTR_RL_REG 0x20900
92 #define HCLGE_RSS_IND_TBL_SIZE 512
93 #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0)
94 #define HCLGE_RSS_KEY_SIZE 40
95 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0
96 #define HCLGE_RSS_HASH_ALGO_SIMPLE 1
97 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2
98 #define HCLGE_RSS_HASH_ALGO_MASK GENMASK(3, 0)
100 #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0)
101 #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0)
102 #define HCLGE_D_PORT_BIT BIT(0)
103 #define HCLGE_S_PORT_BIT BIT(1)
104 #define HCLGE_D_IP_BIT BIT(2)
105 #define HCLGE_S_IP_BIT BIT(3)
106 #define HCLGE_V_TAG_BIT BIT(4)
107 #define HCLGE_RSS_INPUT_TUPLE_SCTP_NO_PORT \
108 (HCLGE_D_IP_BIT | HCLGE_S_IP_BIT | HCLGE_V_TAG_BIT)
110 #define HCLGE_RSS_TC_SIZE_0 1
111 #define HCLGE_RSS_TC_SIZE_1 2
112 #define HCLGE_RSS_TC_SIZE_2 4
113 #define HCLGE_RSS_TC_SIZE_3 8
114 #define HCLGE_RSS_TC_SIZE_4 16
115 #define HCLGE_RSS_TC_SIZE_5 32
116 #define HCLGE_RSS_TC_SIZE_6 64
117 #define HCLGE_RSS_TC_SIZE_7 128
119 #define HCLGE_UMV_TBL_SIZE 3072
120 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \
121 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM)
123 #define HCLGE_TQP_RESET_TRY_TIMES 200
125 #define HCLGE_PHY_PAGE_MDIX 0
126 #define HCLGE_PHY_PAGE_COPPER 0
128 /* Page Selection Reg. */
129 #define HCLGE_PHY_PAGE_REG 22
131 /* Copper Specific Control Register */
132 #define HCLGE_PHY_CSC_REG 16
134 /* Copper Specific Status Register */
135 #define HCLGE_PHY_CSS_REG 17
137 #define HCLGE_PHY_MDIX_CTRL_S 5
138 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5)
140 #define HCLGE_PHY_MDIX_STATUS_B 6
141 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11
143 #define HCLGE_GET_DFX_REG_TYPE_CNT 4
145 /* Factor used to calculate offset and bitmap of VF num */
146 #define HCLGE_VF_NUM_PER_CMD 64
148 #define HCLGE_MAX_QSET_NUM 1024
150 enum HLCGE_PORT_TYPE {
155 #define PF_VPORT_ID 0
157 #define HCLGE_PF_ID_S 0
158 #define HCLGE_PF_ID_M GENMASK(2, 0)
159 #define HCLGE_VF_ID_S 3
160 #define HCLGE_VF_ID_M GENMASK(10, 3)
161 #define HCLGE_PORT_TYPE_B 11
162 #define HCLGE_NETWORK_PORT_ID_S 0
163 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0)
165 /* Reset related Registers */
166 #define HCLGE_PF_OTHER_INT_REG 0x20600
167 #define HCLGE_MISC_RESET_STS_REG 0x20700
168 #define HCLGE_MISC_VECTOR_INT_STS 0x20800
169 #define HCLGE_GLOBAL_RESET_REG 0x20A00
170 #define HCLGE_GLOBAL_RESET_BIT 0
171 #define HCLGE_CORE_RESET_BIT 1
172 #define HCLGE_IMP_RESET_BIT 2
173 #define HCLGE_RESET_INT_M GENMASK(7, 5)
174 #define HCLGE_FUN_RST_ING 0x20C00
175 #define HCLGE_FUN_RST_ING_B 0
177 /* Vector0 register bits define */
178 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5
179 #define HCLGE_VECTOR0_CORERESET_INT_B 6
180 #define HCLGE_VECTOR0_IMPRESET_INT_B 7
182 /* Vector0 interrupt CMDQ event source register(RW) */
183 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100
184 /* CMDQ register bits for RX event(=MBX event) */
185 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1
187 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1
188 #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U
189 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U
191 #define HCLGE_MAC_DEFAULT_FRAME \
192 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN)
193 #define HCLGE_MAC_MIN_FRAME 64
194 #define HCLGE_MAC_MAX_FRAME 9728
196 #define HCLGE_SUPPORT_1G_BIT BIT(0)
197 #define HCLGE_SUPPORT_10G_BIT BIT(1)
198 #define HCLGE_SUPPORT_25G_BIT BIT(2)
199 #define HCLGE_SUPPORT_50G_BIT BIT(3)
200 #define HCLGE_SUPPORT_100G_BIT BIT(4)
201 /* to be compatible with exsit board */
202 #define HCLGE_SUPPORT_40G_BIT BIT(5)
203 #define HCLGE_SUPPORT_100M_BIT BIT(6)
204 #define HCLGE_SUPPORT_10M_BIT BIT(7)
205 #define HCLGE_SUPPORT_200G_BIT BIT(8)
206 #define HCLGE_SUPPORT_GE \
207 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT)
209 enum HCLGE_DEV_STATE {
210 HCLGE_STATE_REINITING,
212 HCLGE_STATE_DISABLED,
213 HCLGE_STATE_REMOVING,
214 HCLGE_STATE_NIC_REGISTERED,
215 HCLGE_STATE_ROCE_REGISTERED,
216 HCLGE_STATE_SERVICE_INITED,
217 HCLGE_STATE_RST_SERVICE_SCHED,
218 HCLGE_STATE_RST_HANDLING,
219 HCLGE_STATE_MBX_SERVICE_SCHED,
220 HCLGE_STATE_MBX_HANDLING,
221 HCLGE_STATE_STATISTICS_UPDATING,
222 HCLGE_STATE_CMD_DISABLE,
223 HCLGE_STATE_LINK_UPDATING,
224 HCLGE_STATE_PROMISC_CHANGED,
225 HCLGE_STATE_RST_FAIL,
229 enum hclge_evt_cause {
230 HCLGE_VECTOR0_EVENT_RST,
231 HCLGE_VECTOR0_EVENT_MBX,
232 HCLGE_VECTOR0_EVENT_ERR,
233 HCLGE_VECTOR0_EVENT_OTHER,
236 enum HCLGE_MAC_SPEED {
237 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */
238 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */
239 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */
240 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
241 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
242 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
243 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
244 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */
245 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */
246 HCLGE_MAC_SPEED_200G = 200000 /* 200000 Mbps = 200 Gbps */
249 enum HCLGE_MAC_DUPLEX {
254 #define QUERY_SFP_SPEED 0
255 #define QUERY_ACTIVE_SPEED 1
261 u8 media_type; /* port media type, e.g. fibre/copper/backplane */
262 u8 mac_addr[ETH_ALEN];
266 u8 speed_type; /* 0: sfp speed, 1: active speed */
269 u32 speed_ability; /* speed ability supported by current media */
270 u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */
271 u32 fec_mode; /* active fec mode */
274 int link; /* store the link status of mac & phy (if phy exists) */
275 struct phy_device *phydev;
276 struct mii_bus *mdio_bus;
277 phy_interface_t phy_if;
278 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
279 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
283 void __iomem *io_base;
284 void __iomem *mem_base;
285 struct hclge_mac mac;
287 struct hclge_cmq cmq;
291 struct hlcge_tqp_stats {
292 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */
293 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
294 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */
295 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
299 /* copy of device pointer from pci_dev,
300 * used when perform DMA mapping
303 struct hnae3_queue q;
304 struct hlcge_tqp_stats tqp_stats;
305 u16 index; /* Global index in a NIC controller */
319 enum hclge_link_fail_code {
321 HCLGE_LF_REF_CLOCK_LOST,
322 HCLGE_LF_XSFP_TX_DISABLE,
323 HCLGE_LF_XSFP_ABSENT,
326 #define HCLGE_LINK_STATUS_DOWN 0
327 #define HCLGE_LINK_STATUS_UP 1
329 #define HCLGE_PG_NUM 4
330 #define HCLGE_SCH_MODE_SP 0
331 #define HCLGE_SCH_MODE_DWRR 1
332 struct hclge_pg_info {
334 u8 pg_sch_mode; /* 0: sp; 1: dwrr */
337 u8 tc_dwrr[HNAE3_MAX_TC];
340 struct hclge_tc_info {
342 u8 tc_sch_mode; /* 0: sp; 1: dwrr */
356 u8 mac_addr[ETH_ALEN];
363 struct hclge_tm_info {
365 u8 num_pg; /* It must be 1 if vNET-Base schd */
366 u8 pg_dwrr[HCLGE_PG_NUM];
367 u8 prio_tc[HNAE3_MAX_USER_PRIO];
368 struct hclge_pg_info pg_info[HCLGE_PG_NUM];
369 struct hclge_tc_info tc_info[HNAE3_MAX_TC];
370 enum hclge_fc_mode fc_mode;
371 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */
372 u8 pfc_en; /* PFC enabled or not for user priority */
375 struct hclge_comm_stats_str {
376 char desc[ETH_GSTRING_LEN];
377 unsigned long offset;
380 /* mac stats ,opcode id: 0x0032 */
381 struct hclge_mac_stats {
382 u64 mac_tx_mac_pause_num;
383 u64 mac_rx_mac_pause_num;
384 u64 mac_tx_pfc_pri0_pkt_num;
385 u64 mac_tx_pfc_pri1_pkt_num;
386 u64 mac_tx_pfc_pri2_pkt_num;
387 u64 mac_tx_pfc_pri3_pkt_num;
388 u64 mac_tx_pfc_pri4_pkt_num;
389 u64 mac_tx_pfc_pri5_pkt_num;
390 u64 mac_tx_pfc_pri6_pkt_num;
391 u64 mac_tx_pfc_pri7_pkt_num;
392 u64 mac_rx_pfc_pri0_pkt_num;
393 u64 mac_rx_pfc_pri1_pkt_num;
394 u64 mac_rx_pfc_pri2_pkt_num;
395 u64 mac_rx_pfc_pri3_pkt_num;
396 u64 mac_rx_pfc_pri4_pkt_num;
397 u64 mac_rx_pfc_pri5_pkt_num;
398 u64 mac_rx_pfc_pri6_pkt_num;
399 u64 mac_rx_pfc_pri7_pkt_num;
400 u64 mac_tx_total_pkt_num;
401 u64 mac_tx_total_oct_num;
402 u64 mac_tx_good_pkt_num;
403 u64 mac_tx_bad_pkt_num;
404 u64 mac_tx_good_oct_num;
405 u64 mac_tx_bad_oct_num;
406 u64 mac_tx_uni_pkt_num;
407 u64 mac_tx_multi_pkt_num;
408 u64 mac_tx_broad_pkt_num;
409 u64 mac_tx_undersize_pkt_num;
410 u64 mac_tx_oversize_pkt_num;
411 u64 mac_tx_64_oct_pkt_num;
412 u64 mac_tx_65_127_oct_pkt_num;
413 u64 mac_tx_128_255_oct_pkt_num;
414 u64 mac_tx_256_511_oct_pkt_num;
415 u64 mac_tx_512_1023_oct_pkt_num;
416 u64 mac_tx_1024_1518_oct_pkt_num;
417 u64 mac_tx_1519_2047_oct_pkt_num;
418 u64 mac_tx_2048_4095_oct_pkt_num;
419 u64 mac_tx_4096_8191_oct_pkt_num;
421 u64 mac_tx_8192_9216_oct_pkt_num;
422 u64 mac_tx_9217_12287_oct_pkt_num;
423 u64 mac_tx_12288_16383_oct_pkt_num;
424 u64 mac_tx_1519_max_good_oct_pkt_num;
425 u64 mac_tx_1519_max_bad_oct_pkt_num;
427 u64 mac_rx_total_pkt_num;
428 u64 mac_rx_total_oct_num;
429 u64 mac_rx_good_pkt_num;
430 u64 mac_rx_bad_pkt_num;
431 u64 mac_rx_good_oct_num;
432 u64 mac_rx_bad_oct_num;
433 u64 mac_rx_uni_pkt_num;
434 u64 mac_rx_multi_pkt_num;
435 u64 mac_rx_broad_pkt_num;
436 u64 mac_rx_undersize_pkt_num;
437 u64 mac_rx_oversize_pkt_num;
438 u64 mac_rx_64_oct_pkt_num;
439 u64 mac_rx_65_127_oct_pkt_num;
440 u64 mac_rx_128_255_oct_pkt_num;
441 u64 mac_rx_256_511_oct_pkt_num;
442 u64 mac_rx_512_1023_oct_pkt_num;
443 u64 mac_rx_1024_1518_oct_pkt_num;
444 u64 mac_rx_1519_2047_oct_pkt_num;
445 u64 mac_rx_2048_4095_oct_pkt_num;
446 u64 mac_rx_4096_8191_oct_pkt_num;
448 u64 mac_rx_8192_9216_oct_pkt_num;
449 u64 mac_rx_9217_12287_oct_pkt_num;
450 u64 mac_rx_12288_16383_oct_pkt_num;
451 u64 mac_rx_1519_max_good_oct_pkt_num;
452 u64 mac_rx_1519_max_bad_oct_pkt_num;
454 u64 mac_tx_fragment_pkt_num;
455 u64 mac_tx_undermin_pkt_num;
456 u64 mac_tx_jabber_pkt_num;
457 u64 mac_tx_err_all_pkt_num;
458 u64 mac_tx_from_app_good_pkt_num;
459 u64 mac_tx_from_app_bad_pkt_num;
460 u64 mac_rx_fragment_pkt_num;
461 u64 mac_rx_undermin_pkt_num;
462 u64 mac_rx_jabber_pkt_num;
463 u64 mac_rx_fcs_err_pkt_num;
464 u64 mac_rx_send_app_good_pkt_num;
465 u64 mac_rx_send_app_bad_pkt_num;
466 u64 mac_tx_pfc_pause_pkt_num;
467 u64 mac_rx_pfc_pause_pkt_num;
468 u64 mac_tx_ctrl_pkt_num;
469 u64 mac_rx_ctrl_pkt_num;
472 #define HCLGE_STATS_TIMER_INTERVAL 300UL
474 struct hclge_vlan_type_cfg {
475 u16 rx_ot_fst_vlan_type;
476 u16 rx_ot_sec_vlan_type;
477 u16 rx_in_fst_vlan_type;
478 u16 rx_in_sec_vlan_type;
484 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1,
485 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2,
486 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1,
487 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2,
490 enum HCLGE_FD_KEY_TYPE {
491 HCLGE_FD_KEY_BASE_ON_PTYPE,
492 HCLGE_FD_KEY_BASE_ON_TUPLE,
495 enum HCLGE_FD_STAGE {
501 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet
502 * INNER_XXX indicate tuples in tunneled header of tunnel packet or
503 * tuples of non-tunnel packet
505 enum HCLGE_FD_TUPLE {
539 enum HCLGE_FD_META_DATA {
553 u8 key_length; /* use bit as unit */
556 #define MAX_KEY_LENGTH 400
557 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4)
558 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4)
559 #define MAX_META_DATA_LENGTH 32
561 /* assigned by firmware, the real filter number for each pf may be less */
562 #define MAX_FD_FILTER_NUM 4096
563 #define HCLGE_ARFS_EXPIRE_INTERVAL 5UL
565 enum HCLGE_FD_ACTIVE_RULE_TYPE {
567 HCLGE_FD_ARFS_ACTIVE,
569 HCLGE_FD_TC_FLOWER_ACTIVE,
572 enum HCLGE_FD_PACKET_TYPE {
577 enum HCLGE_FD_ACTION {
578 HCLGE_FD_ACTION_SELECT_QUEUE,
579 HCLGE_FD_ACTION_DROP_PACKET,
580 HCLGE_FD_ACTION_SELECT_TC,
583 struct hclge_fd_key_cfg {
585 u8 inner_sipv6_word_en;
586 u8 inner_dipv6_word_en;
587 u8 outer_sipv6_word_en;
588 u8 outer_dipv6_word_en;
590 u32 meta_data_active;
593 struct hclge_fd_cfg {
595 u16 max_key_length; /* use bit as unit */
596 u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */
597 u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */
598 struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM];
603 struct hclge_fd_rule_tuples {
604 u8 src_mac[ETH_ALEN];
605 u8 dst_mac[ETH_ALEN];
606 /* Be compatible for ip address of both ipv4 and ipv6.
607 * For ipv4 address, we store it in src/dst_ip[3].
609 u32 src_ip[IPV6_SIZE];
610 u32 dst_ip[IPV6_SIZE];
619 struct hclge_fd_rule {
620 struct hlist_node rule_node;
621 struct hclge_fd_rule_tuples tuples;
622 struct hclge_fd_rule_tuples tuples_mask;
627 unsigned long cookie;
631 u16 flow_id; /* only used for arfs */
637 enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type;
641 struct hclge_fd_ad_data {
644 u8 forward_to_direct_queue;
649 u8 write_rule_id_to_bd;
656 enum HCLGE_MAC_NODE_STATE {
662 struct hclge_mac_node {
663 struct list_head node;
664 enum HCLGE_MAC_NODE_STATE state;
665 u8 mac_addr[ETH_ALEN];
668 enum HCLGE_MAC_ADDR_TYPE {
673 struct hclge_vport_vlan_cfg {
674 struct list_head node;
679 struct hclge_rst_stats {
680 u32 reset_done_cnt; /* the number of reset has completed */
681 u32 hw_reset_done_cnt; /* the number of HW reset has completed */
682 u32 pf_rst_cnt; /* the number of PF reset */
683 u32 flr_rst_cnt; /* the number of FLR */
684 u32 global_rst_cnt; /* the number of GLOBAL */
685 u32 imp_rst_cnt; /* the number of IMP reset */
686 u32 reset_cnt; /* the number of reset */
687 u32 reset_fail_cnt; /* the number of reset fail */
690 /* time and register status when mac tunnel interruption occur */
691 struct hclge_mac_tnl_stats {
696 #define HCLGE_RESET_INTERVAL (10 * HZ)
697 #define HCLGE_WAIT_RESET_DONE 100
700 struct hclge_vf_vlan_cfg {
710 /* For each bit of TCAM entry, it uses a pair of 'x' and
711 * 'y' to indicate which value to match, like below:
712 * ----------------------------------
713 * | bit x | bit y | search value |
714 * ----------------------------------
715 * | 0 | 0 | always hit |
716 * ----------------------------------
717 * | 1 | 0 | match '0' |
718 * ----------------------------------
719 * | 0 | 1 | match '1' |
720 * ----------------------------------
721 * | 1 | 1 | invalid |
722 * ----------------------------------
723 * Then for input key(k) and mask(v), we can calculate the value by
728 #define calc_x(x, k, v) (x = ~(k) & (v))
729 #define calc_y(y, k, v) \
731 const typeof(k) _k_ = (k); \
732 const typeof(v) _v_ = (v); \
733 (y) = (_k_ ^ ~_v_) & (_k_); \
736 #define HCLGE_MAC_TNL_LOG_SIZE 8
737 #define HCLGE_VPORT_NUM 256
739 struct pci_dev *pdev;
740 struct hnae3_ae_dev *ae_dev;
742 struct hclge_misc_vector misc_vector;
743 struct hclge_mac_stats mac_stats;
745 unsigned long flr_state;
746 unsigned long last_reset_time;
748 enum hnae3_reset_type reset_type;
749 enum hnae3_reset_type reset_level;
750 unsigned long default_reset_request;
751 unsigned long reset_request; /* reset has been requested */
752 unsigned long reset_pending; /* client rst is pending to be served */
753 struct hclge_rst_stats rst_stats;
754 struct semaphore reset_sem; /* protect reset process */
756 u16 num_vmdq_vport; /* Num vmdq vport this PF has set up */
757 u16 num_tqps; /* Num task queue pairs of this PF */
758 u16 num_req_vfs; /* Num VFs requested for this PF */
760 u16 base_tqp_pid; /* Base task tqp physical id of this PF */
761 u16 alloc_rss_size; /* Allocated RSS task queue */
762 u16 vf_rss_size_max; /* HW defined VF max RSS task queue */
763 u16 pf_rss_size_max; /* HW defined PF max RSS task queue */
765 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */
766 u16 num_alloc_vport; /* Num vports this driver supports */
769 u16 num_tx_desc; /* desc num of per tx queue */
770 u16 num_rx_desc; /* desc num of per rx queue */
772 enum hclge_fc_mode fc_mode_last_time;
773 u8 support_sfp_query;
775 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1
776 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2
783 struct hclge_tm_info tm_info;
791 u16 num_nic_msi; /* Num of nic vectors for this PF */
792 u16 num_roce_msi; /* Num of roce vectors for this PF */
793 int roce_base_vector;
795 unsigned long service_timer_period;
796 unsigned long service_timer_previous;
797 struct timer_list reset_timer;
798 struct delayed_work service_task;
801 int num_alloc_vfs; /* Actual number of VFs allocated */
803 struct hclge_tqp *htqp;
804 struct hclge_vport *vport;
806 struct dentry *hclge_dbgfs;
808 struct hnae3_client *nic_client;
809 struct hnae3_client *roce_client;
811 #define HCLGE_FLAG_MAIN BIT(0)
812 #define HCLGE_FLAG_DCB_CAPABLE BIT(1)
813 #define HCLGE_FLAG_DCB_ENABLE BIT(2)
814 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3)
817 u32 pkt_buf_size; /* Total pf buf size for tx/rx */
818 u32 tx_buf_size; /* Tx buffer size for each TC */
819 u32 dv_buf_size; /* Dv buffer size for each TC */
821 u32 mps; /* Max packet size */
822 /* vport_lock protect resource shared by vports */
823 struct mutex vport_lock;
825 struct hclge_vlan_type_cfg vlan_type_cfg;
827 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)];
828 unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
830 unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
832 struct hclge_fd_cfg fd_cfg;
833 struct hlist_head fd_rule_list;
834 spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */
835 u16 hclge_fd_rule_num;
836 unsigned long serv_processed_cnt;
837 unsigned long last_serv_processed;
838 unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)];
839 enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type;
843 /* max available unicast mac vlan space */
845 /* private unicast mac vlan space, it's same for PF and its VFs */
847 /* unicast mac vlan space shared by PF and its VFs */
850 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats,
851 HCLGE_MAC_TNL_LOG_SIZE);
853 /* affinity mask and notify for misc interrupt */
854 cpumask_t affinity_mask;
855 struct irq_affinity_notify affinity_notify;
858 /* VPort level vlan tag configuration for TX direction */
859 struct hclge_tx_vtag_cfg {
860 bool accept_tag1; /* Whether accept tag1 packet from host */
861 bool accept_untag1; /* Whether accept untag1 packet from host */
864 bool insert_tag1_en; /* Whether insert inner vlan tag */
865 bool insert_tag2_en; /* Whether insert outer vlan tag */
866 u16 default_tag1; /* The default inner vlan tag to insert */
867 u16 default_tag2; /* The default outer vlan tag to insert */
868 bool tag_shift_mode_en;
871 /* VPort level vlan tag configuration for RX direction */
872 struct hclge_rx_vtag_cfg {
873 bool rx_vlan_offload_en; /* Whether enable rx vlan offload */
874 bool strip_tag1_en; /* Whether strip inner vlan tag */
875 bool strip_tag2_en; /* Whether strip outer vlan tag */
876 bool vlan1_vlan_prionly; /* Inner vlan tag up to descriptor enable */
877 bool vlan2_vlan_prionly; /* Outer vlan tag up to descriptor enable */
878 bool strip_tag1_discard_en; /* Inner vlan tag discard for BD enable */
879 bool strip_tag2_discard_en; /* Outer vlan tag discard for BD enable */
882 struct hclge_rss_tuple_cfg {
893 enum HCLGE_VPORT_STATE {
894 HCLGE_VPORT_STATE_ALIVE,
895 HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
896 HCLGE_VPORT_STATE_MAX
899 struct hclge_vlan_info {
900 u16 vlan_proto; /* so far support 802.1Q only */
905 struct hclge_port_base_vlan_config {
907 struct hclge_vlan_info vlan_info;
910 struct hclge_vf_info {
920 u16 alloc_tqps; /* Allocated Tx/Rx queues */
922 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */
923 /* User configured lookup table entries */
924 u16 *rss_indirection_tbl;
925 int rss_algo; /* User configured hash algorithm */
926 /* User configured rss tuple sets */
927 struct hclge_rss_tuple_cfg rss_tuple_sets;
932 u32 bw_limit; /* VSI BW Limit (0 = disabled) */
935 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];
936 struct hclge_port_base_vlan_config port_base_vlan_cfg;
937 struct hclge_tx_vtag_cfg txvlan_cfg;
938 struct hclge_rx_vtag_cfg rxvlan_cfg;
943 struct hclge_dev *back; /* Back reference to associated dev */
944 struct hnae3_handle nic;
945 struct hnae3_handle roce;
948 unsigned long last_active_jiffies;
949 u32 mps; /* Max packet size */
950 struct hclge_vf_info vf_info;
952 u8 overflow_promisc_flags;
953 u8 last_promisc_flags;
955 spinlock_t mac_list_lock; /* protect mac address need to add/detele */
956 struct list_head uc_mac_list; /* Store VF unicast table */
957 struct list_head mc_mac_list; /* Store VF multicast table */
958 struct list_head vlan_list; /* Store VF vlan table */
961 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc,
962 bool en_mc_pmc, bool en_bc_pmc);
963 int hclge_add_uc_addr_common(struct hclge_vport *vport,
964 const unsigned char *addr);
965 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
966 const unsigned char *addr);
967 int hclge_add_mc_addr_common(struct hclge_vport *vport,
968 const unsigned char *addr);
969 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
970 const unsigned char *addr);
972 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle);
973 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
974 int vector_id, bool en,
975 struct hnae3_ring_chain_node *ring_chain);
977 static inline int hclge_get_queue_id(struct hnae3_queue *queue)
979 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q);
984 static inline bool hclge_is_reset_pending(struct hclge_dev *hdev)
986 return !!hdev->reset_pending;
989 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport);
990 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);
991 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
992 u16 vlan_id, bool is_kill);
993 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable);
995 int hclge_buffer_alloc(struct hclge_dev *hdev);
996 int hclge_rss_init_hw(struct hclge_dev *hdev);
997 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev);
999 void hclge_mbx_handler(struct hclge_dev *hdev);
1000 int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id);
1001 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id);
1002 int hclge_cfg_flowctrl(struct hclge_dev *hdev);
1003 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id);
1004 int hclge_vport_start(struct hclge_vport *vport);
1005 void hclge_vport_stop(struct hclge_vport *vport);
1006 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu);
1007 int hclge_dbg_run_cmd(struct hnae3_handle *handle, const char *cmd_buf);
1008 int hclge_dbg_read_cmd(struct hnae3_handle *handle, const char *cmd_buf,
1009 char *buf, int len);
1010 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id);
1011 int hclge_notify_client(struct hclge_dev *hdev,
1012 enum hnae3_reset_notify_type type);
1013 int hclge_update_mac_list(struct hclge_vport *vport,
1014 enum HCLGE_MAC_NODE_STATE state,
1015 enum HCLGE_MAC_ADDR_TYPE mac_type,
1016 const unsigned char *addr);
1017 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport,
1018 const u8 *old_addr, const u8 *new_addr);
1019 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list,
1020 enum HCLGE_MAC_ADDR_TYPE mac_type);
1021 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list);
1022 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev);
1023 void hclge_restore_mac_table_common(struct hclge_vport *vport);
1024 void hclge_restore_vport_vlan_table(struct hclge_vport *vport);
1025 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state,
1026 struct hclge_vlan_info *vlan_info);
1027 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid,
1028 u16 state, u16 vlan_tag, u16 qos,
1030 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time);
1031 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev,
1032 struct hclge_desc *desc);
1033 void hclge_report_hw_error(struct hclge_dev *hdev,
1034 enum hnae3_hw_error_type type);
1035 void hclge_inform_vf_promisc_info(struct hclge_vport *vport);
1036 void hclge_dbg_dump_rst_info(struct hclge_dev *hdev);