drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

   1 /*
   2  * Copyright (c) 2016-2017 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/device.h>
  12 #include <linux/etherdevice.h>
  13 #include <linux/init.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/netdevice.h>
  18 #include <linux/pci.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/if_vlan.h>
  21 #include <net/rtnetlink.h>
  22 #include "hclge_cmd.h"
  23 #include "hclge_dcb.h"
  24 #include "hclge_main.h"
  25 #include "hclge_mbx.h"
  26 #include "hclge_mdio.h"
  27 #include "hclge_tm.h"
  28 #include "hnae3.h"
  29
  30 #define HCLGE_NAME                      "hclge"
  31 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
  32 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
  33 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
  34 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
  35
  36 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
  37                                      enum hclge_mta_dmac_sel_type mta_mac_sel,
  38                                      bool enable);
  39 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
  40 static int hclge_init_vlan_config(struct hclge_dev *hdev);
  41 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
  42
  43 static struct hnae3_ae_algo ae_algo;
  44
  45 static const struct pci_device_id ae_algo_pci_tbl[] = {
  46         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
  47         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
  48         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
  49         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
  50         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
  51         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
  52         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
  53         /* required last entry */
  54         {0, }
  55 };
  56
  57 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
  58
  59 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
  60         "Mac    Loopback test",
  61         "Serdes Loopback test",
  62         "Phy    Loopback test"
  63 };
  64
  65 static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
  66         {"igu_rx_oversize_pkt",
  67                 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
  68         {"igu_rx_undersize_pkt",
  69                 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
  70         {"igu_rx_out_all_pkt",
  71                 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
  72         {"igu_rx_uni_pkt",
  73                 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
  74         {"igu_rx_multi_pkt",
  75                 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
  76         {"igu_rx_broad_pkt",
  77                 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
  78         {"egu_tx_out_all_pkt",
  79                 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
  80         {"egu_tx_uni_pkt",
  81                 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
  82         {"egu_tx_multi_pkt",
  83                 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
  84         {"egu_tx_broad_pkt",
  85                 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
  86         {"ssu_ppp_mac_key_num",
  87                 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
  88         {"ssu_ppp_host_key_num",
  89                 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
  90         {"ppp_ssu_mac_rlt_num",
  91                 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
  92         {"ppp_ssu_host_rlt_num",
  93                 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
  94         {"ssu_tx_in_num",
  95                 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
  96         {"ssu_tx_out_num",
  97                 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
  98         {"ssu_rx_in_num",
  99                 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
 100         {"ssu_rx_out_num",
 101                 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
 102 };
 103
 104 static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
 105         {"igu_rx_err_pkt",
 106                 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
 107         {"igu_rx_no_eof_pkt",
 108                 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
 109         {"igu_rx_no_sof_pkt",
 110                 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
 111         {"egu_tx_1588_pkt",
 112                 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
 113         {"ssu_full_drop_num",
 114                 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
 115         {"ssu_part_drop_num",
 116                 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
 117         {"ppp_key_drop_num",
 118                 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
 119         {"ppp_rlt_drop_num",
 120                 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
 121         {"ssu_key_drop_num",
 122                 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
 123         {"pkt_curr_buf_cnt",
 124                 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
 125         {"qcn_fb_rcv_cnt",
 126                 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
 127         {"qcn_fb_drop_cnt",
 128                 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
 129         {"qcn_fb_invaild_cnt",
 130                 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
 131         {"rx_packet_tc0_in_cnt",
 132                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
 133         {"rx_packet_tc1_in_cnt",
 134                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
 135         {"rx_packet_tc2_in_cnt",
 136                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
 137         {"rx_packet_tc3_in_cnt",
 138                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
 139         {"rx_packet_tc4_in_cnt",
 140                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
 141         {"rx_packet_tc5_in_cnt",
 142                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
 143         {"rx_packet_tc6_in_cnt",
 144                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
 145         {"rx_packet_tc7_in_cnt",
 146                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
 147         {"rx_packet_tc0_out_cnt",
 148                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
 149         {"rx_packet_tc1_out_cnt",
 150                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
 151         {"rx_packet_tc2_out_cnt",
 152                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
 153         {"rx_packet_tc3_out_cnt",
 154                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
 155         {"rx_packet_tc4_out_cnt",
 156                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
 157         {"rx_packet_tc5_out_cnt",
 158                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
 159         {"rx_packet_tc6_out_cnt",
 160                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
 161         {"rx_packet_tc7_out_cnt",
 162                 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
 163         {"tx_packet_tc0_in_cnt",
 164                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
 165         {"tx_packet_tc1_in_cnt",
 166                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
 167         {"tx_packet_tc2_in_cnt",
 168                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
 169         {"tx_packet_tc3_in_cnt",
 170                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
 171         {"tx_packet_tc4_in_cnt",
 172                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
 173         {"tx_packet_tc5_in_cnt",
 174                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
 175         {"tx_packet_tc6_in_cnt",
 176                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
 177         {"tx_packet_tc7_in_cnt",
 178                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
 179         {"tx_packet_tc0_out_cnt",
 180                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
 181         {"tx_packet_tc1_out_cnt",
 182                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
 183         {"tx_packet_tc2_out_cnt",
 184                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
 185         {"tx_packet_tc3_out_cnt",
 186                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
 187         {"tx_packet_tc4_out_cnt",
 188                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
 189         {"tx_packet_tc5_out_cnt",
 190                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
 191         {"tx_packet_tc6_out_cnt",
 192                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
 193         {"tx_packet_tc7_out_cnt",
 194                 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
 195         {"pkt_curr_buf_tc0_cnt",
 196                 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
 197         {"pkt_curr_buf_tc1_cnt",
 198                 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
 199         {"pkt_curr_buf_tc2_cnt",
 200                 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
 201         {"pkt_curr_buf_tc3_cnt",
 202                 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
 203         {"pkt_curr_buf_tc4_cnt",
 204                 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
 205         {"pkt_curr_buf_tc5_cnt",
 206                 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
 207         {"pkt_curr_buf_tc6_cnt",
 208                 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
 209         {"pkt_curr_buf_tc7_cnt",
 210                 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
 211         {"mb_uncopy_num",
 212                 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
 213         {"lo_pri_unicast_rlt_drop_num",
 214                 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
 215         {"hi_pri_multicast_rlt_drop_num",
 216                 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
 217         {"lo_pri_multicast_rlt_drop_num",
 218                 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
 219         {"rx_oq_drop_pkt_cnt",
 220                 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
 221         {"tx_oq_drop_pkt_cnt",
 222                 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
 223         {"nic_l2_err_drop_pkt_cnt",
 224                 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
 225         {"roc_l2_err_drop_pkt_cnt",
 226                 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
 227 };
 228
 229 static const struct hclge_comm_stats_str g_mac_stats_string[] = {
 230         {"mac_tx_mac_pause_num",
 231                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
 232         {"mac_rx_mac_pause_num",
 233                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
 234         {"mac_tx_pfc_pri0_pkt_num",
 235                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
 236         {"mac_tx_pfc_pri1_pkt_num",
 237                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
 238         {"mac_tx_pfc_pri2_pkt_num",
 239                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
 240         {"mac_tx_pfc_pri3_pkt_num",
 241                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
 242         {"mac_tx_pfc_pri4_pkt_num",
 243                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
 244         {"mac_tx_pfc_pri5_pkt_num",
 245                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
 246         {"mac_tx_pfc_pri6_pkt_num",
 247                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
 248         {"mac_tx_pfc_pri7_pkt_num",
 249                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
 250         {"mac_rx_pfc_pri0_pkt_num",
 251                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
 252         {"mac_rx_pfc_pri1_pkt_num",
 253                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
 254         {"mac_rx_pfc_pri2_pkt_num",
 255                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
 256         {"mac_rx_pfc_pri3_pkt_num",
 257                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
 258         {"mac_rx_pfc_pri4_pkt_num",
 259                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
 260         {"mac_rx_pfc_pri5_pkt_num",
 261                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
 262         {"mac_rx_pfc_pri6_pkt_num",
 263                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
 264         {"mac_rx_pfc_pri7_pkt_num",
 265                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
 266         {"mac_tx_total_pkt_num",
 267                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
 268         {"mac_tx_total_oct_num",
 269                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
 270         {"mac_tx_good_pkt_num",
 271                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
 272         {"mac_tx_bad_pkt_num",
 273                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
 274         {"mac_tx_good_oct_num",
 275                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
 276         {"mac_tx_bad_oct_num",
 277                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
 278         {"mac_tx_uni_pkt_num",
 279                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
 280         {"mac_tx_multi_pkt_num",
 281                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
 282         {"mac_tx_broad_pkt_num",
 283                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
 284         {"mac_tx_undersize_pkt_num",
 285                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
 286         {"mac_tx_oversize_pkt_num",
 287                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
 288         {"mac_tx_64_oct_pkt_num",
 289                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
 290         {"mac_tx_65_127_oct_pkt_num",
 291                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
 292         {"mac_tx_128_255_oct_pkt_num",
 293                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
 294         {"mac_tx_256_511_oct_pkt_num",
 295                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
 296         {"mac_tx_512_1023_oct_pkt_num",
 297                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
 298         {"mac_tx_1024_1518_oct_pkt_num",
 299                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
 300         {"mac_tx_1519_2047_oct_pkt_num",
 301                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
 302         {"mac_tx_2048_4095_oct_pkt_num",
 303                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
 304         {"mac_tx_4096_8191_oct_pkt_num",
 305                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
 306         {"mac_tx_8192_9216_oct_pkt_num",
 307                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
 308         {"mac_tx_9217_12287_oct_pkt_num",
 309                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
 310         {"mac_tx_12288_16383_oct_pkt_num",
 311                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
 312         {"mac_tx_1519_max_good_pkt_num",
 313                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
 314         {"mac_tx_1519_max_bad_pkt_num",
 315                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
 316         {"mac_rx_total_pkt_num",
 317                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
 318         {"mac_rx_total_oct_num",
 319                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
 320         {"mac_rx_good_pkt_num",
 321                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
 322         {"mac_rx_bad_pkt_num",
 323                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
 324         {"mac_rx_good_oct_num",
 325                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
 326         {"mac_rx_bad_oct_num",
 327                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
 328         {"mac_rx_uni_pkt_num",
 329                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
 330         {"mac_rx_multi_pkt_num",
 331                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
 332         {"mac_rx_broad_pkt_num",
 333                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
 334         {"mac_rx_undersize_pkt_num",
 335                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
 336         {"mac_rx_oversize_pkt_num",
 337                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
 338         {"mac_rx_64_oct_pkt_num",
 339                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
 340         {"mac_rx_65_127_oct_pkt_num",
 341                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
 342         {"mac_rx_128_255_oct_pkt_num",
 343                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
 344         {"mac_rx_256_511_oct_pkt_num",
 345                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
 346         {"mac_rx_512_1023_oct_pkt_num",
 347                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
 348         {"mac_rx_1024_1518_oct_pkt_num",
 349                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
 350         {"mac_rx_1519_2047_oct_pkt_num",
 351                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
 352         {"mac_rx_2048_4095_oct_pkt_num",
 353                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
 354         {"mac_rx_4096_8191_oct_pkt_num",
 355                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
 356         {"mac_rx_8192_9216_oct_pkt_num",
 357                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
 358         {"mac_rx_9217_12287_oct_pkt_num",
 359                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
 360         {"mac_rx_12288_16383_oct_pkt_num",
 361                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
 362         {"mac_rx_1519_max_good_pkt_num",
 363                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
 364         {"mac_rx_1519_max_bad_pkt_num",
 365                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
 366
 367         {"mac_tx_fragment_pkt_num",
 368                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
 369         {"mac_tx_undermin_pkt_num",
 370                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
 371         {"mac_tx_jabber_pkt_num",
 372                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
 373         {"mac_tx_err_all_pkt_num",
 374                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
 375         {"mac_tx_from_app_good_pkt_num",
 376                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
 377         {"mac_tx_from_app_bad_pkt_num",
 378                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
 379         {"mac_rx_fragment_pkt_num",
 380                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
 381         {"mac_rx_undermin_pkt_num",
 382                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
 383         {"mac_rx_jabber_pkt_num",
 384                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
 385         {"mac_rx_fcs_err_pkt_num",
 386                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
 387         {"mac_rx_send_app_good_pkt_num",
 388                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
 389         {"mac_rx_send_app_bad_pkt_num",
 390                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
 391 };
 392
 393 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
 394         {
 395                 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
 396                 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
 397                 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
 398                 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
 399                 .i_port_bitmap = 0x1,
 400         },
 401 };
 402
 403 static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
 404 {
 405 #define HCLGE_64_BIT_CMD_NUM 5
 406 #define HCLGE_64_BIT_RTN_DATANUM 4
 407         u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
 408         struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
 409         __le64 *desc_data;
 410         int i, k, n;
 411         int ret;
 412
 413         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
 414         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
 415         if (ret) {
 416                 dev_err(&hdev->pdev->dev,
 417                         "Get 64 bit pkt stats fail, status = %d.\n", ret);
 418                 return ret;
 419         }
 420
 421         for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
 422                 if (unlikely(i == 0)) {
 423                         desc_data = (__le64 *)(&desc[i].data[0]);
 424                         n = HCLGE_64_BIT_RTN_DATANUM - 1;
 425                 } else {
 426                         desc_data = (__le64 *)(&desc[i]);
 427                         n = HCLGE_64_BIT_RTN_DATANUM;
 428                 }
 429                 for (k = 0; k < n; k++) {
 430                         *data++ += le64_to_cpu(*desc_data);
 431                         desc_data++;
 432                 }
 433         }
 434
 435         return 0;
 436 }
 437
 438 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
 439 {
 440         stats->pkt_curr_buf_cnt     = 0;
 441         stats->pkt_curr_buf_tc0_cnt = 0;
 442         stats->pkt_curr_buf_tc1_cnt = 0;
 443         stats->pkt_curr_buf_tc2_cnt = 0;
 444         stats->pkt_curr_buf_tc3_cnt = 0;
 445         stats->pkt_curr_buf_tc4_cnt = 0;
 446         stats->pkt_curr_buf_tc5_cnt = 0;
 447         stats->pkt_curr_buf_tc6_cnt = 0;
 448         stats->pkt_curr_buf_tc7_cnt = 0;
 449 }
 450
 451 static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
 452 {
 453 #define HCLGE_32_BIT_CMD_NUM 8
 454 #define HCLGE_32_BIT_RTN_DATANUM 8
 455
 456         struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
 457         struct hclge_32_bit_stats *all_32_bit_stats;
 458         __le32 *desc_data;
 459         int i, k, n;
 460         u64 *data;
 461         int ret;
 462
 463         all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
 464         data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
 465
 466         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
 467         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
 468         if (ret) {
 469                 dev_err(&hdev->pdev->dev,
 470                         "Get 32 bit pkt stats fail, status = %d.\n", ret);
 471
 472                 return ret;
 473         }
 474
 475         hclge_reset_partial_32bit_counter(all_32_bit_stats);
 476         for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
 477                 if (unlikely(i == 0)) {
 478                         __le16 *desc_data_16bit;
 479
 480                         all_32_bit_stats->igu_rx_err_pkt +=
 481                                 le32_to_cpu(desc[i].data[0]);
 482
 483                         desc_data_16bit = (__le16 *)&desc[i].data[1];
 484                         all_32_bit_stats->igu_rx_no_eof_pkt +=
 485                                 le16_to_cpu(*desc_data_16bit);
 486
 487                         desc_data_16bit++;
 488                         all_32_bit_stats->igu_rx_no_sof_pkt +=
 489                                 le16_to_cpu(*desc_data_16bit);
 490
 491                         desc_data = &desc[i].data[2];
 492                         n = HCLGE_32_BIT_RTN_DATANUM - 4;
 493                 } else {
 494                         desc_data = (__le32 *)&desc[i];
 495                         n = HCLGE_32_BIT_RTN_DATANUM;
 496                 }
 497                 for (k = 0; k < n; k++) {
 498                         *data++ += le32_to_cpu(*desc_data);
 499                         desc_data++;
 500                 }
 501         }
 502
 503         return 0;
 504 }
 505
 506 static int hclge_mac_update_stats(struct hclge_dev *hdev)
 507 {
 508 #define HCLGE_MAC_CMD_NUM 21
 509 #define HCLGE_RTN_DATA_NUM 4
 510
 511         u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
 512         struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
 513         __le64 *desc_data;
 514         int i, k, n;
 515         int ret;
 516
 517         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
 518         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
 519         if (ret) {
 520                 dev_err(&hdev->pdev->dev,
 521                         "Get MAC pkt stats fail, status = %d.\n", ret);
 522
 523                 return ret;
 524         }
 525
 526         for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
 527                 if (unlikely(i == 0)) {
 528                         desc_data = (__le64 *)(&desc[i].data[0]);
 529                         n = HCLGE_RTN_DATA_NUM - 2;
 530                 } else {
 531                         desc_data = (__le64 *)(&desc[i]);
 532                         n = HCLGE_RTN_DATA_NUM;
 533                 }
 534                 for (k = 0; k < n; k++) {
 535                         *data++ += le64_to_cpu(*desc_data);
 536                         desc_data++;
 537                 }
 538         }
 539
 540         return 0;
 541 }
 542
 543 static int hclge_tqps_update_stats(struct hnae3_handle *handle)
 544 {
 545         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 546         struct hclge_vport *vport = hclge_get_vport(handle);
 547         struct hclge_dev *hdev = vport->back;
 548         struct hnae3_queue *queue;
 549         struct hclge_desc desc[1];
 550         struct hclge_tqp *tqp;
 551         int ret, i;
 552
 553         for (i = 0; i < kinfo->num_tqps; i++) {
 554                 queue = handle->kinfo.tqp[i];
 555                 tqp = container_of(queue, struct hclge_tqp, q);
 556                 /* command : HCLGE_OPC_QUERY_IGU_STAT */
 557                 hclge_cmd_setup_basic_desc(&desc[0],
 558                                            HCLGE_OPC_QUERY_RX_STATUS,
 559                                            true);
 560
 561                 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
 562                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
 563                 if (ret) {
 564                         dev_err(&hdev->pdev->dev,
 565                                 "Query tqp stat fail, status = %d,queue = %d\n",
 566                                 ret,    i);
 567                         return ret;
 568                 }
 569                 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
 570                         le32_to_cpu(desc[0].data[1]);
 571         }
 572
 573         for (i = 0; i < kinfo->num_tqps; i++) {
 574                 queue = handle->kinfo.tqp[i];
 575                 tqp = container_of(queue, struct hclge_tqp, q);
 576                 /* command : HCLGE_OPC_QUERY_IGU_STAT */
 577                 hclge_cmd_setup_basic_desc(&desc[0],
 578                                            HCLGE_OPC_QUERY_TX_STATUS,
 579                                            true);
 580
 581                 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
 582                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
 583                 if (ret) {
 584                         dev_err(&hdev->pdev->dev,
 585                                 "Query tqp stat fail, status = %d,queue = %d\n",
 586                                 ret, i);
 587                         return ret;
 588                 }
 589                 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
 590                         le32_to_cpu(desc[0].data[1]);
 591         }
 592
 593         return 0;
 594 }
 595
 596 static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
 597 {
 598         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 599         struct hclge_tqp *tqp;
 600         u64 *buff = data;
 601         int i;
 602
 603         for (i = 0; i < kinfo->num_tqps; i++) {
 604                 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
 605                 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
 606         }
 607
 608         for (i = 0; i < kinfo->num_tqps; i++) {
 609                 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
 610                 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
 611         }
 612
 613         return buff;
 614 }
 615
 616 static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
 617 {
 618         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 619
 620         return kinfo->num_tqps * (2);
 621 }
 622
 623 static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
 624 {
 625         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 626         u8 *buff = data;
 627         int i = 0;
 628
 629         for (i = 0; i < kinfo->num_tqps; i++) {
 630                 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
 631                         struct hclge_tqp, q);
 632                 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd",
 633                          tqp->index);
 634                 buff = buff + ETH_GSTRING_LEN;
 635         }
 636
 637         for (i = 0; i < kinfo->num_tqps; i++) {
 638                 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
 639                         struct hclge_tqp, q);
 640                 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd",
 641                          tqp->index);
 642                 buff = buff + ETH_GSTRING_LEN;
 643         }
 644
 645         return buff;
 646 }
 647
 648 static u64 *hclge_comm_get_stats(void *comm_stats,
 649                                  const struct hclge_comm_stats_str strs[],
 650                                  int size, u64 *data)
 651 {
 652         u64 *buf = data;
 653         u32 i;
 654
 655         for (i = 0; i < size; i++)
 656                 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
 657
 658         return buf + size;
 659 }
 660
 661 static u8 *hclge_comm_get_strings(u32 stringset,
 662                                   const struct hclge_comm_stats_str strs[],
 663                                   int size, u8 *data)
 664 {
 665         char *buff = (char *)data;
 666         u32 i;
 667
 668         if (stringset != ETH_SS_STATS)
 669                 return buff;
 670
 671         for (i = 0; i < size; i++) {
 672                 snprintf(buff, ETH_GSTRING_LEN,
 673                          strs[i].desc);
 674                 buff = buff + ETH_GSTRING_LEN;
 675         }
 676
 677         return (u8 *)buff;
 678 }
 679
 680 static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
 681                                  struct net_device_stats *net_stats)
 682 {
 683         net_stats->tx_dropped = 0;
 684         net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
 685         net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
 686         net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
 687
 688         net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
 689         net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
 690         net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
 691         net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
 692         net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
 693
 694         net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
 695         net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
 696
 697         net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
 698         net_stats->rx_length_errors =
 699                 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
 700         net_stats->rx_length_errors +=
 701                 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
 702         net_stats->rx_over_errors =
 703                 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
 704 }
 705
 706 static void hclge_update_stats_for_all(struct hclge_dev *hdev)
 707 {
 708         struct hnae3_handle *handle;
 709         int status;
 710
 711         handle = &hdev->vport[0].nic;
 712         if (handle->client) {
 713                 status = hclge_tqps_update_stats(handle);
 714                 if (status) {
 715                         dev_err(&hdev->pdev->dev,
 716                                 "Update TQPS stats fail, status = %d.\n",
 717                                 status);
 718                 }
 719         }
 720
 721         status = hclge_mac_update_stats(hdev);
 722         if (status)
 723                 dev_err(&hdev->pdev->dev,
 724                         "Update MAC stats fail, status = %d.\n", status);
 725
 726         status = hclge_32_bit_update_stats(hdev);
 727         if (status)
 728                 dev_err(&hdev->pdev->dev,
 729                         "Update 32 bit stats fail, status = %d.\n",
 730                         status);
 731
 732         hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
 733 }
 734
 735 static void hclge_update_stats(struct hnae3_handle *handle,
 736                                struct net_device_stats *net_stats)
 737 {
 738         struct hclge_vport *vport = hclge_get_vport(handle);
 739         struct hclge_dev *hdev = vport->back;
 740         struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
 741         int status;
 742
 743         if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
 744                 return;
 745
 746         status = hclge_mac_update_stats(hdev);
 747         if (status)
 748                 dev_err(&hdev->pdev->dev,
 749                         "Update MAC stats fail, status = %d.\n",
 750                         status);
 751
 752         status = hclge_32_bit_update_stats(hdev);
 753         if (status)
 754                 dev_err(&hdev->pdev->dev,
 755                         "Update 32 bit stats fail, status = %d.\n",
 756                         status);
 757
 758         status = hclge_64_bit_update_stats(hdev);
 759         if (status)
 760                 dev_err(&hdev->pdev->dev,
 761                         "Update 64 bit stats fail, status = %d.\n",
 762                         status);
 763
 764         status = hclge_tqps_update_stats(handle);
 765         if (status)
 766                 dev_err(&hdev->pdev->dev,
 767                         "Update TQPS stats fail, status = %d.\n",
 768                         status);
 769
 770         hclge_update_netstat(hw_stats, net_stats);
 771
 772         clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
 773 }
 774
 775 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
 776 {
 777 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
 778
 779         struct hclge_vport *vport = hclge_get_vport(handle);
 780         struct hclge_dev *hdev = vport->back;
 781         int count = 0;
 782
 783         /* Loopback test support rules:
 784          * mac: only GE mode support
 785          * serdes: all mac mode will support include GE/XGE/LGE/CGE
 786          * phy: only support when phy device exist on board
 787          */
 788         if (stringset == ETH_SS_TEST) {
 789                 /* clear loopback bit flags at first */
 790                 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
 791                 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
 792                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
 793                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
 794                         count += 1;
 795                         handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
 796                 } else {
 797                         count = -EOPNOTSUPP;
 798                 }
 799         } else if (stringset == ETH_SS_STATS) {
 800                 count = ARRAY_SIZE(g_mac_stats_string) +
 801                         ARRAY_SIZE(g_all_32bit_stats_string) +
 802                         ARRAY_SIZE(g_all_64bit_stats_string) +
 803                         hclge_tqps_get_sset_count(handle, stringset);
 804         }
 805
 806         return count;
 807 }
 808
 809 static void hclge_get_strings(struct hnae3_handle *handle,
 810                               u32 stringset,
 811                               u8 *data)
 812 {
 813         u8 *p = (char *)data;
 814         int size;
 815
 816         if (stringset == ETH_SS_STATS) {
 817                 size = ARRAY_SIZE(g_mac_stats_string);
 818                 p = hclge_comm_get_strings(stringset,
 819                                            g_mac_stats_string,
 820                                            size,
 821                                            p);
 822                 size = ARRAY_SIZE(g_all_32bit_stats_string);
 823                 p = hclge_comm_get_strings(stringset,
 824                                            g_all_32bit_stats_string,
 825                                            size,
 826                                            p);
 827                 size = ARRAY_SIZE(g_all_64bit_stats_string);
 828                 p = hclge_comm_get_strings(stringset,
 829                                            g_all_64bit_stats_string,
 830                                            size,
 831                                            p);
 832                 p = hclge_tqps_get_strings(handle, p);
 833         } else if (stringset == ETH_SS_TEST) {
 834                 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
 835                         memcpy(p,
 836                                hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
 837                                ETH_GSTRING_LEN);
 838                         p += ETH_GSTRING_LEN;
 839                 }
 840                 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
 841                         memcpy(p,
 842                                hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
 843                                ETH_GSTRING_LEN);
 844                         p += ETH_GSTRING_LEN;
 845                 }
 846                 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
 847                         memcpy(p,
 848                                hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
 849                                ETH_GSTRING_LEN);
 850                         p += ETH_GSTRING_LEN;
 851                 }
 852         }
 853 }
 854
 855 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
 856 {
 857         struct hclge_vport *vport = hclge_get_vport(handle);
 858         struct hclge_dev *hdev = vport->back;
 859         u64 *p;
 860
 861         p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
 862                                  g_mac_stats_string,
 863                                  ARRAY_SIZE(g_mac_stats_string),
 864                                  data);
 865         p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
 866                                  g_all_32bit_stats_string,
 867                                  ARRAY_SIZE(g_all_32bit_stats_string),
 868                                  p);
 869         p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
 870                                  g_all_64bit_stats_string,
 871                                  ARRAY_SIZE(g_all_64bit_stats_string),
 872                                  p);
 873         p = hclge_tqps_get_stats(handle, p);
 874 }
 875
 876 static int hclge_parse_func_status(struct hclge_dev *hdev,
 877                                    struct hclge_func_status_cmd *status)
 878 {
 879         if (!(status->pf_state & HCLGE_PF_STATE_DONE))
 880                 return -EINVAL;
 881
 882         /* Set the pf to main pf */
 883         if (status->pf_state & HCLGE_PF_STATE_MAIN)
 884                 hdev->flag |= HCLGE_FLAG_MAIN;
 885         else
 886                 hdev->flag &= ~HCLGE_FLAG_MAIN;
 887
 888         return 0;
 889 }
 890
 891 static int hclge_query_function_status(struct hclge_dev *hdev)
 892 {
 893         struct hclge_func_status_cmd *req;
 894         struct hclge_desc desc;
 895         int timeout = 0;
 896         int ret;
 897
 898         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
 899         req = (struct hclge_func_status_cmd *)desc.data;
 900
 901         do {
 902                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 903                 if (ret) {
 904                         dev_err(&hdev->pdev->dev,
 905                                 "query function status failed %d.\n",
 906                                 ret);
 907
 908                         return ret;
 909                 }
 910
 911                 /* Check pf reset is done */
 912                 if (req->pf_state)
 913                         break;
 914                 usleep_range(1000, 2000);
 915         } while (timeout++ < 5);
 916
 917         ret = hclge_parse_func_status(hdev, req);
 918
 919         return ret;
 920 }
 921
 922 static int hclge_query_pf_resource(struct hclge_dev *hdev)
 923 {
 924         struct hclge_pf_res_cmd *req;
 925         struct hclge_desc desc;
 926         int ret;
 927
 928         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
 929         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 930         if (ret) {
 931                 dev_err(&hdev->pdev->dev,
 932                         "query pf resource failed %d.\n", ret);
 933                 return ret;
 934         }
 935
 936         req = (struct hclge_pf_res_cmd *)desc.data;
 937         hdev->num_tqps = __le16_to_cpu(req->tqp_num);
 938         hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
 939
 940         if (hnae3_dev_roce_supported(hdev)) {
 941                 hdev->num_roce_msi =
 942                 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
 943                                 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
 944
 945                 /* PF should have NIC vectors and Roce vectors,
 946                  * NIC vectors are queued before Roce vectors.
 947                  */
 948                 hdev->num_msi = hdev->num_roce_msi  + HCLGE_ROCE_VECTOR_OFFSET;
 949         } else {
 950                 hdev->num_msi =
 951                 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
 952                                 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
 953         }
 954
 955         return 0;
 956 }
 957
 958 static int hclge_parse_speed(int speed_cmd, int *speed)
 959 {
 960         switch (speed_cmd) {
 961         case 6:
 962                 *speed = HCLGE_MAC_SPEED_10M;
 963                 break;
 964         case 7:
 965                 *speed = HCLGE_MAC_SPEED_100M;
 966                 break;
 967         case 0:
 968                 *speed = HCLGE_MAC_SPEED_1G;
 969                 break;
 970         case 1:
 971                 *speed = HCLGE_MAC_SPEED_10G;
 972                 break;
 973         case 2:
 974                 *speed = HCLGE_MAC_SPEED_25G;
 975                 break;
 976         case 3:
 977                 *speed = HCLGE_MAC_SPEED_40G;
 978                 break;
 979         case 4:
 980                 *speed = HCLGE_MAC_SPEED_50G;
 981                 break;
 982         case 5:
 983                 *speed = HCLGE_MAC_SPEED_100G;
 984                 break;
 985         default:
 986                 return -EINVAL;
 987         }
 988
 989         return 0;
 990 }
 991
 992 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
 993                                         u8 speed_ability)
 994 {
 995         unsigned long *supported = hdev->hw.mac.supported;
 996
 997         if (speed_ability & HCLGE_SUPPORT_1G_BIT)
 998                 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
 999                         supported);
1000
1001         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
1002                 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
1003                         supported);
1004
1005         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1006                 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1007                         supported);
1008
1009         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1010                 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1011                         supported);
1012
1013         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1014                 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1015                         supported);
1016
1017         set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
1018         set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
1019 }
1020
1021 static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
1022 {
1023         u8 media_type = hdev->hw.mac.media_type;
1024
1025         if (media_type != HNAE3_MEDIA_TYPE_FIBER)
1026                 return;
1027
1028         hclge_parse_fiber_link_mode(hdev, speed_ability);
1029 }
1030
1031 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
1032 {
1033         struct hclge_cfg_param_cmd *req;
1034         u64 mac_addr_tmp_high;
1035         u64 mac_addr_tmp;
1036         int i;
1037
1038         req = (struct hclge_cfg_param_cmd *)desc[0].data;
1039
1040         /* get the configuration */
1041         cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1042                                               HCLGE_CFG_VMDQ_M,
1043                                               HCLGE_CFG_VMDQ_S);
1044         cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1045                                       HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
1046         cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1047                                             HCLGE_CFG_TQP_DESC_N_M,
1048                                             HCLGE_CFG_TQP_DESC_N_S);
1049
1050         cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
1051                                         HCLGE_CFG_PHY_ADDR_M,
1052                                         HCLGE_CFG_PHY_ADDR_S);
1053         cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
1054                                           HCLGE_CFG_MEDIA_TP_M,
1055                                           HCLGE_CFG_MEDIA_TP_S);
1056         cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
1057                                           HCLGE_CFG_RX_BUF_LEN_M,
1058                                           HCLGE_CFG_RX_BUF_LEN_S);
1059         /* get mac_address */
1060         mac_addr_tmp = __le32_to_cpu(req->param[2]);
1061         mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
1062                                             HCLGE_CFG_MAC_ADDR_H_M,
1063                                             HCLGE_CFG_MAC_ADDR_H_S);
1064
1065         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1066
1067         cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
1068                                              HCLGE_CFG_DEFAULT_SPEED_M,
1069                                              HCLGE_CFG_DEFAULT_SPEED_S);
1070         cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
1071                                             HCLGE_CFG_RSS_SIZE_M,
1072                                             HCLGE_CFG_RSS_SIZE_S);
1073
1074         for (i = 0; i < ETH_ALEN; i++)
1075                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1076
1077         req = (struct hclge_cfg_param_cmd *)desc[1].data;
1078         cfg->numa_node_map = __le32_to_cpu(req->param[0]);
1079
1080         cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
1081                                              HCLGE_CFG_SPEED_ABILITY_M,
1082                                              HCLGE_CFG_SPEED_ABILITY_S);
1083 }
1084
1085 /* hclge_get_cfg: query the static parameter from flash
1086  * @hdev: pointer to struct hclge_dev
1087  * @hcfg: the config structure to be getted
1088  */
1089 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1090 {
1091         struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
1092         struct hclge_cfg_param_cmd *req;
1093         int i, ret;
1094
1095         for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
1096                 u32 offset = 0;
1097
1098                 req = (struct hclge_cfg_param_cmd *)desc[i].data;
1099                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1100                                            true);
1101                 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
1102                                 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1103                 /* Len should be united by 4 bytes when send to hardware */
1104                 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
1105                                 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
1106                 req->offset = cpu_to_le32(offset);
1107         }
1108
1109         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1110         if (ret) {
1111                 dev_err(&hdev->pdev->dev,
1112                         "get config failed %d.\n", ret);
1113                 return ret;
1114         }
1115
1116         hclge_parse_cfg(hcfg, desc);
1117         return 0;
1118 }
1119
1120 static int hclge_get_cap(struct hclge_dev *hdev)
1121 {
1122         int ret;
1123
1124         ret = hclge_query_function_status(hdev);
1125         if (ret) {
1126                 dev_err(&hdev->pdev->dev,
1127                         "query function status error %d.\n", ret);
1128                 return ret;
1129         }
1130
1131         /* get pf resource */
1132         ret = hclge_query_pf_resource(hdev);
1133         if (ret) {
1134                 dev_err(&hdev->pdev->dev,
1135                         "query pf resource error %d.\n", ret);
1136                 return ret;
1137         }
1138
1139         return 0;
1140 }
1141
1142 static int hclge_configure(struct hclge_dev *hdev)
1143 {
1144         struct hclge_cfg cfg;
1145         int ret, i;
1146
1147         ret = hclge_get_cfg(hdev, &cfg);
1148         if (ret) {
1149                 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1150                 return ret;
1151         }
1152
1153         hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1154         hdev->base_tqp_pid = 0;
1155         hdev->rss_size_max = cfg.rss_size_max;
1156         hdev->rx_buf_len = cfg.rx_buf_len;
1157         ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
1158         hdev->hw.mac.media_type = cfg.media_type;
1159         hdev->hw.mac.phy_addr = cfg.phy_addr;
1160         hdev->num_desc = cfg.tqp_desc_num;
1161         hdev->tm_info.num_pg = 1;
1162         hdev->tc_max = cfg.tc_num;
1163         hdev->tm_info.hw_pfc_map = 0;
1164
1165         ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1166         if (ret) {
1167                 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1168                 return ret;
1169         }
1170
1171         hclge_parse_link_mode(hdev, cfg.speed_ability);
1172
1173         if ((hdev->tc_max > HNAE3_MAX_TC) ||
1174             (hdev->tc_max < 1)) {
1175                 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
1176                          hdev->tc_max);
1177                 hdev->tc_max = 1;
1178         }
1179
1180         /* Dev does not support DCB */
1181         if (!hnae3_dev_dcb_supported(hdev)) {
1182                 hdev->tc_max = 1;
1183                 hdev->pfc_max = 0;
1184         } else {
1185                 hdev->pfc_max = hdev->tc_max;
1186         }
1187
1188         hdev->tm_info.num_tc = hdev->tc_max;
1189
1190         /* Currently not support uncontiuous tc */
1191         for (i = 0; i < hdev->tm_info.num_tc; i++)
1192                 hnae3_set_bit(hdev->hw_tc_map, i, 1);
1193
1194         hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1195
1196         return ret;
1197 }
1198
1199 static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1200                             int tso_mss_max)
1201 {
1202         struct hclge_cfg_tso_status_cmd *req;
1203         struct hclge_desc desc;
1204         u16 tso_mss;
1205
1206         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1207
1208         req = (struct hclge_cfg_tso_status_cmd *)desc.data;
1209
1210         tso_mss = 0;
1211         hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1212                         HCLGE_TSO_MSS_MIN_S, tso_mss_min);
1213         req->tso_mss_min = cpu_to_le16(tso_mss);
1214
1215         tso_mss = 0;
1216         hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1217                         HCLGE_TSO_MSS_MIN_S, tso_mss_max);
1218         req->tso_mss_max = cpu_to_le16(tso_mss);
1219
1220         return hclge_cmd_send(&hdev->hw, &desc, 1);
1221 }
1222
1223 static int hclge_alloc_tqps(struct hclge_dev *hdev)
1224 {
1225         struct hclge_tqp *tqp;
1226         int i;
1227
1228         hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1229                                   sizeof(struct hclge_tqp), GFP_KERNEL);
1230         if (!hdev->htqp)
1231                 return -ENOMEM;
1232
1233         tqp = hdev->htqp;
1234
1235         for (i = 0; i < hdev->num_tqps; i++) {
1236                 tqp->dev = &hdev->pdev->dev;
1237                 tqp->index = i;
1238
1239                 tqp->q.ae_algo = &ae_algo;
1240                 tqp->q.buf_size = hdev->rx_buf_len;
1241                 tqp->q.desc_num = hdev->num_desc;
1242                 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1243                         i * HCLGE_TQP_REG_SIZE;
1244
1245                 tqp++;
1246         }
1247
1248         return 0;
1249 }
1250
1251 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1252                                   u16 tqp_pid, u16 tqp_vid, bool is_pf)
1253 {
1254         struct hclge_tqp_map_cmd *req;
1255         struct hclge_desc desc;
1256         int ret;
1257
1258         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1259
1260         req = (struct hclge_tqp_map_cmd *)desc.data;
1261         req->tqp_id = cpu_to_le16(tqp_pid);
1262         req->tqp_vf = func_id;
1263         req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1264                         1 << HCLGE_TQP_MAP_EN_B;
1265         req->tqp_vid = cpu_to_le16(tqp_vid);
1266
1267         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1268         if (ret) {
1269                 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1270                         ret);
1271                 return ret;
1272         }
1273
1274         return 0;
1275 }
1276
1277 static int  hclge_assign_tqp(struct hclge_vport *vport,
1278                              struct hnae3_queue **tqp, u16 num_tqps)
1279 {
1280         struct hclge_dev *hdev = vport->back;
1281         int i, alloced;
1282
1283         for (i = 0, alloced = 0; i < hdev->num_tqps &&
1284              alloced < num_tqps; i++) {
1285                 if (!hdev->htqp[i].alloced) {
1286                         hdev->htqp[i].q.handle = &vport->nic;
1287                         hdev->htqp[i].q.tqp_index = alloced;
1288                         tqp[alloced] = &hdev->htqp[i].q;
1289                         hdev->htqp[i].alloced = true;
1290                         alloced++;
1291                 }
1292         }
1293         vport->alloc_tqps = num_tqps;
1294
1295         return 0;
1296 }
1297
1298 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1299 {
1300         struct hnae3_handle *nic = &vport->nic;
1301         struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1302         struct hclge_dev *hdev = vport->back;
1303         int i, ret;
1304
1305         kinfo->num_desc = hdev->num_desc;
1306         kinfo->rx_buf_len = hdev->rx_buf_len;
1307         kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1308         kinfo->rss_size
1309                 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1310         kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1311
1312         for (i = 0; i < HNAE3_MAX_TC; i++) {
1313                 if (hdev->hw_tc_map & BIT(i)) {
1314                         kinfo->tc_info[i].enable = true;
1315                         kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1316                         kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1317                         kinfo->tc_info[i].tc = i;
1318                 } else {
1319                         /* Set to default queue if TC is disable */
1320                         kinfo->tc_info[i].enable = false;
1321                         kinfo->tc_info[i].tqp_offset = 0;
1322                         kinfo->tc_info[i].tqp_count = 1;
1323                         kinfo->tc_info[i].tc = 0;
1324                 }
1325         }
1326
1327         kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1328                                   sizeof(struct hnae3_queue *), GFP_KERNEL);
1329         if (!kinfo->tqp)
1330                 return -ENOMEM;
1331
1332         ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1333         if (ret) {
1334                 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1335                 return -EINVAL;
1336         }
1337
1338         return 0;
1339 }
1340
1341 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1342                                   struct hclge_vport *vport)
1343 {
1344         struct hnae3_handle *nic = &vport->nic;
1345         struct hnae3_knic_private_info *kinfo;
1346         u16 i;
1347
1348         kinfo = &nic->kinfo;
1349         for (i = 0; i < kinfo->num_tqps; i++) {
1350                 struct hclge_tqp *q =
1351                         container_of(kinfo->tqp[i], struct hclge_tqp, q);
1352                 bool is_pf;
1353                 int ret;
1354
1355                 is_pf = !(vport->vport_id);
1356                 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1357                                              i, is_pf);
1358                 if (ret)
1359                         return ret;
1360         }
1361
1362         return 0;
1363 }
1364
1365 static int hclge_map_tqp(struct hclge_dev *hdev)
1366 {
1367         struct hclge_vport *vport = hdev->vport;
1368         u16 i, num_vport;
1369
1370         num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1371         for (i = 0; i < num_vport; i++) {
1372                 int ret;
1373
1374                 ret = hclge_map_tqp_to_vport(hdev, vport);
1375                 if (ret)
1376                         return ret;
1377
1378                 vport++;
1379         }
1380
1381         return 0;
1382 }
1383
1384 static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1385 {
1386         /* this would be initialized later */
1387 }
1388
1389 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1390 {
1391         struct hnae3_handle *nic = &vport->nic;
1392         struct hclge_dev *hdev = vport->back;
1393         int ret;
1394
1395         nic->pdev = hdev->pdev;
1396         nic->ae_algo = &ae_algo;
1397         nic->numa_node_mask = hdev->numa_node_mask;
1398
1399         if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1400                 ret = hclge_knic_setup(vport, num_tqps);
1401                 if (ret) {
1402                         dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1403                                 ret);
1404                         return ret;
1405                 }
1406         } else {
1407                 hclge_unic_setup(vport, num_tqps);
1408         }
1409
1410         return 0;
1411 }
1412
1413 static int hclge_alloc_vport(struct hclge_dev *hdev)
1414 {
1415         struct pci_dev *pdev = hdev->pdev;
1416         struct hclge_vport *vport;
1417         u32 tqp_main_vport;
1418         u32 tqp_per_vport;
1419         int num_vport, i;
1420         int ret;
1421
1422         /* We need to alloc a vport for main NIC of PF */
1423         num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1424
1425         if (hdev->num_tqps < num_vport) {
1426                 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1427                         hdev->num_tqps, num_vport);
1428                 return -EINVAL;
1429         }
1430
1431         /* Alloc the same number of TQPs for every vport */
1432         tqp_per_vport = hdev->num_tqps / num_vport;
1433         tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1434
1435         vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1436                              GFP_KERNEL);
1437         if (!vport)
1438                 return -ENOMEM;
1439
1440         hdev->vport = vport;
1441         hdev->num_alloc_vport = num_vport;
1442
1443         if (IS_ENABLED(CONFIG_PCI_IOV))
1444                 hdev->num_alloc_vfs = hdev->num_req_vfs;
1445
1446         for (i = 0; i < num_vport; i++) {
1447                 vport->back = hdev;
1448                 vport->vport_id = i;
1449
1450                 if (i == 0)
1451                         ret = hclge_vport_setup(vport, tqp_main_vport);
1452                 else
1453                         ret = hclge_vport_setup(vport, tqp_per_vport);
1454                 if (ret) {
1455                         dev_err(&pdev->dev,
1456                                 "vport setup failed for vport %d, %d\n",
1457                                 i, ret);
1458                         return ret;
1459                 }
1460
1461                 vport++;
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int  hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1468                                     struct hclge_pkt_buf_alloc *buf_alloc)
1469 {
1470 /* TX buffer size is unit by 128 byte */
1471 #define HCLGE_BUF_SIZE_UNIT_SHIFT       7
1472 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK    BIT(15)
1473         struct hclge_tx_buff_alloc_cmd *req;
1474         struct hclge_desc desc;
1475         int ret;
1476         u8 i;
1477
1478         req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
1479
1480         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1481         for (i = 0; i < HCLGE_TC_NUM; i++) {
1482                 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1483
1484                 req->tx_pkt_buff[i] =
1485                         cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1486                                      HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1487         }
1488
1489         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1490         if (ret) {
1491                 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1492                         ret);
1493                 return ret;
1494         }
1495
1496         return 0;
1497 }
1498
1499 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1500                                  struct hclge_pkt_buf_alloc *buf_alloc)
1501 {
1502         int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
1503
1504         if (ret) {
1505                 dev_err(&hdev->pdev->dev,
1506                         "tx buffer alloc failed %d\n", ret);
1507                 return ret;
1508         }
1509
1510         return 0;
1511 }
1512
1513 static int hclge_get_tc_num(struct hclge_dev *hdev)
1514 {
1515         int i, cnt = 0;
1516
1517         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1518                 if (hdev->hw_tc_map & BIT(i))
1519                         cnt++;
1520         return cnt;
1521 }
1522
1523 static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1524 {
1525         int i, cnt = 0;
1526
1527         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1528                 if (hdev->hw_tc_map & BIT(i) &&
1529                     hdev->tm_info.hw_pfc_map & BIT(i))
1530                         cnt++;
1531         return cnt;
1532 }
1533
1534 /* Get the number of pfc enabled TCs, which have private buffer */
1535 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1536                                   struct hclge_pkt_buf_alloc *buf_alloc)
1537 {
1538         struct hclge_priv_buf *priv;
1539         int i, cnt = 0;
1540
1541         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1542                 priv = &buf_alloc->priv_buf[i];
1543                 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1544                     priv->enable)
1545                         cnt++;
1546         }
1547
1548         return cnt;
1549 }
1550
1551 /* Get the number of pfc disabled TCs, which have private buffer */
1552 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1553                                      struct hclge_pkt_buf_alloc *buf_alloc)
1554 {
1555         struct hclge_priv_buf *priv;
1556         int i, cnt = 0;
1557
1558         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1559                 priv = &buf_alloc->priv_buf[i];
1560                 if (hdev->hw_tc_map & BIT(i) &&
1561                     !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1562                     priv->enable)
1563                         cnt++;
1564         }
1565
1566         return cnt;
1567 }
1568
1569 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1570 {
1571         struct hclge_priv_buf *priv;
1572         u32 rx_priv = 0;
1573         int i;
1574
1575         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1576                 priv = &buf_alloc->priv_buf[i];
1577                 if (priv->enable)
1578                         rx_priv += priv->buf_size;
1579         }
1580         return rx_priv;
1581 }
1582
1583 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1584 {
1585         u32 i, total_tx_size = 0;
1586
1587         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1588                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1589
1590         return total_tx_size;
1591 }
1592
1593 static bool  hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1594                                 struct hclge_pkt_buf_alloc *buf_alloc,
1595                                 u32 rx_all)
1596 {
1597         u32 shared_buf_min, shared_buf_tc, shared_std;
1598         int tc_num, pfc_enable_num;
1599         u32 shared_buf;
1600         u32 rx_priv;
1601         int i;
1602
1603         tc_num = hclge_get_tc_num(hdev);
1604         pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1605
1606         if (hnae3_dev_dcb_supported(hdev))
1607                 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1608         else
1609                 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1610
1611         shared_buf_tc = pfc_enable_num * hdev->mps +
1612                         (tc_num - pfc_enable_num) * hdev->mps / 2 +
1613                         hdev->mps;
1614         shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1615
1616         rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
1617         if (rx_all <= rx_priv + shared_std)
1618                 return false;
1619
1620         shared_buf = rx_all - rx_priv;
1621         buf_alloc->s_buf.buf_size = shared_buf;
1622         buf_alloc->s_buf.self.high = shared_buf;
1623         buf_alloc->s_buf.self.low =  2 * hdev->mps;
1624
1625         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1626                 if ((hdev->hw_tc_map & BIT(i)) &&
1627                     (hdev->tm_info.hw_pfc_map & BIT(i))) {
1628                         buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1629                         buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
1630                 } else {
1631                         buf_alloc->s_buf.tc_thrd[i].low = 0;
1632                         buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
1633                 }
1634         }
1635
1636         return true;
1637 }
1638
1639 static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1640                                 struct hclge_pkt_buf_alloc *buf_alloc)
1641 {
1642         u32 i, total_size;
1643
1644         total_size = hdev->pkt_buf_size;
1645
1646         /* alloc tx buffer for all enabled tc */
1647         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1648                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1649
1650                 if (total_size < HCLGE_DEFAULT_TX_BUF)
1651                         return -ENOMEM;
1652
1653                 if (hdev->hw_tc_map & BIT(i))
1654                         priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1655                 else
1656                         priv->tx_buf_size = 0;
1657
1658                 total_size -= priv->tx_buf_size;
1659         }
1660
1661         return 0;
1662 }
1663
1664 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1665  * @hdev: pointer to struct hclge_dev
1666  * @buf_alloc: pointer to buffer calculation data
1667  * @return: 0: calculate sucessful, negative: fail
1668  */
1669 static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1670                                 struct hclge_pkt_buf_alloc *buf_alloc)
1671 {
1672         u32 rx_all = hdev->pkt_buf_size;
1673         int no_pfc_priv_num, pfc_priv_num;
1674         struct hclge_priv_buf *priv;
1675         int i;
1676
1677         rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
1678
1679         /* When DCB is not supported, rx private
1680          * buffer is not allocated.
1681          */
1682         if (!hnae3_dev_dcb_supported(hdev)) {
1683                 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1684                         return -ENOMEM;
1685
1686                 return 0;
1687         }
1688
1689         /* step 1, try to alloc private buffer for all enabled tc */
1690         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1691                 priv = &buf_alloc->priv_buf[i];
1692                 if (hdev->hw_tc_map & BIT(i)) {
1693                         priv->enable = 1;
1694                         if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1695                                 priv->wl.low = hdev->mps;
1696                                 priv->wl.high = priv->wl.low + hdev->mps;
1697                                 priv->buf_size = priv->wl.high +
1698                                                 HCLGE_DEFAULT_DV;
1699                         } else {
1700                                 priv->wl.low = 0;
1701                                 priv->wl.high = 2 * hdev->mps;
1702                                 priv->buf_size = priv->wl.high;
1703                         }
1704                 } else {
1705                         priv->enable = 0;
1706                         priv->wl.low = 0;
1707                         priv->wl.high = 0;
1708                         priv->buf_size = 0;
1709                 }
1710         }
1711
1712         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1713                 return 0;
1714
1715         /* step 2, try to decrease the buffer size of
1716          * no pfc TC's private buffer
1717          */
1718         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1719                 priv = &buf_alloc->priv_buf[i];
1720
1721                 priv->enable = 0;
1722                 priv->wl.low = 0;
1723                 priv->wl.high = 0;
1724                 priv->buf_size = 0;
1725
1726                 if (!(hdev->hw_tc_map & BIT(i)))
1727                         continue;
1728
1729                 priv->enable = 1;
1730
1731                 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1732                         priv->wl.low = 128;
1733                         priv->wl.high = priv->wl.low + hdev->mps;
1734                         priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1735                 } else {
1736                         priv->wl.low = 0;
1737                         priv->wl.high = hdev->mps;
1738                         priv->buf_size = priv->wl.high;
1739                 }
1740         }
1741
1742         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1743                 return 0;
1744
1745         /* step 3, try to reduce the number of pfc disabled TCs,
1746          * which have private buffer
1747          */
1748         /* get the total no pfc enable TC number, which have private buffer */
1749         no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
1750
1751         /* let the last to be cleared first */
1752         for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1753                 priv = &buf_alloc->priv_buf[i];
1754
1755                 if (hdev->hw_tc_map & BIT(i) &&
1756                     !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1757                         /* Clear the no pfc TC private buffer */
1758                         priv->wl.low = 0;
1759                         priv->wl.high = 0;
1760                         priv->buf_size = 0;
1761                         priv->enable = 0;
1762                         no_pfc_priv_num--;
1763                 }
1764
1765                 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1766                     no_pfc_priv_num == 0)
1767                         break;
1768         }
1769
1770         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1771                 return 0;
1772
1773         /* step 4, try to reduce the number of pfc enabled TCs
1774          * which have private buffer.
1775          */
1776         pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
1777
1778         /* let the last to be cleared first */
1779         for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1780                 priv = &buf_alloc->priv_buf[i];
1781
1782                 if (hdev->hw_tc_map & BIT(i) &&
1783                     hdev->tm_info.hw_pfc_map & BIT(i)) {
1784                         /* Reduce the number of pfc TC with private buffer */
1785                         priv->wl.low = 0;
1786                         priv->enable = 0;
1787                         priv->wl.high = 0;
1788                         priv->buf_size = 0;
1789                         pfc_priv_num--;
1790                 }
1791
1792                 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1793                     pfc_priv_num == 0)
1794                         break;
1795         }
1796         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1797                 return 0;
1798
1799         return -ENOMEM;
1800 }
1801
1802 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1803                                    struct hclge_pkt_buf_alloc *buf_alloc)
1804 {
1805         struct hclge_rx_priv_buff_cmd *req;
1806         struct hclge_desc desc;
1807         int ret;
1808         int i;
1809
1810         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
1811         req = (struct hclge_rx_priv_buff_cmd *)desc.data;
1812
1813         /* Alloc private buffer TCs */
1814         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1815                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1816
1817                 req->buf_num[i] =
1818                         cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1819                 req->buf_num[i] |=
1820                         cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
1821         }
1822
1823         req->shared_buf =
1824                 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
1825                             (1 << HCLGE_TC0_PRI_BUF_EN_B));
1826
1827         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1828         if (ret) {
1829                 dev_err(&hdev->pdev->dev,
1830                         "rx private buffer alloc cmd failed %d\n", ret);
1831                 return ret;
1832         }
1833
1834         return 0;
1835 }
1836
1837 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1838                                    struct hclge_pkt_buf_alloc *buf_alloc)
1839 {
1840         struct hclge_rx_priv_wl_buf *req;
1841         struct hclge_priv_buf *priv;
1842         struct hclge_desc desc[2];
1843         int i, j;
1844         int ret;
1845
1846         for (i = 0; i < 2; i++) {
1847                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1848                                            false);
1849                 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1850
1851                 /* The first descriptor set the NEXT bit to 1 */
1852                 if (i == 0)
1853                         desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1854                 else
1855                         desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1856
1857                 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1858                         u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1859
1860                         priv = &buf_alloc->priv_buf[idx];
1861                         req->tc_wl[j].high =
1862                                 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1863                         req->tc_wl[j].high |=
1864                                 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1865                         req->tc_wl[j].low =
1866                                 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1867                         req->tc_wl[j].low |=
1868                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1869                 }
1870         }
1871
1872         /* Send 2 descriptor at one time */
1873         ret = hclge_cmd_send(&hdev->hw, desc, 2);
1874         if (ret) {
1875                 dev_err(&hdev->pdev->dev,
1876                         "rx private waterline config cmd failed %d\n",
1877                         ret);
1878                 return ret;
1879         }
1880         return 0;
1881 }
1882
1883 static int hclge_common_thrd_config(struct hclge_dev *hdev,
1884                                     struct hclge_pkt_buf_alloc *buf_alloc)
1885 {
1886         struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
1887         struct hclge_rx_com_thrd *req;
1888         struct hclge_desc desc[2];
1889         struct hclge_tc_thrd *tc;
1890         int i, j;
1891         int ret;
1892
1893         for (i = 0; i < 2; i++) {
1894                 hclge_cmd_setup_basic_desc(&desc[i],
1895                                            HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1896                 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1897
1898                 /* The first descriptor set the NEXT bit to 1 */
1899                 if (i == 0)
1900                         desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1901                 else
1902                         desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1903
1904                 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1905                         tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1906
1907                         req->com_thrd[j].high =
1908                                 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1909                         req->com_thrd[j].high |=
1910                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1911                         req->com_thrd[j].low =
1912                                 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1913                         req->com_thrd[j].low |=
1914                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1915                 }
1916         }
1917
1918         /* Send 2 descriptors at one time */
1919         ret = hclge_cmd_send(&hdev->hw, desc, 2);
1920         if (ret) {
1921                 dev_err(&hdev->pdev->dev,
1922                         "common threshold config cmd failed %d\n", ret);
1923                 return ret;
1924         }
1925         return 0;
1926 }
1927
1928 static int hclge_common_wl_config(struct hclge_dev *hdev,
1929                                   struct hclge_pkt_buf_alloc *buf_alloc)
1930 {
1931         struct hclge_shared_buf *buf = &buf_alloc->s_buf;
1932         struct hclge_rx_com_wl *req;
1933         struct hclge_desc desc;
1934         int ret;
1935
1936         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1937
1938         req = (struct hclge_rx_com_wl *)desc.data;
1939         req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1940         req->com_wl.high |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1941
1942         req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1943         req->com_wl.low |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1944
1945         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1946         if (ret) {
1947                 dev_err(&hdev->pdev->dev,
1948                         "common waterline config cmd failed %d\n", ret);
1949                 return ret;
1950         }
1951
1952         return 0;
1953 }
1954
1955 int hclge_buffer_alloc(struct hclge_dev *hdev)
1956 {
1957         struct hclge_pkt_buf_alloc *pkt_buf;
1958         int ret;
1959
1960         pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1961         if (!pkt_buf)
1962                 return -ENOMEM;
1963
1964         ret = hclge_tx_buffer_calc(hdev, pkt_buf);
1965         if (ret) {
1966                 dev_err(&hdev->pdev->dev,
1967                         "could not calc tx buffer size for all TCs %d\n", ret);
1968                 goto out;
1969         }
1970
1971         ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
1972         if (ret) {
1973                 dev_err(&hdev->pdev->dev,
1974                         "could not alloc tx buffers %d\n", ret);
1975                 goto out;
1976         }
1977
1978         ret = hclge_rx_buffer_calc(hdev, pkt_buf);
1979         if (ret) {
1980                 dev_err(&hdev->pdev->dev,
1981                         "could not calc rx priv buffer size for all TCs %d\n",
1982                         ret);
1983                 goto out;
1984         }
1985
1986         ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
1987         if (ret) {
1988                 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1989                         ret);
1990                 goto out;
1991         }
1992
1993         if (hnae3_dev_dcb_supported(hdev)) {
1994                 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
1995                 if (ret) {
1996                         dev_err(&hdev->pdev->dev,
1997                                 "could not configure rx private waterline %d\n",
1998                                 ret);
1999                         goto out;
2000                 }
2001
2002                 ret = hclge_common_thrd_config(hdev, pkt_buf);
2003                 if (ret) {
2004                         dev_err(&hdev->pdev->dev,
2005                                 "could not configure common threshold %d\n",
2006                                 ret);
2007                         goto out;
2008                 }
2009         }
2010
2011         ret = hclge_common_wl_config(hdev, pkt_buf);
2012         if (ret)
2013                 dev_err(&hdev->pdev->dev,
2014                         "could not configure common waterline %d\n", ret);
2015
2016 out:
2017         kfree(pkt_buf);
2018         return ret;
2019 }
2020
2021 static int hclge_init_roce_base_info(struct hclge_vport *vport)
2022 {
2023         struct hnae3_handle *roce = &vport->roce;
2024         struct hnae3_handle *nic = &vport->nic;
2025
2026         roce->rinfo.num_vectors = vport->back->num_roce_msi;
2027
2028         if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
2029             vport->back->num_msi_left == 0)
2030                 return -EINVAL;
2031
2032         roce->rinfo.base_vector = vport->back->roce_base_vector;
2033
2034         roce->rinfo.netdev = nic->kinfo.netdev;
2035         roce->rinfo.roce_io_base = vport->back->hw.io_base;
2036
2037         roce->pdev = nic->pdev;
2038         roce->ae_algo = nic->ae_algo;
2039         roce->numa_node_mask = nic->numa_node_mask;
2040
2041         return 0;
2042 }
2043
2044 static int hclge_init_msi(struct hclge_dev *hdev)
2045 {
2046         struct pci_dev *pdev = hdev->pdev;
2047         int vectors;
2048         int i;
2049
2050         vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
2051                                         PCI_IRQ_MSI | PCI_IRQ_MSIX);
2052         if (vectors < 0) {
2053                 dev_err(&pdev->dev,
2054                         "failed(%d) to allocate MSI/MSI-X vectors\n",
2055                         vectors);
2056                 return vectors;
2057         }
2058         if (vectors < hdev->num_msi)
2059                 dev_warn(&hdev->pdev->dev,
2060                          "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2061                          hdev->num_msi, vectors);
2062
2063         hdev->num_msi = vectors;
2064         hdev->num_msi_left = vectors;
2065         hdev->base_msi_vector = pdev->irq;
2066         hdev->roce_base_vector = hdev->base_msi_vector +
2067                                 HCLGE_ROCE_VECTOR_OFFSET;
2068
2069         hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2070                                            sizeof(u16), GFP_KERNEL);
2071         if (!hdev->vector_status) {
2072                 pci_free_irq_vectors(pdev);
2073                 return -ENOMEM;
2074         }
2075
2076         for (i = 0; i < hdev->num_msi; i++)
2077                 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2078
2079         hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2080                                         sizeof(int), GFP_KERNEL);
2081         if (!hdev->vector_irq) {
2082                 pci_free_irq_vectors(pdev);
2083                 return -ENOMEM;
2084         }
2085
2086         return 0;
2087 }
2088
2089 static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2090 {
2091         struct hclge_mac *mac = &hdev->hw.mac;
2092
2093         if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2094                 mac->duplex = (u8)duplex;
2095         else
2096                 mac->duplex = HCLGE_MAC_FULL;
2097
2098         mac->speed = speed;
2099 }
2100
2101 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2102 {
2103         struct hclge_config_mac_speed_dup_cmd *req;
2104         struct hclge_desc desc;
2105         int ret;
2106
2107         req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
2108
2109         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2110
2111         hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2112
2113         switch (speed) {
2114         case HCLGE_MAC_SPEED_10M:
2115                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2116                                 HCLGE_CFG_SPEED_S, 6);
2117                 break;
2118         case HCLGE_MAC_SPEED_100M:
2119                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2120                                 HCLGE_CFG_SPEED_S, 7);
2121                 break;
2122         case HCLGE_MAC_SPEED_1G:
2123                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2124                                 HCLGE_CFG_SPEED_S, 0);
2125                 break;
2126         case HCLGE_MAC_SPEED_10G:
2127                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2128                                 HCLGE_CFG_SPEED_S, 1);
2129                 break;
2130         case HCLGE_MAC_SPEED_25G:
2131                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2132                                 HCLGE_CFG_SPEED_S, 2);
2133                 break;
2134         case HCLGE_MAC_SPEED_40G:
2135                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2136                                 HCLGE_CFG_SPEED_S, 3);
2137                 break;
2138         case HCLGE_MAC_SPEED_50G:
2139                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2140                                 HCLGE_CFG_SPEED_S, 4);
2141                 break;
2142         case HCLGE_MAC_SPEED_100G:
2143                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2144                                 HCLGE_CFG_SPEED_S, 5);
2145                 break;
2146         default:
2147                 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
2148                 return -EINVAL;
2149         }
2150
2151         hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2152                       1);
2153
2154         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2155         if (ret) {
2156                 dev_err(&hdev->pdev->dev,
2157                         "mac speed/duplex config cmd failed %d.\n", ret);
2158                 return ret;
2159         }
2160
2161         hclge_check_speed_dup(hdev, duplex, speed);
2162
2163         return 0;
2164 }
2165
2166 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2167                                      u8 duplex)
2168 {
2169         struct hclge_vport *vport = hclge_get_vport(handle);
2170         struct hclge_dev *hdev = vport->back;
2171
2172         return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2173 }
2174
2175 static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2176                                         u8 *duplex)
2177 {
2178         struct hclge_query_an_speed_dup_cmd *req;
2179         struct hclge_desc desc;
2180         int speed_tmp;
2181         int ret;
2182
2183         req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
2184
2185         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2186         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2187         if (ret) {
2188                 dev_err(&hdev->pdev->dev,
2189                         "mac speed/autoneg/duplex query cmd failed %d\n",
2190                         ret);
2191                 return ret;
2192         }
2193
2194         *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2195         speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2196                                     HCLGE_QUERY_SPEED_S);
2197
2198         ret = hclge_parse_speed(speed_tmp, speed);
2199         if (ret) {
2200                 dev_err(&hdev->pdev->dev,
2201                         "could not parse speed(=%d), %d\n", speed_tmp, ret);
2202                 return -EIO;
2203         }
2204
2205         return 0;
2206 }
2207
2208 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2209 {
2210         struct hclge_config_auto_neg_cmd *req;
2211         struct hclge_desc desc;
2212         u32 flag = 0;
2213         int ret;
2214
2215         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2216
2217         req = (struct hclge_config_auto_neg_cmd *)desc.data;
2218         hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2219         req->cfg_an_cmd_flag = cpu_to_le32(flag);
2220
2221         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2222         if (ret) {
2223                 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2224                         ret);
2225                 return ret;
2226         }
2227
2228         return 0;
2229 }
2230
2231 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2232 {
2233         struct hclge_vport *vport = hclge_get_vport(handle);
2234         struct hclge_dev *hdev = vport->back;
2235
2236         return hclge_set_autoneg_en(hdev, enable);
2237 }
2238
2239 static int hclge_get_autoneg(struct hnae3_handle *handle)
2240 {
2241         struct hclge_vport *vport = hclge_get_vport(handle);
2242         struct hclge_dev *hdev = vport->back;
2243         struct phy_device *phydev = hdev->hw.mac.phydev;
2244
2245         if (phydev)
2246                 return phydev->autoneg;
2247
2248         return hdev->hw.mac.autoneg;
2249 }
2250
2251 static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
2252                                            bool mask_vlan,
2253                                            u8 *mac_mask)
2254 {
2255         struct hclge_mac_vlan_mask_entry_cmd *req;
2256         struct hclge_desc desc;
2257         int status;
2258
2259         req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
2260         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
2261
2262         hnae3_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
2263                       mask_vlan ? 1 : 0);
2264         ether_addr_copy(req->mac_mask, mac_mask);
2265
2266         status = hclge_cmd_send(&hdev->hw, &desc, 1);
2267         if (status)
2268                 dev_err(&hdev->pdev->dev,
2269                         "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2270                         status);
2271
2272         return status;
2273 }
2274
2275 static int hclge_mac_init(struct hclge_dev *hdev)
2276 {
2277         struct hnae3_handle *handle = &hdev->vport[0].nic;
2278         struct net_device *netdev = handle->kinfo.netdev;
2279         struct hclge_mac *mac = &hdev->hw.mac;
2280         u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2281         struct hclge_vport *vport;
2282         int mtu;
2283         int ret;
2284         int i;
2285
2286         ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2287         if (ret) {
2288                 dev_err(&hdev->pdev->dev,
2289                         "Config mac speed dup fail ret=%d\n", ret);
2290                 return ret;
2291         }
2292
2293         mac->link = 0;
2294
2295         /* Initialize the MTA table work mode */
2296         hdev->enable_mta        = true;
2297         hdev->mta_mac_sel_type  = HCLGE_MAC_ADDR_47_36;
2298
2299         ret = hclge_set_mta_filter_mode(hdev,
2300                                         hdev->mta_mac_sel_type,
2301                                         hdev->enable_mta);
2302         if (ret) {
2303                 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2304                         ret);
2305                 return ret;
2306         }
2307
2308         for (i = 0; i < hdev->num_alloc_vport; i++) {
2309                 vport = &hdev->vport[i];
2310                 vport->accept_mta_mc = false;
2311
2312                 memset(vport->mta_shadow, 0, sizeof(vport->mta_shadow));
2313                 ret = hclge_cfg_func_mta_filter(hdev, vport->vport_id, false);
2314                 if (ret) {
2315                         dev_err(&hdev->pdev->dev,
2316                                 "set mta filter mode fail ret=%d\n", ret);
2317                         return ret;
2318                 }
2319         }
2320
2321         ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
2322         if (ret) {
2323                 dev_err(&hdev->pdev->dev,
2324                         "set default mac_vlan_mask fail ret=%d\n", ret);
2325                 return ret;
2326         }
2327
2328         if (netdev)
2329                 mtu = netdev->mtu;
2330         else
2331                 mtu = ETH_DATA_LEN;
2332
2333         ret = hclge_set_mtu(handle, mtu);
2334         if (ret) {
2335                 dev_err(&hdev->pdev->dev,
2336                         "set mtu failed ret=%d\n", ret);
2337                 return ret;
2338         }
2339
2340         return 0;
2341 }
2342
2343 static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2344 {
2345         if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2346                 schedule_work(&hdev->mbx_service_task);
2347 }
2348
2349 static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2350 {
2351         if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2352                 schedule_work(&hdev->rst_service_task);
2353 }
2354
2355 static void hclge_task_schedule(struct hclge_dev *hdev)
2356 {
2357         if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2358             !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2359             !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2360                 (void)schedule_work(&hdev->service_task);
2361 }
2362
2363 static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2364 {
2365         struct hclge_link_status_cmd *req;
2366         struct hclge_desc desc;
2367         int link_status;
2368         int ret;
2369
2370         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2371         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2372         if (ret) {
2373                 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2374                         ret);
2375                 return ret;
2376         }
2377
2378         req = (struct hclge_link_status_cmd *)desc.data;
2379         link_status = req->status & HCLGE_LINK_STATUS;
2380
2381         return !!link_status;
2382 }
2383
2384 static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2385 {
2386         int mac_state;
2387         int link_stat;
2388
2389         mac_state = hclge_get_mac_link_status(hdev);
2390
2391         if (hdev->hw.mac.phydev) {
2392                 if (!genphy_read_status(hdev->hw.mac.phydev))
2393                         link_stat = mac_state &
2394                                 hdev->hw.mac.phydev->link;
2395                 else
2396                         link_stat = 0;
2397
2398         } else {
2399                 link_stat = mac_state;
2400         }
2401
2402         return !!link_stat;
2403 }
2404
2405 static void hclge_update_link_status(struct hclge_dev *hdev)
2406 {
2407         struct hnae3_client *client = hdev->nic_client;
2408         struct hnae3_handle *handle;
2409         int state;
2410         int i;
2411
2412         if (!client)
2413                 return;
2414         state = hclge_get_mac_phy_link(hdev);
2415         if (state != hdev->hw.mac.link) {
2416                 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2417                         handle = &hdev->vport[i].nic;
2418                         client->ops->link_status_change(handle, state);
2419                 }
2420                 hdev->hw.mac.link = state;
2421         }
2422 }
2423
2424 static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2425 {
2426         struct hclge_mac mac = hdev->hw.mac;
2427         u8 duplex;
2428         int speed;
2429         int ret;
2430
2431         /* get the speed and duplex as autoneg'result from mac cmd when phy
2432          * doesn't exit.
2433          */
2434         if (mac.phydev || !mac.autoneg)
2435                 return 0;
2436
2437         ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2438         if (ret) {
2439                 dev_err(&hdev->pdev->dev,
2440                         "mac autoneg/speed/duplex query failed %d\n", ret);
2441                 return ret;
2442         }
2443
2444         if ((mac.speed != speed) || (mac.duplex != duplex)) {
2445                 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2446                 if (ret) {
2447                         dev_err(&hdev->pdev->dev,
2448                                 "mac speed/duplex config failed %d\n", ret);
2449                         return ret;
2450                 }
2451         }
2452
2453         return 0;
2454 }
2455
2456 static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2457 {
2458         struct hclge_vport *vport = hclge_get_vport(handle);
2459         struct hclge_dev *hdev = vport->back;
2460
2461         return hclge_update_speed_duplex(hdev);
2462 }
2463
2464 static int hclge_get_status(struct hnae3_handle *handle)
2465 {
2466         struct hclge_vport *vport = hclge_get_vport(handle);
2467         struct hclge_dev *hdev = vport->back;
2468
2469         hclge_update_link_status(hdev);
2470
2471         return hdev->hw.mac.link;
2472 }
2473
2474 static void hclge_service_timer(struct timer_list *t)
2475 {
2476         struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
2477
2478         mod_timer(&hdev->service_timer, jiffies + HZ);
2479         hdev->hw_stats.stats_timer++;
2480         hclge_task_schedule(hdev);
2481 }
2482
2483 static void hclge_service_complete(struct hclge_dev *hdev)
2484 {
2485         WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2486
2487         /* Flush memory before next watchdog */
2488         smp_mb__before_atomic();
2489         clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2490 }
2491
2492 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2493 {
2494         u32 rst_src_reg;
2495         u32 cmdq_src_reg;
2496
2497         /* fetch the events from their corresponding regs */
2498         rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
2499         cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2500
2501         /* Assumption: If by any chance reset and mailbox events are reported
2502          * together then we will only process reset event in this go and will
2503          * defer the processing of the mailbox events. Since, we would have not
2504          * cleared RX CMDQ event this time we would receive again another
2505          * interrupt from H/W just for the mailbox.
2506          */
2507
2508         /* check for vector0 reset event sources */
2509         if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2510                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2511                 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2512                 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2513                 return HCLGE_VECTOR0_EVENT_RST;
2514         }
2515
2516         if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2517                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2518                 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2519                 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2520                 return HCLGE_VECTOR0_EVENT_RST;
2521         }
2522
2523         if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2524                 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2525                 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2526                 return HCLGE_VECTOR0_EVENT_RST;
2527         }
2528
2529         /* check for vector0 mailbox(=CMDQ RX) event source */
2530         if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2531                 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2532                 *clearval = cmdq_src_reg;
2533                 return HCLGE_VECTOR0_EVENT_MBX;
2534         }
2535
2536         return HCLGE_VECTOR0_EVENT_OTHER;
2537 }
2538
2539 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2540                                     u32 regclr)
2541 {
2542         switch (event_type) {
2543         case HCLGE_VECTOR0_EVENT_RST:
2544                 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
2545                 break;
2546         case HCLGE_VECTOR0_EVENT_MBX:
2547                 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2548                 break;
2549         }
2550 }
2551
2552 static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
2553 {
2554         hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
2555                                 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
2556                                 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
2557                                 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
2558         hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
2559 }
2560
2561 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2562 {
2563         writel(enable ? 1 : 0, vector->addr);
2564 }
2565
2566 static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2567 {
2568         struct hclge_dev *hdev = data;
2569         u32 event_cause;
2570         u32 clearval;
2571
2572         hclge_enable_vector(&hdev->misc_vector, false);
2573         event_cause = hclge_check_event_cause(hdev, &clearval);
2574
2575         /* vector 0 interrupt is shared with reset and mailbox source events.*/
2576         switch (event_cause) {
2577         case HCLGE_VECTOR0_EVENT_RST:
2578                 hclge_reset_task_schedule(hdev);
2579                 break;
2580         case HCLGE_VECTOR0_EVENT_MBX:
2581                 /* If we are here then,
2582                  * 1. Either we are not handling any mbx task and we are not
2583                  *    scheduled as well
2584                  *                        OR
2585                  * 2. We could be handling a mbx task but nothing more is
2586                  *    scheduled.
2587                  * In both cases, we should schedule mbx task as there are more
2588                  * mbx messages reported by this interrupt.
2589                  */
2590                 hclge_mbx_task_schedule(hdev);
2591                 break;
2592         default:
2593                 dev_warn(&hdev->pdev->dev,
2594                          "received unknown or unhandled event of vector0\n");
2595                 break;
2596         }
2597
2598         /* clear the source of interrupt if it is not cause by reset */
2599         if (event_cause != HCLGE_VECTOR0_EVENT_RST) {
2600                 hclge_clear_event_cause(hdev, event_cause, clearval);
2601                 hclge_enable_vector(&hdev->misc_vector, true);
2602         }
2603
2604         return IRQ_HANDLED;
2605 }
2606
2607 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2608 {
2609         if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2610                 dev_warn(&hdev->pdev->dev,
2611                          "vector(vector_id %d) has been freed.\n", vector_id);
2612                 return;
2613         }
2614
2615         hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2616         hdev->num_msi_left += 1;
2617         hdev->num_msi_used -= 1;
2618 }
2619
2620 static void hclge_get_misc_vector(struct hclge_dev *hdev)
2621 {
2622         struct hclge_misc_vector *vector = &hdev->misc_vector;
2623
2624         vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2625
2626         vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2627         hdev->vector_status[0] = 0;
2628
2629         hdev->num_msi_left -= 1;
2630         hdev->num_msi_used += 1;
2631 }
2632
2633 static int hclge_misc_irq_init(struct hclge_dev *hdev)
2634 {
2635         int ret;
2636
2637         hclge_get_misc_vector(hdev);
2638
2639         /* this would be explicitly freed in the end */
2640         ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2641                           0, "hclge_misc", hdev);
2642         if (ret) {
2643                 hclge_free_vector(hdev, 0);
2644                 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2645                         hdev->misc_vector.vector_irq);
2646         }
2647
2648         return ret;
2649 }
2650
2651 static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2652 {
2653         free_irq(hdev->misc_vector.vector_irq, hdev);
2654         hclge_free_vector(hdev, 0);
2655 }
2656
2657 static int hclge_notify_client(struct hclge_dev *hdev,
2658                                enum hnae3_reset_notify_type type)
2659 {
2660         struct hnae3_client *client = hdev->nic_client;
2661         u16 i;
2662
2663         if (!client->ops->reset_notify)
2664                 return -EOPNOTSUPP;
2665
2666         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2667                 struct hnae3_handle *handle = &hdev->vport[i].nic;
2668                 int ret;
2669
2670                 ret = client->ops->reset_notify(handle, type);
2671                 if (ret)
2672                         return ret;
2673         }
2674
2675         return 0;
2676 }
2677
2678 static int hclge_reset_wait(struct hclge_dev *hdev)
2679 {
2680 #define HCLGE_RESET_WATI_MS     100
2681 #define HCLGE_RESET_WAIT_CNT    5
2682         u32 val, reg, reg_bit;
2683         u32 cnt = 0;
2684
2685         switch (hdev->reset_type) {
2686         case HNAE3_GLOBAL_RESET:
2687                 reg = HCLGE_GLOBAL_RESET_REG;
2688                 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2689                 break;
2690         case HNAE3_CORE_RESET:
2691                 reg = HCLGE_GLOBAL_RESET_REG;
2692                 reg_bit = HCLGE_CORE_RESET_BIT;
2693                 break;
2694         case HNAE3_FUNC_RESET:
2695                 reg = HCLGE_FUN_RST_ING;
2696                 reg_bit = HCLGE_FUN_RST_ING_B;
2697                 break;
2698         default:
2699                 dev_err(&hdev->pdev->dev,
2700                         "Wait for unsupported reset type: %d\n",
2701                         hdev->reset_type);
2702                 return -EINVAL;
2703         }
2704
2705         val = hclge_read_dev(&hdev->hw, reg);
2706         while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2707                 msleep(HCLGE_RESET_WATI_MS);
2708                 val = hclge_read_dev(&hdev->hw, reg);
2709                 cnt++;
2710         }
2711
2712         if (cnt >= HCLGE_RESET_WAIT_CNT) {
2713                 dev_warn(&hdev->pdev->dev,
2714                          "Wait for reset timeout: %d\n", hdev->reset_type);
2715                 return -EBUSY;
2716         }
2717
2718         return 0;
2719 }
2720
2721 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2722 {
2723         struct hclge_desc desc;
2724         struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2725         int ret;
2726
2727         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2728         hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2729         req->fun_reset_vfid = func_id;
2730
2731         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2732         if (ret)
2733                 dev_err(&hdev->pdev->dev,
2734                         "send function reset cmd fail, status =%d\n", ret);
2735
2736         return ret;
2737 }
2738
2739 static void hclge_do_reset(struct hclge_dev *hdev)
2740 {
2741         struct pci_dev *pdev = hdev->pdev;
2742         u32 val;
2743
2744         switch (hdev->reset_type) {
2745         case HNAE3_GLOBAL_RESET:
2746                 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2747                 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2748                 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2749                 dev_info(&pdev->dev, "Global Reset requested\n");
2750                 break;
2751         case HNAE3_CORE_RESET:
2752                 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2753                 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2754                 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2755                 dev_info(&pdev->dev, "Core Reset requested\n");
2756                 break;
2757         case HNAE3_FUNC_RESET:
2758                 dev_info(&pdev->dev, "PF Reset requested\n");
2759                 hclge_func_reset_cmd(hdev, 0);
2760                 /* schedule again to check later */
2761                 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2762                 hclge_reset_task_schedule(hdev);
2763                 break;
2764         default:
2765                 dev_warn(&pdev->dev,
2766                          "Unsupported reset type: %d\n", hdev->reset_type);
2767                 break;
2768         }
2769 }
2770
2771 static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2772                                                    unsigned long *addr)
2773 {
2774         enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2775
2776         /* return the highest priority reset level amongst all */
2777         if (test_bit(HNAE3_GLOBAL_RESET, addr))
2778                 rst_level = HNAE3_GLOBAL_RESET;
2779         else if (test_bit(HNAE3_CORE_RESET, addr))
2780                 rst_level = HNAE3_CORE_RESET;
2781         else if (test_bit(HNAE3_IMP_RESET, addr))
2782                 rst_level = HNAE3_IMP_RESET;
2783         else if (test_bit(HNAE3_FUNC_RESET, addr))
2784                 rst_level = HNAE3_FUNC_RESET;
2785
2786         /* now, clear all other resets */
2787         clear_bit(HNAE3_GLOBAL_RESET, addr);
2788         clear_bit(HNAE3_CORE_RESET, addr);
2789         clear_bit(HNAE3_IMP_RESET, addr);
2790         clear_bit(HNAE3_FUNC_RESET, addr);
2791
2792         return rst_level;
2793 }
2794
2795 static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2796 {
2797         u32 clearval = 0;
2798
2799         switch (hdev->reset_type) {
2800         case HNAE3_IMP_RESET:
2801                 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2802                 break;
2803         case HNAE3_GLOBAL_RESET:
2804                 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2805                 break;
2806         case HNAE3_CORE_RESET:
2807                 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2808                 break;
2809         default:
2810                 break;
2811         }
2812
2813         if (!clearval)
2814                 return;
2815
2816         hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2817         hclge_enable_vector(&hdev->misc_vector, true);
2818 }
2819
2820 static void hclge_reset(struct hclge_dev *hdev)
2821 {
2822         struct hnae3_handle *handle;
2823
2824         /* perform reset of the stack & ae device for a client */
2825         handle = &hdev->vport[0].nic;
2826         rtnl_lock();
2827         hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2828
2829         if (!hclge_reset_wait(hdev)) {
2830                 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2831                 hclge_reset_ae_dev(hdev->ae_dev);
2832                 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2833
2834                 hclge_clear_reset_cause(hdev);
2835         } else {
2836                 /* schedule again to check pending resets later */
2837                 set_bit(hdev->reset_type, &hdev->reset_pending);
2838                 hclge_reset_task_schedule(hdev);
2839         }
2840
2841         hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2842         handle->last_reset_time = jiffies;
2843         rtnl_unlock();
2844 }
2845
2846 static void hclge_reset_event(struct hnae3_handle *handle)
2847 {
2848         struct hclge_vport *vport = hclge_get_vport(handle);
2849         struct hclge_dev *hdev = vport->back;
2850
2851         /* check if this is a new reset request and we are not here just because
2852          * last reset attempt did not succeed and watchdog hit us again. We will
2853          * know this if last reset request did not occur very recently (watchdog
2854          * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2855          * In case of new request we reset the "reset level" to PF reset.
2856          * And if it is a repeat reset request of the most recent one then we
2857          * want to make sure we throttle the reset request. Therefore, we will
2858          * not allow it again before 3*HZ times.
2859          */
2860         if (time_before(jiffies, (handle->last_reset_time + 3 * HZ)))
2861                 return;
2862         else if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ)))
2863                 handle->reset_level = HNAE3_FUNC_RESET;
2864
2865         dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
2866                  handle->reset_level);
2867
2868         /* request reset & schedule reset task */
2869         set_bit(handle->reset_level, &hdev->reset_request);
2870         hclge_reset_task_schedule(hdev);
2871
2872         if (handle->reset_level < HNAE3_GLOBAL_RESET)
2873                 handle->reset_level++;
2874 }
2875
2876 static void hclge_reset_subtask(struct hclge_dev *hdev)
2877 {
2878         /* check if there is any ongoing reset in the hardware. This status can
2879          * be checked from reset_pending. If there is then, we need to wait for
2880          * hardware to complete reset.
2881          *    a. If we are able to figure out in reasonable time that hardware
2882          *       has fully resetted then, we can proceed with driver, client
2883          *       reset.
2884          *    b. else, we can come back later to check this status so re-sched
2885          *       now.
2886          */
2887         hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2888         if (hdev->reset_type != HNAE3_NONE_RESET)
2889                 hclge_reset(hdev);
2890
2891         /* check if we got any *new* reset requests to be honored */
2892         hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2893         if (hdev->reset_type != HNAE3_NONE_RESET)
2894                 hclge_do_reset(hdev);
2895
2896         hdev->reset_type = HNAE3_NONE_RESET;
2897 }
2898
2899 static void hclge_reset_service_task(struct work_struct *work)
2900 {
2901         struct hclge_dev *hdev =
2902                 container_of(work, struct hclge_dev, rst_service_task);
2903
2904         if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2905                 return;
2906
2907         clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2908
2909         hclge_reset_subtask(hdev);
2910
2911         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
2912 }
2913
2914 static void hclge_mailbox_service_task(struct work_struct *work)
2915 {
2916         struct hclge_dev *hdev =
2917                 container_of(work, struct hclge_dev, mbx_service_task);
2918
2919         if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2920                 return;
2921
2922         clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2923
2924         hclge_mbx_handler(hdev);
2925
2926         clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2927 }
2928
2929 static void hclge_service_task(struct work_struct *work)
2930 {
2931         struct hclge_dev *hdev =
2932                 container_of(work, struct hclge_dev, service_task);
2933
2934         if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2935                 hclge_update_stats_for_all(hdev);
2936                 hdev->hw_stats.stats_timer = 0;
2937         }
2938
2939         hclge_update_speed_duplex(hdev);
2940         hclge_update_link_status(hdev);
2941         hclge_service_complete(hdev);
2942 }
2943
2944 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2945 {
2946         /* VF handle has no client */
2947         if (!handle->client)
2948                 return container_of(handle, struct hclge_vport, nic);
2949         else if (handle->client->type == HNAE3_CLIENT_ROCE)
2950                 return container_of(handle, struct hclge_vport, roce);
2951         else
2952                 return container_of(handle, struct hclge_vport, nic);
2953 }
2954
2955 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2956                             struct hnae3_vector_info *vector_info)
2957 {
2958         struct hclge_vport *vport = hclge_get_vport(handle);
2959         struct hnae3_vector_info *vector = vector_info;
2960         struct hclge_dev *hdev = vport->back;
2961         int alloc = 0;
2962         int i, j;
2963
2964         vector_num = min(hdev->num_msi_left, vector_num);
2965
2966         for (j = 0; j < vector_num; j++) {
2967                 for (i = 1; i < hdev->num_msi; i++) {
2968                         if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2969                                 vector->vector = pci_irq_vector(hdev->pdev, i);
2970                                 vector->io_addr = hdev->hw.io_base +
2971                                         HCLGE_VECTOR_REG_BASE +
2972                                         (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2973                                         vport->vport_id *
2974                                         HCLGE_VECTOR_VF_OFFSET;
2975                                 hdev->vector_status[i] = vport->vport_id;
2976                                 hdev->vector_irq[i] = vector->vector;
2977
2978                                 vector++;
2979                                 alloc++;
2980
2981                                 break;
2982                         }
2983                 }
2984         }
2985         hdev->num_msi_left -= alloc;
2986         hdev->num_msi_used += alloc;
2987
2988         return alloc;
2989 }
2990
2991 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2992 {
2993         int i;
2994
2995         for (i = 0; i < hdev->num_msi; i++)
2996                 if (vector == hdev->vector_irq[i])
2997                         return i;
2998
2999         return -EINVAL;
3000 }
3001
3002 static int hclge_put_vector(struct hnae3_handle *handle, int vector)
3003 {
3004         struct hclge_vport *vport = hclge_get_vport(handle);
3005         struct hclge_dev *hdev = vport->back;
3006         int vector_id;
3007
3008         vector_id = hclge_get_vector_index(hdev, vector);
3009         if (vector_id < 0) {
3010                 dev_err(&hdev->pdev->dev,
3011                         "Get vector index fail. vector_id =%d\n", vector_id);
3012                 return vector_id;
3013         }
3014
3015         hclge_free_vector(hdev, vector_id);
3016
3017         return 0;
3018 }
3019
3020 static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
3021 {
3022         return HCLGE_RSS_KEY_SIZE;
3023 }
3024
3025 static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
3026 {
3027         return HCLGE_RSS_IND_TBL_SIZE;
3028 }
3029
3030 static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
3031                                   const u8 hfunc, const u8 *key)
3032 {
3033         struct hclge_rss_config_cmd *req;
3034         struct hclge_desc desc;
3035         int key_offset;
3036         int key_size;
3037         int ret;
3038
3039         req = (struct hclge_rss_config_cmd *)desc.data;
3040
3041         for (key_offset = 0; key_offset < 3; key_offset++) {
3042                 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
3043                                            false);
3044
3045                 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
3046                 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
3047
3048                 if (key_offset == 2)
3049                         key_size =
3050                         HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
3051                 else
3052                         key_size = HCLGE_RSS_HASH_KEY_NUM;
3053
3054                 memcpy(req->hash_key,
3055                        key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
3056
3057                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3058                 if (ret) {
3059                         dev_err(&hdev->pdev->dev,
3060                                 "Configure RSS config fail, status = %d\n",
3061                                 ret);
3062                         return ret;
3063                 }
3064         }
3065         return 0;
3066 }
3067
3068 static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
3069 {
3070         struct hclge_rss_indirection_table_cmd *req;
3071         struct hclge_desc desc;
3072         int i, j;
3073         int ret;
3074
3075         req = (struct hclge_rss_indirection_table_cmd *)desc.data;
3076
3077         for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
3078                 hclge_cmd_setup_basic_desc
3079                         (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
3080
3081                 req->start_table_index =
3082                         cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
3083                 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
3084
3085                 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
3086                         req->rss_result[j] =
3087                                 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
3088
3089                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3090                 if (ret) {
3091                         dev_err(&hdev->pdev->dev,
3092                                 "Configure rss indir table fail,status = %d\n",
3093                                 ret);
3094                         return ret;
3095                 }
3096         }
3097         return 0;
3098 }
3099
3100 static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3101                                  u16 *tc_size, u16 *tc_offset)
3102 {
3103         struct hclge_rss_tc_mode_cmd *req;
3104         struct hclge_desc desc;
3105         int ret;
3106         int i;
3107
3108         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
3109         req = (struct hclge_rss_tc_mode_cmd *)desc.data;
3110
3111         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3112                 u16 mode = 0;
3113
3114                 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3115                 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
3116                                 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
3117                 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
3118                                 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
3119
3120                 req->rss_tc_mode[i] = cpu_to_le16(mode);
3121         }
3122
3123         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3124         if (ret) {
3125                 dev_err(&hdev->pdev->dev,
3126                         "Configure rss tc mode fail, status = %d\n", ret);
3127                 return ret;
3128         }
3129
3130         return 0;
3131 }
3132
3133 static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3134 {
3135         struct hclge_rss_input_tuple_cmd *req;
3136         struct hclge_desc desc;
3137         int ret;
3138
3139         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3140
3141         req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3142
3143         /* Get the tuple cfg from pf */
3144         req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
3145         req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
3146         req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
3147         req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
3148         req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
3149         req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
3150         req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
3151         req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
3152         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3153         if (ret) {
3154                 dev_err(&hdev->pdev->dev,
3155                         "Configure rss input fail, status = %d\n", ret);
3156                 return ret;
3157         }
3158
3159         return 0;
3160 }
3161
3162 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3163                          u8 *key, u8 *hfunc)
3164 {
3165         struct hclge_vport *vport = hclge_get_vport(handle);
3166         int i;
3167
3168         /* Get hash algorithm */
3169         if (hfunc)
3170                 *hfunc = vport->rss_algo;
3171
3172         /* Get the RSS Key required by the user */
3173         if (key)
3174                 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3175
3176         /* Get indirect table */
3177         if (indir)
3178                 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3179                         indir[i] =  vport->rss_indirection_tbl[i];
3180
3181         return 0;
3182 }
3183
3184 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3185                          const  u8 *key, const  u8 hfunc)
3186 {
3187         struct hclge_vport *vport = hclge_get_vport(handle);
3188         struct hclge_dev *hdev = vport->back;
3189         u8 hash_algo;
3190         int ret, i;
3191
3192         /* Set the RSS Hash Key if specififed by the user */
3193         if (key) {
3194
3195                 if (hfunc == ETH_RSS_HASH_TOP ||
3196                     hfunc == ETH_RSS_HASH_NO_CHANGE)
3197                         hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3198                 else
3199                         return -EINVAL;
3200                 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3201                 if (ret)
3202                         return ret;
3203
3204                 /* Update the shadow RSS key with user specified qids */
3205                 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3206                 vport->rss_algo = hash_algo;
3207         }
3208
3209         /* Update the shadow RSS table with user specified qids */
3210         for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3211                 vport->rss_indirection_tbl[i] = indir[i];
3212
3213         /* Update the hardware */
3214         return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
3215 }
3216
3217 static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3218 {
3219         u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3220
3221         if (nfc->data & RXH_L4_B_2_3)
3222                 hash_sets |= HCLGE_D_PORT_BIT;
3223         else
3224                 hash_sets &= ~HCLGE_D_PORT_BIT;
3225
3226         if (nfc->data & RXH_IP_SRC)
3227                 hash_sets |= HCLGE_S_IP_BIT;
3228         else
3229                 hash_sets &= ~HCLGE_S_IP_BIT;
3230
3231         if (nfc->data & RXH_IP_DST)
3232                 hash_sets |= HCLGE_D_IP_BIT;
3233         else
3234                 hash_sets &= ~HCLGE_D_IP_BIT;
3235
3236         if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3237                 hash_sets |= HCLGE_V_TAG_BIT;
3238
3239         return hash_sets;
3240 }
3241
3242 static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3243                                struct ethtool_rxnfc *nfc)
3244 {
3245         struct hclge_vport *vport = hclge_get_vport(handle);
3246         struct hclge_dev *hdev = vport->back;
3247         struct hclge_rss_input_tuple_cmd *req;
3248         struct hclge_desc desc;
3249         u8 tuple_sets;
3250         int ret;
3251
3252         if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3253                           RXH_L4_B_0_1 | RXH_L4_B_2_3))
3254                 return -EINVAL;
3255
3256         req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3257         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3258
3259         req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
3260         req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
3261         req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
3262         req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
3263         req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
3264         req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
3265         req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
3266         req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
3267
3268         tuple_sets = hclge_get_rss_hash_bits(nfc);
3269         switch (nfc->flow_type) {
3270         case TCP_V4_FLOW:
3271                 req->ipv4_tcp_en = tuple_sets;
3272                 break;
3273         case TCP_V6_FLOW:
3274                 req->ipv6_tcp_en = tuple_sets;
3275                 break;
3276         case UDP_V4_FLOW:
3277                 req->ipv4_udp_en = tuple_sets;
3278                 break;
3279         case UDP_V6_FLOW:
3280                 req->ipv6_udp_en = tuple_sets;
3281                 break;
3282         case SCTP_V4_FLOW:
3283                 req->ipv4_sctp_en = tuple_sets;
3284                 break;
3285         case SCTP_V6_FLOW:
3286                 if ((nfc->data & RXH_L4_B_0_1) ||
3287                     (nfc->data & RXH_L4_B_2_3))
3288                         return -EINVAL;
3289
3290                 req->ipv6_sctp_en = tuple_sets;
3291                 break;
3292         case IPV4_FLOW:
3293                 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3294                 break;
3295         case IPV6_FLOW:
3296                 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3297                 break;
3298         default:
3299                 return -EINVAL;
3300         }
3301
3302         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3303         if (ret) {
3304                 dev_err(&hdev->pdev->dev,
3305                         "Set rss tuple fail, status = %d\n", ret);
3306                 return ret;
3307         }
3308
3309         vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
3310         vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
3311         vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
3312         vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
3313         vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
3314         vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3315         vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3316         vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
3317         return 0;
3318 }
3319
3320 static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3321                                struct ethtool_rxnfc *nfc)
3322 {
3323         struct hclge_vport *vport = hclge_get_vport(handle);
3324         u8 tuple_sets;
3325
3326         nfc->data = 0;
3327
3328         switch (nfc->flow_type) {
3329         case TCP_V4_FLOW:
3330                 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
3331                 break;
3332         case UDP_V4_FLOW:
3333                 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
3334                 break;
3335         case TCP_V6_FLOW:
3336                 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
3337                 break;
3338         case UDP_V6_FLOW:
3339                 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
3340                 break;
3341         case SCTP_V4_FLOW:
3342                 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
3343                 break;
3344         case SCTP_V6_FLOW:
3345                 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
3346                 break;
3347         case IPV4_FLOW:
3348         case IPV6_FLOW:
3349                 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3350                 break;
3351         default:
3352                 return -EINVAL;
3353         }
3354
3355         if (!tuple_sets)
3356                 return 0;
3357
3358         if (tuple_sets & HCLGE_D_PORT_BIT)
3359                 nfc->data |= RXH_L4_B_2_3;
3360         if (tuple_sets & HCLGE_S_PORT_BIT)
3361                 nfc->data |= RXH_L4_B_0_1;
3362         if (tuple_sets & HCLGE_D_IP_BIT)
3363                 nfc->data |= RXH_IP_DST;
3364         if (tuple_sets & HCLGE_S_IP_BIT)
3365                 nfc->data |= RXH_IP_SRC;
3366
3367         return 0;
3368 }
3369
3370 static int hclge_get_tc_size(struct hnae3_handle *handle)
3371 {
3372         struct hclge_vport *vport = hclge_get_vport(handle);
3373         struct hclge_dev *hdev = vport->back;
3374
3375         return hdev->rss_size_max;
3376 }
3377
3378 int hclge_rss_init_hw(struct hclge_dev *hdev)
3379 {
3380         struct hclge_vport *vport = hdev->vport;
3381         u8 *rss_indir = vport[0].rss_indirection_tbl;
3382         u16 rss_size = vport[0].alloc_rss_size;
3383         u8 *key = vport[0].rss_hash_key;
3384         u8 hfunc = vport[0].rss_algo;
3385         u16 tc_offset[HCLGE_MAX_TC_NUM];
3386         u16 tc_valid[HCLGE_MAX_TC_NUM];
3387         u16 tc_size[HCLGE_MAX_TC_NUM];
3388         u16 roundup_size;
3389         int i, ret;
3390
3391         ret = hclge_set_rss_indir_table(hdev, rss_indir);
3392         if (ret)
3393                 return ret;
3394
3395         ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3396         if (ret)
3397                 return ret;
3398
3399         ret = hclge_set_rss_input_tuple(hdev);
3400         if (ret)
3401                 return ret;
3402
3403         /* Each TC have the same queue size, and tc_size set to hardware is
3404          * the log2 of roundup power of two of rss_size, the acutal queue
3405          * size is limited by indirection table.
3406          */
3407         if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3408                 dev_err(&hdev->pdev->dev,
3409                         "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3410                         rss_size);
3411                 return -EINVAL;
3412         }
3413
3414         roundup_size = roundup_pow_of_two(rss_size);
3415         roundup_size = ilog2(roundup_size);
3416
3417         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3418                 tc_valid[i] = 0;
3419
3420                 if (!(hdev->hw_tc_map & BIT(i)))
3421                         continue;
3422
3423                 tc_valid[i] = 1;
3424                 tc_size[i] = roundup_size;
3425                 tc_offset[i] = rss_size * i;
3426         }
3427
3428         return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3429 }
3430
3431 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3432 {
3433         struct hclge_vport *vport = hdev->vport;
3434         int i, j;
3435
3436         for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3437                 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3438                         vport[j].rss_indirection_tbl[i] =
3439                                 i % vport[j].alloc_rss_size;
3440         }
3441 }
3442
3443 static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3444 {
3445         struct hclge_vport *vport = hdev->vport;
3446         int i;
3447
3448         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3449                 vport[i].rss_tuple_sets.ipv4_tcp_en =
3450                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3451                 vport[i].rss_tuple_sets.ipv4_udp_en =
3452                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3453                 vport[i].rss_tuple_sets.ipv4_sctp_en =
3454                         HCLGE_RSS_INPUT_TUPLE_SCTP;
3455                 vport[i].rss_tuple_sets.ipv4_fragment_en =
3456                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3457                 vport[i].rss_tuple_sets.ipv6_tcp_en =
3458                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3459                 vport[i].rss_tuple_sets.ipv6_udp_en =
3460                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3461                 vport[i].rss_tuple_sets.ipv6_sctp_en =
3462                         HCLGE_RSS_INPUT_TUPLE_SCTP;
3463                 vport[i].rss_tuple_sets.ipv6_fragment_en =
3464                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3465
3466                 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3467
3468                 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
3469         }
3470
3471         hclge_rss_indir_init_cfg(hdev);
3472 }
3473
3474 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3475                                 int vector_id, bool en,
3476                                 struct hnae3_ring_chain_node *ring_chain)
3477 {
3478         struct hclge_dev *hdev = vport->back;
3479         struct hnae3_ring_chain_node *node;
3480         struct hclge_desc desc;
3481         struct hclge_ctrl_vector_chain_cmd *req
3482                 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3483         enum hclge_cmd_status status;
3484         enum hclge_opcode_type op;
3485         u16 tqp_type_and_id;
3486         int i;
3487
3488         op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3489         hclge_cmd_setup_basic_desc(&desc, op, false);
3490         req->int_vector_id = vector_id;
3491
3492         i = 0;
3493         for (node = ring_chain; node; node = node->next) {
3494                 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
3495                 hnae3_set_field(tqp_type_and_id,  HCLGE_INT_TYPE_M,
3496                                 HCLGE_INT_TYPE_S,
3497                                 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3498                 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3499                                 HCLGE_TQP_ID_S, node->tqp_index);
3500                 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3501                                 HCLGE_INT_GL_IDX_S,
3502                                 hnae3_get_field(node->int_gl_idx,
3503                                                 HNAE3_RING_GL_IDX_M,
3504                                                 HNAE3_RING_GL_IDX_S));
3505                 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
3506                 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3507                         req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3508                         req->vfid = vport->vport_id;
3509
3510                         status = hclge_cmd_send(&hdev->hw, &desc, 1);
3511                         if (status) {
3512                                 dev_err(&hdev->pdev->dev,
3513                                         "Map TQP fail, status is %d.\n",
3514                                         status);
3515                                 return -EIO;
3516                         }
3517                         i = 0;
3518
3519                         hclge_cmd_setup_basic_desc(&desc,
3520                                                    op,
3521                                                    false);
3522                         req->int_vector_id = vector_id;
3523                 }
3524         }
3525
3526         if (i > 0) {
3527                 req->int_cause_num = i;
3528                 req->vfid = vport->vport_id;
3529                 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3530                 if (status) {
3531                         dev_err(&hdev->pdev->dev,
3532                                 "Map TQP fail, status is %d.\n", status);
3533                         return -EIO;
3534                 }
3535         }
3536
3537         return 0;
3538 }
3539
3540 static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3541                                     int vector,
3542                                     struct hnae3_ring_chain_node *ring_chain)
3543 {
3544         struct hclge_vport *vport = hclge_get_vport(handle);
3545         struct hclge_dev *hdev = vport->back;
3546         int vector_id;
3547
3548         vector_id = hclge_get_vector_index(hdev, vector);
3549         if (vector_id < 0) {
3550                 dev_err(&hdev->pdev->dev,
3551                         "Get vector index fail. vector_id =%d\n", vector_id);
3552                 return vector_id;
3553         }
3554
3555         return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
3556 }
3557
3558 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3559                                        int vector,
3560                                        struct hnae3_ring_chain_node *ring_chain)
3561 {
3562         struct hclge_vport *vport = hclge_get_vport(handle);
3563         struct hclge_dev *hdev = vport->back;
3564         int vector_id, ret;
3565
3566         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3567                 return 0;
3568
3569         vector_id = hclge_get_vector_index(hdev, vector);
3570         if (vector_id < 0) {
3571                 dev_err(&handle->pdev->dev,
3572                         "Get vector index fail. ret =%d\n", vector_id);
3573                 return vector_id;
3574         }
3575
3576         ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
3577         if (ret)
3578                 dev_err(&handle->pdev->dev,
3579                         "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3580                         vector_id,
3581                         ret);
3582
3583         return ret;
3584 }
3585
3586 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3587                                struct hclge_promisc_param *param)
3588 {
3589         struct hclge_promisc_cfg_cmd *req;
3590         struct hclge_desc desc;
3591         int ret;
3592
3593         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3594
3595         req = (struct hclge_promisc_cfg_cmd *)desc.data;
3596         req->vf_id = param->vf_id;
3597
3598         /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3599          * pdev revision(0x20), new revision support them. The
3600          * value of this two fields will not return error when driver
3601          * send command to fireware in revision(0x20).
3602          */
3603         req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3604                 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
3605
3606         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3607         if (ret) {
3608                 dev_err(&hdev->pdev->dev,
3609                         "Set promisc mode fail, status is %d.\n", ret);
3610                 return ret;
3611         }
3612         return 0;
3613 }
3614
3615 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3616                               bool en_mc, bool en_bc, int vport_id)
3617 {
3618         if (!param)
3619                 return;
3620
3621         memset(param, 0, sizeof(struct hclge_promisc_param));
3622         if (en_uc)
3623                 param->enable = HCLGE_PROMISC_EN_UC;
3624         if (en_mc)
3625                 param->enable |= HCLGE_PROMISC_EN_MC;
3626         if (en_bc)
3627                 param->enable |= HCLGE_PROMISC_EN_BC;
3628         param->vf_id = vport_id;
3629 }
3630
3631 static void hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3632                                    bool en_mc_pmc)
3633 {
3634         struct hclge_vport *vport = hclge_get_vport(handle);
3635         struct hclge_dev *hdev = vport->back;
3636         struct hclge_promisc_param param;
3637
3638         hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3639                                  vport->vport_id);
3640         hclge_cmd_set_promisc_mode(hdev, &param);
3641 }
3642
3643 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3644 {
3645         struct hclge_desc desc;
3646         struct hclge_config_mac_mode_cmd *req =
3647                 (struct hclge_config_mac_mode_cmd *)desc.data;
3648         u32 loop_en = 0;
3649         int ret;
3650
3651         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
3652         hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3653         hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3654         hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3655         hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3656         hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3657         hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3658         hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3659         hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3660         hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3661         hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3662         hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3663         hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3664         hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3665         hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
3666         req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3667
3668         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3669         if (ret)
3670                 dev_err(&hdev->pdev->dev,
3671                         "mac enable fail, ret =%d.\n", ret);
3672 }
3673
3674 static int hclge_set_mac_loopback(struct hclge_dev *hdev, bool en)
3675 {
3676         struct hclge_config_mac_mode_cmd *req;
3677         struct hclge_desc desc;
3678         u32 loop_en;
3679         int ret;
3680
3681         req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3682         /* 1 Read out the MAC mode config at first */
3683         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
3684         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3685         if (ret) {
3686                 dev_err(&hdev->pdev->dev,
3687                         "mac loopback get fail, ret =%d.\n", ret);
3688                 return ret;
3689         }
3690
3691         /* 2 Then setup the loopback flag */
3692         loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
3693         hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
3694
3695         req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3696
3697         /* 3 Config mac work mode with loopback flag
3698          * and its original configure parameters
3699          */
3700         hclge_cmd_reuse_desc(&desc, false);
3701         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3702         if (ret)
3703                 dev_err(&hdev->pdev->dev,
3704                         "mac loopback set fail, ret =%d.\n", ret);
3705         return ret;
3706 }
3707
3708 static int hclge_set_loopback(struct hnae3_handle *handle,
3709                               enum hnae3_loop loop_mode, bool en)
3710 {
3711         struct hclge_vport *vport = hclge_get_vport(handle);
3712         struct hclge_dev *hdev = vport->back;
3713         int ret;
3714
3715         switch (loop_mode) {
3716         case HNAE3_MAC_INTER_LOOP_MAC:
3717                 ret = hclge_set_mac_loopback(hdev, en);
3718                 break;
3719         default:
3720                 ret = -ENOTSUPP;
3721                 dev_err(&hdev->pdev->dev,
3722                         "loop_mode %d is not supported\n", loop_mode);
3723                 break;
3724         }
3725
3726         return ret;
3727 }
3728
3729 static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3730                             int stream_id, bool enable)
3731 {
3732         struct hclge_desc desc;
3733         struct hclge_cfg_com_tqp_queue_cmd *req =
3734                 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
3735         int ret;
3736
3737         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3738         req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3739         req->stream_id = cpu_to_le16(stream_id);
3740         req->enable |= enable << HCLGE_TQP_ENABLE_B;
3741
3742         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3743         if (ret)
3744                 dev_err(&hdev->pdev->dev,
3745                         "Tqp enable fail, status =%d.\n", ret);
3746         return ret;
3747 }
3748
3749 static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3750 {
3751         struct hclge_vport *vport = hclge_get_vport(handle);
3752         struct hnae3_queue *queue;
3753         struct hclge_tqp *tqp;
3754         int i;
3755
3756         for (i = 0; i < vport->alloc_tqps; i++) {
3757                 queue = handle->kinfo.tqp[i];
3758                 tqp = container_of(queue, struct hclge_tqp, q);
3759                 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3760         }
3761 }
3762
3763 static int hclge_ae_start(struct hnae3_handle *handle)
3764 {
3765         struct hclge_vport *vport = hclge_get_vport(handle);
3766         struct hclge_dev *hdev = vport->back;
3767         int i, ret;
3768
3769         for (i = 0; i < vport->alloc_tqps; i++)
3770                 hclge_tqp_enable(hdev, i, 0, true);
3771
3772         /* mac enable */
3773         hclge_cfg_mac_mode(hdev, true);
3774         clear_bit(HCLGE_STATE_DOWN, &hdev->state);
3775         mod_timer(&hdev->service_timer, jiffies + HZ);
3776         hdev->hw.mac.link = 0;
3777
3778         /* reset tqp stats */
3779         hclge_reset_tqp_stats(handle);
3780
3781         ret = hclge_mac_start_phy(hdev);
3782         if (ret)
3783                 return ret;
3784
3785         return 0;
3786 }
3787
3788 static void hclge_ae_stop(struct hnae3_handle *handle)
3789 {
3790         struct hclge_vport *vport = hclge_get_vport(handle);
3791         struct hclge_dev *hdev = vport->back;
3792         int i;
3793
3794         del_timer_sync(&hdev->service_timer);
3795         cancel_work_sync(&hdev->service_task);
3796         clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
3797
3798         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
3799                 hclge_mac_stop_phy(hdev);
3800                 return;
3801         }
3802
3803         for (i = 0; i < vport->alloc_tqps; i++)
3804                 hclge_tqp_enable(hdev, i, 0, false);
3805
3806         /* Mac disable */
3807         hclge_cfg_mac_mode(hdev, false);
3808
3809         hclge_mac_stop_phy(hdev);
3810
3811         /* reset tqp stats */
3812         hclge_reset_tqp_stats(handle);
3813         del_timer_sync(&hdev->service_timer);
3814         cancel_work_sync(&hdev->service_task);
3815         hclge_update_link_status(hdev);
3816 }
3817
3818 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3819                                          u16 cmdq_resp, u8  resp_code,
3820                                          enum hclge_mac_vlan_tbl_opcode op)
3821 {
3822         struct hclge_dev *hdev = vport->back;
3823         int return_status = -EIO;
3824
3825         if (cmdq_resp) {
3826                 dev_err(&hdev->pdev->dev,
3827                         "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3828                         cmdq_resp);
3829                 return -EIO;
3830         }
3831
3832         if (op == HCLGE_MAC_VLAN_ADD) {
3833                 if ((!resp_code) || (resp_code == 1)) {
3834                         return_status = 0;
3835                 } else if (resp_code == 2) {
3836                         return_status = -ENOSPC;
3837                         dev_err(&hdev->pdev->dev,
3838                                 "add mac addr failed for uc_overflow.\n");
3839                 } else if (resp_code == 3) {
3840                         return_status = -ENOSPC;
3841                         dev_err(&hdev->pdev->dev,
3842                                 "add mac addr failed for mc_overflow.\n");
3843                 } else {
3844                         dev_err(&hdev->pdev->dev,
3845                                 "add mac addr failed for undefined, code=%d.\n",
3846                                 resp_code);
3847                 }
3848         } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3849                 if (!resp_code) {
3850                         return_status = 0;
3851                 } else if (resp_code == 1) {
3852                         return_status = -ENOENT;
3853                         dev_dbg(&hdev->pdev->dev,
3854                                 "remove mac addr failed for miss.\n");
3855                 } else {
3856                         dev_err(&hdev->pdev->dev,
3857                                 "remove mac addr failed for undefined, code=%d.\n",
3858                                 resp_code);
3859                 }
3860         } else if (op == HCLGE_MAC_VLAN_LKUP) {
3861                 if (!resp_code) {
3862                         return_status = 0;
3863                 } else if (resp_code == 1) {
3864                         return_status = -ENOENT;
3865                         dev_dbg(&hdev->pdev->dev,
3866                                 "lookup mac addr failed for miss.\n");
3867                 } else {
3868                         dev_err(&hdev->pdev->dev,
3869                                 "lookup mac addr failed for undefined, code=%d.\n",
3870                                 resp_code);
3871                 }
3872         } else {
3873                 return_status = -EINVAL;
3874                 dev_err(&hdev->pdev->dev,
3875                         "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3876                         op);
3877         }
3878
3879         return return_status;
3880 }
3881
3882 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3883 {
3884         int word_num;
3885         int bit_num;
3886
3887         if (vfid > 255 || vfid < 0)
3888                 return -EIO;
3889
3890         if (vfid >= 0 && vfid <= 191) {
3891                 word_num = vfid / 32;
3892                 bit_num  = vfid % 32;
3893                 if (clr)
3894                         desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
3895                 else
3896                         desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
3897         } else {
3898                 word_num = (vfid - 192) / 32;
3899                 bit_num  = vfid % 32;
3900                 if (clr)
3901                         desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
3902                 else
3903                         desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
3904         }
3905
3906         return 0;
3907 }
3908
3909 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3910 {
3911 #define HCLGE_DESC_NUMBER 3
3912 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3913         int i, j;
3914
3915         for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3916                 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3917                         if (desc[i].data[j])
3918                                 return false;
3919
3920         return true;
3921 }
3922
3923 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
3924                                    const u8 *addr)
3925 {
3926         const unsigned char *mac_addr = addr;
3927         u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3928                        (mac_addr[0]) | (mac_addr[1] << 8);
3929         u32 low_val  = mac_addr[4] | (mac_addr[5] << 8);
3930
3931         new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3932         new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3933 }
3934
3935 static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3936                                            const u8 *addr)
3937 {
3938         u16 high_val = addr[1] | (addr[0] << 8);
3939         struct hclge_dev *hdev = vport->back;
3940         u32 rsh = 4 - hdev->mta_mac_sel_type;
3941         u16 ret_val = (high_val >> rsh) & 0xfff;
3942
3943         return ret_val;
3944 }
3945
3946 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3947                                      enum hclge_mta_dmac_sel_type mta_mac_sel,
3948                                      bool enable)
3949 {
3950         struct hclge_mta_filter_mode_cmd *req;
3951         struct hclge_desc desc;
3952         int ret;
3953
3954         req = (struct hclge_mta_filter_mode_cmd *)desc.data;
3955         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3956
3957         hnae3_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3958                       enable);
3959         hnae3_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3960                         HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3961
3962         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3963         if (ret) {
3964                 dev_err(&hdev->pdev->dev,
3965                         "Config mat filter mode failed for cmd_send, ret =%d.\n",
3966                         ret);
3967                 return ret;
3968         }
3969
3970         return 0;
3971 }
3972
3973 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3974                               u8 func_id,
3975                               bool enable)
3976 {
3977         struct hclge_cfg_func_mta_filter_cmd *req;
3978         struct hclge_desc desc;
3979         int ret;
3980
3981         req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
3982         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3983
3984         hnae3_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3985                       enable);
3986         req->function_id = func_id;
3987
3988         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3989         if (ret) {
3990                 dev_err(&hdev->pdev->dev,
3991                         "Config func_id enable failed for cmd_send, ret =%d.\n",
3992                         ret);
3993                 return ret;
3994         }
3995
3996         return 0;
3997 }
3998
3999 static int hclge_set_mta_table_item(struct hclge_vport *vport,
4000                                     u16 idx,
4001                                     bool enable)
4002 {
4003         struct hclge_dev *hdev = vport->back;
4004         struct hclge_cfg_func_mta_item_cmd *req;
4005         struct hclge_desc desc;
4006         u16 item_idx = 0;
4007         int ret;
4008
4009         req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
4010         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
4011         hnae3_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
4012
4013         hnae3_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
4014                         HCLGE_CFG_MTA_ITEM_IDX_S, idx);
4015         req->item_idx = cpu_to_le16(item_idx);
4016
4017         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4018         if (ret) {
4019                 dev_err(&hdev->pdev->dev,
4020                         "Config mta table item failed for cmd_send, ret =%d.\n",
4021                         ret);
4022                 return ret;
4023         }
4024
4025         if (enable)
4026                 set_bit(idx, vport->mta_shadow);
4027         else
4028                 clear_bit(idx, vport->mta_shadow);
4029
4030         return 0;
4031 }
4032
4033 static int hclge_update_mta_status(struct hnae3_handle *handle)
4034 {
4035         unsigned long mta_status[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)];
4036         struct hclge_vport *vport = hclge_get_vport(handle);
4037         struct net_device *netdev = handle->kinfo.netdev;
4038         struct netdev_hw_addr *ha;
4039         u16 tbl_idx;
4040
4041         memset(mta_status, 0, sizeof(mta_status));
4042
4043         /* update mta_status from mc addr list */
4044         netdev_for_each_mc_addr(ha, netdev) {
4045                 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, ha->addr);
4046                 set_bit(tbl_idx, mta_status);
4047         }
4048
4049         return hclge_update_mta_status_common(vport, mta_status,
4050                                         0, HCLGE_MTA_TBL_SIZE, true);
4051 }
4052
4053 int hclge_update_mta_status_common(struct hclge_vport *vport,
4054                                    unsigned long *status,
4055                                    u16 idx,
4056                                    u16 count,
4057                                    bool update_filter)
4058 {
4059         struct hclge_dev *hdev = vport->back;
4060         u16 update_max = idx + count;
4061         u16 check_max;
4062         int ret = 0;
4063         bool used;
4064         u16 i;
4065
4066         /* setup mta check range */
4067         if (update_filter) {
4068                 i = 0;
4069                 check_max = HCLGE_MTA_TBL_SIZE;
4070         } else {
4071                 i = idx;
4072                 check_max = update_max;
4073         }
4074
4075         used = false;
4076         /* check and update all mta item */
4077         for (; i < check_max; i++) {
4078                 /* ignore unused item */
4079                 if (!test_bit(i, vport->mta_shadow))
4080                         continue;
4081
4082                 /* if i in update range then update it */
4083                 if (i >= idx && i < update_max)
4084                         if (!test_bit(i - idx, status))
4085                                 hclge_set_mta_table_item(vport, i, false);
4086
4087                 if (!used && test_bit(i, vport->mta_shadow))
4088                         used = true;
4089         }
4090
4091         /* no longer use mta, disable it */
4092         if (vport->accept_mta_mc && update_filter && !used) {
4093                 ret = hclge_cfg_func_mta_filter(hdev,
4094                                                 vport->vport_id,
4095                                                 false);
4096                 if (ret)
4097                         dev_err(&hdev->pdev->dev,
4098                                 "disable func mta filter fail ret=%d\n",
4099                                 ret);
4100                 else
4101                         vport->accept_mta_mc = false;
4102         }
4103
4104         return ret;
4105 }
4106
4107 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
4108                                      struct hclge_mac_vlan_tbl_entry_cmd *req)
4109 {
4110         struct hclge_dev *hdev = vport->back;
4111         struct hclge_desc desc;
4112         u8 resp_code;
4113         u16 retval;
4114         int ret;
4115
4116         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
4117
4118         memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4119
4120         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4121         if (ret) {
4122                 dev_err(&hdev->pdev->dev,
4123                         "del mac addr failed for cmd_send, ret =%d.\n",
4124                         ret);
4125                 return ret;
4126         }
4127         resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4128         retval = le16_to_cpu(desc.retval);
4129
4130         return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
4131                                              HCLGE_MAC_VLAN_REMOVE);
4132 }
4133
4134 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
4135                                      struct hclge_mac_vlan_tbl_entry_cmd *req,
4136                                      struct hclge_desc *desc,
4137                                      bool is_mc)
4138 {
4139         struct hclge_dev *hdev = vport->back;
4140         u8 resp_code;
4141         u16 retval;
4142         int ret;
4143
4144         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
4145         if (is_mc) {
4146                 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4147                 memcpy(desc[0].data,
4148                        req,
4149                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4150                 hclge_cmd_setup_basic_desc(&desc[1],
4151                                            HCLGE_OPC_MAC_VLAN_ADD,
4152                                            true);
4153                 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4154                 hclge_cmd_setup_basic_desc(&desc[2],
4155                                            HCLGE_OPC_MAC_VLAN_ADD,
4156                                            true);
4157                 ret = hclge_cmd_send(&hdev->hw, desc, 3);
4158         } else {
4159                 memcpy(desc[0].data,
4160                        req,
4161                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4162                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
4163         }
4164         if (ret) {
4165                 dev_err(&hdev->pdev->dev,
4166                         "lookup mac addr failed for cmd_send, ret =%d.\n",
4167                         ret);
4168                 return ret;
4169         }
4170         resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
4171         retval = le16_to_cpu(desc[0].retval);
4172
4173         return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
4174                                              HCLGE_MAC_VLAN_LKUP);
4175 }
4176
4177 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
4178                                   struct hclge_mac_vlan_tbl_entry_cmd *req,
4179                                   struct hclge_desc *mc_desc)
4180 {
4181         struct hclge_dev *hdev = vport->back;
4182         int cfg_status;
4183         u8 resp_code;
4184         u16 retval;
4185         int ret;
4186
4187         if (!mc_desc) {
4188                 struct hclge_desc desc;
4189
4190                 hclge_cmd_setup_basic_desc(&desc,
4191                                            HCLGE_OPC_MAC_VLAN_ADD,
4192                                            false);
4193                 memcpy(desc.data, req,
4194                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4195                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4196                 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4197                 retval = le16_to_cpu(desc.retval);
4198
4199                 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
4200                                                            resp_code,
4201                                                            HCLGE_MAC_VLAN_ADD);
4202         } else {
4203                 hclge_cmd_reuse_desc(&mc_desc[0], false);
4204                 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4205                 hclge_cmd_reuse_desc(&mc_desc[1], false);
4206                 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4207                 hclge_cmd_reuse_desc(&mc_desc[2], false);
4208                 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
4209                 memcpy(mc_desc[0].data, req,
4210                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4211                 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
4212                 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
4213                 retval = le16_to_cpu(mc_desc[0].retval);
4214
4215                 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
4216                                                            resp_code,
4217                                                            HCLGE_MAC_VLAN_ADD);
4218         }
4219
4220         if (ret) {
4221                 dev_err(&hdev->pdev->dev,
4222                         "add mac addr failed for cmd_send, ret =%d.\n",
4223                         ret);
4224                 return ret;
4225         }
4226
4227         return cfg_status;
4228 }
4229
4230 static int hclge_add_uc_addr(struct hnae3_handle *handle,
4231                              const unsigned char *addr)
4232 {
4233         struct hclge_vport *vport = hclge_get_vport(handle);
4234
4235         return hclge_add_uc_addr_common(vport, addr);
4236 }
4237
4238 int hclge_add_uc_addr_common(struct hclge_vport *vport,
4239                              const unsigned char *addr)
4240 {
4241         struct hclge_dev *hdev = vport->back;
4242         struct hclge_mac_vlan_tbl_entry_cmd req;
4243         struct hclge_desc desc;
4244         u16 egress_port = 0;
4245         int ret;
4246
4247         /* mac addr check */
4248         if (is_zero_ether_addr(addr) ||
4249             is_broadcast_ether_addr(addr) ||
4250             is_multicast_ether_addr(addr)) {
4251                 dev_err(&hdev->pdev->dev,
4252                         "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4253                          addr,
4254                          is_zero_ether_addr(addr),
4255                          is_broadcast_ether_addr(addr),
4256                          is_multicast_ether_addr(addr));
4257                 return -EINVAL;
4258         }
4259
4260         memset(&req, 0, sizeof(req));
4261         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4262
4263         hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
4264                         HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
4265
4266         req.egress_port = cpu_to_le16(egress_port);
4267
4268         hclge_prepare_mac_addr(&req, addr);
4269
4270         /* Lookup the mac address in the mac_vlan table, and add
4271          * it if the entry is inexistent. Repeated unicast entry
4272          * is not allowed in the mac vlan table.
4273          */
4274         ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
4275         if (ret == -ENOENT)
4276                 return hclge_add_mac_vlan_tbl(vport, &req, NULL);
4277
4278         /* check if we just hit the duplicate */
4279         if (!ret)
4280                 ret = -EINVAL;
4281
4282         dev_err(&hdev->pdev->dev,
4283                 "PF failed to add unicast entry(%pM) in the MAC table\n",
4284                 addr);
4285
4286         return ret;
4287 }
4288
4289 static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4290                             const unsigned char *addr)
4291 {
4292         struct hclge_vport *vport = hclge_get_vport(handle);
4293
4294         return hclge_rm_uc_addr_common(vport, addr);
4295 }
4296
4297 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4298                             const unsigned char *addr)
4299 {
4300         struct hclge_dev *hdev = vport->back;
4301         struct hclge_mac_vlan_tbl_entry_cmd req;
4302         int ret;
4303
4304         /* mac addr check */
4305         if (is_zero_ether_addr(addr) ||
4306             is_broadcast_ether_addr(addr) ||
4307             is_multicast_ether_addr(addr)) {
4308                 dev_dbg(&hdev->pdev->dev,
4309                         "Remove mac err! invalid mac:%pM.\n",
4310                          addr);
4311                 return -EINVAL;
4312         }
4313
4314         memset(&req, 0, sizeof(req));
4315         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4316         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4317         hclge_prepare_mac_addr(&req, addr);
4318         ret = hclge_remove_mac_vlan_tbl(vport, &req);
4319
4320         return ret;
4321 }
4322
4323 static int hclge_add_mc_addr(struct hnae3_handle *handle,
4324                              const unsigned char *addr)
4325 {
4326         struct hclge_vport *vport = hclge_get_vport(handle);
4327
4328         return  hclge_add_mc_addr_common(vport, addr);
4329 }
4330
4331 int hclge_add_mc_addr_common(struct hclge_vport *vport,
4332                              const unsigned char *addr)
4333 {
4334         struct hclge_dev *hdev = vport->back;
4335         struct hclge_mac_vlan_tbl_entry_cmd req;
4336         struct hclge_desc desc[3];
4337         u16 tbl_idx;
4338         int status;
4339
4340         /* mac addr check */
4341         if (!is_multicast_ether_addr(addr)) {
4342                 dev_err(&hdev->pdev->dev,
4343                         "Add mc mac err! invalid mac:%pM.\n",
4344                          addr);
4345                 return -EINVAL;
4346         }
4347         memset(&req, 0, sizeof(req));
4348         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4349         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4350         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4351         hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4352         hclge_prepare_mac_addr(&req, addr);
4353         status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4354         if (!status) {
4355                 /* This mac addr exist, update VFID for it */
4356                 hclge_update_desc_vfid(desc, vport->vport_id, false);
4357                 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4358         } else {
4359                 /* This mac addr do not exist, add new entry for it */
4360                 memset(desc[0].data, 0, sizeof(desc[0].data));
4361                 memset(desc[1].data, 0, sizeof(desc[0].data));
4362                 memset(desc[2].data, 0, sizeof(desc[0].data));
4363                 hclge_update_desc_vfid(desc, vport->vport_id, false);
4364                 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4365         }
4366
4367         /* If mc mac vlan table is full, use MTA table */
4368         if (status == -ENOSPC) {
4369                 if (!vport->accept_mta_mc) {
4370                         status = hclge_cfg_func_mta_filter(hdev,
4371                                                            vport->vport_id,
4372                                                            true);
4373                         if (status) {
4374                                 dev_err(&hdev->pdev->dev,
4375                                         "set mta filter mode fail ret=%d\n",
4376                                         status);
4377                                 return status;
4378                         }
4379                         vport->accept_mta_mc = true;
4380                 }
4381
4382                 /* Set MTA table for this MAC address */
4383                 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4384                 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4385         }
4386
4387         return status;
4388 }
4389
4390 static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4391                             const unsigned char *addr)
4392 {
4393         struct hclge_vport *vport = hclge_get_vport(handle);
4394
4395         return hclge_rm_mc_addr_common(vport, addr);
4396 }
4397
4398 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4399                             const unsigned char *addr)
4400 {
4401         struct hclge_dev *hdev = vport->back;
4402         struct hclge_mac_vlan_tbl_entry_cmd req;
4403         enum hclge_cmd_status status;
4404         struct hclge_desc desc[3];
4405
4406         /* mac addr check */
4407         if (!is_multicast_ether_addr(addr)) {
4408                 dev_dbg(&hdev->pdev->dev,
4409                         "Remove mc mac err! invalid mac:%pM.\n",
4410                          addr);
4411                 return -EINVAL;
4412         }
4413
4414         memset(&req, 0, sizeof(req));
4415         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4416         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4417         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4418         hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4419         hclge_prepare_mac_addr(&req, addr);
4420         status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4421         if (!status) {
4422                 /* This mac addr exist, remove this handle's VFID for it */
4423                 hclge_update_desc_vfid(desc, vport->vport_id, true);
4424
4425                 if (hclge_is_all_function_id_zero(desc))
4426                         /* All the vfid is zero, so need to delete this entry */
4427                         status = hclge_remove_mac_vlan_tbl(vport, &req);
4428                 else
4429                         /* Not all the vfid is zero, update the vfid */
4430                         status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4431
4432         } else {
4433                 /* Maybe this mac address is in mta table, but it cannot be
4434                  * deleted here because an entry of mta represents an address
4435                  * range rather than a specific address. the delete action to
4436                  * all entries will take effect in update_mta_status called by
4437                  * hns3_nic_set_rx_mode.
4438                  */
4439                 status = 0;
4440         }
4441
4442         return status;
4443 }
4444
4445 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
4446                                               u16 cmdq_resp, u8 resp_code)
4447 {
4448 #define HCLGE_ETHERTYPE_SUCCESS_ADD             0
4449 #define HCLGE_ETHERTYPE_ALREADY_ADD             1
4450 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW        2
4451 #define HCLGE_ETHERTYPE_KEY_CONFLICT            3
4452
4453         int return_status;
4454
4455         if (cmdq_resp) {
4456                 dev_err(&hdev->pdev->dev,
4457                         "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4458                         cmdq_resp);
4459                 return -EIO;
4460         }
4461
4462         switch (resp_code) {
4463         case HCLGE_ETHERTYPE_SUCCESS_ADD:
4464         case HCLGE_ETHERTYPE_ALREADY_ADD:
4465                 return_status = 0;
4466                 break;
4467         case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
4468                 dev_err(&hdev->pdev->dev,
4469                         "add mac ethertype failed for manager table overflow.\n");
4470                 return_status = -EIO;
4471                 break;
4472         case HCLGE_ETHERTYPE_KEY_CONFLICT:
4473                 dev_err(&hdev->pdev->dev,
4474                         "add mac ethertype failed for key conflict.\n");
4475                 return_status = -EIO;
4476                 break;
4477         default:
4478                 dev_err(&hdev->pdev->dev,
4479                         "add mac ethertype failed for undefined, code=%d.\n",
4480                         resp_code);
4481                 return_status = -EIO;
4482         }
4483
4484         return return_status;
4485 }
4486
4487 static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
4488                              const struct hclge_mac_mgr_tbl_entry_cmd *req)
4489 {
4490         struct hclge_desc desc;
4491         u8 resp_code;
4492         u16 retval;
4493         int ret;
4494
4495         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
4496         memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
4497
4498         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4499         if (ret) {
4500                 dev_err(&hdev->pdev->dev,
4501                         "add mac ethertype failed for cmd_send, ret =%d.\n",
4502                         ret);
4503                 return ret;
4504         }
4505
4506         resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4507         retval = le16_to_cpu(desc.retval);
4508
4509         return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
4510 }
4511
4512 static int init_mgr_tbl(struct hclge_dev *hdev)
4513 {
4514         int ret;
4515         int i;
4516
4517         for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
4518                 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
4519                 if (ret) {
4520                         dev_err(&hdev->pdev->dev,
4521                                 "add mac ethertype failed, ret =%d.\n",
4522                                 ret);
4523                         return ret;
4524                 }
4525         }
4526
4527         return 0;
4528 }
4529
4530 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4531 {
4532         struct hclge_vport *vport = hclge_get_vport(handle);
4533         struct hclge_dev *hdev = vport->back;
4534
4535         ether_addr_copy(p, hdev->hw.mac.mac_addr);
4536 }
4537
4538 static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
4539                               bool is_first)
4540 {
4541         const unsigned char *new_addr = (const unsigned char *)p;
4542         struct hclge_vport *vport = hclge_get_vport(handle);
4543         struct hclge_dev *hdev = vport->back;
4544         int ret;
4545
4546         /* mac addr check */
4547         if (is_zero_ether_addr(new_addr) ||
4548             is_broadcast_ether_addr(new_addr) ||
4549             is_multicast_ether_addr(new_addr)) {
4550                 dev_err(&hdev->pdev->dev,
4551                         "Change uc mac err! invalid mac:%p.\n",
4552                          new_addr);
4553                 return -EINVAL;
4554         }
4555
4556         if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
4557                 dev_warn(&hdev->pdev->dev,
4558                          "remove old uc mac address fail.\n");
4559
4560         ret = hclge_add_uc_addr(handle, new_addr);
4561         if (ret) {
4562                 dev_err(&hdev->pdev->dev,
4563                         "add uc mac address fail, ret =%d.\n",
4564                         ret);
4565
4566                 if (!is_first &&
4567                     hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
4568                         dev_err(&hdev->pdev->dev,
4569                                 "restore uc mac address fail.\n");
4570
4571                 return -EIO;
4572         }
4573
4574         ret = hclge_pause_addr_cfg(hdev, new_addr);
4575         if (ret) {
4576                 dev_err(&hdev->pdev->dev,
4577                         "configure mac pause address fail, ret =%d.\n",
4578                         ret);
4579                 return -EIO;
4580         }
4581
4582         ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4583
4584         return 0;
4585 }
4586
4587 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4588                                       bool filter_en)
4589 {
4590         struct hclge_vlan_filter_ctrl_cmd *req;
4591         struct hclge_desc desc;
4592         int ret;
4593
4594         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4595
4596         req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
4597         req->vlan_type = vlan_type;
4598         req->vlan_fe = filter_en;
4599
4600         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4601         if (ret) {
4602                 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4603                         ret);
4604                 return ret;
4605         }
4606
4607         return 0;
4608 }
4609
4610 #define HCLGE_FILTER_TYPE_VF            0
4611 #define HCLGE_FILTER_TYPE_PORT          1
4612
4613 static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
4614 {
4615         struct hclge_vport *vport = hclge_get_vport(handle);
4616         struct hclge_dev *hdev = vport->back;
4617
4618         hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable);
4619 }
4620
4621 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4622                                     bool is_kill, u16 vlan, u8 qos,
4623                                     __be16 proto)
4624 {
4625 #define HCLGE_MAX_VF_BYTES  16
4626         struct hclge_vlan_filter_vf_cfg_cmd *req0;
4627         struct hclge_vlan_filter_vf_cfg_cmd *req1;
4628         struct hclge_desc desc[2];
4629         u8 vf_byte_val;
4630         u8 vf_byte_off;
4631         int ret;
4632
4633         hclge_cmd_setup_basic_desc(&desc[0],
4634                                    HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4635         hclge_cmd_setup_basic_desc(&desc[1],
4636                                    HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4637
4638         desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4639
4640         vf_byte_off = vfid / 8;
4641         vf_byte_val = 1 << (vfid % 8);
4642
4643         req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4644         req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
4645
4646         req0->vlan_id  = cpu_to_le16(vlan);
4647         req0->vlan_cfg = is_kill;
4648
4649         if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4650                 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4651         else
4652                 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4653
4654         ret = hclge_cmd_send(&hdev->hw, desc, 2);
4655         if (ret) {
4656                 dev_err(&hdev->pdev->dev,
4657                         "Send vf vlan command fail, ret =%d.\n",
4658                         ret);
4659                 return ret;
4660         }
4661
4662         if (!is_kill) {
4663 #define HCLGE_VF_VLAN_NO_ENTRY  2
4664                 if (!req0->resp_code || req0->resp_code == 1)
4665                         return 0;
4666
4667                 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
4668                         dev_warn(&hdev->pdev->dev,
4669                                  "vf vlan table is full, vf vlan filter is disabled\n");
4670                         return 0;
4671                 }
4672
4673                 dev_err(&hdev->pdev->dev,
4674                         "Add vf vlan filter fail, ret =%d.\n",
4675                         req0->resp_code);
4676         } else {
4677                 if (!req0->resp_code)
4678                         return 0;
4679
4680                 dev_err(&hdev->pdev->dev,
4681                         "Kill vf vlan filter fail, ret =%d.\n",
4682                         req0->resp_code);
4683         }
4684
4685         return -EIO;
4686 }
4687
4688 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
4689                                       u16 vlan_id, bool is_kill)
4690 {
4691         struct hclge_vlan_filter_pf_cfg_cmd *req;
4692         struct hclge_desc desc;
4693         u8 vlan_offset_byte_val;
4694         u8 vlan_offset_byte;
4695         u8 vlan_offset_160;
4696         int ret;
4697
4698         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4699
4700         vlan_offset_160 = vlan_id / 160;
4701         vlan_offset_byte = (vlan_id % 160) / 8;
4702         vlan_offset_byte_val = 1 << (vlan_id % 8);
4703
4704         req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
4705         req->vlan_offset = vlan_offset_160;
4706         req->vlan_cfg = is_kill;
4707         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4708
4709         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4710         if (ret)
4711                 dev_err(&hdev->pdev->dev,
4712                         "port vlan command, send fail, ret =%d.\n", ret);
4713         return ret;
4714 }
4715
4716 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
4717                                     u16 vport_id, u16 vlan_id, u8 qos,
4718                                     bool is_kill)
4719 {
4720         u16 vport_idx, vport_num = 0;
4721         int ret;
4722
4723         ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
4724                                        0, proto);
4725         if (ret) {
4726                 dev_err(&hdev->pdev->dev,
4727                         "Set %d vport vlan filter config fail, ret =%d.\n",
4728                         vport_id, ret);
4729                 return ret;
4730         }
4731
4732         /* vlan 0 may be added twice when 8021q module is enabled */
4733         if (!is_kill && !vlan_id &&
4734             test_bit(vport_id, hdev->vlan_table[vlan_id]))
4735                 return 0;
4736
4737         if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
4738                 dev_err(&hdev->pdev->dev,
4739                         "Add port vlan failed, vport %d is already in vlan %d\n",
4740                         vport_id, vlan_id);
4741                 return -EINVAL;
4742         }
4743
4744         if (is_kill &&
4745             !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
4746                 dev_err(&hdev->pdev->dev,
4747                         "Delete port vlan failed, vport %d is not in vlan %d\n",
4748                         vport_id, vlan_id);
4749                 return -EINVAL;
4750         }
4751
4752         for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], VLAN_N_VID)
4753                 vport_num++;
4754
4755         if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
4756                 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
4757                                                  is_kill);
4758
4759         return ret;
4760 }
4761
4762 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
4763                           u16 vlan_id, bool is_kill)
4764 {
4765         struct hclge_vport *vport = hclge_get_vport(handle);
4766         struct hclge_dev *hdev = vport->back;
4767
4768         return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
4769                                         0, is_kill);
4770 }
4771
4772 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4773                                     u16 vlan, u8 qos, __be16 proto)
4774 {
4775         struct hclge_vport *vport = hclge_get_vport(handle);
4776         struct hclge_dev *hdev = vport->back;
4777
4778         if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4779                 return -EINVAL;
4780         if (proto != htons(ETH_P_8021Q))
4781                 return -EPROTONOSUPPORT;
4782
4783         return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
4784 }
4785
4786 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4787 {
4788         struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
4789         struct hclge_vport_vtag_tx_cfg_cmd *req;
4790         struct hclge_dev *hdev = vport->back;
4791         struct hclge_desc desc;
4792         int status;
4793
4794         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
4795
4796         req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4797         req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4798         req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
4799         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
4800                       vcfg->accept_tag1 ? 1 : 0);
4801         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
4802                       vcfg->accept_untag1 ? 1 : 0);
4803         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
4804                       vcfg->accept_tag2 ? 1 : 0);
4805         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
4806                       vcfg->accept_untag2 ? 1 : 0);
4807         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
4808                       vcfg->insert_tag1_en ? 1 : 0);
4809         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
4810                       vcfg->insert_tag2_en ? 1 : 0);
4811         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
4812
4813         req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4814         req->vf_bitmap[req->vf_offset] =
4815                 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4816
4817         status = hclge_cmd_send(&hdev->hw, &desc, 1);
4818         if (status)
4819                 dev_err(&hdev->pdev->dev,
4820                         "Send port txvlan cfg command fail, ret =%d\n",
4821                         status);
4822
4823         return status;
4824 }
4825
4826 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4827 {
4828         struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
4829         struct hclge_vport_vtag_rx_cfg_cmd *req;
4830         struct hclge_dev *hdev = vport->back;
4831         struct hclge_desc desc;
4832         int status;
4833
4834         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4835
4836         req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
4837         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4838                       vcfg->strip_tag1_en ? 1 : 0);
4839         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4840                       vcfg->strip_tag2_en ? 1 : 0);
4841         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4842                       vcfg->vlan1_vlan_prionly ? 1 : 0);
4843         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4844                       vcfg->vlan2_vlan_prionly ? 1 : 0);
4845
4846         req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4847         req->vf_bitmap[req->vf_offset] =
4848                 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4849
4850         status = hclge_cmd_send(&hdev->hw, &desc, 1);
4851         if (status)
4852                 dev_err(&hdev->pdev->dev,
4853                         "Send port rxvlan cfg command fail, ret =%d\n",
4854                         status);
4855
4856         return status;
4857 }
4858
4859 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4860 {
4861         struct hclge_rx_vlan_type_cfg_cmd *rx_req;
4862         struct hclge_tx_vlan_type_cfg_cmd *tx_req;
4863         struct hclge_desc desc;
4864         int status;
4865
4866         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
4867         rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
4868         rx_req->ot_fst_vlan_type =
4869                 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
4870         rx_req->ot_sec_vlan_type =
4871                 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
4872         rx_req->in_fst_vlan_type =
4873                 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
4874         rx_req->in_sec_vlan_type =
4875                 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
4876
4877         status = hclge_cmd_send(&hdev->hw, &desc, 1);
4878         if (status) {
4879                 dev_err(&hdev->pdev->dev,
4880                         "Send rxvlan protocol type command fail, ret =%d\n",
4881                         status);
4882                 return status;
4883         }
4884
4885         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4886
4887         tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data;
4888         tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4889         tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4890
4891         status = hclge_cmd_send(&hdev->hw, &desc, 1);
4892         if (status)
4893                 dev_err(&hdev->pdev->dev,
4894                         "Send txvlan protocol type command fail, ret =%d\n",
4895                         status);
4896
4897         return status;
4898 }
4899
4900 static int hclge_init_vlan_config(struct hclge_dev *hdev)
4901 {
4902 #define HCLGE_DEF_VLAN_TYPE             0x8100
4903
4904         struct hnae3_handle *handle;
4905         struct hclge_vport *vport;
4906         int ret;
4907         int i;
4908
4909         ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true);
4910         if (ret)
4911                 return ret;
4912
4913         ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true);
4914         if (ret)
4915                 return ret;
4916
4917         hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4918         hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4919         hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4920         hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4921         hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
4922         hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
4923
4924         ret = hclge_set_vlan_protocol_type(hdev);
4925         if (ret)
4926                 return ret;
4927
4928         for (i = 0; i < hdev->num_alloc_vport; i++) {
4929                 vport = &hdev->vport[i];
4930                 vport->txvlan_cfg.accept_tag1 = true;
4931                 vport->txvlan_cfg.accept_untag1 = true;
4932
4933                 /* accept_tag2 and accept_untag2 are not supported on
4934                  * pdev revision(0x20), new revision support them. The
4935                  * value of this two fields will not return error when driver
4936                  * send command to fireware in revision(0x20).
4937                  * This two fields can not configured by user.
4938                  */
4939                 vport->txvlan_cfg.accept_tag2 = true;
4940                 vport->txvlan_cfg.accept_untag2 = true;
4941
4942                 vport->txvlan_cfg.insert_tag1_en = false;
4943                 vport->txvlan_cfg.insert_tag2_en = false;
4944                 vport->txvlan_cfg.default_tag1 = 0;
4945                 vport->txvlan_cfg.default_tag2 = 0;
4946
4947                 ret = hclge_set_vlan_tx_offload_cfg(vport);
4948                 if (ret)
4949                         return ret;
4950
4951                 vport->rxvlan_cfg.strip_tag1_en = false;
4952                 vport->rxvlan_cfg.strip_tag2_en = true;
4953                 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4954                 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4955
4956                 ret = hclge_set_vlan_rx_offload_cfg(vport);
4957                 if (ret)
4958                         return ret;
4959         }
4960
4961         handle = &hdev->vport[0].nic;
4962         return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
4963 }
4964
4965 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
4966 {
4967         struct hclge_vport *vport = hclge_get_vport(handle);
4968
4969         vport->rxvlan_cfg.strip_tag1_en = false;
4970         vport->rxvlan_cfg.strip_tag2_en = enable;
4971         vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4972         vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4973
4974         return hclge_set_vlan_rx_offload_cfg(vport);
4975 }
4976
4977 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
4978 {
4979         struct hclge_config_max_frm_size_cmd *req;
4980         struct hclge_desc desc;
4981         int max_frm_size;
4982         int ret;
4983
4984         max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4985
4986         if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
4987             max_frm_size > HCLGE_MAC_MAX_FRAME)
4988                 return -EINVAL;
4989
4990         max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
4991
4992         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
4993
4994         req = (struct hclge_config_max_frm_size_cmd *)desc.data;
4995         req->max_frm_size = cpu_to_le16(max_frm_size);
4996         req->min_frm_size = HCLGE_MAC_MIN_FRAME;
4997
4998         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4999         if (ret) {
5000                 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
5001                 return ret;
5002         }
5003
5004         hdev->mps = max_frm_size;
5005
5006         return 0;
5007 }
5008
5009 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
5010 {
5011         struct hclge_vport *vport = hclge_get_vport(handle);
5012         struct hclge_dev *hdev = vport->back;
5013         int ret;
5014
5015         ret = hclge_set_mac_mtu(hdev, new_mtu);
5016         if (ret) {
5017                 dev_err(&hdev->pdev->dev,
5018                         "Change mtu fail, ret =%d\n", ret);
5019                 return ret;
5020         }
5021
5022         ret = hclge_buffer_alloc(hdev);
5023         if (ret)
5024                 dev_err(&hdev->pdev->dev,
5025                         "Allocate buffer fail, ret =%d\n", ret);
5026
5027         return ret;
5028 }
5029
5030 static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
5031                                     bool enable)
5032 {
5033         struct hclge_reset_tqp_queue_cmd *req;
5034         struct hclge_desc desc;
5035         int ret;
5036
5037         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
5038
5039         req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
5040         req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
5041         hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
5042
5043         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5044         if (ret) {
5045                 dev_err(&hdev->pdev->dev,
5046                         "Send tqp reset cmd error, status =%d\n", ret);
5047                 return ret;
5048         }
5049
5050         return 0;
5051 }
5052
5053 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
5054 {
5055         struct hclge_reset_tqp_queue_cmd *req;
5056         struct hclge_desc desc;
5057         int ret;
5058
5059         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
5060
5061         req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
5062         req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
5063
5064         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5065         if (ret) {
5066                 dev_err(&hdev->pdev->dev,
5067                         "Get reset status error, status =%d\n", ret);
5068                 return ret;
5069         }
5070
5071         return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
5072 }
5073
5074 static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
5075                                           u16 queue_id)
5076 {
5077         struct hnae3_queue *queue;
5078         struct hclge_tqp *tqp;
5079
5080         queue = handle->kinfo.tqp[queue_id];
5081         tqp = container_of(queue, struct hclge_tqp, q);
5082
5083         return tqp->index;
5084 }
5085
5086 void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
5087 {
5088         struct hclge_vport *vport = hclge_get_vport(handle);
5089         struct hclge_dev *hdev = vport->back;
5090         int reset_try_times = 0;
5091         int reset_status;
5092         u16 queue_gid;
5093         int ret;
5094
5095         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
5096                 return;
5097
5098         queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
5099
5100         ret = hclge_tqp_enable(hdev, queue_id, 0, false);
5101         if (ret) {
5102                 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
5103                 return;
5104         }
5105
5106         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
5107         if (ret) {
5108                 dev_warn(&hdev->pdev->dev,
5109                          "Send reset tqp cmd fail, ret = %d\n", ret);
5110                 return;
5111         }
5112
5113         reset_try_times = 0;
5114         while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
5115                 /* Wait for tqp hw reset */
5116                 msleep(20);
5117                 reset_status = hclge_get_reset_status(hdev, queue_gid);
5118                 if (reset_status)
5119                         break;
5120         }
5121
5122         if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
5123                 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
5124                 return;
5125         }
5126
5127         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
5128         if (ret) {
5129                 dev_warn(&hdev->pdev->dev,
5130                          "Deassert the soft reset fail, ret = %d\n", ret);
5131                 return;
5132         }
5133 }
5134
5135 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
5136 {
5137         struct hclge_dev *hdev = vport->back;
5138         int reset_try_times = 0;
5139         int reset_status;
5140         u16 queue_gid;
5141         int ret;
5142
5143         queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
5144
5145         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
5146         if (ret) {
5147                 dev_warn(&hdev->pdev->dev,
5148                          "Send reset tqp cmd fail, ret = %d\n", ret);
5149                 return;
5150         }
5151
5152         reset_try_times = 0;
5153         while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
5154                 /* Wait for tqp hw reset */
5155                 msleep(20);
5156                 reset_status = hclge_get_reset_status(hdev, queue_gid);
5157                 if (reset_status)
5158                         break;
5159         }
5160
5161         if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
5162                 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
5163                 return;
5164         }
5165
5166         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
5167         if (ret)
5168                 dev_warn(&hdev->pdev->dev,
5169                          "Deassert the soft reset fail, ret = %d\n", ret);
5170 }
5171
5172 static u32 hclge_get_fw_version(struct hnae3_handle *handle)
5173 {
5174         struct hclge_vport *vport = hclge_get_vport(handle);
5175         struct hclge_dev *hdev = vport->back;
5176
5177         return hdev->fw_version;
5178 }
5179
5180 static void hclge_get_flowctrl_adv(struct hnae3_handle *handle,
5181                                    u32 *flowctrl_adv)
5182 {
5183         struct hclge_vport *vport = hclge_get_vport(handle);
5184         struct hclge_dev *hdev = vport->back;
5185         struct phy_device *phydev = hdev->hw.mac.phydev;
5186
5187         if (!phydev)
5188                 return;
5189
5190         *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) |
5191                          (phydev->advertising & ADVERTISED_Asym_Pause);
5192 }
5193
5194 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5195 {
5196         struct phy_device *phydev = hdev->hw.mac.phydev;
5197
5198         if (!phydev)
5199                 return;
5200
5201         phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
5202
5203         if (rx_en)
5204                 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
5205
5206         if (tx_en)
5207                 phydev->advertising ^= ADVERTISED_Asym_Pause;
5208 }
5209
5210 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5211 {
5212         int ret;
5213
5214         if (rx_en && tx_en)
5215                 hdev->fc_mode_last_time = HCLGE_FC_FULL;
5216         else if (rx_en && !tx_en)
5217                 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
5218         else if (!rx_en && tx_en)
5219                 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
5220         else
5221                 hdev->fc_mode_last_time = HCLGE_FC_NONE;
5222
5223         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
5224                 return 0;
5225
5226         ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
5227         if (ret) {
5228                 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
5229                         ret);
5230                 return ret;
5231         }
5232
5233         hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
5234
5235         return 0;
5236 }
5237
5238 int hclge_cfg_flowctrl(struct hclge_dev *hdev)
5239 {
5240         struct phy_device *phydev = hdev->hw.mac.phydev;
5241         u16 remote_advertising = 0;
5242         u16 local_advertising = 0;
5243         u32 rx_pause, tx_pause;
5244         u8 flowctl;
5245
5246         if (!phydev->link || !phydev->autoneg)
5247                 return 0;
5248
5249         if (phydev->advertising & ADVERTISED_Pause)
5250                 local_advertising = ADVERTISE_PAUSE_CAP;
5251
5252         if (phydev->advertising & ADVERTISED_Asym_Pause)
5253                 local_advertising |= ADVERTISE_PAUSE_ASYM;
5254
5255         if (phydev->pause)
5256                 remote_advertising = LPA_PAUSE_CAP;
5257
5258         if (phydev->asym_pause)
5259                 remote_advertising |= LPA_PAUSE_ASYM;
5260
5261         flowctl = mii_resolve_flowctrl_fdx(local_advertising,
5262                                            remote_advertising);
5263         tx_pause = flowctl & FLOW_CTRL_TX;
5264         rx_pause = flowctl & FLOW_CTRL_RX;
5265
5266         if (phydev->duplex == HCLGE_MAC_HALF) {
5267                 tx_pause = 0;
5268                 rx_pause = 0;
5269         }
5270
5271         return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
5272 }
5273
5274 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
5275                                  u32 *rx_en, u32 *tx_en)
5276 {
5277         struct hclge_vport *vport = hclge_get_vport(handle);
5278         struct hclge_dev *hdev = vport->back;
5279
5280         *auto_neg = hclge_get_autoneg(handle);
5281
5282         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5283                 *rx_en = 0;
5284                 *tx_en = 0;
5285                 return;
5286         }
5287
5288         if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
5289                 *rx_en = 1;
5290                 *tx_en = 0;
5291         } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
5292                 *tx_en = 1;
5293                 *rx_en = 0;
5294         } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
5295                 *rx_en = 1;
5296                 *tx_en = 1;
5297         } else {
5298                 *rx_en = 0;
5299                 *tx_en = 0;
5300         }
5301 }
5302
5303 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
5304                                 u32 rx_en, u32 tx_en)
5305 {
5306         struct hclge_vport *vport = hclge_get_vport(handle);
5307         struct hclge_dev *hdev = vport->back;
5308         struct phy_device *phydev = hdev->hw.mac.phydev;
5309         u32 fc_autoneg;
5310
5311         fc_autoneg = hclge_get_autoneg(handle);
5312         if (auto_neg != fc_autoneg) {
5313                 dev_info(&hdev->pdev->dev,
5314                          "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5315                 return -EOPNOTSUPP;
5316         }
5317
5318         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5319                 dev_info(&hdev->pdev->dev,
5320                          "Priority flow control enabled. Cannot set link flow control.\n");
5321                 return -EOPNOTSUPP;
5322         }
5323
5324         hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
5325
5326         if (!fc_autoneg)
5327                 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
5328
5329         /* Only support flow control negotiation for netdev with
5330          * phy attached for now.
5331          */
5332         if (!phydev)
5333                 return -EOPNOTSUPP;
5334
5335         return phy_start_aneg(phydev);
5336 }
5337
5338 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
5339                                           u8 *auto_neg, u32 *speed, u8 *duplex)
5340 {
5341         struct hclge_vport *vport = hclge_get_vport(handle);
5342         struct hclge_dev *hdev = vport->back;
5343
5344         if (speed)
5345                 *speed = hdev->hw.mac.speed;
5346         if (duplex)
5347                 *duplex = hdev->hw.mac.duplex;
5348         if (auto_neg)
5349                 *auto_neg = hdev->hw.mac.autoneg;
5350 }
5351
5352 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
5353 {
5354         struct hclge_vport *vport = hclge_get_vport(handle);
5355         struct hclge_dev *hdev = vport->back;
5356
5357         if (media_type)
5358                 *media_type = hdev->hw.mac.media_type;
5359 }
5360
5361 static void hclge_get_mdix_mode(struct hnae3_handle *handle,
5362                                 u8 *tp_mdix_ctrl, u8 *tp_mdix)
5363 {
5364         struct hclge_vport *vport = hclge_get_vport(handle);
5365         struct hclge_dev *hdev = vport->back;
5366         struct phy_device *phydev = hdev->hw.mac.phydev;
5367         int mdix_ctrl, mdix, retval, is_resolved;
5368
5369         if (!phydev) {
5370                 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5371                 *tp_mdix = ETH_TP_MDI_INVALID;
5372                 return;
5373         }
5374
5375         phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
5376
5377         retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
5378         mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
5379                                     HCLGE_PHY_MDIX_CTRL_S);
5380
5381         retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
5382         mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
5383         is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
5384
5385         phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
5386
5387         switch (mdix_ctrl) {
5388         case 0x0:
5389                 *tp_mdix_ctrl = ETH_TP_MDI;
5390                 break;
5391         case 0x1:
5392                 *tp_mdix_ctrl = ETH_TP_MDI_X;
5393                 break;
5394         case 0x3:
5395                 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
5396                 break;
5397         default:
5398                 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5399                 break;
5400         }
5401
5402         if (!is_resolved)
5403                 *tp_mdix = ETH_TP_MDI_INVALID;
5404         else if (mdix)
5405                 *tp_mdix = ETH_TP_MDI_X;
5406         else
5407                 *tp_mdix = ETH_TP_MDI;
5408 }
5409
5410 static int hclge_init_client_instance(struct hnae3_client *client,
5411                                       struct hnae3_ae_dev *ae_dev)
5412 {
5413         struct hclge_dev *hdev = ae_dev->priv;
5414         struct hclge_vport *vport;
5415         int i, ret;
5416
5417         for (i = 0; i <  hdev->num_vmdq_vport + 1; i++) {
5418                 vport = &hdev->vport[i];
5419
5420                 switch (client->type) {
5421                 case HNAE3_CLIENT_KNIC:
5422
5423                         hdev->nic_client = client;
5424                         vport->nic.client = client;
5425                         ret = client->ops->init_instance(&vport->nic);
5426                         if (ret)
5427                                 return ret;
5428
5429                         if (hdev->roce_client &&
5430                             hnae3_dev_roce_supported(hdev)) {
5431                                 struct hnae3_client *rc = hdev->roce_client;
5432
5433                                 ret = hclge_init_roce_base_info(vport);
5434                                 if (ret)
5435                                         return ret;
5436
5437                                 ret = rc->ops->init_instance(&vport->roce);
5438                                 if (ret)
5439                                         return ret;
5440                         }
5441
5442                         break;
5443                 case HNAE3_CLIENT_UNIC:
5444                         hdev->nic_client = client;
5445                         vport->nic.client = client;
5446
5447                         ret = client->ops->init_instance(&vport->nic);
5448                         if (ret)
5449                                 return ret;
5450
5451                         break;
5452                 case HNAE3_CLIENT_ROCE:
5453                         if (hnae3_dev_roce_supported(hdev)) {
5454                                 hdev->roce_client = client;
5455                                 vport->roce.client = client;
5456                         }
5457
5458                         if (hdev->roce_client && hdev->nic_client) {
5459                                 ret = hclge_init_roce_base_info(vport);
5460                                 if (ret)
5461                                         return ret;
5462
5463                                 ret = client->ops->init_instance(&vport->roce);
5464                                 if (ret)
5465                                         return ret;
5466                         }
5467                 }
5468         }
5469
5470         return 0;
5471 }
5472
5473 static void hclge_uninit_client_instance(struct hnae3_client *client,
5474                                          struct hnae3_ae_dev *ae_dev)
5475 {
5476         struct hclge_dev *hdev = ae_dev->priv;
5477         struct hclge_vport *vport;
5478         int i;
5479
5480         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5481                 vport = &hdev->vport[i];
5482                 if (hdev->roce_client) {
5483                         hdev->roce_client->ops->uninit_instance(&vport->roce,
5484                                                                 0);
5485                         hdev->roce_client = NULL;
5486                         vport->roce.client = NULL;
5487                 }
5488                 if (client->type == HNAE3_CLIENT_ROCE)
5489                         return;
5490                 if (client->ops->uninit_instance) {
5491                         client->ops->uninit_instance(&vport->nic, 0);
5492                         hdev->nic_client = NULL;
5493                         vport->nic.client = NULL;
5494                 }
5495         }
5496 }
5497
5498 static int hclge_pci_init(struct hclge_dev *hdev)
5499 {
5500         struct pci_dev *pdev = hdev->pdev;
5501         struct hclge_hw *hw;
5502         int ret;
5503
5504         ret = pci_enable_device(pdev);
5505         if (ret) {
5506                 dev_err(&pdev->dev, "failed to enable PCI device\n");
5507                 return ret;
5508         }
5509
5510         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
5511         if (ret) {
5512                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5513                 if (ret) {
5514                         dev_err(&pdev->dev,
5515                                 "can't set consistent PCI DMA");
5516                         goto err_disable_device;
5517                 }
5518                 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
5519         }
5520
5521         ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
5522         if (ret) {
5523                 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
5524                 goto err_disable_device;
5525         }
5526
5527         pci_set_master(pdev);
5528         hw = &hdev->hw;
5529         hw->io_base = pcim_iomap(pdev, 2, 0);
5530         if (!hw->io_base) {
5531                 dev_err(&pdev->dev, "Can't map configuration register space\n");
5532                 ret = -ENOMEM;
5533                 goto err_clr_master;
5534         }
5535
5536         hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
5537
5538         return 0;
5539 err_clr_master:
5540         pci_clear_master(pdev);
5541         pci_release_regions(pdev);
5542 err_disable_device:
5543         pci_disable_device(pdev);
5544
5545         return ret;
5546 }
5547
5548 static void hclge_pci_uninit(struct hclge_dev *hdev)
5549 {
5550         struct pci_dev *pdev = hdev->pdev;
5551
5552         pcim_iounmap(pdev, hdev->hw.io_base);
5553         pci_free_irq_vectors(pdev);
5554         pci_clear_master(pdev);
5555         pci_release_mem_regions(pdev);
5556         pci_disable_device(pdev);
5557 }
5558
5559 static void hclge_state_init(struct hclge_dev *hdev)
5560 {
5561         set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
5562         set_bit(HCLGE_STATE_DOWN, &hdev->state);
5563         clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5564         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
5565         clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5566         clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
5567 }
5568
5569 static void hclge_state_uninit(struct hclge_dev *hdev)
5570 {
5571         set_bit(HCLGE_STATE_DOWN, &hdev->state);
5572
5573         if (hdev->service_timer.function)
5574                 del_timer_sync(&hdev->service_timer);
5575         if (hdev->service_task.func)
5576                 cancel_work_sync(&hdev->service_task);
5577         if (hdev->rst_service_task.func)
5578                 cancel_work_sync(&hdev->rst_service_task);
5579         if (hdev->mbx_service_task.func)
5580                 cancel_work_sync(&hdev->mbx_service_task);
5581 }
5582
5583 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5584 {
5585         struct pci_dev *pdev = ae_dev->pdev;
5586         struct hclge_dev *hdev;
5587         int ret;
5588
5589         hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
5590         if (!hdev) {
5591                 ret = -ENOMEM;
5592                 goto out;
5593         }
5594
5595         hdev->pdev = pdev;
5596         hdev->ae_dev = ae_dev;
5597         hdev->reset_type = HNAE3_NONE_RESET;
5598         hdev->reset_request = 0;
5599         hdev->reset_pending = 0;
5600         ae_dev->priv = hdev;
5601
5602         ret = hclge_pci_init(hdev);
5603         if (ret) {
5604                 dev_err(&pdev->dev, "PCI init failed\n");
5605                 goto out;
5606         }
5607
5608         /* Firmware command queue initialize */
5609         ret = hclge_cmd_queue_init(hdev);
5610         if (ret) {
5611                 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
5612                 goto err_pci_uninit;
5613         }
5614
5615         /* Firmware command initialize */
5616         ret = hclge_cmd_init(hdev);
5617         if (ret)
5618                 goto err_cmd_uninit;
5619
5620         ret = hclge_get_cap(hdev);
5621         if (ret) {
5622                 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5623                         ret);
5624                 goto err_cmd_uninit;
5625         }
5626
5627         ret = hclge_configure(hdev);
5628         if (ret) {
5629                 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5630                 goto err_cmd_uninit;
5631         }
5632
5633         ret = hclge_init_msi(hdev);
5634         if (ret) {
5635                 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
5636                 goto err_cmd_uninit;
5637         }
5638
5639         ret = hclge_misc_irq_init(hdev);
5640         if (ret) {
5641                 dev_err(&pdev->dev,
5642                         "Misc IRQ(vector0) init error, ret = %d.\n",
5643                         ret);
5644                 goto err_msi_uninit;
5645         }
5646
5647         ret = hclge_alloc_tqps(hdev);
5648         if (ret) {
5649                 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
5650                 goto err_msi_irq_uninit;
5651         }
5652
5653         ret = hclge_alloc_vport(hdev);
5654         if (ret) {
5655                 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
5656                 goto err_msi_irq_uninit;
5657         }
5658
5659         ret = hclge_map_tqp(hdev);
5660         if (ret) {
5661                 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5662                 goto err_msi_irq_uninit;
5663         }
5664
5665         if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
5666                 ret = hclge_mac_mdio_config(hdev);
5667                 if (ret) {
5668                         dev_err(&hdev->pdev->dev,
5669                                 "mdio config fail ret=%d\n", ret);
5670                         goto err_msi_irq_uninit;
5671                 }
5672         }
5673
5674         ret = hclge_mac_init(hdev);
5675         if (ret) {
5676                 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5677                 goto err_mdiobus_unreg;
5678         }
5679
5680         ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5681         if (ret) {
5682                 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5683                 goto err_mdiobus_unreg;
5684         }
5685
5686         ret = hclge_init_vlan_config(hdev);
5687         if (ret) {
5688                 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5689                 goto err_mdiobus_unreg;
5690         }
5691
5692         ret = hclge_tm_schd_init(hdev);
5693         if (ret) {
5694                 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
5695                 goto err_mdiobus_unreg;
5696         }
5697
5698         hclge_rss_init_cfg(hdev);
5699         ret = hclge_rss_init_hw(hdev);
5700         if (ret) {
5701                 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5702                 goto err_mdiobus_unreg;
5703         }
5704
5705         ret = init_mgr_tbl(hdev);
5706         if (ret) {
5707                 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
5708                 goto err_mdiobus_unreg;
5709         }
5710
5711         hclge_dcb_ops_set(hdev);
5712
5713         timer_setup(&hdev->service_timer, hclge_service_timer, 0);
5714         INIT_WORK(&hdev->service_task, hclge_service_task);
5715         INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
5716         INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
5717
5718         hclge_clear_all_event_cause(hdev);
5719
5720         /* Enable MISC vector(vector0) */
5721         hclge_enable_vector(&hdev->misc_vector, true);
5722
5723         hclge_state_init(hdev);
5724
5725         pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5726         return 0;
5727
5728 err_mdiobus_unreg:
5729         if (hdev->hw.mac.phydev)
5730                 mdiobus_unregister(hdev->hw.mac.mdio_bus);
5731 err_msi_irq_uninit:
5732         hclge_misc_irq_uninit(hdev);
5733 err_msi_uninit:
5734         pci_free_irq_vectors(pdev);
5735 err_cmd_uninit:
5736         hclge_destroy_cmd_queue(&hdev->hw);
5737 err_pci_uninit:
5738         pcim_iounmap(pdev, hdev->hw.io_base);
5739         pci_clear_master(pdev);
5740         pci_release_regions(pdev);
5741         pci_disable_device(pdev);
5742 out:
5743         return ret;
5744 }
5745
5746 static void hclge_stats_clear(struct hclge_dev *hdev)
5747 {
5748         memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
5749 }
5750
5751 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5752 {
5753         struct hclge_dev *hdev = ae_dev->priv;
5754         struct pci_dev *pdev = ae_dev->pdev;
5755         int ret;
5756
5757         set_bit(HCLGE_STATE_DOWN, &hdev->state);
5758
5759         hclge_stats_clear(hdev);
5760         memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
5761
5762         ret = hclge_cmd_init(hdev);
5763         if (ret) {
5764                 dev_err(&pdev->dev, "Cmd queue init failed\n");
5765                 return ret;
5766         }
5767
5768         ret = hclge_get_cap(hdev);
5769         if (ret) {
5770                 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5771                         ret);
5772                 return ret;
5773         }
5774
5775         ret = hclge_configure(hdev);
5776         if (ret) {
5777                 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5778                 return ret;
5779         }
5780
5781         ret = hclge_map_tqp(hdev);
5782         if (ret) {
5783                 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5784                 return ret;
5785         }
5786
5787         ret = hclge_mac_init(hdev);
5788         if (ret) {
5789                 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5790                 return ret;
5791         }
5792
5793         ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5794         if (ret) {
5795                 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5796                 return ret;
5797         }
5798
5799         ret = hclge_init_vlan_config(hdev);
5800         if (ret) {
5801                 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5802                 return ret;
5803         }
5804
5805         ret = hclge_tm_init_hw(hdev);
5806         if (ret) {
5807                 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
5808                 return ret;
5809         }
5810
5811         ret = hclge_rss_init_hw(hdev);
5812         if (ret) {
5813                 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5814                 return ret;
5815         }
5816
5817         dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5818                  HCLGE_DRIVER_NAME);
5819
5820         return 0;
5821 }
5822
5823 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5824 {
5825         struct hclge_dev *hdev = ae_dev->priv;
5826         struct hclge_mac *mac = &hdev->hw.mac;
5827
5828         hclge_state_uninit(hdev);
5829
5830         if (mac->phydev)
5831                 mdiobus_unregister(mac->mdio_bus);
5832
5833         /* Disable MISC vector(vector0) */
5834         hclge_enable_vector(&hdev->misc_vector, false);
5835         synchronize_irq(hdev->misc_vector.vector_irq);
5836
5837         hclge_destroy_cmd_queue(&hdev->hw);
5838         hclge_misc_irq_uninit(hdev);
5839         hclge_pci_uninit(hdev);
5840         ae_dev->priv = NULL;
5841 }
5842
5843 static u32 hclge_get_max_channels(struct hnae3_handle *handle)
5844 {
5845         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5846         struct hclge_vport *vport = hclge_get_vport(handle);
5847         struct hclge_dev *hdev = vport->back;
5848
5849         return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
5850 }
5851
5852 static void hclge_get_channels(struct hnae3_handle *handle,
5853                                struct ethtool_channels *ch)
5854 {
5855         struct hclge_vport *vport = hclge_get_vport(handle);
5856
5857         ch->max_combined = hclge_get_max_channels(handle);
5858         ch->other_count = 1;
5859         ch->max_other = 1;
5860         ch->combined_count = vport->alloc_tqps;
5861 }
5862
5863 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
5864                                         u16 *free_tqps, u16 *max_rss_size)
5865 {
5866         struct hclge_vport *vport = hclge_get_vport(handle);
5867         struct hclge_dev *hdev = vport->back;
5868         u16 temp_tqps = 0;
5869         int i;
5870
5871         for (i = 0; i < hdev->num_tqps; i++) {
5872                 if (!hdev->htqp[i].alloced)
5873                         temp_tqps++;
5874         }
5875         *free_tqps = temp_tqps;
5876         *max_rss_size = hdev->rss_size_max;
5877 }
5878
5879 static void hclge_release_tqp(struct hclge_vport *vport)
5880 {
5881         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5882         struct hclge_dev *hdev = vport->back;
5883         int i;
5884
5885         for (i = 0; i < kinfo->num_tqps; i++) {
5886                 struct hclge_tqp *tqp =
5887                         container_of(kinfo->tqp[i], struct hclge_tqp, q);
5888
5889                 tqp->q.handle = NULL;
5890                 tqp->q.tqp_index = 0;
5891                 tqp->alloced = false;
5892         }
5893
5894         devm_kfree(&hdev->pdev->dev, kinfo->tqp);
5895         kinfo->tqp = NULL;
5896 }
5897
5898 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5899 {
5900         struct hclge_vport *vport = hclge_get_vport(handle);
5901         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5902         struct hclge_dev *hdev = vport->back;
5903         int cur_rss_size = kinfo->rss_size;
5904         int cur_tqps = kinfo->num_tqps;
5905         u16 tc_offset[HCLGE_MAX_TC_NUM];
5906         u16 tc_valid[HCLGE_MAX_TC_NUM];
5907         u16 tc_size[HCLGE_MAX_TC_NUM];
5908         u16 roundup_size;
5909         u32 *rss_indir;
5910         int ret, i;
5911
5912         hclge_release_tqp(vport);
5913
5914         ret = hclge_knic_setup(vport, new_tqps_num);
5915         if (ret) {
5916                 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5917                 return ret;
5918         }
5919
5920         ret = hclge_map_tqp_to_vport(hdev, vport);
5921         if (ret) {
5922                 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
5923                 return ret;
5924         }
5925
5926         ret = hclge_tm_schd_init(hdev);
5927         if (ret) {
5928                 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
5929                 return ret;
5930         }
5931
5932         roundup_size = roundup_pow_of_two(kinfo->rss_size);
5933         roundup_size = ilog2(roundup_size);
5934         /* Set the RSS TC mode according to the new RSS size */
5935         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
5936                 tc_valid[i] = 0;
5937
5938                 if (!(hdev->hw_tc_map & BIT(i)))
5939                         continue;
5940
5941                 tc_valid[i] = 1;
5942                 tc_size[i] = roundup_size;
5943                 tc_offset[i] = kinfo->rss_size * i;
5944         }
5945         ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
5946         if (ret)
5947                 return ret;
5948
5949         /* Reinitializes the rss indirect table according to the new RSS size */
5950         rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
5951         if (!rss_indir)
5952                 return -ENOMEM;
5953
5954         for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
5955                 rss_indir[i] = i % kinfo->rss_size;
5956
5957         ret = hclge_set_rss(handle, rss_indir, NULL, 0);
5958         if (ret)
5959                 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
5960                         ret);
5961
5962         kfree(rss_indir);
5963
5964         if (!ret)
5965                 dev_info(&hdev->pdev->dev,
5966                          "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5967                          cur_rss_size, kinfo->rss_size,
5968                          cur_tqps, kinfo->rss_size * kinfo->num_tc);
5969
5970         return ret;
5971 }
5972
5973 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
5974                               u32 *regs_num_64_bit)
5975 {
5976         struct hclge_desc desc;
5977         u32 total_num;
5978         int ret;
5979
5980         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
5981         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5982         if (ret) {
5983                 dev_err(&hdev->pdev->dev,
5984                         "Query register number cmd failed, ret = %d.\n", ret);
5985                 return ret;
5986         }
5987
5988         *regs_num_32_bit = le32_to_cpu(desc.data[0]);
5989         *regs_num_64_bit = le32_to_cpu(desc.data[1]);
5990
5991         total_num = *regs_num_32_bit + *regs_num_64_bit;
5992         if (!total_num)
5993                 return -EINVAL;
5994
5995         return 0;
5996 }
5997
5998 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
5999                                  void *data)
6000 {
6001 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
6002
6003         struct hclge_desc *desc;
6004         u32 *reg_val = data;
6005         __le32 *desc_data;
6006         int cmd_num;
6007         int i, k, n;
6008         int ret;
6009
6010         if (regs_num == 0)
6011                 return 0;
6012
6013         cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
6014         desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
6015         if (!desc)
6016                 return -ENOMEM;
6017
6018         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
6019         ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
6020         if (ret) {
6021                 dev_err(&hdev->pdev->dev,
6022                         "Query 32 bit register cmd failed, ret = %d.\n", ret);
6023                 kfree(desc);
6024                 return ret;
6025         }
6026
6027         for (i = 0; i < cmd_num; i++) {
6028                 if (i == 0) {
6029                         desc_data = (__le32 *)(&desc[i].data[0]);
6030                         n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
6031                 } else {
6032                         desc_data = (__le32 *)(&desc[i]);
6033                         n = HCLGE_32_BIT_REG_RTN_DATANUM;
6034                 }
6035                 for (k = 0; k < n; k++) {
6036                         *reg_val++ = le32_to_cpu(*desc_data++);
6037
6038                         regs_num--;
6039                         if (!regs_num)
6040                                 break;
6041                 }
6042         }
6043
6044         kfree(desc);
6045         return 0;
6046 }
6047
6048 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
6049                                  void *data)
6050 {
6051 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
6052
6053         struct hclge_desc *desc;
6054         u64 *reg_val = data;
6055         __le64 *desc_data;
6056         int cmd_num;
6057         int i, k, n;
6058         int ret;
6059
6060         if (regs_num == 0)
6061                 return 0;
6062
6063         cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
6064         desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
6065         if (!desc)
6066                 return -ENOMEM;
6067
6068         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
6069         ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
6070         if (ret) {
6071                 dev_err(&hdev->pdev->dev,
6072                         "Query 64 bit register cmd failed, ret = %d.\n", ret);
6073                 kfree(desc);
6074                 return ret;
6075         }
6076
6077         for (i = 0; i < cmd_num; i++) {
6078                 if (i == 0) {
6079                         desc_data = (__le64 *)(&desc[i].data[0]);
6080                         n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
6081                 } else {
6082                         desc_data = (__le64 *)(&desc[i]);
6083                         n = HCLGE_64_BIT_REG_RTN_DATANUM;
6084                 }
6085                 for (k = 0; k < n; k++) {
6086                         *reg_val++ = le64_to_cpu(*desc_data++);
6087
6088                         regs_num--;
6089                         if (!regs_num)
6090                                 break;
6091                 }
6092         }
6093
6094         kfree(desc);
6095         return 0;
6096 }
6097
6098 static int hclge_get_regs_len(struct hnae3_handle *handle)
6099 {
6100         struct hclge_vport *vport = hclge_get_vport(handle);
6101         struct hclge_dev *hdev = vport->back;
6102         u32 regs_num_32_bit, regs_num_64_bit;
6103         int ret;
6104
6105         ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
6106         if (ret) {
6107                 dev_err(&hdev->pdev->dev,
6108                         "Get register number failed, ret = %d.\n", ret);
6109                 return -EOPNOTSUPP;
6110         }
6111
6112         return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
6113 }
6114
6115 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
6116                            void *data)
6117 {
6118         struct hclge_vport *vport = hclge_get_vport(handle);
6119         struct hclge_dev *hdev = vport->back;
6120         u32 regs_num_32_bit, regs_num_64_bit;
6121         int ret;
6122
6123         *version = hdev->fw_version;
6124
6125         ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
6126         if (ret) {
6127                 dev_err(&hdev->pdev->dev,
6128                         "Get register number failed, ret = %d.\n", ret);
6129                 return;
6130         }
6131
6132         ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
6133         if (ret) {
6134                 dev_err(&hdev->pdev->dev,
6135                         "Get 32 bit register failed, ret = %d.\n", ret);
6136                 return;
6137         }
6138
6139         data = (u32 *)data + regs_num_32_bit;
6140         ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
6141                                     data);
6142         if (ret)
6143                 dev_err(&hdev->pdev->dev,
6144                         "Get 64 bit register failed, ret = %d.\n", ret);
6145 }
6146
6147 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
6148 {
6149         struct hclge_set_led_state_cmd *req;
6150         struct hclge_desc desc;
6151         int ret;
6152
6153         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
6154
6155         req = (struct hclge_set_led_state_cmd *)desc.data;
6156         hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
6157                         HCLGE_LED_LOCATE_STATE_S, locate_led_status);
6158
6159         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6160         if (ret)
6161                 dev_err(&hdev->pdev->dev,
6162                         "Send set led state cmd error, ret =%d\n", ret);
6163
6164         return ret;
6165 }
6166
6167 enum hclge_led_status {
6168         HCLGE_LED_OFF,
6169         HCLGE_LED_ON,
6170         HCLGE_LED_NO_CHANGE = 0xFF,
6171 };
6172
6173 static int hclge_set_led_id(struct hnae3_handle *handle,
6174                             enum ethtool_phys_id_state status)
6175 {
6176         struct hclge_vport *vport = hclge_get_vport(handle);
6177         struct hclge_dev *hdev = vport->back;
6178
6179         switch (status) {
6180         case ETHTOOL_ID_ACTIVE:
6181                 return hclge_set_led_status(hdev, HCLGE_LED_ON);
6182         case ETHTOOL_ID_INACTIVE:
6183                 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
6184         default:
6185                 return -EINVAL;
6186         }
6187 }
6188
6189 static void hclge_get_link_mode(struct hnae3_handle *handle,
6190                                 unsigned long *supported,
6191                                 unsigned long *advertising)
6192 {
6193         unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
6194         struct hclge_vport *vport = hclge_get_vport(handle);
6195         struct hclge_dev *hdev = vport->back;
6196         unsigned int idx = 0;
6197
6198         for (; idx < size; idx++) {
6199                 supported[idx] = hdev->hw.mac.supported[idx];
6200                 advertising[idx] = hdev->hw.mac.advertising[idx];
6201         }
6202 }
6203
6204 static void hclge_get_port_type(struct hnae3_handle *handle,
6205                                 u8 *port_type)
6206 {
6207         struct hclge_vport *vport = hclge_get_vport(handle);
6208         struct hclge_dev *hdev = vport->back;
6209         u8 media_type = hdev->hw.mac.media_type;
6210
6211         switch (media_type) {
6212         case HNAE3_MEDIA_TYPE_FIBER:
6213                 *port_type = PORT_FIBRE;
6214                 break;
6215         case HNAE3_MEDIA_TYPE_COPPER:
6216                 *port_type = PORT_TP;
6217                 break;
6218         case HNAE3_MEDIA_TYPE_UNKNOWN:
6219         default:
6220                 *port_type = PORT_OTHER;
6221                 break;
6222         }
6223 }
6224
6225 static const struct hnae3_ae_ops hclge_ops = {
6226         .init_ae_dev = hclge_init_ae_dev,
6227         .uninit_ae_dev = hclge_uninit_ae_dev,
6228         .init_client_instance = hclge_init_client_instance,
6229         .uninit_client_instance = hclge_uninit_client_instance,
6230         .map_ring_to_vector = hclge_map_ring_to_vector,
6231         .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
6232         .get_vector = hclge_get_vector,
6233         .put_vector = hclge_put_vector,
6234         .set_promisc_mode = hclge_set_promisc_mode,
6235         .set_loopback = hclge_set_loopback,
6236         .start = hclge_ae_start,
6237         .stop = hclge_ae_stop,
6238         .get_status = hclge_get_status,
6239         .get_ksettings_an_result = hclge_get_ksettings_an_result,
6240         .update_speed_duplex_h = hclge_update_speed_duplex_h,
6241         .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
6242         .get_media_type = hclge_get_media_type,
6243         .get_rss_key_size = hclge_get_rss_key_size,
6244         .get_rss_indir_size = hclge_get_rss_indir_size,
6245         .get_rss = hclge_get_rss,
6246         .set_rss = hclge_set_rss,
6247         .set_rss_tuple = hclge_set_rss_tuple,
6248         .get_rss_tuple = hclge_get_rss_tuple,
6249         .get_tc_size = hclge_get_tc_size,
6250         .get_mac_addr = hclge_get_mac_addr,
6251         .set_mac_addr = hclge_set_mac_addr,
6252         .add_uc_addr = hclge_add_uc_addr,
6253         .rm_uc_addr = hclge_rm_uc_addr,
6254         .add_mc_addr = hclge_add_mc_addr,
6255         .rm_mc_addr = hclge_rm_mc_addr,
6256         .update_mta_status = hclge_update_mta_status,
6257         .set_autoneg = hclge_set_autoneg,
6258         .get_autoneg = hclge_get_autoneg,
6259         .get_pauseparam = hclge_get_pauseparam,
6260         .set_pauseparam = hclge_set_pauseparam,
6261         .set_mtu = hclge_set_mtu,
6262         .reset_queue = hclge_reset_tqp,
6263         .get_stats = hclge_get_stats,
6264         .update_stats = hclge_update_stats,
6265         .get_strings = hclge_get_strings,
6266         .get_sset_count = hclge_get_sset_count,
6267         .get_fw_version = hclge_get_fw_version,
6268         .get_mdix_mode = hclge_get_mdix_mode,
6269         .enable_vlan_filter = hclge_enable_vlan_filter,
6270         .set_vlan_filter = hclge_set_vlan_filter,
6271         .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
6272         .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
6273         .reset_event = hclge_reset_event,
6274         .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
6275         .set_channels = hclge_set_channels,
6276         .get_channels = hclge_get_channels,
6277         .get_flowctrl_adv = hclge_get_flowctrl_adv,
6278         .get_regs_len = hclge_get_regs_len,
6279         .get_regs = hclge_get_regs,
6280         .set_led_id = hclge_set_led_id,
6281         .get_link_mode = hclge_get_link_mode,
6282         .get_port_type = hclge_get_port_type,
6283 };
6284
6285 static struct hnae3_ae_algo ae_algo = {
6286         .ops = &hclge_ops,
6287         .pdev_id_table = ae_algo_pci_tbl,
6288 };
6289
6290 static int hclge_init(void)
6291 {
6292         pr_info("%s is initializing\n", HCLGE_NAME);
6293
6294         hnae3_register_ae_algo(&ae_algo);
6295
6296         return 0;
6297 }
6298
6299 static void hclge_exit(void)
6300 {
6301         hnae3_unregister_ae_algo(&ae_algo);
6302 }
6303 module_init(hclge_init);
6304 module_exit(hclge_exit);
6305
6306 MODULE_LICENSE("GPL");
6307 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6308 MODULE_DESCRIPTION("HCLGE Driver");
6309 MODULE_VERSION(HCLGE_MOD_VERSION);