drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Copyright (c) 2018-2019 Hisilicon Limited. */
   3
   4 #include <linux/device.h>
   5
   6 #include "hclge_debugfs.h"
   7 #include "hclge_main.h"
   8 #include "hclge_tm.h"
   9 #include "hnae3.h"
  10
  11 static struct hclge_dbg_reg_type_info hclge_dbg_reg_info[] = {
  12         { .reg_type = "bios common",
  13           .dfx_msg = &hclge_dbg_bios_common_reg[0],
  14           .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_bios_common_reg),
  15                        .offset = HCLGE_DBG_DFX_BIOS_OFFSET,
  16                        .cmd = HCLGE_OPC_DFX_BIOS_COMMON_REG } },
  17         { .reg_type = "ssu",
  18           .dfx_msg = &hclge_dbg_ssu_reg_0[0],
  19           .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ssu_reg_0),
  20                        .offset = HCLGE_DBG_DFX_SSU_0_OFFSET,
  21                        .cmd = HCLGE_OPC_DFX_SSU_REG_0 } },
  22         { .reg_type = "ssu",
  23           .dfx_msg = &hclge_dbg_ssu_reg_1[0],
  24           .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ssu_reg_1),
  25                        .offset = HCLGE_DBG_DFX_SSU_1_OFFSET,
  26                        .cmd = HCLGE_OPC_DFX_SSU_REG_1 } },
  27         { .reg_type = "ssu",
  28           .dfx_msg = &hclge_dbg_ssu_reg_2[0],
  29           .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ssu_reg_2),
  30                        .offset = HCLGE_DBG_DFX_SSU_2_OFFSET,
  31                        .cmd = HCLGE_OPC_DFX_SSU_REG_2 } },
  32         { .reg_type = "igu egu",
  33           .dfx_msg = &hclge_dbg_igu_egu_reg[0],
  34           .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_igu_egu_reg),
  35                        .offset = HCLGE_DBG_DFX_IGU_OFFSET,
  36                        .cmd = HCLGE_OPC_DFX_IGU_EGU_REG } },
  37         { .reg_type = "rpu",
  38           .dfx_msg = &hclge_dbg_rpu_reg_0[0],
  39           .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_rpu_reg_0),
  40                        .offset = HCLGE_DBG_DFX_RPU_0_OFFSET,
  41                        .cmd = HCLGE_OPC_DFX_RPU_REG_0 } },
  42         { .reg_type = "rpu",
  43           .dfx_msg = &hclge_dbg_rpu_reg_1[0],
  44           .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_rpu_reg_1),
  45                        .offset = HCLGE_DBG_DFX_RPU_1_OFFSET,
  46                        .cmd = HCLGE_OPC_DFX_RPU_REG_1 } },
  47         { .reg_type = "ncsi",
  48           .dfx_msg = &hclge_dbg_ncsi_reg[0],
  49           .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ncsi_reg),
  50                        .offset = HCLGE_DBG_DFX_NCSI_OFFSET,
  51                        .cmd = HCLGE_OPC_DFX_NCSI_REG } },
  52         { .reg_type = "rtc",
  53           .dfx_msg = &hclge_dbg_rtc_reg[0],
  54           .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_rtc_reg),
  55                        .offset = HCLGE_DBG_DFX_RTC_OFFSET,
  56                        .cmd = HCLGE_OPC_DFX_RTC_REG } },
  57         { .reg_type = "ppp",
  58           .dfx_msg = &hclge_dbg_ppp_reg[0],
  59           .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ppp_reg),
  60                        .offset = HCLGE_DBG_DFX_PPP_OFFSET,
  61                        .cmd = HCLGE_OPC_DFX_PPP_REG } },
  62         { .reg_type = "rcb",
  63           .dfx_msg = &hclge_dbg_rcb_reg[0],
  64           .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_rcb_reg),
  65                        .offset = HCLGE_DBG_DFX_RCB_OFFSET,
  66                        .cmd = HCLGE_OPC_DFX_RCB_REG } },
  67         { .reg_type = "tqp",
  68           .dfx_msg = &hclge_dbg_tqp_reg[0],
  69           .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_tqp_reg),
  70                        .offset = HCLGE_DBG_DFX_TQP_OFFSET,
  71                        .cmd = HCLGE_OPC_DFX_TQP_REG } },
  72 };
  73
  74 static int hclge_dbg_get_dfx_bd_num(struct hclge_dev *hdev, int offset)
  75 {
  76         struct hclge_desc desc[HCLGE_GET_DFX_REG_TYPE_CNT];
  77         int entries_per_desc;
  78         int index;
  79         int ret;
  80
  81         ret = hclge_query_bd_num_cmd_send(hdev, desc);
  82         if (ret) {
  83                 dev_err(&hdev->pdev->dev,
  84                         "get dfx bdnum fail, ret = %d\n", ret);
  85                 return ret;
  86         }
  87
  88         entries_per_desc = ARRAY_SIZE(desc[0].data);
  89         index = offset % entries_per_desc;
  90         return le32_to_cpu(desc[offset / entries_per_desc].data[index]);
  91 }
  92
  93 static int hclge_dbg_cmd_send(struct hclge_dev *hdev,
  94                               struct hclge_desc *desc_src,
  95                               int index, int bd_num,
  96                               enum hclge_opcode_type cmd)
  97 {
  98         struct hclge_desc *desc = desc_src;
  99         int ret, i;
 100
 101         hclge_cmd_setup_basic_desc(desc, cmd, true);
 102         desc->data[0] = cpu_to_le32(index);
 103
 104         for (i = 1; i < bd_num; i++) {
 105                 desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
 106                 desc++;
 107                 hclge_cmd_setup_basic_desc(desc, cmd, true);
 108         }
 109
 110         ret = hclge_cmd_send(&hdev->hw, desc_src, bd_num);
 111         if (ret)
 112                 dev_err(&hdev->pdev->dev,
 113                         "cmd(0x%x) send fail, ret = %d\n", cmd, ret);
 114         return ret;
 115 }
 116
 117 static void hclge_dbg_dump_reg_common(struct hclge_dev *hdev,
 118                                       struct hclge_dbg_reg_type_info *reg_info,
 119                                       const char *cmd_buf)
 120 {
 121 #define IDX_OFFSET      1
 122
 123         const char *s = &cmd_buf[strlen(reg_info->reg_type) + IDX_OFFSET];
 124         struct hclge_dbg_dfx_message *dfx_message = reg_info->dfx_msg;
 125         struct hclge_dbg_reg_common_msg *reg_msg = &reg_info->reg_msg;
 126         struct hclge_desc *desc_src;
 127         struct hclge_desc *desc;
 128         int entries_per_desc;
 129         int bd_num, buf_len;
 130         int index = 0;
 131         int min_num;
 132         int ret, i;
 133
 134         if (*s) {
 135                 ret = kstrtouint(s, 0, &index);
 136                 index = (ret != 0) ? 0 : index;
 137         }
 138
 139         bd_num = hclge_dbg_get_dfx_bd_num(hdev, reg_msg->offset);
 140         if (bd_num <= 0) {
 141                 dev_err(&hdev->pdev->dev, "get cmd(%d) bd num(%d) failed\n",
 142                         reg_msg->offset, bd_num);
 143                 return;
 144         }
 145
 146         buf_len = sizeof(struct hclge_desc) * bd_num;
 147         desc_src = kzalloc(buf_len, GFP_KERNEL);
 148         if (!desc_src) {
 149                 dev_err(&hdev->pdev->dev, "call kzalloc failed\n");
 150                 return;
 151         }
 152
 153         desc = desc_src;
 154         ret = hclge_dbg_cmd_send(hdev, desc, index, bd_num, reg_msg->cmd);
 155         if (ret) {
 156                 kfree(desc_src);
 157                 return;
 158         }
 159
 160         entries_per_desc = ARRAY_SIZE(desc->data);
 161         min_num = min_t(int, bd_num * entries_per_desc, reg_msg->msg_num);
 162
 163         desc = desc_src;
 164         for (i = 0; i < min_num; i++) {
 165                 if (i > 0 && (i % entries_per_desc) == 0)
 166                         desc++;
 167                 if (dfx_message->flag)
 168                         dev_info(&hdev->pdev->dev, "%s: 0x%x\n",
 169                                  dfx_message->message,
 170                                  le32_to_cpu(desc->data[i % entries_per_desc]));
 171
 172                 dfx_message++;
 173         }
 174
 175         kfree(desc_src);
 176 }
 177
 178 static void hclge_dbg_dump_dcb(struct hclge_dev *hdev, const char *cmd_buf)
 179 {
 180         struct device *dev = &hdev->pdev->dev;
 181         struct hclge_dbg_bitmap_cmd *bitmap;
 182         enum hclge_opcode_type cmd;
 183         int rq_id, pri_id, qset_id;
 184         int port_id, nq_id, pg_id;
 185         struct hclge_desc desc[2];
 186
 187         int cnt, ret;
 188
 189         cnt = sscanf(cmd_buf, "%i %i %i %i %i %i",
 190                      &port_id, &pri_id, &pg_id, &rq_id, &nq_id, &qset_id);
 191         if (cnt != 6) {
 192                 dev_err(&hdev->pdev->dev,
 193                         "dump dcb: bad command parameter, cnt=%d\n", cnt);
 194                 return;
 195         }
 196
 197         cmd = HCLGE_OPC_QSET_DFX_STS;
 198         ret = hclge_dbg_cmd_send(hdev, desc, qset_id, 1, cmd);
 199         if (ret)
 200                 goto err_dcb_cmd_send;
 201
 202         bitmap = (struct hclge_dbg_bitmap_cmd *)&desc[0].data[1];
 203         dev_info(dev, "roce_qset_mask: 0x%x\n", bitmap->bit0);
 204         dev_info(dev, "nic_qs_mask: 0x%x\n", bitmap->bit1);
 205         dev_info(dev, "qs_shaping_pass: 0x%x\n", bitmap->bit2);
 206         dev_info(dev, "qs_bp_sts: 0x%x\n", bitmap->bit3);
 207
 208         cmd = HCLGE_OPC_PRI_DFX_STS;
 209         ret = hclge_dbg_cmd_send(hdev, desc, pri_id, 1, cmd);
 210         if (ret)
 211                 goto err_dcb_cmd_send;
 212
 213         bitmap = (struct hclge_dbg_bitmap_cmd *)&desc[0].data[1];
 214         dev_info(dev, "pri_mask: 0x%x\n", bitmap->bit0);
 215         dev_info(dev, "pri_cshaping_pass: 0x%x\n", bitmap->bit1);
 216         dev_info(dev, "pri_pshaping_pass: 0x%x\n", bitmap->bit2);
 217
 218         cmd = HCLGE_OPC_PG_DFX_STS;
 219         ret = hclge_dbg_cmd_send(hdev, desc, pg_id, 1, cmd);
 220         if (ret)
 221                 goto err_dcb_cmd_send;
 222
 223         bitmap = (struct hclge_dbg_bitmap_cmd *)&desc[0].data[1];
 224         dev_info(dev, "pg_mask: 0x%x\n", bitmap->bit0);
 225         dev_info(dev, "pg_cshaping_pass: 0x%x\n", bitmap->bit1);
 226         dev_info(dev, "pg_pshaping_pass: 0x%x\n", bitmap->bit2);
 227
 228         cmd = HCLGE_OPC_PORT_DFX_STS;
 229         ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1, cmd);
 230         if (ret)
 231                 goto err_dcb_cmd_send;
 232
 233         bitmap = (struct hclge_dbg_bitmap_cmd *)&desc[0].data[1];
 234         dev_info(dev, "port_mask: 0x%x\n", bitmap->bit0);
 235         dev_info(dev, "port_shaping_pass: 0x%x\n", bitmap->bit1);
 236
 237         cmd = HCLGE_OPC_SCH_NQ_CNT;
 238         ret = hclge_dbg_cmd_send(hdev, desc, nq_id, 1, cmd);
 239         if (ret)
 240                 goto err_dcb_cmd_send;
 241
 242         dev_info(dev, "sch_nq_cnt: 0x%x\n", le32_to_cpu(desc[0].data[1]));
 243
 244         cmd = HCLGE_OPC_SCH_RQ_CNT;
 245         ret = hclge_dbg_cmd_send(hdev, desc, nq_id, 1, cmd);
 246         if (ret)
 247                 goto err_dcb_cmd_send;
 248
 249         dev_info(dev, "sch_rq_cnt: 0x%x\n", le32_to_cpu(desc[0].data[1]));
 250
 251         cmd = HCLGE_OPC_TM_INTERNAL_STS;
 252         ret = hclge_dbg_cmd_send(hdev, desc, 0, 2, cmd);
 253         if (ret)
 254                 goto err_dcb_cmd_send;
 255
 256         dev_info(dev, "pri_bp: 0x%x\n", le32_to_cpu(desc[0].data[1]));
 257         dev_info(dev, "fifo_dfx_info: 0x%x\n", le32_to_cpu(desc[0].data[2]));
 258         dev_info(dev, "sch_roce_fifo_afull_gap: 0x%x\n",
 259                  le32_to_cpu(desc[0].data[3]));
 260         dev_info(dev, "tx_private_waterline: 0x%x\n",
 261                  le32_to_cpu(desc[0].data[4]));
 262         dev_info(dev, "tm_bypass_en: 0x%x\n", le32_to_cpu(desc[0].data[5]));
 263         dev_info(dev, "SSU_TM_BYPASS_EN: 0x%x\n", le32_to_cpu(desc[1].data[0]));
 264         dev_info(dev, "SSU_RESERVE_CFG: 0x%x\n", le32_to_cpu(desc[1].data[1]));
 265
 266         cmd = HCLGE_OPC_TM_INTERNAL_CNT;
 267         ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1, cmd);
 268         if (ret)
 269                 goto err_dcb_cmd_send;
 270
 271         dev_info(dev, "SCH_NIC_NUM: 0x%x\n", le32_to_cpu(desc[0].data[1]));
 272         dev_info(dev, "SCH_ROCE_NUM: 0x%x\n", le32_to_cpu(desc[0].data[2]));
 273
 274         cmd = HCLGE_OPC_TM_INTERNAL_STS_1;
 275         ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1, cmd);
 276         if (ret)
 277                 goto err_dcb_cmd_send;
 278
 279         dev_info(dev, "TC_MAP_SEL: 0x%x\n", le32_to_cpu(desc[0].data[1]));
 280         dev_info(dev, "IGU_PFC_PRI_EN: 0x%x\n", le32_to_cpu(desc[0].data[2]));
 281         dev_info(dev, "MAC_PFC_PRI_EN: 0x%x\n", le32_to_cpu(desc[0].data[3]));
 282         dev_info(dev, "IGU_PRI_MAP_TC_CFG: 0x%x\n",
 283                  le32_to_cpu(desc[0].data[4]));
 284         dev_info(dev, "IGU_TX_PRI_MAP_TC_CFG: 0x%x\n",
 285                  le32_to_cpu(desc[0].data[5]));
 286         return;
 287
 288 err_dcb_cmd_send:
 289         dev_err(&hdev->pdev->dev,
 290                 "failed to dump dcb dfx, cmd = %#x, ret = %d\n",
 291                 cmd, ret);
 292 }
 293
 294 static void hclge_dbg_dump_reg_cmd(struct hclge_dev *hdev, const char *cmd_buf)
 295 {
 296         struct hclge_dbg_reg_type_info *reg_info;
 297         bool has_dump = false;
 298         int i;
 299
 300         for (i = 0; i < ARRAY_SIZE(hclge_dbg_reg_info); i++) {
 301                 reg_info = &hclge_dbg_reg_info[i];
 302                 if (!strncmp(cmd_buf, reg_info->reg_type,
 303                              strlen(reg_info->reg_type))) {
 304                         hclge_dbg_dump_reg_common(hdev, reg_info, cmd_buf);
 305                         has_dump = true;
 306                 }
 307         }
 308
 309         if (strncmp(cmd_buf, "dcb", 3) == 0) {
 310                 hclge_dbg_dump_dcb(hdev, &cmd_buf[sizeof("dcb")]);
 311                 has_dump = true;
 312         }
 313
 314         if (!has_dump) {
 315                 dev_info(&hdev->pdev->dev, "unknown command\n");
 316                 return;
 317         }
 318 }
 319
 320 static void hclge_title_idx_print(struct hclge_dev *hdev, bool flag, int index,
 321                                   char *title_buf, char *true_buf,
 322                                   char *false_buf)
 323 {
 324         if (flag)
 325                 dev_info(&hdev->pdev->dev, "%s(%d): %s weight: %u\n",
 326                          title_buf, index, true_buf,
 327                          hdev->tm_info.pg_info[0].tc_dwrr[index]);
 328         else
 329                 dev_info(&hdev->pdev->dev, "%s(%d): %s\n", title_buf, index,
 330                          false_buf);
 331 }
 332
 333 static void hclge_dbg_dump_tc(struct hclge_dev *hdev)
 334 {
 335         struct hclge_ets_tc_weight_cmd *ets_weight;
 336         struct hclge_desc desc;
 337         int i, ret;
 338
 339         if (!hnae3_dev_dcb_supported(hdev)) {
 340                 dev_info(&hdev->pdev->dev,
 341                          "Only DCB-supported dev supports tc\n");
 342                 return;
 343         }
 344
 345         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, true);
 346
 347         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 348         if (ret) {
 349                 dev_err(&hdev->pdev->dev, "dump tc fail, ret = %d\n", ret);
 350                 return;
 351         }
 352
 353         ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data;
 354
 355         dev_info(&hdev->pdev->dev, "dump tc: %u tc enabled\n",
 356                  hdev->tm_info.num_tc);
 357         dev_info(&hdev->pdev->dev, "weight_offset: %u\n",
 358                  ets_weight->weight_offset);
 359
 360         for (i = 0; i < HNAE3_MAX_TC; i++)
 361                 hclge_title_idx_print(hdev, ets_weight->tc_weight[i], i,
 362                                       "tc", "no sp mode", "sp mode");
 363 }
 364
 365 static void hclge_dbg_dump_tm_pg(struct hclge_dev *hdev)
 366 {
 367         struct hclge_port_shapping_cmd *port_shap_cfg_cmd;
 368         struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd;
 369         struct hclge_pg_shapping_cmd *pg_shap_cfg_cmd;
 370         enum hclge_opcode_type cmd;
 371         struct hclge_desc desc;
 372         int ret;
 373
 374         cmd = HCLGE_OPC_TM_PG_C_SHAPPING;
 375         hclge_cmd_setup_basic_desc(&desc, cmd, true);
 376         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 377         if (ret)
 378                 goto err_tm_pg_cmd_send;
 379
 380         pg_shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data;
 381         dev_info(&hdev->pdev->dev, "PG_C pg_id: %u\n", pg_shap_cfg_cmd->pg_id);
 382         dev_info(&hdev->pdev->dev, "PG_C pg_shapping: 0x%x\n",
 383                  le32_to_cpu(pg_shap_cfg_cmd->pg_shapping_para));
 384
 385         cmd = HCLGE_OPC_TM_PG_P_SHAPPING;
 386         hclge_cmd_setup_basic_desc(&desc, cmd, true);
 387         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 388         if (ret)
 389                 goto err_tm_pg_cmd_send;
 390
 391         pg_shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data;
 392         dev_info(&hdev->pdev->dev, "PG_P pg_id: %u\n", pg_shap_cfg_cmd->pg_id);
 393         dev_info(&hdev->pdev->dev, "PG_P pg_shapping: 0x%x\n",
 394                  le32_to_cpu(pg_shap_cfg_cmd->pg_shapping_para));
 395
 396         cmd = HCLGE_OPC_TM_PORT_SHAPPING;
 397         hclge_cmd_setup_basic_desc(&desc, cmd, true);
 398         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 399         if (ret)
 400                 goto err_tm_pg_cmd_send;
 401
 402         port_shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data;
 403         dev_info(&hdev->pdev->dev, "PORT port_shapping: 0x%x\n",
 404                  le32_to_cpu(port_shap_cfg_cmd->port_shapping_para));
 405
 406         cmd = HCLGE_OPC_TM_PG_SCH_MODE_CFG;
 407         hclge_cmd_setup_basic_desc(&desc, cmd, true);
 408         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 409         if (ret)
 410                 goto err_tm_pg_cmd_send;
 411
 412         dev_info(&hdev->pdev->dev, "PG_SCH pg_id: %u\n",
 413                  le32_to_cpu(desc.data[0]));
 414
 415         cmd = HCLGE_OPC_TM_PRI_SCH_MODE_CFG;
 416         hclge_cmd_setup_basic_desc(&desc, cmd, true);
 417         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 418         if (ret)
 419                 goto err_tm_pg_cmd_send;
 420
 421         dev_info(&hdev->pdev->dev, "PRI_SCH pri_id: %u\n",
 422                  le32_to_cpu(desc.data[0]));
 423
 424         cmd = HCLGE_OPC_TM_QS_SCH_MODE_CFG;
 425         hclge_cmd_setup_basic_desc(&desc, cmd, true);
 426         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 427         if (ret)
 428                 goto err_tm_pg_cmd_send;
 429
 430         dev_info(&hdev->pdev->dev, "QS_SCH qs_id: %u\n",
 431                  le32_to_cpu(desc.data[0]));
 432
 433         if (!hnae3_dev_dcb_supported(hdev)) {
 434                 dev_info(&hdev->pdev->dev,
 435                          "Only DCB-supported dev supports tm mapping\n");
 436                 return;
 437         }
 438
 439         cmd = HCLGE_OPC_TM_BP_TO_QSET_MAPPING;
 440         hclge_cmd_setup_basic_desc(&desc, cmd, true);
 441         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 442         if (ret)
 443                 goto err_tm_pg_cmd_send;
 444
 445         bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data;
 446         dev_info(&hdev->pdev->dev, "BP_TO_QSET tc_id: %u\n",
 447                  bp_to_qs_map_cmd->tc_id);
 448         dev_info(&hdev->pdev->dev, "BP_TO_QSET qs_group_id: 0x%x\n",
 449                  bp_to_qs_map_cmd->qs_group_id);
 450         dev_info(&hdev->pdev->dev, "BP_TO_QSET qs_bit_map: 0x%x\n",
 451                  le32_to_cpu(bp_to_qs_map_cmd->qs_bit_map));
 452         return;
 453
 454 err_tm_pg_cmd_send:
 455         dev_err(&hdev->pdev->dev, "dump tm_pg fail(0x%x), ret = %d\n",
 456                 cmd, ret);
 457 }
 458
 459 static void hclge_dbg_dump_tm(struct hclge_dev *hdev)
 460 {
 461         struct hclge_priority_weight_cmd *priority_weight;
 462         struct hclge_pg_to_pri_link_cmd *pg_to_pri_map;
 463         struct hclge_qs_to_pri_link_cmd *qs_to_pri_map;
 464         struct hclge_nq_to_qs_link_cmd *nq_to_qs_map;
 465         struct hclge_pri_shapping_cmd *shap_cfg_cmd;
 466         struct hclge_pg_weight_cmd *pg_weight;
 467         struct hclge_qs_weight_cmd *qs_weight;
 468         enum hclge_opcode_type cmd;
 469         struct hclge_desc desc;
 470         int ret;
 471
 472         cmd = HCLGE_OPC_TM_PG_TO_PRI_LINK;
 473         hclge_cmd_setup_basic_desc(&desc, cmd, true);
 474         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 475         if (ret)
 476                 goto err_tm_cmd_send;
 477
 478         pg_to_pri_map = (struct hclge_pg_to_pri_link_cmd *)desc.data;
 479         dev_info(&hdev->pdev->dev, "dump tm\n");
 480         dev_info(&hdev->pdev->dev, "PG_TO_PRI gp_id: %u\n",
 481                  pg_to_pri_map->pg_id);
 482         dev_info(&hdev->pdev->dev, "PG_TO_PRI map: 0x%x\n",
 483                  pg_to_pri_map->pri_bit_map);
 484
 485         cmd = HCLGE_OPC_TM_QS_TO_PRI_LINK;
 486         hclge_cmd_setup_basic_desc(&desc, cmd, true);
 487         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 488         if (ret)
 489                 goto err_tm_cmd_send;
 490
 491         qs_to_pri_map = (struct hclge_qs_to_pri_link_cmd *)desc.data;
 492         dev_info(&hdev->pdev->dev, "QS_TO_PRI qs_id: %u\n",
 493                  le16_to_cpu(qs_to_pri_map->qs_id));
 494         dev_info(&hdev->pdev->dev, "QS_TO_PRI priority: %u\n",
 495                  qs_to_pri_map->priority);
 496         dev_info(&hdev->pdev->dev, "QS_TO_PRI link_vld: %u\n",
 497                  qs_to_pri_map->link_vld);
 498
 499         cmd = HCLGE_OPC_TM_NQ_TO_QS_LINK;
 500         hclge_cmd_setup_basic_desc(&desc, cmd, true);
 501         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 502         if (ret)
 503                 goto err_tm_cmd_send;
 504
 505         nq_to_qs_map = (struct hclge_nq_to_qs_link_cmd *)desc.data;
 506         dev_info(&hdev->pdev->dev, "NQ_TO_QS nq_id: %u\n",
 507                  le16_to_cpu(nq_to_qs_map->nq_id));
 508         dev_info(&hdev->pdev->dev, "NQ_TO_QS qset_id: 0x%x\n",
 509                  le16_to_cpu(nq_to_qs_map->qset_id));
 510
 511         cmd = HCLGE_OPC_TM_PG_WEIGHT;
 512         hclge_cmd_setup_basic_desc(&desc, cmd, true);
 513         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 514         if (ret)
 515                 goto err_tm_cmd_send;
 516
 517         pg_weight = (struct hclge_pg_weight_cmd *)desc.data;
 518         dev_info(&hdev->pdev->dev, "PG pg_id: %u\n", pg_weight->pg_id);
 519         dev_info(&hdev->pdev->dev, "PG dwrr: %u\n", pg_weight->dwrr);
 520
 521         cmd = HCLGE_OPC_TM_QS_WEIGHT;
 522         hclge_cmd_setup_basic_desc(&desc, cmd, true);
 523         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 524         if (ret)
 525                 goto err_tm_cmd_send;
 526
 527         qs_weight = (struct hclge_qs_weight_cmd *)desc.data;
 528         dev_info(&hdev->pdev->dev, "QS qs_id: %u\n",
 529                  le16_to_cpu(qs_weight->qs_id));
 530         dev_info(&hdev->pdev->dev, "QS dwrr: %u\n", qs_weight->dwrr);
 531
 532         cmd = HCLGE_OPC_TM_PRI_WEIGHT;
 533         hclge_cmd_setup_basic_desc(&desc, cmd, true);
 534         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 535         if (ret)
 536                 goto err_tm_cmd_send;
 537
 538         priority_weight = (struct hclge_priority_weight_cmd *)desc.data;
 539         dev_info(&hdev->pdev->dev, "PRI pri_id: %u\n", priority_weight->pri_id);
 540         dev_info(&hdev->pdev->dev, "PRI dwrr: %u\n", priority_weight->dwrr);
 541
 542         cmd = HCLGE_OPC_TM_PRI_C_SHAPPING;
 543         hclge_cmd_setup_basic_desc(&desc, cmd, true);
 544         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 545         if (ret)
 546                 goto err_tm_cmd_send;
 547
 548         shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data;
 549         dev_info(&hdev->pdev->dev, "PRI_C pri_id: %u\n", shap_cfg_cmd->pri_id);
 550         dev_info(&hdev->pdev->dev, "PRI_C pri_shapping: 0x%x\n",
 551                  le32_to_cpu(shap_cfg_cmd->pri_shapping_para));
 552
 553         cmd = HCLGE_OPC_TM_PRI_P_SHAPPING;
 554         hclge_cmd_setup_basic_desc(&desc, cmd, true);
 555         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 556         if (ret)
 557                 goto err_tm_cmd_send;
 558
 559         shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data;
 560         dev_info(&hdev->pdev->dev, "PRI_P pri_id: %u\n", shap_cfg_cmd->pri_id);
 561         dev_info(&hdev->pdev->dev, "PRI_P pri_shapping: 0x%x\n",
 562                  le32_to_cpu(shap_cfg_cmd->pri_shapping_para));
 563
 564         hclge_dbg_dump_tm_pg(hdev);
 565
 566         return;
 567
 568 err_tm_cmd_send:
 569         dev_err(&hdev->pdev->dev, "dump tm fail(0x%x), ret = %d\n",
 570                 cmd, ret);
 571 }
 572
 573 static void hclge_dbg_dump_tm_map(struct hclge_dev *hdev,
 574                                   const char *cmd_buf)
 575 {
 576         struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd;
 577         struct hclge_nq_to_qs_link_cmd *nq_to_qs_map;
 578         struct hclge_qs_to_pri_link_cmd *map;
 579         struct hclge_tqp_tx_queue_tc_cmd *tc;
 580         enum hclge_opcode_type cmd;
 581         struct hclge_desc desc;
 582         int queue_id, group_id;
 583         u32 qset_maping[32];
 584         int tc_id, qset_id;
 585         int pri_id, ret;
 586         u32 i;
 587
 588         ret = kstrtouint(cmd_buf, 0, &queue_id);
 589         queue_id = (ret != 0) ? 0 : queue_id;
 590
 591         cmd = HCLGE_OPC_TM_NQ_TO_QS_LINK;
 592         nq_to_qs_map = (struct hclge_nq_to_qs_link_cmd *)desc.data;
 593         hclge_cmd_setup_basic_desc(&desc, cmd, true);
 594         nq_to_qs_map->nq_id = cpu_to_le16(queue_id);
 595         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 596         if (ret)
 597                 goto err_tm_map_cmd_send;
 598         qset_id = le16_to_cpu(nq_to_qs_map->qset_id) & 0x3FF;
 599
 600         cmd = HCLGE_OPC_TM_QS_TO_PRI_LINK;
 601         map = (struct hclge_qs_to_pri_link_cmd *)desc.data;
 602         hclge_cmd_setup_basic_desc(&desc, cmd, true);
 603         map->qs_id = cpu_to_le16(qset_id);
 604         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 605         if (ret)
 606                 goto err_tm_map_cmd_send;
 607         pri_id = map->priority;
 608
 609         cmd = HCLGE_OPC_TQP_TX_QUEUE_TC;
 610         tc = (struct hclge_tqp_tx_queue_tc_cmd *)desc.data;
 611         hclge_cmd_setup_basic_desc(&desc, cmd, true);
 612         tc->queue_id = cpu_to_le16(queue_id);
 613         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 614         if (ret)
 615                 goto err_tm_map_cmd_send;
 616         tc_id = tc->tc_id & 0x7;
 617
 618         dev_info(&hdev->pdev->dev, "queue_id | qset_id | pri_id | tc_id\n");
 619         dev_info(&hdev->pdev->dev, "%04d     | %04d    | %02d     | %02d\n",
 620                  queue_id, qset_id, pri_id, tc_id);
 621
 622         if (!hnae3_dev_dcb_supported(hdev)) {
 623                 dev_info(&hdev->pdev->dev,
 624                          "Only DCB-supported dev supports tm mapping\n");
 625                 return;
 626         }
 627
 628         cmd = HCLGE_OPC_TM_BP_TO_QSET_MAPPING;
 629         bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data;
 630         for (group_id = 0; group_id < 32; group_id++) {
 631                 hclge_cmd_setup_basic_desc(&desc, cmd, true);
 632                 bp_to_qs_map_cmd->tc_id = tc_id;
 633                 bp_to_qs_map_cmd->qs_group_id = group_id;
 634                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 635                 if (ret)
 636                         goto err_tm_map_cmd_send;
 637
 638                 qset_maping[group_id] =
 639                         le32_to_cpu(bp_to_qs_map_cmd->qs_bit_map);
 640         }
 641
 642         dev_info(&hdev->pdev->dev, "index | tm bp qset maping:\n");
 643
 644         i = 0;
 645         for (group_id = 0; group_id < 4; group_id++) {
 646                 dev_info(&hdev->pdev->dev,
 647                          "%04d  | %08x:%08x:%08x:%08x:%08x:%08x:%08x:%08x\n",
 648                          group_id * 256, qset_maping[(u32)(i + 7)],
 649                          qset_maping[(u32)(i + 6)], qset_maping[(u32)(i + 5)],
 650                          qset_maping[(u32)(i + 4)], qset_maping[(u32)(i + 3)],
 651                          qset_maping[(u32)(i + 2)], qset_maping[(u32)(i + 1)],
 652                          qset_maping[i]);
 653                 i += 8;
 654         }
 655
 656         return;
 657
 658 err_tm_map_cmd_send:
 659         dev_err(&hdev->pdev->dev, "dump tqp map fail(0x%x), ret = %d\n",
 660                 cmd, ret);
 661 }
 662
 663 static void hclge_dbg_dump_qos_pause_cfg(struct hclge_dev *hdev)
 664 {
 665         struct hclge_cfg_pause_param_cmd *pause_param;
 666         struct hclge_desc desc;
 667         int ret;
 668
 669         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true);
 670
 671         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 672         if (ret) {
 673                 dev_err(&hdev->pdev->dev, "dump checksum fail, ret = %d\n",
 674                         ret);
 675                 return;
 676         }
 677
 678         pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data;
 679         dev_info(&hdev->pdev->dev, "dump qos pause cfg\n");
 680         dev_info(&hdev->pdev->dev, "pause_trans_gap: 0x%x\n",
 681                  pause_param->pause_trans_gap);
 682         dev_info(&hdev->pdev->dev, "pause_trans_time: 0x%x\n",
 683                  le16_to_cpu(pause_param->pause_trans_time));
 684 }
 685
 686 static void hclge_dbg_dump_qos_pri_map(struct hclge_dev *hdev)
 687 {
 688         struct hclge_qos_pri_map_cmd *pri_map;
 689         struct hclge_desc desc;
 690         int ret;
 691
 692         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, true);
 693
 694         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 695         if (ret) {
 696                 dev_err(&hdev->pdev->dev,
 697                         "dump qos pri map fail, ret = %d\n", ret);
 698                 return;
 699         }
 700
 701         pri_map = (struct hclge_qos_pri_map_cmd *)desc.data;
 702         dev_info(&hdev->pdev->dev, "dump qos pri map\n");
 703         dev_info(&hdev->pdev->dev, "vlan_to_pri: 0x%x\n", pri_map->vlan_pri);
 704         dev_info(&hdev->pdev->dev, "pri_0_to_tc: 0x%x\n", pri_map->pri0_tc);
 705         dev_info(&hdev->pdev->dev, "pri_1_to_tc: 0x%x\n", pri_map->pri1_tc);
 706         dev_info(&hdev->pdev->dev, "pri_2_to_tc: 0x%x\n", pri_map->pri2_tc);
 707         dev_info(&hdev->pdev->dev, "pri_3_to_tc: 0x%x\n", pri_map->pri3_tc);
 708         dev_info(&hdev->pdev->dev, "pri_4_to_tc: 0x%x\n", pri_map->pri4_tc);
 709         dev_info(&hdev->pdev->dev, "pri_5_to_tc: 0x%x\n", pri_map->pri5_tc);
 710         dev_info(&hdev->pdev->dev, "pri_6_to_tc: 0x%x\n", pri_map->pri6_tc);
 711         dev_info(&hdev->pdev->dev, "pri_7_to_tc: 0x%x\n", pri_map->pri7_tc);
 712 }
 713
 714 static void hclge_dbg_dump_qos_buf_cfg(struct hclge_dev *hdev)
 715 {
 716         struct hclge_tx_buff_alloc_cmd *tx_buf_cmd;
 717         struct hclge_rx_priv_buff_cmd *rx_buf_cmd;
 718         struct hclge_rx_priv_wl_buf *rx_priv_wl;
 719         struct hclge_rx_com_wl *rx_packet_cnt;
 720         struct hclge_rx_com_thrd *rx_com_thrd;
 721         struct hclge_rx_com_wl *rx_com_wl;
 722         enum hclge_opcode_type cmd;
 723         struct hclge_desc desc[2];
 724         int i, ret;
 725
 726         cmd = HCLGE_OPC_TX_BUFF_ALLOC;
 727         hclge_cmd_setup_basic_desc(desc, cmd, true);
 728         ret = hclge_cmd_send(&hdev->hw, desc, 1);
 729         if (ret)
 730                 goto err_qos_cmd_send;
 731
 732         dev_info(&hdev->pdev->dev, "dump qos buf cfg\n");
 733
 734         tx_buf_cmd = (struct hclge_tx_buff_alloc_cmd *)desc[0].data;
 735         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
 736                 dev_info(&hdev->pdev->dev, "tx_packet_buf_tc_%d: 0x%x\n", i,
 737                          le16_to_cpu(tx_buf_cmd->tx_pkt_buff[i]));
 738
 739         cmd = HCLGE_OPC_RX_PRIV_BUFF_ALLOC;
 740         hclge_cmd_setup_basic_desc(desc, cmd, true);
 741         ret = hclge_cmd_send(&hdev->hw, desc, 1);
 742         if (ret)
 743                 goto err_qos_cmd_send;
 744
 745         dev_info(&hdev->pdev->dev, "\n");
 746         rx_buf_cmd = (struct hclge_rx_priv_buff_cmd *)desc[0].data;
 747         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
 748                 dev_info(&hdev->pdev->dev, "rx_packet_buf_tc_%d: 0x%x\n", i,
 749                          le16_to_cpu(rx_buf_cmd->buf_num[i]));
 750
 751         dev_info(&hdev->pdev->dev, "rx_share_buf: 0x%x\n",
 752                  le16_to_cpu(rx_buf_cmd->shared_buf));
 753
 754         cmd = HCLGE_OPC_RX_COM_WL_ALLOC;
 755         hclge_cmd_setup_basic_desc(desc, cmd, true);
 756         ret = hclge_cmd_send(&hdev->hw, desc, 1);
 757         if (ret)
 758                 goto err_qos_cmd_send;
 759
 760         rx_com_wl = (struct hclge_rx_com_wl *)desc[0].data;
 761         dev_info(&hdev->pdev->dev, "\n");
 762         dev_info(&hdev->pdev->dev, "rx_com_wl: high: 0x%x, low: 0x%x\n",
 763                  le16_to_cpu(rx_com_wl->com_wl.high),
 764                  le16_to_cpu(rx_com_wl->com_wl.low));
 765
 766         cmd = HCLGE_OPC_RX_GBL_PKT_CNT;
 767         hclge_cmd_setup_basic_desc(desc, cmd, true);
 768         ret = hclge_cmd_send(&hdev->hw, desc, 1);
 769         if (ret)
 770                 goto err_qos_cmd_send;
 771
 772         rx_packet_cnt = (struct hclge_rx_com_wl *)desc[0].data;
 773         dev_info(&hdev->pdev->dev,
 774                  "rx_global_packet_cnt: high: 0x%x, low: 0x%x\n",
 775                  le16_to_cpu(rx_packet_cnt->com_wl.high),
 776                  le16_to_cpu(rx_packet_cnt->com_wl.low));
 777         dev_info(&hdev->pdev->dev, "\n");
 778
 779         if (!hnae3_dev_dcb_supported(hdev)) {
 780                 dev_info(&hdev->pdev->dev,
 781                          "Only DCB-supported dev supports rx priv wl\n");
 782                 return;
 783         }
 784         cmd = HCLGE_OPC_RX_PRIV_WL_ALLOC;
 785         hclge_cmd_setup_basic_desc(&desc[0], cmd, true);
 786         desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
 787         hclge_cmd_setup_basic_desc(&desc[1], cmd, true);
 788         ret = hclge_cmd_send(&hdev->hw, desc, 2);
 789         if (ret)
 790                 goto err_qos_cmd_send;
 791
 792         rx_priv_wl = (struct hclge_rx_priv_wl_buf *)desc[0].data;
 793         for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++)
 794                 dev_info(&hdev->pdev->dev,
 795                          "rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n", i,
 796                          le16_to_cpu(rx_priv_wl->tc_wl[i].high),
 797                          le16_to_cpu(rx_priv_wl->tc_wl[i].low));
 798
 799         rx_priv_wl = (struct hclge_rx_priv_wl_buf *)desc[1].data;
 800         for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++)
 801                 dev_info(&hdev->pdev->dev,
 802                          "rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n",
 803                          i + HCLGE_TC_NUM_ONE_DESC,
 804                          le16_to_cpu(rx_priv_wl->tc_wl[i].high),
 805                          le16_to_cpu(rx_priv_wl->tc_wl[i].low));
 806
 807         cmd = HCLGE_OPC_RX_COM_THRD_ALLOC;
 808         hclge_cmd_setup_basic_desc(&desc[0], cmd, true);
 809         desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
 810         hclge_cmd_setup_basic_desc(&desc[1], cmd, true);
 811         ret = hclge_cmd_send(&hdev->hw, desc, 2);
 812         if (ret)
 813                 goto err_qos_cmd_send;
 814
 815         dev_info(&hdev->pdev->dev, "\n");
 816         rx_com_thrd = (struct hclge_rx_com_thrd *)desc[0].data;
 817         for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++)
 818                 dev_info(&hdev->pdev->dev,
 819                          "rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n", i,
 820                          le16_to_cpu(rx_com_thrd->com_thrd[i].high),
 821                          le16_to_cpu(rx_com_thrd->com_thrd[i].low));
 822
 823         rx_com_thrd = (struct hclge_rx_com_thrd *)desc[1].data;
 824         for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++)
 825                 dev_info(&hdev->pdev->dev,
 826                          "rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n",
 827                          i + HCLGE_TC_NUM_ONE_DESC,
 828                          le16_to_cpu(rx_com_thrd->com_thrd[i].high),
 829                          le16_to_cpu(rx_com_thrd->com_thrd[i].low));
 830         return;
 831
 832 err_qos_cmd_send:
 833         dev_err(&hdev->pdev->dev,
 834                 "dump qos buf cfg fail(0x%x), ret = %d\n", cmd, ret);
 835 }
 836
 837 static void hclge_dbg_dump_mng_table(struct hclge_dev *hdev)
 838 {
 839         struct hclge_mac_ethertype_idx_rd_cmd *req0;
 840         char printf_buf[HCLGE_DBG_BUF_LEN];
 841         struct hclge_desc desc;
 842         u32 msg_egress_port;
 843         int ret, i;
 844
 845         dev_info(&hdev->pdev->dev, "mng tab:\n");
 846         memset(printf_buf, 0, HCLGE_DBG_BUF_LEN);
 847         strncat(printf_buf,
 848                 "entry|mac_addr         |mask|ether|mask|vlan|mask",
 849                 HCLGE_DBG_BUF_LEN - 1);
 850         strncat(printf_buf + strlen(printf_buf),
 851                 "|i_map|i_dir|e_type|pf_id|vf_id|q_id|drop\n",
 852                 HCLGE_DBG_BUF_LEN - strlen(printf_buf) - 1);
 853
 854         dev_info(&hdev->pdev->dev, "%s", printf_buf);
 855
 856         for (i = 0; i < HCLGE_DBG_MNG_TBL_MAX; i++) {
 857                 hclge_cmd_setup_basic_desc(&desc, HCLGE_MAC_ETHERTYPE_IDX_RD,
 858                                            true);
 859                 req0 = (struct hclge_mac_ethertype_idx_rd_cmd *)&desc.data;
 860                 req0->index = cpu_to_le16(i);
 861
 862                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 863                 if (ret) {
 864                         dev_err(&hdev->pdev->dev,
 865                                 "call hclge_cmd_send fail, ret = %d\n", ret);
 866                         return;
 867                 }
 868
 869                 if (!req0->resp_code)
 870                         continue;
 871
 872                 memset(printf_buf, 0, HCLGE_DBG_BUF_LEN);
 873                 snprintf(printf_buf, HCLGE_DBG_BUF_LEN,
 874                          "%02u   |%02x:%02x:%02x:%02x:%02x:%02x|",
 875                          le16_to_cpu(req0->index),
 876                          req0->mac_addr[0], req0->mac_addr[1],
 877                          req0->mac_addr[2], req0->mac_addr[3],
 878                          req0->mac_addr[4], req0->mac_addr[5]);
 879
 880                 snprintf(printf_buf + strlen(printf_buf),
 881                          HCLGE_DBG_BUF_LEN - strlen(printf_buf),
 882                          "%x   |%04x |%x   |%04x|%x   |%02x   |%02x   |",
 883                          !!(req0->flags & HCLGE_DBG_MNG_MAC_MASK_B),
 884                          le16_to_cpu(req0->ethter_type),
 885                          !!(req0->flags & HCLGE_DBG_MNG_ETHER_MASK_B),
 886                          le16_to_cpu(req0->vlan_tag) & HCLGE_DBG_MNG_VLAN_TAG,
 887                          !!(req0->flags & HCLGE_DBG_MNG_VLAN_MASK_B),
 888                          req0->i_port_bitmap, req0->i_port_direction);
 889
 890                 msg_egress_port = le16_to_cpu(req0->egress_port);
 891                 snprintf(printf_buf + strlen(printf_buf),
 892                          HCLGE_DBG_BUF_LEN - strlen(printf_buf),
 893                          "%x     |%x    |%02x   |%04x|%x\n",
 894                          !!(msg_egress_port & HCLGE_DBG_MNG_E_TYPE_B),
 895                          msg_egress_port & HCLGE_DBG_MNG_PF_ID,
 896                          (msg_egress_port >> 3) & HCLGE_DBG_MNG_VF_ID,
 897                          le16_to_cpu(req0->egress_queue),
 898                          !!(msg_egress_port & HCLGE_DBG_MNG_DROP_B));
 899
 900                 dev_info(&hdev->pdev->dev, "%s", printf_buf);
 901         }
 902 }
 903
 904 static int hclge_dbg_fd_tcam_read(struct hclge_dev *hdev, u8 stage,
 905                                   bool sel_x, u32 loc)
 906 {
 907         struct hclge_fd_tcam_config_1_cmd *req1;
 908         struct hclge_fd_tcam_config_2_cmd *req2;
 909         struct hclge_fd_tcam_config_3_cmd *req3;
 910         struct hclge_desc desc[3];
 911         int ret, i;
 912         u32 *req;
 913
 914         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, true);
 915         desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
 916         hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, true);
 917         desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
 918         hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, true);
 919
 920         req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
 921         req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
 922         req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
 923
 924         req1->stage  = stage;
 925         req1->xy_sel = sel_x ? 1 : 0;
 926         req1->index  = cpu_to_le32(loc);
 927
 928         ret = hclge_cmd_send(&hdev->hw, desc, 3);
 929         if (ret)
 930                 return ret;
 931
 932         dev_info(&hdev->pdev->dev, " read result tcam key %s(%u):\n",
 933                  sel_x ? "x" : "y", loc);
 934
 935         /* tcam_data0 ~ tcam_data1 */
 936         req = (u32 *)req1->tcam_data;
 937         for (i = 0; i < 2; i++)
 938                 dev_info(&hdev->pdev->dev, "%08x\n", *req++);
 939
 940         /* tcam_data2 ~ tcam_data7 */
 941         req = (u32 *)req2->tcam_data;
 942         for (i = 0; i < 6; i++)
 943                 dev_info(&hdev->pdev->dev, "%08x\n", *req++);
 944
 945         /* tcam_data8 ~ tcam_data12 */
 946         req = (u32 *)req3->tcam_data;
 947         for (i = 0; i < 5; i++)
 948                 dev_info(&hdev->pdev->dev, "%08x\n", *req++);
 949
 950         return ret;
 951 }
 952
 953 static int hclge_dbg_get_rules_location(struct hclge_dev *hdev, u16 *rule_locs)
 954 {
 955         struct hclge_fd_rule *rule;
 956         struct hlist_node *node;
 957         int cnt = 0;
 958
 959         spin_lock_bh(&hdev->fd_rule_lock);
 960         hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
 961                 rule_locs[cnt] = rule->location;
 962                 cnt++;
 963         }
 964         spin_unlock_bh(&hdev->fd_rule_lock);
 965
 966         if (cnt != hdev->hclge_fd_rule_num)
 967                 return -EINVAL;
 968
 969         return cnt;
 970 }
 971
 972 static void hclge_dbg_fd_tcam(struct hclge_dev *hdev)
 973 {
 974         int i, ret, rule_cnt;
 975         u16 *rule_locs;
 976
 977         if (!hnae3_dev_fd_supported(hdev)) {
 978                 dev_err(&hdev->pdev->dev,
 979                         "Only FD-supported dev supports dump fd tcam\n");
 980                 return;
 981         }
 982
 983         if (!hdev->hclge_fd_rule_num ||
 984             !hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
 985                 return;
 986
 987         rule_locs = kcalloc(hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1],
 988                             sizeof(u16), GFP_KERNEL);
 989         if (!rule_locs)
 990                 return;
 991
 992         rule_cnt = hclge_dbg_get_rules_location(hdev, rule_locs);
 993         if (rule_cnt <= 0) {
 994                 dev_err(&hdev->pdev->dev,
 995                         "failed to get rule number, ret = %d\n", rule_cnt);
 996                 kfree(rule_locs);
 997                 return;
 998         }
 999
1000         for (i = 0; i < rule_cnt; i++) {
1001                 ret = hclge_dbg_fd_tcam_read(hdev, 0, true, rule_locs[i]);
1002                 if (ret) {
1003                         dev_err(&hdev->pdev->dev,
1004                                 "failed to get fd tcam key x, ret = %d\n", ret);
1005                         kfree(rule_locs);
1006                         return;
1007                 }
1008
1009                 ret = hclge_dbg_fd_tcam_read(hdev, 0, false, rule_locs[i]);
1010                 if (ret) {
1011                         dev_err(&hdev->pdev->dev,
1012                                 "failed to get fd tcam key y, ret = %d\n", ret);
1013                         kfree(rule_locs);
1014                         return;
1015                 }
1016         }
1017
1018         kfree(rule_locs);
1019 }
1020
1021 void hclge_dbg_dump_rst_info(struct hclge_dev *hdev)
1022 {
1023         dev_info(&hdev->pdev->dev, "PF reset count: %u\n",
1024                  hdev->rst_stats.pf_rst_cnt);
1025         dev_info(&hdev->pdev->dev, "FLR reset count: %u\n",
1026                  hdev->rst_stats.flr_rst_cnt);
1027         dev_info(&hdev->pdev->dev, "GLOBAL reset count: %u\n",
1028                  hdev->rst_stats.global_rst_cnt);
1029         dev_info(&hdev->pdev->dev, "IMP reset count: %u\n",
1030                  hdev->rst_stats.imp_rst_cnt);
1031         dev_info(&hdev->pdev->dev, "reset done count: %u\n",
1032                  hdev->rst_stats.reset_done_cnt);
1033         dev_info(&hdev->pdev->dev, "HW reset done count: %u\n",
1034                  hdev->rst_stats.hw_reset_done_cnt);
1035         dev_info(&hdev->pdev->dev, "reset count: %u\n",
1036                  hdev->rst_stats.reset_cnt);
1037         dev_info(&hdev->pdev->dev, "reset fail count: %u\n",
1038                  hdev->rst_stats.reset_fail_cnt);
1039         dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n",
1040                  hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_REG_BASE));
1041         dev_info(&hdev->pdev->dev, "reset interrupt source: 0x%x\n",
1042                  hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG));
1043         dev_info(&hdev->pdev->dev, "reset interrupt status: 0x%x\n",
1044                  hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS));
1045         dev_info(&hdev->pdev->dev, "hardware reset status: 0x%x\n",
1046                  hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG));
1047         dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n",
1048                  hclge_read_dev(&hdev->hw, HCLGE_NIC_CSQ_DEPTH_REG));
1049         dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n",
1050                  hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING));
1051         dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state);
1052 }
1053
1054 static void hclge_dbg_dump_serv_info(struct hclge_dev *hdev)
1055 {
1056         dev_info(&hdev->pdev->dev, "last_serv_processed: %lu\n",
1057                  hdev->last_serv_processed);
1058         dev_info(&hdev->pdev->dev, "last_serv_cnt: %lu\n",
1059                  hdev->serv_processed_cnt);
1060 }
1061
1062 static void hclge_dbg_get_m7_stats_info(struct hclge_dev *hdev)
1063 {
1064         struct hclge_desc *desc_src, *desc_tmp;
1065         struct hclge_get_m7_bd_cmd *req;
1066         struct hclge_desc desc;
1067         u32 bd_num, buf_len;
1068         int ret, i;
1069
1070         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_M7_STATS_BD, true);
1071
1072         req = (struct hclge_get_m7_bd_cmd *)desc.data;
1073         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1074         if (ret) {
1075                 dev_err(&hdev->pdev->dev,
1076                         "get firmware statistics bd number failed, ret = %d\n",
1077                         ret);
1078                 return;
1079         }
1080
1081         bd_num = le32_to_cpu(req->bd_num);
1082
1083         buf_len  = sizeof(struct hclge_desc) * bd_num;
1084         desc_src = kzalloc(buf_len, GFP_KERNEL);
1085         if (!desc_src) {
1086                 dev_err(&hdev->pdev->dev,
1087                         "allocate desc for get_m7_stats failed\n");
1088                 return;
1089         }
1090
1091         desc_tmp = desc_src;
1092         ret  = hclge_dbg_cmd_send(hdev, desc_tmp, 0, bd_num,
1093                                   HCLGE_OPC_M7_STATS_INFO);
1094         if (ret) {
1095                 kfree(desc_src);
1096                 dev_err(&hdev->pdev->dev,
1097                         "get firmware statistics failed, ret = %d\n", ret);
1098                 return;
1099         }
1100
1101         for (i = 0; i < bd_num; i++) {
1102                 dev_info(&hdev->pdev->dev, "0x%08x  0x%08x  0x%08x\n",
1103                          le32_to_cpu(desc_tmp->data[0]),
1104                          le32_to_cpu(desc_tmp->data[1]),
1105                          le32_to_cpu(desc_tmp->data[2]));
1106                 dev_info(&hdev->pdev->dev, "0x%08x  0x%08x  0x%08x\n",
1107                          le32_to_cpu(desc_tmp->data[3]),
1108                          le32_to_cpu(desc_tmp->data[4]),
1109                          le32_to_cpu(desc_tmp->data[5]));
1110
1111                 desc_tmp++;
1112         }
1113
1114         kfree(desc_src);
1115 }
1116
1117 #define HCLGE_CMD_NCL_CONFIG_BD_NUM     5
1118
1119 static void hclge_ncl_config_data_print(struct hclge_dev *hdev,
1120                                         struct hclge_desc *desc, int *offset,
1121                                         int *length)
1122 {
1123 #define HCLGE_CMD_DATA_NUM              6
1124
1125         int i;
1126         int j;
1127
1128         for (i = 0; i < HCLGE_CMD_NCL_CONFIG_BD_NUM; i++) {
1129                 for (j = 0; j < HCLGE_CMD_DATA_NUM; j++) {
1130                         if (i == 0 && j == 0)
1131                                 continue;
1132
1133                         dev_info(&hdev->pdev->dev, "0x%04x | 0x%08x\n",
1134                                  *offset,
1135                                  le32_to_cpu(desc[i].data[j]));
1136                         *offset += sizeof(u32);
1137                         *length -= sizeof(u32);
1138                         if (*length <= 0)
1139                                 return;
1140                 }
1141         }
1142 }
1143
1144 /* hclge_dbg_dump_ncl_config: print specified range of NCL_CONFIG file
1145  * @hdev: pointer to struct hclge_dev
1146  * @cmd_buf: string that contains offset and length
1147  */
1148 static void hclge_dbg_dump_ncl_config(struct hclge_dev *hdev,
1149                                       const char *cmd_buf)
1150 {
1151 #define HCLGE_MAX_NCL_CONFIG_OFFSET     4096
1152 #define HCLGE_NCL_CONFIG_LENGTH_IN_EACH_CMD     (20 + 24 * 4)
1153
1154         struct hclge_desc desc[HCLGE_CMD_NCL_CONFIG_BD_NUM];
1155         int bd_num = HCLGE_CMD_NCL_CONFIG_BD_NUM;
1156         int offset;
1157         int length;
1158         int data0;
1159         int ret;
1160
1161         ret = sscanf(cmd_buf, "%x %x", &offset, &length);
1162         if (ret != 2 || offset >= HCLGE_MAX_NCL_CONFIG_OFFSET ||
1163             length > HCLGE_MAX_NCL_CONFIG_OFFSET - offset) {
1164                 dev_err(&hdev->pdev->dev, "Invalid offset or length.\n");
1165                 return;
1166         }
1167         if (offset < 0 || length <= 0) {
1168                 dev_err(&hdev->pdev->dev, "Non-positive offset or length.\n");
1169                 return;
1170         }
1171
1172         dev_info(&hdev->pdev->dev, "offset |    data\n");
1173
1174         while (length > 0) {
1175                 data0 = offset;
1176                 if (length >= HCLGE_NCL_CONFIG_LENGTH_IN_EACH_CMD)
1177                         data0 |= HCLGE_NCL_CONFIG_LENGTH_IN_EACH_CMD << 16;
1178                 else
1179                         data0 |= length << 16;
1180                 ret = hclge_dbg_cmd_send(hdev, desc, data0, bd_num,
1181                                          HCLGE_OPC_QUERY_NCL_CONFIG);
1182                 if (ret)
1183                         return;
1184
1185                 hclge_ncl_config_data_print(hdev, desc, &offset, &length);
1186         }
1187 }
1188
1189 static void hclge_dbg_dump_loopback(struct hclge_dev *hdev,
1190                                     const char *cmd_buf)
1191 {
1192         struct phy_device *phydev = hdev->hw.mac.phydev;
1193         struct hclge_config_mac_mode_cmd *req_app;
1194         struct hclge_serdes_lb_cmd *req_serdes;
1195         struct hclge_desc desc;
1196         u8 loopback_en;
1197         int ret;
1198
1199         req_app = (struct hclge_config_mac_mode_cmd *)desc.data;
1200         req_serdes = (struct hclge_serdes_lb_cmd *)desc.data;
1201
1202         dev_info(&hdev->pdev->dev, "mac id: %u\n", hdev->hw.mac.mac_id);
1203
1204         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
1205         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1206         if (ret) {
1207                 dev_err(&hdev->pdev->dev,
1208                         "failed to dump app loopback status, ret = %d\n", ret);
1209                 return;
1210         }
1211
1212         loopback_en = hnae3_get_bit(le32_to_cpu(req_app->txrx_pad_fcs_loop_en),
1213                                     HCLGE_MAC_APP_LP_B);
1214         dev_info(&hdev->pdev->dev, "app loopback: %s\n",
1215                  loopback_en ? "on" : "off");
1216
1217         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, true);
1218         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1219         if (ret) {
1220                 dev_err(&hdev->pdev->dev,
1221                         "failed to dump serdes loopback status, ret = %d\n",
1222                         ret);
1223                 return;
1224         }
1225
1226         loopback_en = req_serdes->enable & HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
1227         dev_info(&hdev->pdev->dev, "serdes serial loopback: %s\n",
1228                  loopback_en ? "on" : "off");
1229
1230         loopback_en = req_serdes->enable &
1231                         HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B;
1232         dev_info(&hdev->pdev->dev, "serdes parallel loopback: %s\n",
1233                  loopback_en ? "on" : "off");
1234
1235         if (phydev)
1236                 dev_info(&hdev->pdev->dev, "phy loopback: %s\n",
1237                          phydev->loopback_enabled ? "on" : "off");
1238 }
1239
1240 /* hclge_dbg_dump_mac_tnl_status: print message about mac tnl interrupt
1241  * @hdev: pointer to struct hclge_dev
1242  */
1243 static void hclge_dbg_dump_mac_tnl_status(struct hclge_dev *hdev)
1244 {
1245 #define HCLGE_BILLION_NANO_SECONDS 1000000000
1246
1247         struct hclge_mac_tnl_stats stats;
1248         unsigned long rem_nsec;
1249
1250         dev_info(&hdev->pdev->dev, "Recently generated mac tnl interruption:\n");
1251
1252         while (kfifo_get(&hdev->mac_tnl_log, &stats)) {
1253                 rem_nsec = do_div(stats.time, HCLGE_BILLION_NANO_SECONDS);
1254                 dev_info(&hdev->pdev->dev, "[%07lu.%03lu] status = 0x%x\n",
1255                          (unsigned long)stats.time, rem_nsec / 1000,
1256                          stats.status);
1257         }
1258 }
1259
1260 static void hclge_dbg_dump_qs_shaper_single(struct hclge_dev *hdev, u16 qsid)
1261 {
1262         struct hclge_qs_shapping_cmd *shap_cfg_cmd;
1263         u8 ir_u, ir_b, ir_s, bs_b, bs_s;
1264         struct hclge_desc desc;
1265         u32 shapping_para;
1266         int ret;
1267
1268         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QCN_SHAPPING_CFG, true);
1269
1270         shap_cfg_cmd = (struct hclge_qs_shapping_cmd *)desc.data;
1271         shap_cfg_cmd->qs_id = cpu_to_le16(qsid);
1272
1273         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1274         if (ret) {
1275                 dev_err(&hdev->pdev->dev,
1276                         "qs%u failed to get tx_rate, ret=%d\n",
1277                         qsid, ret);
1278                 return;
1279         }
1280
1281         shapping_para = le32_to_cpu(shap_cfg_cmd->qs_shapping_para);
1282         ir_b = hclge_tm_get_field(shapping_para, IR_B);
1283         ir_u = hclge_tm_get_field(shapping_para, IR_U);
1284         ir_s = hclge_tm_get_field(shapping_para, IR_S);
1285         bs_b = hclge_tm_get_field(shapping_para, BS_B);
1286         bs_s = hclge_tm_get_field(shapping_para, BS_S);
1287
1288         dev_info(&hdev->pdev->dev,
1289                  "qs%u ir_b:%u, ir_u:%u, ir_s:%u, bs_b:%u, bs_s:%u\n",
1290                  qsid, ir_b, ir_u, ir_s, bs_b, bs_s);
1291 }
1292
1293 static void hclge_dbg_dump_qs_shaper_all(struct hclge_dev *hdev)
1294 {
1295         struct hnae3_knic_private_info *kinfo;
1296         struct hclge_vport *vport;
1297         int vport_id, i;
1298
1299         for (vport_id = 0; vport_id <= pci_num_vf(hdev->pdev); vport_id++) {
1300                 vport = &hdev->vport[vport_id];
1301                 kinfo = &vport->nic.kinfo;
1302
1303                 dev_info(&hdev->pdev->dev, "qs cfg of vport%d:\n", vport_id);
1304
1305                 for (i = 0; i < kinfo->num_tc; i++) {
1306                         u16 qsid = vport->qs_offset + i;
1307
1308                         hclge_dbg_dump_qs_shaper_single(hdev, qsid);
1309                 }
1310         }
1311 }
1312
1313 static void hclge_dbg_dump_qs_shaper(struct hclge_dev *hdev,
1314                                      const char *cmd_buf)
1315 {
1316 #define HCLGE_MAX_QSET_NUM 1024
1317
1318         u16 qsid;
1319         int ret;
1320
1321         ret = kstrtou16(cmd_buf, 0, &qsid);
1322         if (ret) {
1323                 hclge_dbg_dump_qs_shaper_all(hdev);
1324                 return;
1325         }
1326
1327         if (qsid >= HCLGE_MAX_QSET_NUM) {
1328                 dev_err(&hdev->pdev->dev, "qsid(%u) out of range[0-1023]\n",
1329                         qsid);
1330                 return;
1331         }
1332
1333         hclge_dbg_dump_qs_shaper_single(hdev, qsid);
1334 }
1335
1336 int hclge_dbg_run_cmd(struct hnae3_handle *handle, const char *cmd_buf)
1337 {
1338 #define DUMP_REG        "dump reg"
1339 #define DUMP_TM_MAP     "dump tm map"
1340 #define DUMP_LOOPBACK   "dump loopback"
1341
1342         struct hclge_vport *vport = hclge_get_vport(handle);
1343         struct hclge_dev *hdev = vport->back;
1344
1345         if (strncmp(cmd_buf, "dump fd tcam", 12) == 0) {
1346                 hclge_dbg_fd_tcam(hdev);
1347         } else if (strncmp(cmd_buf, "dump tc", 7) == 0) {
1348                 hclge_dbg_dump_tc(hdev);
1349         } else if (strncmp(cmd_buf, DUMP_TM_MAP, strlen(DUMP_TM_MAP)) == 0) {
1350                 hclge_dbg_dump_tm_map(hdev, &cmd_buf[sizeof(DUMP_TM_MAP)]);
1351         } else if (strncmp(cmd_buf, "dump tm", 7) == 0) {
1352                 hclge_dbg_dump_tm(hdev);
1353         } else if (strncmp(cmd_buf, "dump qos pause cfg", 18) == 0) {
1354                 hclge_dbg_dump_qos_pause_cfg(hdev);
1355         } else if (strncmp(cmd_buf, "dump qos pri map", 16) == 0) {
1356                 hclge_dbg_dump_qos_pri_map(hdev);
1357         } else if (strncmp(cmd_buf, "dump qos buf cfg", 16) == 0) {
1358                 hclge_dbg_dump_qos_buf_cfg(hdev);
1359         } else if (strncmp(cmd_buf, "dump mng tbl", 12) == 0) {
1360                 hclge_dbg_dump_mng_table(hdev);
1361         } else if (strncmp(cmd_buf, DUMP_REG, strlen(DUMP_REG)) == 0) {
1362                 hclge_dbg_dump_reg_cmd(hdev, &cmd_buf[sizeof(DUMP_REG)]);
1363         } else if (strncmp(cmd_buf, "dump reset info", 15) == 0) {
1364                 hclge_dbg_dump_rst_info(hdev);
1365         } else if (strncmp(cmd_buf, "dump serv info", 14) == 0) {
1366                 hclge_dbg_dump_serv_info(hdev);
1367         } else if (strncmp(cmd_buf, "dump m7 info", 12) == 0) {
1368                 hclge_dbg_get_m7_stats_info(hdev);
1369         } else if (strncmp(cmd_buf, "dump ncl_config", 15) == 0) {
1370                 hclge_dbg_dump_ncl_config(hdev,
1371                                           &cmd_buf[sizeof("dump ncl_config")]);
1372         } else if (strncmp(cmd_buf, "dump mac tnl status", 19) == 0) {
1373                 hclge_dbg_dump_mac_tnl_status(hdev);
1374         } else if (strncmp(cmd_buf, DUMP_LOOPBACK,
1375                    strlen(DUMP_LOOPBACK)) == 0) {
1376                 hclge_dbg_dump_loopback(hdev, &cmd_buf[sizeof(DUMP_LOOPBACK)]);
1377         } else if (strncmp(cmd_buf, "dump qs shaper", 14) == 0) {
1378                 hclge_dbg_dump_qs_shaper(hdev,
1379                                          &cmd_buf[sizeof("dump qs shaper")]);
1380         } else {
1381                 dev_info(&hdev->pdev->dev, "unknown command\n");
1382                 return -EINVAL;
1383         }
1384
1385         return 0;
1386 }