1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
7 #include <linux/if_vlan.h>
11 #define HNS3_MOD_VERSION "1.0"
13 extern const char hns3_driver_version[];
16 HNS3_NIC_STATE_TESTING,
17 HNS3_NIC_STATE_RESETTING,
18 HNS3_NIC_STATE_REINITING,
20 HNS3_NIC_STATE_DISABLED,
21 HNS3_NIC_STATE_REMOVING,
22 HNS3_NIC_STATE_SERVICE_INITED,
23 HNS3_NIC_STATE_SERVICE_SCHED,
24 HNS3_NIC_STATE2_RESET_REQUESTED,
28 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000
29 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004
30 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008
31 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C
32 #define HNS3_RING_RX_RING_TAIL_REG 0x00018
33 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C
34 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020
35 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C
37 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040
38 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044
39 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048
40 #define HNS3_RING_TX_RING_TC_REG 0x00050
41 #define HNS3_RING_TX_RING_TAIL_REG 0x00058
42 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C
43 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060
44 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064
45 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C
47 #define HNS3_RING_PREFETCH_EN_REG 0x0007C
48 #define HNS3_RING_CFG_VF_NUM_REG 0x00080
49 #define HNS3_RING_ASID_REG 0x0008C
50 #define HNS3_RING_RX_VM_REG 0x00090
51 #define HNS3_RING_T0_BE_RST 0x00094
52 #define HNS3_RING_COULD_BE_RST 0x00098
53 #define HNS3_RING_WRR_WEIGHT_REG 0x0009c
55 #define HNS3_RING_INTMSK_RXWL_REG 0x000A0
56 #define HNS3_RING_INTSTS_RX_RING_REG 0x000A4
57 #define HNS3_RX_RING_INT_STS_REG 0x000A8
58 #define HNS3_RING_INTMSK_TXWL_REG 0x000AC
59 #define HNS3_RING_INTSTS_TX_RING_REG 0x000B0
60 #define HNS3_TX_RING_INT_STS_REG 0x000B4
61 #define HNS3_RING_INTMSK_RX_OVERTIME_REG 0x000B8
62 #define HNS3_RING_INTSTS_RX_OVERTIME_REG 0x000BC
63 #define HNS3_RING_INTMSK_TX_OVERTIME_REG 0x000C4
64 #define HNS3_RING_INTSTS_TX_OVERTIME_REG 0x000C8
66 #define HNS3_RING_MB_CTRL_REG 0x00100
67 #define HNS3_RING_MB_DATA_BASE_REG 0x00200
69 #define HNS3_TX_REG_OFFSET 0x40
71 #define HNS3_RX_HEAD_SIZE 256
73 #define HNS3_TX_TIMEOUT (5 * HZ)
74 #define HNS3_RING_NAME_LEN 16
75 #define HNS3_BUFFER_SIZE_2048 2048
76 #define HNS3_RING_MAX_PENDING 32768
77 #define HNS3_RING_MIN_PENDING 8
78 #define HNS3_RING_BD_MULTIPLE 8
79 #define HNS3_MAX_MTU 9728
81 #define HNS3_BD_SIZE_512_TYPE 0
82 #define HNS3_BD_SIZE_1024_TYPE 1
83 #define HNS3_BD_SIZE_2048_TYPE 2
84 #define HNS3_BD_SIZE_4096_TYPE 3
86 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1
87 #define HNS3_RX_FLAG_L3ID_IPV4 0x0
88 #define HNS3_RX_FLAG_L3ID_IPV6 0x1
89 #define HNS3_RX_FLAG_L4ID_UDP 0x0
90 #define HNS3_RX_FLAG_L4ID_TCP 0x1
92 #define HNS3_RXD_DMAC_S 0
93 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
94 #define HNS3_RXD_VLAN_S 2
95 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
96 #define HNS3_RXD_L3ID_S 4
97 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
98 #define HNS3_RXD_L4ID_S 8
99 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
100 #define HNS3_RXD_FRAG_B 12
101 #define HNS3_RXD_STRP_TAGP_S 13
102 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
104 #define HNS3_RXD_L2E_B 16
105 #define HNS3_RXD_L3E_B 17
106 #define HNS3_RXD_L4E_B 18
107 #define HNS3_RXD_TRUNCAT_B 19
108 #define HNS3_RXD_HOI_B 20
109 #define HNS3_RXD_DOI_B 21
110 #define HNS3_RXD_OL3E_B 22
111 #define HNS3_RXD_OL4E_B 23
113 #define HNS3_RXD_ODMAC_S 0
114 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
115 #define HNS3_RXD_OVLAN_S 2
116 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
117 #define HNS3_RXD_OL3ID_S 4
118 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
119 #define HNS3_RXD_OL4ID_S 8
120 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
121 #define HNS3_RXD_FBHI_S 12
122 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
123 #define HNS3_RXD_FBLI_S 14
124 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
126 #define HNS3_RXD_BDTYPE_S 0
127 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
128 #define HNS3_RXD_VLD_B 4
129 #define HNS3_RXD_UDP0_B 5
130 #define HNS3_RXD_EXTEND_B 7
131 #define HNS3_RXD_FE_B 8
132 #define HNS3_RXD_LUM_B 9
133 #define HNS3_RXD_CRCP_B 10
134 #define HNS3_RXD_L3L4P_B 11
135 #define HNS3_RXD_TSIND_S 12
136 #define HNS3_RXD_TSIND_M (0x7 << HNS3_RXD_TSIND_S)
137 #define HNS3_RXD_LKBK_B 15
138 #define HNS3_RXD_HDL_S 16
139 #define HNS3_RXD_HDL_M (0x7ff << HNS3_RXD_HDL_S)
140 #define HNS3_RXD_HSIND_B 31
142 #define HNS3_TXD_L3T_S 0
143 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
144 #define HNS3_TXD_L4T_S 2
145 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
146 #define HNS3_TXD_L3CS_B 4
147 #define HNS3_TXD_L4CS_B 5
148 #define HNS3_TXD_VLAN_B 6
149 #define HNS3_TXD_TSO_B 7
151 #define HNS3_TXD_L2LEN_S 8
152 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
153 #define HNS3_TXD_L3LEN_S 16
154 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
155 #define HNS3_TXD_L4LEN_S 24
156 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S)
158 #define HNS3_TXD_OL3T_S 0
159 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
160 #define HNS3_TXD_OVLAN_B 2
161 #define HNS3_TXD_MACSEC_B 3
162 #define HNS3_TXD_TUNTYPE_S 4
163 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
165 #define HNS3_TXD_BDTYPE_S 0
166 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
167 #define HNS3_TXD_FE_B 4
168 #define HNS3_TXD_SC_S 5
169 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
170 #define HNS3_TXD_EXTEND_B 7
171 #define HNS3_TXD_VLD_B 8
172 #define HNS3_TXD_RI_B 9
173 #define HNS3_TXD_RA_B 10
174 #define HNS3_TXD_TSYN_B 11
175 #define HNS3_TXD_DECTTL_S 12
176 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
178 #define HNS3_TXD_MSS_S 0
179 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
181 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0)
182 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1)
184 #define HNS3_VECTOR_NOT_INITED 0
185 #define HNS3_VECTOR_INITED 1
187 #define HNS3_MAX_BD_SIZE 65535
188 #define HNS3_MAX_BD_PER_FRAG 8
189 #define HNS3_MAX_BD_PER_PKT MAX_SKB_FRAGS
191 #define HNS3_VECTOR_GL0_OFFSET 0x100
192 #define HNS3_VECTOR_GL1_OFFSET 0x200
193 #define HNS3_VECTOR_GL2_OFFSET 0x300
194 #define HNS3_VECTOR_RL_OFFSET 0x900
195 #define HNS3_VECTOR_RL_EN_B 6
197 enum hns3_pkt_l3t_type {
204 enum hns3_pkt_l4t_type {
211 enum hns3_pkt_ol3t_type {
214 HNS3_OL3T_IPV4_NO_CSUM,
218 enum hns3_pkt_tun_type {
225 /* hardware spec ring buffer format */
226 struct __packed hns3_desc {
233 __le32 type_cs_vlan_tso_len;
235 __u8 type_cs_vlan_tso;
241 __le16 outer_vlan_tag;
245 __le32 ol_type_vlan_len_msec;
247 __u8 ol_type_vlan_msec;
255 __le16 bdtp_fe_sc_vld_ra_ri;
271 __le16 o_dm_vlan_id_fb;
281 struct hns3_desc_cb {
282 dma_addr_t dma; /* dma address of this desc */
283 void *buf; /* cpu addr for a desc */
285 /* priv data for the desc, e.g. skb when use with ip stack*/
290 u32 length; /* length of the buffer */
292 /* desc type, used by the ring user to mark the type of the priv data */
296 enum hns3_pkt_l3type {
301 HNS3_L3_TYPE_IPV4_OPT,
302 HNS3_L3_TYPE_IPV6_EXT,
305 HNS3_L3_TYPE_MAC_PAUSE,
306 HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/
308 /* reserved for 0xA~0xB*/
310 HNS3_L3_TYPE_CNM = 0xc,
312 /* reserved for 0xD~0xE*/
314 HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */
317 enum hns3_pkt_l4type {
325 /* reserved for 0x6~0xE */
327 HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */
330 enum hns3_pkt_ol3type {
331 HNS3_OL3_TYPE_IPV4 = 0,
333 /* reserved for 0x2~0x3 */
334 HNS3_OL3_TYPE_IPV4_OPT = 4,
335 HNS3_OL3_TYPE_IPV6_EXT,
337 /* reserved for 0x6~0xE*/
339 HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */
342 enum hns3_pkt_ol4type {
343 HNS3_OL4_TYPE_NO_TUN,
344 HNS3_OL4_TYPE_MAC_IN_UDP,
346 HNS3_OL4_TYPE_UNKNOWN
375 struct hns3_enet_ring {
376 u8 __iomem *io_base; /* base io address for the ring */
377 struct hns3_desc *desc; /* dma map address space */
378 struct hns3_desc_cb *desc_cb;
379 struct hns3_enet_ring *next;
380 struct hns3_enet_tqp_vector *tqp_vector;
381 struct hnae3_queue *tqp;
382 char ring_name[HNS3_RING_NAME_LEN];
383 struct device *dev; /* will be used for DMA mapping of descriptors */
386 struct ring_stats stats;
387 struct u64_stats_sync syncp;
389 dma_addr_t desc_dma_addr;
390 u32 buf_size; /* size for hnae_desc->addr, preset by AE */
391 u16 desc_num; /* total number of desc */
392 u16 max_desc_num_per_pkt;
393 u16 max_raw_data_sz_per_desc;
395 int next_to_use; /* idx of next spare desc */
397 /* idx of lastest sent desc, the ring is empty when equal to
402 u32 flag; /* ring attribute */
406 cpumask_t affinity_mask;
411 struct hns3_nic_ring_data {
412 struct hns3_enet_ring *ring;
413 struct napi_struct napi;
415 int (*poll_one)(struct hns3_nic_ring_data *, int, void *);
416 void (*ex_process)(struct hns3_nic_ring_data *, struct sk_buff *);
417 void (*fini_process)(struct hns3_nic_ring_data *);
420 struct hns3_nic_ops {
421 int (*fill_desc)(struct hns3_enet_ring *ring, void *priv,
422 int size, dma_addr_t dma, int frag_end,
423 enum hns_desc_type type);
424 int (*maybe_stop_tx)(struct sk_buff **out_skb,
425 int *bnum, struct hns3_enet_ring *ring);
426 void (*get_rxd_bnum)(u32 bnum_flag, int *out_bnum);
429 enum hns3_flow_level_range {
436 enum hns3_link_mode_bits {
437 HNS3_LM_FIBRE_BIT = BIT(0),
438 HNS3_LM_AUTONEG_BIT = BIT(1),
439 HNS3_LM_TP_BIT = BIT(2),
440 HNS3_LM_PAUSE_BIT = BIT(3),
441 HNS3_LM_BACKPLANE_BIT = BIT(4),
442 HNS3_LM_10BASET_HALF_BIT = BIT(5),
443 HNS3_LM_10BASET_FULL_BIT = BIT(6),
444 HNS3_LM_100BASET_HALF_BIT = BIT(7),
445 HNS3_LM_100BASET_FULL_BIT = BIT(8),
446 HNS3_LM_1000BASET_FULL_BIT = BIT(9),
447 HNS3_LM_10000BASEKR_FULL_BIT = BIT(10),
448 HNS3_LM_25000BASEKR_FULL_BIT = BIT(11),
449 HNS3_LM_40000BASELR4_FULL_BIT = BIT(12),
450 HNS3_LM_50000BASEKR2_FULL_BIT = BIT(13),
451 HNS3_LM_100000BASEKR4_FULL_BIT = BIT(14),
455 #define HNS3_INT_GL_MAX 0x1FE0
456 #define HNS3_INT_GL_50K 0x0014
457 #define HNS3_INT_GL_20K 0x0032
458 #define HNS3_INT_GL_18K 0x0036
459 #define HNS3_INT_GL_8K 0x007C
461 #define HNS3_INT_RL_MAX 0x00EC
462 #define HNS3_INT_RL_ENABLE_MASK 0x40
464 #define HNS3_INT_ADAPT_DOWN_START 100
466 struct hns3_enet_coalesce {
469 enum hns3_flow_level_range flow_level;
472 struct hns3_enet_ring_group {
473 /* array of pointers to rings */
474 struct hns3_enet_ring *ring;
475 u64 total_bytes; /* total bytes processed this group */
476 u64 total_packets; /* total packets processed this group */
478 struct hns3_enet_coalesce coal;
481 struct hns3_enet_tqp_vector {
482 struct hnae3_handle *handle;
483 u8 __iomem *mask_addr;
487 u16 idx; /* index in the TQP vector array per handle. */
489 struct napi_struct napi;
491 struct hns3_enet_ring_group rx_group;
492 struct hns3_enet_ring_group tx_group;
494 u16 num_tqps; /* total number of tqps in TQP vector */
496 char name[HNAE3_INT_NAME_LEN];
498 /* when 0 should adjust interrupt coalesce parameter */
500 unsigned long last_jiffies;
501 } ____cacheline_internodealigned_in_smp;
503 enum hns3_udp_tnl_type {
509 struct hns3_udp_tunnel {
514 struct hns3_nic_priv {
515 struct hnae3_handle *ae_handle;
518 struct net_device *netdev;
520 struct hns3_nic_ops ops;
523 * the cb for nic to manage the ring buffer, the first half of the
524 * array is for tx_ring and vice versa for the second half
526 struct hns3_nic_ring_data *ring_data;
527 struct hns3_enet_tqp_vector *tqp_vector;
530 /* The most recently read link state */
532 u64 tx_timeout_count;
536 struct timer_list service_timer;
538 struct work_struct service_task;
540 struct notifier_block notifier_block;
541 /* Vxlan/Geneve information */
542 struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX];
543 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
558 /* the distance between [begin, end) in a ring buffer
559 * note: there is a unuse slot between the begin and the end
561 static inline int ring_dist(struct hns3_enet_ring *ring, int begin, int end)
563 return (end - begin + ring->desc_num) % ring->desc_num;
566 static inline int ring_space(struct hns3_enet_ring *ring)
568 return ring->desc_num -
569 ring_dist(ring, ring->next_to_clean, ring->next_to_use) - 1;
572 static inline int is_ring_empty(struct hns3_enet_ring *ring)
574 return ring->next_to_use == ring->next_to_clean;
577 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value)
579 u8 __iomem *reg_addr = READ_ONCE(base);
581 writel(value, reg_addr + reg);
584 #define hns3_write_dev(a, reg, value) \
585 hns3_write_reg((a)->io_base, (reg), (value))
587 #define hnae3_queue_xmit(tqp, buf_num) writel_relaxed(buf_num, \
588 (tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG)
590 #define ring_to_dev(ring) (&(ring)->tqp->handle->pdev->dev)
592 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \
593 DMA_TO_DEVICE : DMA_FROM_DEVICE)
595 #define tx_ring_data(priv, idx) ((priv)->ring_data[idx])
597 #define hnae3_buf_size(_ring) ((_ring)->buf_size)
598 #define hnae3_page_order(_ring) (get_order(hnae3_buf_size(_ring)))
599 #define hnae3_page_size(_ring) (PAGE_SIZE << hnae3_page_order(_ring))
601 /* iterator for handling rings in ring group */
602 #define hns3_for_each_ring(pos, head) \
603 for (pos = (head).ring; pos; pos = pos->next)
605 #define hns3_get_handle(ndev) \
606 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle)
608 #define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1)
609 #define hns3_gl_round_down(int_gl) round_down(int_gl, 2)
611 #define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2)
612 #define hns3_rl_round_down(int_rl) round_down(int_rl, 4)
614 void hns3_ethtool_set_ops(struct net_device *netdev);
615 int hns3_set_channels(struct net_device *netdev,
616 struct ethtool_channels *ch);
618 bool hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget);
619 int hns3_init_all_ring(struct hns3_nic_priv *priv);
620 int hns3_uninit_all_ring(struct hns3_nic_priv *priv);
621 int hns3_nic_reset_all_ring(struct hnae3_handle *h);
622 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
623 int hns3_clean_rx_ring(
624 struct hns3_enet_ring *ring, int budget,
625 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *));
627 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
629 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
631 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
634 #ifdef CONFIG_HNS3_DCB
635 void hns3_dcbnl_setup(struct hnae3_handle *handle);
637 static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {}