2 * Copyright (c) 2014-2015 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/cdev.h>
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <asm/cacheflush.h>
17 #include <linux/platform_device.h>
19 #include <linux/of_address.h>
20 #include <linux/of_platform.h>
21 #include <linux/of_irq.h>
22 #include <linux/spinlock.h>
24 #include "hns_dsaf_main.h"
25 #include "hns_dsaf_ppe.h"
26 #include "hns_dsaf_rcb.h"
28 #define RCB_COMMON_REG_OFFSET 0x80000
32 #define RCB_RESET_WAIT_TIMES 30
33 #define RCB_RESET_TRY_TIMES 10
35 /* Because default mtu is 1500, rcb buffer size is set to 2048 enough */
36 #define RCB_DEFAULT_BUFFER_SIZE 2048
39 *hns_rcb_wait_fbd_clean - clean fbd
40 *@qs: ring struct pointer array
44 void hns_rcb_wait_fbd_clean(struct hnae_queue **qs, int q_num, u32 flag)
49 for (wait_cnt = i = 0; i < q_num; wait_cnt++) {
50 usleep_range(200, 300);
52 if (flag & RCB_INT_FLAG_TX)
53 fbd_num += dsaf_read_dev(qs[i],
54 RCB_RING_TX_RING_FBDNUM_REG);
55 if (flag & RCB_INT_FLAG_RX)
56 fbd_num += dsaf_read_dev(qs[i],
57 RCB_RING_RX_RING_FBDNUM_REG);
60 if (wait_cnt >= 10000)
65 dev_err(qs[i]->handle->owner_dev,
66 "queue(%d) wait fbd(%d) clean fail!!\n", i, fbd_num);
69 int hns_rcb_wait_tx_ring_clean(struct hnae_queue *qs)
74 tail = dsaf_read_dev(&qs->tx_ring, RCB_REG_TAIL);
76 while (wait_cnt++ < HNS_MAX_WAIT_CNT) {
77 head = dsaf_read_dev(&qs->tx_ring, RCB_REG_HEAD);
81 usleep_range(100, 200);
84 if (wait_cnt >= HNS_MAX_WAIT_CNT) {
85 dev_err(qs->dev->dev, "rcb wait timeout, head not equal to tail.\n");
93 *hns_rcb_reset_ring_hw - ring reset
94 *@q: ring struct pointer
96 void hns_rcb_reset_ring_hw(struct hnae_queue *q)
104 while (try_cnt++ < RCB_RESET_TRY_TIMES) {
105 usleep_range(100, 200);
106 tx_fbd_num = dsaf_read_dev(q, RCB_RING_TX_RING_FBDNUM_REG);
110 dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, 0);
112 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1);
115 could_ret = dsaf_read_dev(q, RCB_RING_COULD_BE_RST);
118 while (!could_ret && (wait_cnt < RCB_RESET_WAIT_TIMES)) {
119 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0);
121 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1);
124 could_ret = dsaf_read_dev(q, RCB_RING_COULD_BE_RST);
129 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0);
135 if (try_cnt >= RCB_RESET_TRY_TIMES)
136 dev_err(q->dev->dev, "port%d reset ring fail\n",
137 hns_ae_get_vf_cb(q->handle)->port_index);
141 *hns_rcb_int_ctrl_hw - rcb irq enable control
142 *@q: hnae queue struct pointer
143 *@flag:ring flag tx or rx
146 void hns_rcb_int_ctrl_hw(struct hnae_queue *q, u32 flag, u32 mask)
148 u32 int_mask_en = !!mask;
150 if (flag & RCB_INT_FLAG_TX) {
151 dsaf_write_dev(q, RCB_RING_INTMSK_TXWL_REG, int_mask_en);
152 dsaf_write_dev(q, RCB_RING_INTMSK_TX_OVERTIME_REG,
156 if (flag & RCB_INT_FLAG_RX) {
157 dsaf_write_dev(q, RCB_RING_INTMSK_RXWL_REG, int_mask_en);
158 dsaf_write_dev(q, RCB_RING_INTMSK_RX_OVERTIME_REG,
163 void hns_rcb_int_clr_hw(struct hnae_queue *q, u32 flag)
165 if (flag & RCB_INT_FLAG_TX) {
166 dsaf_write_dev(q, RCB_RING_INTSTS_TX_RING_REG, 1);
167 dsaf_write_dev(q, RCB_RING_INTSTS_TX_OVERTIME_REG, 1);
170 if (flag & RCB_INT_FLAG_RX) {
171 dsaf_write_dev(q, RCB_RING_INTSTS_RX_RING_REG, 1);
172 dsaf_write_dev(q, RCB_RING_INTSTS_RX_OVERTIME_REG, 1);
176 void hns_rcbv2_int_ctrl_hw(struct hnae_queue *q, u32 flag, u32 mask)
178 u32 int_mask_en = !!mask;
180 if (flag & RCB_INT_FLAG_TX)
181 dsaf_write_dev(q, RCB_RING_INTMSK_TXWL_REG, int_mask_en);
183 if (flag & RCB_INT_FLAG_RX)
184 dsaf_write_dev(q, RCB_RING_INTMSK_RXWL_REG, int_mask_en);
187 void hns_rcbv2_int_clr_hw(struct hnae_queue *q, u32 flag)
189 if (flag & RCB_INT_FLAG_TX)
190 dsaf_write_dev(q, RCBV2_TX_RING_INT_STS_REG, 1);
192 if (flag & RCB_INT_FLAG_RX)
193 dsaf_write_dev(q, RCBV2_RX_RING_INT_STS_REG, 1);
197 *hns_rcb_ring_enable_hw - enable ring
200 void hns_rcb_ring_enable_hw(struct hnae_queue *q, u32 val)
202 dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, !!val);
205 void hns_rcb_start(struct hnae_queue *q, u32 val)
207 hns_rcb_ring_enable_hw(q, val);
211 *hns_rcb_common_init_commit_hw - make rcb common init completed
212 *@rcb_common: rcb common device
214 void hns_rcb_common_init_commit_hw(struct rcb_common_cb *rcb_common)
216 wmb(); /* Sync point before breakpoint */
217 dsaf_write_dev(rcb_common, RCB_COM_CFG_SYS_FSH_REG, 1);
218 wmb(); /* Sync point after breakpoint */
221 /* hns_rcb_set_tx_ring_bs - init rcb ring buf size regester
223 *@buf_size: buffer size set to hw
225 void hns_rcb_set_tx_ring_bs(struct hnae_queue *q, u32 buf_size)
227 u32 bd_size_type = hns_rcb_buf_size2type(buf_size);
229 dsaf_write_dev(q, RCB_RING_TX_RING_BD_LEN_REG,
233 /* hns_rcb_set_rx_ring_bs - init rcb ring buf size regester
235 *@buf_size: buffer size set to hw
237 void hns_rcb_set_rx_ring_bs(struct hnae_queue *q, u32 buf_size)
239 u32 bd_size_type = hns_rcb_buf_size2type(buf_size);
241 dsaf_write_dev(q, RCB_RING_RX_RING_BD_LEN_REG,
246 *hns_rcb_ring_init - init rcb ring
247 *@ring_pair: ring pair control block
248 *@ring_type: ring type, RX_RING or TX_RING
250 static void hns_rcb_ring_init(struct ring_pair_cb *ring_pair, int ring_type)
252 struct hnae_queue *q = &ring_pair->q;
253 struct hnae_ring *ring =
254 (ring_type == RX_RING) ? &q->rx_ring : &q->tx_ring;
255 dma_addr_t dma = ring->desc_dma_addr;
257 if (ring_type == RX_RING) {
258 dsaf_write_dev(q, RCB_RING_RX_RING_BASEADDR_L_REG,
260 dsaf_write_dev(q, RCB_RING_RX_RING_BASEADDR_H_REG,
261 (u32)((dma >> 31) >> 1));
263 hns_rcb_set_rx_ring_bs(q, ring->buf_size);
265 dsaf_write_dev(q, RCB_RING_RX_RING_BD_NUM_REG,
266 ring_pair->port_id_in_comm);
267 dsaf_write_dev(q, RCB_RING_RX_RING_PKTLINE_REG,
268 ring_pair->port_id_in_comm);
270 dsaf_write_dev(q, RCB_RING_TX_RING_BASEADDR_L_REG,
272 dsaf_write_dev(q, RCB_RING_TX_RING_BASEADDR_H_REG,
273 (u32)((dma >> 31) >> 1));
275 hns_rcb_set_tx_ring_bs(q, ring->buf_size);
277 dsaf_write_dev(q, RCB_RING_TX_RING_BD_NUM_REG,
278 ring_pair->port_id_in_comm);
279 dsaf_write_dev(q, RCB_RING_TX_RING_PKTLINE_REG,
280 ring_pair->port_id_in_comm + HNS_RCB_TX_PKTLINE_OFFSET);
285 *hns_rcb_init_hw - init rcb hardware
288 void hns_rcb_init_hw(struct ring_pair_cb *ring)
290 hns_rcb_ring_init(ring, RX_RING);
291 hns_rcb_ring_init(ring, TX_RING);
295 *hns_rcb_set_port_desc_cnt - set rcb port description num
296 *@rcb_common: rcb_common device
297 *@port_idx:port index
300 static void hns_rcb_set_port_desc_cnt(struct rcb_common_cb *rcb_common,
301 u32 port_idx, u32 desc_cnt)
303 dsaf_write_dev(rcb_common, RCB_CFG_BD_NUM_REG + port_idx * 4,
307 static void hns_rcb_set_port_timeout(
308 struct rcb_common_cb *rcb_common, u32 port_idx, u32 timeout)
310 if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver)) {
311 dsaf_write_dev(rcb_common, RCB_CFG_OVERTIME_REG,
312 timeout * HNS_RCB_CLK_FREQ_MHZ);
313 } else if (!HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev)) {
314 if (timeout > HNS_RCB_DEF_GAP_TIME_USECS)
315 dsaf_write_dev(rcb_common,
316 RCB_PORT_INT_GAPTIME_REG + port_idx * 4,
317 HNS_RCB_DEF_GAP_TIME_USECS);
319 dsaf_write_dev(rcb_common,
320 RCB_PORT_INT_GAPTIME_REG + port_idx * 4,
323 dsaf_write_dev(rcb_common,
324 RCB_PORT_CFG_OVERTIME_REG + port_idx * 4,
327 dsaf_write_dev(rcb_common,
328 RCB_PORT_CFG_OVERTIME_REG + port_idx * 4,
333 static int hns_rcb_common_get_port_num(struct rcb_common_cb *rcb_common)
335 if (!HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev))
336 return HNS_RCB_SERVICE_NW_ENGINE_NUM;
338 return HNS_RCB_DEBUG_NW_ENGINE_NUM;
341 /*clr rcb comm exception irq**/
342 static void hns_rcb_comm_exc_irq_en(
343 struct rcb_common_cb *rcb_common, int en)
345 u32 clr_vlue = 0xfffffffful;
346 u32 msk_vlue = en ? 0 : 0xfffffffful;
349 dsaf_write_dev(rcb_common, RCB_COM_INTSTS_ECC_ERR_REG, clr_vlue);
351 dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_RING_STS, clr_vlue);
353 dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_BD_RINT_STS, clr_vlue);
355 dsaf_write_dev(rcb_common, RCB_COM_RINT_TX_PKT_REG, clr_vlue);
356 dsaf_write_dev(rcb_common, RCB_COM_AXI_ERR_STS, clr_vlue);
359 dsaf_write_dev(rcb_common, RCB_COM_INTMASK_ECC_ERR_REG, msk_vlue);
361 dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_INTMASK_RING, msk_vlue);
363 /*for tx bd neednot cacheline, so msk sf_txring_fbd_intmask (bit 1)**/
364 dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_INTMASK_BD, msk_vlue | 2);
366 dsaf_write_dev(rcb_common, RCB_COM_INTMSK_TX_PKT_REG, msk_vlue);
367 dsaf_write_dev(rcb_common, RCB_COM_AXI_WR_ERR_INTMASK, msk_vlue);
371 *hns_rcb_common_init_hw - init rcb common hardware
372 *@rcb_common: rcb_common device
373 *retuen 0 - success , negative --fail
375 int hns_rcb_common_init_hw(struct rcb_common_cb *rcb_common)
379 int port_num = hns_rcb_common_get_port_num(rcb_common);
381 hns_rcb_comm_exc_irq_en(rcb_common, 0);
383 reg_val = dsaf_read_dev(rcb_common, RCB_COM_CFG_INIT_FLAG_REG);
384 if (0x1 != (reg_val & 0x1)) {
385 dev_err(rcb_common->dsaf_dev->dev,
386 "RCB_COM_CFG_INIT_FLAG_REG reg = 0x%x\n", reg_val);
390 for (i = 0; i < port_num; i++) {
391 hns_rcb_set_port_desc_cnt(rcb_common, i, rcb_common->desc_num);
392 hns_rcb_set_rx_coalesced_frames(
393 rcb_common, i, HNS_RCB_DEF_RX_COALESCED_FRAMES);
394 if (!AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver) &&
395 !HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev))
396 hns_rcb_set_tx_coalesced_frames(
397 rcb_common, i, HNS_RCB_DEF_TX_COALESCED_FRAMES);
398 hns_rcb_set_port_timeout(
399 rcb_common, i, HNS_RCB_DEF_COALESCED_USECS);
402 dsaf_write_dev(rcb_common, RCB_COM_CFG_ENDIAN_REG,
403 HNS_RCB_COMMON_ENDIAN);
405 if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver)) {
406 dsaf_write_dev(rcb_common, RCB_COM_CFG_FNA_REG, 0x0);
407 dsaf_write_dev(rcb_common, RCB_COM_CFG_FA_REG, 0x1);
409 dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_USER_REG,
410 RCB_COM_CFG_FNA_B, false);
411 dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_USER_REG,
412 RCB_COM_CFG_FA_B, true);
413 dsaf_set_dev_bit(rcb_common, RCBV2_COM_CFG_TSO_MODE_REG,
414 RCB_COM_TSO_MODE_B, HNS_TSO_MODE_8BD_32K);
420 int hns_rcb_buf_size2type(u32 buf_size)
426 bd_size_type = HNS_BD_SIZE_512_TYPE;
429 bd_size_type = HNS_BD_SIZE_1024_TYPE;
432 bd_size_type = HNS_BD_SIZE_2048_TYPE;
435 bd_size_type = HNS_BD_SIZE_4096_TYPE;
438 bd_size_type = -EINVAL;
444 static void hns_rcb_ring_get_cfg(struct hnae_queue *q, int ring_type)
446 struct hnae_ring *ring;
447 struct rcb_common_cb *rcb_common;
448 struct ring_pair_cb *ring_pair_cb;
449 u16 desc_num, mdnum_ppkt;
450 bool irq_idx, is_ver1;
452 ring_pair_cb = container_of(q, struct ring_pair_cb, q);
453 is_ver1 = AE_IS_VER1(ring_pair_cb->rcb_common->dsaf_dev->dsaf_ver);
454 if (ring_type == RX_RING) {
456 ring->io_base = ring_pair_cb->q.io_base;
457 irq_idx = HNS_RCB_IRQ_IDX_RX;
458 mdnum_ppkt = HNS_RCB_RING_MAX_BD_PER_PKT;
461 ring->io_base = (u8 __iomem *)ring_pair_cb->q.io_base +
462 HNS_RCB_TX_REG_OFFSET;
463 irq_idx = HNS_RCB_IRQ_IDX_TX;
464 mdnum_ppkt = is_ver1 ? HNS_RCB_RING_MAX_TXBD_PER_PKT :
465 HNS_RCBV2_RING_MAX_TXBD_PER_PKT;
468 rcb_common = ring_pair_cb->rcb_common;
469 desc_num = rcb_common->dsaf_dev->desc_num;
472 ring->desc_cb = NULL;
474 ring->irq = ring_pair_cb->virq[irq_idx];
475 ring->desc_dma_addr = 0;
477 ring->buf_size = RCB_DEFAULT_BUFFER_SIZE;
478 ring->desc_num = desc_num;
479 ring->max_desc_num_per_pkt = mdnum_ppkt;
480 ring->max_raw_data_sz_per_desc = HNS_RCB_MAX_PKT_SIZE;
481 ring->max_pkt_size = HNS_RCB_MAX_PKT_SIZE;
482 ring->next_to_use = 0;
483 ring->next_to_clean = 0;
486 static void hns_rcb_ring_pair_get_cfg(struct ring_pair_cb *ring_pair_cb)
488 ring_pair_cb->q.handle = NULL;
490 hns_rcb_ring_get_cfg(&ring_pair_cb->q, RX_RING);
491 hns_rcb_ring_get_cfg(&ring_pair_cb->q, TX_RING);
494 static int hns_rcb_get_port_in_comm(
495 struct rcb_common_cb *rcb_common, int ring_idx)
497 return ring_idx / (rcb_common->max_q_per_vf * rcb_common->max_vfn);
500 #define SERVICE_RING_IRQ_IDX(v1) \
501 ((v1) ? HNS_SERVICE_RING_IRQ_IDX : HNSV2_SERVICE_RING_IRQ_IDX)
502 static int hns_rcb_get_base_irq_idx(struct rcb_common_cb *rcb_common)
504 bool is_ver1 = AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver);
506 if (!HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev))
507 return SERVICE_RING_IRQ_IDX(is_ver1);
509 return HNS_DEBUG_RING_IRQ_IDX;
512 #define RCB_COMM_BASE_TO_RING_BASE(base, ringid)\
513 ((base) + 0x10000 + HNS_RCB_REG_OFFSET * (ringid))
515 *hns_rcb_get_cfg - get rcb config
516 *@rcb_common: rcb common device
518 int hns_rcb_get_cfg(struct rcb_common_cb *rcb_common)
520 struct ring_pair_cb *ring_pair_cb;
522 u32 ring_num = rcb_common->ring_num;
523 int base_irq_idx = hns_rcb_get_base_irq_idx(rcb_common);
524 struct platform_device *pdev =
525 to_platform_device(rcb_common->dsaf_dev->dev);
526 bool is_ver1 = AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver);
528 for (i = 0; i < ring_num; i++) {
529 ring_pair_cb = &rcb_common->ring_pair_cb[i];
530 ring_pair_cb->rcb_common = rcb_common;
531 ring_pair_cb->dev = rcb_common->dsaf_dev->dev;
532 ring_pair_cb->index = i;
533 ring_pair_cb->q.io_base =
534 RCB_COMM_BASE_TO_RING_BASE(rcb_common->io_base, i);
535 ring_pair_cb->port_id_in_comm =
536 hns_rcb_get_port_in_comm(rcb_common, i);
537 ring_pair_cb->virq[HNS_RCB_IRQ_IDX_TX] =
538 is_ver1 ? platform_get_irq(pdev, base_irq_idx + i * 2) :
539 platform_get_irq(pdev, base_irq_idx + i * 3 + 1);
540 ring_pair_cb->virq[HNS_RCB_IRQ_IDX_RX] =
541 is_ver1 ? platform_get_irq(pdev, base_irq_idx + i * 2 + 1) :
542 platform_get_irq(pdev, base_irq_idx + i * 3);
543 if ((ring_pair_cb->virq[HNS_RCB_IRQ_IDX_TX] == -EPROBE_DEFER) ||
544 (ring_pair_cb->virq[HNS_RCB_IRQ_IDX_RX] == -EPROBE_DEFER))
545 return -EPROBE_DEFER;
547 ring_pair_cb->q.phy_base =
548 RCB_COMM_BASE_TO_RING_BASE(rcb_common->phy_base, i);
549 hns_rcb_ring_pair_get_cfg(ring_pair_cb);
556 *hns_rcb_get_rx_coalesced_frames - get rcb port rx coalesced frames
557 *@rcb_common: rcb_common device
558 *@port_idx:port id in comm
560 *Returns: coalesced_frames
562 u32 hns_rcb_get_rx_coalesced_frames(
563 struct rcb_common_cb *rcb_common, u32 port_idx)
565 return dsaf_read_dev(rcb_common, RCB_CFG_PKTLINE_REG + port_idx * 4);
569 *hns_rcb_get_tx_coalesced_frames - get rcb port tx coalesced frames
570 *@rcb_common: rcb_common device
571 *@port_idx:port id in comm
573 *Returns: coalesced_frames
575 u32 hns_rcb_get_tx_coalesced_frames(
576 struct rcb_common_cb *rcb_common, u32 port_idx)
580 reg = RCB_CFG_PKTLINE_REG + (port_idx + HNS_RCB_TX_PKTLINE_OFFSET) * 4;
581 return dsaf_read_dev(rcb_common, reg);
585 *hns_rcb_get_coalesce_usecs - get rcb port coalesced time_out
586 *@rcb_common: rcb_common device
587 *@port_idx:port id in comm
591 u32 hns_rcb_get_coalesce_usecs(
592 struct rcb_common_cb *rcb_common, u32 port_idx)
594 if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver))
595 return dsaf_read_dev(rcb_common, RCB_CFG_OVERTIME_REG) /
596 HNS_RCB_CLK_FREQ_MHZ;
598 return dsaf_read_dev(rcb_common,
599 RCB_PORT_CFG_OVERTIME_REG + port_idx * 4);
603 *hns_rcb_set_coalesce_usecs - set rcb port coalesced time_out
604 *@rcb_common: rcb_common device
605 *@port_idx:port id in comm
606 *@timeout:tx/rx time for coalesced time_out
609 * Zero for success, or an error code in case of failure
611 int hns_rcb_set_coalesce_usecs(
612 struct rcb_common_cb *rcb_common, u32 port_idx, u32 timeout)
614 u32 old_timeout = hns_rcb_get_coalesce_usecs(rcb_common, port_idx);
616 if (timeout == old_timeout)
619 if (AE_IS_VER1(rcb_common->dsaf_dev->dsaf_ver)) {
620 if (!HNS_DSAF_IS_DEBUG(rcb_common->dsaf_dev)) {
621 dev_err(rcb_common->dsaf_dev->dev,
622 "error: not support coalesce_usecs setting!\n");
626 if (timeout > HNS_RCB_MAX_COALESCED_USECS || timeout == 0) {
627 dev_err(rcb_common->dsaf_dev->dev,
628 "error: coalesce_usecs setting supports 1~1023us\n");
631 hns_rcb_set_port_timeout(rcb_common, port_idx, timeout);
636 *hns_rcb_set_tx_coalesced_frames - set rcb coalesced frames
637 *@rcb_common: rcb_common device
638 *@port_idx:port id in comm
639 *@coalesced_frames:tx/rx BD num for coalesced frames
642 * Zero for success, or an error code in case of failure
644 int hns_rcb_set_tx_coalesced_frames(
645 struct rcb_common_cb *rcb_common, u32 port_idx, u32 coalesced_frames)
648 hns_rcb_get_tx_coalesced_frames(rcb_common, port_idx);
651 if (coalesced_frames == old_waterline)
654 if (coalesced_frames != 1) {
655 dev_err(rcb_common->dsaf_dev->dev,
656 "error: not support tx coalesce_frames setting!\n");
660 reg = RCB_CFG_PKTLINE_REG + (port_idx + HNS_RCB_TX_PKTLINE_OFFSET) * 4;
661 dsaf_write_dev(rcb_common, reg, coalesced_frames);
666 *hns_rcb_set_rx_coalesced_frames - set rcb rx coalesced frames
667 *@rcb_common: rcb_common device
668 *@port_idx:port id in comm
669 *@coalesced_frames:tx/rx BD num for coalesced frames
672 * Zero for success, or an error code in case of failure
674 int hns_rcb_set_rx_coalesced_frames(
675 struct rcb_common_cb *rcb_common, u32 port_idx, u32 coalesced_frames)
678 hns_rcb_get_rx_coalesced_frames(rcb_common, port_idx);
680 if (coalesced_frames == old_waterline)
683 if (coalesced_frames >= rcb_common->desc_num ||
684 coalesced_frames > HNS_RCB_MAX_COALESCED_FRAMES ||
685 coalesced_frames < HNS_RCB_MIN_COALESCED_FRAMES) {
686 dev_err(rcb_common->dsaf_dev->dev,
687 "error: not support coalesce_frames setting!\n");
691 dsaf_write_dev(rcb_common, RCB_CFG_PKTLINE_REG + port_idx * 4,
697 *hns_rcb_get_queue_mode - get max VM number and max ring number per VM
698 * accordding to dsaf mode
699 *@dsaf_mode: dsaf mode
700 *@max_vfn : max vfn number
701 *@max_q_per_vf:max ring number per vm
703 void hns_rcb_get_queue_mode(enum dsaf_mode dsaf_mode, u16 *max_vfn,
707 case DSAF_MODE_DISABLE_6PORT_0VM:
711 case DSAF_MODE_DISABLE_FIX:
712 case DSAF_MODE_DISABLE_SP:
716 case DSAF_MODE_DISABLE_2PORT_64VM:
720 case DSAF_MODE_DISABLE_6PORT_16VM:
731 static int hns_rcb_get_ring_num(struct dsaf_device *dsaf_dev)
733 switch (dsaf_dev->dsaf_mode) {
734 case DSAF_MODE_ENABLE_FIX:
735 case DSAF_MODE_DISABLE_SP:
738 case DSAF_MODE_DISABLE_FIX:
741 case DSAF_MODE_ENABLE_0VM:
744 case DSAF_MODE_DISABLE_6PORT_0VM:
745 case DSAF_MODE_ENABLE_16VM:
746 case DSAF_MODE_DISABLE_6PORT_2VM:
747 case DSAF_MODE_DISABLE_6PORT_16VM:
748 case DSAF_MODE_DISABLE_6PORT_4VM:
749 case DSAF_MODE_ENABLE_8VM:
752 case DSAF_MODE_DISABLE_2PORT_16VM:
753 case DSAF_MODE_DISABLE_2PORT_8VM:
754 case DSAF_MODE_ENABLE_32VM:
755 case DSAF_MODE_DISABLE_2PORT_64VM:
756 case DSAF_MODE_ENABLE_128VM:
760 dev_warn(dsaf_dev->dev,
761 "get ring num fail,use default!dsaf_mode=%d\n",
762 dsaf_dev->dsaf_mode);
767 static void __iomem *hns_rcb_common_get_vaddr(struct rcb_common_cb *rcb_common)
769 struct dsaf_device *dsaf_dev = rcb_common->dsaf_dev;
771 return dsaf_dev->ppe_base + RCB_COMMON_REG_OFFSET;
774 static phys_addr_t hns_rcb_common_get_paddr(struct rcb_common_cb *rcb_common)
776 struct dsaf_device *dsaf_dev = rcb_common->dsaf_dev;
778 return dsaf_dev->ppe_paddr + RCB_COMMON_REG_OFFSET;
781 int hns_rcb_common_get_cfg(struct dsaf_device *dsaf_dev,
784 struct rcb_common_cb *rcb_common;
785 enum dsaf_mode dsaf_mode = dsaf_dev->dsaf_mode;
788 int ring_num = hns_rcb_get_ring_num(dsaf_dev);
791 devm_kzalloc(dsaf_dev->dev, sizeof(*rcb_common) +
792 ring_num * sizeof(struct ring_pair_cb), GFP_KERNEL);
794 dev_err(dsaf_dev->dev, "rcb common devm_kzalloc fail!\n");
797 rcb_common->comm_index = comm_index;
798 rcb_common->ring_num = ring_num;
799 rcb_common->dsaf_dev = dsaf_dev;
801 rcb_common->desc_num = dsaf_dev->desc_num;
803 hns_rcb_get_queue_mode(dsaf_mode, &max_vfn, &max_q_per_vf);
804 rcb_common->max_vfn = max_vfn;
805 rcb_common->max_q_per_vf = max_q_per_vf;
807 rcb_common->io_base = hns_rcb_common_get_vaddr(rcb_common);
808 rcb_common->phy_base = hns_rcb_common_get_paddr(rcb_common);
810 dsaf_dev->rcb_common[comm_index] = rcb_common;
814 void hns_rcb_common_free_cfg(struct dsaf_device *dsaf_dev,
817 dsaf_dev->rcb_common[comm_index] = NULL;
820 void hns_rcb_update_stats(struct hnae_queue *queue)
822 struct ring_pair_cb *ring =
823 container_of(queue, struct ring_pair_cb, q);
824 struct dsaf_device *dsaf_dev = ring->rcb_common->dsaf_dev;
825 struct ppe_common_cb *ppe_common
826 = dsaf_dev->ppe_common[ring->rcb_common->comm_index];
827 struct hns_ring_hw_stats *hw_stats = &ring->hw_stats;
829 hw_stats->rx_pkts += dsaf_read_dev(queue,
830 RCB_RING_RX_RING_PKTNUM_RECORD_REG);
831 dsaf_write_dev(queue, RCB_RING_RX_RING_PKTNUM_RECORD_REG, 0x1);
833 hw_stats->ppe_rx_ok_pkts += dsaf_read_dev(ppe_common,
834 PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG + 4 * ring->index);
835 hw_stats->ppe_rx_drop_pkts += dsaf_read_dev(ppe_common,
836 PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG + 4 * ring->index);
838 hw_stats->tx_pkts += dsaf_read_dev(queue,
839 RCB_RING_TX_RING_PKTNUM_RECORD_REG);
840 dsaf_write_dev(queue, RCB_RING_TX_RING_PKTNUM_RECORD_REG, 0x1);
842 hw_stats->ppe_tx_ok_pkts += dsaf_read_dev(ppe_common,
843 PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG + 4 * ring->index);
844 hw_stats->ppe_tx_drop_pkts += dsaf_read_dev(ppe_common,
845 PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG + 4 * ring->index);
849 *hns_rcb_get_stats - get rcb statistic
851 *@data:statistic value
853 void hns_rcb_get_stats(struct hnae_queue *queue, u64 *data)
855 u64 *regs_buff = data;
856 struct ring_pair_cb *ring =
857 container_of(queue, struct ring_pair_cb, q);
858 struct hns_ring_hw_stats *hw_stats = &ring->hw_stats;
860 regs_buff[0] = hw_stats->tx_pkts;
861 regs_buff[1] = hw_stats->ppe_tx_ok_pkts;
862 regs_buff[2] = hw_stats->ppe_tx_drop_pkts;
864 dsaf_read_dev(queue, RCB_RING_TX_RING_FBDNUM_REG);
866 regs_buff[4] = queue->tx_ring.stats.tx_pkts;
867 regs_buff[5] = queue->tx_ring.stats.tx_bytes;
868 regs_buff[6] = queue->tx_ring.stats.tx_err_cnt;
869 regs_buff[7] = queue->tx_ring.stats.io_err_cnt;
870 regs_buff[8] = queue->tx_ring.stats.sw_err_cnt;
871 regs_buff[9] = queue->tx_ring.stats.seg_pkt_cnt;
872 regs_buff[10] = queue->tx_ring.stats.restart_queue;
873 regs_buff[11] = queue->tx_ring.stats.tx_busy;
875 regs_buff[12] = hw_stats->rx_pkts;
876 regs_buff[13] = hw_stats->ppe_rx_ok_pkts;
877 regs_buff[14] = hw_stats->ppe_rx_drop_pkts;
879 dsaf_read_dev(queue, RCB_RING_RX_RING_FBDNUM_REG);
881 regs_buff[16] = queue->rx_ring.stats.rx_pkts;
882 regs_buff[17] = queue->rx_ring.stats.rx_bytes;
883 regs_buff[18] = queue->rx_ring.stats.rx_err_cnt;
884 regs_buff[19] = queue->rx_ring.stats.io_err_cnt;
885 regs_buff[20] = queue->rx_ring.stats.sw_err_cnt;
886 regs_buff[21] = queue->rx_ring.stats.seg_pkt_cnt;
887 regs_buff[22] = queue->rx_ring.stats.reuse_pg_cnt;
888 regs_buff[23] = queue->rx_ring.stats.err_pkt_len;
889 regs_buff[24] = queue->rx_ring.stats.non_vld_descs;
890 regs_buff[25] = queue->rx_ring.stats.err_bd_num;
891 regs_buff[26] = queue->rx_ring.stats.l2_err;
892 regs_buff[27] = queue->rx_ring.stats.l3l4_csum_err;
896 *hns_rcb_get_ring_sset_count - rcb string set count
897 *@stringset:ethtool cmd
898 *return rcb ring string set count
900 int hns_rcb_get_ring_sset_count(int stringset)
902 if (stringset == ETH_SS_STATS)
903 return HNS_RING_STATIC_REG_NUM;
909 *hns_rcb_get_common_regs_count - rcb common regs count
912 int hns_rcb_get_common_regs_count(void)
914 return HNS_RCB_COMMON_DUMP_REG_NUM;
918 *rcb_get_sset_count - rcb ring regs count
921 int hns_rcb_get_ring_regs_count(void)
923 return HNS_RCB_RING_DUMP_REG_NUM;
927 *hns_rcb_get_strings - get rcb string set
928 *@stringset:string set index
929 *@data:strings name value
932 void hns_rcb_get_strings(int stringset, u8 *data, int index)
934 char *buff = (char *)data;
936 if (stringset != ETH_SS_STATS)
939 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_rcb_pkt_num", index);
940 buff = buff + ETH_GSTRING_LEN;
941 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_ppe_tx_pkt_num", index);
942 buff = buff + ETH_GSTRING_LEN;
943 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_ppe_drop_pkt_num", index);
944 buff = buff + ETH_GSTRING_LEN;
945 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_fbd_num", index);
946 buff = buff + ETH_GSTRING_LEN;
948 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_pkt_num", index);
949 buff = buff + ETH_GSTRING_LEN;
950 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_bytes", index);
951 buff = buff + ETH_GSTRING_LEN;
952 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_err_cnt", index);
953 buff = buff + ETH_GSTRING_LEN;
954 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_io_err", index);
955 buff = buff + ETH_GSTRING_LEN;
956 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_sw_err", index);
957 buff = buff + ETH_GSTRING_LEN;
958 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_seg_pkt", index);
959 buff = buff + ETH_GSTRING_LEN;
960 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_restart_queue", index);
961 buff = buff + ETH_GSTRING_LEN;
962 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_tx_busy", index);
963 buff = buff + ETH_GSTRING_LEN;
965 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_rcb_pkt_num", index);
966 buff = buff + ETH_GSTRING_LEN;
967 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_ppe_pkt_num", index);
968 buff = buff + ETH_GSTRING_LEN;
969 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_ppe_drop_pkt_num", index);
970 buff = buff + ETH_GSTRING_LEN;
971 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_fbd_num", index);
972 buff = buff + ETH_GSTRING_LEN;
974 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_pkt_num", index);
975 buff = buff + ETH_GSTRING_LEN;
976 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_bytes", index);
977 buff = buff + ETH_GSTRING_LEN;
978 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_err_cnt", index);
979 buff = buff + ETH_GSTRING_LEN;
980 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_io_err", index);
981 buff = buff + ETH_GSTRING_LEN;
982 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_sw_err", index);
983 buff = buff + ETH_GSTRING_LEN;
984 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_seg_pkt", index);
985 buff = buff + ETH_GSTRING_LEN;
986 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_reuse_pg", index);
987 buff = buff + ETH_GSTRING_LEN;
988 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_len_err", index);
989 buff = buff + ETH_GSTRING_LEN;
990 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_non_vld_desc_err", index);
991 buff = buff + ETH_GSTRING_LEN;
992 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_bd_num_err", index);
993 buff = buff + ETH_GSTRING_LEN;
994 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_l2_err", index);
995 buff = buff + ETH_GSTRING_LEN;
996 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_l3l4csum_err", index);
999 void hns_rcb_get_common_regs(struct rcb_common_cb *rcb_com, void *data)
1002 bool is_ver1 = AE_IS_VER1(rcb_com->dsaf_dev->dsaf_ver);
1003 bool is_dbg = HNS_DSAF_IS_DEBUG(rcb_com->dsaf_dev);
1008 /*rcb common registers */
1009 regs[0] = dsaf_read_dev(rcb_com, RCB_COM_CFG_ENDIAN_REG);
1010 regs[1] = dsaf_read_dev(rcb_com, RCB_COM_CFG_SYS_FSH_REG);
1011 regs[2] = dsaf_read_dev(rcb_com, RCB_COM_CFG_INIT_FLAG_REG);
1013 regs[3] = dsaf_read_dev(rcb_com, RCB_COM_CFG_PKT_REG);
1014 regs[4] = dsaf_read_dev(rcb_com, RCB_COM_CFG_RINVLD_REG);
1015 regs[5] = dsaf_read_dev(rcb_com, RCB_COM_CFG_FNA_REG);
1016 regs[6] = dsaf_read_dev(rcb_com, RCB_COM_CFG_FA_REG);
1017 regs[7] = dsaf_read_dev(rcb_com, RCB_COM_CFG_PKT_TC_BP_REG);
1018 regs[8] = dsaf_read_dev(rcb_com, RCB_COM_CFG_PPE_TNL_CLKEN_REG);
1020 regs[9] = dsaf_read_dev(rcb_com, RCB_COM_INTMSK_TX_PKT_REG);
1021 regs[10] = dsaf_read_dev(rcb_com, RCB_COM_RINT_TX_PKT_REG);
1022 regs[11] = dsaf_read_dev(rcb_com, RCB_COM_INTMASK_ECC_ERR_REG);
1023 regs[12] = dsaf_read_dev(rcb_com, RCB_COM_INTSTS_ECC_ERR_REG);
1024 regs[13] = dsaf_read_dev(rcb_com, RCB_COM_EBD_SRAM_ERR_REG);
1025 regs[14] = dsaf_read_dev(rcb_com, RCB_COM_RXRING_ERR_REG);
1026 regs[15] = dsaf_read_dev(rcb_com, RCB_COM_TXRING_ERR_REG);
1027 regs[16] = dsaf_read_dev(rcb_com, RCB_COM_TX_FBD_ERR_REG);
1028 regs[17] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK_EN_REG);
1029 regs[18] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK0_REG);
1030 regs[19] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK1_REG);
1031 regs[20] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK2_REG);
1032 regs[21] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK3_REG);
1033 regs[22] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK4_REG);
1034 regs[23] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK5_REG);
1035 regs[24] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR0_REG);
1036 regs[25] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR3_REG);
1037 regs[26] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR4_REG);
1038 regs[27] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR5_REG);
1040 regs[28] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_INTMASK_RING);
1041 regs[29] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_RING_STS);
1042 regs[30] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_RING);
1043 regs[31] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_INTMASK_BD);
1044 regs[32] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_BD_RINT_STS);
1045 regs[33] = dsaf_read_dev(rcb_com, RCB_COM_RCB_RD_BD_BUSY);
1046 regs[34] = dsaf_read_dev(rcb_com, RCB_COM_RCB_FBD_CRT_EN);
1047 regs[35] = dsaf_read_dev(rcb_com, RCB_COM_AXI_WR_ERR_INTMASK);
1048 regs[36] = dsaf_read_dev(rcb_com, RCB_COM_AXI_ERR_STS);
1049 regs[37] = dsaf_read_dev(rcb_com, RCB_COM_CHK_TX_FBD_NUM_REG);
1051 /* rcb common entry registers */
1052 for (i = 0; i < 16; i++) { /* total 16 model registers */
1054 = dsaf_read_dev(rcb_com, RCB_CFG_BD_NUM_REG + 4 * i);
1056 = dsaf_read_dev(rcb_com, RCB_CFG_PKTLINE_REG + 4 * i);
1059 reg_tmp = is_ver1 ? RCB_CFG_OVERTIME_REG : RCB_PORT_CFG_OVERTIME_REG;
1060 reg_num_tmp = (is_ver1 || is_dbg) ? 1 : 6;
1061 for (i = 0; i < reg_num_tmp; i++)
1062 regs[70 + i] = dsaf_read_dev(rcb_com, reg_tmp);
1064 regs[76] = dsaf_read_dev(rcb_com, RCB_CFG_PKTLINE_INT_NUM_REG);
1065 regs[77] = dsaf_read_dev(rcb_com, RCB_CFG_OVERTIME_INT_NUM_REG);
1067 /* mark end of rcb common regs */
1068 for (i = 78; i < 80; i++)
1069 regs[i] = 0xcccccccc;
1072 void hns_rcb_get_ring_regs(struct hnae_queue *queue, void *data)
1075 struct ring_pair_cb *ring_pair
1076 = container_of(queue, struct ring_pair_cb, q);
1079 /*rcb ring registers */
1080 regs[0] = dsaf_read_dev(queue, RCB_RING_RX_RING_BASEADDR_L_REG);
1081 regs[1] = dsaf_read_dev(queue, RCB_RING_RX_RING_BASEADDR_H_REG);
1082 regs[2] = dsaf_read_dev(queue, RCB_RING_RX_RING_BD_NUM_REG);
1083 regs[3] = dsaf_read_dev(queue, RCB_RING_RX_RING_BD_LEN_REG);
1084 regs[4] = dsaf_read_dev(queue, RCB_RING_RX_RING_PKTLINE_REG);
1085 regs[5] = dsaf_read_dev(queue, RCB_RING_RX_RING_TAIL_REG);
1086 regs[6] = dsaf_read_dev(queue, RCB_RING_RX_RING_HEAD_REG);
1087 regs[7] = dsaf_read_dev(queue, RCB_RING_RX_RING_FBDNUM_REG);
1088 regs[8] = dsaf_read_dev(queue, RCB_RING_RX_RING_PKTNUM_RECORD_REG);
1090 regs[9] = dsaf_read_dev(queue, RCB_RING_TX_RING_BASEADDR_L_REG);
1091 regs[10] = dsaf_read_dev(queue, RCB_RING_TX_RING_BASEADDR_H_REG);
1092 regs[11] = dsaf_read_dev(queue, RCB_RING_TX_RING_BD_NUM_REG);
1093 regs[12] = dsaf_read_dev(queue, RCB_RING_TX_RING_BD_LEN_REG);
1094 regs[13] = dsaf_read_dev(queue, RCB_RING_TX_RING_PKTLINE_REG);
1095 regs[15] = dsaf_read_dev(queue, RCB_RING_TX_RING_TAIL_REG);
1096 regs[16] = dsaf_read_dev(queue, RCB_RING_TX_RING_HEAD_REG);
1097 regs[17] = dsaf_read_dev(queue, RCB_RING_TX_RING_FBDNUM_REG);
1098 regs[18] = dsaf_read_dev(queue, RCB_RING_TX_RING_OFFSET_REG);
1099 regs[19] = dsaf_read_dev(queue, RCB_RING_TX_RING_PKTNUM_RECORD_REG);
1101 regs[20] = dsaf_read_dev(queue, RCB_RING_PREFETCH_EN_REG);
1102 regs[21] = dsaf_read_dev(queue, RCB_RING_CFG_VF_NUM_REG);
1103 regs[22] = dsaf_read_dev(queue, RCB_RING_ASID_REG);
1104 regs[23] = dsaf_read_dev(queue, RCB_RING_RX_VM_REG);
1105 regs[24] = dsaf_read_dev(queue, RCB_RING_T0_BE_RST);
1106 regs[25] = dsaf_read_dev(queue, RCB_RING_COULD_BE_RST);
1107 regs[26] = dsaf_read_dev(queue, RCB_RING_WRR_WEIGHT_REG);
1109 regs[27] = dsaf_read_dev(queue, RCB_RING_INTMSK_RXWL_REG);
1110 regs[28] = dsaf_read_dev(queue, RCB_RING_INTSTS_RX_RING_REG);
1111 regs[29] = dsaf_read_dev(queue, RCB_RING_INTMSK_TXWL_REG);
1112 regs[30] = dsaf_read_dev(queue, RCB_RING_INTSTS_TX_RING_REG);
1113 regs[31] = dsaf_read_dev(queue, RCB_RING_INTMSK_RX_OVERTIME_REG);
1114 regs[32] = dsaf_read_dev(queue, RCB_RING_INTSTS_RX_OVERTIME_REG);
1115 regs[33] = dsaf_read_dev(queue, RCB_RING_INTMSK_TX_OVERTIME_REG);
1116 regs[34] = dsaf_read_dev(queue, RCB_RING_INTSTS_TX_OVERTIME_REG);
1118 /* mark end of ring regs */
1119 for (i = 35; i < 40; i++)
1120 regs[i] = 0xcccccc00 + ring_pair->index;