drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c

   1 /*
   2  * Copyright (c) 2014-2015 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/device.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/netdevice.h>
  17 #include <linux/mfd/syscon.h>
  18 #include <linux/of.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/vmalloc.h>
  24
  25 #include "hns_dsaf_mac.h"
  26 #include "hns_dsaf_main.h"
  27 #include "hns_dsaf_ppe.h"
  28 #include "hns_dsaf_rcb.h"
  29 #include "hns_dsaf_misc.h"
  30
  31 const char *g_dsaf_mode_match[DSAF_MODE_MAX] = {
  32         [DSAF_MODE_DISABLE_2PORT_64VM] = "2port-64vf",
  33         [DSAF_MODE_DISABLE_6PORT_0VM] = "6port-16rss",
  34         [DSAF_MODE_DISABLE_6PORT_16VM] = "6port-16vf",
  35         [DSAF_MODE_DISABLE_SP] = "single-port",
  36 };
  37
  38 static const struct acpi_device_id hns_dsaf_acpi_match[] = {
  39         { "HISI00B1", 0 },
  40         { "HISI00B2", 0 },
  41         { },
  42 };
  43 MODULE_DEVICE_TABLE(acpi, hns_dsaf_acpi_match);
  44
  45 int hns_dsaf_get_cfg(struct dsaf_device *dsaf_dev)
  46 {
  47         int ret, i;
  48         u32 desc_num;
  49         u32 buf_size;
  50         u32 reset_offset = 0;
  51         u32 res_idx = 0;
  52         const char *mode_str;
  53         struct regmap *syscon;
  54         struct resource *res;
  55         struct device_node *np = dsaf_dev->dev->of_node, *np_temp;
  56         struct platform_device *pdev = to_platform_device(dsaf_dev->dev);
  57
  58         if (dev_of_node(dsaf_dev->dev)) {
  59                 if (of_device_is_compatible(np, "hisilicon,hns-dsaf-v1"))
  60                         dsaf_dev->dsaf_ver = AE_VERSION_1;
  61                 else
  62                         dsaf_dev->dsaf_ver = AE_VERSION_2;
  63         } else if (is_acpi_node(dsaf_dev->dev->fwnode)) {
  64                 if (acpi_dev_found(hns_dsaf_acpi_match[0].id))
  65                         dsaf_dev->dsaf_ver = AE_VERSION_1;
  66                 else if (acpi_dev_found(hns_dsaf_acpi_match[1].id))
  67                         dsaf_dev->dsaf_ver = AE_VERSION_2;
  68                 else
  69                         return -ENXIO;
  70         } else {
  71                 dev_err(dsaf_dev->dev, "cannot get cfg data from of or acpi\n");
  72                 return -ENXIO;
  73         }
  74
  75         ret = device_property_read_string(dsaf_dev->dev, "mode", &mode_str);
  76         if (ret) {
  77                 dev_err(dsaf_dev->dev, "get dsaf mode fail, ret=%d!\n", ret);
  78                 return ret;
  79         }
  80         for (i = 0; i < DSAF_MODE_MAX; i++) {
  81                 if (g_dsaf_mode_match[i] &&
  82                     !strcmp(mode_str, g_dsaf_mode_match[i]))
  83                         break;
  84         }
  85         if (i >= DSAF_MODE_MAX ||
  86             i == DSAF_MODE_INVALID || i == DSAF_MODE_ENABLE) {
  87                 dev_err(dsaf_dev->dev,
  88                         "%s prs mode str fail!\n", dsaf_dev->ae_dev.name);
  89                 return -EINVAL;
  90         }
  91         dsaf_dev->dsaf_mode = (enum dsaf_mode)i;
  92
  93         if (dsaf_dev->dsaf_mode > DSAF_MODE_ENABLE)
  94                 dsaf_dev->dsaf_en = HRD_DSAF_NO_DSAF_MODE;
  95         else
  96                 dsaf_dev->dsaf_en = HRD_DSAF_MODE;
  97
  98         if ((i == DSAF_MODE_ENABLE_16VM) ||
  99             (i == DSAF_MODE_DISABLE_2PORT_8VM) ||
 100             (i == DSAF_MODE_DISABLE_6PORT_2VM))
 101                 dsaf_dev->dsaf_tc_mode = HRD_DSAF_8TC_MODE;
 102         else
 103                 dsaf_dev->dsaf_tc_mode = HRD_DSAF_4TC_MODE;
 104
 105         if (dev_of_node(dsaf_dev->dev)) {
 106                 np_temp = of_parse_phandle(np, "subctrl-syscon", 0);
 107                 syscon = syscon_node_to_regmap(np_temp);
 108                 of_node_put(np_temp);
 109                 if (IS_ERR_OR_NULL(syscon)) {
 110                         res = platform_get_resource(pdev, IORESOURCE_MEM,
 111                                                     res_idx++);
 112                         if (!res) {
 113                                 dev_err(dsaf_dev->dev, "subctrl info is needed!\n");
 114                                 return -ENOMEM;
 115                         }
 116
 117                         dsaf_dev->sc_base = devm_ioremap_resource(&pdev->dev,
 118                                                                   res);
 119                         if (IS_ERR(dsaf_dev->sc_base))
 120                                 return PTR_ERR(dsaf_dev->sc_base);
 121
 122                         res = platform_get_resource(pdev, IORESOURCE_MEM,
 123                                                     res_idx++);
 124                         if (!res) {
 125                                 dev_err(dsaf_dev->dev, "serdes-ctrl info is needed!\n");
 126                                 return -ENOMEM;
 127                         }
 128
 129                         dsaf_dev->sds_base = devm_ioremap_resource(&pdev->dev,
 130                                                                    res);
 131                         if (IS_ERR(dsaf_dev->sds_base))
 132                                 return PTR_ERR(dsaf_dev->sds_base);
 133                 } else {
 134                         dsaf_dev->sub_ctrl = syscon;
 135                 }
 136         }
 137
 138         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ppe-base");
 139         if (!res) {
 140                 res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx++);
 141                 if (!res) {
 142                         dev_err(dsaf_dev->dev, "ppe-base info is needed!\n");
 143                         return -ENOMEM;
 144                 }
 145         }
 146         dsaf_dev->ppe_base = devm_ioremap_resource(&pdev->dev, res);
 147         if (IS_ERR(dsaf_dev->ppe_base))
 148                 return PTR_ERR(dsaf_dev->ppe_base);
 149         dsaf_dev->ppe_paddr = res->start;
 150
 151         if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
 152                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 153                                                    "dsaf-base");
 154                 if (!res) {
 155                         res = platform_get_resource(pdev, IORESOURCE_MEM,
 156                                                     res_idx);
 157                         if (!res) {
 158                                 dev_err(dsaf_dev->dev,
 159                                         "dsaf-base info is needed!\n");
 160                                 return -ENOMEM;
 161                         }
 162                 }
 163                 dsaf_dev->io_base = devm_ioremap_resource(&pdev->dev, res);
 164                 if (IS_ERR(dsaf_dev->io_base))
 165                         return PTR_ERR(dsaf_dev->io_base);
 166         }
 167
 168         ret = device_property_read_u32(dsaf_dev->dev, "desc-num", &desc_num);
 169         if (ret < 0 || desc_num < HNS_DSAF_MIN_DESC_CNT ||
 170             desc_num > HNS_DSAF_MAX_DESC_CNT) {
 171                 dev_err(dsaf_dev->dev, "get desc-num(%d) fail, ret=%d!\n",
 172                         desc_num, ret);
 173                 return -EINVAL;
 174         }
 175         dsaf_dev->desc_num = desc_num;
 176
 177         ret = device_property_read_u32(dsaf_dev->dev, "reset-field-offset",
 178                                        &reset_offset);
 179         if (ret < 0) {
 180                 dev_dbg(dsaf_dev->dev,
 181                         "get reset-field-offset fail, ret=%d!\r\n", ret);
 182         }
 183         dsaf_dev->reset_offset = reset_offset;
 184
 185         ret = device_property_read_u32(dsaf_dev->dev, "buf-size", &buf_size);
 186         if (ret < 0) {
 187                 dev_err(dsaf_dev->dev,
 188                         "get buf-size fail, ret=%d!\r\n", ret);
 189                 return ret;
 190         }
 191         dsaf_dev->buf_size = buf_size;
 192
 193         dsaf_dev->buf_size_type = hns_rcb_buf_size2type(buf_size);
 194         if (dsaf_dev->buf_size_type < 0) {
 195                 dev_err(dsaf_dev->dev,
 196                         "buf_size(%d) is wrong!\n", buf_size);
 197                 return -EINVAL;
 198         }
 199
 200         dsaf_dev->misc_op = hns_misc_op_get(dsaf_dev);
 201         if (!dsaf_dev->misc_op)
 202                 return -ENOMEM;
 203
 204         if (!dma_set_mask_and_coherent(dsaf_dev->dev, DMA_BIT_MASK(64ULL)))
 205                 dev_dbg(dsaf_dev->dev, "set mask to 64bit\n");
 206         else
 207                 dev_err(dsaf_dev->dev, "set mask to 64bit fail!\n");
 208
 209         return 0;
 210 }
 211
 212 /**
 213  * hns_dsaf_sbm_link_sram_init_en - config dsaf_sbm_init_en
 214  * @dsaf_id: dsa fabric id
 215  */
 216 static void hns_dsaf_sbm_link_sram_init_en(struct dsaf_device *dsaf_dev)
 217 {
 218         dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG, DSAF_CFG_SBM_INIT_S, 1);
 219 }
 220
 221 /**
 222  * hns_dsaf_reg_cnt_clr_ce - config hns_dsaf_reg_cnt_clr_ce
 223  * @dsaf_id: dsa fabric id
 224  * @hns_dsaf_reg_cnt_clr_ce: config value
 225  */
 226 static void
 227 hns_dsaf_reg_cnt_clr_ce(struct dsaf_device *dsaf_dev, u32 reg_cnt_clr_ce)
 228 {
 229         dsaf_set_dev_bit(dsaf_dev, DSAF_DSA_REG_CNT_CLR_CE_REG,
 230                          DSAF_CNT_CLR_CE_S, reg_cnt_clr_ce);
 231 }
 232
 233 /**
 234  * hns_ppe_qid_cfg - config ppe qid
 235  * @dsaf_id: dsa fabric id
 236  * @pppe_qid_cfg: value array
 237  */
 238 static void
 239 hns_dsaf_ppe_qid_cfg(struct dsaf_device *dsaf_dev, u32 qid_cfg)
 240 {
 241         u32 i;
 242
 243         for (i = 0; i < DSAF_COMM_CHN; i++) {
 244                 dsaf_set_dev_field(dsaf_dev,
 245                                    DSAF_PPE_QID_CFG_0_REG + 0x0004 * i,
 246                                    DSAF_PPE_QID_CFG_M, DSAF_PPE_QID_CFG_S,
 247                                    qid_cfg);
 248         }
 249 }
 250
 251 static void hns_dsaf_mix_def_qid_cfg(struct dsaf_device *dsaf_dev)
 252 {
 253         u16 max_q_per_vf, max_vfn;
 254         u32 q_id, q_num_per_port;
 255         u32 i;
 256
 257         hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf);
 258         q_num_per_port = max_vfn * max_q_per_vf;
 259
 260         for (i = 0, q_id = 0; i < DSAF_SERVICE_NW_NUM; i++) {
 261                 dsaf_set_dev_field(dsaf_dev,
 262                                    DSAF_MIX_DEF_QID_0_REG + 0x0004 * i,
 263                                    0xff, 0, q_id);
 264                 q_id += q_num_per_port;
 265         }
 266 }
 267
 268 static void hns_dsaf_inner_qid_cfg(struct dsaf_device *dsaf_dev)
 269 {
 270         u16 max_q_per_vf, max_vfn;
 271         u32 q_id, q_num_per_port;
 272         u32 mac_id;
 273
 274         if (AE_IS_VER1(dsaf_dev->dsaf_ver))
 275                 return;
 276
 277         hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf);
 278         q_num_per_port = max_vfn * max_q_per_vf;
 279
 280         for (mac_id = 0, q_id = 0; mac_id < DSAF_SERVICE_NW_NUM; mac_id++) {
 281                 dsaf_set_dev_field(dsaf_dev,
 282                                    DSAFV2_SERDES_LBK_0_REG + 4 * mac_id,
 283                                    DSAFV2_SERDES_LBK_QID_M,
 284                                    DSAFV2_SERDES_LBK_QID_S,
 285                                    q_id);
 286                 q_id += q_num_per_port;
 287         }
 288 }
 289
 290 /**
 291  * hns_dsaf_sw_port_type_cfg - cfg sw type
 292  * @dsaf_id: dsa fabric id
 293  * @psw_port_type: array
 294  */
 295 static void hns_dsaf_sw_port_type_cfg(struct dsaf_device *dsaf_dev,
 296                                       enum dsaf_sw_port_type port_type)
 297 {
 298         u32 i;
 299
 300         for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
 301                 dsaf_set_dev_field(dsaf_dev,
 302                                    DSAF_SW_PORT_TYPE_0_REG + 0x0004 * i,
 303                                    DSAF_SW_PORT_TYPE_M, DSAF_SW_PORT_TYPE_S,
 304                                    port_type);
 305         }
 306 }
 307
 308 /**
 309  * hns_dsaf_stp_port_type_cfg - cfg stp type
 310  * @dsaf_id: dsa fabric id
 311  * @pstp_port_type: array
 312  */
 313 static void hns_dsaf_stp_port_type_cfg(struct dsaf_device *dsaf_dev,
 314                                        enum dsaf_stp_port_type port_type)
 315 {
 316         u32 i;
 317
 318         for (i = 0; i < DSAF_COMM_CHN; i++) {
 319                 dsaf_set_dev_field(dsaf_dev,
 320                                    DSAF_STP_PORT_TYPE_0_REG + 0x0004 * i,
 321                                    DSAF_STP_PORT_TYPE_M, DSAF_STP_PORT_TYPE_S,
 322                                    port_type);
 323         }
 324 }
 325
 326 #define HNS_DSAF_SBM_NUM(dev) \
 327         (AE_IS_VER1((dev)->dsaf_ver) ? DSAF_SBM_NUM : DSAFV2_SBM_NUM)
 328 /**
 329  * hns_dsaf_sbm_cfg - config sbm
 330  * @dsaf_id: dsa fabric id
 331  */
 332 static void hns_dsaf_sbm_cfg(struct dsaf_device *dsaf_dev)
 333 {
 334         u32 o_sbm_cfg;
 335         u32 i;
 336
 337         for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 338                 o_sbm_cfg = dsaf_read_dev(dsaf_dev,
 339                                           DSAF_SBM_CFG_REG_0_REG + 0x80 * i);
 340                 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_EN_S, 1);
 341                 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_SHCUT_EN_S, 0);
 342                 dsaf_write_dev(dsaf_dev,
 343                                DSAF_SBM_CFG_REG_0_REG + 0x80 * i, o_sbm_cfg);
 344         }
 345 }
 346
 347 /**
 348  * hns_dsaf_sbm_cfg_mib_en - config sbm
 349  * @dsaf_id: dsa fabric id
 350  */
 351 static int hns_dsaf_sbm_cfg_mib_en(struct dsaf_device *dsaf_dev)
 352 {
 353         u32 sbm_cfg_mib_en;
 354         u32 i;
 355         u32 reg;
 356         u32 read_cnt;
 357
 358         /* validate configure by setting SBM_CFG_MIB_EN bit from 0 to 1. */
 359         for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 360                 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
 361                 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 0);
 362         }
 363
 364         for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 365                 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
 366                 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 1);
 367         }
 368
 369         /* waitint for all sbm enable finished */
 370         for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 371                 read_cnt = 0;
 372                 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
 373                 do {
 374                         udelay(1);
 375                         sbm_cfg_mib_en = dsaf_get_dev_bit(
 376                                         dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S);
 377                         read_cnt++;
 378                 } while (sbm_cfg_mib_en == 0 &&
 379                         read_cnt < DSAF_CFG_READ_CNT);
 380
 381                 if (sbm_cfg_mib_en == 0) {
 382                         dev_err(dsaf_dev->dev,
 383                                 "sbm_cfg_mib_en fail,%s,sbm_num=%d\n",
 384                                 dsaf_dev->ae_dev.name, i);
 385                         return -ENODEV;
 386                 }
 387         }
 388
 389         return 0;
 390 }
 391
 392 /**
 393  * hns_dsaf_sbm_bp_wl_cfg - config sbm
 394  * @dsaf_id: dsa fabric id
 395  */
 396 static void hns_dsaf_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev)
 397 {
 398         u32 o_sbm_bp_cfg;
 399         u32 reg;
 400         u32 i;
 401
 402         /* XGE */
 403         for (i = 0; i < DSAF_XGE_NUM; i++) {
 404                 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i;
 405                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 406                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M,
 407                                DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S, 512);
 408                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M,
 409                                DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0);
 410                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M,
 411                                DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0);
 412                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 413
 414                 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i;
 415                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 416                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M,
 417                                DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0);
 418                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M,
 419                                DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0);
 420                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 421
 422                 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i;
 423                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 424                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
 425                                DSAF_SBM_CFG2_SET_BUF_NUM_S, 104);
 426                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
 427                                DSAF_SBM_CFG2_RESET_BUF_NUM_S, 128);
 428                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 429
 430                 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i;
 431                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 432                 dsaf_set_field(o_sbm_bp_cfg,
 433                                DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
 434                                DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 110);
 435                 dsaf_set_field(o_sbm_bp_cfg,
 436                                DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
 437                                DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 160);
 438                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 439
 440                 /* for no enable pfc mode */
 441                 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i;
 442                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 443                 dsaf_set_field(o_sbm_bp_cfg,
 444                                DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
 445                                DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 128);
 446                 dsaf_set_field(o_sbm_bp_cfg,
 447                                DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
 448                                DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 192);
 449                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 450         }
 451
 452         /* PPE */
 453         for (i = 0; i < DSAF_COMM_CHN; i++) {
 454                 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i;
 455                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 456                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
 457                                DSAF_SBM_CFG2_SET_BUF_NUM_S, 10);
 458                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
 459                                DSAF_SBM_CFG2_RESET_BUF_NUM_S, 12);
 460                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 461         }
 462
 463         /* RoCEE */
 464         for (i = 0; i < DSAF_COMM_CHN; i++) {
 465                 reg = DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i;
 466                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 467                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
 468                                DSAF_SBM_CFG2_SET_BUF_NUM_S, 2);
 469                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
 470                                DSAF_SBM_CFG2_RESET_BUF_NUM_S, 4);
 471                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 472         }
 473 }
 474
 475 static void hns_dsafv2_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev)
 476 {
 477         u32 o_sbm_bp_cfg;
 478         u32 reg;
 479         u32 i;
 480
 481         /* XGE */
 482         for (i = 0; i < DSAFV2_SBM_XGE_CHN; i++) {
 483                 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i;
 484                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 485                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M,
 486                                DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_S, 256);
 487                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M,
 488                                DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0);
 489                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M,
 490                                DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0);
 491                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 492
 493                 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i;
 494                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 495                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M,
 496                                DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0);
 497                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M,
 498                                DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0);
 499                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 500
 501                 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i;
 502                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 503                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_SET_BUF_NUM_M,
 504                                DSAFV2_SBM_CFG2_SET_BUF_NUM_S, 104);
 505                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_RESET_BUF_NUM_M,
 506                                DSAFV2_SBM_CFG2_RESET_BUF_NUM_S, 128);
 507                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 508
 509                 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i;
 510                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 511                 dsaf_set_field(o_sbm_bp_cfg,
 512                                DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
 513                                DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 55);
 514                 dsaf_set_field(o_sbm_bp_cfg,
 515                                DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
 516                                DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 110);
 517                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 518
 519                 /* for no enable pfc mode */
 520                 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i;
 521                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 522                 dsaf_set_field(o_sbm_bp_cfg,
 523                                DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M,
 524                                DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S, 128);
 525                 dsaf_set_field(o_sbm_bp_cfg,
 526                                DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M,
 527                                DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S, 192);
 528                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 529         }
 530
 531         /* PPE */
 532         for (i = 0; i < DSAFV2_SBM_PPE_CHN; i++) {
 533                 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i;
 534                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 535                 dsaf_set_field(o_sbm_bp_cfg,
 536                                DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_M,
 537                                DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_S, 2);
 538                 dsaf_set_field(o_sbm_bp_cfg,
 539                                DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_M,
 540                                DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_S, 3);
 541                 dsaf_set_field(o_sbm_bp_cfg,
 542                                DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_M,
 543                                DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_S, 52);
 544                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 545         }
 546
 547         /* RoCEE */
 548         for (i = 0; i < DASFV2_ROCEE_CRD_NUM; i++) {
 549                 reg = DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i;
 550                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 551                 dsaf_set_field(o_sbm_bp_cfg,
 552                                DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_M,
 553                                DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_S, 2);
 554                 dsaf_set_field(o_sbm_bp_cfg,
 555                                DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_M,
 556                                DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_S, 4);
 557                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 558         }
 559 }
 560
 561 /**
 562  * hns_dsaf_voq_bp_all_thrd_cfg -  voq
 563  * @dsaf_id: dsa fabric id
 564  */
 565 static void hns_dsaf_voq_bp_all_thrd_cfg(struct dsaf_device *dsaf_dev)
 566 {
 567         u32 voq_bp_all_thrd;
 568         u32 i;
 569
 570         for (i = 0; i < DSAF_VOQ_NUM; i++) {
 571                 voq_bp_all_thrd = dsaf_read_dev(
 572                         dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i);
 573                 if (i < DSAF_XGE_NUM) {
 574                         dsaf_set_field(voq_bp_all_thrd,
 575                                        DSAF_VOQ_BP_ALL_DOWNTHRD_M,
 576                                        DSAF_VOQ_BP_ALL_DOWNTHRD_S, 930);
 577                         dsaf_set_field(voq_bp_all_thrd,
 578                                        DSAF_VOQ_BP_ALL_UPTHRD_M,
 579                                        DSAF_VOQ_BP_ALL_UPTHRD_S, 950);
 580                 } else {
 581                         dsaf_set_field(voq_bp_all_thrd,
 582                                        DSAF_VOQ_BP_ALL_DOWNTHRD_M,
 583                                        DSAF_VOQ_BP_ALL_DOWNTHRD_S, 220);
 584                         dsaf_set_field(voq_bp_all_thrd,
 585                                        DSAF_VOQ_BP_ALL_UPTHRD_M,
 586                                        DSAF_VOQ_BP_ALL_UPTHRD_S, 230);
 587                 }
 588                 dsaf_write_dev(
 589                         dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i,
 590                         voq_bp_all_thrd);
 591         }
 592 }
 593
 594 static void hns_dsaf_tbl_tcam_match_cfg(
 595         struct dsaf_device *dsaf_dev,
 596         struct dsaf_tbl_tcam_data *ptbl_tcam_data)
 597 {
 598         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MATCH_CFG_L_REG,
 599                        ptbl_tcam_data->tbl_tcam_data_low);
 600         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MATCH_CFG_H_REG,
 601                        ptbl_tcam_data->tbl_tcam_data_high);
 602 }
 603
 604 /**
 605  * hns_dsaf_tbl_tcam_data_cfg - tbl
 606  * @dsaf_id: dsa fabric id
 607  * @ptbl_tcam_data: addr
 608  */
 609 static void hns_dsaf_tbl_tcam_data_cfg(
 610         struct dsaf_device *dsaf_dev,
 611         struct dsaf_tbl_tcam_data *ptbl_tcam_data)
 612 {
 613         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_LOW_0_REG,
 614                        ptbl_tcam_data->tbl_tcam_data_low);
 615         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_HIGH_0_REG,
 616                        ptbl_tcam_data->tbl_tcam_data_high);
 617 }
 618
 619 /**
 620  * dsaf_tbl_tcam_mcast_cfg - tbl
 621  * @dsaf_id: dsa fabric id
 622  * @ptbl_tcam_mcast: addr
 623  */
 624 static void hns_dsaf_tbl_tcam_mcast_cfg(
 625         struct dsaf_device *dsaf_dev,
 626         struct dsaf_tbl_tcam_mcast_cfg *mcast)
 627 {
 628         u32 mcast_cfg4;
 629
 630         mcast_cfg4 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
 631         dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S,
 632                      mcast->tbl_mcast_item_vld);
 633         dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_OLD_EN_S,
 634                      mcast->tbl_mcast_old_en);
 635         dsaf_set_field(mcast_cfg4, DSAF_TBL_MCAST_CFG4_VM128_112_M,
 636                        DSAF_TBL_MCAST_CFG4_VM128_112_S,
 637                        mcast->tbl_mcast_port_msk[4]);
 638         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, mcast_cfg4);
 639
 640         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG,
 641                        mcast->tbl_mcast_port_msk[3]);
 642
 643         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG,
 644                        mcast->tbl_mcast_port_msk[2]);
 645
 646         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG,
 647                        mcast->tbl_mcast_port_msk[1]);
 648
 649         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG,
 650                        mcast->tbl_mcast_port_msk[0]);
 651 }
 652
 653 /**
 654  * hns_dsaf_tbl_tcam_ucast_cfg - tbl
 655  * @dsaf_id: dsa fabric id
 656  * @ptbl_tcam_ucast: addr
 657  */
 658 static void hns_dsaf_tbl_tcam_ucast_cfg(
 659         struct dsaf_device *dsaf_dev,
 660         struct dsaf_tbl_tcam_ucast_cfg *tbl_tcam_ucast)
 661 {
 662         u32 ucast_cfg1;
 663
 664         ucast_cfg1 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
 665         dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S,
 666                      tbl_tcam_ucast->tbl_ucast_mac_discard);
 667         dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_ITEM_VLD_S,
 668                      tbl_tcam_ucast->tbl_ucast_item_vld);
 669         dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OLD_EN_S,
 670                      tbl_tcam_ucast->tbl_ucast_old_en);
 671         dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_DVC_S,
 672                      tbl_tcam_ucast->tbl_ucast_dvc);
 673         dsaf_set_field(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
 674                        DSAF_TBL_UCAST_CFG1_OUT_PORT_S,
 675                        tbl_tcam_ucast->tbl_ucast_out_port);
 676         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG, ucast_cfg1);
 677 }
 678
 679 /**
 680  * hns_dsaf_tbl_line_cfg - tbl
 681  * @dsaf_id: dsa fabric id
 682  * @ptbl_lin: addr
 683  */
 684 static void hns_dsaf_tbl_line_cfg(struct dsaf_device *dsaf_dev,
 685                                   struct dsaf_tbl_line_cfg *tbl_lin)
 686 {
 687         u32 tbl_line;
 688
 689         tbl_line = dsaf_read_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG);
 690         dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_MAC_DISCARD_S,
 691                      tbl_lin->tbl_line_mac_discard);
 692         dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_DVC_S,
 693                      tbl_lin->tbl_line_dvc);
 694         dsaf_set_field(tbl_line, DSAF_TBL_LINE_CFG_OUT_PORT_M,
 695                        DSAF_TBL_LINE_CFG_OUT_PORT_S,
 696                        tbl_lin->tbl_line_out_port);
 697         dsaf_write_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG, tbl_line);
 698 }
 699
 700 /**
 701  * hns_dsaf_tbl_tcam_mcast_pul - tbl
 702  * @dsaf_id: dsa fabric id
 703  */
 704 static void hns_dsaf_tbl_tcam_mcast_pul(struct dsaf_device *dsaf_dev)
 705 {
 706         u32 o_tbl_pul;
 707
 708         o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 709         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1);
 710         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 711         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0);
 712         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 713 }
 714
 715 /**
 716  * hns_dsaf_tbl_line_pul - tbl
 717  * @dsaf_id: dsa fabric id
 718  */
 719 static void hns_dsaf_tbl_line_pul(struct dsaf_device *dsaf_dev)
 720 {
 721         u32 tbl_pul;
 722
 723         tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 724         dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 1);
 725         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
 726         dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 0);
 727         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
 728 }
 729
 730 /**
 731  * hns_dsaf_tbl_tcam_data_mcast_pul - tbl
 732  * @dsaf_id: dsa fabric id
 733  */
 734 static void hns_dsaf_tbl_tcam_data_mcast_pul(
 735         struct dsaf_device *dsaf_dev)
 736 {
 737         u32 o_tbl_pul;
 738
 739         o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 740         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1);
 741         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1);
 742         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 743         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0);
 744         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0);
 745         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 746 }
 747
 748 /**
 749  * hns_dsaf_tbl_tcam_data_ucast_pul - tbl
 750  * @dsaf_id: dsa fabric id
 751  */
 752 static void hns_dsaf_tbl_tcam_data_ucast_pul(
 753         struct dsaf_device *dsaf_dev)
 754 {
 755         u32 o_tbl_pul;
 756
 757         o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 758         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1);
 759         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 1);
 760         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 761         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0);
 762         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 0);
 763         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 764 }
 765
 766 void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en)
 767 {
 768         if (AE_IS_VER1(dsaf_dev->dsaf_ver) && !HNS_DSAF_IS_DEBUG(dsaf_dev))
 769                 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG,
 770                                  DSAF_CFG_MIX_MODE_S, !!en);
 771 }
 772
 773 /**
 774  * hns_dsaf_tbl_stat_en - tbl
 775  * @dsaf_id: dsa fabric id
 776  * @ptbl_stat_en: addr
 777  */
 778 static void hns_dsaf_tbl_stat_en(struct dsaf_device *dsaf_dev)
 779 {
 780         u32 o_tbl_ctrl;
 781
 782         o_tbl_ctrl = dsaf_read_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG);
 783         dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S, 1);
 784         dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_UC_LKUP_NUM_EN_S, 1);
 785         dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_MC_LKUP_NUM_EN_S, 1);
 786         dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_BC_LKUP_NUM_EN_S, 1);
 787         dsaf_write_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG, o_tbl_ctrl);
 788 }
 789
 790 /**
 791  * hns_dsaf_rocee_bp_en - rocee back press enable
 792  * @dsaf_id: dsa fabric id
 793  */
 794 static void hns_dsaf_rocee_bp_en(struct dsaf_device *dsaf_dev)
 795 {
 796         if (AE_IS_VER1(dsaf_dev->dsaf_ver))
 797                 dsaf_set_dev_bit(dsaf_dev, DSAF_XGE_CTRL_SIG_CFG_0_REG,
 798                                  DSAF_FC_XGE_TX_PAUSE_S, 1);
 799 }
 800
 801 /* set msk for dsaf exception irq*/
 802 static void hns_dsaf_int_xge_msk_set(struct dsaf_device *dsaf_dev,
 803                                      u32 chnn_num, u32 mask_set)
 804 {
 805         dsaf_write_dev(dsaf_dev,
 806                        DSAF_XGE_INT_MSK_0_REG + 0x4 * chnn_num, mask_set);
 807 }
 808
 809 static void hns_dsaf_int_ppe_msk_set(struct dsaf_device *dsaf_dev,
 810                                      u32 chnn_num, u32 msk_set)
 811 {
 812         dsaf_write_dev(dsaf_dev,
 813                        DSAF_PPE_INT_MSK_0_REG + 0x4 * chnn_num, msk_set);
 814 }
 815
 816 static void hns_dsaf_int_rocee_msk_set(struct dsaf_device *dsaf_dev,
 817                                        u32 chnn, u32 msk_set)
 818 {
 819         dsaf_write_dev(dsaf_dev,
 820                        DSAF_ROCEE_INT_MSK_0_REG + 0x4 * chnn, msk_set);
 821 }
 822
 823 static void
 824 hns_dsaf_int_tbl_msk_set(struct dsaf_device *dsaf_dev, u32 msk_set)
 825 {
 826         dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_MSK_0_REG, msk_set);
 827 }
 828
 829 /* clr dsaf exception irq*/
 830 static void hns_dsaf_int_xge_src_clr(struct dsaf_device *dsaf_dev,
 831                                      u32 chnn_num, u32 int_src)
 832 {
 833         dsaf_write_dev(dsaf_dev,
 834                        DSAF_XGE_INT_SRC_0_REG + 0x4 * chnn_num, int_src);
 835 }
 836
 837 static void hns_dsaf_int_ppe_src_clr(struct dsaf_device *dsaf_dev,
 838                                      u32 chnn, u32 int_src)
 839 {
 840         dsaf_write_dev(dsaf_dev,
 841                        DSAF_PPE_INT_SRC_0_REG + 0x4 * chnn, int_src);
 842 }
 843
 844 static void hns_dsaf_int_rocee_src_clr(struct dsaf_device *dsaf_dev,
 845                                        u32 chnn, u32 int_src)
 846 {
 847         dsaf_write_dev(dsaf_dev,
 848                        DSAF_ROCEE_INT_SRC_0_REG + 0x4 * chnn, int_src);
 849 }
 850
 851 static void hns_dsaf_int_tbl_src_clr(struct dsaf_device *dsaf_dev,
 852                                      u32 int_src)
 853 {
 854         dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_SRC_0_REG, int_src);
 855 }
 856
 857 /**
 858  * hns_dsaf_single_line_tbl_cfg - INT
 859  * @dsaf_id: dsa fabric id
 860  * @address:
 861  * @ptbl_line:
 862  */
 863 static void hns_dsaf_single_line_tbl_cfg(
 864         struct dsaf_device *dsaf_dev,
 865         u32 address, struct dsaf_tbl_line_cfg *ptbl_line)
 866 {
 867         spin_lock_bh(&dsaf_dev->tcam_lock);
 868
 869         /*Write Addr*/
 870         hns_dsaf_tbl_line_addr_cfg(dsaf_dev, address);
 871
 872         /*Write Line*/
 873         hns_dsaf_tbl_line_cfg(dsaf_dev, ptbl_line);
 874
 875         /*Write Plus*/
 876         hns_dsaf_tbl_line_pul(dsaf_dev);
 877
 878         spin_unlock_bh(&dsaf_dev->tcam_lock);
 879 }
 880
 881 /**
 882  * hns_dsaf_tcam_uc_cfg - INT
 883  * @dsaf_id: dsa fabric id
 884  * @address,
 885  * @ptbl_tcam_data,
 886  */
 887 static void hns_dsaf_tcam_uc_cfg(
 888         struct dsaf_device *dsaf_dev, u32 address,
 889         struct dsaf_tbl_tcam_data *ptbl_tcam_data,
 890         struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast)
 891 {
 892         spin_lock_bh(&dsaf_dev->tcam_lock);
 893
 894         /*Write Addr*/
 895         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 896         /*Write Tcam Data*/
 897         hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data);
 898         /*Write Tcam Ucast*/
 899         hns_dsaf_tbl_tcam_ucast_cfg(dsaf_dev, ptbl_tcam_ucast);
 900         /*Write Plus*/
 901         hns_dsaf_tbl_tcam_data_ucast_pul(dsaf_dev);
 902
 903         spin_unlock_bh(&dsaf_dev->tcam_lock);
 904 }
 905
 906 /**
 907  * hns_dsaf_tcam_mc_cfg - cfg the tcam for mc
 908  * @dsaf_dev: dsa fabric device struct pointer
 909  * @address: tcam index
 910  * @ptbl_tcam_data: tcam data struct pointer
 911  * @ptbl_tcam_mcast: tcam mask struct pointer, it must be null for HNSv1
 912  */
 913 static void hns_dsaf_tcam_mc_cfg(
 914         struct dsaf_device *dsaf_dev, u32 address,
 915         struct dsaf_tbl_tcam_data *ptbl_tcam_data,
 916         struct dsaf_tbl_tcam_data *ptbl_tcam_mask,
 917         struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast)
 918 {
 919         spin_lock_bh(&dsaf_dev->tcam_lock);
 920
 921         /*Write Addr*/
 922         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 923         /*Write Tcam Data*/
 924         hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data);
 925         /*Write Tcam Mcast*/
 926         hns_dsaf_tbl_tcam_mcast_cfg(dsaf_dev, ptbl_tcam_mcast);
 927         /* Write Match Data */
 928         if (ptbl_tcam_mask)
 929                 hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, ptbl_tcam_mask);
 930
 931         /* Write Puls */
 932         hns_dsaf_tbl_tcam_data_mcast_pul(dsaf_dev);
 933
 934         spin_unlock_bh(&dsaf_dev->tcam_lock);
 935 }
 936
 937 /**
 938  * hns_dsaf_tcam_mc_invld - INT
 939  * @dsaf_id: dsa fabric id
 940  * @address
 941  */
 942 static void hns_dsaf_tcam_mc_invld(struct dsaf_device *dsaf_dev, u32 address)
 943 {
 944         spin_lock_bh(&dsaf_dev->tcam_lock);
 945
 946         /*Write Addr*/
 947         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 948
 949         /*write tcam mcast*/
 950         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG, 0);
 951         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG, 0);
 952         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG, 0);
 953         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG, 0);
 954         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, 0);
 955
 956         /*Write Plus*/
 957         hns_dsaf_tbl_tcam_mcast_pul(dsaf_dev);
 958
 959         spin_unlock_bh(&dsaf_dev->tcam_lock);
 960 }
 961
 962 void hns_dsaf_tcam_addr_get(struct dsaf_drv_tbl_tcam_key *mac_key, u8 *addr)
 963 {
 964         addr[0] = mac_key->high.bits.mac_0;
 965         addr[1] = mac_key->high.bits.mac_1;
 966         addr[2] = mac_key->high.bits.mac_2;
 967         addr[3] = mac_key->high.bits.mac_3;
 968         addr[4] = mac_key->low.bits.mac_4;
 969         addr[5] = mac_key->low.bits.mac_5;
 970 }
 971
 972 /**
 973  * hns_dsaf_tcam_uc_get - INT
 974  * @dsaf_id: dsa fabric id
 975  * @address
 976  * @ptbl_tcam_data
 977  * @ptbl_tcam_ucast
 978  */
 979 static void hns_dsaf_tcam_uc_get(
 980         struct dsaf_device *dsaf_dev, u32 address,
 981         struct dsaf_tbl_tcam_data *ptbl_tcam_data,
 982         struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast)
 983 {
 984         u32 tcam_read_data0;
 985         u32 tcam_read_data4;
 986
 987         spin_lock_bh(&dsaf_dev->tcam_lock);
 988
 989         /*Write Addr*/
 990         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 991
 992         /*read tcam item puls*/
 993         hns_dsaf_tbl_tcam_load_pul(dsaf_dev);
 994
 995         /*read tcam data*/
 996         ptbl_tcam_data->tbl_tcam_data_high
 997                 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
 998         ptbl_tcam_data->tbl_tcam_data_low
 999                 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
1000
1001         /*read tcam mcast*/
1002         tcam_read_data0 = dsaf_read_dev(dsaf_dev,
1003                                         DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
1004         tcam_read_data4 = dsaf_read_dev(dsaf_dev,
1005                                         DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
1006
1007         ptbl_tcam_ucast->tbl_ucast_item_vld
1008                 = dsaf_get_bit(tcam_read_data4,
1009                                DSAF_TBL_MCAST_CFG4_ITEM_VLD_S);
1010         ptbl_tcam_ucast->tbl_ucast_old_en
1011                 = dsaf_get_bit(tcam_read_data4, DSAF_TBL_MCAST_CFG4_OLD_EN_S);
1012         ptbl_tcam_ucast->tbl_ucast_mac_discard
1013                 = dsaf_get_bit(tcam_read_data0,
1014                                DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S);
1015         ptbl_tcam_ucast->tbl_ucast_out_port
1016                 = dsaf_get_field(tcam_read_data0,
1017                                  DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
1018                                  DSAF_TBL_UCAST_CFG1_OUT_PORT_S);
1019         ptbl_tcam_ucast->tbl_ucast_dvc
1020                 = dsaf_get_bit(tcam_read_data0, DSAF_TBL_UCAST_CFG1_DVC_S);
1021
1022         spin_unlock_bh(&dsaf_dev->tcam_lock);
1023 }
1024
1025 /**
1026  * hns_dsaf_tcam_mc_get - INT
1027  * @dsaf_id: dsa fabric id
1028  * @address
1029  * @ptbl_tcam_data
1030  * @ptbl_tcam_ucast
1031  */
1032 static void hns_dsaf_tcam_mc_get(
1033         struct dsaf_device *dsaf_dev, u32 address,
1034         struct dsaf_tbl_tcam_data *ptbl_tcam_data,
1035         struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast)
1036 {
1037         u32 data_tmp;
1038
1039         spin_lock_bh(&dsaf_dev->tcam_lock);
1040
1041         /*Write Addr*/
1042         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
1043
1044         /*read tcam item puls*/
1045         hns_dsaf_tbl_tcam_load_pul(dsaf_dev);
1046
1047         /*read tcam data*/
1048         ptbl_tcam_data->tbl_tcam_data_high =
1049                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
1050         ptbl_tcam_data->tbl_tcam_data_low =
1051                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
1052
1053         /*read tcam mcast*/
1054         ptbl_tcam_mcast->tbl_mcast_port_msk[0] =
1055                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
1056         ptbl_tcam_mcast->tbl_mcast_port_msk[1] =
1057                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
1058         ptbl_tcam_mcast->tbl_mcast_port_msk[2] =
1059                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
1060         ptbl_tcam_mcast->tbl_mcast_port_msk[3] =
1061                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
1062
1063         data_tmp = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
1064         ptbl_tcam_mcast->tbl_mcast_item_vld =
1065                 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S);
1066         ptbl_tcam_mcast->tbl_mcast_old_en =
1067                 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_OLD_EN_S);
1068         ptbl_tcam_mcast->tbl_mcast_port_msk[4] =
1069                 dsaf_get_field(data_tmp, DSAF_TBL_MCAST_CFG4_VM128_112_M,
1070                                DSAF_TBL_MCAST_CFG4_VM128_112_S);
1071
1072         spin_unlock_bh(&dsaf_dev->tcam_lock);
1073 }
1074
1075 /**
1076  * hns_dsaf_tbl_line_init - INT
1077  * @dsaf_id: dsa fabric id
1078  */
1079 static void hns_dsaf_tbl_line_init(struct dsaf_device *dsaf_dev)
1080 {
1081         u32 i;
1082         /* defaultly set all lineal mac table entry resulting discard */
1083         struct dsaf_tbl_line_cfg tbl_line[] = {{1, 0, 0} };
1084
1085         for (i = 0; i < DSAF_LINE_SUM; i++)
1086                 hns_dsaf_single_line_tbl_cfg(dsaf_dev, i, tbl_line);
1087 }
1088
1089 /**
1090  * hns_dsaf_tbl_tcam_init - INT
1091  * @dsaf_id: dsa fabric id
1092  */
1093 static void hns_dsaf_tbl_tcam_init(struct dsaf_device *dsaf_dev)
1094 {
1095         u32 i;
1096         struct dsaf_tbl_tcam_data tcam_data[] = {{0, 0} };
1097         struct dsaf_tbl_tcam_ucast_cfg tcam_ucast[] = {{0, 0, 0, 0, 0} };
1098
1099         /*tcam tbl*/
1100         for (i = 0; i < DSAF_TCAM_SUM; i++)
1101                 hns_dsaf_tcam_uc_cfg(dsaf_dev, i, tcam_data, tcam_ucast);
1102 }
1103
1104 /**
1105  * hns_dsaf_pfc_en_cfg - dsaf pfc pause cfg
1106  * @mac_cb: mac contrl block
1107  */
1108 static void hns_dsaf_pfc_en_cfg(struct dsaf_device *dsaf_dev,
1109                                 int mac_id, int tc_en)
1110 {
1111         dsaf_write_dev(dsaf_dev, DSAF_PFC_EN_0_REG + mac_id * 4, tc_en);
1112 }
1113
1114 static void hns_dsaf_set_pfc_pause(struct dsaf_device *dsaf_dev,
1115                                    int mac_id, int tx_en, int rx_en)
1116 {
1117         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1118                 if (!tx_en || !rx_en)
1119                         dev_err(dsaf_dev->dev, "dsaf v1 can not close pfc!\n");
1120
1121                 return;
1122         }
1123
1124         dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1125                          DSAF_PFC_PAUSE_RX_EN_B, !!rx_en);
1126         dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1127                          DSAF_PFC_PAUSE_TX_EN_B, !!tx_en);
1128 }
1129
1130 int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
1131                                  u32 en)
1132 {
1133         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1134                 if (!en) {
1135                         dev_err(dsaf_dev->dev, "dsafv1 can't close rx_pause!\n");
1136                         return -EINVAL;
1137                 }
1138         }
1139
1140         dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1141                          DSAF_MAC_PAUSE_RX_EN_B, !!en);
1142
1143         return 0;
1144 }
1145
1146 void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
1147                                   u32 *en)
1148 {
1149         if (AE_IS_VER1(dsaf_dev->dsaf_ver))
1150                 *en = 1;
1151         else
1152                 *en = dsaf_get_dev_bit(dsaf_dev,
1153                                        DSAF_PAUSE_CFG_REG + mac_id * 4,
1154                                        DSAF_MAC_PAUSE_RX_EN_B);
1155 }
1156
1157 /**
1158  * hns_dsaf_tbl_tcam_init - INT
1159  * @dsaf_id: dsa fabric id
1160  * @dsaf_mode
1161  */
1162 static void hns_dsaf_comm_init(struct dsaf_device *dsaf_dev)
1163 {
1164         u32 i;
1165         u32 o_dsaf_cfg;
1166         bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
1167
1168         o_dsaf_cfg = dsaf_read_dev(dsaf_dev, DSAF_CFG_0_REG);
1169         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_EN_S, dsaf_dev->dsaf_en);
1170         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_TC_MODE_S, dsaf_dev->dsaf_tc_mode);
1171         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_CRC_EN_S, 0);
1172         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_MIX_MODE_S, 0);
1173         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_LOCA_ADDR_EN_S, 0);
1174         dsaf_write_dev(dsaf_dev, DSAF_CFG_0_REG, o_dsaf_cfg);
1175
1176         hns_dsaf_reg_cnt_clr_ce(dsaf_dev, 1);
1177         hns_dsaf_stp_port_type_cfg(dsaf_dev, DSAF_STP_PORT_TYPE_FORWARD);
1178
1179         /* set 22 queue per tx ppe engine, only used in switch mode */
1180         hns_dsaf_ppe_qid_cfg(dsaf_dev, DSAF_DEFAUTL_QUEUE_NUM_PER_PPE);
1181
1182         /* set promisc def queue id */
1183         hns_dsaf_mix_def_qid_cfg(dsaf_dev);
1184
1185         /* set inner loopback queue id */
1186         hns_dsaf_inner_qid_cfg(dsaf_dev);
1187
1188         /* in non switch mode, set all port to access mode */
1189         hns_dsaf_sw_port_type_cfg(dsaf_dev, DSAF_SW_PORT_TYPE_NON_VLAN);
1190
1191         /*set dsaf pfc  to 0 for parseing rx pause*/
1192         for (i = 0; i < DSAF_COMM_CHN; i++) {
1193                 hns_dsaf_pfc_en_cfg(dsaf_dev, i, 0);
1194                 hns_dsaf_set_pfc_pause(dsaf_dev, i, is_ver1, is_ver1);
1195         }
1196
1197         /*msk and  clr exception irqs */
1198         for (i = 0; i < DSAF_COMM_CHN; i++) {
1199                 hns_dsaf_int_xge_src_clr(dsaf_dev, i, 0xfffffffful);
1200                 hns_dsaf_int_ppe_src_clr(dsaf_dev, i, 0xfffffffful);
1201                 hns_dsaf_int_rocee_src_clr(dsaf_dev, i, 0xfffffffful);
1202
1203                 hns_dsaf_int_xge_msk_set(dsaf_dev, i, 0xfffffffful);
1204                 hns_dsaf_int_ppe_msk_set(dsaf_dev, i, 0xfffffffful);
1205                 hns_dsaf_int_rocee_msk_set(dsaf_dev, i, 0xfffffffful);
1206         }
1207         hns_dsaf_int_tbl_src_clr(dsaf_dev, 0xfffffffful);
1208         hns_dsaf_int_tbl_msk_set(dsaf_dev, 0xfffffffful);
1209 }
1210
1211 /**
1212  * hns_dsaf_inode_init - INT
1213  * @dsaf_id: dsa fabric id
1214  */
1215 static void hns_dsaf_inode_init(struct dsaf_device *dsaf_dev)
1216 {
1217         u32 reg;
1218         u32 tc_cfg;
1219         u32 i;
1220
1221         if (dsaf_dev->dsaf_tc_mode == HRD_DSAF_4TC_MODE)
1222                 tc_cfg = HNS_DSAF_I4TC_CFG;
1223         else
1224                 tc_cfg = HNS_DSAF_I8TC_CFG;
1225
1226         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1227                 for (i = 0; i < DSAF_INODE_NUM; i++) {
1228                         reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i;
1229                         dsaf_set_dev_field(dsaf_dev, reg,
1230                                            DSAF_INODE_IN_PORT_NUM_M,
1231                                            DSAF_INODE_IN_PORT_NUM_S,
1232                                            i % DSAF_XGE_NUM);
1233                 }
1234         } else {
1235                 for (i = 0; i < DSAF_PORT_TYPE_NUM; i++) {
1236                         reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i;
1237                         dsaf_set_dev_field(dsaf_dev, reg,
1238                                            DSAF_INODE_IN_PORT_NUM_M,
1239                                            DSAF_INODE_IN_PORT_NUM_S, 0);
1240                         dsaf_set_dev_field(dsaf_dev, reg,
1241                                            DSAFV2_INODE_IN_PORT1_NUM_M,
1242                                            DSAFV2_INODE_IN_PORT1_NUM_S, 1);
1243                         dsaf_set_dev_field(dsaf_dev, reg,
1244                                            DSAFV2_INODE_IN_PORT2_NUM_M,
1245                                            DSAFV2_INODE_IN_PORT2_NUM_S, 2);
1246                         dsaf_set_dev_field(dsaf_dev, reg,
1247                                            DSAFV2_INODE_IN_PORT3_NUM_M,
1248                                            DSAFV2_INODE_IN_PORT3_NUM_S, 3);
1249                         dsaf_set_dev_field(dsaf_dev, reg,
1250                                            DSAFV2_INODE_IN_PORT4_NUM_M,
1251                                            DSAFV2_INODE_IN_PORT4_NUM_S, 4);
1252                         dsaf_set_dev_field(dsaf_dev, reg,
1253                                            DSAFV2_INODE_IN_PORT5_NUM_M,
1254                                            DSAFV2_INODE_IN_PORT5_NUM_S, 5);
1255                 }
1256         }
1257         for (i = 0; i < DSAF_INODE_NUM; i++) {
1258                 reg = DSAF_INODE_PRI_TC_CFG_0_REG + 0x80 * i;
1259                 dsaf_write_dev(dsaf_dev, reg, tc_cfg);
1260         }
1261 }
1262
1263 /**
1264  * hns_dsaf_sbm_init - INT
1265  * @dsaf_id: dsa fabric id
1266  */
1267 static int hns_dsaf_sbm_init(struct dsaf_device *dsaf_dev)
1268 {
1269         u32 flag;
1270         u32 finish_msk;
1271         u32 cnt = 0;
1272         int ret;
1273
1274         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1275                 hns_dsaf_sbm_bp_wl_cfg(dsaf_dev);
1276                 finish_msk = DSAF_SRAM_INIT_OVER_M;
1277         } else {
1278                 hns_dsafv2_sbm_bp_wl_cfg(dsaf_dev);
1279                 finish_msk = DSAFV2_SRAM_INIT_OVER_M;
1280         }
1281
1282         /* enable sbm chanel, disable sbm chanel shcut function*/
1283         hns_dsaf_sbm_cfg(dsaf_dev);
1284
1285         /* enable sbm mib */
1286         ret = hns_dsaf_sbm_cfg_mib_en(dsaf_dev);
1287         if (ret) {
1288                 dev_err(dsaf_dev->dev,
1289                         "hns_dsaf_sbm_cfg_mib_en fail,%s, ret=%d\n",
1290                         dsaf_dev->ae_dev.name, ret);
1291                 return ret;
1292         }
1293
1294         /* enable sbm initial link sram */
1295         hns_dsaf_sbm_link_sram_init_en(dsaf_dev);
1296
1297         do {
1298                 usleep_range(200, 210);/*udelay(200);*/
1299                 flag = dsaf_get_dev_field(dsaf_dev, DSAF_SRAM_INIT_OVER_0_REG,
1300                                           finish_msk, DSAF_SRAM_INIT_OVER_S);
1301                 cnt++;
1302         } while (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S) &&
1303                  cnt < DSAF_CFG_READ_CNT);
1304
1305         if (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S)) {
1306                 dev_err(dsaf_dev->dev,
1307                         "hns_dsaf_sbm_init fail %s, flag=%d, cnt=%d\n",
1308                         dsaf_dev->ae_dev.name, flag, cnt);
1309                 return -ENODEV;
1310         }
1311
1312         hns_dsaf_rocee_bp_en(dsaf_dev);
1313
1314         return 0;
1315 }
1316
1317 /**
1318  * hns_dsaf_tbl_init - INT
1319  * @dsaf_id: dsa fabric id
1320  */
1321 static void hns_dsaf_tbl_init(struct dsaf_device *dsaf_dev)
1322 {
1323         hns_dsaf_tbl_stat_en(dsaf_dev);
1324
1325         hns_dsaf_tbl_tcam_init(dsaf_dev);
1326         hns_dsaf_tbl_line_init(dsaf_dev);
1327 }
1328
1329 /**
1330  * hns_dsaf_voq_init - INT
1331  * @dsaf_id: dsa fabric id
1332  */
1333 static void hns_dsaf_voq_init(struct dsaf_device *dsaf_dev)
1334 {
1335         hns_dsaf_voq_bp_all_thrd_cfg(dsaf_dev);
1336 }
1337
1338 /**
1339  * hns_dsaf_init_hw - init dsa fabric hardware
1340  * @dsaf_dev: dsa fabric device struct pointer
1341  */
1342 static int hns_dsaf_init_hw(struct dsaf_device *dsaf_dev)
1343 {
1344         int ret;
1345
1346         dev_dbg(dsaf_dev->dev,
1347                 "hns_dsaf_init_hw begin %s !\n", dsaf_dev->ae_dev.name);
1348
1349         dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0);
1350         mdelay(10);
1351         dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 1);
1352
1353         hns_dsaf_comm_init(dsaf_dev);
1354
1355         /*init XBAR_INODE*/
1356         hns_dsaf_inode_init(dsaf_dev);
1357
1358         /*init SBM*/
1359         ret = hns_dsaf_sbm_init(dsaf_dev);
1360         if (ret)
1361                 return ret;
1362
1363         /*init TBL*/
1364         hns_dsaf_tbl_init(dsaf_dev);
1365
1366         /*init VOQ*/
1367         hns_dsaf_voq_init(dsaf_dev);
1368
1369         return 0;
1370 }
1371
1372 /**
1373  * hns_dsaf_remove_hw - uninit dsa fabric hardware
1374  * @dsaf_dev: dsa fabric device struct pointer
1375  */
1376 static void hns_dsaf_remove_hw(struct dsaf_device *dsaf_dev)
1377 {
1378         /*reset*/
1379         dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0);
1380 }
1381
1382 /**
1383  * hns_dsaf_init - init dsa fabric
1384  * @dsaf_dev: dsa fabric device struct pointer
1385  * retuen 0 - success , negative --fail
1386  */
1387 static int hns_dsaf_init(struct dsaf_device *dsaf_dev)
1388 {
1389         struct dsaf_drv_priv *priv =
1390             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1391         u32 i;
1392         int ret;
1393
1394         if (HNS_DSAF_IS_DEBUG(dsaf_dev))
1395                 return 0;
1396
1397         if (AE_IS_VER1(dsaf_dev->dsaf_ver))
1398                 dsaf_dev->tcam_max_num = DSAF_TCAM_SUM;
1399         else
1400                 dsaf_dev->tcam_max_num =
1401                         DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM;
1402
1403         spin_lock_init(&dsaf_dev->tcam_lock);
1404         ret = hns_dsaf_init_hw(dsaf_dev);
1405         if (ret)
1406                 return ret;
1407
1408         /* malloc mem for tcam mac key(vlan+mac) */
1409         priv->soft_mac_tbl = vzalloc(array_size(DSAF_TCAM_SUM,
1410                                                 sizeof(*priv->soft_mac_tbl)));
1411         if (!priv->soft_mac_tbl) {
1412                 ret = -ENOMEM;
1413                 goto remove_hw;
1414         }
1415
1416         /*all entry invall */
1417         for (i = 0; i < DSAF_TCAM_SUM; i++)
1418                 (priv->soft_mac_tbl + i)->index = DSAF_INVALID_ENTRY_IDX;
1419
1420         return 0;
1421
1422 remove_hw:
1423         hns_dsaf_remove_hw(dsaf_dev);
1424         return ret;
1425 }
1426
1427 /**
1428  * hns_dsaf_free - free dsa fabric
1429  * @dsaf_dev: dsa fabric device struct pointer
1430  */
1431 static void hns_dsaf_free(struct dsaf_device *dsaf_dev)
1432 {
1433         struct dsaf_drv_priv *priv =
1434             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1435
1436         hns_dsaf_remove_hw(dsaf_dev);
1437
1438         /* free all mac mem */
1439         vfree(priv->soft_mac_tbl);
1440         priv->soft_mac_tbl = NULL;
1441 }
1442
1443 /**
1444  * hns_dsaf_find_soft_mac_entry - find dsa fabric soft entry
1445  * @dsaf_dev: dsa fabric device struct pointer
1446  * @mac_key: mac entry struct pointer
1447  */
1448 static u16 hns_dsaf_find_soft_mac_entry(
1449         struct dsaf_device *dsaf_dev,
1450         struct dsaf_drv_tbl_tcam_key *mac_key)
1451 {
1452         struct dsaf_drv_priv *priv =
1453             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1454         struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1455         u32 i;
1456
1457         soft_mac_entry = priv->soft_mac_tbl;
1458         for (i = 0; i < dsaf_dev->tcam_max_num; i++) {
1459                 /* invall tab entry */
1460                 if ((soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX) &&
1461                     (soft_mac_entry->tcam_key.high.val == mac_key->high.val) &&
1462                     (soft_mac_entry->tcam_key.low.val == mac_key->low.val))
1463                         /* return find result --soft index */
1464                         return soft_mac_entry->index;
1465
1466                 soft_mac_entry++;
1467         }
1468         return DSAF_INVALID_ENTRY_IDX;
1469 }
1470
1471 /**
1472  * hns_dsaf_find_empty_mac_entry - search dsa fabric soft empty-entry
1473  * @dsaf_dev: dsa fabric device struct pointer
1474  */
1475 static u16 hns_dsaf_find_empty_mac_entry(struct dsaf_device *dsaf_dev)
1476 {
1477         struct dsaf_drv_priv *priv =
1478             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1479         struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1480         u32 i;
1481
1482         soft_mac_entry = priv->soft_mac_tbl;
1483         for (i = 0; i < dsaf_dev->tcam_max_num; i++) {
1484                 /* inv all entry */
1485                 if (soft_mac_entry->index == DSAF_INVALID_ENTRY_IDX)
1486                         /* return find result --soft index */
1487                         return i;
1488
1489                 soft_mac_entry++;
1490         }
1491         return DSAF_INVALID_ENTRY_IDX;
1492 }
1493
1494 /**
1495  * hns_dsaf_set_mac_key - set mac key
1496  * @dsaf_dev: dsa fabric device struct pointer
1497  * @mac_key: tcam key pointer
1498  * @vlan_id: vlan id
1499  * @in_port_num: input port num
1500  * @addr: mac addr
1501  */
1502 static void hns_dsaf_set_mac_key(
1503         struct dsaf_device *dsaf_dev,
1504         struct dsaf_drv_tbl_tcam_key *mac_key, u16 vlan_id, u8 in_port_num,
1505         u8 *addr)
1506 {
1507         u8 port;
1508
1509         if (dsaf_dev->dsaf_mode <= DSAF_MODE_ENABLE)
1510                 /*DSAF mode : in port id fixed 0*/
1511                 port = 0;
1512         else
1513                 /*non-dsaf mode*/
1514                 port = in_port_num;
1515
1516         mac_key->high.bits.mac_0 = addr[0];
1517         mac_key->high.bits.mac_1 = addr[1];
1518         mac_key->high.bits.mac_2 = addr[2];
1519         mac_key->high.bits.mac_3 = addr[3];
1520         mac_key->low.bits.mac_4 = addr[4];
1521         mac_key->low.bits.mac_5 = addr[5];
1522         mac_key->low.bits.port_vlan = 0;
1523         dsaf_set_field(mac_key->low.bits.port_vlan, DSAF_TBL_TCAM_KEY_VLAN_M,
1524                        DSAF_TBL_TCAM_KEY_VLAN_S, vlan_id);
1525         dsaf_set_field(mac_key->low.bits.port_vlan, DSAF_TBL_TCAM_KEY_PORT_M,
1526                        DSAF_TBL_TCAM_KEY_PORT_S, port);
1527
1528         mac_key->low.bits.port_vlan = le16_to_cpu(mac_key->low.bits.port_vlan);
1529 }
1530
1531 /**
1532  * hns_dsaf_set_mac_uc_entry - set mac uc-entry
1533  * @dsaf_dev: dsa fabric device struct pointer
1534  * @mac_entry: uc-mac entry
1535  */
1536 int hns_dsaf_set_mac_uc_entry(
1537         struct dsaf_device *dsaf_dev,
1538         struct dsaf_drv_mac_single_dest_entry *mac_entry)
1539 {
1540         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1541         struct dsaf_drv_tbl_tcam_key mac_key;
1542         struct dsaf_tbl_tcam_ucast_cfg mac_data;
1543         struct dsaf_drv_priv *priv =
1544             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1545         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1546         struct dsaf_tbl_tcam_data tcam_data;
1547
1548         /* mac addr check */
1549         if (MAC_IS_ALL_ZEROS(mac_entry->addr) ||
1550             MAC_IS_BROADCAST(mac_entry->addr) ||
1551             MAC_IS_MULTICAST(mac_entry->addr)) {
1552                 dev_err(dsaf_dev->dev, "set_uc %s Mac %pM err!\n",
1553                         dsaf_dev->ae_dev.name, mac_entry->addr);
1554                 return -EINVAL;
1555         }
1556
1557         /* config key */
1558         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1559                              mac_entry->in_port_num, mac_entry->addr);
1560
1561         /* entry ie exist? */
1562         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1563         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1564                 /*if has not inv entry,find a empty entry */
1565                 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1566                 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1567                         /* has not empty,return error */
1568                         dev_err(dsaf_dev->dev,
1569                                 "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1570                                 dsaf_dev->ae_dev.name,
1571                                 mac_key.high.val, mac_key.low.val);
1572                         return -EINVAL;
1573                 }
1574         }
1575
1576         dev_dbg(dsaf_dev->dev,
1577                 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1578                 dsaf_dev->ae_dev.name, mac_key.high.val,
1579                 mac_key.low.val, entry_index);
1580
1581         /* config hardware entry */
1582         mac_data.tbl_ucast_item_vld = 1;
1583         mac_data.tbl_ucast_mac_discard = 0;
1584         mac_data.tbl_ucast_old_en = 0;
1585         /* default config dvc to 0 */
1586         mac_data.tbl_ucast_dvc = 0;
1587         mac_data.tbl_ucast_out_port = mac_entry->port_num;
1588         tcam_data.tbl_tcam_data_high = cpu_to_le32(mac_key.high.val);
1589         tcam_data.tbl_tcam_data_low = cpu_to_le32(mac_key.low.val);
1590
1591         hns_dsaf_tcam_uc_cfg(dsaf_dev, entry_index, &tcam_data, &mac_data);
1592
1593         /* config software entry */
1594         soft_mac_entry += entry_index;
1595         soft_mac_entry->index = entry_index;
1596         soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1597         soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1598
1599         return 0;
1600 }
1601
1602 int hns_dsaf_rm_mac_addr(
1603         struct dsaf_device *dsaf_dev,
1604         struct dsaf_drv_mac_single_dest_entry *mac_entry)
1605 {
1606         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1607         struct dsaf_tbl_tcam_ucast_cfg mac_data;
1608         struct dsaf_drv_tbl_tcam_key mac_key;
1609
1610         /* mac addr check */
1611         if (!is_valid_ether_addr(mac_entry->addr)) {
1612                 dev_err(dsaf_dev->dev, "rm_uc_addr %s Mac %pM err!\n",
1613                         dsaf_dev->ae_dev.name, mac_entry->addr);
1614                 return -EINVAL;
1615         }
1616
1617         /* config key */
1618         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1619                              mac_entry->in_port_num, mac_entry->addr);
1620
1621         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1622         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1623                 /* can not find the tcam entry, return 0 */
1624                 dev_info(dsaf_dev->dev,
1625                          "rm_uc_addr no tcam, %s Mac key(%#x:%#x)\n",
1626                          dsaf_dev->ae_dev.name,
1627                          mac_key.high.val, mac_key.low.val);
1628                 return 0;
1629         }
1630
1631         dev_dbg(dsaf_dev->dev,
1632                 "rm_uc_addr, %s Mac key(%#x:%#x) entry_index%d\n",
1633                 dsaf_dev->ae_dev.name, mac_key.high.val,
1634                 mac_key.low.val, entry_index);
1635
1636         hns_dsaf_tcam_uc_get(
1637                         dsaf_dev, entry_index,
1638                         (struct dsaf_tbl_tcam_data *)&mac_key,
1639                         &mac_data);
1640
1641         /* unicast entry not used locally should not clear */
1642         if (mac_entry->port_num != mac_data.tbl_ucast_out_port)
1643                 return -EFAULT;
1644
1645         return hns_dsaf_del_mac_entry(dsaf_dev,
1646                                       mac_entry->in_vlan_id,
1647                                       mac_entry->in_port_num,
1648                                       mac_entry->addr);
1649 }
1650
1651 static void hns_dsaf_setup_mc_mask(struct dsaf_device *dsaf_dev,
1652                                    u8 port_num, u8 *mask, u8 *addr)
1653 {
1654         if (MAC_IS_BROADCAST(addr))
1655                 memset(mask, 0xff, ETH_ALEN);
1656         else
1657                 memcpy(mask, dsaf_dev->mac_cb[port_num]->mc_mask, ETH_ALEN);
1658 }
1659
1660 static void hns_dsaf_mc_mask_bit_clear(char *dst, const char *src)
1661 {
1662         u16 *a = (u16 *)dst;
1663         const u16 *b = (const u16 *)src;
1664
1665         a[0] &= b[0];
1666         a[1] &= b[1];
1667         a[2] &= b[2];
1668 }
1669
1670 /**
1671  * hns_dsaf_add_mac_mc_port - add mac mc-port
1672  * @dsaf_dev: dsa fabric device struct pointer
1673  * @mac_entry: mc-mac entry
1674  */
1675 int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev,
1676                              struct dsaf_drv_mac_single_dest_entry *mac_entry)
1677 {
1678         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1679         struct dsaf_drv_tbl_tcam_key mac_key;
1680         struct dsaf_drv_tbl_tcam_key mask_key;
1681         struct dsaf_tbl_tcam_data *pmask_key = NULL;
1682         struct dsaf_tbl_tcam_mcast_cfg mac_data;
1683         struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
1684         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1685         struct dsaf_drv_tbl_tcam_key tmp_mac_key;
1686         struct dsaf_tbl_tcam_data tcam_data;
1687         u8 mc_addr[ETH_ALEN];
1688         int mskid;
1689
1690         /*chechk mac addr */
1691         if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
1692                 dev_err(dsaf_dev->dev, "set_entry failed,addr %pM!\n",
1693                         mac_entry->addr);
1694                 return -EINVAL;
1695         }
1696
1697         ether_addr_copy(mc_addr, mac_entry->addr);
1698         if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1699                 u8 mc_mask[ETH_ALEN];
1700
1701                 /* prepare for key data setting */
1702                 hns_dsaf_setup_mc_mask(dsaf_dev, mac_entry->in_port_num,
1703                                        mc_mask, mac_entry->addr);
1704                 hns_dsaf_mc_mask_bit_clear(mc_addr, mc_mask);
1705
1706                 /* config key mask */
1707                 hns_dsaf_set_mac_key(dsaf_dev, &mask_key,
1708                                      0x0,
1709                                      0xff,
1710                                      mc_mask);
1711
1712                 mask_key.high.val = le32_to_cpu(mask_key.high.val);
1713                 mask_key.low.val = le32_to_cpu(mask_key.low.val);
1714
1715                 pmask_key = (struct dsaf_tbl_tcam_data *)(&mask_key);
1716         }
1717
1718         /*config key */
1719         hns_dsaf_set_mac_key(
1720                 dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1721                 mac_entry->in_port_num, mc_addr);
1722
1723         memset(&mac_data, 0, sizeof(struct dsaf_tbl_tcam_mcast_cfg));
1724
1725         /* check if the tcam is exist */
1726         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1727         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1728                 /*if hasnot , find a empty*/
1729                 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1730                 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1731                         /*if hasnot empty, error*/
1732                         dev_err(dsaf_dev->dev,
1733                                 "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1734                                 dsaf_dev->ae_dev.name, mac_key.high.val,
1735                                 mac_key.low.val);
1736                         return -EINVAL;
1737                 }
1738         } else {
1739                 /* if exist, add in */
1740                 hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, &tcam_data,
1741                                      &mac_data);
1742
1743                 tmp_mac_key.high.val =
1744                         le32_to_cpu(tcam_data.tbl_tcam_data_high);
1745                 tmp_mac_key.low.val = le32_to_cpu(tcam_data.tbl_tcam_data_low);
1746         }
1747
1748         /* config hardware entry */
1749         if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) {
1750                 mskid = mac_entry->port_num;
1751         } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) {
1752                 mskid = mac_entry->port_num -
1753                         DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
1754         } else {
1755                 dev_err(dsaf_dev->dev,
1756                         "%s,pnum(%d)error,key(%#x:%#x)\n",
1757                         dsaf_dev->ae_dev.name, mac_entry->port_num,
1758                         mac_key.high.val, mac_key.low.val);
1759                 return -EINVAL;
1760         }
1761         dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 1);
1762         mac_data.tbl_mcast_old_en = 0;
1763         mac_data.tbl_mcast_item_vld = 1;
1764
1765         dev_dbg(dsaf_dev->dev,
1766                 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1767                 dsaf_dev->ae_dev.name, mac_key.high.val,
1768                 mac_key.low.val, entry_index);
1769
1770         tcam_data.tbl_tcam_data_high = cpu_to_le32(mac_key.high.val);
1771         tcam_data.tbl_tcam_data_low = cpu_to_le32(mac_key.low.val);
1772
1773         /* config mc entry with mask */
1774         hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index, &tcam_data,
1775                              pmask_key, &mac_data);
1776
1777         /*config software entry */
1778         soft_mac_entry += entry_index;
1779         soft_mac_entry->index = entry_index;
1780         soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1781         soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1782
1783         return 0;
1784 }
1785
1786 /**
1787  * hns_dsaf_del_mac_entry - del mac mc-port
1788  * @dsaf_dev: dsa fabric device struct pointer
1789  * @vlan_id: vlian id
1790  * @in_port_num: input port num
1791  * @addr : mac addr
1792  */
1793 int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id,
1794                            u8 in_port_num, u8 *addr)
1795 {
1796         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1797         struct dsaf_drv_tbl_tcam_key mac_key;
1798         struct dsaf_drv_priv *priv =
1799             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1800         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1801
1802         /*check mac addr */
1803         if (MAC_IS_ALL_ZEROS(addr) || MAC_IS_BROADCAST(addr)) {
1804                 dev_err(dsaf_dev->dev, "del_entry failed,addr %pM!\n",
1805                         addr);
1806                 return -EINVAL;
1807         }
1808
1809         /*config key */
1810         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, addr);
1811
1812         /*exist ?*/
1813         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1814         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1815                 /*not exist, error */
1816                 dev_err(dsaf_dev->dev,
1817                         "del_mac_entry failed, %s Mac key(%#x:%#x)\n",
1818                         dsaf_dev->ae_dev.name,
1819                         mac_key.high.val, mac_key.low.val);
1820                 return -EINVAL;
1821         }
1822         dev_dbg(dsaf_dev->dev,
1823                 "del_mac_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1824                 dsaf_dev->ae_dev.name, mac_key.high.val,
1825                 mac_key.low.val, entry_index);
1826
1827         /*do del opt*/
1828         hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index);
1829
1830         /*del soft emtry */
1831         soft_mac_entry += entry_index;
1832         soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
1833
1834         return 0;
1835 }
1836
1837 /**
1838  * hns_dsaf_del_mac_mc_port - del mac mc- port
1839  * @dsaf_dev: dsa fabric device struct pointer
1840  * @mac_entry: mac entry
1841  */
1842 int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev,
1843                              struct dsaf_drv_mac_single_dest_entry *mac_entry)
1844 {
1845         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1846         struct dsaf_drv_tbl_tcam_key mac_key;
1847         struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
1848         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1849         u16 vlan_id;
1850         u8 in_port_num;
1851         struct dsaf_tbl_tcam_mcast_cfg mac_data;
1852         struct dsaf_tbl_tcam_data tcam_data;
1853         int mskid;
1854         const u8 empty_msk[sizeof(mac_data.tbl_mcast_port_msk)] = {0};
1855         struct dsaf_drv_tbl_tcam_key mask_key, tmp_mac_key;
1856         struct dsaf_tbl_tcam_data *pmask_key = NULL;
1857         u8 mc_addr[ETH_ALEN];
1858
1859         if (!(void *)mac_entry) {
1860                 dev_err(dsaf_dev->dev,
1861                         "hns_dsaf_del_mac_mc_port mac_entry is NULL\n");
1862                 return -EINVAL;
1863         }
1864
1865         /*check mac addr */
1866         if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
1867                 dev_err(dsaf_dev->dev, "del_port failed, addr %pM!\n",
1868                         mac_entry->addr);
1869                 return -EINVAL;
1870         }
1871
1872         /* always mask vlan_id field */
1873         ether_addr_copy(mc_addr, mac_entry->addr);
1874
1875         if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1876                 u8 mc_mask[ETH_ALEN];
1877
1878                 /* prepare for key data setting */
1879                 hns_dsaf_setup_mc_mask(dsaf_dev, mac_entry->in_port_num,
1880                                        mc_mask, mac_entry->addr);
1881                 hns_dsaf_mc_mask_bit_clear(mc_addr, mc_mask);
1882
1883                 /* config key mask */
1884                 hns_dsaf_set_mac_key(dsaf_dev, &mask_key, 0x00, 0xff, mc_mask);
1885
1886                 mask_key.high.val = le32_to_cpu(mask_key.high.val);
1887                 mask_key.low.val = le32_to_cpu(mask_key.low.val);
1888
1889                 pmask_key = (struct dsaf_tbl_tcam_data *)(&mask_key);
1890         }
1891
1892         /* get key info */
1893         vlan_id = mac_entry->in_vlan_id;
1894         in_port_num = mac_entry->in_port_num;
1895
1896         /* config key */
1897         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, mc_addr);
1898
1899         /* check if the tcam entry is exist */
1900         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1901         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1902                 /*find none */
1903                 dev_err(dsaf_dev->dev,
1904                         "find_soft_mac_entry failed, %s Mac key(%#x:%#x)\n",
1905                         dsaf_dev->ae_dev.name,
1906                         mac_key.high.val, mac_key.low.val);
1907                 return -EINVAL;
1908         }
1909
1910         dev_dbg(dsaf_dev->dev,
1911                 "del_mac_mc_port, %s key(%#x:%#x) index%d\n",
1912                 dsaf_dev->ae_dev.name, mac_key.high.val,
1913                 mac_key.low.val, entry_index);
1914
1915         /* read entry */
1916         hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, &tcam_data, &mac_data);
1917
1918         tmp_mac_key.high.val = le32_to_cpu(tcam_data.tbl_tcam_data_high);
1919         tmp_mac_key.low.val = le32_to_cpu(tcam_data.tbl_tcam_data_low);
1920
1921         /*del the port*/
1922         if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) {
1923                 mskid = mac_entry->port_num;
1924         } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) {
1925                 mskid = mac_entry->port_num -
1926                         DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
1927         } else {
1928                 dev_err(dsaf_dev->dev,
1929                         "%s,pnum(%d)error,key(%#x:%#x)\n",
1930                         dsaf_dev->ae_dev.name, mac_entry->port_num,
1931                         mac_key.high.val, mac_key.low.val);
1932                 return -EINVAL;
1933         }
1934         dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 0);
1935
1936         /*check non port, do del entry */
1937         if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk,
1938                     sizeof(mac_data.tbl_mcast_port_msk))) {
1939                 hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index);
1940
1941                 /* del soft entry */
1942                 soft_mac_entry += entry_index;
1943                 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
1944         } else { /* not zero, just del port, update */
1945                 tcam_data.tbl_tcam_data_high = cpu_to_le32(mac_key.high.val);
1946                 tcam_data.tbl_tcam_data_low = cpu_to_le32(mac_key.low.val);
1947
1948                 hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index,
1949                                      &tcam_data,
1950                                      pmask_key, &mac_data);
1951         }
1952
1953         return 0;
1954 }
1955
1956 int hns_dsaf_clr_mac_mc_port(struct dsaf_device *dsaf_dev, u8 mac_id,
1957                              u8 port_num)
1958 {
1959         struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
1960         struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1961         struct dsaf_tbl_tcam_mcast_cfg mac_data;
1962         int ret = 0, i;
1963
1964         if (HNS_DSAF_IS_DEBUG(dsaf_dev))
1965                 return 0;
1966
1967         for (i = 0; i < DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM; i++) {
1968                 u8 addr[ETH_ALEN];
1969                 u8 port;
1970
1971                 soft_mac_entry = priv->soft_mac_tbl + i;
1972
1973                 hns_dsaf_tcam_addr_get(&soft_mac_entry->tcam_key, addr);
1974                 port = dsaf_get_field(
1975                                 soft_mac_entry->tcam_key.low.bits.port_vlan,
1976                                 DSAF_TBL_TCAM_KEY_PORT_M,
1977                                 DSAF_TBL_TCAM_KEY_PORT_S);
1978                 /* check valid tcam mc entry */
1979                 if (soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX &&
1980                     port == mac_id &&
1981                     is_multicast_ether_addr(addr) &&
1982                     !is_broadcast_ether_addr(addr)) {
1983                         const u32 empty_msk[DSAF_PORT_MSK_NUM] = {0};
1984                         struct dsaf_drv_mac_single_dest_entry mac_entry;
1985
1986                         /* disable receiving of this multicast address for
1987                          * the VF.
1988                          */
1989                         ether_addr_copy(mac_entry.addr, addr);
1990                         mac_entry.in_vlan_id = dsaf_get_field(
1991                                 soft_mac_entry->tcam_key.low.bits.port_vlan,
1992                                 DSAF_TBL_TCAM_KEY_VLAN_M,
1993                                 DSAF_TBL_TCAM_KEY_VLAN_S);
1994                         mac_entry.in_port_num = mac_id;
1995                         mac_entry.port_num = port_num;
1996                         if (hns_dsaf_del_mac_mc_port(dsaf_dev, &mac_entry)) {
1997                                 ret = -EINVAL;
1998                                 continue;
1999                         }
2000
2001                         /* disable receiving of this multicast address for
2002                          * the mac port if all VF are disable
2003                          */
2004                         hns_dsaf_tcam_mc_get(dsaf_dev, i,
2005                                              (struct dsaf_tbl_tcam_data *)
2006                                              (&soft_mac_entry->tcam_key),
2007                                              &mac_data);
2008                         dsaf_set_bit(mac_data.tbl_mcast_port_msk[mac_id / 32],
2009                                      mac_id % 32, 0);
2010                         if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk,
2011                                     sizeof(u32) * DSAF_PORT_MSK_NUM)) {
2012                                 mac_entry.port_num = mac_id;
2013                                 if (hns_dsaf_del_mac_mc_port(dsaf_dev,
2014                                                              &mac_entry)) {
2015                                         ret = -EINVAL;
2016                                         continue;
2017                                 }
2018                         }
2019                 }
2020         }
2021
2022         return ret;
2023 }
2024
2025 static struct dsaf_device *hns_dsaf_alloc_dev(struct device *dev,
2026                                               size_t sizeof_priv)
2027 {
2028         struct dsaf_device *dsaf_dev;
2029
2030         dsaf_dev = devm_kzalloc(dev,
2031                                 sizeof(*dsaf_dev) + sizeof_priv, GFP_KERNEL);
2032         if (unlikely(!dsaf_dev)) {
2033                 dsaf_dev = ERR_PTR(-ENOMEM);
2034         } else {
2035                 dsaf_dev->dev = dev;
2036                 dev_set_drvdata(dev, dsaf_dev);
2037         }
2038
2039         return dsaf_dev;
2040 }
2041
2042 /**
2043  * hns_dsaf_free_dev - free dev mem
2044  * @dev: struct device pointer
2045  */
2046 static void hns_dsaf_free_dev(struct dsaf_device *dsaf_dev)
2047 {
2048         (void)dev_set_drvdata(dsaf_dev->dev, NULL);
2049 }
2050
2051 /**
2052  * dsaf_pfc_unit_cnt - set pfc unit count
2053  * @dsaf_id: dsa fabric id
2054  * @pport_rate:  value array
2055  * @pdsaf_pfc_unit_cnt:  value array
2056  */
2057 static void hns_dsaf_pfc_unit_cnt(struct dsaf_device *dsaf_dev, int  mac_id,
2058                                   enum dsaf_port_rate_mode rate)
2059 {
2060         u32 unit_cnt;
2061
2062         switch (rate) {
2063         case DSAF_PORT_RATE_10000:
2064                 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE;
2065                 break;
2066         case DSAF_PORT_RATE_1000:
2067                 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000;
2068                 break;
2069         case DSAF_PORT_RATE_2500:
2070                 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000;
2071                 break;
2072         default:
2073                 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE;
2074         }
2075
2076         dsaf_set_dev_field(dsaf_dev,
2077                            (DSAF_PFC_UNIT_CNT_0_REG + 0x4 * (u64)mac_id),
2078                            DSAF_PFC_UNINT_CNT_M, DSAF_PFC_UNINT_CNT_S,
2079                            unit_cnt);
2080 }
2081
2082 /**
2083  * dsaf_port_work_rate_cfg - fifo
2084  * @dsaf_id: dsa fabric id
2085  * @xge_ge_work_mode
2086  */
2087 void hns_dsaf_port_work_rate_cfg(struct dsaf_device *dsaf_dev, int mac_id,
2088                                  enum dsaf_port_rate_mode rate_mode)
2089 {
2090         u32 port_work_mode;
2091
2092         port_work_mode = dsaf_read_dev(
2093                 dsaf_dev, DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id);
2094
2095         if (rate_mode == DSAF_PORT_RATE_10000)
2096                 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 1);
2097         else
2098                 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 0);
2099
2100         dsaf_write_dev(dsaf_dev,
2101                        DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id,
2102                        port_work_mode);
2103
2104         hns_dsaf_pfc_unit_cnt(dsaf_dev, mac_id, rate_mode);
2105 }
2106
2107 /**
2108  * hns_dsaf_fix_mac_mode - dsaf modify mac mode
2109  * @mac_cb: mac contrl block
2110  */
2111 void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb)
2112 {
2113         enum dsaf_port_rate_mode mode;
2114         struct dsaf_device *dsaf_dev = mac_cb->dsaf_dev;
2115         int mac_id = mac_cb->mac_id;
2116
2117         if (mac_cb->mac_type != HNAE_PORT_SERVICE)
2118                 return;
2119         if (mac_cb->phy_if == PHY_INTERFACE_MODE_XGMII)
2120                 mode = DSAF_PORT_RATE_10000;
2121         else
2122                 mode = DSAF_PORT_RATE_1000;
2123
2124         hns_dsaf_port_work_rate_cfg(dsaf_dev, mac_id, mode);
2125 }
2126
2127 static u32 hns_dsaf_get_inode_prio_reg(int index)
2128 {
2129         int base_index, offset;
2130         u32 base_addr = DSAF_INODE_IN_PRIO_PAUSE_BASE_REG;
2131
2132         base_index = (index + 1) / DSAF_REG_PER_ZONE;
2133         offset = (index + 1) % DSAF_REG_PER_ZONE;
2134
2135         return base_addr + DSAF_INODE_IN_PRIO_PAUSE_BASE_OFFSET * base_index +
2136                 DSAF_INODE_IN_PRIO_PAUSE_OFFSET * offset;
2137 }
2138
2139 void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 node_num)
2140 {
2141         struct dsaf_hw_stats *hw_stats
2142                 = &dsaf_dev->hw_stats[node_num];
2143         bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2144         int i;
2145         u32 reg_tmp;
2146
2147         hw_stats->pad_drop += dsaf_read_dev(dsaf_dev,
2148                 DSAF_INODE_PAD_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2149         hw_stats->man_pkts += dsaf_read_dev(dsaf_dev,
2150                 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + 0x80 * (u64)node_num);
2151         hw_stats->rx_pkts += dsaf_read_dev(dsaf_dev,
2152                 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + 0x80 * (u64)node_num);
2153         hw_stats->rx_pkt_id += dsaf_read_dev(dsaf_dev,
2154                 DSAF_INODE_SBM_PID_NUM_0_REG + 0x80 * (u64)node_num);
2155
2156         reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG :
2157                             DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG;
2158         hw_stats->rx_pause_frame +=
2159                 dsaf_read_dev(dsaf_dev, reg_tmp + 0x80 * (u64)node_num);
2160
2161         hw_stats->release_buf_num += dsaf_read_dev(dsaf_dev,
2162                 DSAF_INODE_SBM_RELS_NUM_0_REG + 0x80 * (u64)node_num);
2163         hw_stats->sbm_drop += dsaf_read_dev(dsaf_dev,
2164                 DSAF_INODE_SBM_DROP_NUM_0_REG + 0x80 * (u64)node_num);
2165         hw_stats->crc_false += dsaf_read_dev(dsaf_dev,
2166                 DSAF_INODE_CRC_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
2167         hw_stats->bp_drop += dsaf_read_dev(dsaf_dev,
2168                 DSAF_INODE_BP_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2169         hw_stats->rslt_drop += dsaf_read_dev(dsaf_dev,
2170                 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2171         hw_stats->local_addr_false += dsaf_read_dev(dsaf_dev,
2172                 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
2173
2174         hw_stats->vlan_drop += dsaf_read_dev(dsaf_dev,
2175                 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + 0x80 * (u64)node_num);
2176         hw_stats->stp_drop += dsaf_read_dev(dsaf_dev,
2177                 DSAF_INODE_IN_DATA_STP_DISC_0_REG + 0x80 * (u64)node_num);
2178
2179         /* pfc pause frame statistics stored in dsaf inode*/
2180         if ((node_num < DSAF_SERVICE_NW_NUM) && !is_ver1) {
2181                 for (i = 0; i < DSAF_PRIO_NR; i++) {
2182                         reg_tmp = hns_dsaf_get_inode_prio_reg(i);
2183                         hw_stats->rx_pfc[i] += dsaf_read_dev(dsaf_dev,
2184                                 reg_tmp + 0x4 * (u64)node_num);
2185                         hw_stats->tx_pfc[i] += dsaf_read_dev(dsaf_dev,
2186                                 DSAF_XOD_XGE_PFC_PRIO_CNT_BASE_REG +
2187                                 DSAF_XOD_XGE_PFC_PRIO_CNT_OFFSET * i +
2188                                 0xF0 * (u64)node_num);
2189                 }
2190         }
2191         hw_stats->tx_pkts += dsaf_read_dev(dsaf_dev,
2192                 DSAF_XOD_RCVPKT_CNT_0_REG + 0x90 * (u64)node_num);
2193 }
2194
2195 /**
2196  *hns_dsaf_get_regs - dump dsaf regs
2197  *@dsaf_dev: dsaf device
2198  *@data:data for value of regs
2199  */
2200 void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data)
2201 {
2202         u32 i = 0;
2203         u32 j;
2204         u32 *p = data;
2205         u32 reg_tmp;
2206         bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver);
2207
2208         /* dsaf common registers */
2209         p[0] = dsaf_read_dev(ddev, DSAF_SRAM_INIT_OVER_0_REG);
2210         p[1] = dsaf_read_dev(ddev, DSAF_CFG_0_REG);
2211         p[2] = dsaf_read_dev(ddev, DSAF_ECC_ERR_INVERT_0_REG);
2212         p[3] = dsaf_read_dev(ddev, DSAF_ABNORMAL_TIMEOUT_0_REG);
2213         p[4] = dsaf_read_dev(ddev, DSAF_FSM_TIMEOUT_0_REG);
2214         p[5] = dsaf_read_dev(ddev, DSAF_DSA_REG_CNT_CLR_CE_REG);
2215         p[6] = dsaf_read_dev(ddev, DSAF_DSA_SBM_INF_FIFO_THRD_REG);
2216         p[7] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_SEL_REG);
2217         p[8] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_CNT_REG);
2218
2219         p[9] = dsaf_read_dev(ddev, DSAF_PFC_EN_0_REG + port * 4);
2220         p[10] = dsaf_read_dev(ddev, DSAF_PFC_UNIT_CNT_0_REG + port * 4);
2221         p[11] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4);
2222         p[12] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4);
2223         p[13] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4);
2224         p[14] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4);
2225         p[15] = dsaf_read_dev(ddev, DSAF_PPE_INT_MSK_0_REG + port * 4);
2226         p[16] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_MSK_0_REG + port * 4);
2227         p[17] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4);
2228         p[18] = dsaf_read_dev(ddev, DSAF_PPE_INT_SRC_0_REG + port * 4);
2229         p[19] =  dsaf_read_dev(ddev, DSAF_ROCEE_INT_SRC_0_REG + port * 4);
2230         p[20] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4);
2231         p[21] = dsaf_read_dev(ddev, DSAF_PPE_INT_STS_0_REG + port * 4);
2232         p[22] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_STS_0_REG + port * 4);
2233         p[23] = dsaf_read_dev(ddev, DSAF_PPE_QID_CFG_0_REG + port * 4);
2234
2235         for (i = 0; i < DSAF_SW_PORT_NUM; i++)
2236                 p[24 + i] = dsaf_read_dev(ddev,
2237                                 DSAF_SW_PORT_TYPE_0_REG + i * 4);
2238
2239         p[32] = dsaf_read_dev(ddev, DSAF_MIX_DEF_QID_0_REG + port * 4);
2240
2241         for (i = 0; i < DSAF_SW_PORT_NUM; i++)
2242                 p[33 + i] = dsaf_read_dev(ddev,
2243                                 DSAF_PORT_DEF_VLAN_0_REG + i * 4);
2244
2245         for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++)
2246                 p[41 + i] = dsaf_read_dev(ddev,
2247                                 DSAF_VM_DEF_VLAN_0_REG + i * 4);
2248
2249         /* dsaf inode registers */
2250         p[170] = dsaf_read_dev(ddev, DSAF_INODE_CUT_THROUGH_CFG_0_REG);
2251
2252         p[171] = dsaf_read_dev(ddev,
2253                         DSAF_INODE_ECC_ERR_ADDR_0_REG + port * 0x80);
2254
2255         for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
2256                 j = i * DSAF_COMM_CHN + port;
2257                 p[172 + i] = dsaf_read_dev(ddev,
2258                                 DSAF_INODE_IN_PORT_NUM_0_REG + j * 0x80);
2259                 p[175 + i] = dsaf_read_dev(ddev,
2260                                 DSAF_INODE_PRI_TC_CFG_0_REG + j * 0x80);
2261                 p[178 + i] = dsaf_read_dev(ddev,
2262                                 DSAF_INODE_BP_STATUS_0_REG + j * 0x80);
2263                 p[181 + i] = dsaf_read_dev(ddev,
2264                                 DSAF_INODE_PAD_DISCARD_NUM_0_REG + j * 0x80);
2265                 p[184 + i] = dsaf_read_dev(ddev,
2266                                 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + j * 0x80);
2267                 p[187 + i] = dsaf_read_dev(ddev,
2268                                 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + j * 0x80);
2269                 p[190 + i] = dsaf_read_dev(ddev,
2270                                 DSAF_INODE_SBM_PID_NUM_0_REG + j * 0x80);
2271                 reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG :
2272                                     DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG;
2273                 p[193 + i] = dsaf_read_dev(ddev, reg_tmp + j * 0x80);
2274                 p[196 + i] = dsaf_read_dev(ddev,
2275                                 DSAF_INODE_SBM_RELS_NUM_0_REG + j * 0x80);
2276                 p[199 + i] = dsaf_read_dev(ddev,
2277                                 DSAF_INODE_SBM_DROP_NUM_0_REG + j * 0x80);
2278                 p[202 + i] = dsaf_read_dev(ddev,
2279                                 DSAF_INODE_CRC_FALSE_NUM_0_REG + j * 0x80);
2280                 p[205 + i] = dsaf_read_dev(ddev,
2281                                 DSAF_INODE_BP_DISCARD_NUM_0_REG + j * 0x80);
2282                 p[208 + i] = dsaf_read_dev(ddev,
2283                                 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + j * 0x80);
2284                 p[211 + i] = dsaf_read_dev(ddev,
2285                         DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + j * 0x80);
2286                 p[214 + i] = dsaf_read_dev(ddev,
2287                                 DSAF_INODE_VOQ_OVER_NUM_0_REG + j * 0x80);
2288                 p[217 + i] = dsaf_read_dev(ddev,
2289                                 DSAF_INODE_BD_SAVE_STATUS_0_REG + j * 4);
2290                 p[220 + i] = dsaf_read_dev(ddev,
2291                                 DSAF_INODE_BD_ORDER_STATUS_0_REG + j * 4);
2292                 p[223 + i] = dsaf_read_dev(ddev,
2293                                 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + j * 4);
2294                 p[224 + i] = dsaf_read_dev(ddev,
2295                                 DSAF_INODE_IN_DATA_STP_DISC_0_REG + j * 4);
2296         }
2297
2298         p[227] = dsaf_read_dev(ddev, DSAF_INODE_GE_FC_EN_0_REG + port * 4);
2299
2300         for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
2301                 j = i * DSAF_COMM_CHN + port;
2302                 p[228 + i] = dsaf_read_dev(ddev,
2303                                 DSAF_INODE_VC0_IN_PKT_NUM_0_REG + j * 4);
2304         }
2305
2306         p[231] = dsaf_read_dev(ddev,
2307                 DSAF_INODE_VC1_IN_PKT_NUM_0_REG + port * 4);
2308
2309         /* dsaf inode registers */
2310         for (i = 0; i < HNS_DSAF_SBM_NUM(ddev) / DSAF_COMM_CHN; i++) {
2311                 j = i * DSAF_COMM_CHN + port;
2312                 p[232 + i] = dsaf_read_dev(ddev,
2313                                 DSAF_SBM_CFG_REG_0_REG + j * 0x80);
2314                 p[235 + i] = dsaf_read_dev(ddev,
2315                                 DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + j * 0x80);
2316                 p[238 + i] = dsaf_read_dev(ddev,
2317                                 DSAF_SBM_BP_CFG_1_REG_0_REG + j * 0x80);
2318                 p[241 + i] = dsaf_read_dev(ddev,
2319                                 DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + j * 0x80);
2320                 p[244 + i] = dsaf_read_dev(ddev,
2321                                 DSAF_SBM_FREE_CNT_0_0_REG + j * 0x80);
2322                 p[245 + i] = dsaf_read_dev(ddev,
2323                                 DSAF_SBM_FREE_CNT_1_0_REG + j * 0x80);
2324                 p[248 + i] = dsaf_read_dev(ddev,
2325                                 DSAF_SBM_BP_CNT_0_0_REG + j * 0x80);
2326                 p[251 + i] = dsaf_read_dev(ddev,
2327                                 DSAF_SBM_BP_CNT_1_0_REG + j * 0x80);
2328                 p[254 + i] = dsaf_read_dev(ddev,
2329                                 DSAF_SBM_BP_CNT_2_0_REG + j * 0x80);
2330                 p[257 + i] = dsaf_read_dev(ddev,
2331                                 DSAF_SBM_BP_CNT_3_0_REG + j * 0x80);
2332                 p[260 + i] = dsaf_read_dev(ddev,
2333                                 DSAF_SBM_INER_ST_0_REG + j * 0x80);
2334                 p[263 + i] = dsaf_read_dev(ddev,
2335                                 DSAF_SBM_MIB_REQ_FAILED_TC_0_REG + j * 0x80);
2336                 p[266 + i] = dsaf_read_dev(ddev,
2337                                 DSAF_SBM_LNK_INPORT_CNT_0_REG + j * 0x80);
2338                 p[269 + i] = dsaf_read_dev(ddev,
2339                                 DSAF_SBM_LNK_DROP_CNT_0_REG + j * 0x80);
2340                 p[272 + i] = dsaf_read_dev(ddev,
2341                                 DSAF_SBM_INF_OUTPORT_CNT_0_REG + j * 0x80);
2342                 p[275 + i] = dsaf_read_dev(ddev,
2343                                 DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG + j * 0x80);
2344                 p[278 + i] = dsaf_read_dev(ddev,
2345                                 DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG + j * 0x80);
2346                 p[281 + i] = dsaf_read_dev(ddev,
2347                                 DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG + j * 0x80);
2348                 p[284 + i] = dsaf_read_dev(ddev,
2349                                 DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG + j * 0x80);
2350                 p[287 + i] = dsaf_read_dev(ddev,
2351                                 DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG + j * 0x80);
2352                 p[290 + i] = dsaf_read_dev(ddev,
2353                                 DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG + j * 0x80);
2354                 p[293 + i] = dsaf_read_dev(ddev,
2355                                 DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG + j * 0x80);
2356                 p[296 + i] = dsaf_read_dev(ddev,
2357                                 DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG + j * 0x80);
2358                 p[299 + i] = dsaf_read_dev(ddev,
2359                                 DSAF_SBM_LNK_REQ_CNT_0_REG + j * 0x80);
2360                 p[302 + i] = dsaf_read_dev(ddev,
2361                                 DSAF_SBM_LNK_RELS_CNT_0_REG + j * 0x80);
2362                 p[305 + i] = dsaf_read_dev(ddev,
2363                                 DSAF_SBM_BP_CFG_3_REG_0_REG + j * 0x80);
2364                 p[308 + i] = dsaf_read_dev(ddev,
2365                                 DSAF_SBM_BP_CFG_4_REG_0_REG + j * 0x80);
2366         }
2367
2368         /* dsaf onode registers */
2369         for (i = 0; i < DSAF_XOD_NUM; i++) {
2370                 p[311 + i] = dsaf_read_dev(ddev,
2371                                 DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG + i * 0x90);
2372                 p[319 + i] = dsaf_read_dev(ddev,
2373                                 DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG + i * 0x90);
2374                 p[327 + i] = dsaf_read_dev(ddev,
2375                                 DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG + i * 0x90);
2376                 p[335 + i] = dsaf_read_dev(ddev,
2377                                 DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG + i * 0x90);
2378                 p[343 + i] = dsaf_read_dev(ddev,
2379                                 DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG + i * 0x90);
2380                 p[351 + i] = dsaf_read_dev(ddev,
2381                                 DSAF_XOD_ETS_TOKEN_CFG_0_REG + i * 0x90);
2382         }
2383
2384         p[359] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_0_0_REG + port * 0x90);
2385         p[360] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_1_0_REG + port * 0x90);
2386         p[361] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_2_0_REG + port * 0x90);
2387
2388         for (i = 0; i < DSAF_XOD_BIG_NUM / DSAF_COMM_CHN; i++) {
2389                 j = i * DSAF_COMM_CHN + port;
2390                 p[362 + i] = dsaf_read_dev(ddev,
2391                                 DSAF_XOD_GNT_L_0_REG + j * 0x90);
2392                 p[365 + i] = dsaf_read_dev(ddev,
2393                                 DSAF_XOD_GNT_H_0_REG + j * 0x90);
2394                 p[368 + i] = dsaf_read_dev(ddev,
2395                                 DSAF_XOD_CONNECT_STATE_0_REG + j * 0x90);
2396                 p[371 + i] = dsaf_read_dev(ddev,
2397                                 DSAF_XOD_RCVPKT_CNT_0_REG + j * 0x90);
2398                 p[374 + i] = dsaf_read_dev(ddev,
2399                                 DSAF_XOD_RCVTC0_CNT_0_REG + j * 0x90);
2400                 p[377 + i] = dsaf_read_dev(ddev,
2401                                 DSAF_XOD_RCVTC1_CNT_0_REG + j * 0x90);
2402                 p[380 + i] = dsaf_read_dev(ddev,
2403                                 DSAF_XOD_RCVTC2_CNT_0_REG + j * 0x90);
2404                 p[383 + i] = dsaf_read_dev(ddev,
2405                                 DSAF_XOD_RCVTC3_CNT_0_REG + j * 0x90);
2406                 p[386 + i] = dsaf_read_dev(ddev,
2407                                 DSAF_XOD_RCVVC0_CNT_0_REG + j * 0x90);
2408                 p[389 + i] = dsaf_read_dev(ddev,
2409                                 DSAF_XOD_RCVVC1_CNT_0_REG + j * 0x90);
2410         }
2411
2412         p[392] = dsaf_read_dev(ddev,
2413                 DSAF_XOD_XGE_RCVIN0_CNT_0_REG + port * 0x90);
2414         p[393] = dsaf_read_dev(ddev,
2415                 DSAF_XOD_XGE_RCVIN1_CNT_0_REG + port * 0x90);
2416         p[394] = dsaf_read_dev(ddev,
2417                 DSAF_XOD_XGE_RCVIN2_CNT_0_REG + port * 0x90);
2418         p[395] = dsaf_read_dev(ddev,
2419                 DSAF_XOD_XGE_RCVIN3_CNT_0_REG + port * 0x90);
2420         p[396] = dsaf_read_dev(ddev,
2421                 DSAF_XOD_XGE_RCVIN4_CNT_0_REG + port * 0x90);
2422         p[397] = dsaf_read_dev(ddev,
2423                 DSAF_XOD_XGE_RCVIN5_CNT_0_REG + port * 0x90);
2424         p[398] = dsaf_read_dev(ddev,
2425                 DSAF_XOD_XGE_RCVIN6_CNT_0_REG + port * 0x90);
2426         p[399] = dsaf_read_dev(ddev,
2427                 DSAF_XOD_XGE_RCVIN7_CNT_0_REG + port * 0x90);
2428         p[400] = dsaf_read_dev(ddev,
2429                 DSAF_XOD_PPE_RCVIN0_CNT_0_REG + port * 0x90);
2430         p[401] = dsaf_read_dev(ddev,
2431                 DSAF_XOD_PPE_RCVIN1_CNT_0_REG + port * 0x90);
2432         p[402] = dsaf_read_dev(ddev,
2433                 DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG + port * 0x90);
2434         p[403] = dsaf_read_dev(ddev,
2435                 DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG + port * 0x90);
2436         p[404] = dsaf_read_dev(ddev,
2437                 DSAF_XOD_FIFO_STATUS_0_REG + port * 0x90);
2438
2439         /* dsaf voq registers */
2440         for (i = 0; i < DSAF_VOQ_NUM / DSAF_COMM_CHN; i++) {
2441                 j = (i * DSAF_COMM_CHN + port) * 0x90;
2442                 p[405 + i] = dsaf_read_dev(ddev,
2443                         DSAF_VOQ_ECC_INVERT_EN_0_REG + j);
2444                 p[408 + i] = dsaf_read_dev(ddev,
2445                         DSAF_VOQ_SRAM_PKT_NUM_0_REG + j);
2446                 p[411 + i] = dsaf_read_dev(ddev, DSAF_VOQ_IN_PKT_NUM_0_REG + j);
2447                 p[414 + i] = dsaf_read_dev(ddev,
2448                         DSAF_VOQ_OUT_PKT_NUM_0_REG + j);
2449                 p[417 + i] = dsaf_read_dev(ddev,
2450                         DSAF_VOQ_ECC_ERR_ADDR_0_REG + j);
2451                 p[420 + i] = dsaf_read_dev(ddev, DSAF_VOQ_BP_STATUS_0_REG + j);
2452                 p[423 + i] = dsaf_read_dev(ddev, DSAF_VOQ_SPUP_IDLE_0_REG + j);
2453                 p[426 + i] = dsaf_read_dev(ddev,
2454                         DSAF_VOQ_XGE_XOD_REQ_0_0_REG + j);
2455                 p[429 + i] = dsaf_read_dev(ddev,
2456                         DSAF_VOQ_XGE_XOD_REQ_1_0_REG + j);
2457                 p[432 + i] = dsaf_read_dev(ddev,
2458                         DSAF_VOQ_PPE_XOD_REQ_0_REG + j);
2459                 p[435 + i] = dsaf_read_dev(ddev,
2460                         DSAF_VOQ_ROCEE_XOD_REQ_0_REG + j);
2461                 p[438 + i] = dsaf_read_dev(ddev,
2462                         DSAF_VOQ_BP_ALL_THRD_0_REG + j);
2463         }
2464
2465         /* dsaf tbl registers */
2466         p[441] = dsaf_read_dev(ddev, DSAF_TBL_CTRL_0_REG);
2467         p[442] = dsaf_read_dev(ddev, DSAF_TBL_INT_MSK_0_REG);
2468         p[443] = dsaf_read_dev(ddev, DSAF_TBL_INT_SRC_0_REG);
2469         p[444] = dsaf_read_dev(ddev, DSAF_TBL_INT_STS_0_REG);
2470         p[445] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_ADDR_0_REG);
2471         p[446] = dsaf_read_dev(ddev, DSAF_TBL_LINE_ADDR_0_REG);
2472         p[447] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_HIGH_0_REG);
2473         p[448] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_LOW_0_REG);
2474         p[449] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
2475         p[450] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG);
2476         p[451] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG);
2477         p[452] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG);
2478         p[453] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG);
2479         p[454] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
2480         p[455] = dsaf_read_dev(ddev, DSAF_TBL_LIN_CFG_0_REG);
2481         p[456] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
2482         p[457] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
2483         p[458] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
2484         p[459] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
2485         p[460] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
2486         p[461] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
2487         p[462] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
2488         p[463] = dsaf_read_dev(ddev, DSAF_TBL_LIN_RDATA_0_REG);
2489
2490         for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
2491                 j = i * 0x8;
2492                 p[464 + 2 * i] = dsaf_read_dev(ddev,
2493                         DSAF_TBL_DA0_MIS_INFO1_0_REG + j);
2494                 p[465 + 2 * i] = dsaf_read_dev(ddev,
2495                         DSAF_TBL_DA0_MIS_INFO0_0_REG + j);
2496         }
2497
2498         p[480] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO2_0_REG);
2499         p[481] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO1_0_REG);
2500         p[482] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO0_0_REG);
2501         p[483] = dsaf_read_dev(ddev, DSAF_TBL_PUL_0_REG);
2502         p[484] = dsaf_read_dev(ddev, DSAF_TBL_OLD_RSLT_0_REG);
2503         p[485] = dsaf_read_dev(ddev, DSAF_TBL_OLD_SCAN_VAL_0_REG);
2504         p[486] = dsaf_read_dev(ddev, DSAF_TBL_DFX_CTRL_0_REG);
2505         p[487] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_0_REG);
2506         p[488] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_2_0_REG);
2507         p[489] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_I_0_REG);
2508         p[490] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_O_0_REG);
2509         p[491] = dsaf_read_dev(ddev, DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG);
2510
2511         /* dsaf other registers */
2512         p[492] = dsaf_read_dev(ddev, DSAF_INODE_FIFO_WL_0_REG + port * 0x4);
2513         p[493] = dsaf_read_dev(ddev, DSAF_ONODE_FIFO_WL_0_REG + port * 0x4);
2514         p[494] = dsaf_read_dev(ddev, DSAF_XGE_GE_WORK_MODE_0_REG + port * 0x4);
2515         p[495] = dsaf_read_dev(ddev,
2516                 DSAF_XGE_APP_RX_LINK_UP_0_REG + port * 0x4);
2517         p[496] = dsaf_read_dev(ddev, DSAF_NETPORT_CTRL_SIG_0_REG + port * 0x4);
2518         p[497] = dsaf_read_dev(ddev, DSAF_XGE_CTRL_SIG_CFG_0_REG + port * 0x4);
2519
2520         if (!is_ver1)
2521                 p[498] = dsaf_read_dev(ddev, DSAF_PAUSE_CFG_REG + port * 0x4);
2522
2523         /* mark end of dsaf regs */
2524         for (i = 499; i < 504; i++)
2525                 p[i] = 0xdddddddd;
2526 }
2527
2528 static char *hns_dsaf_get_node_stats_strings(char *data, int node,
2529                                              struct dsaf_device *dsaf_dev)
2530 {
2531         char *buff = data;
2532         int i;
2533         bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2534
2535         snprintf(buff, ETH_GSTRING_LEN, "innod%d_pad_drop_pkts", node);
2536         buff += ETH_GSTRING_LEN;
2537         snprintf(buff, ETH_GSTRING_LEN, "innod%d_manage_pkts", node);
2538         buff += ETH_GSTRING_LEN;
2539         snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkts", node);
2540         buff += ETH_GSTRING_LEN;
2541         snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkt_id", node);
2542         buff += ETH_GSTRING_LEN;
2543         snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pause_frame", node);
2544         buff += ETH_GSTRING_LEN;
2545         snprintf(buff, ETH_GSTRING_LEN, "innod%d_release_buf_num", node);
2546         buff += ETH_GSTRING_LEN;
2547         snprintf(buff, ETH_GSTRING_LEN, "innod%d_sbm_drop_pkts", node);
2548         buff += ETH_GSTRING_LEN;
2549         snprintf(buff, ETH_GSTRING_LEN, "innod%d_crc_false_pkts", node);
2550         buff += ETH_GSTRING_LEN;
2551         snprintf(buff, ETH_GSTRING_LEN, "innod%d_bp_drop_pkts", node);
2552         buff += ETH_GSTRING_LEN;
2553         snprintf(buff, ETH_GSTRING_LEN, "innod%d_lookup_rslt_drop_pkts", node);
2554         buff += ETH_GSTRING_LEN;
2555         snprintf(buff, ETH_GSTRING_LEN, "innod%d_local_rslt_fail_pkts", node);
2556         buff += ETH_GSTRING_LEN;
2557         snprintf(buff, ETH_GSTRING_LEN, "innod%d_vlan_drop_pkts", node);
2558         buff += ETH_GSTRING_LEN;
2559         snprintf(buff, ETH_GSTRING_LEN, "innod%d_stp_drop_pkts", node);
2560         buff += ETH_GSTRING_LEN;
2561         if (node < DSAF_SERVICE_NW_NUM && !is_ver1) {
2562                 for (i = 0; i < DSAF_PRIO_NR; i++) {
2563                         snprintf(buff + 0 * ETH_GSTRING_LEN * DSAF_PRIO_NR,
2564                                  ETH_GSTRING_LEN, "inod%d_pfc_prio%d_pkts",
2565                                  node, i);
2566                         snprintf(buff + 1 * ETH_GSTRING_LEN * DSAF_PRIO_NR,
2567                                  ETH_GSTRING_LEN, "onod%d_pfc_prio%d_pkts",
2568                                  node, i);
2569                         buff += ETH_GSTRING_LEN;
2570                 }
2571                 buff += 1 * DSAF_PRIO_NR * ETH_GSTRING_LEN;
2572         }
2573         snprintf(buff, ETH_GSTRING_LEN, "onnod%d_tx_pkts", node);
2574         buff += ETH_GSTRING_LEN;
2575
2576         return buff;
2577 }
2578
2579 static u64 *hns_dsaf_get_node_stats(struct dsaf_device *ddev, u64 *data,
2580                                     int node_num)
2581 {
2582         u64 *p = data;
2583         int i;
2584         struct dsaf_hw_stats *hw_stats = &ddev->hw_stats[node_num];
2585         bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver);
2586
2587         p[0] = hw_stats->pad_drop;
2588         p[1] = hw_stats->man_pkts;
2589         p[2] = hw_stats->rx_pkts;
2590         p[3] = hw_stats->rx_pkt_id;
2591         p[4] = hw_stats->rx_pause_frame;
2592         p[5] = hw_stats->release_buf_num;
2593         p[6] = hw_stats->sbm_drop;
2594         p[7] = hw_stats->crc_false;
2595         p[8] = hw_stats->bp_drop;
2596         p[9] = hw_stats->rslt_drop;
2597         p[10] = hw_stats->local_addr_false;
2598         p[11] = hw_stats->vlan_drop;
2599         p[12] = hw_stats->stp_drop;
2600         if (node_num < DSAF_SERVICE_NW_NUM && !is_ver1) {
2601                 for (i = 0; i < DSAF_PRIO_NR; i++) {
2602                         p[13 + i + 0 * DSAF_PRIO_NR] = hw_stats->rx_pfc[i];
2603                         p[13 + i + 1 * DSAF_PRIO_NR] = hw_stats->tx_pfc[i];
2604                 }
2605                 p[29] = hw_stats->tx_pkts;
2606                 return &p[30];
2607         }
2608
2609         p[13] = hw_stats->tx_pkts;
2610         return &p[14];
2611 }
2612
2613 /**
2614  *hns_dsaf_get_stats - get dsaf statistic
2615  *@ddev: dsaf device
2616  *@data:statistic value
2617  *@port: port num
2618  */
2619 void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port)
2620 {
2621         u64 *p = data;
2622         int node_num = port;
2623
2624         /* for ge/xge node info */
2625         p = hns_dsaf_get_node_stats(ddev, p, node_num);
2626
2627         /* for ppe node info */
2628         node_num = port + DSAF_PPE_INODE_BASE;
2629         (void)hns_dsaf_get_node_stats(ddev, p, node_num);
2630 }
2631
2632 /**
2633  *hns_dsaf_get_sset_count - get dsaf string set count
2634  *@stringset: type of values in data
2635  *return dsaf string name count
2636  */
2637 int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset)
2638 {
2639         bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2640
2641         if (stringset == ETH_SS_STATS) {
2642                 if (is_ver1)
2643                         return DSAF_STATIC_NUM;
2644                 else
2645                         return DSAF_V2_STATIC_NUM;
2646         }
2647         return 0;
2648 }
2649
2650 /**
2651  *hns_dsaf_get_strings - get dsaf string set
2652  *@stringset:srting set index
2653  *@data:strings name value
2654  *@port:port index
2655  */
2656 void hns_dsaf_get_strings(int stringset, u8 *data, int port,
2657                           struct dsaf_device *dsaf_dev)
2658 {
2659         char *buff = (char *)data;
2660         int node = port;
2661
2662         if (stringset != ETH_SS_STATS)
2663                 return;
2664
2665         /* for ge/xge node info */
2666         buff = hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev);
2667
2668         /* for ppe node info */
2669         node = port + DSAF_PPE_INODE_BASE;
2670         (void)hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev);
2671 }
2672
2673 /**
2674  *hns_dsaf_get_sset_count - get dsaf regs count
2675  *return dsaf regs count
2676  */
2677 int hns_dsaf_get_regs_count(void)
2678 {
2679         return DSAF_DUMP_REGS_NUM;
2680 }
2681
2682 /* Reserve the last TCAM entry for promisc support */
2683 #define dsaf_promisc_tcam_entry(port) \
2684         (DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM + (port))
2685 void hns_dsaf_set_promisc_tcam(struct dsaf_device *dsaf_dev,
2686                                u32 port, bool enable)
2687 {
2688         struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
2689         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
2690         u16 entry_index;
2691         struct dsaf_drv_tbl_tcam_key tbl_tcam_data, tbl_tcam_mask;
2692         struct dsaf_tbl_tcam_mcast_cfg mac_data = {0};
2693
2694         if ((AE_IS_VER1(dsaf_dev->dsaf_ver)) || HNS_DSAF_IS_DEBUG(dsaf_dev))
2695                 return;
2696
2697         /* find the tcam entry index for promisc */
2698         entry_index = dsaf_promisc_tcam_entry(port);
2699
2700         memset(&tbl_tcam_data, 0, sizeof(tbl_tcam_data));
2701         memset(&tbl_tcam_mask, 0, sizeof(tbl_tcam_mask));
2702
2703         /* config key mask */
2704         if (enable) {
2705                 dsaf_set_field(tbl_tcam_data.low.bits.port_vlan,
2706                                DSAF_TBL_TCAM_KEY_PORT_M,
2707                                DSAF_TBL_TCAM_KEY_PORT_S, port);
2708                 dsaf_set_field(tbl_tcam_mask.low.bits.port_vlan,
2709                                DSAF_TBL_TCAM_KEY_PORT_M,
2710                                DSAF_TBL_TCAM_KEY_PORT_S, 0xf);
2711
2712                 /* SUB_QID */
2713                 dsaf_set_bit(mac_data.tbl_mcast_port_msk[0],
2714                              DSAF_SERVICE_NW_NUM, true);
2715                 mac_data.tbl_mcast_item_vld = true;     /* item_vld bit */
2716         } else {
2717                 mac_data.tbl_mcast_item_vld = false;    /* item_vld bit */
2718         }
2719
2720         dev_dbg(dsaf_dev->dev,
2721                 "set_promisc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
2722                 dsaf_dev->ae_dev.name, tbl_tcam_data.high.val,
2723                 tbl_tcam_data.low.val, entry_index);
2724
2725         /* config promisc entry with mask */
2726         hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index,
2727                              (struct dsaf_tbl_tcam_data *)&tbl_tcam_data,
2728                              (struct dsaf_tbl_tcam_data *)&tbl_tcam_mask,
2729                              &mac_data);
2730
2731         /* config software entry */
2732         soft_mac_entry += entry_index;
2733         soft_mac_entry->index = enable ? entry_index : DSAF_INVALID_ENTRY_IDX;
2734 }
2735
2736 /**
2737  * dsaf_probe - probo dsaf dev
2738  * @pdev: dasf platform device
2739  * retuen 0 - success , negative --fail
2740  */
2741 static int hns_dsaf_probe(struct platform_device *pdev)
2742 {
2743         struct dsaf_device *dsaf_dev;
2744         int ret;
2745
2746         dsaf_dev = hns_dsaf_alloc_dev(&pdev->dev, sizeof(struct dsaf_drv_priv));
2747         if (IS_ERR(dsaf_dev)) {
2748                 ret = PTR_ERR(dsaf_dev);
2749                 dev_err(&pdev->dev,
2750                         "dsaf_probe dsaf_alloc_dev failed, ret = %#x!\n", ret);
2751                 return ret;
2752         }
2753
2754         ret = hns_dsaf_get_cfg(dsaf_dev);
2755         if (ret)
2756                 goto free_dev;
2757
2758         ret = hns_dsaf_init(dsaf_dev);
2759         if (ret)
2760                 goto free_dev;
2761
2762         ret = hns_mac_init(dsaf_dev);
2763         if (ret)
2764                 goto uninit_dsaf;
2765
2766         ret = hns_ppe_init(dsaf_dev);
2767         if (ret)
2768                 goto uninit_mac;
2769
2770         ret = hns_dsaf_ae_init(dsaf_dev);
2771         if (ret)
2772                 goto uninit_ppe;
2773
2774         return 0;
2775
2776 uninit_ppe:
2777         hns_ppe_uninit(dsaf_dev);
2778
2779 uninit_mac:
2780         hns_mac_uninit(dsaf_dev);
2781
2782 uninit_dsaf:
2783         hns_dsaf_free(dsaf_dev);
2784
2785 free_dev:
2786         hns_dsaf_free_dev(dsaf_dev);
2787
2788         return ret;
2789 }
2790
2791 /**
2792  * dsaf_remove - remove dsaf dev
2793  * @pdev: dasf platform device
2794  */
2795 static int hns_dsaf_remove(struct platform_device *pdev)
2796 {
2797         struct dsaf_device *dsaf_dev = dev_get_drvdata(&pdev->dev);
2798
2799         hns_dsaf_ae_uninit(dsaf_dev);
2800
2801         hns_ppe_uninit(dsaf_dev);
2802
2803         hns_mac_uninit(dsaf_dev);
2804
2805         hns_dsaf_free(dsaf_dev);
2806
2807         hns_dsaf_free_dev(dsaf_dev);
2808
2809         return 0;
2810 }
2811
2812 static const struct of_device_id g_dsaf_match[] = {
2813         {.compatible = "hisilicon,hns-dsaf-v1"},
2814         {.compatible = "hisilicon,hns-dsaf-v2"},
2815         {}
2816 };
2817 MODULE_DEVICE_TABLE(of, g_dsaf_match);
2818
2819 static struct platform_driver g_dsaf_driver = {
2820         .probe = hns_dsaf_probe,
2821         .remove = hns_dsaf_remove,
2822         .driver = {
2823                 .name = DSAF_DRV_NAME,
2824                 .of_match_table = g_dsaf_match,
2825                 .acpi_match_table = hns_dsaf_acpi_match,
2826         },
2827 };
2828
2829 module_platform_driver(g_dsaf_driver);
2830
2831 /**
2832  * hns_dsaf_roce_reset - reset dsaf and roce
2833  * @dsaf_fwnode: Pointer to framework node for the dasf
2834  * @enable: false - request reset , true - drop reset
2835  * retuen 0 - success , negative -fail
2836  */
2837 int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset)
2838 {
2839         struct dsaf_device *dsaf_dev;
2840         struct platform_device *pdev;
2841         u32 mp;
2842         u32 sl;
2843         u32 credit;
2844         int i;
2845         const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
2846                 {DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
2847                 {DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
2848                 {DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
2849                 {DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
2850                 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
2851                 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
2852                 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
2853                 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
2854         };
2855         const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
2856                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
2857                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
2858                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
2859                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
2860                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
2861                 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
2862                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
2863                 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
2864         };
2865
2866         /* find the platform device corresponding to fwnode */
2867         if (is_of_node(dsaf_fwnode)) {
2868                 pdev = of_find_device_by_node(to_of_node(dsaf_fwnode));
2869         } else if (is_acpi_device_node(dsaf_fwnode)) {
2870                 pdev = hns_dsaf_find_platform_device(dsaf_fwnode);
2871         } else {
2872                 pr_err("fwnode is neither OF or ACPI type\n");
2873                 return -EINVAL;
2874         }
2875
2876         /* check if we were a success in fetching pdev */
2877         if (!pdev) {
2878                 pr_err("couldn't find platform device for node\n");
2879                 return -ENODEV;
2880         }
2881
2882         /* retrieve the dsaf_device from the driver data */
2883         dsaf_dev = dev_get_drvdata(&pdev->dev);
2884         if (!dsaf_dev) {
2885                 dev_err(&pdev->dev, "dsaf_dev is NULL\n");
2886                 return -ENODEV;
2887         }
2888
2889         /* now, make sure we are running on compatible SoC */
2890         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
2891                 dev_err(dsaf_dev->dev, "%s v1 chip doesn't support RoCE!\n",
2892                         dsaf_dev->ae_dev.name);
2893                 return -ENODEV;
2894         }
2895
2896         /* do reset or de-reset according to the flag */
2897         if (!dereset) {
2898                 /* reset rocee-channels in dsaf and rocee */
2899                 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,
2900                                                       false);
2901                 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, false);
2902         } else {
2903                 /* configure dsaf tx roce correspond to port map and sl map */
2904                 mp = dsaf_read_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG);
2905                 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
2906                         dsaf_set_field(mp, 7 << i * 3, i * 3,
2907                                        port_map[i][DSAF_ROCE_6PORT_MODE]);
2908                 dsaf_set_field(mp, 3 << i * 3, i * 3, 0);
2909                 dsaf_write_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG, mp);
2910
2911                 sl = dsaf_read_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG);
2912                 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
2913                         dsaf_set_field(sl, 3 << i * 2, i * 2,
2914                                        sl_map[i][DSAF_ROCE_6PORT_MODE]);
2915                 dsaf_write_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG, sl);
2916
2917                 /* de-reset rocee-channels in dsaf and rocee */
2918                 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,
2919                                                       true);
2920                 msleep(SRST_TIME_INTERVAL);
2921                 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, true);
2922
2923                 /* enable dsaf channel rocee credit */
2924                 credit = dsaf_read_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG);
2925                 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 0);
2926                 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
2927
2928                 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 1);
2929                 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
2930         }
2931         return 0;
2932 }
2933 EXPORT_SYMBOL(hns_dsaf_roce_reset);
2934
2935 MODULE_LICENSE("GPL");
2936 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
2937 MODULE_DESCRIPTION("HNS DSAF driver");
2938 MODULE_VERSION(DSAF_MOD_VERSION);