drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/delay.h>
  74 #include <linux/netdevice.h>
  75 #include <linux/etherdevice.h>
  76 #include <linux/skbuff.h>
  77 #include <linux/if_vlan.h>
  78 #include <linux/spinlock.h>
  79 #include <linux/mm.h>
  80 #include <linux/of_address.h>
  81 #include <linux/of_irq.h>
  82 #include <linux/of_mdio.h>
  83 #include <linux/of_platform.h>
  84 #include <linux/ip.h>
  85 #include <linux/tcp.h>
  86 #include <linux/udp.h>
  87 #include <linux/in.h>
  88 #include <linux/net_tstamp.h>
  89
  90 #include <asm/io.h>
  91 #ifdef CONFIG_PPC
  92 #include <asm/reg.h>
  93 #include <asm/mpc85xx.h>
  94 #endif
  95 #include <asm/irq.h>
  96 #include <asm/uaccess.h>
  97 #include <linux/module.h>
  98 #include <linux/dma-mapping.h>
  99 #include <linux/crc32.h>
 100 #include <linux/mii.h>
 101 #include <linux/phy.h>
 102 #include <linux/phy_fixed.h>
 103 #include <linux/of.h>
 104 #include <linux/of_net.h>
 105 #include <linux/of_address.h>
 106 #include <linux/of_irq.h>
 107
 108 #include "gianfar.h"
 109
 110 #define TX_TIMEOUT      (5*HZ)
 111
 112 const char gfar_driver_version[] = "2.0";
 113
 114 static int gfar_enet_open(struct net_device *dev);
 115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 116 static void gfar_reset_task(struct work_struct *work);
 117 static void gfar_timeout(struct net_device *dev);
 118 static int gfar_close(struct net_device *dev);
 119 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
 120                                 int alloc_cnt);
 121 static int gfar_set_mac_address(struct net_device *dev);
 122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 123 static irqreturn_t gfar_error(int irq, void *dev_id);
 124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 126 static void adjust_link(struct net_device *dev);
 127 static noinline void gfar_update_link_state(struct gfar_private *priv);
 128 static int init_phy(struct net_device *dev);
 129 static int gfar_probe(struct platform_device *ofdev);
 130 static int gfar_remove(struct platform_device *ofdev);
 131 static void free_skb_resources(struct gfar_private *priv);
 132 static void gfar_set_multi(struct net_device *dev);
 133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 134 static void gfar_configure_serdes(struct net_device *dev);
 135 static int gfar_poll_rx(struct napi_struct *napi, int budget);
 136 static int gfar_poll_tx(struct napi_struct *napi, int budget);
 137 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
 138 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
 139 #ifdef CONFIG_NET_POLL_CONTROLLER
 140 static void gfar_netpoll(struct net_device *dev);
 141 #endif
 142 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 143 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 144 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb);
 145 static void gfar_halt_nodisable(struct gfar_private *priv);
 146 static void gfar_clear_exact_match(struct net_device *dev);
 147 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 148                                   const u8 *addr);
 149 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 150
 151 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 152 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 153 MODULE_LICENSE("GPL");
 154
 155 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 156                             dma_addr_t buf)
 157 {
 158         u32 lstatus;
 159
 160         bdp->bufPtr = cpu_to_be32(buf);
 161
 162         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 163         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 164                 lstatus |= BD_LFLAG(RXBD_WRAP);
 165
 166         gfar_wmb();
 167
 168         bdp->lstatus = cpu_to_be32(lstatus);
 169 }
 170
 171 static void gfar_init_bds(struct net_device *ndev)
 172 {
 173         struct gfar_private *priv = netdev_priv(ndev);
 174         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 175         struct gfar_priv_tx_q *tx_queue = NULL;
 176         struct gfar_priv_rx_q *rx_queue = NULL;
 177         struct txbd8 *txbdp;
 178         u32 __iomem *rfbptr;
 179         int i, j;
 180
 181         for (i = 0; i < priv->num_tx_queues; i++) {
 182                 tx_queue = priv->tx_queue[i];
 183                 /* Initialize some variables in our dev structure */
 184                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 185                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 186                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 187                 tx_queue->skb_curtx = 0;
 188                 tx_queue->skb_dirtytx = 0;
 189
 190                 /* Initialize Transmit Descriptor Ring */
 191                 txbdp = tx_queue->tx_bd_base;
 192                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 193                         txbdp->lstatus = 0;
 194                         txbdp->bufPtr = 0;
 195                         txbdp++;
 196                 }
 197
 198                 /* Set the last descriptor in the ring to indicate wrap */
 199                 txbdp--;
 200                 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
 201                                             TXBD_WRAP);
 202         }
 203
 204         rfbptr = &regs->rfbptr0;
 205         for (i = 0; i < priv->num_rx_queues; i++) {
 206                 rx_queue = priv->rx_queue[i];
 207
 208                 rx_queue->next_to_clean = 0;
 209                 rx_queue->next_to_use = 0;
 210                 rx_queue->next_to_alloc = 0;
 211
 212                 /* make sure next_to_clean != next_to_use after this
 213                  * by leaving at least 1 unused descriptor
 214                  */
 215                 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
 216
 217                 rx_queue->rfbptr = rfbptr;
 218                 rfbptr += 2;
 219         }
 220 }
 221
 222 static int gfar_alloc_skb_resources(struct net_device *ndev)
 223 {
 224         void *vaddr;
 225         dma_addr_t addr;
 226         int i, j;
 227         struct gfar_private *priv = netdev_priv(ndev);
 228         struct device *dev = priv->dev;
 229         struct gfar_priv_tx_q *tx_queue = NULL;
 230         struct gfar_priv_rx_q *rx_queue = NULL;
 231
 232         priv->total_tx_ring_size = 0;
 233         for (i = 0; i < priv->num_tx_queues; i++)
 234                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 235
 236         priv->total_rx_ring_size = 0;
 237         for (i = 0; i < priv->num_rx_queues; i++)
 238                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 239
 240         /* Allocate memory for the buffer descriptors */
 241         vaddr = dma_alloc_coherent(dev,
 242                                    (priv->total_tx_ring_size *
 243                                     sizeof(struct txbd8)) +
 244                                    (priv->total_rx_ring_size *
 245                                     sizeof(struct rxbd8)),
 246                                    &addr, GFP_KERNEL);
 247         if (!vaddr)
 248                 return -ENOMEM;
 249
 250         for (i = 0; i < priv->num_tx_queues; i++) {
 251                 tx_queue = priv->tx_queue[i];
 252                 tx_queue->tx_bd_base = vaddr;
 253                 tx_queue->tx_bd_dma_base = addr;
 254                 tx_queue->dev = ndev;
 255                 /* enet DMA only understands physical addresses */
 256                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 257                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 258         }
 259
 260         /* Start the rx descriptor ring where the tx ring leaves off */
 261         for (i = 0; i < priv->num_rx_queues; i++) {
 262                 rx_queue = priv->rx_queue[i];
 263                 rx_queue->rx_bd_base = vaddr;
 264                 rx_queue->rx_bd_dma_base = addr;
 265                 rx_queue->ndev = ndev;
 266                 rx_queue->dev = dev;
 267                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 268                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 269         }
 270
 271         /* Setup the skbuff rings */
 272         for (i = 0; i < priv->num_tx_queues; i++) {
 273                 tx_queue = priv->tx_queue[i];
 274                 tx_queue->tx_skbuff =
 275                         kmalloc_array(tx_queue->tx_ring_size,
 276                                       sizeof(*tx_queue->tx_skbuff),
 277                                       GFP_KERNEL);
 278                 if (!tx_queue->tx_skbuff)
 279                         goto cleanup;
 280
 281                 for (j = 0; j < tx_queue->tx_ring_size; j++)
 282                         tx_queue->tx_skbuff[j] = NULL;
 283         }
 284
 285         for (i = 0; i < priv->num_rx_queues; i++) {
 286                 rx_queue = priv->rx_queue[i];
 287                 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
 288                                             sizeof(*rx_queue->rx_buff),
 289                                             GFP_KERNEL);
 290                 if (!rx_queue->rx_buff)
 291                         goto cleanup;
 292         }
 293
 294         gfar_init_bds(ndev);
 295
 296         return 0;
 297
 298 cleanup:
 299         free_skb_resources(priv);
 300         return -ENOMEM;
 301 }
 302
 303 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 304 {
 305         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 306         u32 __iomem *baddr;
 307         int i;
 308
 309         baddr = &regs->tbase0;
 310         for (i = 0; i < priv->num_tx_queues; i++) {
 311                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 312                 baddr += 2;
 313         }
 314
 315         baddr = &regs->rbase0;
 316         for (i = 0; i < priv->num_rx_queues; i++) {
 317                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 318                 baddr += 2;
 319         }
 320 }
 321
 322 static void gfar_init_rqprm(struct gfar_private *priv)
 323 {
 324         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 325         u32 __iomem *baddr;
 326         int i;
 327
 328         baddr = &regs->rqprm0;
 329         for (i = 0; i < priv->num_rx_queues; i++) {
 330                 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
 331                            (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
 332                 baddr++;
 333         }
 334 }
 335
 336 static void gfar_rx_offload_en(struct gfar_private *priv)
 337 {
 338         /* set this when rx hw offload (TOE) functions are being used */
 339         priv->uses_rxfcb = 0;
 340
 341         if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
 342                 priv->uses_rxfcb = 1;
 343
 344         if (priv->hwts_rx_en || priv->rx_filer_enable)
 345                 priv->uses_rxfcb = 1;
 346 }
 347
 348 static void gfar_mac_rx_config(struct gfar_private *priv)
 349 {
 350         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 351         u32 rctrl = 0;
 352
 353         if (priv->rx_filer_enable) {
 354                 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
 355                 /* Program the RIR0 reg with the required distribution */
 356                 if (priv->poll_mode == GFAR_SQ_POLLING)
 357                         gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
 358                 else /* GFAR_MQ_POLLING */
 359                         gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
 360         }
 361
 362         /* Restore PROMISC mode */
 363         if (priv->ndev->flags & IFF_PROMISC)
 364                 rctrl |= RCTRL_PROM;
 365
 366         if (priv->ndev->features & NETIF_F_RXCSUM)
 367                 rctrl |= RCTRL_CHECKSUMMING;
 368
 369         if (priv->extended_hash)
 370                 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
 371
 372         if (priv->padding) {
 373                 rctrl &= ~RCTRL_PAL_MASK;
 374                 rctrl |= RCTRL_PADDING(priv->padding);
 375         }
 376
 377         /* Enable HW time stamping if requested from user space */
 378         if (priv->hwts_rx_en)
 379                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 380
 381         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
 382                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 383
 384         /* Clear the LFC bit */
 385         gfar_write(&regs->rctrl, rctrl);
 386         /* Init flow control threshold values */
 387         gfar_init_rqprm(priv);
 388         gfar_write(&regs->ptv, DEFAULT_LFC_PTVVAL);
 389         rctrl |= RCTRL_LFC;
 390
 391         /* Init rctrl based on our settings */
 392         gfar_write(&regs->rctrl, rctrl);
 393 }
 394
 395 static void gfar_mac_tx_config(struct gfar_private *priv)
 396 {
 397         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 398         u32 tctrl = 0;
 399
 400         if (priv->ndev->features & NETIF_F_IP_CSUM)
 401                 tctrl |= TCTRL_INIT_CSUM;
 402
 403         if (priv->prio_sched_en)
 404                 tctrl |= TCTRL_TXSCHED_PRIO;
 405         else {
 406                 tctrl |= TCTRL_TXSCHED_WRRS;
 407                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 408                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 409         }
 410
 411         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
 412                 tctrl |= TCTRL_VLINS;
 413
 414         gfar_write(&regs->tctrl, tctrl);
 415 }
 416
 417 static void gfar_configure_coalescing(struct gfar_private *priv,
 418                                unsigned long tx_mask, unsigned long rx_mask)
 419 {
 420         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 421         u32 __iomem *baddr;
 422
 423         if (priv->mode == MQ_MG_MODE) {
 424                 int i = 0;
 425
 426                 baddr = &regs->txic0;
 427                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
 428                         gfar_write(baddr + i, 0);
 429                         if (likely(priv->tx_queue[i]->txcoalescing))
 430                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
 431                 }
 432
 433                 baddr = &regs->rxic0;
 434                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
 435                         gfar_write(baddr + i, 0);
 436                         if (likely(priv->rx_queue[i]->rxcoalescing))
 437                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
 438                 }
 439         } else {
 440                 /* Backward compatible case -- even if we enable
 441                  * multiple queues, there's only single reg to program
 442                  */
 443                 gfar_write(&regs->txic, 0);
 444                 if (likely(priv->tx_queue[0]->txcoalescing))
 445                         gfar_write(&regs->txic, priv->tx_queue[0]->txic);
 446
 447                 gfar_write(&regs->rxic, 0);
 448                 if (unlikely(priv->rx_queue[0]->rxcoalescing))
 449                         gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
 450         }
 451 }
 452
 453 void gfar_configure_coalescing_all(struct gfar_private *priv)
 454 {
 455         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 456 }
 457
 458 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 459 {
 460         struct gfar_private *priv = netdev_priv(dev);
 461         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 462         unsigned long tx_packets = 0, tx_bytes = 0;
 463         int i;
 464
 465         for (i = 0; i < priv->num_rx_queues; i++) {
 466                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 467                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 468                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 469         }
 470
 471         dev->stats.rx_packets = rx_packets;
 472         dev->stats.rx_bytes   = rx_bytes;
 473         dev->stats.rx_dropped = rx_dropped;
 474
 475         for (i = 0; i < priv->num_tx_queues; i++) {
 476                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 477                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 478         }
 479
 480         dev->stats.tx_bytes   = tx_bytes;
 481         dev->stats.tx_packets = tx_packets;
 482
 483         return &dev->stats;
 484 }
 485
 486 static int gfar_set_mac_addr(struct net_device *dev, void *p)
 487 {
 488         eth_mac_addr(dev, p);
 489
 490         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
 491
 492         return 0;
 493 }
 494
 495 static const struct net_device_ops gfar_netdev_ops = {
 496         .ndo_open = gfar_enet_open,
 497         .ndo_start_xmit = gfar_start_xmit,
 498         .ndo_stop = gfar_close,
 499         .ndo_change_mtu = gfar_change_mtu,
 500         .ndo_set_features = gfar_set_features,
 501         .ndo_set_rx_mode = gfar_set_multi,
 502         .ndo_tx_timeout = gfar_timeout,
 503         .ndo_do_ioctl = gfar_ioctl,
 504         .ndo_get_stats = gfar_get_stats,
 505         .ndo_set_mac_address = gfar_set_mac_addr,
 506         .ndo_validate_addr = eth_validate_addr,
 507 #ifdef CONFIG_NET_POLL_CONTROLLER
 508         .ndo_poll_controller = gfar_netpoll,
 509 #endif
 510 };
 511
 512 static void gfar_ints_disable(struct gfar_private *priv)
 513 {
 514         int i;
 515         for (i = 0; i < priv->num_grps; i++) {
 516                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 517                 /* Clear IEVENT */
 518                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 519
 520                 /* Initialize IMASK */
 521                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 522         }
 523 }
 524
 525 static void gfar_ints_enable(struct gfar_private *priv)
 526 {
 527         int i;
 528         for (i = 0; i < priv->num_grps; i++) {
 529                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 530                 /* Unmask the interrupts we look for */
 531                 gfar_write(&regs->imask, IMASK_DEFAULT);
 532         }
 533 }
 534
 535 static int gfar_alloc_tx_queues(struct gfar_private *priv)
 536 {
 537         int i;
 538
 539         for (i = 0; i < priv->num_tx_queues; i++) {
 540                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 541                                             GFP_KERNEL);
 542                 if (!priv->tx_queue[i])
 543                         return -ENOMEM;
 544
 545                 priv->tx_queue[i]->tx_skbuff = NULL;
 546                 priv->tx_queue[i]->qindex = i;
 547                 priv->tx_queue[i]->dev = priv->ndev;
 548                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 549         }
 550         return 0;
 551 }
 552
 553 static int gfar_alloc_rx_queues(struct gfar_private *priv)
 554 {
 555         int i;
 556
 557         for (i = 0; i < priv->num_rx_queues; i++) {
 558                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 559                                             GFP_KERNEL);
 560                 if (!priv->rx_queue[i])
 561                         return -ENOMEM;
 562
 563                 priv->rx_queue[i]->qindex = i;
 564                 priv->rx_queue[i]->ndev = priv->ndev;
 565         }
 566         return 0;
 567 }
 568
 569 static void gfar_free_tx_queues(struct gfar_private *priv)
 570 {
 571         int i;
 572
 573         for (i = 0; i < priv->num_tx_queues; i++)
 574                 kfree(priv->tx_queue[i]);
 575 }
 576
 577 static void gfar_free_rx_queues(struct gfar_private *priv)
 578 {
 579         int i;
 580
 581         for (i = 0; i < priv->num_rx_queues; i++)
 582                 kfree(priv->rx_queue[i]);
 583 }
 584
 585 static void unmap_group_regs(struct gfar_private *priv)
 586 {
 587         int i;
 588
 589         for (i = 0; i < MAXGROUPS; i++)
 590                 if (priv->gfargrp[i].regs)
 591                         iounmap(priv->gfargrp[i].regs);
 592 }
 593
 594 static void free_gfar_dev(struct gfar_private *priv)
 595 {
 596         int i, j;
 597
 598         for (i = 0; i < priv->num_grps; i++)
 599                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 600                         kfree(priv->gfargrp[i].irqinfo[j]);
 601                         priv->gfargrp[i].irqinfo[j] = NULL;
 602                 }
 603
 604         free_netdev(priv->ndev);
 605 }
 606
 607 static void disable_napi(struct gfar_private *priv)
 608 {
 609         int i;
 610
 611         for (i = 0; i < priv->num_grps; i++) {
 612                 napi_disable(&priv->gfargrp[i].napi_rx);
 613                 napi_disable(&priv->gfargrp[i].napi_tx);
 614         }
 615 }
 616
 617 static void enable_napi(struct gfar_private *priv)
 618 {
 619         int i;
 620
 621         for (i = 0; i < priv->num_grps; i++) {
 622                 napi_enable(&priv->gfargrp[i].napi_rx);
 623                 napi_enable(&priv->gfargrp[i].napi_tx);
 624         }
 625 }
 626
 627 static int gfar_parse_group(struct device_node *np,
 628                             struct gfar_private *priv, const char *model)
 629 {
 630         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 631         int i;
 632
 633         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 634                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 635                                           GFP_KERNEL);
 636                 if (!grp->irqinfo[i])
 637                         return -ENOMEM;
 638         }
 639
 640         grp->regs = of_iomap(np, 0);
 641         if (!grp->regs)
 642                 return -ENOMEM;
 643
 644         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 645
 646         /* If we aren't the FEC we have multiple interrupts */
 647         if (model && strcasecmp(model, "FEC")) {
 648                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 649                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 650                 if (!gfar_irq(grp, TX)->irq ||
 651                     !gfar_irq(grp, RX)->irq ||
 652                     !gfar_irq(grp, ER)->irq)
 653                         return -EINVAL;
 654         }
 655
 656         grp->priv = priv;
 657         spin_lock_init(&grp->grplock);
 658         if (priv->mode == MQ_MG_MODE) {
 659                 u32 rxq_mask, txq_mask;
 660                 int ret;
 661
 662                 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 663                 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 664
 665                 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
 666                 if (!ret) {
 667                         grp->rx_bit_map = rxq_mask ?
 668                         rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 669                 }
 670
 671                 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
 672                 if (!ret) {
 673                         grp->tx_bit_map = txq_mask ?
 674                         txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 675                 }
 676
 677                 if (priv->poll_mode == GFAR_SQ_POLLING) {
 678                         /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
 679                         grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 680                         grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 681                 }
 682         } else {
 683                 grp->rx_bit_map = 0xFF;
 684                 grp->tx_bit_map = 0xFF;
 685         }
 686
 687         /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
 688          * right to left, so we need to revert the 8 bits to get the q index
 689          */
 690         grp->rx_bit_map = bitrev8(grp->rx_bit_map);
 691         grp->tx_bit_map = bitrev8(grp->tx_bit_map);
 692
 693         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
 694          * also assign queues to groups
 695          */
 696         for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
 697                 if (!grp->rx_queue)
 698                         grp->rx_queue = priv->rx_queue[i];
 699                 grp->num_rx_queues++;
 700                 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
 701                 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
 702                 priv->rx_queue[i]->grp = grp;
 703         }
 704
 705         for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
 706                 if (!grp->tx_queue)
 707                         grp->tx_queue = priv->tx_queue[i];
 708                 grp->num_tx_queues++;
 709                 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
 710                 priv->tqueue |= (TQUEUE_EN0 >> i);
 711                 priv->tx_queue[i]->grp = grp;
 712         }
 713
 714         priv->num_grps++;
 715
 716         return 0;
 717 }
 718
 719 static int gfar_of_group_count(struct device_node *np)
 720 {
 721         struct device_node *child;
 722         int num = 0;
 723
 724         for_each_available_child_of_node(np, child)
 725                 if (!of_node_cmp(child->name, "queue-group"))
 726                         num++;
 727
 728         return num;
 729 }
 730
 731 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 732 {
 733         const char *model;
 734         const char *ctype;
 735         const void *mac_addr;
 736         int err = 0, i;
 737         struct net_device *dev = NULL;
 738         struct gfar_private *priv = NULL;
 739         struct device_node *np = ofdev->dev.of_node;
 740         struct device_node *child = NULL;
 741         u32 stash_len = 0;
 742         u32 stash_idx = 0;
 743         unsigned int num_tx_qs, num_rx_qs;
 744         unsigned short mode, poll_mode;
 745
 746         if (!np)
 747                 return -ENODEV;
 748
 749         if (of_device_is_compatible(np, "fsl,etsec2")) {
 750                 mode = MQ_MG_MODE;
 751                 poll_mode = GFAR_SQ_POLLING;
 752         } else {
 753                 mode = SQ_SG_MODE;
 754                 poll_mode = GFAR_SQ_POLLING;
 755         }
 756
 757         if (mode == SQ_SG_MODE) {
 758                 num_tx_qs = 1;
 759                 num_rx_qs = 1;
 760         } else { /* MQ_MG_MODE */
 761                 /* get the actual number of supported groups */
 762                 unsigned int num_grps = gfar_of_group_count(np);
 763
 764                 if (num_grps == 0 || num_grps > MAXGROUPS) {
 765                         dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
 766                                 num_grps);
 767                         pr_err("Cannot do alloc_etherdev, aborting\n");
 768                         return -EINVAL;
 769                 }
 770
 771                 if (poll_mode == GFAR_SQ_POLLING) {
 772                         num_tx_qs = num_grps; /* one txq per int group */
 773                         num_rx_qs = num_grps; /* one rxq per int group */
 774                 } else { /* GFAR_MQ_POLLING */
 775                         u32 tx_queues, rx_queues;
 776                         int ret;
 777
 778                         /* parse the num of HW tx and rx queues */
 779                         ret = of_property_read_u32(np, "fsl,num_tx_queues",
 780                                                    &tx_queues);
 781                         num_tx_qs = ret ? 1 : tx_queues;
 782
 783                         ret = of_property_read_u32(np, "fsl,num_rx_queues",
 784                                                    &rx_queues);
 785                         num_rx_qs = ret ? 1 : rx_queues;
 786                 }
 787         }
 788
 789         if (num_tx_qs > MAX_TX_QS) {
 790                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 791                        num_tx_qs, MAX_TX_QS);
 792                 pr_err("Cannot do alloc_etherdev, aborting\n");
 793                 return -EINVAL;
 794         }
 795
 796         if (num_rx_qs > MAX_RX_QS) {
 797                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 798                        num_rx_qs, MAX_RX_QS);
 799                 pr_err("Cannot do alloc_etherdev, aborting\n");
 800                 return -EINVAL;
 801         }
 802
 803         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 804         dev = *pdev;
 805         if (NULL == dev)
 806                 return -ENOMEM;
 807
 808         priv = netdev_priv(dev);
 809         priv->ndev = dev;
 810
 811         priv->mode = mode;
 812         priv->poll_mode = poll_mode;
 813
 814         priv->num_tx_queues = num_tx_qs;
 815         netif_set_real_num_rx_queues(dev, num_rx_qs);
 816         priv->num_rx_queues = num_rx_qs;
 817
 818         err = gfar_alloc_tx_queues(priv);
 819         if (err)
 820                 goto tx_alloc_failed;
 821
 822         err = gfar_alloc_rx_queues(priv);
 823         if (err)
 824                 goto rx_alloc_failed;
 825
 826         err = of_property_read_string(np, "model", &model);
 827         if (err) {
 828                 pr_err("Device model property missing, aborting\n");
 829                 goto rx_alloc_failed;
 830         }
 831
 832         /* Init Rx queue filer rule set linked list */
 833         INIT_LIST_HEAD(&priv->rx_list.list);
 834         priv->rx_list.count = 0;
 835         mutex_init(&priv->rx_queue_access);
 836
 837         for (i = 0; i < MAXGROUPS; i++)
 838                 priv->gfargrp[i].regs = NULL;
 839
 840         /* Parse and initialize group specific information */
 841         if (priv->mode == MQ_MG_MODE) {
 842                 for_each_available_child_of_node(np, child) {
 843                         if (of_node_cmp(child->name, "queue-group"))
 844                                 continue;
 845
 846                         err = gfar_parse_group(child, priv, model);
 847                         if (err)
 848                                 goto err_grp_init;
 849                 }
 850         } else { /* SQ_SG_MODE */
 851                 err = gfar_parse_group(np, priv, model);
 852                 if (err)
 853                         goto err_grp_init;
 854         }
 855
 856         if (of_property_read_bool(np, "bd-stash")) {
 857                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 858                 priv->bd_stash_en = 1;
 859         }
 860
 861         err = of_property_read_u32(np, "rx-stash-len", &stash_len);
 862
 863         if (err == 0)
 864                 priv->rx_stash_size = stash_len;
 865
 866         err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
 867
 868         if (err == 0)
 869                 priv->rx_stash_index = stash_idx;
 870
 871         if (stash_len || stash_idx)
 872                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 873
 874         mac_addr = of_get_mac_address(np);
 875
 876         if (mac_addr)
 877                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 878
 879         if (model && !strcasecmp(model, "TSEC"))
 880                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 881                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 882                                      FSL_GIANFAR_DEV_HAS_RMON |
 883                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 884
 885         if (model && !strcasecmp(model, "eTSEC"))
 886                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 887                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 888                                      FSL_GIANFAR_DEV_HAS_RMON |
 889                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 890                                      FSL_GIANFAR_DEV_HAS_CSUM |
 891                                      FSL_GIANFAR_DEV_HAS_VLAN |
 892                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 893                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 894                                      FSL_GIANFAR_DEV_HAS_TIMER |
 895                                      FSL_GIANFAR_DEV_HAS_RX_FILER;
 896
 897         err = of_property_read_string(np, "phy-connection-type", &ctype);
 898
 899         /* We only care about rgmii-id.  The rest are autodetected */
 900         if (err == 0 && !strcmp(ctype, "rgmii-id"))
 901                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 902         else
 903                 priv->interface = PHY_INTERFACE_MODE_MII;
 904
 905         if (of_find_property(np, "fsl,magic-packet", NULL))
 906                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 907
 908         if (of_get_property(np, "fsl,wake-on-filer", NULL))
 909                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
 910
 911         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 912
 913         /* In the case of a fixed PHY, the DT node associated
 914          * to the PHY is the Ethernet MAC DT node.
 915          */
 916         if (!priv->phy_node && of_phy_is_fixed_link(np)) {
 917                 err = of_phy_register_fixed_link(np);
 918                 if (err)
 919                         goto err_grp_init;
 920
 921                 priv->phy_node = of_node_get(np);
 922         }
 923
 924         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 925         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 926
 927         return 0;
 928
 929 err_grp_init:
 930         unmap_group_regs(priv);
 931 rx_alloc_failed:
 932         gfar_free_rx_queues(priv);
 933 tx_alloc_failed:
 934         gfar_free_tx_queues(priv);
 935         free_gfar_dev(priv);
 936         return err;
 937 }
 938
 939 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
 940 {
 941         struct hwtstamp_config config;
 942         struct gfar_private *priv = netdev_priv(netdev);
 943
 944         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 945                 return -EFAULT;
 946
 947         /* reserved for future extensions */
 948         if (config.flags)
 949                 return -EINVAL;
 950
 951         switch (config.tx_type) {
 952         case HWTSTAMP_TX_OFF:
 953                 priv->hwts_tx_en = 0;
 954                 break;
 955         case HWTSTAMP_TX_ON:
 956                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 957                         return -ERANGE;
 958                 priv->hwts_tx_en = 1;
 959                 break;
 960         default:
 961                 return -ERANGE;
 962         }
 963
 964         switch (config.rx_filter) {
 965         case HWTSTAMP_FILTER_NONE:
 966                 if (priv->hwts_rx_en) {
 967                         priv->hwts_rx_en = 0;
 968                         reset_gfar(netdev);
 969                 }
 970                 break;
 971         default:
 972                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 973                         return -ERANGE;
 974                 if (!priv->hwts_rx_en) {
 975                         priv->hwts_rx_en = 1;
 976                         reset_gfar(netdev);
 977                 }
 978                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 979                 break;
 980         }
 981
 982         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 983                 -EFAULT : 0;
 984 }
 985
 986 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
 987 {
 988         struct hwtstamp_config config;
 989         struct gfar_private *priv = netdev_priv(netdev);
 990
 991         config.flags = 0;
 992         config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
 993         config.rx_filter = (priv->hwts_rx_en ?
 994                             HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
 995
 996         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 997                 -EFAULT : 0;
 998 }
 999
1000 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1001 {
1002         struct gfar_private *priv = netdev_priv(dev);
1003
1004         if (!netif_running(dev))
1005                 return -EINVAL;
1006
1007         if (cmd == SIOCSHWTSTAMP)
1008                 return gfar_hwtstamp_set(dev, rq);
1009         if (cmd == SIOCGHWTSTAMP)
1010                 return gfar_hwtstamp_get(dev, rq);
1011
1012         if (!priv->phydev)
1013                 return -ENODEV;
1014
1015         return phy_mii_ioctl(priv->phydev, rq, cmd);
1016 }
1017
1018 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1019                                    u32 class)
1020 {
1021         u32 rqfpr = FPR_FILER_MASK;
1022         u32 rqfcr = 0x0;
1023
1024         rqfar--;
1025         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
1026         priv->ftp_rqfpr[rqfar] = rqfpr;
1027         priv->ftp_rqfcr[rqfar] = rqfcr;
1028         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1029
1030         rqfar--;
1031         rqfcr = RQFCR_CMP_NOMATCH;
1032         priv->ftp_rqfpr[rqfar] = rqfpr;
1033         priv->ftp_rqfcr[rqfar] = rqfcr;
1034         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1035
1036         rqfar--;
1037         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1038         rqfpr = class;
1039         priv->ftp_rqfcr[rqfar] = rqfcr;
1040         priv->ftp_rqfpr[rqfar] = rqfpr;
1041         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1042
1043         rqfar--;
1044         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1045         rqfpr = class;
1046         priv->ftp_rqfcr[rqfar] = rqfcr;
1047         priv->ftp_rqfpr[rqfar] = rqfpr;
1048         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1049
1050         return rqfar;
1051 }
1052
1053 static void gfar_init_filer_table(struct gfar_private *priv)
1054 {
1055         int i = 0x0;
1056         u32 rqfar = MAX_FILER_IDX;
1057         u32 rqfcr = 0x0;
1058         u32 rqfpr = FPR_FILER_MASK;
1059
1060         /* Default rule */
1061         rqfcr = RQFCR_CMP_MATCH;
1062         priv->ftp_rqfcr[rqfar] = rqfcr;
1063         priv->ftp_rqfpr[rqfar] = rqfpr;
1064         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1065
1066         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1067         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1068         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1069         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1070         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1071         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1072
1073         /* cur_filer_idx indicated the first non-masked rule */
1074         priv->cur_filer_idx = rqfar;
1075
1076         /* Rest are masked rules */
1077         rqfcr = RQFCR_CMP_NOMATCH;
1078         for (i = 0; i < rqfar; i++) {
1079                 priv->ftp_rqfcr[i] = rqfcr;
1080                 priv->ftp_rqfpr[i] = rqfpr;
1081                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1082         }
1083 }
1084
1085 #ifdef CONFIG_PPC
1086 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
1087 {
1088         unsigned int pvr = mfspr(SPRN_PVR);
1089         unsigned int svr = mfspr(SPRN_SVR);
1090         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1091         unsigned int rev = svr & 0xffff;
1092
1093         /* MPC8313 Rev 2.0 and higher; All MPC837x */
1094         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
1095             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1096                 priv->errata |= GFAR_ERRATA_74;
1097
1098         /* MPC8313 and MPC837x all rev */
1099         if ((pvr == 0x80850010 && mod == 0x80b0) ||
1100             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1101                 priv->errata |= GFAR_ERRATA_76;
1102
1103         /* MPC8313 Rev < 2.0 */
1104         if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1105                 priv->errata |= GFAR_ERRATA_12;
1106 }
1107
1108 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1109 {
1110         unsigned int svr = mfspr(SPRN_SVR);
1111
1112         if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
1113                 priv->errata |= GFAR_ERRATA_12;
1114         /* P2020/P1010 Rev 1; MPC8548 Rev 2 */
1115         if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1116             ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)) ||
1117             ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) < 0x31)))
1118                 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
1119 }
1120 #endif
1121
1122 static void gfar_detect_errata(struct gfar_private *priv)
1123 {
1124         struct device *dev = &priv->ofdev->dev;
1125
1126         /* no plans to fix */
1127         priv->errata |= GFAR_ERRATA_A002;
1128
1129 #ifdef CONFIG_PPC
1130         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1131                 __gfar_detect_errata_85xx(priv);
1132         else /* non-mpc85xx parts, i.e. e300 core based */
1133                 __gfar_detect_errata_83xx(priv);
1134 #endif
1135
1136         if (priv->errata)
1137                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1138                          priv->errata);
1139 }
1140
1141 void gfar_mac_reset(struct gfar_private *priv)
1142 {
1143         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1144         u32 tempval;
1145
1146         /* Reset MAC layer */
1147         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1148
1149         /* We need to delay at least 3 TX clocks */
1150         udelay(3);
1151
1152         /* the soft reset bit is not self-resetting, so we need to
1153          * clear it before resuming normal operation
1154          */
1155         gfar_write(&regs->maccfg1, 0);
1156
1157         udelay(3);
1158
1159         gfar_rx_offload_en(priv);
1160
1161         /* Initialize the max receive frame/buffer lengths */
1162         gfar_write(&regs->maxfrm, GFAR_JUMBO_FRAME_SIZE);
1163         gfar_write(&regs->mrblr, GFAR_RXB_SIZE);
1164
1165         /* Initialize the Minimum Frame Length Register */
1166         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1167
1168         /* Initialize MACCFG2. */
1169         tempval = MACCFG2_INIT_SETTINGS;
1170
1171         /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
1172          * are marked as truncated.  Avoid this by MACCFG2[Huge Frame]=1,
1173          * and by checking RxBD[LG] and discarding larger than MAXFRM.
1174          */
1175         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1176                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1177
1178         gfar_write(&regs->maccfg2, tempval);
1179
1180         /* Clear mac addr hash registers */
1181         gfar_write(&regs->igaddr0, 0);
1182         gfar_write(&regs->igaddr1, 0);
1183         gfar_write(&regs->igaddr2, 0);
1184         gfar_write(&regs->igaddr3, 0);
1185         gfar_write(&regs->igaddr4, 0);
1186         gfar_write(&regs->igaddr5, 0);
1187         gfar_write(&regs->igaddr6, 0);
1188         gfar_write(&regs->igaddr7, 0);
1189
1190         gfar_write(&regs->gaddr0, 0);
1191         gfar_write(&regs->gaddr1, 0);
1192         gfar_write(&regs->gaddr2, 0);
1193         gfar_write(&regs->gaddr3, 0);
1194         gfar_write(&regs->gaddr4, 0);
1195         gfar_write(&regs->gaddr5, 0);
1196         gfar_write(&regs->gaddr6, 0);
1197         gfar_write(&regs->gaddr7, 0);
1198
1199         if (priv->extended_hash)
1200                 gfar_clear_exact_match(priv->ndev);
1201
1202         gfar_mac_rx_config(priv);
1203
1204         gfar_mac_tx_config(priv);
1205
1206         gfar_set_mac_address(priv->ndev);
1207
1208         gfar_set_multi(priv->ndev);
1209
1210         /* clear ievent and imask before configuring coalescing */
1211         gfar_ints_disable(priv);
1212
1213         /* Configure the coalescing support */
1214         gfar_configure_coalescing_all(priv);
1215 }
1216
1217 static void gfar_hw_init(struct gfar_private *priv)
1218 {
1219         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1220         u32 attrs;
1221
1222         /* Stop the DMA engine now, in case it was running before
1223          * (The firmware could have used it, and left it running).
1224          */
1225         gfar_halt(priv);
1226
1227         gfar_mac_reset(priv);
1228
1229         /* Zero out the rmon mib registers if it has them */
1230         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1231                 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1232
1233                 /* Mask off the CAM interrupts */
1234                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1235                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1236         }
1237
1238         /* Initialize ECNTRL */
1239         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1240
1241         /* Set the extraction length and index */
1242         attrs = ATTRELI_EL(priv->rx_stash_size) |
1243                 ATTRELI_EI(priv->rx_stash_index);
1244
1245         gfar_write(&regs->attreli, attrs);
1246
1247         /* Start with defaults, and add stashing
1248          * depending on driver parameters
1249          */
1250         attrs = ATTR_INIT_SETTINGS;
1251
1252         if (priv->bd_stash_en)
1253                 attrs |= ATTR_BDSTASH;
1254
1255         if (priv->rx_stash_size != 0)
1256                 attrs |= ATTR_BUFSTASH;
1257
1258         gfar_write(&regs->attr, attrs);
1259
1260         /* FIFO configs */
1261         gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1262         gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1263         gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1264
1265         /* Program the interrupt steering regs, only for MG devices */
1266         if (priv->num_grps > 1)
1267                 gfar_write_isrg(priv);
1268 }
1269
1270 static void gfar_init_addr_hash_table(struct gfar_private *priv)
1271 {
1272         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1273
1274         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1275                 priv->extended_hash = 1;
1276                 priv->hash_width = 9;
1277
1278                 priv->hash_regs[0] = &regs->igaddr0;
1279                 priv->hash_regs[1] = &regs->igaddr1;
1280                 priv->hash_regs[2] = &regs->igaddr2;
1281                 priv->hash_regs[3] = &regs->igaddr3;
1282                 priv->hash_regs[4] = &regs->igaddr4;
1283                 priv->hash_regs[5] = &regs->igaddr5;
1284                 priv->hash_regs[6] = &regs->igaddr6;
1285                 priv->hash_regs[7] = &regs->igaddr7;
1286                 priv->hash_regs[8] = &regs->gaddr0;
1287                 priv->hash_regs[9] = &regs->gaddr1;
1288                 priv->hash_regs[10] = &regs->gaddr2;
1289                 priv->hash_regs[11] = &regs->gaddr3;
1290                 priv->hash_regs[12] = &regs->gaddr4;
1291                 priv->hash_regs[13] = &regs->gaddr5;
1292                 priv->hash_regs[14] = &regs->gaddr6;
1293                 priv->hash_regs[15] = &regs->gaddr7;
1294
1295         } else {
1296                 priv->extended_hash = 0;
1297                 priv->hash_width = 8;
1298
1299                 priv->hash_regs[0] = &regs->gaddr0;
1300                 priv->hash_regs[1] = &regs->gaddr1;
1301                 priv->hash_regs[2] = &regs->gaddr2;
1302                 priv->hash_regs[3] = &regs->gaddr3;
1303                 priv->hash_regs[4] = &regs->gaddr4;
1304                 priv->hash_regs[5] = &regs->gaddr5;
1305                 priv->hash_regs[6] = &regs->gaddr6;
1306                 priv->hash_regs[7] = &regs->gaddr7;
1307         }
1308 }
1309
1310 /* Set up the ethernet device structure, private data,
1311  * and anything else we need before we start
1312  */
1313 static int gfar_probe(struct platform_device *ofdev)
1314 {
1315         struct net_device *dev = NULL;
1316         struct gfar_private *priv = NULL;
1317         int err = 0, i;
1318
1319         err = gfar_of_init(ofdev, &dev);
1320
1321         if (err)
1322                 return err;
1323
1324         priv = netdev_priv(dev);
1325         priv->ndev = dev;
1326         priv->ofdev = ofdev;
1327         priv->dev = &ofdev->dev;
1328         SET_NETDEV_DEV(dev, &ofdev->dev);
1329
1330         INIT_WORK(&priv->reset_task, gfar_reset_task);
1331
1332         platform_set_drvdata(ofdev, priv);
1333
1334         gfar_detect_errata(priv);
1335
1336         /* Set the dev->base_addr to the gfar reg region */
1337         dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1338
1339         /* Fill in the dev structure */
1340         dev->watchdog_timeo = TX_TIMEOUT;
1341         dev->mtu = 1500;
1342         dev->netdev_ops = &gfar_netdev_ops;
1343         dev->ethtool_ops = &gfar_ethtool_ops;
1344
1345         /* Register for napi ...We are registering NAPI for each grp */
1346         for (i = 0; i < priv->num_grps; i++) {
1347                 if (priv->poll_mode == GFAR_SQ_POLLING) {
1348                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1349                                        gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1350                         netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
1351                                        gfar_poll_tx_sq, 2);
1352                 } else {
1353                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1354                                        gfar_poll_rx, GFAR_DEV_WEIGHT);
1355                         netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
1356                                        gfar_poll_tx, 2);
1357                 }
1358         }
1359
1360         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1361                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1362                                    NETIF_F_RXCSUM;
1363                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1364                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1365         }
1366
1367         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1368                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1369                                     NETIF_F_HW_VLAN_CTAG_RX;
1370                 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1371         }
1372
1373         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
1374
1375         gfar_init_addr_hash_table(priv);
1376
1377         /* Insert receive time stamps into padding alignment bytes */
1378         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1379                 priv->padding = 8;
1380
1381         if (dev->features & NETIF_F_IP_CSUM ||
1382             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1383                 dev->needed_headroom = GMAC_FCB_LEN;
1384
1385         /* Initializing some of the rx/tx queue level parameters */
1386         for (i = 0; i < priv->num_tx_queues; i++) {
1387                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1388                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1389                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1390                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1391         }
1392
1393         for (i = 0; i < priv->num_rx_queues; i++) {
1394                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1395                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1396                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1397         }
1398
1399         /* Always enable rx filer if available */
1400         priv->rx_filer_enable =
1401             (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0;
1402         /* Enable most messages by default */
1403         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1404         /* use pritority h/w tx queue scheduling for single queue devices */
1405         if (priv->num_tx_queues == 1)
1406                 priv->prio_sched_en = 1;
1407
1408         set_bit(GFAR_DOWN, &priv->state);
1409
1410         gfar_hw_init(priv);
1411
1412         /* Carrier starts down, phylib will bring it up */
1413         netif_carrier_off(dev);
1414
1415         err = register_netdev(dev);
1416
1417         if (err) {
1418                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1419                 goto register_fail;
1420         }
1421
1422         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
1423                 priv->wol_supported |= GFAR_WOL_MAGIC;
1424
1425         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
1426             priv->rx_filer_enable)
1427                 priv->wol_supported |= GFAR_WOL_FILER_UCAST;
1428
1429         device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
1430
1431         /* fill out IRQ number and name fields */
1432         for (i = 0; i < priv->num_grps; i++) {
1433                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1434                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1435                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1436                                 dev->name, "_g", '0' + i, "_tx");
1437                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1438                                 dev->name, "_g", '0' + i, "_rx");
1439                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1440                                 dev->name, "_g", '0' + i, "_er");
1441                 } else
1442                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1443         }
1444
1445         /* Initialize the filer table */
1446         gfar_init_filer_table(priv);
1447
1448         /* Print out the device info */
1449         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1450
1451         /* Even more device info helps when determining which kernel
1452          * provided which set of benchmarks.
1453          */
1454         netdev_info(dev, "Running with NAPI enabled\n");
1455         for (i = 0; i < priv->num_rx_queues; i++)
1456                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1457                             i, priv->rx_queue[i]->rx_ring_size);
1458         for (i = 0; i < priv->num_tx_queues; i++)
1459                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1460                             i, priv->tx_queue[i]->tx_ring_size);
1461
1462         return 0;
1463
1464 register_fail:
1465         unmap_group_regs(priv);
1466         gfar_free_rx_queues(priv);
1467         gfar_free_tx_queues(priv);
1468         of_node_put(priv->phy_node);
1469         of_node_put(priv->tbi_node);
1470         free_gfar_dev(priv);
1471         return err;
1472 }
1473
1474 static int gfar_remove(struct platform_device *ofdev)
1475 {
1476         struct gfar_private *priv = platform_get_drvdata(ofdev);
1477
1478         of_node_put(priv->phy_node);
1479         of_node_put(priv->tbi_node);
1480
1481         unregister_netdev(priv->ndev);
1482         unmap_group_regs(priv);
1483         gfar_free_rx_queues(priv);
1484         gfar_free_tx_queues(priv);
1485         free_gfar_dev(priv);
1486
1487         return 0;
1488 }
1489
1490 #ifdef CONFIG_PM
1491
1492 static void __gfar_filer_disable(struct gfar_private *priv)
1493 {
1494         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1495         u32 temp;
1496
1497         temp = gfar_read(&regs->rctrl);
1498         temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
1499         gfar_write(&regs->rctrl, temp);
1500 }
1501
1502 static void __gfar_filer_enable(struct gfar_private *priv)
1503 {
1504         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1505         u32 temp;
1506
1507         temp = gfar_read(&regs->rctrl);
1508         temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
1509         gfar_write(&regs->rctrl, temp);
1510 }
1511
1512 /* Filer rules implementing wol capabilities */
1513 static void gfar_filer_config_wol(struct gfar_private *priv)
1514 {
1515         unsigned int i;
1516         u32 rqfcr;
1517
1518         __gfar_filer_disable(priv);
1519
1520         /* clear the filer table, reject any packet by default */
1521         rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
1522         for (i = 0; i <= MAX_FILER_IDX; i++)
1523                 gfar_write_filer(priv, i, rqfcr, 0);
1524
1525         i = 0;
1526         if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
1527                 /* unicast packet, accept it */
1528                 struct net_device *ndev = priv->ndev;
1529                 /* get the default rx queue index */
1530                 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
1531                 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
1532                                     (ndev->dev_addr[1] << 8) |
1533                                      ndev->dev_addr[2];
1534
1535                 rqfcr = (qindex << 10) | RQFCR_AND |
1536                         RQFCR_CMP_EXACT | RQFCR_PID_DAH;
1537
1538                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1539
1540                 dest_mac_addr = (ndev->dev_addr[3] << 16) |
1541                                 (ndev->dev_addr[4] << 8) |
1542                                  ndev->dev_addr[5];
1543                 rqfcr = (qindex << 10) | RQFCR_GPI |
1544                         RQFCR_CMP_EXACT | RQFCR_PID_DAL;
1545                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1546         }
1547
1548         __gfar_filer_enable(priv);
1549 }
1550
1551 static void gfar_filer_restore_table(struct gfar_private *priv)
1552 {
1553         u32 rqfcr, rqfpr;
1554         unsigned int i;
1555
1556         __gfar_filer_disable(priv);
1557
1558         for (i = 0; i <= MAX_FILER_IDX; i++) {
1559                 rqfcr = priv->ftp_rqfcr[i];
1560                 rqfpr = priv->ftp_rqfpr[i];
1561                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1562         }
1563
1564         __gfar_filer_enable(priv);
1565 }
1566
1567 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */
1568 static void gfar_start_wol_filer(struct gfar_private *priv)
1569 {
1570         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1571         u32 tempval;
1572         int i = 0;
1573
1574         /* Enable Rx hw queues */
1575         gfar_write(&regs->rqueue, priv->rqueue);
1576
1577         /* Initialize DMACTRL to have WWR and WOP */
1578         tempval = gfar_read(&regs->dmactrl);
1579         tempval |= DMACTRL_INIT_SETTINGS;
1580         gfar_write(&regs->dmactrl, tempval);
1581
1582         /* Make sure we aren't stopped */
1583         tempval = gfar_read(&regs->dmactrl);
1584         tempval &= ~DMACTRL_GRS;
1585         gfar_write(&regs->dmactrl, tempval);
1586
1587         for (i = 0; i < priv->num_grps; i++) {
1588                 regs = priv->gfargrp[i].regs;
1589                 /* Clear RHLT, so that the DMA starts polling now */
1590                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1591                 /* enable the Filer General Purpose Interrupt */
1592                 gfar_write(&regs->imask, IMASK_FGPI);
1593         }
1594
1595         /* Enable Rx DMA */
1596         tempval = gfar_read(&regs->maccfg1);
1597         tempval |= MACCFG1_RX_EN;
1598         gfar_write(&regs->maccfg1, tempval);
1599 }
1600
1601 static int gfar_suspend(struct device *dev)
1602 {
1603         struct gfar_private *priv = dev_get_drvdata(dev);
1604         struct net_device *ndev = priv->ndev;
1605         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1606         u32 tempval;
1607         u16 wol = priv->wol_opts;
1608
1609         if (!netif_running(ndev))
1610                 return 0;
1611
1612         disable_napi(priv);
1613         netif_tx_lock(ndev);
1614         netif_device_detach(ndev);
1615         netif_tx_unlock(ndev);
1616
1617         gfar_halt(priv);
1618
1619         if (wol & GFAR_WOL_MAGIC) {
1620                 /* Enable interrupt on Magic Packet */
1621                 gfar_write(&regs->imask, IMASK_MAG);
1622
1623                 /* Enable Magic Packet mode */
1624                 tempval = gfar_read(&regs->maccfg2);
1625                 tempval |= MACCFG2_MPEN;
1626                 gfar_write(&regs->maccfg2, tempval);
1627
1628                 /* re-enable the Rx block */
1629                 tempval = gfar_read(&regs->maccfg1);
1630                 tempval |= MACCFG1_RX_EN;
1631                 gfar_write(&regs->maccfg1, tempval);
1632
1633         } else if (wol & GFAR_WOL_FILER_UCAST) {
1634                 gfar_filer_config_wol(priv);
1635                 gfar_start_wol_filer(priv);
1636
1637         } else {
1638                 phy_stop(priv->phydev);
1639         }
1640
1641         return 0;
1642 }
1643
1644 static int gfar_resume(struct device *dev)
1645 {
1646         struct gfar_private *priv = dev_get_drvdata(dev);
1647         struct net_device *ndev = priv->ndev;
1648         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1649         u32 tempval;
1650         u16 wol = priv->wol_opts;
1651
1652         if (!netif_running(ndev))
1653                 return 0;
1654
1655         if (wol & GFAR_WOL_MAGIC) {
1656                 /* Disable Magic Packet mode */
1657                 tempval = gfar_read(&regs->maccfg2);
1658                 tempval &= ~MACCFG2_MPEN;
1659                 gfar_write(&regs->maccfg2, tempval);
1660
1661         } else if (wol & GFAR_WOL_FILER_UCAST) {
1662                 /* need to stop rx only, tx is already down */
1663                 gfar_halt(priv);
1664                 gfar_filer_restore_table(priv);
1665
1666         } else {
1667                 phy_start(priv->phydev);
1668         }
1669
1670         gfar_start(priv);
1671
1672         netif_device_attach(ndev);
1673         enable_napi(priv);
1674
1675         return 0;
1676 }
1677
1678 static int gfar_restore(struct device *dev)
1679 {
1680         struct gfar_private *priv = dev_get_drvdata(dev);
1681         struct net_device *ndev = priv->ndev;
1682
1683         if (!netif_running(ndev)) {
1684                 netif_device_attach(ndev);
1685
1686                 return 0;
1687         }
1688
1689         gfar_init_bds(ndev);
1690
1691         gfar_mac_reset(priv);
1692
1693         gfar_init_tx_rx_base(priv);
1694
1695         gfar_start(priv);
1696
1697         priv->oldlink = 0;
1698         priv->oldspeed = 0;
1699         priv->oldduplex = -1;
1700
1701         if (priv->phydev)
1702                 phy_start(priv->phydev);
1703
1704         netif_device_attach(ndev);
1705         enable_napi(priv);
1706
1707         return 0;
1708 }
1709
1710 static struct dev_pm_ops gfar_pm_ops = {
1711         .suspend = gfar_suspend,
1712         .resume = gfar_resume,
1713         .freeze = gfar_suspend,
1714         .thaw = gfar_resume,
1715         .restore = gfar_restore,
1716 };
1717
1718 #define GFAR_PM_OPS (&gfar_pm_ops)
1719
1720 #else
1721
1722 #define GFAR_PM_OPS NULL
1723
1724 #endif
1725
1726 /* Reads the controller's registers to determine what interface
1727  * connects it to the PHY.
1728  */
1729 static phy_interface_t gfar_get_interface(struct net_device *dev)
1730 {
1731         struct gfar_private *priv = netdev_priv(dev);
1732         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1733         u32 ecntrl;
1734
1735         ecntrl = gfar_read(&regs->ecntrl);
1736
1737         if (ecntrl & ECNTRL_SGMII_MODE)
1738                 return PHY_INTERFACE_MODE_SGMII;
1739
1740         if (ecntrl & ECNTRL_TBI_MODE) {
1741                 if (ecntrl & ECNTRL_REDUCED_MODE)
1742                         return PHY_INTERFACE_MODE_RTBI;
1743                 else
1744                         return PHY_INTERFACE_MODE_TBI;
1745         }
1746
1747         if (ecntrl & ECNTRL_REDUCED_MODE) {
1748                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1749                         return PHY_INTERFACE_MODE_RMII;
1750                 }
1751                 else {
1752                         phy_interface_t interface = priv->interface;
1753
1754                         /* This isn't autodetected right now, so it must
1755                          * be set by the device tree or platform code.
1756                          */
1757                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1758                                 return PHY_INTERFACE_MODE_RGMII_ID;
1759
1760                         return PHY_INTERFACE_MODE_RGMII;
1761                 }
1762         }
1763
1764         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1765                 return PHY_INTERFACE_MODE_GMII;
1766
1767         return PHY_INTERFACE_MODE_MII;
1768 }
1769
1770
1771 /* Initializes driver's PHY state, and attaches to the PHY.
1772  * Returns 0 on success.
1773  */
1774 static int init_phy(struct net_device *dev)
1775 {
1776         struct gfar_private *priv = netdev_priv(dev);
1777         uint gigabit_support =
1778                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1779                 GFAR_SUPPORTED_GBIT : 0;
1780         phy_interface_t interface;
1781
1782         priv->oldlink = 0;
1783         priv->oldspeed = 0;
1784         priv->oldduplex = -1;
1785
1786         interface = gfar_get_interface(dev);
1787
1788         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1789                                       interface);
1790         if (!priv->phydev) {
1791                 dev_err(&dev->dev, "could not attach to PHY\n");
1792                 return -ENODEV;
1793         }
1794
1795         if (interface == PHY_INTERFACE_MODE_SGMII)
1796                 gfar_configure_serdes(dev);
1797
1798         /* Remove any features not supported by the controller */
1799         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1800         priv->phydev->advertising = priv->phydev->supported;
1801
1802         /* Add support for flow control, but don't advertise it by default */
1803         priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1804
1805         return 0;
1806 }
1807
1808 /* Initialize TBI PHY interface for communicating with the
1809  * SERDES lynx PHY on the chip.  We communicate with this PHY
1810  * through the MDIO bus on each controller, treating it as a
1811  * "normal" PHY at the address found in the TBIPA register.  We assume
1812  * that the TBIPA register is valid.  Either the MDIO bus code will set
1813  * it to a value that doesn't conflict with other PHYs on the bus, or the
1814  * value doesn't matter, as there are no other PHYs on the bus.
1815  */
1816 static void gfar_configure_serdes(struct net_device *dev)
1817 {
1818         struct gfar_private *priv = netdev_priv(dev);
1819         struct phy_device *tbiphy;
1820
1821         if (!priv->tbi_node) {
1822                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1823                                     "device tree specify a tbi-handle\n");
1824                 return;
1825         }
1826
1827         tbiphy = of_phy_find_device(priv->tbi_node);
1828         if (!tbiphy) {
1829                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1830                 return;
1831         }
1832
1833         /* If the link is already up, we must already be ok, and don't need to
1834          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1835          * everything for us?  Resetting it takes the link down and requires
1836          * several seconds for it to come back.
1837          */
1838         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1839                 put_device(&tbiphy->mdio.dev);
1840                 return;
1841         }
1842
1843         /* Single clk mode, mii mode off(for serdes communication) */
1844         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1845
1846         phy_write(tbiphy, MII_ADVERTISE,
1847                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1848                   ADVERTISE_1000XPSE_ASYM);
1849
1850         phy_write(tbiphy, MII_BMCR,
1851                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1852                   BMCR_SPEED1000);
1853
1854         put_device(&tbiphy->mdio.dev);
1855 }
1856
1857 static int __gfar_is_rx_idle(struct gfar_private *priv)
1858 {
1859         u32 res;
1860
1861         /* Normaly TSEC should not hang on GRS commands, so we should
1862          * actually wait for IEVENT_GRSC flag.
1863          */
1864         if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1865                 return 0;
1866
1867         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1868          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1869          * and the Rx can be safely reset.
1870          */
1871         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1872         res &= 0x7f807f80;
1873         if ((res & 0xffff) == (res >> 16))
1874                 return 1;
1875
1876         return 0;
1877 }
1878
1879 /* Halt the receive and transmit queues */
1880 static void gfar_halt_nodisable(struct gfar_private *priv)
1881 {
1882         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1883         u32 tempval;
1884         unsigned int timeout;
1885         int stopped;
1886
1887         gfar_ints_disable(priv);
1888
1889         if (gfar_is_dma_stopped(priv))
1890                 return;
1891
1892         /* Stop the DMA, and wait for it to stop */
1893         tempval = gfar_read(&regs->dmactrl);
1894         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1895         gfar_write(&regs->dmactrl, tempval);
1896
1897 retry:
1898         timeout = 1000;
1899         while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1900                 cpu_relax();
1901                 timeout--;
1902         }
1903
1904         if (!timeout)
1905                 stopped = gfar_is_dma_stopped(priv);
1906
1907         if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1908             !__gfar_is_rx_idle(priv))
1909                 goto retry;
1910 }
1911
1912 /* Halt the receive and transmit queues */
1913 void gfar_halt(struct gfar_private *priv)
1914 {
1915         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1916         u32 tempval;
1917
1918         /* Dissable the Rx/Tx hw queues */
1919         gfar_write(&regs->rqueue, 0);
1920         gfar_write(&regs->tqueue, 0);
1921
1922         mdelay(10);
1923
1924         gfar_halt_nodisable(priv);
1925
1926         /* Disable Rx/Tx DMA */
1927         tempval = gfar_read(&regs->maccfg1);
1928         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1929         gfar_write(&regs->maccfg1, tempval);
1930 }
1931
1932 void stop_gfar(struct net_device *dev)
1933 {
1934         struct gfar_private *priv = netdev_priv(dev);
1935
1936         netif_tx_stop_all_queues(dev);
1937
1938         smp_mb__before_atomic();
1939         set_bit(GFAR_DOWN, &priv->state);
1940         smp_mb__after_atomic();
1941
1942         disable_napi(priv);
1943
1944         /* disable ints and gracefully shut down Rx/Tx DMA */
1945         gfar_halt(priv);
1946
1947         phy_stop(priv->phydev);
1948
1949         free_skb_resources(priv);
1950 }
1951
1952 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1953 {
1954         struct txbd8 *txbdp;
1955         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1956         int i, j;
1957
1958         txbdp = tx_queue->tx_bd_base;
1959
1960         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1961                 if (!tx_queue->tx_skbuff[i])
1962                         continue;
1963
1964                 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1965                                  be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1966                 txbdp->lstatus = 0;
1967                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1968                      j++) {
1969                         txbdp++;
1970                         dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1971                                        be16_to_cpu(txbdp->length),
1972                                        DMA_TO_DEVICE);
1973                 }
1974                 txbdp++;
1975                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1976                 tx_queue->tx_skbuff[i] = NULL;
1977         }
1978         kfree(tx_queue->tx_skbuff);
1979         tx_queue->tx_skbuff = NULL;
1980 }
1981
1982 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1983 {
1984         int i;
1985
1986         struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
1987
1988         if (rx_queue->skb)
1989                 dev_kfree_skb(rx_queue->skb);
1990
1991         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1992                 struct  gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
1993
1994                 rxbdp->lstatus = 0;
1995                 rxbdp->bufPtr = 0;
1996                 rxbdp++;
1997
1998                 if (!rxb->page)
1999                         continue;
2000
2001                 dma_unmap_single(rx_queue->dev, rxb->dma,
2002                                  PAGE_SIZE, DMA_FROM_DEVICE);
2003                 __free_page(rxb->page);
2004
2005                 rxb->page = NULL;
2006         }
2007
2008         kfree(rx_queue->rx_buff);
2009         rx_queue->rx_buff = NULL;
2010 }
2011
2012 /* If there are any tx skbs or rx skbs still around, free them.
2013  * Then free tx_skbuff and rx_skbuff
2014  */
2015 static void free_skb_resources(struct gfar_private *priv)
2016 {
2017         struct gfar_priv_tx_q *tx_queue = NULL;
2018         struct gfar_priv_rx_q *rx_queue = NULL;
2019         int i;
2020
2021         /* Go through all the buffer descriptors and free their data buffers */
2022         for (i = 0; i < priv->num_tx_queues; i++) {
2023                 struct netdev_queue *txq;
2024
2025                 tx_queue = priv->tx_queue[i];
2026                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
2027                 if (tx_queue->tx_skbuff)
2028                         free_skb_tx_queue(tx_queue);
2029                 netdev_tx_reset_queue(txq);
2030         }
2031
2032         for (i = 0; i < priv->num_rx_queues; i++) {
2033                 rx_queue = priv->rx_queue[i];
2034                 if (rx_queue->rx_buff)
2035                         free_skb_rx_queue(rx_queue);
2036         }
2037
2038         dma_free_coherent(priv->dev,
2039                           sizeof(struct txbd8) * priv->total_tx_ring_size +
2040                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
2041                           priv->tx_queue[0]->tx_bd_base,
2042                           priv->tx_queue[0]->tx_bd_dma_base);
2043 }
2044
2045 void gfar_start(struct gfar_private *priv)
2046 {
2047         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2048         u32 tempval;
2049         int i = 0;
2050
2051         /* Enable Rx/Tx hw queues */
2052         gfar_write(&regs->rqueue, priv->rqueue);
2053         gfar_write(&regs->tqueue, priv->tqueue);
2054
2055         /* Initialize DMACTRL to have WWR and WOP */
2056         tempval = gfar_read(&regs->dmactrl);
2057         tempval |= DMACTRL_INIT_SETTINGS;
2058         gfar_write(&regs->dmactrl, tempval);
2059
2060         /* Make sure we aren't stopped */
2061         tempval = gfar_read(&regs->dmactrl);
2062         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
2063         gfar_write(&regs->dmactrl, tempval);
2064
2065         for (i = 0; i < priv->num_grps; i++) {
2066                 regs = priv->gfargrp[i].regs;
2067                 /* Clear THLT/RHLT, so that the DMA starts polling now */
2068                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
2069                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
2070         }
2071
2072         /* Enable Rx/Tx DMA */
2073         tempval = gfar_read(&regs->maccfg1);
2074         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
2075         gfar_write(&regs->maccfg1, tempval);
2076
2077         gfar_ints_enable(priv);
2078
2079         priv->ndev->trans_start = jiffies; /* prevent tx timeout */
2080 }
2081
2082 static void free_grp_irqs(struct gfar_priv_grp *grp)
2083 {
2084         free_irq(gfar_irq(grp, TX)->irq, grp);
2085         free_irq(gfar_irq(grp, RX)->irq, grp);
2086         free_irq(gfar_irq(grp, ER)->irq, grp);
2087 }
2088
2089 static int register_grp_irqs(struct gfar_priv_grp *grp)
2090 {
2091         struct gfar_private *priv = grp->priv;
2092         struct net_device *dev = priv->ndev;
2093         int err;
2094
2095         /* If the device has multiple interrupts, register for
2096          * them.  Otherwise, only register for the one
2097          */
2098         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2099                 /* Install our interrupt handlers for Error,
2100                  * Transmit, and Receive
2101                  */
2102                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2103                                   gfar_irq(grp, ER)->name, grp);
2104                 if (err < 0) {
2105                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2106                                   gfar_irq(grp, ER)->irq);
2107
2108                         goto err_irq_fail;
2109                 }
2110                 enable_irq_wake(gfar_irq(grp, ER)->irq);
2111
2112                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2113                                   gfar_irq(grp, TX)->name, grp);
2114                 if (err < 0) {
2115                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2116                                   gfar_irq(grp, TX)->irq);
2117                         goto tx_irq_fail;
2118                 }
2119                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2120                                   gfar_irq(grp, RX)->name, grp);
2121                 if (err < 0) {
2122                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2123                                   gfar_irq(grp, RX)->irq);
2124                         goto rx_irq_fail;
2125                 }
2126                 enable_irq_wake(gfar_irq(grp, RX)->irq);
2127
2128         } else {
2129                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2130                                   gfar_irq(grp, TX)->name, grp);
2131                 if (err < 0) {
2132                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2133                                   gfar_irq(grp, TX)->irq);
2134                         goto err_irq_fail;
2135                 }
2136                 enable_irq_wake(gfar_irq(grp, TX)->irq);
2137         }
2138
2139         return 0;
2140
2141 rx_irq_fail:
2142         free_irq(gfar_irq(grp, TX)->irq, grp);
2143 tx_irq_fail:
2144         free_irq(gfar_irq(grp, ER)->irq, grp);
2145 err_irq_fail:
2146         return err;
2147
2148 }
2149
2150 static void gfar_free_irq(struct gfar_private *priv)
2151 {
2152         int i;
2153
2154         /* Free the IRQs */
2155         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2156                 for (i = 0; i < priv->num_grps; i++)
2157                         free_grp_irqs(&priv->gfargrp[i]);
2158         } else {
2159                 for (i = 0; i < priv->num_grps; i++)
2160                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2161                                  &priv->gfargrp[i]);
2162         }
2163 }
2164
2165 static int gfar_request_irq(struct gfar_private *priv)
2166 {
2167         int err, i, j;
2168
2169         for (i = 0; i < priv->num_grps; i++) {
2170                 err = register_grp_irqs(&priv->gfargrp[i]);
2171                 if (err) {
2172                         for (j = 0; j < i; j++)
2173                                 free_grp_irqs(&priv->gfargrp[j]);
2174                         return err;
2175                 }
2176         }
2177
2178         return 0;
2179 }
2180
2181 /* Bring the controller up and running */
2182 int startup_gfar(struct net_device *ndev)
2183 {
2184         struct gfar_private *priv = netdev_priv(ndev);
2185         int err;
2186
2187         gfar_mac_reset(priv);
2188
2189         err = gfar_alloc_skb_resources(ndev);
2190         if (err)
2191                 return err;
2192
2193         gfar_init_tx_rx_base(priv);
2194
2195         smp_mb__before_atomic();
2196         clear_bit(GFAR_DOWN, &priv->state);
2197         smp_mb__after_atomic();
2198
2199         /* Start Rx/Tx DMA and enable the interrupts */
2200         gfar_start(priv);
2201
2202         /* force link state update after mac reset */
2203         priv->oldlink = 0;
2204         priv->oldspeed = 0;
2205         priv->oldduplex = -1;
2206
2207         phy_start(priv->phydev);
2208
2209         enable_napi(priv);
2210
2211         netif_tx_wake_all_queues(ndev);
2212
2213         return 0;
2214 }
2215
2216 /* Called when something needs to use the ethernet device
2217  * Returns 0 for success.
2218  */
2219 static int gfar_enet_open(struct net_device *dev)
2220 {
2221         struct gfar_private *priv = netdev_priv(dev);
2222         int err;
2223
2224         err = init_phy(dev);
2225         if (err)
2226                 return err;
2227
2228         err = gfar_request_irq(priv);
2229         if (err)
2230                 return err;
2231
2232         err = startup_gfar(dev);
2233         if (err)
2234                 return err;
2235
2236         return err;
2237 }
2238
2239 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2240 {
2241         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2242
2243         memset(fcb, 0, GMAC_FCB_LEN);
2244
2245         return fcb;
2246 }
2247
2248 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2249                                     int fcb_length)
2250 {
2251         /* If we're here, it's a IP packet with a TCP or UDP
2252          * payload.  We set it to checksum, using a pseudo-header
2253          * we provide
2254          */
2255         u8 flags = TXFCB_DEFAULT;
2256
2257         /* Tell the controller what the protocol is
2258          * And provide the already calculated phcs
2259          */
2260         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2261                 flags |= TXFCB_UDP;
2262                 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
2263         } else
2264                 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
2265
2266         /* l3os is the distance between the start of the
2267          * frame (skb->data) and the start of the IP hdr.
2268          * l4os is the distance between the start of the
2269          * l3 hdr and the l4 hdr
2270          */
2271         fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
2272         fcb->l4os = skb_network_header_len(skb);
2273
2274         fcb->flags = flags;
2275 }
2276
2277 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2278 {
2279         fcb->flags |= TXFCB_VLN;
2280         fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
2281 }
2282
2283 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2284                                       struct txbd8 *base, int ring_size)
2285 {
2286         struct txbd8 *new_bd = bdp + stride;
2287
2288         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2289 }
2290
2291 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2292                                       int ring_size)
2293 {
2294         return skip_txbd(bdp, 1, base, ring_size);
2295 }
2296
2297 /* eTSEC12: csum generation not supported for some fcb offsets */
2298 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2299                                        unsigned long fcb_addr)
2300 {
2301         return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2302                (fcb_addr % 0x20) > 0x18);
2303 }
2304
2305 /* eTSEC76: csum generation for frames larger than 2500 may
2306  * cause excess delays before start of transmission
2307  */
2308 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2309                                        unsigned int len)
2310 {
2311         return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2312                (len > 2500));
2313 }
2314
2315 /* This is called by the kernel when a frame is ready for transmission.
2316  * It is pointed to by the dev->hard_start_xmit function pointer
2317  */
2318 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2319 {
2320         struct gfar_private *priv = netdev_priv(dev);
2321         struct gfar_priv_tx_q *tx_queue = NULL;
2322         struct netdev_queue *txq;
2323         struct gfar __iomem *regs = NULL;
2324         struct txfcb *fcb = NULL;
2325         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2326         u32 lstatus;
2327         int i, rq = 0;
2328         int do_tstamp, do_csum, do_vlan;
2329         u32 bufaddr;
2330         unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2331
2332         rq = skb->queue_mapping;
2333         tx_queue = priv->tx_queue[rq];
2334         txq = netdev_get_tx_queue(dev, rq);
2335         base = tx_queue->tx_bd_base;
2336         regs = tx_queue->grp->regs;
2337
2338         do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2339         do_vlan = skb_vlan_tag_present(skb);
2340         do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2341                     priv->hwts_tx_en;
2342
2343         if (do_csum || do_vlan)
2344                 fcb_len = GMAC_FCB_LEN;
2345
2346         /* check if time stamp should be generated */
2347         if (unlikely(do_tstamp))
2348                 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2349
2350         /* make space for additional header when fcb is needed */
2351         if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2352                 struct sk_buff *skb_new;
2353
2354                 skb_new = skb_realloc_headroom(skb, fcb_len);
2355                 if (!skb_new) {
2356                         dev->stats.tx_errors++;
2357                         dev_kfree_skb_any(skb);
2358                         return NETDEV_TX_OK;
2359                 }
2360
2361                 if (skb->sk)
2362                         skb_set_owner_w(skb_new, skb->sk);
2363                 dev_consume_skb_any(skb);
2364                 skb = skb_new;
2365         }
2366
2367         /* total number of fragments in the SKB */
2368         nr_frags = skb_shinfo(skb)->nr_frags;
2369
2370         /* calculate the required number of TxBDs for this skb */
2371         if (unlikely(do_tstamp))
2372                 nr_txbds = nr_frags + 2;
2373         else
2374                 nr_txbds = nr_frags + 1;
2375
2376         /* check if there is space to queue this packet */
2377         if (nr_txbds > tx_queue->num_txbdfree) {
2378                 /* no space, stop the queue */
2379                 netif_tx_stop_queue(txq);
2380                 dev->stats.tx_fifo_errors++;
2381                 return NETDEV_TX_BUSY;
2382         }
2383
2384         /* Update transmit stats */
2385         bytes_sent = skb->len;
2386         tx_queue->stats.tx_bytes += bytes_sent;
2387         /* keep Tx bytes on wire for BQL accounting */
2388         GFAR_CB(skb)->bytes_sent = bytes_sent;
2389         tx_queue->stats.tx_packets++;
2390
2391         txbdp = txbdp_start = tx_queue->cur_tx;
2392         lstatus = be32_to_cpu(txbdp->lstatus);
2393
2394         /* Time stamp insertion requires one additional TxBD */
2395         if (unlikely(do_tstamp))
2396                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2397                                                  tx_queue->tx_ring_size);
2398
2399         if (nr_frags == 0) {
2400                 if (unlikely(do_tstamp)) {
2401                         u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2402
2403                         lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2404                         txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2405                 } else {
2406                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2407                 }
2408         } else {
2409                 /* Place the fragment addresses and lengths into the TxBDs */
2410                 for (i = 0; i < nr_frags; i++) {
2411                         unsigned int frag_len;
2412                         /* Point at the next BD, wrapping as needed */
2413                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2414
2415                         frag_len = skb_shinfo(skb)->frags[i].size;
2416
2417                         lstatus = be32_to_cpu(txbdp->lstatus) | frag_len |
2418                                   BD_LFLAG(TXBD_READY);
2419
2420                         /* Handle the last BD specially */
2421                         if (i == nr_frags - 1)
2422                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2423
2424                         bufaddr = skb_frag_dma_map(priv->dev,
2425                                                    &skb_shinfo(skb)->frags[i],
2426                                                    0,
2427                                                    frag_len,
2428                                                    DMA_TO_DEVICE);
2429                         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2430                                 goto dma_map_err;
2431
2432                         /* set the TxBD length and buffer pointer */
2433                         txbdp->bufPtr = cpu_to_be32(bufaddr);
2434                         txbdp->lstatus = cpu_to_be32(lstatus);
2435                 }
2436
2437                 lstatus = be32_to_cpu(txbdp_start->lstatus);
2438         }
2439
2440         /* Add TxPAL between FCB and frame if required */
2441         if (unlikely(do_tstamp)) {
2442                 skb_push(skb, GMAC_TXPAL_LEN);
2443                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2444         }
2445
2446         /* Add TxFCB if required */
2447         if (fcb_len) {
2448                 fcb = gfar_add_fcb(skb);
2449                 lstatus |= BD_LFLAG(TXBD_TOE);
2450         }
2451
2452         /* Set up checksumming */
2453         if (do_csum) {
2454                 gfar_tx_checksum(skb, fcb, fcb_len);
2455
2456                 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2457                     unlikely(gfar_csum_errata_76(priv, skb->len))) {
2458                         __skb_pull(skb, GMAC_FCB_LEN);
2459                         skb_checksum_help(skb);
2460                         if (do_vlan || do_tstamp) {
2461                                 /* put back a new fcb for vlan/tstamp TOE */
2462                                 fcb = gfar_add_fcb(skb);
2463                         } else {
2464                                 /* Tx TOE not used */
2465                                 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2466                                 fcb = NULL;
2467                         }
2468                 }
2469         }
2470
2471         if (do_vlan)
2472                 gfar_tx_vlan(skb, fcb);
2473
2474         /* Setup tx hardware time stamping if requested */
2475         if (unlikely(do_tstamp)) {
2476                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2477                 fcb->ptp = 1;
2478         }
2479
2480         bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2481                                  DMA_TO_DEVICE);
2482         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2483                 goto dma_map_err;
2484
2485         txbdp_start->bufPtr = cpu_to_be32(bufaddr);
2486
2487         /* If time stamping is requested one additional TxBD must be set up. The
2488          * first TxBD points to the FCB and must have a data length of
2489          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2490          * the full frame length.
2491          */
2492         if (unlikely(do_tstamp)) {
2493                 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2494
2495                 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
2496                 bufaddr += fcb_len;
2497                 lstatus_ts |= BD_LFLAG(TXBD_READY) |
2498                               (skb_headlen(skb) - fcb_len);
2499
2500                 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
2501                 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2502                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2503         } else {
2504                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2505         }
2506
2507         netdev_tx_sent_queue(txq, bytes_sent);
2508
2509         gfar_wmb();
2510
2511         txbdp_start->lstatus = cpu_to_be32(lstatus);
2512
2513         gfar_wmb(); /* force lstatus write before tx_skbuff */
2514
2515         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2516
2517         /* Update the current skb pointer to the next entry we will use
2518          * (wrapping if necessary)
2519          */
2520         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2521                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2522
2523         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2524
2525         /* We can work in parallel with gfar_clean_tx_ring(), except
2526          * when modifying num_txbdfree. Note that we didn't grab the lock
2527          * when we were reading the num_txbdfree and checking for available
2528          * space, that's because outside of this function it can only grow.
2529          */
2530         spin_lock_bh(&tx_queue->txlock);
2531         /* reduce TxBD free count */
2532         tx_queue->num_txbdfree -= (nr_txbds);
2533         spin_unlock_bh(&tx_queue->txlock);
2534
2535         /* If the next BD still needs to be cleaned up, then the bds
2536          * are full.  We need to tell the kernel to stop sending us stuff.
2537          */
2538         if (!tx_queue->num_txbdfree) {
2539                 netif_tx_stop_queue(txq);
2540
2541                 dev->stats.tx_fifo_errors++;
2542         }
2543
2544         /* Tell the DMA to go go go */
2545         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2546
2547         return NETDEV_TX_OK;
2548
2549 dma_map_err:
2550         txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2551         if (do_tstamp)
2552                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2553         for (i = 0; i < nr_frags; i++) {
2554                 lstatus = be32_to_cpu(txbdp->lstatus);
2555                 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2556                         break;
2557
2558                 lstatus &= ~BD_LFLAG(TXBD_READY);
2559                 txbdp->lstatus = cpu_to_be32(lstatus);
2560                 bufaddr = be32_to_cpu(txbdp->bufPtr);
2561                 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2562                                DMA_TO_DEVICE);
2563                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2564         }
2565         gfar_wmb();
2566         dev_kfree_skb_any(skb);
2567         return NETDEV_TX_OK;
2568 }
2569
2570 /* Stops the kernel queue, and halts the controller */
2571 static int gfar_close(struct net_device *dev)
2572 {
2573         struct gfar_private *priv = netdev_priv(dev);
2574
2575         cancel_work_sync(&priv->reset_task);
2576         stop_gfar(dev);
2577
2578         /* Disconnect from the PHY */
2579         phy_disconnect(priv->phydev);
2580         priv->phydev = NULL;
2581
2582         gfar_free_irq(priv);
2583
2584         return 0;
2585 }
2586
2587 /* Changes the mac address if the controller is not running. */
2588 static int gfar_set_mac_address(struct net_device *dev)
2589 {
2590         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2591
2592         return 0;
2593 }
2594
2595 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2596 {
2597         struct gfar_private *priv = netdev_priv(dev);
2598         int frame_size = new_mtu + ETH_HLEN;
2599
2600         if ((frame_size < 64) || (frame_size > GFAR_JUMBO_FRAME_SIZE)) {
2601                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2602                 return -EINVAL;
2603         }
2604
2605         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2606                 cpu_relax();
2607
2608         if (dev->flags & IFF_UP)
2609                 stop_gfar(dev);
2610
2611         dev->mtu = new_mtu;
2612
2613         if (dev->flags & IFF_UP)
2614                 startup_gfar(dev);
2615
2616         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2617
2618         return 0;
2619 }
2620
2621 void reset_gfar(struct net_device *ndev)
2622 {
2623         struct gfar_private *priv = netdev_priv(ndev);
2624
2625         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2626                 cpu_relax();
2627
2628         stop_gfar(ndev);
2629         startup_gfar(ndev);
2630
2631         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2632 }
2633
2634 /* gfar_reset_task gets scheduled when a packet has not been
2635  * transmitted after a set amount of time.
2636  * For now, assume that clearing out all the structures, and
2637  * starting over will fix the problem.
2638  */
2639 static void gfar_reset_task(struct work_struct *work)
2640 {
2641         struct gfar_private *priv = container_of(work, struct gfar_private,
2642                                                  reset_task);
2643         reset_gfar(priv->ndev);
2644 }
2645
2646 static void gfar_timeout(struct net_device *dev)
2647 {
2648         struct gfar_private *priv = netdev_priv(dev);
2649
2650         dev->stats.tx_errors++;
2651         schedule_work(&priv->reset_task);
2652 }
2653
2654 /* Interrupt Handler for Transmit complete */
2655 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2656 {
2657         struct net_device *dev = tx_queue->dev;
2658         struct netdev_queue *txq;
2659         struct gfar_private *priv = netdev_priv(dev);
2660         struct txbd8 *bdp, *next = NULL;
2661         struct txbd8 *lbdp = NULL;
2662         struct txbd8 *base = tx_queue->tx_bd_base;
2663         struct sk_buff *skb;
2664         int skb_dirtytx;
2665         int tx_ring_size = tx_queue->tx_ring_size;
2666         int frags = 0, nr_txbds = 0;
2667         int i;
2668         int howmany = 0;
2669         int tqi = tx_queue->qindex;
2670         unsigned int bytes_sent = 0;
2671         u32 lstatus;
2672         size_t buflen;
2673
2674         txq = netdev_get_tx_queue(dev, tqi);
2675         bdp = tx_queue->dirty_tx;
2676         skb_dirtytx = tx_queue->skb_dirtytx;
2677
2678         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2679
2680                 frags = skb_shinfo(skb)->nr_frags;
2681
2682                 /* When time stamping, one additional TxBD must be freed.
2683                  * Also, we need to dma_unmap_single() the TxPAL.
2684                  */
2685                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2686                         nr_txbds = frags + 2;
2687                 else
2688                         nr_txbds = frags + 1;
2689
2690                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2691
2692                 lstatus = be32_to_cpu(lbdp->lstatus);
2693
2694                 /* Only clean completed frames */
2695                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2696                     (lstatus & BD_LENGTH_MASK))
2697                         break;
2698
2699                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2700                         next = next_txbd(bdp, base, tx_ring_size);
2701                         buflen = be16_to_cpu(next->length) +
2702                                  GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2703                 } else
2704                         buflen = be16_to_cpu(bdp->length);
2705
2706                 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2707                                  buflen, DMA_TO_DEVICE);
2708
2709                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2710                         struct skb_shared_hwtstamps shhwtstamps;
2711                         u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2712                                           ~0x7UL);
2713
2714                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2715                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2716                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2717                         skb_tstamp_tx(skb, &shhwtstamps);
2718                         gfar_clear_txbd_status(bdp);
2719                         bdp = next;
2720                 }
2721
2722                 gfar_clear_txbd_status(bdp);
2723                 bdp = next_txbd(bdp, base, tx_ring_size);
2724
2725                 for (i = 0; i < frags; i++) {
2726                         dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2727                                        be16_to_cpu(bdp->length),
2728                                        DMA_TO_DEVICE);
2729                         gfar_clear_txbd_status(bdp);
2730                         bdp = next_txbd(bdp, base, tx_ring_size);
2731                 }
2732
2733                 bytes_sent += GFAR_CB(skb)->bytes_sent;
2734
2735                 dev_kfree_skb_any(skb);
2736
2737                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2738
2739                 skb_dirtytx = (skb_dirtytx + 1) &
2740                               TX_RING_MOD_MASK(tx_ring_size);
2741
2742                 howmany++;
2743                 spin_lock(&tx_queue->txlock);
2744                 tx_queue->num_txbdfree += nr_txbds;
2745                 spin_unlock(&tx_queue->txlock);
2746         }
2747
2748         /* If we freed a buffer, we can restart transmission, if necessary */
2749         if (tx_queue->num_txbdfree &&
2750             netif_tx_queue_stopped(txq) &&
2751             !(test_bit(GFAR_DOWN, &priv->state)))
2752                 netif_wake_subqueue(priv->ndev, tqi);
2753
2754         /* Update dirty indicators */
2755         tx_queue->skb_dirtytx = skb_dirtytx;
2756         tx_queue->dirty_tx = bdp;
2757
2758         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2759 }
2760
2761 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
2762 {
2763         struct page *page;
2764         dma_addr_t addr;
2765
2766         page = dev_alloc_page();
2767         if (unlikely(!page))
2768                 return false;
2769
2770         addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
2771         if (unlikely(dma_mapping_error(rxq->dev, addr))) {
2772                 __free_page(page);
2773
2774                 return false;
2775         }
2776
2777         rxb->dma = addr;
2778         rxb->page = page;
2779         rxb->page_offset = 0;
2780
2781         return true;
2782 }
2783
2784 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
2785 {
2786         struct gfar_private *priv = netdev_priv(rx_queue->ndev);
2787         struct gfar_extra_stats *estats = &priv->extra_stats;
2788
2789         netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
2790         atomic64_inc(&estats->rx_alloc_err);
2791 }
2792
2793 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
2794                                 int alloc_cnt)
2795 {
2796         struct rxbd8 *bdp;
2797         struct gfar_rx_buff *rxb;
2798         int i;
2799
2800         i = rx_queue->next_to_use;
2801         bdp = &rx_queue->rx_bd_base[i];
2802         rxb = &rx_queue->rx_buff[i];
2803
2804         while (alloc_cnt--) {
2805                 /* try reuse page */
2806                 if (unlikely(!rxb->page)) {
2807                         if (unlikely(!gfar_new_page(rx_queue, rxb))) {
2808                                 gfar_rx_alloc_err(rx_queue);
2809                                 break;
2810                         }
2811                 }
2812
2813                 /* Setup the new RxBD */
2814                 gfar_init_rxbdp(rx_queue, bdp,
2815                                 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
2816
2817                 /* Update to the next pointer */
2818                 bdp++;
2819                 rxb++;
2820
2821                 if (unlikely(++i == rx_queue->rx_ring_size)) {
2822                         i = 0;
2823                         bdp = rx_queue->rx_bd_base;
2824                         rxb = rx_queue->rx_buff;
2825                 }
2826         }
2827
2828         rx_queue->next_to_use = i;
2829         rx_queue->next_to_alloc = i;
2830 }
2831
2832 static void count_errors(u32 lstatus, struct net_device *ndev)
2833 {
2834         struct gfar_private *priv = netdev_priv(ndev);
2835         struct net_device_stats *stats = &ndev->stats;
2836         struct gfar_extra_stats *estats = &priv->extra_stats;
2837
2838         /* If the packet was truncated, none of the other errors matter */
2839         if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2840                 stats->rx_length_errors++;
2841
2842                 atomic64_inc(&estats->rx_trunc);
2843
2844                 return;
2845         }
2846         /* Count the errors, if there were any */
2847         if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2848                 stats->rx_length_errors++;
2849
2850                 if (lstatus & BD_LFLAG(RXBD_LARGE))
2851                         atomic64_inc(&estats->rx_large);
2852                 else
2853                         atomic64_inc(&estats->rx_short);
2854         }
2855         if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2856                 stats->rx_frame_errors++;
2857                 atomic64_inc(&estats->rx_nonoctet);
2858         }
2859         if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2860                 atomic64_inc(&estats->rx_crcerr);
2861                 stats->rx_crc_errors++;
2862         }
2863         if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2864                 atomic64_inc(&estats->rx_overrun);
2865                 stats->rx_over_errors++;
2866         }
2867 }
2868
2869 irqreturn_t gfar_receive(int irq, void *grp_id)
2870 {
2871         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2872         unsigned long flags;
2873         u32 imask, ievent;
2874
2875         ievent = gfar_read(&grp->regs->ievent);
2876
2877         if (unlikely(ievent & IEVENT_FGPI)) {
2878                 gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2879                 return IRQ_HANDLED;
2880         }
2881
2882         if (likely(napi_schedule_prep(&grp->napi_rx))) {
2883                 spin_lock_irqsave(&grp->grplock, flags);
2884                 imask = gfar_read(&grp->regs->imask);
2885                 imask &= IMASK_RX_DISABLED;
2886                 gfar_write(&grp->regs->imask, imask);
2887                 spin_unlock_irqrestore(&grp->grplock, flags);
2888                 __napi_schedule(&grp->napi_rx);
2889         } else {
2890                 /* Clear IEVENT, so interrupts aren't called again
2891                  * because of the packets that have already arrived.
2892                  */
2893                 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2894         }
2895
2896         return IRQ_HANDLED;
2897 }
2898
2899 /* Interrupt Handler for Transmit complete */
2900 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2901 {
2902         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2903         unsigned long flags;
2904         u32 imask;
2905
2906         if (likely(napi_schedule_prep(&grp->napi_tx))) {
2907                 spin_lock_irqsave(&grp->grplock, flags);
2908                 imask = gfar_read(&grp->regs->imask);
2909                 imask &= IMASK_TX_DISABLED;
2910                 gfar_write(&grp->regs->imask, imask);
2911                 spin_unlock_irqrestore(&grp->grplock, flags);
2912                 __napi_schedule(&grp->napi_tx);
2913         } else {
2914                 /* Clear IEVENT, so interrupts aren't called again
2915                  * because of the packets that have already arrived.
2916                  */
2917                 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2918         }
2919
2920         return IRQ_HANDLED;
2921 }
2922
2923 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2924                              struct sk_buff *skb, bool first)
2925 {
2926         unsigned int size = lstatus & BD_LENGTH_MASK;
2927         struct page *page = rxb->page;
2928
2929         /* Remove the FCS from the packet length */
2930         if (likely(lstatus & BD_LFLAG(RXBD_LAST)))
2931                 size -= ETH_FCS_LEN;
2932
2933         if (likely(first))
2934                 skb_put(skb, size);
2935         else
2936                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2937                                 rxb->page_offset + RXBUF_ALIGNMENT,
2938                                 size, GFAR_RXB_TRUESIZE);
2939
2940         /* try reuse page */
2941         if (unlikely(page_count(page) != 1))
2942                 return false;
2943
2944         /* change offset to the other half */
2945         rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2946
2947         atomic_inc(&page->_count);
2948
2949         return true;
2950 }
2951
2952 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2953                                struct gfar_rx_buff *old_rxb)
2954 {
2955         struct gfar_rx_buff *new_rxb;
2956         u16 nta = rxq->next_to_alloc;
2957
2958         new_rxb = &rxq->rx_buff[nta];
2959
2960         /* find next buf that can reuse a page */
2961         nta++;
2962         rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2963
2964         /* copy page reference */
2965         *new_rxb = *old_rxb;
2966
2967         /* sync for use by the device */
2968         dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2969                                          old_rxb->page_offset,
2970                                          GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2971 }
2972
2973 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2974                                             u32 lstatus, struct sk_buff *skb)
2975 {
2976         struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2977         struct page *page = rxb->page;
2978         bool first = false;
2979
2980         if (likely(!skb)) {
2981                 void *buff_addr = page_address(page) + rxb->page_offset;
2982
2983                 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
2984                 if (unlikely(!skb)) {
2985                         gfar_rx_alloc_err(rx_queue);
2986                         return NULL;
2987                 }
2988                 skb_reserve(skb, RXBUF_ALIGNMENT);
2989                 first = true;
2990         }
2991
2992         dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
2993                                       GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2994
2995         if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
2996                 /* reuse the free half of the page */
2997                 gfar_reuse_rx_page(rx_queue, rxb);
2998         } else {
2999                 /* page cannot be reused, unmap it */
3000                 dma_unmap_page(rx_queue->dev, rxb->dma,
3001                                PAGE_SIZE, DMA_FROM_DEVICE);
3002         }
3003
3004         /* clear rxb content */
3005         rxb->page = NULL;
3006
3007         return skb;
3008 }
3009
3010 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
3011 {
3012         /* If valid headers were found, and valid sums
3013          * were verified, then we tell the kernel that no
3014          * checksumming is necessary.  Otherwise, it is [FIXME]
3015          */
3016         if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
3017             (RXFCB_CIP | RXFCB_CTU))
3018                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3019         else
3020                 skb_checksum_none_assert(skb);
3021 }
3022
3023 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
3024 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
3025 {
3026         struct gfar_private *priv = netdev_priv(ndev);
3027         struct rxfcb *fcb = NULL;
3028
3029         /* fcb is at the beginning if exists */
3030         fcb = (struct rxfcb *)skb->data;
3031
3032         /* Remove the FCB from the skb
3033          * Remove the padded bytes, if there are any
3034          */
3035         if (priv->uses_rxfcb)
3036                 skb_pull(skb, GMAC_FCB_LEN);
3037
3038         /* Get receive timestamp from the skb */
3039         if (priv->hwts_rx_en) {
3040                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
3041                 u64 *ns = (u64 *) skb->data;
3042
3043                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3044                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
3045         }
3046
3047         if (priv->padding)
3048                 skb_pull(skb, priv->padding);
3049
3050         if (ndev->features & NETIF_F_RXCSUM)
3051                 gfar_rx_checksum(skb, fcb);
3052
3053         /* Tell the skb what kind of packet this is */
3054         skb->protocol = eth_type_trans(skb, ndev);
3055
3056         /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
3057          * Even if vlan rx accel is disabled, on some chips
3058          * RXFCB_VLN is pseudo randomly set.
3059          */
3060         if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
3061             be16_to_cpu(fcb->flags) & RXFCB_VLN)
3062                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3063                                        be16_to_cpu(fcb->vlctl));
3064 }
3065
3066 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
3067  * until the budget/quota has been reached. Returns the number
3068  * of frames handled
3069  */
3070 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
3071 {
3072         struct net_device *ndev = rx_queue->ndev;
3073         struct gfar_private *priv = netdev_priv(ndev);
3074         struct rxbd8 *bdp;
3075         int i, howmany = 0;
3076         struct sk_buff *skb = rx_queue->skb;
3077         int cleaned_cnt = gfar_rxbd_unused(rx_queue);
3078         unsigned int total_bytes = 0, total_pkts = 0;
3079
3080         /* Get the first full descriptor */
3081         i = rx_queue->next_to_clean;
3082
3083         while (rx_work_limit--) {
3084                 u32 lstatus;
3085
3086                 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
3087                         gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3088                         cleaned_cnt = 0;
3089                 }
3090
3091                 bdp = &rx_queue->rx_bd_base[i];
3092                 lstatus = be32_to_cpu(bdp->lstatus);
3093                 if (lstatus & BD_LFLAG(RXBD_EMPTY))
3094                         break;
3095
3096                 /* order rx buffer descriptor reads */
3097                 rmb();
3098
3099                 /* fetch next to clean buffer from the ring */
3100                 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
3101                 if (unlikely(!skb))
3102                         break;
3103
3104                 cleaned_cnt++;
3105                 howmany++;
3106
3107                 if (unlikely(++i == rx_queue->rx_ring_size))
3108                         i = 0;
3109
3110                 rx_queue->next_to_clean = i;
3111
3112                 /* fetch next buffer if not the last in frame */
3113                 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
3114                         continue;
3115
3116                 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
3117                         count_errors(lstatus, ndev);
3118
3119                         /* discard faulty buffer */
3120                         dev_kfree_skb(skb);
3121                         skb = NULL;
3122                         rx_queue->stats.rx_dropped++;
3123                         continue;
3124                 }
3125
3126                 /* Increment the number of packets */
3127                 total_pkts++;
3128                 total_bytes += skb->len;
3129
3130                 skb_record_rx_queue(skb, rx_queue->qindex);
3131
3132                 gfar_process_frame(ndev, skb);
3133
3134                 /* Send the packet up the stack */
3135                 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
3136
3137                 skb = NULL;
3138         }
3139
3140         /* Store incomplete frames for completion */
3141         rx_queue->skb = skb;
3142
3143         rx_queue->stats.rx_packets += total_pkts;
3144         rx_queue->stats.rx_bytes += total_bytes;
3145
3146         if (cleaned_cnt)
3147                 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3148
3149         /* Update Last Free RxBD pointer for LFC */
3150         if (unlikely(priv->tx_actual_en)) {
3151                 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3152
3153                 gfar_write(rx_queue->rfbptr, bdp_dma);
3154         }
3155
3156         return howmany;
3157 }
3158
3159 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
3160 {
3161         struct gfar_priv_grp *gfargrp =
3162                 container_of(napi, struct gfar_priv_grp, napi_rx);
3163         struct gfar __iomem *regs = gfargrp->regs;
3164         struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
3165         int work_done = 0;
3166
3167         /* Clear IEVENT, so interrupts aren't called again
3168          * because of the packets that have already arrived
3169          */
3170         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3171
3172         work_done = gfar_clean_rx_ring(rx_queue, budget);
3173
3174         if (work_done < budget) {
3175                 u32 imask;
3176                 napi_complete(napi);
3177                 /* Clear the halt bit in RSTAT */
3178                 gfar_write(&regs->rstat, gfargrp->rstat);
3179
3180                 spin_lock_irq(&gfargrp->grplock);
3181                 imask = gfar_read(&regs->imask);
3182                 imask |= IMASK_RX_DEFAULT;
3183                 gfar_write(&regs->imask, imask);
3184                 spin_unlock_irq(&gfargrp->grplock);
3185         }
3186
3187         return work_done;
3188 }
3189
3190 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
3191 {
3192         struct gfar_priv_grp *gfargrp =
3193                 container_of(napi, struct gfar_priv_grp, napi_tx);
3194         struct gfar __iomem *regs = gfargrp->regs;
3195         struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
3196         u32 imask;
3197
3198         /* Clear IEVENT, so interrupts aren't called again
3199          * because of the packets that have already arrived
3200          */
3201         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3202
3203         /* run Tx cleanup to completion */
3204         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
3205                 gfar_clean_tx_ring(tx_queue);
3206
3207         napi_complete(napi);
3208
3209         spin_lock_irq(&gfargrp->grplock);
3210         imask = gfar_read(&regs->imask);
3211         imask |= IMASK_TX_DEFAULT;
3212         gfar_write(&regs->imask, imask);
3213         spin_unlock_irq(&gfargrp->grplock);
3214
3215         return 0;
3216 }
3217
3218 static int gfar_poll_rx(struct napi_struct *napi, int budget)
3219 {
3220         struct gfar_priv_grp *gfargrp =
3221                 container_of(napi, struct gfar_priv_grp, napi_rx);
3222         struct gfar_private *priv = gfargrp->priv;
3223         struct gfar __iomem *regs = gfargrp->regs;
3224         struct gfar_priv_rx_q *rx_queue = NULL;
3225         int work_done = 0, work_done_per_q = 0;
3226         int i, budget_per_q = 0;
3227         unsigned long rstat_rxf;
3228         int num_act_queues;
3229
3230         /* Clear IEVENT, so interrupts aren't called again
3231          * because of the packets that have already arrived
3232          */
3233         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3234
3235         rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
3236
3237         num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3238         if (num_act_queues)
3239                 budget_per_q = budget/num_act_queues;
3240
3241         for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3242                 /* skip queue if not active */
3243                 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3244                         continue;
3245
3246                 rx_queue = priv->rx_queue[i];
3247                 work_done_per_q =
3248                         gfar_clean_rx_ring(rx_queue, budget_per_q);
3249                 work_done += work_done_per_q;
3250
3251                 /* finished processing this queue */
3252                 if (work_done_per_q < budget_per_q) {
3253                         /* clear active queue hw indication */
3254                         gfar_write(&regs->rstat,
3255                                    RSTAT_CLEAR_RXF0 >> i);
3256                         num_act_queues--;
3257
3258                         if (!num_act_queues)
3259                                 break;
3260                 }
3261         }
3262
3263         if (!num_act_queues) {
3264                 u32 imask;
3265                 napi_complete(napi);
3266
3267                 /* Clear the halt bit in RSTAT */
3268                 gfar_write(&regs->rstat, gfargrp->rstat);
3269
3270                 spin_lock_irq(&gfargrp->grplock);
3271                 imask = gfar_read(&regs->imask);
3272                 imask |= IMASK_RX_DEFAULT;
3273                 gfar_write(&regs->imask, imask);
3274                 spin_unlock_irq(&gfargrp->grplock);
3275         }
3276
3277         return work_done;
3278 }
3279
3280 static int gfar_poll_tx(struct napi_struct *napi, int budget)
3281 {
3282         struct gfar_priv_grp *gfargrp =
3283                 container_of(napi, struct gfar_priv_grp, napi_tx);
3284         struct gfar_private *priv = gfargrp->priv;
3285         struct gfar __iomem *regs = gfargrp->regs;
3286         struct gfar_priv_tx_q *tx_queue = NULL;
3287         int has_tx_work = 0;
3288         int i;
3289
3290         /* Clear IEVENT, so interrupts aren't called again
3291          * because of the packets that have already arrived
3292          */
3293         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3294
3295         for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3296                 tx_queue = priv->tx_queue[i];
3297                 /* run Tx cleanup to completion */
3298                 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3299                         gfar_clean_tx_ring(tx_queue);
3300                         has_tx_work = 1;
3301                 }
3302         }
3303
3304         if (!has_tx_work) {
3305                 u32 imask;
3306                 napi_complete(napi);
3307
3308                 spin_lock_irq(&gfargrp->grplock);
3309                 imask = gfar_read(&regs->imask);
3310                 imask |= IMASK_TX_DEFAULT;
3311                 gfar_write(&regs->imask, imask);
3312                 spin_unlock_irq(&gfargrp->grplock);
3313         }
3314
3315         return 0;
3316 }
3317
3318
3319 #ifdef CONFIG_NET_POLL_CONTROLLER
3320 /* Polling 'interrupt' - used by things like netconsole to send skbs
3321  * without having to re-enable interrupts. It's not called while
3322  * the interrupt routine is executing.
3323  */
3324 static void gfar_netpoll(struct net_device *dev)
3325 {
3326         struct gfar_private *priv = netdev_priv(dev);
3327         int i;
3328
3329         /* If the device has multiple interrupts, run tx/rx */
3330         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3331                 for (i = 0; i < priv->num_grps; i++) {
3332                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3333
3334                         disable_irq(gfar_irq(grp, TX)->irq);
3335                         disable_irq(gfar_irq(grp, RX)->irq);
3336                         disable_irq(gfar_irq(grp, ER)->irq);
3337                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3338                         enable_irq(gfar_irq(grp, ER)->irq);
3339                         enable_irq(gfar_irq(grp, RX)->irq);
3340                         enable_irq(gfar_irq(grp, TX)->irq);
3341                 }
3342         } else {
3343                 for (i = 0; i < priv->num_grps; i++) {
3344                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3345
3346                         disable_irq(gfar_irq(grp, TX)->irq);
3347                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3348                         enable_irq(gfar_irq(grp, TX)->irq);
3349                 }
3350         }
3351 }
3352 #endif
3353
3354 /* The interrupt handler for devices with one interrupt */
3355 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3356 {
3357         struct gfar_priv_grp *gfargrp = grp_id;
3358
3359         /* Save ievent for future reference */
3360         u32 events = gfar_read(&gfargrp->regs->ievent);
3361
3362         /* Check for reception */
3363         if (events & IEVENT_RX_MASK)
3364                 gfar_receive(irq, grp_id);
3365
3366         /* Check for transmit completion */
3367         if (events & IEVENT_TX_MASK)
3368                 gfar_transmit(irq, grp_id);
3369
3370         /* Check for errors */
3371         if (events & IEVENT_ERR_MASK)
3372                 gfar_error(irq, grp_id);
3373
3374         return IRQ_HANDLED;
3375 }
3376
3377 /* Called every time the controller might need to be made
3378  * aware of new link state.  The PHY code conveys this
3379  * information through variables in the phydev structure, and this
3380  * function converts those variables into the appropriate
3381  * register values, and can bring down the device if needed.
3382  */
3383 static void adjust_link(struct net_device *dev)
3384 {
3385         struct gfar_private *priv = netdev_priv(dev);
3386         struct phy_device *phydev = priv->phydev;
3387
3388         if (unlikely(phydev->link != priv->oldlink ||
3389                      (phydev->link && (phydev->duplex != priv->oldduplex ||
3390                                        phydev->speed != priv->oldspeed))))
3391                 gfar_update_link_state(priv);
3392 }
3393
3394 /* Update the hash table based on the current list of multicast
3395  * addresses we subscribe to.  Also, change the promiscuity of
3396  * the device based on the flags (this function is called
3397  * whenever dev->flags is changed
3398  */
3399 static void gfar_set_multi(struct net_device *dev)
3400 {
3401         struct netdev_hw_addr *ha;
3402         struct gfar_private *priv = netdev_priv(dev);
3403         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3404         u32 tempval;
3405
3406         if (dev->flags & IFF_PROMISC) {
3407                 /* Set RCTRL to PROM */
3408                 tempval = gfar_read(&regs->rctrl);
3409                 tempval |= RCTRL_PROM;
3410                 gfar_write(&regs->rctrl, tempval);
3411         } else {
3412                 /* Set RCTRL to not PROM */
3413                 tempval = gfar_read(&regs->rctrl);
3414                 tempval &= ~(RCTRL_PROM);
3415                 gfar_write(&regs->rctrl, tempval);
3416         }
3417
3418         if (dev->flags & IFF_ALLMULTI) {
3419                 /* Set the hash to rx all multicast frames */
3420                 gfar_write(&regs->igaddr0, 0xffffffff);
3421                 gfar_write(&regs->igaddr1, 0xffffffff);
3422                 gfar_write(&regs->igaddr2, 0xffffffff);
3423                 gfar_write(&regs->igaddr3, 0xffffffff);
3424                 gfar_write(&regs->igaddr4, 0xffffffff);
3425                 gfar_write(&regs->igaddr5, 0xffffffff);
3426                 gfar_write(&regs->igaddr6, 0xffffffff);
3427                 gfar_write(&regs->igaddr7, 0xffffffff);
3428                 gfar_write(&regs->gaddr0, 0xffffffff);
3429                 gfar_write(&regs->gaddr1, 0xffffffff);
3430                 gfar_write(&regs->gaddr2, 0xffffffff);
3431                 gfar_write(&regs->gaddr3, 0xffffffff);
3432                 gfar_write(&regs->gaddr4, 0xffffffff);
3433                 gfar_write(&regs->gaddr5, 0xffffffff);
3434                 gfar_write(&regs->gaddr6, 0xffffffff);
3435                 gfar_write(&regs->gaddr7, 0xffffffff);
3436         } else {
3437                 int em_num;
3438                 int idx;
3439
3440                 /* zero out the hash */
3441                 gfar_write(&regs->igaddr0, 0x0);
3442                 gfar_write(&regs->igaddr1, 0x0);
3443                 gfar_write(&regs->igaddr2, 0x0);
3444                 gfar_write(&regs->igaddr3, 0x0);
3445                 gfar_write(&regs->igaddr4, 0x0);
3446                 gfar_write(&regs->igaddr5, 0x0);
3447                 gfar_write(&regs->igaddr6, 0x0);
3448                 gfar_write(&regs->igaddr7, 0x0);
3449                 gfar_write(&regs->gaddr0, 0x0);
3450                 gfar_write(&regs->gaddr1, 0x0);
3451                 gfar_write(&regs->gaddr2, 0x0);
3452                 gfar_write(&regs->gaddr3, 0x0);
3453                 gfar_write(&regs->gaddr4, 0x0);
3454                 gfar_write(&regs->gaddr5, 0x0);
3455                 gfar_write(&regs->gaddr6, 0x0);
3456                 gfar_write(&regs->gaddr7, 0x0);
3457
3458                 /* If we have extended hash tables, we need to
3459                  * clear the exact match registers to prepare for
3460                  * setting them
3461                  */
3462                 if (priv->extended_hash) {
3463                         em_num = GFAR_EM_NUM + 1;
3464                         gfar_clear_exact_match(dev);
3465                         idx = 1;
3466                 } else {
3467                         idx = 0;
3468                         em_num = 0;
3469                 }
3470
3471                 if (netdev_mc_empty(dev))
3472                         return;
3473
3474                 /* Parse the list, and set the appropriate bits */
3475                 netdev_for_each_mc_addr(ha, dev) {
3476                         if (idx < em_num) {
3477                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3478                                 idx++;
3479                         } else
3480                                 gfar_set_hash_for_addr(dev, ha->addr);
3481                 }
3482         }
3483 }
3484
3485
3486 /* Clears each of the exact match registers to zero, so they
3487  * don't interfere with normal reception
3488  */
3489 static void gfar_clear_exact_match(struct net_device *dev)
3490 {
3491         int idx;
3492         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3493
3494         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3495                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3496 }
3497
3498 /* Set the appropriate hash bit for the given addr */
3499 /* The algorithm works like so:
3500  * 1) Take the Destination Address (ie the multicast address), and
3501  * do a CRC on it (little endian), and reverse the bits of the
3502  * result.
3503  * 2) Use the 8 most significant bits as a hash into a 256-entry
3504  * table.  The table is controlled through 8 32-bit registers:
3505  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3506  * gaddr7.  This means that the 3 most significant bits in the
3507  * hash index which gaddr register to use, and the 5 other bits
3508  * indicate which bit (assuming an IBM numbering scheme, which
3509  * for PowerPC (tm) is usually the case) in the register holds
3510  * the entry.
3511  */
3512 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3513 {
3514         u32 tempval;
3515         struct gfar_private *priv = netdev_priv(dev);
3516         u32 result = ether_crc(ETH_ALEN, addr);
3517         int width = priv->hash_width;
3518         u8 whichbit = (result >> (32 - width)) & 0x1f;
3519         u8 whichreg = result >> (32 - width + 5);
3520         u32 value = (1 << (31-whichbit));
3521
3522         tempval = gfar_read(priv->hash_regs[whichreg]);
3523         tempval |= value;
3524         gfar_write(priv->hash_regs[whichreg], tempval);
3525 }
3526
3527
3528 /* There are multiple MAC Address register pairs on some controllers
3529  * This function sets the numth pair to a given address
3530  */
3531 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3532                                   const u8 *addr)
3533 {
3534         struct gfar_private *priv = netdev_priv(dev);
3535         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3536         u32 tempval;
3537         u32 __iomem *macptr = &regs->macstnaddr1;
3538
3539         macptr += num*2;
3540
3541         /* For a station address of 0x12345678ABCD in transmission
3542          * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3543          * MACnADDR2 is set to 0x34120000.
3544          */
3545         tempval = (addr[5] << 24) | (addr[4] << 16) |
3546                   (addr[3] << 8)  |  addr[2];
3547
3548         gfar_write(macptr, tempval);
3549
3550         tempval = (addr[1] << 24) | (addr[0] << 16);
3551
3552         gfar_write(macptr+1, tempval);
3553 }
3554
3555 /* GFAR error interrupt handler */
3556 static irqreturn_t gfar_error(int irq, void *grp_id)
3557 {
3558         struct gfar_priv_grp *gfargrp = grp_id;
3559         struct gfar __iomem *regs = gfargrp->regs;
3560         struct gfar_private *priv= gfargrp->priv;
3561         struct net_device *dev = priv->ndev;
3562
3563         /* Save ievent for future reference */
3564         u32 events = gfar_read(&regs->ievent);
3565
3566         /* Clear IEVENT */
3567         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3568
3569         /* Magic Packet is not an error. */
3570         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3571             (events & IEVENT_MAG))
3572                 events &= ~IEVENT_MAG;
3573
3574         /* Hmm... */
3575         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3576                 netdev_dbg(dev,
3577                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3578                            events, gfar_read(&regs->imask));
3579
3580         /* Update the error counters */
3581         if (events & IEVENT_TXE) {
3582                 dev->stats.tx_errors++;
3583
3584                 if (events & IEVENT_LC)
3585                         dev->stats.tx_window_errors++;
3586                 if (events & IEVENT_CRL)
3587                         dev->stats.tx_aborted_errors++;
3588                 if (events & IEVENT_XFUN) {
3589                         netif_dbg(priv, tx_err, dev,
3590                                   "TX FIFO underrun, packet dropped\n");
3591                         dev->stats.tx_dropped++;
3592                         atomic64_inc(&priv->extra_stats.tx_underrun);
3593
3594                         schedule_work(&priv->reset_task);
3595                 }
3596                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3597         }
3598         if (events & IEVENT_BSY) {
3599                 dev->stats.rx_over_errors++;
3600                 atomic64_inc(&priv->extra_stats.rx_bsy);
3601
3602                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3603                           gfar_read(&regs->rstat));
3604         }
3605         if (events & IEVENT_BABR) {
3606                 dev->stats.rx_errors++;
3607                 atomic64_inc(&priv->extra_stats.rx_babr);
3608
3609                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3610         }
3611         if (events & IEVENT_EBERR) {
3612                 atomic64_inc(&priv->extra_stats.eberr);
3613                 netif_dbg(priv, rx_err, dev, "bus error\n");
3614         }
3615         if (events & IEVENT_RXC)
3616                 netif_dbg(priv, rx_status, dev, "control frame\n");
3617
3618         if (events & IEVENT_BABT) {
3619                 atomic64_inc(&priv->extra_stats.tx_babt);
3620                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3621         }
3622         return IRQ_HANDLED;
3623 }
3624
3625 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3626 {
3627         struct phy_device *phydev = priv->phydev;
3628         u32 val = 0;
3629
3630         if (!phydev->duplex)
3631                 return val;
3632
3633         if (!priv->pause_aneg_en) {
3634                 if (priv->tx_pause_en)
3635                         val |= MACCFG1_TX_FLOW;
3636                 if (priv->rx_pause_en)
3637                         val |= MACCFG1_RX_FLOW;
3638         } else {
3639                 u16 lcl_adv, rmt_adv;
3640                 u8 flowctrl;
3641                 /* get link partner capabilities */
3642                 rmt_adv = 0;
3643                 if (phydev->pause)
3644                         rmt_adv = LPA_PAUSE_CAP;
3645                 if (phydev->asym_pause)
3646                         rmt_adv |= LPA_PAUSE_ASYM;
3647
3648                 lcl_adv = 0;
3649                 if (phydev->advertising & ADVERTISED_Pause)
3650                         lcl_adv |= ADVERTISE_PAUSE_CAP;
3651                 if (phydev->advertising & ADVERTISED_Asym_Pause)
3652                         lcl_adv |= ADVERTISE_PAUSE_ASYM;
3653
3654                 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3655                 if (flowctrl & FLOW_CTRL_TX)
3656                         val |= MACCFG1_TX_FLOW;
3657                 if (flowctrl & FLOW_CTRL_RX)
3658                         val |= MACCFG1_RX_FLOW;
3659         }
3660
3661         return val;
3662 }
3663
3664 static noinline void gfar_update_link_state(struct gfar_private *priv)
3665 {
3666         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3667         struct phy_device *phydev = priv->phydev;
3668         struct gfar_priv_rx_q *rx_queue = NULL;
3669         int i;
3670
3671         if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3672                 return;
3673
3674         if (phydev->link) {
3675                 u32 tempval1 = gfar_read(&regs->maccfg1);
3676                 u32 tempval = gfar_read(&regs->maccfg2);
3677                 u32 ecntrl = gfar_read(&regs->ecntrl);
3678                 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW);
3679
3680                 if (phydev->duplex != priv->oldduplex) {
3681                         if (!(phydev->duplex))
3682                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
3683                         else
3684                                 tempval |= MACCFG2_FULL_DUPLEX;
3685
3686                         priv->oldduplex = phydev->duplex;
3687                 }
3688
3689                 if (phydev->speed != priv->oldspeed) {
3690                         switch (phydev->speed) {
3691                         case 1000:
3692                                 tempval =
3693                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3694
3695                                 ecntrl &= ~(ECNTRL_R100);
3696                                 break;
3697                         case 100:
3698                         case 10:
3699                                 tempval =
3700                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3701
3702                                 /* Reduced mode distinguishes
3703                                  * between 10 and 100
3704                                  */
3705                                 if (phydev->speed == SPEED_100)
3706                                         ecntrl |= ECNTRL_R100;
3707                                 else
3708                                         ecntrl &= ~(ECNTRL_R100);
3709                                 break;
3710                         default:
3711                                 netif_warn(priv, link, priv->ndev,
3712                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3713                                            phydev->speed);
3714                                 break;
3715                         }
3716
3717                         priv->oldspeed = phydev->speed;
3718                 }
3719
3720                 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3721                 tempval1 |= gfar_get_flowctrl_cfg(priv);
3722
3723                 /* Turn last free buffer recording on */
3724                 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3725                         for (i = 0; i < priv->num_rx_queues; i++) {
3726                                 u32 bdp_dma;
3727
3728                                 rx_queue = priv->rx_queue[i];
3729                                 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3730                                 gfar_write(rx_queue->rfbptr, bdp_dma);
3731                         }
3732
3733                         priv->tx_actual_en = 1;
3734                 }
3735
3736                 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3737                         priv->tx_actual_en = 0;
3738
3739                 gfar_write(&regs->maccfg1, tempval1);
3740                 gfar_write(&regs->maccfg2, tempval);
3741                 gfar_write(&regs->ecntrl, ecntrl);
3742
3743                 if (!priv->oldlink)
3744                         priv->oldlink = 1;
3745
3746         } else if (priv->oldlink) {
3747                 priv->oldlink = 0;
3748                 priv->oldspeed = 0;
3749                 priv->oldduplex = -1;
3750         }
3751
3752         if (netif_msg_link(priv))
3753                 phy_print_status(phydev);
3754 }
3755
3756 static const struct of_device_id gfar_match[] =
3757 {
3758         {
3759                 .type = "network",
3760                 .compatible = "gianfar",
3761         },
3762         {
3763                 .compatible = "fsl,etsec2",
3764         },
3765         {},
3766 };
3767 MODULE_DEVICE_TABLE(of, gfar_match);
3768
3769 /* Structure for a device driver */
3770 static struct platform_driver gfar_driver = {
3771         .driver = {
3772                 .name = "fsl-gianfar",
3773                 .pm = GFAR_PM_OPS,
3774                 .of_match_table = gfar_match,
3775         },
3776         .probe = gfar_probe,
3777         .remove = gfar_remove,
3778 };
3779
3780 module_platform_driver(gfar_driver);