1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 #include "fman_memac.h"
12 #include <linux/slab.h>
14 #include <linux/pcs-lynx.h>
15 #include <linux/phy.h>
16 #include <linux/phy_fixed.h>
17 #include <linux/phy/phy.h>
18 #include <linux/of_mdio.h>
20 /* Num of additional exact match MAC adr regs */
21 #define MEMAC_NUM_OF_PADDRS 7
23 /* Control and Configuration Register (COMMAND_CONFIG) */
24 #define CMD_CFG_REG_LOWP_RXETY 0x01000000 /* 07 Rx low power indication */
25 #define CMD_CFG_TX_LOWP_ENA 0x00800000 /* 08 Tx Low Power Idle Enable */
26 #define CMD_CFG_PFC_MODE 0x00080000 /* 12 Enable PFC */
27 #define CMD_CFG_NO_LEN_CHK 0x00020000 /* 14 Payload length check disable */
28 #define CMD_CFG_SW_RESET 0x00001000 /* 19 S/W Reset, self clearing bit */
29 #define CMD_CFG_TX_PAD_EN 0x00000800 /* 20 Enable Tx padding of frames */
30 #define CMD_CFG_PAUSE_IGNORE 0x00000100 /* 23 Ignore Pause frame quanta */
31 #define CMD_CFG_CRC_FWD 0x00000040 /* 25 Terminate/frwd CRC of frames */
32 #define CMD_CFG_PAD_EN 0x00000020 /* 26 Frame padding removal */
33 #define CMD_CFG_PROMIS_EN 0x00000010 /* 27 Promiscuous operation enable */
34 #define CMD_CFG_RX_EN 0x00000002 /* 30 MAC receive path enable */
35 #define CMD_CFG_TX_EN 0x00000001 /* 31 MAC transmit path enable */
37 /* Transmit FIFO Sections Register (TX_FIFO_SECTIONS) */
38 #define TX_FIFO_SECTIONS_TX_EMPTY_MASK 0xFFFF0000
39 #define TX_FIFO_SECTIONS_TX_AVAIL_MASK 0x0000FFFF
40 #define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G 0x00400000
41 #define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G 0x00100000
42 #define TX_FIFO_SECTIONS_TX_AVAIL_10G 0x00000019
43 #define TX_FIFO_SECTIONS_TX_AVAIL_1G 0x00000020
44 #define TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G 0x00000060
46 #define GET_TX_EMPTY_DEFAULT_VALUE(_val) \
48 _val &= ~TX_FIFO_SECTIONS_TX_EMPTY_MASK; \
49 ((_val == TX_FIFO_SECTIONS_TX_AVAIL_10G) ? \
50 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G) :\
51 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G));\
54 /* Interface Mode Register (IF_MODE) */
56 #define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */
57 #define IF_MODE_10G 0x00000000 /* 30-31 10G interface */
58 #define IF_MODE_MII 0x00000001 /* 30-31 MII interface */
59 #define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */
60 #define IF_MODE_RGMII 0x00000004
61 #define IF_MODE_RGMII_AUTO 0x00008000
62 #define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */
63 #define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */
64 #define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */
65 #define IF_MODE_RGMII_SP_MASK 0x00006000 /* Setsp mask bits */
66 #define IF_MODE_RGMII_FD 0x00001000 /* Full duplex RGMII */
67 #define IF_MODE_HD 0x00000040 /* Half duplex operation */
69 /* Hash table Control Register (HASHTABLE_CTRL) */
70 #define HASH_CTRL_MCAST_EN 0x00000100
71 /* 26-31 Hash table address code */
72 #define HASH_CTRL_ADDR_MASK 0x0000003F
73 /* MAC mcast indication */
74 #define GROUP_ADDRESS 0x0000010000000000LL
75 #define HASH_TABLE_SIZE 64 /* Hash tbl size */
77 /* Interrupt Mask Register (IMASK) */
78 #define MEMAC_IMASK_MGI 0x40000000 /* 1 Magic pkt detect indication */
79 #define MEMAC_IMASK_TSECC_ER 0x20000000 /* 2 Timestamp FIFO ECC error evnt */
80 #define MEMAC_IMASK_TECC_ER 0x02000000 /* 6 Transmit frame ECC error evnt */
81 #define MEMAC_IMASK_RECC_ER 0x01000000 /* 7 Receive frame ECC error evnt */
83 #define MEMAC_ALL_ERRS_IMASK \
84 ((u32)(MEMAC_IMASK_TSECC_ER | \
85 MEMAC_IMASK_TECC_ER | \
86 MEMAC_IMASK_RECC_ER | \
89 #define MEMAC_IEVNT_PCS 0x80000000 /* PCS (XG). Link sync (G) */
90 #define MEMAC_IEVNT_AN 0x40000000 /* Auto-negotiation */
91 #define MEMAC_IEVNT_LT 0x20000000 /* Link Training/New page */
92 #define MEMAC_IEVNT_MGI 0x00004000 /* Magic pkt detection */
93 #define MEMAC_IEVNT_TS_ECC_ER 0x00002000 /* Timestamp FIFO ECC error*/
94 #define MEMAC_IEVNT_RX_FIFO_OVFL 0x00001000 /* Rx FIFO overflow */
95 #define MEMAC_IEVNT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */
96 #define MEMAC_IEVNT_TX_FIFO_OVFL 0x00000400 /* Tx FIFO overflow */
97 #define MEMAC_IEVNT_TX_ECC_ER 0x00000200 /* Tx frame ECC error */
98 #define MEMAC_IEVNT_RX_ECC_ER 0x00000100 /* Rx frame ECC error */
99 #define MEMAC_IEVNT_LI_FAULT 0x00000080 /* Link Interruption flt */
100 #define MEMAC_IEVNT_RX_EMPTY 0x00000040 /* Rx FIFO empty */
101 #define MEMAC_IEVNT_TX_EMPTY 0x00000020 /* Tx FIFO empty */
102 #define MEMAC_IEVNT_RX_LOWP 0x00000010 /* Low Power Idle */
103 #define MEMAC_IEVNT_PHY_LOS 0x00000004 /* Phy loss of signal */
104 #define MEMAC_IEVNT_REM_FAULT 0x00000002 /* Remote fault (XGMII) */
105 #define MEMAC_IEVNT_LOC_FAULT 0x00000001 /* Local fault (XGMII) */
107 #define DEFAULT_PAUSE_QUANTA 0xf000
108 #define DEFAULT_FRAME_LENGTH 0x600
109 #define DEFAULT_TX_IPG_LENGTH 12
111 #define CLXY_PAUSE_QUANTA_CLX_PQNT 0x0000FFFF
112 #define CLXY_PAUSE_QUANTA_CLY_PQNT 0xFFFF0000
113 #define CLXY_PAUSE_THRESH_CLX_QTH 0x0000FFFF
114 #define CLXY_PAUSE_THRESH_CLY_QTH 0xFFFF0000
117 /* Lower 32 bits of 48-bit MAC address */
119 /* Upper 16 bits of 48-bit MAC address */
125 u32 res0000[2]; /* General Control and Status */
126 u32 command_config; /* 0x008 Ctrl and cfg */
127 struct mac_addr mac_addr0; /* 0x00C-0x010 MAC_ADDR_0...1 */
128 u32 maxfrm; /* 0x014 Max frame length */
130 u32 rx_fifo_sections; /* Receive FIFO configuration reg */
131 u32 tx_fifo_sections; /* Transmit FIFO configuration reg */
133 u32 hashtable_ctrl; /* 0x02C Hash table control */
135 u32 ievent; /* 0x040 Interrupt event */
136 u32 tx_ipg_length; /* 0x044 Transmitter inter-packet-gap */
138 u32 imask; /* 0x04C Interrupt mask */
140 u32 pause_quanta[4]; /* 0x054 Pause quanta */
141 u32 pause_thresh[4]; /* 0x064 Pause quanta threshold */
142 u32 rx_pause_status; /* 0x074 Receive pause status */
144 struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS];/* 0x80-0x0B4 mac padr */
145 u32 lpwake_timer; /* 0x0B8 Low Power Wakeup Timer */
146 u32 sleep_timer; /* 0x0BC Transmit EEE Low Power Timer */
148 u32 statn_config; /* 0x0E0 Statistics configuration */
150 /* Rx Statistics Counter */
204 /* Tx Statistics Counter */
249 /* Line Interface Control */
250 u32 if_mode; /* 0x300 Interface Mode Control */
251 u32 if_status; /* 0x304 Interface Status */
254 u32 hg_config; /* 0x340 Control and cfg */
256 u32 hg_pause_quanta; /* 0x350 Pause quanta */
258 u32 hg_pause_thresh; /* 0x360 Pause quanta threshold */
260 u32 hgrx_pause_status; /* 0x370 Receive pause status */
261 u32 hg_fifos_status; /* 0x374 fifos status */
262 u32 rhm; /* 0x378 rx messages counter */
263 u32 thm; /* 0x37C tx messages counter */
269 bool promiscuous_mode_enable;
270 struct fixed_phy_status *fixed_link;
271 u16 max_frame_length;
277 /* Pointer to MAC memory mapped registers */
278 struct memac_regs __iomem *regs;
279 /* MAC address of device */
281 struct mac_device *dev_id; /* device cookie used by the exception cbs */
282 fman_mac_exception_cb *exception_cb;
283 fman_mac_exception_cb *event_cb;
284 /* Pointer to driver's global address hash table */
285 struct eth_hash_t *multicast_addr_hash;
286 /* Pointer to driver's individual address hash table */
287 struct eth_hash_t *unicast_addr_hash;
290 struct memac_cfg *memac_drv_param;
292 struct fman_rev_info fm_rev_info;
294 struct phylink_pcs *sgmii_pcs;
295 struct phylink_pcs *qsgmii_pcs;
296 struct phylink_pcs *xfi_pcs;
297 bool allmulti_enabled;
298 bool rgmii_no_half_duplex;
301 static void add_addr_in_paddr(struct memac_regs __iomem *regs, const u8 *adr,
306 tmp0 = (u32)(adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24);
307 tmp1 = (u32)(adr[4] | adr[5] << 8);
309 if (paddr_num == 0) {
310 iowrite32be(tmp0, ®s->mac_addr0.mac_addr_l);
311 iowrite32be(tmp1, ®s->mac_addr0.mac_addr_u);
313 iowrite32be(tmp0, ®s->mac_addr[paddr_num - 1].mac_addr_l);
314 iowrite32be(tmp1, ®s->mac_addr[paddr_num - 1].mac_addr_u);
318 static int reset(struct memac_regs __iomem *regs)
323 tmp = ioread32be(®s->command_config);
325 tmp |= CMD_CFG_SW_RESET;
327 iowrite32be(tmp, ®s->command_config);
332 } while ((ioread32be(®s->command_config) & CMD_CFG_SW_RESET) &&
341 static void set_exception(struct memac_regs __iomem *regs, u32 val,
346 tmp = ioread32be(®s->imask);
352 iowrite32be(tmp, ®s->imask);
355 static int init(struct memac_regs __iomem *regs, struct memac_cfg *cfg,
362 if (cfg->promiscuous_mode_enable)
363 tmp |= CMD_CFG_PROMIS_EN;
364 if (cfg->pause_ignore)
365 tmp |= CMD_CFG_PAUSE_IGNORE;
367 /* Payload length check disable */
368 tmp |= CMD_CFG_NO_LEN_CHK;
369 /* Enable padding of frames in transmit direction */
370 tmp |= CMD_CFG_TX_PAD_EN;
372 tmp |= CMD_CFG_CRC_FWD;
374 iowrite32be(tmp, ®s->command_config);
376 /* Max Frame Length */
377 iowrite32be((u32)cfg->max_frame_length, ®s->maxfrm);
380 iowrite32be((u32)cfg->pause_quanta, ®s->pause_quanta[0]);
381 iowrite32be((u32)0, ®s->pause_thresh[0]);
383 /* clear all pending events and set-up interrupts */
384 iowrite32be(0xffffffff, ®s->ievent);
385 set_exception(regs, exceptions, true);
390 static void set_dflts(struct memac_cfg *cfg)
392 cfg->reset_on_init = false;
393 cfg->promiscuous_mode_enable = false;
394 cfg->pause_ignore = false;
395 cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH;
396 cfg->max_frame_length = DEFAULT_FRAME_LENGTH;
397 cfg->pause_quanta = DEFAULT_PAUSE_QUANTA;
400 static u32 get_mac_addr_hash_code(u64 eth_addr)
406 for (i = 0; i < 6; i++) {
407 mask1 = eth_addr & (u64)0x01;
410 for (j = 0; j < 7; j++) {
411 mask2 = eth_addr & (u64)0x01;
416 xor_val |= (mask1 << (5 - i));
422 static int check_init_parameters(struct fman_mac *memac)
424 if (!memac->exception_cb) {
425 pr_err("Uninitialized exception handler\n");
428 if (!memac->event_cb) {
429 pr_warn("Uninitialize event handler\n");
436 static int get_exception_flag(enum fman_mac_exceptions exception)
441 case FM_MAC_EX_10G_TX_ECC_ER:
442 bit_mask = MEMAC_IMASK_TECC_ER;
444 case FM_MAC_EX_10G_RX_ECC_ER:
445 bit_mask = MEMAC_IMASK_RECC_ER;
447 case FM_MAC_EX_TS_FIFO_ECC_ERR:
448 bit_mask = MEMAC_IMASK_TSECC_ER;
450 case FM_MAC_EX_MAGIC_PACKET_INDICATION:
451 bit_mask = MEMAC_IMASK_MGI;
461 static void memac_err_exception(void *handle)
463 struct fman_mac *memac = (struct fman_mac *)handle;
464 struct memac_regs __iomem *regs = memac->regs;
467 event = ioread32be(®s->ievent);
468 imask = ioread32be(®s->imask);
470 /* Imask include both error and notification/event bits.
471 * Leaving only error bits enabled by imask.
472 * The imask error bits are shifted by 16 bits offset from
473 * their corresponding location in the ievent - hence the >> 16
475 event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16);
477 iowrite32be(event, ®s->ievent);
479 if (event & MEMAC_IEVNT_TS_ECC_ER)
480 memac->exception_cb(memac->dev_id, FM_MAC_EX_TS_FIFO_ECC_ERR);
481 if (event & MEMAC_IEVNT_TX_ECC_ER)
482 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_TX_ECC_ER);
483 if (event & MEMAC_IEVNT_RX_ECC_ER)
484 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_RX_ECC_ER);
487 static void memac_exception(void *handle)
489 struct fman_mac *memac = (struct fman_mac *)handle;
490 struct memac_regs __iomem *regs = memac->regs;
493 event = ioread32be(®s->ievent);
494 imask = ioread32be(®s->imask);
496 /* Imask include both error and notification/event bits.
497 * Leaving only error bits enabled by imask.
498 * The imask error bits are shifted by 16 bits offset from
499 * their corresponding location in the ievent - hence the >> 16
501 event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16);
503 iowrite32be(event, ®s->ievent);
505 if (event & MEMAC_IEVNT_MGI)
506 memac->exception_cb(memac->dev_id,
507 FM_MAC_EX_MAGIC_PACKET_INDICATION);
510 static void free_init_resources(struct fman_mac *memac)
512 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
515 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
516 FMAN_INTR_TYPE_NORMAL);
518 /* release the driver's group hash table */
519 free_hash_table(memac->multicast_addr_hash);
520 memac->multicast_addr_hash = NULL;
522 /* release the driver's individual hash table */
523 free_hash_table(memac->unicast_addr_hash);
524 memac->unicast_addr_hash = NULL;
527 static int memac_enable(struct fman_mac *memac)
531 ret = phy_init(memac->serdes);
533 dev_err(memac->dev_id->dev,
534 "could not initialize serdes: %pe\n", ERR_PTR(ret));
538 ret = phy_power_on(memac->serdes);
540 dev_err(memac->dev_id->dev,
541 "could not power on serdes: %pe\n", ERR_PTR(ret));
542 phy_exit(memac->serdes);
548 static void memac_disable(struct fman_mac *memac)
550 phy_power_off(memac->serdes);
551 phy_exit(memac->serdes);
554 static int memac_set_promiscuous(struct fman_mac *memac, bool new_val)
556 struct memac_regs __iomem *regs = memac->regs;
559 tmp = ioread32be(®s->command_config);
561 tmp |= CMD_CFG_PROMIS_EN;
563 tmp &= ~CMD_CFG_PROMIS_EN;
565 iowrite32be(tmp, ®s->command_config);
570 static int memac_set_tx_pause_frames(struct fman_mac *memac, u8 priority,
571 u16 pause_time, u16 thresh_time)
573 struct memac_regs __iomem *regs = memac->regs;
576 tmp = ioread32be(®s->tx_fifo_sections);
578 GET_TX_EMPTY_DEFAULT_VALUE(tmp);
579 iowrite32be(tmp, ®s->tx_fifo_sections);
581 tmp = ioread32be(®s->command_config);
582 tmp &= ~CMD_CFG_PFC_MODE;
584 iowrite32be(tmp, ®s->command_config);
586 tmp = ioread32be(®s->pause_quanta[priority / 2]);
588 tmp &= CLXY_PAUSE_QUANTA_CLX_PQNT;
590 tmp &= CLXY_PAUSE_QUANTA_CLY_PQNT;
591 tmp |= ((u32)pause_time << (16 * (priority % 2)));
592 iowrite32be(tmp, ®s->pause_quanta[priority / 2]);
594 tmp = ioread32be(®s->pause_thresh[priority / 2]);
596 tmp &= CLXY_PAUSE_THRESH_CLX_QTH;
598 tmp &= CLXY_PAUSE_THRESH_CLY_QTH;
599 tmp |= ((u32)thresh_time << (16 * (priority % 2)));
600 iowrite32be(tmp, ®s->pause_thresh[priority / 2]);
605 static int memac_accept_rx_pause_frames(struct fman_mac *memac, bool en)
607 struct memac_regs __iomem *regs = memac->regs;
610 tmp = ioread32be(®s->command_config);
612 tmp &= ~CMD_CFG_PAUSE_IGNORE;
614 tmp |= CMD_CFG_PAUSE_IGNORE;
616 iowrite32be(tmp, ®s->command_config);
621 static void memac_validate(struct phylink_config *config,
622 unsigned long *supported,
623 struct phylink_link_state *state)
625 struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
626 unsigned long caps = config->mac_capabilities;
628 if (phy_interface_mode_is_rgmii(state->interface) &&
629 memac->rgmii_no_half_duplex)
630 caps &= ~(MAC_10HD | MAC_100HD);
632 phylink_validate_mask_caps(supported, state, caps);
636 * memac_if_mode() - Convert an interface mode into an IF_MODE config
637 * @interface: A phy interface mode
639 * Return: A configuration word, suitable for programming into the lower bits
642 static u32 memac_if_mode(phy_interface_t interface)
645 case PHY_INTERFACE_MODE_MII:
647 case PHY_INTERFACE_MODE_RGMII:
648 case PHY_INTERFACE_MODE_RGMII_ID:
649 case PHY_INTERFACE_MODE_RGMII_RXID:
650 case PHY_INTERFACE_MODE_RGMII_TXID:
651 return IF_MODE_GMII | IF_MODE_RGMII;
652 case PHY_INTERFACE_MODE_SGMII:
653 case PHY_INTERFACE_MODE_1000BASEX:
654 case PHY_INTERFACE_MODE_QSGMII:
656 case PHY_INTERFACE_MODE_10GBASER:
664 static struct phylink_pcs *memac_select_pcs(struct phylink_config *config,
665 phy_interface_t iface)
667 struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
670 case PHY_INTERFACE_MODE_SGMII:
671 case PHY_INTERFACE_MODE_1000BASEX:
672 return memac->sgmii_pcs;
673 case PHY_INTERFACE_MODE_QSGMII:
674 return memac->qsgmii_pcs;
675 case PHY_INTERFACE_MODE_10GBASER:
676 return memac->xfi_pcs;
682 static int memac_prepare(struct phylink_config *config, unsigned int mode,
683 phy_interface_t iface)
685 struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
688 case PHY_INTERFACE_MODE_SGMII:
689 case PHY_INTERFACE_MODE_1000BASEX:
690 case PHY_INTERFACE_MODE_QSGMII:
691 case PHY_INTERFACE_MODE_10GBASER:
692 return phy_set_mode_ext(memac->serdes, PHY_MODE_ETHERNET,
699 static void memac_mac_config(struct phylink_config *config, unsigned int mode,
700 const struct phylink_link_state *state)
702 struct mac_device *mac_dev = fman_config_to_mac(config);
703 struct memac_regs __iomem *regs = mac_dev->fman_mac->regs;
704 u32 tmp = ioread32be(®s->if_mode);
706 tmp &= ~(IF_MODE_MASK | IF_MODE_RGMII);
707 tmp |= memac_if_mode(state->interface);
708 if (phylink_autoneg_inband(mode))
709 tmp |= IF_MODE_RGMII_AUTO;
710 iowrite32be(tmp, ®s->if_mode);
713 static void memac_link_up(struct phylink_config *config, struct phy_device *phy,
714 unsigned int mode, phy_interface_t interface,
715 int speed, int duplex, bool tx_pause, bool rx_pause)
717 struct mac_device *mac_dev = fman_config_to_mac(config);
718 struct fman_mac *memac = mac_dev->fman_mac;
719 struct memac_regs __iomem *regs = memac->regs;
720 u32 tmp = memac_if_mode(interface);
721 u16 pause_time = tx_pause ? FSL_FM_PAUSE_TIME_ENABLE :
722 FSL_FM_PAUSE_TIME_DISABLE;
724 memac_set_tx_pause_frames(memac, 0, pause_time, 0);
725 memac_accept_rx_pause_frames(memac, rx_pause);
727 if (duplex == DUPLEX_HALF)
732 tmp |= IF_MODE_RGMII_1000;
735 tmp |= IF_MODE_RGMII_100;
738 tmp |= IF_MODE_RGMII_10;
741 iowrite32be(tmp, ®s->if_mode);
745 if (speed == SPEED_10000) {
746 if (memac->fm_rev_info.major == 6 &&
747 memac->fm_rev_info.minor == 4)
748 tmp = TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G;
750 tmp = TX_FIFO_SECTIONS_TX_AVAIL_10G;
751 tmp |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G;
753 tmp = TX_FIFO_SECTIONS_TX_AVAIL_1G |
754 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G;
756 iowrite32be(tmp, ®s->tx_fifo_sections);
758 mac_dev->update_speed(mac_dev, speed);
760 tmp = ioread32be(®s->command_config);
761 tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
762 iowrite32be(tmp, ®s->command_config);
765 static void memac_link_down(struct phylink_config *config, unsigned int mode,
766 phy_interface_t interface)
768 struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
769 struct memac_regs __iomem *regs = memac->regs;
773 tmp = ioread32be(®s->command_config);
774 tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
775 iowrite32be(tmp, ®s->command_config);
778 static const struct phylink_mac_ops memac_mac_ops = {
779 .validate = memac_validate,
780 .mac_select_pcs = memac_select_pcs,
781 .mac_prepare = memac_prepare,
782 .mac_config = memac_mac_config,
783 .mac_link_up = memac_link_up,
784 .mac_link_down = memac_link_down,
787 static int memac_modify_mac_address(struct fman_mac *memac,
788 const enet_addr_t *enet_addr)
790 add_addr_in_paddr(memac->regs, (const u8 *)(*enet_addr), 0);
795 static int memac_add_hash_mac_address(struct fman_mac *memac,
796 enet_addr_t *eth_addr)
798 struct memac_regs __iomem *regs = memac->regs;
799 struct eth_hash_entry *hash_entry;
803 addr = ENET_ADDR_TO_UINT64(*eth_addr);
805 if (!(addr & GROUP_ADDRESS)) {
806 /* Unicast addresses not supported in hash */
807 pr_err("Unicast Address\n");
810 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK;
812 /* Create element to be added to the driver hash table */
813 hash_entry = kmalloc(sizeof(*hash_entry), GFP_ATOMIC);
816 hash_entry->addr = addr;
817 INIT_LIST_HEAD(&hash_entry->node);
819 list_add_tail(&hash_entry->node,
820 &memac->multicast_addr_hash->lsts[hash]);
821 iowrite32be(hash | HASH_CTRL_MCAST_EN, ®s->hashtable_ctrl);
826 static int memac_set_allmulti(struct fman_mac *memac, bool enable)
829 struct memac_regs __iomem *regs = memac->regs;
832 for (entry = 0; entry < HASH_TABLE_SIZE; entry++)
833 iowrite32be(entry | HASH_CTRL_MCAST_EN,
834 ®s->hashtable_ctrl);
836 for (entry = 0; entry < HASH_TABLE_SIZE; entry++)
837 iowrite32be(entry & ~HASH_CTRL_MCAST_EN,
838 ®s->hashtable_ctrl);
841 memac->allmulti_enabled = enable;
846 static int memac_set_tstamp(struct fman_mac *memac, bool enable)
848 return 0; /* Always enabled. */
851 static int memac_del_hash_mac_address(struct fman_mac *memac,
852 enet_addr_t *eth_addr)
854 struct memac_regs __iomem *regs = memac->regs;
855 struct eth_hash_entry *hash_entry = NULL;
856 struct list_head *pos;
860 addr = ENET_ADDR_TO_UINT64(*eth_addr);
862 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK;
864 list_for_each(pos, &memac->multicast_addr_hash->lsts[hash]) {
865 hash_entry = ETH_HASH_ENTRY_OBJ(pos);
866 if (hash_entry && hash_entry->addr == addr) {
867 list_del_init(&hash_entry->node);
873 if (!memac->allmulti_enabled) {
874 if (list_empty(&memac->multicast_addr_hash->lsts[hash]))
875 iowrite32be(hash & ~HASH_CTRL_MCAST_EN,
876 ®s->hashtable_ctrl);
882 static int memac_set_exception(struct fman_mac *memac,
883 enum fman_mac_exceptions exception, bool enable)
887 bit_mask = get_exception_flag(exception);
890 memac->exceptions |= bit_mask;
892 memac->exceptions &= ~bit_mask;
894 pr_err("Undefined exception\n");
897 set_exception(memac->regs, bit_mask, enable);
902 static int memac_init(struct fman_mac *memac)
904 struct memac_cfg *memac_drv_param;
905 enet_addr_t eth_addr;
909 err = check_init_parameters(memac);
913 memac_drv_param = memac->memac_drv_param;
915 /* First, reset the MAC if desired. */
916 if (memac_drv_param->reset_on_init) {
917 err = reset(memac->regs);
919 pr_err("mEMAC reset failed\n");
925 if (memac->addr != 0) {
926 MAKE_ENET_ADDR_FROM_UINT64(memac->addr, eth_addr);
927 add_addr_in_paddr(memac->regs, (const u8 *)eth_addr, 0);
930 init(memac->regs, memac->memac_drv_param, memac->exceptions);
932 /* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 errata workaround
933 * Exists only in FMan 6.0 and 6.3.
935 if ((memac->fm_rev_info.major == 6) &&
936 ((memac->fm_rev_info.minor == 0) ||
937 (memac->fm_rev_info.minor == 3))) {
938 /* MAC strips CRC from received frames - this workaround
939 * should decrease the likelihood of bug appearance
941 reg32 = ioread32be(&memac->regs->command_config);
942 reg32 &= ~CMD_CFG_CRC_FWD;
943 iowrite32be(reg32, &memac->regs->command_config);
946 /* Max Frame Length */
947 err = fman_set_mac_max_frame(memac->fm, memac->mac_id,
948 memac_drv_param->max_frame_length);
950 pr_err("settings Mac max frame length is FAILED\n");
954 memac->multicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE);
955 if (!memac->multicast_addr_hash) {
956 free_init_resources(memac);
957 pr_err("allocation hash table is FAILED\n");
961 memac->unicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE);
962 if (!memac->unicast_addr_hash) {
963 free_init_resources(memac);
964 pr_err("allocation hash table is FAILED\n");
968 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
969 FMAN_INTR_TYPE_ERR, memac_err_exception, memac);
971 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
972 FMAN_INTR_TYPE_NORMAL, memac_exception, memac);
977 static void pcs_put(struct phylink_pcs *pcs)
979 struct mdio_device *mdiodev;
981 if (IS_ERR_OR_NULL(pcs))
984 mdiodev = lynx_get_mdio_device(pcs);
985 lynx_pcs_destroy(pcs);
986 mdio_device_free(mdiodev);
989 static int memac_free(struct fman_mac *memac)
991 free_init_resources(memac);
993 pcs_put(memac->sgmii_pcs);
994 pcs_put(memac->qsgmii_pcs);
995 pcs_put(memac->xfi_pcs);
996 kfree(memac->memac_drv_param);
1002 static struct fman_mac *memac_config(struct mac_device *mac_dev,
1003 struct fman_mac_params *params)
1005 struct fman_mac *memac;
1006 struct memac_cfg *memac_drv_param;
1008 /* allocate memory for the m_emac data structure */
1009 memac = kzalloc(sizeof(*memac), GFP_KERNEL);
1013 /* allocate memory for the m_emac driver parameters data structure */
1014 memac_drv_param = kzalloc(sizeof(*memac_drv_param), GFP_KERNEL);
1015 if (!memac_drv_param) {
1020 /* Plant parameter structure pointer */
1021 memac->memac_drv_param = memac_drv_param;
1023 set_dflts(memac_drv_param);
1025 memac->addr = ENET_ADDR_TO_UINT64(mac_dev->addr);
1027 memac->regs = mac_dev->vaddr;
1028 memac->mac_id = params->mac_id;
1029 memac->exceptions = (MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER |
1030 MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI);
1031 memac->exception_cb = params->exception_cb;
1032 memac->event_cb = params->event_cb;
1033 memac->dev_id = mac_dev;
1034 memac->fm = params->fm;
1036 /* Save FMan revision */
1037 fman_get_revision(memac->fm, &memac->fm_rev_info);
1042 static struct phylink_pcs *memac_pcs_create(struct device_node *mac_node,
1045 struct device_node *node;
1046 struct mdio_device *mdiodev = NULL;
1047 struct phylink_pcs *pcs;
1049 node = of_parse_phandle(mac_node, "pcsphy-handle", index);
1050 if (node && of_device_is_available(node))
1051 mdiodev = of_mdio_find_device(node);
1055 return ERR_PTR(-EPROBE_DEFER);
1057 pcs = lynx_pcs_create(mdiodev);
1059 mdio_device_free(mdiodev);
1064 static bool memac_supports(struct mac_device *mac_dev, phy_interface_t iface)
1066 /* If there's no serdes device, assume that it's been configured for
1067 * whatever the default interface mode is.
1069 if (!mac_dev->fman_mac->serdes)
1070 return mac_dev->phy_if == iface;
1071 /* Otherwise, ask the serdes */
1072 return !phy_validate(mac_dev->fman_mac->serdes, PHY_MODE_ETHERNET,
1076 int memac_initialization(struct mac_device *mac_dev,
1077 struct device_node *mac_node,
1078 struct fman_mac_params *params)
1081 struct device_node *fixed;
1082 struct phylink_pcs *pcs;
1083 struct fman_mac *memac;
1084 unsigned long capabilities;
1085 unsigned long *supported;
1087 mac_dev->phylink_ops = &memac_mac_ops;
1088 mac_dev->set_promisc = memac_set_promiscuous;
1089 mac_dev->change_addr = memac_modify_mac_address;
1090 mac_dev->add_hash_mac_addr = memac_add_hash_mac_address;
1091 mac_dev->remove_hash_mac_addr = memac_del_hash_mac_address;
1092 mac_dev->set_exception = memac_set_exception;
1093 mac_dev->set_allmulti = memac_set_allmulti;
1094 mac_dev->set_tstamp = memac_set_tstamp;
1095 mac_dev->set_multi = fman_set_multi;
1096 mac_dev->enable = memac_enable;
1097 mac_dev->disable = memac_disable;
1099 mac_dev->fman_mac = memac_config(mac_dev, params);
1100 if (!mac_dev->fman_mac)
1103 memac = mac_dev->fman_mac;
1104 memac->memac_drv_param->max_frame_length = fman_get_max_frm();
1105 memac->memac_drv_param->reset_on_init = true;
1107 err = of_property_match_string(mac_node, "pcs-handle-names", "xfi");
1109 memac->xfi_pcs = memac_pcs_create(mac_node, err);
1110 if (IS_ERR(memac->xfi_pcs)) {
1111 err = PTR_ERR(memac->xfi_pcs);
1112 dev_err_probe(mac_dev->dev, err, "missing xfi pcs\n");
1113 goto _return_fm_mac_free;
1115 } else if (err != -EINVAL && err != -ENODATA) {
1116 goto _return_fm_mac_free;
1119 err = of_property_match_string(mac_node, "pcs-handle-names", "qsgmii");
1121 memac->qsgmii_pcs = memac_pcs_create(mac_node, err);
1122 if (IS_ERR(memac->qsgmii_pcs)) {
1123 err = PTR_ERR(memac->qsgmii_pcs);
1124 dev_err_probe(mac_dev->dev, err,
1125 "missing qsgmii pcs\n");
1126 goto _return_fm_mac_free;
1128 } else if (err != -EINVAL && err != -ENODATA) {
1129 goto _return_fm_mac_free;
1132 /* For compatibility, if pcs-handle-names is missing, we assume this
1133 * phy is the first one in pcsphy-handle
1135 err = of_property_match_string(mac_node, "pcs-handle-names", "sgmii");
1136 if (err == -EINVAL || err == -ENODATA)
1137 pcs = memac_pcs_create(mac_node, 0);
1139 goto _return_fm_mac_free;
1141 pcs = memac_pcs_create(mac_node, err);
1145 dev_err_probe(mac_dev->dev, err, "missing pcs\n");
1146 goto _return_fm_mac_free;
1149 /* If err is set here, it means that pcs-handle-names was missing above
1150 * (and therefore that xfi_pcs cannot be set). If we are defaulting to
1151 * XGMII, assume this is for XFI. Otherwise, assume it is for SGMII.
1153 if (err && mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
1154 memac->xfi_pcs = pcs;
1156 memac->sgmii_pcs = pcs;
1158 memac->serdes = devm_of_phy_optional_get(mac_dev->dev, mac_node,
1160 if (!memac->serdes) {
1161 dev_dbg(mac_dev->dev, "could not get (optional) serdes\n");
1162 } else if (IS_ERR(memac->serdes)) {
1163 err = PTR_ERR(memac->serdes);
1164 goto _return_fm_mac_free;
1167 /* The internal connection to the serdes is XGMII, but this isn't
1168 * really correct for the phy mode (which is the external connection).
1169 * However, this is how all older device trees say that they want
1170 * 10GBASE-R (aka XFI), so just convert it for them.
1172 if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
1173 mac_dev->phy_if = PHY_INTERFACE_MODE_10GBASER;
1175 /* TODO: The following interface modes are supported by (some) hardware
1176 * but not by this driver:
1181 supported = mac_dev->phylink_config.supported_interfaces;
1183 /* Note that half duplex is only supported on 10/100M interfaces. */
1185 if (memac->sgmii_pcs &&
1186 (memac_supports(mac_dev, PHY_INTERFACE_MODE_SGMII) ||
1187 memac_supports(mac_dev, PHY_INTERFACE_MODE_1000BASEX))) {
1188 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
1189 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
1192 if (memac->sgmii_pcs &&
1193 memac_supports(mac_dev, PHY_INTERFACE_MODE_2500BASEX))
1194 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
1196 if (memac->qsgmii_pcs &&
1197 memac_supports(mac_dev, PHY_INTERFACE_MODE_QSGMII))
1198 __set_bit(PHY_INTERFACE_MODE_QSGMII, supported);
1199 else if (mac_dev->phy_if == PHY_INTERFACE_MODE_QSGMII)
1200 dev_warn(mac_dev->dev, "no QSGMII pcs specified\n");
1202 if (memac->xfi_pcs &&
1203 memac_supports(mac_dev, PHY_INTERFACE_MODE_10GBASER)) {
1204 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
1206 /* From what I can tell, no 10g macs support RGMII. */
1207 phy_interface_set_rgmii(supported);
1208 __set_bit(PHY_INTERFACE_MODE_MII, supported);
1211 capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | MAC_10 | MAC_100;
1212 capabilities |= MAC_1000FD | MAC_2500FD | MAC_10000FD;
1214 /* These SoCs don't support half duplex at all; there's no different
1215 * FMan version or compatible, so we just have to check the machine
1216 * compatible instead
1218 if (of_machine_is_compatible("fsl,ls1043a") ||
1219 of_machine_is_compatible("fsl,ls1046a") ||
1220 of_machine_is_compatible("fsl,B4QDS"))
1221 capabilities &= ~(MAC_10HD | MAC_100HD);
1223 mac_dev->phylink_config.mac_capabilities = capabilities;
1225 /* The T2080 and T4240 don't support half duplex RGMII. There is no
1226 * other way to identify these SoCs, so just use the machine
1229 if (of_machine_is_compatible("fsl,T2080QDS") ||
1230 of_machine_is_compatible("fsl,T2080RDB") ||
1231 of_machine_is_compatible("fsl,T2081QDS") ||
1232 of_machine_is_compatible("fsl,T4240QDS") ||
1233 of_machine_is_compatible("fsl,T4240RDB"))
1234 memac->rgmii_no_half_duplex = true;
1236 /* Most boards should use MLO_AN_INBAND, but existing boards don't have
1237 * a managed property. Default to MLO_AN_INBAND if nothing else is
1238 * specified. We need to be careful and not enable this if we have a
1239 * fixed link or if we are using MII or RGMII, since those
1240 * configurations modes don't use in-band autonegotiation.
1242 fixed = of_get_child_by_name(mac_node, "fixed-link");
1243 if (!fixed && !of_property_read_bool(mac_node, "fixed-link") &&
1244 !of_property_read_bool(mac_node, "managed") &&
1245 mac_dev->phy_if != PHY_INTERFACE_MODE_MII &&
1246 !phy_interface_mode_is_rgmii(mac_dev->phy_if))
1247 mac_dev->phylink_config.ovr_an_inband = true;
1250 err = memac_init(mac_dev->fman_mac);
1252 goto _return_fm_mac_free;
1254 dev_info(mac_dev->dev, "FMan MEMAC\n");
1258 _return_fm_mac_free:
1259 memac_free(mac_dev->fman_mac);