2 * Copyright 2008-2015 Freescale Semiconductor Inc.
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33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
35 #include "fman_memac.h"
38 #include <linux/slab.h>
40 #include <linux/phy.h>
41 #include <linux/phy_fixed.h>
42 #include <linux/of_mdio.h>
45 #define MDIO_SGMII_CR 0x00
46 #define MDIO_SGMII_DEV_ABIL_SGMII 0x04
47 #define MDIO_SGMII_LINK_TMR_L 0x12
48 #define MDIO_SGMII_LINK_TMR_H 0x13
49 #define MDIO_SGMII_IF_MODE 0x14
51 /* SGMII Control defines */
52 #define SGMII_CR_AN_EN 0x1000
53 #define SGMII_CR_RESTART_AN 0x0200
54 #define SGMII_CR_FD 0x0100
55 #define SGMII_CR_SPEED_SEL1_1G 0x0040
56 #define SGMII_CR_DEF_VAL (SGMII_CR_AN_EN | SGMII_CR_FD | \
57 SGMII_CR_SPEED_SEL1_1G)
59 /* SGMII Device Ability for SGMII defines */
60 #define MDIO_SGMII_DEV_ABIL_SGMII_MODE 0x4001
61 #define MDIO_SGMII_DEV_ABIL_BASEX_MODE 0x01A0
63 /* Link timer define */
64 #define LINK_TMR_L 0xa120
65 #define LINK_TMR_H 0x0007
66 #define LINK_TMR_L_BASEX 0xaf08
67 #define LINK_TMR_H_BASEX 0x002f
69 /* SGMII IF Mode defines */
70 #define IF_MODE_USE_SGMII_AN 0x0002
71 #define IF_MODE_SGMII_EN 0x0001
72 #define IF_MODE_SGMII_SPEED_100M 0x0004
73 #define IF_MODE_SGMII_SPEED_1G 0x0008
74 #define IF_MODE_SGMII_DUPLEX_HALF 0x0010
76 /* Num of additional exact match MAC adr regs */
77 #define MEMAC_NUM_OF_PADDRS 7
79 /* Control and Configuration Register (COMMAND_CONFIG) */
80 #define CMD_CFG_REG_LOWP_RXETY 0x01000000 /* 07 Rx low power indication */
81 #define CMD_CFG_TX_LOWP_ENA 0x00800000 /* 08 Tx Low Power Idle Enable */
82 #define CMD_CFG_PFC_MODE 0x00080000 /* 12 Enable PFC */
83 #define CMD_CFG_NO_LEN_CHK 0x00020000 /* 14 Payload length check disable */
84 #define CMD_CFG_SW_RESET 0x00001000 /* 19 S/W Reset, self clearing bit */
85 #define CMD_CFG_TX_PAD_EN 0x00000800 /* 20 Enable Tx padding of frames */
86 #define CMD_CFG_PAUSE_IGNORE 0x00000100 /* 23 Ignore Pause frame quanta */
87 #define CMD_CFG_CRC_FWD 0x00000040 /* 25 Terminate/frwd CRC of frames */
88 #define CMD_CFG_PAD_EN 0x00000020 /* 26 Frame padding removal */
89 #define CMD_CFG_PROMIS_EN 0x00000010 /* 27 Promiscuous operation enable */
90 #define CMD_CFG_RX_EN 0x00000002 /* 30 MAC receive path enable */
91 #define CMD_CFG_TX_EN 0x00000001 /* 31 MAC transmit path enable */
93 /* Transmit FIFO Sections Register (TX_FIFO_SECTIONS) */
94 #define TX_FIFO_SECTIONS_TX_EMPTY_MASK 0xFFFF0000
95 #define TX_FIFO_SECTIONS_TX_AVAIL_MASK 0x0000FFFF
96 #define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G 0x00400000
97 #define TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G 0x00100000
98 #define TX_FIFO_SECTIONS_TX_AVAIL_10G 0x00000019
99 #define TX_FIFO_SECTIONS_TX_AVAIL_1G 0x00000020
100 #define TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G 0x00000060
102 #define GET_TX_EMPTY_DEFAULT_VALUE(_val) \
104 _val &= ~TX_FIFO_SECTIONS_TX_EMPTY_MASK; \
105 ((_val == TX_FIFO_SECTIONS_TX_AVAIL_10G) ? \
106 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G) :\
107 (_val |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G));\
110 /* Interface Mode Register (IF_MODE) */
112 #define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */
113 #define IF_MODE_10G 0x00000000 /* 30-31 10G interface */
114 #define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */
115 #define IF_MODE_RGMII 0x00000004
116 #define IF_MODE_RGMII_AUTO 0x00008000
117 #define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */
118 #define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */
119 #define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */
120 #define IF_MODE_RGMII_SP_MASK 0x00006000 /* Setsp mask bits */
121 #define IF_MODE_RGMII_FD 0x00001000 /* Full duplex RGMII */
122 #define IF_MODE_HD 0x00000040 /* Half duplex operation */
124 /* Hash table Control Register (HASHTABLE_CTRL) */
125 #define HASH_CTRL_MCAST_EN 0x00000100
126 /* 26-31 Hash table address code */
127 #define HASH_CTRL_ADDR_MASK 0x0000003F
128 /* MAC mcast indication */
129 #define GROUP_ADDRESS 0x0000010000000000LL
130 #define HASH_TABLE_SIZE 64 /* Hash tbl size */
132 /* Interrupt Mask Register (IMASK) */
133 #define MEMAC_IMASK_MGI 0x40000000 /* 1 Magic pkt detect indication */
134 #define MEMAC_IMASK_TSECC_ER 0x20000000 /* 2 Timestamp FIFO ECC error evnt */
135 #define MEMAC_IMASK_TECC_ER 0x02000000 /* 6 Transmit frame ECC error evnt */
136 #define MEMAC_IMASK_RECC_ER 0x01000000 /* 7 Receive frame ECC error evnt */
138 #define MEMAC_ALL_ERRS_IMASK \
139 ((u32)(MEMAC_IMASK_TSECC_ER | \
140 MEMAC_IMASK_TECC_ER | \
141 MEMAC_IMASK_RECC_ER | \
144 #define MEMAC_IEVNT_PCS 0x80000000 /* PCS (XG). Link sync (G) */
145 #define MEMAC_IEVNT_AN 0x40000000 /* Auto-negotiation */
146 #define MEMAC_IEVNT_LT 0x20000000 /* Link Training/New page */
147 #define MEMAC_IEVNT_MGI 0x00004000 /* Magic pkt detection */
148 #define MEMAC_IEVNT_TS_ECC_ER 0x00002000 /* Timestamp FIFO ECC error*/
149 #define MEMAC_IEVNT_RX_FIFO_OVFL 0x00001000 /* Rx FIFO overflow */
150 #define MEMAC_IEVNT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */
151 #define MEMAC_IEVNT_TX_FIFO_OVFL 0x00000400 /* Tx FIFO overflow */
152 #define MEMAC_IEVNT_TX_ECC_ER 0x00000200 /* Tx frame ECC error */
153 #define MEMAC_IEVNT_RX_ECC_ER 0x00000100 /* Rx frame ECC error */
154 #define MEMAC_IEVNT_LI_FAULT 0x00000080 /* Link Interruption flt */
155 #define MEMAC_IEVNT_RX_EMPTY 0x00000040 /* Rx FIFO empty */
156 #define MEMAC_IEVNT_TX_EMPTY 0x00000020 /* Tx FIFO empty */
157 #define MEMAC_IEVNT_RX_LOWP 0x00000010 /* Low Power Idle */
158 #define MEMAC_IEVNT_PHY_LOS 0x00000004 /* Phy loss of signal */
159 #define MEMAC_IEVNT_REM_FAULT 0x00000002 /* Remote fault (XGMII) */
160 #define MEMAC_IEVNT_LOC_FAULT 0x00000001 /* Local fault (XGMII) */
162 #define DEFAULT_PAUSE_QUANTA 0xf000
163 #define DEFAULT_FRAME_LENGTH 0x600
164 #define DEFAULT_TX_IPG_LENGTH 12
166 #define CLXY_PAUSE_QUANTA_CLX_PQNT 0x0000FFFF
167 #define CLXY_PAUSE_QUANTA_CLY_PQNT 0xFFFF0000
168 #define CLXY_PAUSE_THRESH_CLX_QTH 0x0000FFFF
169 #define CLXY_PAUSE_THRESH_CLY_QTH 0xFFFF0000
172 /* Lower 32 bits of 48-bit MAC address */
174 /* Upper 16 bits of 48-bit MAC address */
180 u32 res0000[2]; /* General Control and Status */
181 u32 command_config; /* 0x008 Ctrl and cfg */
182 struct mac_addr mac_addr0; /* 0x00C-0x010 MAC_ADDR_0...1 */
183 u32 maxfrm; /* 0x014 Max frame length */
185 u32 rx_fifo_sections; /* Receive FIFO configuration reg */
186 u32 tx_fifo_sections; /* Transmit FIFO configuration reg */
188 u32 hashtable_ctrl; /* 0x02C Hash table control */
190 u32 ievent; /* 0x040 Interrupt event */
191 u32 tx_ipg_length; /* 0x044 Transmitter inter-packet-gap */
193 u32 imask; /* 0x04C Interrupt mask */
195 u32 pause_quanta[4]; /* 0x054 Pause quanta */
196 u32 pause_thresh[4]; /* 0x064 Pause quanta threshold */
197 u32 rx_pause_status; /* 0x074 Receive pause status */
199 struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS];/* 0x80-0x0B4 mac padr */
200 u32 lpwake_timer; /* 0x0B8 Low Power Wakeup Timer */
201 u32 sleep_timer; /* 0x0BC Transmit EEE Low Power Timer */
203 u32 statn_config; /* 0x0E0 Statistics configuration */
205 /* Rx Statistics Counter */
259 /* Tx Statistics Counter */
304 /* Line Interface Control */
305 u32 if_mode; /* 0x300 Interface Mode Control */
306 u32 if_status; /* 0x304 Interface Status */
309 u32 hg_config; /* 0x340 Control and cfg */
311 u32 hg_pause_quanta; /* 0x350 Pause quanta */
313 u32 hg_pause_thresh; /* 0x360 Pause quanta threshold */
315 u32 hgrx_pause_status; /* 0x370 Receive pause status */
316 u32 hg_fifos_status; /* 0x374 fifos status */
317 u32 rhm; /* 0x378 rx messages counter */
318 u32 thm; /* 0x37C tx messages counter */
324 bool promiscuous_mode_enable;
325 struct fixed_phy_status *fixed_link;
326 u16 max_frame_length;
332 /* Pointer to MAC memory mapped registers */
333 struct memac_regs __iomem *regs;
334 /* MAC address of device */
336 /* Ethernet physical interface */
337 phy_interface_t phy_if;
339 void *dev_id; /* device cookie used by the exception cbs */
340 fman_mac_exception_cb *exception_cb;
341 fman_mac_exception_cb *event_cb;
342 /* Pointer to driver's global address hash table */
343 struct eth_hash_t *multicast_addr_hash;
344 /* Pointer to driver's individual address hash table */
345 struct eth_hash_t *unicast_addr_hash;
348 struct memac_cfg *memac_drv_param;
350 struct fman_rev_info fm_rev_info;
352 struct phy_device *pcsphy;
353 bool allmulti_enabled;
356 static void add_addr_in_paddr(struct memac_regs __iomem *regs, u8 *adr,
361 tmp0 = (u32)(adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24);
362 tmp1 = (u32)(adr[4] | adr[5] << 8);
364 if (paddr_num == 0) {
365 iowrite32be(tmp0, ®s->mac_addr0.mac_addr_l);
366 iowrite32be(tmp1, ®s->mac_addr0.mac_addr_u);
368 iowrite32be(tmp0, ®s->mac_addr[paddr_num - 1].mac_addr_l);
369 iowrite32be(tmp1, ®s->mac_addr[paddr_num - 1].mac_addr_u);
373 static int reset(struct memac_regs __iomem *regs)
378 tmp = ioread32be(®s->command_config);
380 tmp |= CMD_CFG_SW_RESET;
382 iowrite32be(tmp, ®s->command_config);
387 } while ((ioread32be(®s->command_config) & CMD_CFG_SW_RESET) &&
396 static void set_exception(struct memac_regs __iomem *regs, u32 val,
401 tmp = ioread32be(®s->imask);
407 iowrite32be(tmp, ®s->imask);
410 static int init(struct memac_regs __iomem *regs, struct memac_cfg *cfg,
411 phy_interface_t phy_if, u16 speed, bool slow_10g_if,
418 if (cfg->promiscuous_mode_enable)
419 tmp |= CMD_CFG_PROMIS_EN;
420 if (cfg->pause_ignore)
421 tmp |= CMD_CFG_PAUSE_IGNORE;
423 /* Payload length check disable */
424 tmp |= CMD_CFG_NO_LEN_CHK;
425 /* Enable padding of frames in transmit direction */
426 tmp |= CMD_CFG_TX_PAD_EN;
428 tmp |= CMD_CFG_CRC_FWD;
430 iowrite32be(tmp, ®s->command_config);
432 /* Max Frame Length */
433 iowrite32be((u32)cfg->max_frame_length, ®s->maxfrm);
436 iowrite32be((u32)cfg->pause_quanta, ®s->pause_quanta[0]);
437 iowrite32be((u32)0, ®s->pause_thresh[0]);
442 case PHY_INTERFACE_MODE_XGMII:
447 if (phy_if == PHY_INTERFACE_MODE_RGMII ||
448 phy_if == PHY_INTERFACE_MODE_RGMII_ID ||
449 phy_if == PHY_INTERFACE_MODE_RGMII_RXID ||
450 phy_if == PHY_INTERFACE_MODE_RGMII_TXID)
451 tmp |= IF_MODE_RGMII | IF_MODE_RGMII_AUTO;
453 iowrite32be(tmp, ®s->if_mode);
455 /* TX_FIFO_SECTIONS */
457 if (phy_if == PHY_INTERFACE_MODE_XGMII) {
459 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G |
460 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
462 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_10G |
463 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
466 tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_1G |
467 TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G);
469 iowrite32be(tmp, ®s->tx_fifo_sections);
471 /* clear all pending events and set-up interrupts */
472 iowrite32be(0xffffffff, ®s->ievent);
473 set_exception(regs, exceptions, true);
478 static void set_dflts(struct memac_cfg *cfg)
480 cfg->reset_on_init = false;
481 cfg->promiscuous_mode_enable = false;
482 cfg->pause_ignore = false;
483 cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH;
484 cfg->max_frame_length = DEFAULT_FRAME_LENGTH;
485 cfg->pause_quanta = DEFAULT_PAUSE_QUANTA;
488 static u32 get_mac_addr_hash_code(u64 eth_addr)
494 for (i = 0; i < 6; i++) {
495 mask1 = eth_addr & (u64)0x01;
498 for (j = 0; j < 7; j++) {
499 mask2 = eth_addr & (u64)0x01;
504 xor_val |= (mask1 << (5 - i));
510 static void setup_sgmii_internal_phy(struct fman_mac *memac,
511 struct fixed_phy_status *fixed_link)
515 if (WARN_ON(!memac->pcsphy))
519 tmp_reg16 = IF_MODE_SGMII_EN;
522 tmp_reg16 |= IF_MODE_USE_SGMII_AN;
524 switch (fixed_link->speed) {
526 /* For 10M: IF_MODE[SPEED_10M] = 0 */
529 tmp_reg16 |= IF_MODE_SGMII_SPEED_100M;
531 case 1000: /* fallthrough */
533 tmp_reg16 |= IF_MODE_SGMII_SPEED_1G;
536 if (!fixed_link->duplex)
537 tmp_reg16 |= IF_MODE_SGMII_DUPLEX_HALF;
539 phy_write(memac->pcsphy, MDIO_SGMII_IF_MODE, tmp_reg16);
541 /* Device ability according to SGMII specification */
542 tmp_reg16 = MDIO_SGMII_DEV_ABIL_SGMII_MODE;
543 phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16);
545 /* Adjust link timer for SGMII -
546 * According to Cisco SGMII specification the timer should be 1.6 ms.
547 * The link_timer register is configured in units of the clock.
548 * - When running as 1G SGMII, Serdes clock is 125 MHz, so
549 * unit = 1 / (125*10^6 Hz) = 8 ns.
550 * 1.6 ms in units of 8 ns = 1.6ms / 8ns = 2*10^5 = 0x30d40
551 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so
552 * unit = 1 / (312.5*10^6 Hz) = 3.2 ns.
553 * 1.6 ms in units of 3.2 ns = 1.6ms / 3.2ns = 5*10^5 = 0x7a120.
554 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII,
555 * we always set up here a value of 2.5 SGMII.
557 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H);
558 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L);
562 tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN;
565 tmp_reg16 = SGMII_CR_DEF_VAL & ~SGMII_CR_AN_EN;
566 phy_write(memac->pcsphy, 0x0, tmp_reg16);
569 static void setup_sgmii_internal_phy_base_x(struct fman_mac *memac)
573 /* AN Device capability */
574 tmp_reg16 = MDIO_SGMII_DEV_ABIL_BASEX_MODE;
575 phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16);
577 /* Adjust link timer for SGMII -
578 * For Serdes 1000BaseX auto-negotiation the timer should be 10 ms.
579 * The link_timer register is configured in units of the clock.
580 * - When running as 1G SGMII, Serdes clock is 125 MHz, so
581 * unit = 1 / (125*10^6 Hz) = 8 ns.
582 * 10 ms in units of 8 ns = 10ms / 8ns = 1250000 = 0x1312d0
583 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so
584 * unit = 1 / (312.5*10^6 Hz) = 3.2 ns.
585 * 10 ms in units of 3.2 ns = 10ms / 3.2ns = 3125000 = 0x2faf08.
586 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII,
587 * we always set up here a value of 2.5 SGMII.
589 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H_BASEX);
590 phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L_BASEX);
593 tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN;
594 phy_write(memac->pcsphy, 0x0, tmp_reg16);
597 static int check_init_parameters(struct fman_mac *memac)
599 if (memac->addr == 0) {
600 pr_err("Ethernet MAC must have a valid MAC address\n");
603 if (!memac->exception_cb) {
604 pr_err("Uninitialized exception handler\n");
607 if (!memac->event_cb) {
608 pr_warn("Uninitialize event handler\n");
615 static int get_exception_flag(enum fman_mac_exceptions exception)
620 case FM_MAC_EX_10G_TX_ECC_ER:
621 bit_mask = MEMAC_IMASK_TECC_ER;
623 case FM_MAC_EX_10G_RX_ECC_ER:
624 bit_mask = MEMAC_IMASK_RECC_ER;
626 case FM_MAC_EX_TS_FIFO_ECC_ERR:
627 bit_mask = MEMAC_IMASK_TSECC_ER;
629 case FM_MAC_EX_MAGIC_PACKET_INDICATION:
630 bit_mask = MEMAC_IMASK_MGI;
640 static void memac_err_exception(void *handle)
642 struct fman_mac *memac = (struct fman_mac *)handle;
643 struct memac_regs __iomem *regs = memac->regs;
646 event = ioread32be(®s->ievent);
647 imask = ioread32be(®s->imask);
649 /* Imask include both error and notification/event bits.
650 * Leaving only error bits enabled by imask.
651 * The imask error bits are shifted by 16 bits offset from
652 * their corresponding location in the ievent - hence the >> 16
654 event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16);
656 iowrite32be(event, ®s->ievent);
658 if (event & MEMAC_IEVNT_TS_ECC_ER)
659 memac->exception_cb(memac->dev_id, FM_MAC_EX_TS_FIFO_ECC_ERR);
660 if (event & MEMAC_IEVNT_TX_ECC_ER)
661 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_TX_ECC_ER);
662 if (event & MEMAC_IEVNT_RX_ECC_ER)
663 memac->exception_cb(memac->dev_id, FM_MAC_EX_10G_RX_ECC_ER);
666 static void memac_exception(void *handle)
668 struct fman_mac *memac = (struct fman_mac *)handle;
669 struct memac_regs __iomem *regs = memac->regs;
672 event = ioread32be(®s->ievent);
673 imask = ioread32be(®s->imask);
675 /* Imask include both error and notification/event bits.
676 * Leaving only error bits enabled by imask.
677 * The imask error bits are shifted by 16 bits offset from
678 * their corresponding location in the ievent - hence the >> 16
680 event &= ((imask & MEMAC_ALL_ERRS_IMASK) >> 16);
682 iowrite32be(event, ®s->ievent);
684 if (event & MEMAC_IEVNT_MGI)
685 memac->exception_cb(memac->dev_id,
686 FM_MAC_EX_MAGIC_PACKET_INDICATION);
689 static void free_init_resources(struct fman_mac *memac)
691 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
694 fman_unregister_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
695 FMAN_INTR_TYPE_NORMAL);
697 /* release the driver's group hash table */
698 free_hash_table(memac->multicast_addr_hash);
699 memac->multicast_addr_hash = NULL;
701 /* release the driver's individual hash table */
702 free_hash_table(memac->unicast_addr_hash);
703 memac->unicast_addr_hash = NULL;
706 static bool is_init_done(struct memac_cfg *memac_drv_params)
708 /* Checks if mEMAC driver parameters were initialized */
709 if (!memac_drv_params)
715 int memac_enable(struct fman_mac *memac, enum comm_mode mode)
717 struct memac_regs __iomem *regs = memac->regs;
720 if (!is_init_done(memac->memac_drv_param))
723 tmp = ioread32be(®s->command_config);
724 if (mode & COMM_MODE_RX)
725 tmp |= CMD_CFG_RX_EN;
726 if (mode & COMM_MODE_TX)
727 tmp |= CMD_CFG_TX_EN;
729 iowrite32be(tmp, ®s->command_config);
734 int memac_disable(struct fman_mac *memac, enum comm_mode mode)
736 struct memac_regs __iomem *regs = memac->regs;
739 if (!is_init_done(memac->memac_drv_param))
742 tmp = ioread32be(®s->command_config);
743 if (mode & COMM_MODE_RX)
744 tmp &= ~CMD_CFG_RX_EN;
745 if (mode & COMM_MODE_TX)
746 tmp &= ~CMD_CFG_TX_EN;
748 iowrite32be(tmp, ®s->command_config);
753 int memac_set_promiscuous(struct fman_mac *memac, bool new_val)
755 struct memac_regs __iomem *regs = memac->regs;
758 if (!is_init_done(memac->memac_drv_param))
761 tmp = ioread32be(®s->command_config);
763 tmp |= CMD_CFG_PROMIS_EN;
765 tmp &= ~CMD_CFG_PROMIS_EN;
767 iowrite32be(tmp, ®s->command_config);
772 int memac_adjust_link(struct fman_mac *memac, u16 speed)
774 struct memac_regs __iomem *regs = memac->regs;
777 if (!is_init_done(memac->memac_drv_param))
780 tmp = ioread32be(®s->if_mode);
782 /* Set full duplex */
785 if (phy_interface_mode_is_rgmii(memac->phy_if)) {
786 /* Configure RGMII in manual mode */
787 tmp &= ~IF_MODE_RGMII_AUTO;
788 tmp &= ~IF_MODE_RGMII_SP_MASK;
790 tmp |= IF_MODE_RGMII_FD;
794 tmp |= IF_MODE_RGMII_1000;
797 tmp |= IF_MODE_RGMII_100;
800 tmp |= IF_MODE_RGMII_10;
807 iowrite32be(tmp, ®s->if_mode);
812 int memac_cfg_max_frame_len(struct fman_mac *memac, u16 new_val)
814 if (is_init_done(memac->memac_drv_param))
817 memac->memac_drv_param->max_frame_length = new_val;
822 int memac_cfg_reset_on_init(struct fman_mac *memac, bool enable)
824 if (is_init_done(memac->memac_drv_param))
827 memac->memac_drv_param->reset_on_init = enable;
832 int memac_cfg_fixed_link(struct fman_mac *memac,
833 struct fixed_phy_status *fixed_link)
835 if (is_init_done(memac->memac_drv_param))
838 memac->memac_drv_param->fixed_link = fixed_link;
843 int memac_set_tx_pause_frames(struct fman_mac *memac, u8 priority,
844 u16 pause_time, u16 thresh_time)
846 struct memac_regs __iomem *regs = memac->regs;
849 if (!is_init_done(memac->memac_drv_param))
852 tmp = ioread32be(®s->tx_fifo_sections);
854 GET_TX_EMPTY_DEFAULT_VALUE(tmp);
855 iowrite32be(tmp, ®s->tx_fifo_sections);
857 tmp = ioread32be(®s->command_config);
858 tmp &= ~CMD_CFG_PFC_MODE;
861 iowrite32be(tmp, ®s->command_config);
863 tmp = ioread32be(®s->pause_quanta[priority / 2]);
865 tmp &= CLXY_PAUSE_QUANTA_CLX_PQNT;
867 tmp &= CLXY_PAUSE_QUANTA_CLY_PQNT;
868 tmp |= ((u32)pause_time << (16 * (priority % 2)));
869 iowrite32be(tmp, ®s->pause_quanta[priority / 2]);
871 tmp = ioread32be(®s->pause_thresh[priority / 2]);
873 tmp &= CLXY_PAUSE_THRESH_CLX_QTH;
875 tmp &= CLXY_PAUSE_THRESH_CLY_QTH;
876 tmp |= ((u32)thresh_time << (16 * (priority % 2)));
877 iowrite32be(tmp, ®s->pause_thresh[priority / 2]);
882 int memac_accept_rx_pause_frames(struct fman_mac *memac, bool en)
884 struct memac_regs __iomem *regs = memac->regs;
887 if (!is_init_done(memac->memac_drv_param))
890 tmp = ioread32be(®s->command_config);
892 tmp &= ~CMD_CFG_PAUSE_IGNORE;
894 tmp |= CMD_CFG_PAUSE_IGNORE;
896 iowrite32be(tmp, ®s->command_config);
901 int memac_modify_mac_address(struct fman_mac *memac, enet_addr_t *enet_addr)
903 if (!is_init_done(memac->memac_drv_param))
906 add_addr_in_paddr(memac->regs, (u8 *)(*enet_addr), 0);
911 int memac_add_hash_mac_address(struct fman_mac *memac, enet_addr_t *eth_addr)
913 struct memac_regs __iomem *regs = memac->regs;
914 struct eth_hash_entry *hash_entry;
918 if (!is_init_done(memac->memac_drv_param))
921 addr = ENET_ADDR_TO_UINT64(*eth_addr);
923 if (!(addr & GROUP_ADDRESS)) {
924 /* Unicast addresses not supported in hash */
925 pr_err("Unicast Address\n");
928 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK;
930 /* Create element to be added to the driver hash table */
931 hash_entry = kmalloc(sizeof(*hash_entry), GFP_ATOMIC);
934 hash_entry->addr = addr;
935 INIT_LIST_HEAD(&hash_entry->node);
937 list_add_tail(&hash_entry->node,
938 &memac->multicast_addr_hash->lsts[hash]);
939 iowrite32be(hash | HASH_CTRL_MCAST_EN, ®s->hashtable_ctrl);
944 int memac_set_allmulti(struct fman_mac *memac, bool enable)
947 struct memac_regs __iomem *regs = memac->regs;
949 if (!is_init_done(memac->memac_drv_param))
953 for (entry = 0; entry < HASH_TABLE_SIZE; entry++)
954 iowrite32be(entry | HASH_CTRL_MCAST_EN,
955 ®s->hashtable_ctrl);
957 for (entry = 0; entry < HASH_TABLE_SIZE; entry++)
958 iowrite32be(entry & ~HASH_CTRL_MCAST_EN,
959 ®s->hashtable_ctrl);
962 memac->allmulti_enabled = enable;
967 int memac_set_tstamp(struct fman_mac *memac, bool enable)
969 return 0; /* Always enabled. */
972 int memac_del_hash_mac_address(struct fman_mac *memac, enet_addr_t *eth_addr)
974 struct memac_regs __iomem *regs = memac->regs;
975 struct eth_hash_entry *hash_entry = NULL;
976 struct list_head *pos;
980 if (!is_init_done(memac->memac_drv_param))
983 addr = ENET_ADDR_TO_UINT64(*eth_addr);
985 hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK;
987 list_for_each(pos, &memac->multicast_addr_hash->lsts[hash]) {
988 hash_entry = ETH_HASH_ENTRY_OBJ(pos);
989 if (hash_entry->addr == addr) {
990 list_del_init(&hash_entry->node);
996 if (!memac->allmulti_enabled) {
997 if (list_empty(&memac->multicast_addr_hash->lsts[hash]))
998 iowrite32be(hash & ~HASH_CTRL_MCAST_EN,
999 ®s->hashtable_ctrl);
1005 int memac_set_exception(struct fman_mac *memac,
1006 enum fman_mac_exceptions exception, bool enable)
1010 if (!is_init_done(memac->memac_drv_param))
1013 bit_mask = get_exception_flag(exception);
1016 memac->exceptions |= bit_mask;
1018 memac->exceptions &= ~bit_mask;
1020 pr_err("Undefined exception\n");
1023 set_exception(memac->regs, bit_mask, enable);
1028 int memac_init(struct fman_mac *memac)
1030 struct memac_cfg *memac_drv_param;
1032 enet_addr_t eth_addr;
1033 bool slow_10g_if = false;
1034 struct fixed_phy_status *fixed_link;
1038 if (is_init_done(memac->memac_drv_param))
1041 err = check_init_parameters(memac);
1045 memac_drv_param = memac->memac_drv_param;
1047 if (memac->fm_rev_info.major == 6 && memac->fm_rev_info.minor == 4)
1050 /* First, reset the MAC if desired. */
1051 if (memac_drv_param->reset_on_init) {
1052 err = reset(memac->regs);
1054 pr_err("mEMAC reset failed\n");
1060 MAKE_ENET_ADDR_FROM_UINT64(memac->addr, eth_addr);
1061 add_addr_in_paddr(memac->regs, (u8 *)eth_addr, 0);
1063 fixed_link = memac_drv_param->fixed_link;
1065 init(memac->regs, memac->memac_drv_param, memac->phy_if,
1066 memac->max_speed, slow_10g_if, memac->exceptions);
1068 /* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 errata workaround
1069 * Exists only in FMan 6.0 and 6.3.
1071 if ((memac->fm_rev_info.major == 6) &&
1072 ((memac->fm_rev_info.minor == 0) ||
1073 (memac->fm_rev_info.minor == 3))) {
1074 /* MAC strips CRC from received frames - this workaround
1075 * should decrease the likelihood of bug appearance
1077 reg32 = ioread32be(&memac->regs->command_config);
1078 reg32 &= ~CMD_CFG_CRC_FWD;
1079 iowrite32be(reg32, &memac->regs->command_config);
1082 if (memac->phy_if == PHY_INTERFACE_MODE_SGMII) {
1083 /* Configure internal SGMII PHY */
1084 if (memac->basex_if)
1085 setup_sgmii_internal_phy_base_x(memac);
1087 setup_sgmii_internal_phy(memac, fixed_link);
1088 } else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII) {
1089 /* Configure 4 internal SGMII PHYs */
1090 for (i = 0; i < 4; i++) {
1091 u8 qsmgii_phy_addr, phy_addr;
1092 /* QSGMII PHY address occupies 3 upper bits of 5-bit
1093 * phy_address; the lower 2 bits are used to extend
1094 * register address space and access each one of 4
1095 * ports inside QSGMII.
1097 phy_addr = memac->pcsphy->mdio.addr;
1098 qsmgii_phy_addr = (u8)((phy_addr << 2) | i);
1099 memac->pcsphy->mdio.addr = qsmgii_phy_addr;
1100 if (memac->basex_if)
1101 setup_sgmii_internal_phy_base_x(memac);
1103 setup_sgmii_internal_phy(memac, fixed_link);
1105 memac->pcsphy->mdio.addr = phy_addr;
1109 /* Max Frame Length */
1110 err = fman_set_mac_max_frame(memac->fm, memac->mac_id,
1111 memac_drv_param->max_frame_length);
1113 pr_err("settings Mac max frame length is FAILED\n");
1117 memac->multicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE);
1118 if (!memac->multicast_addr_hash) {
1119 free_init_resources(memac);
1120 pr_err("allocation hash table is FAILED\n");
1124 memac->unicast_addr_hash = alloc_hash_table(HASH_TABLE_SIZE);
1125 if (!memac->unicast_addr_hash) {
1126 free_init_resources(memac);
1127 pr_err("allocation hash table is FAILED\n");
1131 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
1132 FMAN_INTR_TYPE_ERR, memac_err_exception, memac);
1134 fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
1135 FMAN_INTR_TYPE_NORMAL, memac_exception, memac);
1137 kfree(memac_drv_param);
1138 memac->memac_drv_param = NULL;
1143 int memac_free(struct fman_mac *memac)
1145 free_init_resources(memac);
1148 put_device(&memac->pcsphy->mdio.dev);
1150 kfree(memac->memac_drv_param);
1156 struct fman_mac *memac_config(struct fman_mac_params *params)
1158 struct fman_mac *memac;
1159 struct memac_cfg *memac_drv_param;
1160 void __iomem *base_addr;
1162 base_addr = params->base_addr;
1163 /* allocate memory for the m_emac data structure */
1164 memac = kzalloc(sizeof(*memac), GFP_KERNEL);
1168 /* allocate memory for the m_emac driver parameters data structure */
1169 memac_drv_param = kzalloc(sizeof(*memac_drv_param), GFP_KERNEL);
1170 if (!memac_drv_param) {
1175 /* Plant parameter structure pointer */
1176 memac->memac_drv_param = memac_drv_param;
1178 set_dflts(memac_drv_param);
1180 memac->addr = ENET_ADDR_TO_UINT64(params->addr);
1182 memac->regs = base_addr;
1183 memac->max_speed = params->max_speed;
1184 memac->phy_if = params->phy_if;
1185 memac->mac_id = params->mac_id;
1186 memac->exceptions = (MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER |
1187 MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI);
1188 memac->exception_cb = params->exception_cb;
1189 memac->event_cb = params->event_cb;
1190 memac->dev_id = params->dev_id;
1191 memac->fm = params->fm;
1192 memac->basex_if = params->basex_if;
1194 /* Save FMan revision */
1195 fman_get_revision(memac->fm, &memac->fm_rev_info);
1197 if (memac->phy_if == PHY_INTERFACE_MODE_SGMII ||
1198 memac->phy_if == PHY_INTERFACE_MODE_QSGMII) {
1199 if (!params->internal_phy_node) {
1200 pr_err("PCS PHY node is not available\n");
1205 memac->pcsphy = of_phy_find_device(params->internal_phy_node);
1206 if (!memac->pcsphy) {
1207 pr_err("of_phy_find_device (PCS PHY) failed\n");