drivers/net/ethernet/freescale/fman/fman.c

   1 /*
   2  * Copyright 2008-2015 Freescale Semiconductor Inc.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions are met:
   6  *     * Redistributions of source code must retain the above copyright
   7  *       notice, this list of conditions and the following disclaimer.
   8  *     * Redistributions in binary form must reproduce the above copyright
   9  *       notice, this list of conditions and the following disclaimer in the
  10  *       documentation and/or other materials provided with the distribution.
  11  *     * Neither the name of Freescale Semiconductor nor the
  12  *       names of its contributors may be used to endorse or promote products
  13  *       derived from this software without specific prior written permission.
  14  *
  15  *
  16  * ALTERNATIVELY, this software may be distributed under the terms of the
  17  * GNU General Public License ("GPL") as published by the Free Software
  18  * Foundation, either version 2 of that License or (at your option) any
  19  * later version.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  22  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  23  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  24  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  25  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  27  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  28  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  30  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  34
  35 #include <linux/fsl/guts.h>
  36 #include <linux/slab.h>
  37 #include <linux/delay.h>
  38 #include <linux/module.h>
  39 #include <linux/of_platform.h>
  40 #include <linux/clk.h>
  41 #include <linux/of_address.h>
  42 #include <linux/of_irq.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/libfdt_env.h>
  45
  46 #include "fman.h"
  47 #include "fman_muram.h"
  48 #include "fman_keygen.h"
  49
  50 /* General defines */
  51 #define FMAN_LIODN_TBL                  64      /* size of LIODN table */
  52 #define MAX_NUM_OF_MACS                 10
  53 #define FM_NUM_OF_FMAN_CTRL_EVENT_REGS  4
  54 #define BASE_RX_PORTID                  0x08
  55 #define BASE_TX_PORTID                  0x28
  56
  57 /* Modules registers offsets */
  58 #define BMI_OFFSET              0x00080000
  59 #define QMI_OFFSET              0x00080400
  60 #define KG_OFFSET               0x000C1000
  61 #define DMA_OFFSET              0x000C2000
  62 #define FPM_OFFSET              0x000C3000
  63 #define IMEM_OFFSET             0x000C4000
  64 #define HWP_OFFSET              0x000C7000
  65 #define CGP_OFFSET              0x000DB000
  66
  67 /* Exceptions bit map */
  68 #define EX_DMA_BUS_ERROR                0x80000000
  69 #define EX_DMA_READ_ECC                 0x40000000
  70 #define EX_DMA_SYSTEM_WRITE_ECC 0x20000000
  71 #define EX_DMA_FM_WRITE_ECC             0x10000000
  72 #define EX_FPM_STALL_ON_TASKS           0x08000000
  73 #define EX_FPM_SINGLE_ECC               0x04000000
  74 #define EX_FPM_DOUBLE_ECC               0x02000000
  75 #define EX_QMI_SINGLE_ECC               0x01000000
  76 #define EX_QMI_DEQ_FROM_UNKNOWN_PORTID  0x00800000
  77 #define EX_QMI_DOUBLE_ECC               0x00400000
  78 #define EX_BMI_LIST_RAM_ECC             0x00200000
  79 #define EX_BMI_STORAGE_PROFILE_ECC      0x00100000
  80 #define EX_BMI_STATISTICS_RAM_ECC       0x00080000
  81 #define EX_IRAM_ECC                     0x00040000
  82 #define EX_MURAM_ECC                    0x00020000
  83 #define EX_BMI_DISPATCH_RAM_ECC 0x00010000
  84 #define EX_DMA_SINGLE_PORT_ECC          0x00008000
  85
  86 /* DMA defines */
  87 /* masks */
  88 #define DMA_MODE_BER                    0x00200000
  89 #define DMA_MODE_ECC                    0x00000020
  90 #define DMA_MODE_SECURE_PROT            0x00000800
  91 #define DMA_MODE_AXI_DBG_MASK           0x0F000000
  92
  93 #define DMA_TRANSFER_PORTID_MASK        0xFF000000
  94 #define DMA_TRANSFER_TNUM_MASK          0x00FF0000
  95 #define DMA_TRANSFER_LIODN_MASK 0x00000FFF
  96
  97 #define DMA_STATUS_BUS_ERR              0x08000000
  98 #define DMA_STATUS_READ_ECC             0x04000000
  99 #define DMA_STATUS_SYSTEM_WRITE_ECC     0x02000000
 100 #define DMA_STATUS_FM_WRITE_ECC 0x01000000
 101 #define DMA_STATUS_FM_SPDAT_ECC 0x00080000
 102
 103 #define DMA_MODE_CACHE_OR_SHIFT         30
 104 #define DMA_MODE_AXI_DBG_SHIFT                  24
 105 #define DMA_MODE_CEN_SHIFT                      13
 106 #define DMA_MODE_CEN_MASK                       0x00000007
 107 #define DMA_MODE_DBG_SHIFT                      7
 108 #define DMA_MODE_AID_MODE_SHIFT         4
 109
 110 #define DMA_THRESH_COMMQ_SHIFT                  24
 111 #define DMA_THRESH_READ_INT_BUF_SHIFT           16
 112 #define DMA_THRESH_READ_INT_BUF_MASK            0x0000003f
 113 #define DMA_THRESH_WRITE_INT_BUF_MASK           0x0000003f
 114
 115 #define DMA_TRANSFER_PORTID_SHIFT               24
 116 #define DMA_TRANSFER_TNUM_SHIFT         16
 117
 118 #define DMA_CAM_SIZEOF_ENTRY                    0x40
 119 #define DMA_CAM_UNITS                           8
 120
 121 #define DMA_LIODN_SHIFT         16
 122 #define DMA_LIODN_BASE_MASK     0x00000FFF
 123
 124 /* FPM defines */
 125 #define FPM_EV_MASK_DOUBLE_ECC          0x80000000
 126 #define FPM_EV_MASK_STALL               0x40000000
 127 #define FPM_EV_MASK_SINGLE_ECC          0x20000000
 128 #define FPM_EV_MASK_RELEASE_FM          0x00010000
 129 #define FPM_EV_MASK_DOUBLE_ECC_EN       0x00008000
 130 #define FPM_EV_MASK_STALL_EN            0x00004000
 131 #define FPM_EV_MASK_SINGLE_ECC_EN       0x00002000
 132 #define FPM_EV_MASK_EXTERNAL_HALT       0x00000008
 133 #define FPM_EV_MASK_ECC_ERR_HALT        0x00000004
 134
 135 #define FPM_RAM_MURAM_ECC               0x00008000
 136 #define FPM_RAM_IRAM_ECC                0x00004000
 137 #define FPM_IRAM_ECC_ERR_EX_EN          0x00020000
 138 #define FPM_MURAM_ECC_ERR_EX_EN 0x00040000
 139 #define FPM_RAM_IRAM_ECC_EN             0x40000000
 140 #define FPM_RAM_RAMS_ECC_EN             0x80000000
 141 #define FPM_RAM_RAMS_ECC_EN_SRC_SEL     0x08000000
 142
 143 #define FPM_REV1_MAJOR_MASK             0x0000FF00
 144 #define FPM_REV1_MINOR_MASK             0x000000FF
 145
 146 #define FPM_DISP_LIMIT_SHIFT            24
 147
 148 #define FPM_PRT_FM_CTL1                 0x00000001
 149 #define FPM_PRT_FM_CTL2                 0x00000002
 150 #define FPM_PORT_FM_CTL_PORTID_SHIFT    24
 151 #define FPM_PRC_ORA_FM_CTL_SEL_SHIFT    16
 152
 153 #define FPM_THR1_PRS_SHIFT              24
 154 #define FPM_THR1_KG_SHIFT               16
 155 #define FPM_THR1_PLCR_SHIFT             8
 156 #define FPM_THR1_BMI_SHIFT              0
 157
 158 #define FPM_THR2_QMI_ENQ_SHIFT          24
 159 #define FPM_THR2_QMI_DEQ_SHIFT          0
 160 #define FPM_THR2_FM_CTL1_SHIFT          16
 161 #define FPM_THR2_FM_CTL2_SHIFT          8
 162
 163 #define FPM_EV_MASK_CAT_ERR_SHIFT       1
 164 #define FPM_EV_MASK_DMA_ERR_SHIFT       0
 165
 166 #define FPM_REV1_MAJOR_SHIFT            8
 167
 168 #define FPM_RSTC_FM_RESET               0x80000000
 169 #define FPM_RSTC_MAC0_RESET             0x40000000
 170 #define FPM_RSTC_MAC1_RESET             0x20000000
 171 #define FPM_RSTC_MAC2_RESET             0x10000000
 172 #define FPM_RSTC_MAC3_RESET             0x08000000
 173 #define FPM_RSTC_MAC8_RESET             0x04000000
 174 #define FPM_RSTC_MAC4_RESET             0x02000000
 175 #define FPM_RSTC_MAC5_RESET             0x01000000
 176 #define FPM_RSTC_MAC6_RESET             0x00800000
 177 #define FPM_RSTC_MAC7_RESET             0x00400000
 178 #define FPM_RSTC_MAC9_RESET             0x00200000
 179
 180 #define FPM_TS_INT_SHIFT                16
 181 #define FPM_TS_CTL_EN                   0x80000000
 182
 183 /* BMI defines */
 184 #define BMI_INIT_START                          0x80000000
 185 #define BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC     0x80000000
 186 #define BMI_ERR_INTR_EN_LIST_RAM_ECC            0x40000000
 187 #define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC      0x20000000
 188 #define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC        0x10000000
 189 #define BMI_NUM_OF_TASKS_MASK                   0x3F000000
 190 #define BMI_NUM_OF_EXTRA_TASKS_MASK             0x000F0000
 191 #define BMI_NUM_OF_DMAS_MASK                    0x00000F00
 192 #define BMI_NUM_OF_EXTRA_DMAS_MASK              0x0000000F
 193 #define BMI_FIFO_SIZE_MASK                      0x000003FF
 194 #define BMI_EXTRA_FIFO_SIZE_MASK                0x03FF0000
 195 #define BMI_CFG2_DMAS_MASK                      0x0000003F
 196 #define BMI_CFG2_TASKS_MASK                     0x0000003F
 197
 198 #define BMI_CFG2_TASKS_SHIFT            16
 199 #define BMI_CFG2_DMAS_SHIFT             0
 200 #define BMI_CFG1_FIFO_SIZE_SHIFT        16
 201 #define BMI_NUM_OF_TASKS_SHIFT          24
 202 #define BMI_EXTRA_NUM_OF_TASKS_SHIFT    16
 203 #define BMI_NUM_OF_DMAS_SHIFT           8
 204 #define BMI_EXTRA_NUM_OF_DMAS_SHIFT     0
 205
 206 #define BMI_FIFO_ALIGN                  0x100
 207
 208 #define BMI_EXTRA_FIFO_SIZE_SHIFT       16
 209
 210 /* QMI defines */
 211 #define QMI_CFG_ENQ_EN                  0x80000000
 212 #define QMI_CFG_DEQ_EN                  0x40000000
 213 #define QMI_CFG_EN_COUNTERS             0x10000000
 214 #define QMI_CFG_DEQ_MASK                0x0000003F
 215 #define QMI_CFG_ENQ_MASK                0x00003F00
 216 #define QMI_CFG_ENQ_SHIFT               8
 217
 218 #define QMI_ERR_INTR_EN_DOUBLE_ECC      0x80000000
 219 #define QMI_ERR_INTR_EN_DEQ_FROM_DEF    0x40000000
 220 #define QMI_INTR_EN_SINGLE_ECC          0x80000000
 221
 222 #define QMI_GS_HALT_NOT_BUSY            0x00000002
 223
 224 /* HWP defines */
 225 #define HWP_RPIMAC_PEN                  0x00000001
 226
 227 /* IRAM defines */
 228 #define IRAM_IADD_AIE                   0x80000000
 229 #define IRAM_READY                      0x80000000
 230
 231 /* Default values */
 232 #define DEFAULT_CATASTROPHIC_ERR                0
 233 #define DEFAULT_DMA_ERR                         0
 234 #define DEFAULT_AID_MODE                        FMAN_DMA_AID_OUT_TNUM
 235 #define DEFAULT_DMA_COMM_Q_LOW                  0x2A
 236 #define DEFAULT_DMA_COMM_Q_HIGH         0x3F
 237 #define DEFAULT_CACHE_OVERRIDE                  0
 238 #define DEFAULT_DMA_CAM_NUM_OF_ENTRIES          64
 239 #define DEFAULT_DMA_DBG_CNT_MODE                0
 240 #define DEFAULT_DMA_SOS_EMERGENCY               0
 241 #define DEFAULT_DMA_WATCHDOG                    0
 242 #define DEFAULT_DISP_LIMIT                      0
 243 #define DEFAULT_PRS_DISP_TH                     16
 244 #define DEFAULT_PLCR_DISP_TH                    16
 245 #define DEFAULT_KG_DISP_TH                      16
 246 #define DEFAULT_BMI_DISP_TH                     16
 247 #define DEFAULT_QMI_ENQ_DISP_TH         16
 248 #define DEFAULT_QMI_DEQ_DISP_TH         16
 249 #define DEFAULT_FM_CTL1_DISP_TH         16
 250 #define DEFAULT_FM_CTL2_DISP_TH         16
 251
 252 #define DFLT_AXI_DBG_NUM_OF_BEATS               1
 253
 254 #define DFLT_DMA_READ_INT_BUF_LOW(dma_thresh_max_buf)   \
 255         ((dma_thresh_max_buf + 1) / 2)
 256 #define DFLT_DMA_READ_INT_BUF_HIGH(dma_thresh_max_buf)  \
 257         ((dma_thresh_max_buf + 1) * 3 / 4)
 258 #define DFLT_DMA_WRITE_INT_BUF_LOW(dma_thresh_max_buf)  \
 259         ((dma_thresh_max_buf + 1) / 2)
 260 #define DFLT_DMA_WRITE_INT_BUF_HIGH(dma_thresh_max_buf)\
 261         ((dma_thresh_max_buf + 1) * 3 / 4)
 262
 263 #define DMA_COMM_Q_LOW_FMAN_V3          0x2A
 264 #define DMA_COMM_Q_LOW_FMAN_V2(dma_thresh_max_commq)            \
 265         ((dma_thresh_max_commq + 1) / 2)
 266 #define DFLT_DMA_COMM_Q_LOW(major, dma_thresh_max_commq)        \
 267         ((major == 6) ? DMA_COMM_Q_LOW_FMAN_V3 :                \
 268         DMA_COMM_Q_LOW_FMAN_V2(dma_thresh_max_commq))
 269
 270 #define DMA_COMM_Q_HIGH_FMAN_V3 0x3f
 271 #define DMA_COMM_Q_HIGH_FMAN_V2(dma_thresh_max_commq)           \
 272         ((dma_thresh_max_commq + 1) * 3 / 4)
 273 #define DFLT_DMA_COMM_Q_HIGH(major, dma_thresh_max_commq)       \
 274         ((major == 6) ? DMA_COMM_Q_HIGH_FMAN_V3 :               \
 275         DMA_COMM_Q_HIGH_FMAN_V2(dma_thresh_max_commq))
 276
 277 #define TOTAL_NUM_OF_TASKS_FMAN_V3L     59
 278 #define TOTAL_NUM_OF_TASKS_FMAN_V3H     124
 279 #define DFLT_TOTAL_NUM_OF_TASKS(major, minor, bmi_max_num_of_tasks)     \
 280         ((major == 6) ? ((minor == 1 || minor == 4) ?                   \
 281         TOTAL_NUM_OF_TASKS_FMAN_V3L : TOTAL_NUM_OF_TASKS_FMAN_V3H) :    \
 282         bmi_max_num_of_tasks)
 283
 284 #define DMA_CAM_NUM_OF_ENTRIES_FMAN_V3          64
 285 #define DMA_CAM_NUM_OF_ENTRIES_FMAN_V2          32
 286 #define DFLT_DMA_CAM_NUM_OF_ENTRIES(major)                      \
 287         (major == 6 ? DMA_CAM_NUM_OF_ENTRIES_FMAN_V3 :          \
 288         DMA_CAM_NUM_OF_ENTRIES_FMAN_V2)
 289
 290 #define FM_TIMESTAMP_1_USEC_BIT             8
 291
 292 /* Defines used for enabling/disabling FMan interrupts */
 293 #define ERR_INTR_EN_DMA         0x00010000
 294 #define ERR_INTR_EN_FPM         0x80000000
 295 #define ERR_INTR_EN_BMI         0x00800000
 296 #define ERR_INTR_EN_QMI         0x00400000
 297 #define ERR_INTR_EN_MURAM       0x00040000
 298 #define ERR_INTR_EN_MAC0        0x00004000
 299 #define ERR_INTR_EN_MAC1        0x00002000
 300 #define ERR_INTR_EN_MAC2        0x00001000
 301 #define ERR_INTR_EN_MAC3        0x00000800
 302 #define ERR_INTR_EN_MAC4        0x00000400
 303 #define ERR_INTR_EN_MAC5        0x00000200
 304 #define ERR_INTR_EN_MAC6        0x00000100
 305 #define ERR_INTR_EN_MAC7        0x00000080
 306 #define ERR_INTR_EN_MAC8        0x00008000
 307 #define ERR_INTR_EN_MAC9        0x00000040
 308
 309 #define INTR_EN_QMI             0x40000000
 310 #define INTR_EN_MAC0            0x00080000
 311 #define INTR_EN_MAC1            0x00040000
 312 #define INTR_EN_MAC2            0x00020000
 313 #define INTR_EN_MAC3            0x00010000
 314 #define INTR_EN_MAC4            0x00000040
 315 #define INTR_EN_MAC5            0x00000020
 316 #define INTR_EN_MAC6            0x00000008
 317 #define INTR_EN_MAC7            0x00000002
 318 #define INTR_EN_MAC8            0x00200000
 319 #define INTR_EN_MAC9            0x00100000
 320 #define INTR_EN_REV0            0x00008000
 321 #define INTR_EN_REV1            0x00004000
 322 #define INTR_EN_REV2            0x00002000
 323 #define INTR_EN_REV3            0x00001000
 324 #define INTR_EN_TMR             0x01000000
 325
 326 enum fman_dma_aid_mode {
 327         FMAN_DMA_AID_OUT_PORT_ID = 0,             /* 4 LSB of PORT_ID */
 328         FMAN_DMA_AID_OUT_TNUM                     /* 4 LSB of TNUM */
 329 };
 330
 331 struct fman_iram_regs {
 332         u32 iadd;       /* FM IRAM instruction address register */
 333         u32 idata;      /* FM IRAM instruction data register */
 334         u32 itcfg;      /* FM IRAM timing config register */
 335         u32 iready;     /* FM IRAM ready register */
 336 };
 337
 338 struct fman_fpm_regs {
 339         u32 fmfp_tnc;           /* FPM TNUM Control 0x00 */
 340         u32 fmfp_prc;           /* FPM Port_ID FmCtl Association 0x04 */
 341         u32 fmfp_brkc;          /* FPM Breakpoint Control 0x08 */
 342         u32 fmfp_mxd;           /* FPM Flush Control 0x0c */
 343         u32 fmfp_dist1;         /* FPM Dispatch Thresholds1 0x10 */
 344         u32 fmfp_dist2;         /* FPM Dispatch Thresholds2 0x14 */
 345         u32 fm_epi;             /* FM Error Pending Interrupts 0x18 */
 346         u32 fm_rie;             /* FM Error Interrupt Enable 0x1c */
 347         u32 fmfp_fcev[4];       /* FPM FMan-Controller Event 1-4 0x20-0x2f */
 348         u32 res0030[4];         /* res 0x30 - 0x3f */
 349         u32 fmfp_cee[4];        /* PM FMan-Controller Event 1-4 0x40-0x4f */
 350         u32 res0050[4];         /* res 0x50-0x5f */
 351         u32 fmfp_tsc1;          /* FPM TimeStamp Control1 0x60 */
 352         u32 fmfp_tsc2;          /* FPM TimeStamp Control2 0x64 */
 353         u32 fmfp_tsp;           /* FPM Time Stamp 0x68 */
 354         u32 fmfp_tsf;           /* FPM Time Stamp Fraction 0x6c */
 355         u32 fm_rcr;             /* FM Rams Control 0x70 */
 356         u32 fmfp_extc;          /* FPM External Requests Control 0x74 */
 357         u32 fmfp_ext1;          /* FPM External Requests Config1 0x78 */
 358         u32 fmfp_ext2;          /* FPM External Requests Config2 0x7c */
 359         u32 fmfp_drd[16];       /* FPM Data_Ram Data 0-15 0x80 - 0xbf */
 360         u32 fmfp_dra;           /* FPM Data Ram Access 0xc0 */
 361         u32 fm_ip_rev_1;        /* FM IP Block Revision 1 0xc4 */
 362         u32 fm_ip_rev_2;        /* FM IP Block Revision 2 0xc8 */
 363         u32 fm_rstc;            /* FM Reset Command 0xcc */
 364         u32 fm_cld;             /* FM Classifier Debug 0xd0 */
 365         u32 fm_npi;             /* FM Normal Pending Interrupts 0xd4 */
 366         u32 fmfp_exte;          /* FPM External Requests Enable 0xd8 */
 367         u32 fmfp_ee;            /* FPM Event&Mask 0xdc */
 368         u32 fmfp_cev[4];        /* FPM CPU Event 1-4 0xe0-0xef */
 369         u32 res00f0[4];         /* res 0xf0-0xff */
 370         u32 fmfp_ps[50];        /* FPM Port Status 0x100-0x1c7 */
 371         u32 res01c8[14];        /* res 0x1c8-0x1ff */
 372         u32 fmfp_clfabc;        /* FPM CLFABC 0x200 */
 373         u32 fmfp_clfcc;         /* FPM CLFCC 0x204 */
 374         u32 fmfp_clfaval;       /* FPM CLFAVAL 0x208 */
 375         u32 fmfp_clfbval;       /* FPM CLFBVAL 0x20c */
 376         u32 fmfp_clfcval;       /* FPM CLFCVAL 0x210 */
 377         u32 fmfp_clfamsk;       /* FPM CLFAMSK 0x214 */
 378         u32 fmfp_clfbmsk;       /* FPM CLFBMSK 0x218 */
 379         u32 fmfp_clfcmsk;       /* FPM CLFCMSK 0x21c */
 380         u32 fmfp_clfamc;        /* FPM CLFAMC 0x220 */
 381         u32 fmfp_clfbmc;        /* FPM CLFBMC 0x224 */
 382         u32 fmfp_clfcmc;        /* FPM CLFCMC 0x228 */
 383         u32 fmfp_decceh;        /* FPM DECCEH 0x22c */
 384         u32 res0230[116];       /* res 0x230 - 0x3ff */
 385         u32 fmfp_ts[128];       /* 0x400: FPM Task Status 0x400 - 0x5ff */
 386         u32 res0600[0x400 - 384];
 387 };
 388
 389 struct fman_bmi_regs {
 390         u32 fmbm_init;          /* BMI Initialization 0x00 */
 391         u32 fmbm_cfg1;          /* BMI Configuration 1 0x04 */
 392         u32 fmbm_cfg2;          /* BMI Configuration 2 0x08 */
 393         u32 res000c[5];         /* 0x0c - 0x1f */
 394         u32 fmbm_ievr;          /* Interrupt Event Register 0x20 */
 395         u32 fmbm_ier;           /* Interrupt Enable Register 0x24 */
 396         u32 fmbm_ifr;           /* Interrupt Force Register 0x28 */
 397         u32 res002c[5];         /* 0x2c - 0x3f */
 398         u32 fmbm_arb[8];        /* BMI Arbitration 0x40 - 0x5f */
 399         u32 res0060[12];        /* 0x60 - 0x8f */
 400         u32 fmbm_dtc[3];        /* Debug Trap Counter 0x90 - 0x9b */
 401         u32 res009c;            /* 0x9c */
 402         u32 fmbm_dcv[3][4];     /* Debug Compare val 0xa0-0xcf */
 403         u32 fmbm_dcm[3][4];     /* Debug Compare Mask 0xd0-0xff */
 404         u32 fmbm_gde;           /* BMI Global Debug Enable 0x100 */
 405         u32 fmbm_pp[63];        /* BMI Port Parameters 0x104 - 0x1ff */
 406         u32 res0200;            /* 0x200 */
 407         u32 fmbm_pfs[63];       /* BMI Port FIFO Size 0x204 - 0x2ff */
 408         u32 res0300;            /* 0x300 */
 409         u32 fmbm_spliodn[63];   /* Port Partition ID 0x304 - 0x3ff */
 410 };
 411
 412 struct fman_qmi_regs {
 413         u32 fmqm_gc;            /* General Configuration Register 0x00 */
 414         u32 res0004;            /* 0x04 */
 415         u32 fmqm_eie;           /* Error Interrupt Event Register 0x08 */
 416         u32 fmqm_eien;          /* Error Interrupt Enable Register 0x0c */
 417         u32 fmqm_eif;           /* Error Interrupt Force Register 0x10 */
 418         u32 fmqm_ie;            /* Interrupt Event Register 0x14 */
 419         u32 fmqm_ien;           /* Interrupt Enable Register 0x18 */
 420         u32 fmqm_if;            /* Interrupt Force Register 0x1c */
 421         u32 fmqm_gs;            /* Global Status Register 0x20 */
 422         u32 fmqm_ts;            /* Task Status Register 0x24 */
 423         u32 fmqm_etfc;          /* Enqueue Total Frame Counter 0x28 */
 424         u32 fmqm_dtfc;          /* Dequeue Total Frame Counter 0x2c */
 425         u32 fmqm_dc0;           /* Dequeue Counter 0 0x30 */
 426         u32 fmqm_dc1;           /* Dequeue Counter 1 0x34 */
 427         u32 fmqm_dc2;           /* Dequeue Counter 2 0x38 */
 428         u32 fmqm_dc3;           /* Dequeue Counter 3 0x3c */
 429         u32 fmqm_dfdc;          /* Dequeue FQID from Default Counter 0x40 */
 430         u32 fmqm_dfcc;          /* Dequeue FQID from Context Counter 0x44 */
 431         u32 fmqm_dffc;          /* Dequeue FQID from FD Counter 0x48 */
 432         u32 fmqm_dcc;           /* Dequeue Confirm Counter 0x4c */
 433         u32 res0050[7];         /* 0x50 - 0x6b */
 434         u32 fmqm_tapc;          /* Tnum Aging Period Control 0x6c */
 435         u32 fmqm_dmcvc;         /* Dequeue MAC Command Valid Counter 0x70 */
 436         u32 fmqm_difdcc;        /* Dequeue Invalid FD Command Counter 0x74 */
 437         u32 fmqm_da1v;          /* Dequeue A1 Valid Counter 0x78 */
 438         u32 res007c;            /* 0x7c */
 439         u32 fmqm_dtc;           /* 0x80 Debug Trap Counter 0x80 */
 440         u32 fmqm_efddd;         /* 0x84 Enqueue Frame desc Dynamic dbg 0x84 */
 441         u32 res0088[2];         /* 0x88 - 0x8f */
 442         struct {
 443                 u32 fmqm_dtcfg1;        /* 0x90 dbg trap cfg 1 Register 0x00 */
 444                 u32 fmqm_dtval1;        /* Debug Trap Value 1 Register 0x04 */
 445                 u32 fmqm_dtm1;          /* Debug Trap Mask 1 Register 0x08 */
 446                 u32 fmqm_dtc1;          /* Debug Trap Counter 1 Register 0x0c */
 447                 u32 fmqm_dtcfg2;        /* dbg Trap cfg 2 Register 0x10 */
 448                 u32 fmqm_dtval2;        /* Debug Trap Value 2 Register 0x14 */
 449                 u32 fmqm_dtm2;          /* Debug Trap Mask 2 Register 0x18 */
 450                 u32 res001c;            /* 0x1c */
 451         } dbg_traps[3];                 /* 0x90 - 0xef */
 452         u8 res00f0[0x400 - 0xf0];       /* 0xf0 - 0x3ff */
 453 };
 454
 455 struct fman_dma_regs {
 456         u32 fmdmsr;     /* FM DMA status register 0x00 */
 457         u32 fmdmmr;     /* FM DMA mode register 0x04 */
 458         u32 fmdmtr;     /* FM DMA bus threshold register 0x08 */
 459         u32 fmdmhy;     /* FM DMA bus hysteresis register 0x0c */
 460         u32 fmdmsetr;   /* FM DMA SOS emergency Threshold Register 0x10 */
 461         u32 fmdmtah;    /* FM DMA transfer bus address high reg 0x14 */
 462         u32 fmdmtal;    /* FM DMA transfer bus address low reg 0x18 */
 463         u32 fmdmtcid;   /* FM DMA transfer bus communication ID reg 0x1c */
 464         u32 fmdmra;     /* FM DMA bus internal ram address register 0x20 */
 465         u32 fmdmrd;     /* FM DMA bus internal ram data register 0x24 */
 466         u32 fmdmwcr;    /* FM DMA CAM watchdog counter value 0x28 */
 467         u32 fmdmebcr;   /* FM DMA CAM base in MURAM register 0x2c */
 468         u32 fmdmccqdr;  /* FM DMA CAM and CMD Queue Debug reg 0x30 */
 469         u32 fmdmccqvr1; /* FM DMA CAM and CMD Queue Value reg #1 0x34 */
 470         u32 fmdmccqvr2; /* FM DMA CAM and CMD Queue Value reg #2 0x38 */
 471         u32 fmdmcqvr3;  /* FM DMA CMD Queue Value register #3 0x3c */
 472         u32 fmdmcqvr4;  /* FM DMA CMD Queue Value register #4 0x40 */
 473         u32 fmdmcqvr5;  /* FM DMA CMD Queue Value register #5 0x44 */
 474         u32 fmdmsefrc;  /* FM DMA Semaphore Entry Full Reject Cntr 0x48 */
 475         u32 fmdmsqfrc;  /* FM DMA Semaphore Queue Full Reject Cntr 0x4c */
 476         u32 fmdmssrc;   /* FM DMA Semaphore SYNC Reject Counter 0x50 */
 477         u32 fmdmdcr;    /* FM DMA Debug Counter 0x54 */
 478         u32 fmdmemsr;   /* FM DMA Emergency Smoother Register 0x58 */
 479         u32 res005c;    /* 0x5c */
 480         u32 fmdmplr[FMAN_LIODN_TBL / 2];        /* DMA LIODN regs 0x60-0xdf */
 481         u32 res00e0[0x400 - 56];
 482 };
 483
 484 struct fman_hwp_regs {
 485         u32 res0000[0x844 / 4];         /* 0x000..0x843 */
 486         u32 fmprrpimac; /* FM Parser Internal memory access control */
 487         u32 res[(0x1000 - 0x848) / 4];  /* 0x848..0xFFF */
 488 };
 489
 490 /* Structure that holds current FMan state.
 491  * Used for saving run time information.
 492  */
 493 struct fman_state_struct {
 494         u8 fm_id;
 495         u16 fm_clk_freq;
 496         struct fman_rev_info rev_info;
 497         bool enabled_time_stamp;
 498         u8 count1_micro_bit;
 499         u8 total_num_of_tasks;
 500         u8 accumulated_num_of_tasks;
 501         u32 accumulated_fifo_size;
 502         u8 accumulated_num_of_open_dmas;
 503         u8 accumulated_num_of_deq_tnums;
 504         u32 exceptions;
 505         u32 extra_fifo_pool_size;
 506         u8 extra_tasks_pool_size;
 507         u8 extra_open_dmas_pool_size;
 508         u16 port_mfl[MAX_NUM_OF_MACS];
 509         u16 mac_mfl[MAX_NUM_OF_MACS];
 510
 511         /* SOC specific */
 512         u32 fm_iram_size;
 513         /* DMA */
 514         u32 dma_thresh_max_commq;
 515         u32 dma_thresh_max_buf;
 516         u32 max_num_of_open_dmas;
 517         /* QMI */
 518         u32 qmi_max_num_of_tnums;
 519         u32 qmi_def_tnums_thresh;
 520         /* BMI */
 521         u32 bmi_max_num_of_tasks;
 522         u32 bmi_max_fifo_size;
 523         /* General */
 524         u32 fm_port_num_of_cg;
 525         u32 num_of_rx_ports;
 526         u32 total_fifo_size;
 527
 528         u32 qman_channel_base;
 529         u32 num_of_qman_channels;
 530
 531         struct resource *res;
 532 };
 533
 534 /* Structure that holds FMan initial configuration */
 535 struct fman_cfg {
 536         u8 disp_limit_tsh;
 537         u8 prs_disp_tsh;
 538         u8 plcr_disp_tsh;
 539         u8 kg_disp_tsh;
 540         u8 bmi_disp_tsh;
 541         u8 qmi_enq_disp_tsh;
 542         u8 qmi_deq_disp_tsh;
 543         u8 fm_ctl1_disp_tsh;
 544         u8 fm_ctl2_disp_tsh;
 545         int dma_cache_override;
 546         enum fman_dma_aid_mode dma_aid_mode;
 547         u32 dma_axi_dbg_num_of_beats;
 548         u32 dma_cam_num_of_entries;
 549         u32 dma_watchdog;
 550         u8 dma_comm_qtsh_asrt_emer;
 551         u32 dma_write_buf_tsh_asrt_emer;
 552         u32 dma_read_buf_tsh_asrt_emer;
 553         u8 dma_comm_qtsh_clr_emer;
 554         u32 dma_write_buf_tsh_clr_emer;
 555         u32 dma_read_buf_tsh_clr_emer;
 556         u32 dma_sos_emergency;
 557         int dma_dbg_cnt_mode;
 558         int catastrophic_err;
 559         int dma_err;
 560         u32 exceptions;
 561         u16 clk_freq;
 562         u32 cam_base_addr;
 563         u32 fifo_base_addr;
 564         u32 total_fifo_size;
 565         u32 total_num_of_tasks;
 566         u32 qmi_def_tnums_thresh;
 567 };
 568
 569 static irqreturn_t fman_exceptions(struct fman *fman,
 570                                    enum fman_exceptions exception)
 571 {
 572         dev_dbg(fman->dev, "%s: FMan[%d] exception %d\n",
 573                 __func__, fman->state->fm_id, exception);
 574
 575         return IRQ_HANDLED;
 576 }
 577
 578 static irqreturn_t fman_bus_error(struct fman *fman, u8 __maybe_unused port_id,
 579                                   u64 __maybe_unused addr,
 580                                   u8 __maybe_unused tnum,
 581                                   u16 __maybe_unused liodn)
 582 {
 583         dev_dbg(fman->dev, "%s: FMan[%d] bus error: port_id[%d]\n",
 584                 __func__, fman->state->fm_id, port_id);
 585
 586         return IRQ_HANDLED;
 587 }
 588
 589 static inline irqreturn_t call_mac_isr(struct fman *fman, u8 id)
 590 {
 591         if (fman->intr_mng[id].isr_cb) {
 592                 fman->intr_mng[id].isr_cb(fman->intr_mng[id].src_handle);
 593
 594                 return IRQ_HANDLED;
 595         }
 596
 597         return IRQ_NONE;
 598 }
 599
 600 static inline u8 hw_port_id_to_sw_port_id(u8 major, u8 hw_port_id)
 601 {
 602         u8 sw_port_id = 0;
 603
 604         if (hw_port_id >= BASE_TX_PORTID)
 605                 sw_port_id = hw_port_id - BASE_TX_PORTID;
 606         else if (hw_port_id >= BASE_RX_PORTID)
 607                 sw_port_id = hw_port_id - BASE_RX_PORTID;
 608         else
 609                 sw_port_id = 0;
 610
 611         return sw_port_id;
 612 }
 613
 614 static void set_port_order_restoration(struct fman_fpm_regs __iomem *fpm_rg,
 615                                        u8 port_id)
 616 {
 617         u32 tmp = 0;
 618
 619         tmp = port_id << FPM_PORT_FM_CTL_PORTID_SHIFT;
 620
 621         tmp |= FPM_PRT_FM_CTL2 | FPM_PRT_FM_CTL1;
 622
 623         /* order restoration */
 624         if (port_id % 2)
 625                 tmp |= FPM_PRT_FM_CTL1 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT;
 626         else
 627                 tmp |= FPM_PRT_FM_CTL2 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT;
 628
 629         iowrite32be(tmp, &fpm_rg->fmfp_prc);
 630 }
 631
 632 static void set_port_liodn(struct fman *fman, u8 port_id,
 633                            u32 liodn_base, u32 liodn_ofst)
 634 {
 635         u32 tmp;
 636
 637         iowrite32be(liodn_ofst, &fman->bmi_regs->fmbm_spliodn[port_id - 1]);
 638         if (!IS_ENABLED(CONFIG_FSL_PAMU))
 639                 return;
 640         /* set LIODN base for this port */
 641         tmp = ioread32be(&fman->dma_regs->fmdmplr[port_id / 2]);
 642         if (port_id % 2) {
 643                 tmp &= ~DMA_LIODN_BASE_MASK;
 644                 tmp |= liodn_base;
 645         } else {
 646                 tmp &= ~(DMA_LIODN_BASE_MASK << DMA_LIODN_SHIFT);
 647                 tmp |= liodn_base << DMA_LIODN_SHIFT;
 648         }
 649         iowrite32be(tmp, &fman->dma_regs->fmdmplr[port_id / 2]);
 650 }
 651
 652 static void enable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg)
 653 {
 654         u32 tmp;
 655
 656         tmp = ioread32be(&fpm_rg->fm_rcr);
 657         if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL)
 658                 iowrite32be(tmp | FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
 659         else
 660                 iowrite32be(tmp | FPM_RAM_RAMS_ECC_EN |
 661                             FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
 662 }
 663
 664 static void disable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg)
 665 {
 666         u32 tmp;
 667
 668         tmp = ioread32be(&fpm_rg->fm_rcr);
 669         if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL)
 670                 iowrite32be(tmp & ~FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
 671         else
 672                 iowrite32be(tmp & ~(FPM_RAM_RAMS_ECC_EN | FPM_RAM_IRAM_ECC_EN),
 673                             &fpm_rg->fm_rcr);
 674 }
 675
 676 static void fman_defconfig(struct fman_cfg *cfg)
 677 {
 678         memset(cfg, 0, sizeof(struct fman_cfg));
 679
 680         cfg->catastrophic_err = DEFAULT_CATASTROPHIC_ERR;
 681         cfg->dma_err = DEFAULT_DMA_ERR;
 682         cfg->dma_aid_mode = DEFAULT_AID_MODE;
 683         cfg->dma_comm_qtsh_clr_emer = DEFAULT_DMA_COMM_Q_LOW;
 684         cfg->dma_comm_qtsh_asrt_emer = DEFAULT_DMA_COMM_Q_HIGH;
 685         cfg->dma_cache_override = DEFAULT_CACHE_OVERRIDE;
 686         cfg->dma_cam_num_of_entries = DEFAULT_DMA_CAM_NUM_OF_ENTRIES;
 687         cfg->dma_dbg_cnt_mode = DEFAULT_DMA_DBG_CNT_MODE;
 688         cfg->dma_sos_emergency = DEFAULT_DMA_SOS_EMERGENCY;
 689         cfg->dma_watchdog = DEFAULT_DMA_WATCHDOG;
 690         cfg->disp_limit_tsh = DEFAULT_DISP_LIMIT;
 691         cfg->prs_disp_tsh = DEFAULT_PRS_DISP_TH;
 692         cfg->plcr_disp_tsh = DEFAULT_PLCR_DISP_TH;
 693         cfg->kg_disp_tsh = DEFAULT_KG_DISP_TH;
 694         cfg->bmi_disp_tsh = DEFAULT_BMI_DISP_TH;
 695         cfg->qmi_enq_disp_tsh = DEFAULT_QMI_ENQ_DISP_TH;
 696         cfg->qmi_deq_disp_tsh = DEFAULT_QMI_DEQ_DISP_TH;
 697         cfg->fm_ctl1_disp_tsh = DEFAULT_FM_CTL1_DISP_TH;
 698         cfg->fm_ctl2_disp_tsh = DEFAULT_FM_CTL2_DISP_TH;
 699 }
 700
 701 static int dma_init(struct fman *fman)
 702 {
 703         struct fman_dma_regs __iomem *dma_rg = fman->dma_regs;
 704         struct fman_cfg *cfg = fman->cfg;
 705         u32 tmp_reg;
 706
 707         /* Init DMA Registers */
 708
 709         /* clear status reg events */
 710         tmp_reg = (DMA_STATUS_BUS_ERR | DMA_STATUS_READ_ECC |
 711                    DMA_STATUS_SYSTEM_WRITE_ECC | DMA_STATUS_FM_WRITE_ECC);
 712         iowrite32be(ioread32be(&dma_rg->fmdmsr) | tmp_reg, &dma_rg->fmdmsr);
 713
 714         /* configure mode register */
 715         tmp_reg = 0;
 716         tmp_reg |= cfg->dma_cache_override << DMA_MODE_CACHE_OR_SHIFT;
 717         if (cfg->exceptions & EX_DMA_BUS_ERROR)
 718                 tmp_reg |= DMA_MODE_BER;
 719         if ((cfg->exceptions & EX_DMA_SYSTEM_WRITE_ECC) |
 720             (cfg->exceptions & EX_DMA_READ_ECC) |
 721             (cfg->exceptions & EX_DMA_FM_WRITE_ECC))
 722                 tmp_reg |= DMA_MODE_ECC;
 723         if (cfg->dma_axi_dbg_num_of_beats)
 724                 tmp_reg |= (DMA_MODE_AXI_DBG_MASK &
 725                         ((cfg->dma_axi_dbg_num_of_beats - 1)
 726                         << DMA_MODE_AXI_DBG_SHIFT));
 727
 728         tmp_reg |= (((cfg->dma_cam_num_of_entries / DMA_CAM_UNITS) - 1) &
 729                 DMA_MODE_CEN_MASK) << DMA_MODE_CEN_SHIFT;
 730         tmp_reg |= DMA_MODE_SECURE_PROT;
 731         tmp_reg |= cfg->dma_dbg_cnt_mode << DMA_MODE_DBG_SHIFT;
 732         tmp_reg |= cfg->dma_aid_mode << DMA_MODE_AID_MODE_SHIFT;
 733
 734         iowrite32be(tmp_reg, &dma_rg->fmdmmr);
 735
 736         /* configure thresholds register */
 737         tmp_reg = ((u32)cfg->dma_comm_qtsh_asrt_emer <<
 738                 DMA_THRESH_COMMQ_SHIFT);
 739         tmp_reg |= (cfg->dma_read_buf_tsh_asrt_emer &
 740                 DMA_THRESH_READ_INT_BUF_MASK) << DMA_THRESH_READ_INT_BUF_SHIFT;
 741         tmp_reg |= cfg->dma_write_buf_tsh_asrt_emer &
 742                 DMA_THRESH_WRITE_INT_BUF_MASK;
 743
 744         iowrite32be(tmp_reg, &dma_rg->fmdmtr);
 745
 746         /* configure hysteresis register */
 747         tmp_reg = ((u32)cfg->dma_comm_qtsh_clr_emer <<
 748                 DMA_THRESH_COMMQ_SHIFT);
 749         tmp_reg |= (cfg->dma_read_buf_tsh_clr_emer &
 750                 DMA_THRESH_READ_INT_BUF_MASK) << DMA_THRESH_READ_INT_BUF_SHIFT;
 751         tmp_reg |= cfg->dma_write_buf_tsh_clr_emer &
 752                 DMA_THRESH_WRITE_INT_BUF_MASK;
 753
 754         iowrite32be(tmp_reg, &dma_rg->fmdmhy);
 755
 756         /* configure emergency threshold */
 757         iowrite32be(cfg->dma_sos_emergency, &dma_rg->fmdmsetr);
 758
 759         /* configure Watchdog */
 760         iowrite32be((cfg->dma_watchdog * cfg->clk_freq), &dma_rg->fmdmwcr);
 761
 762         iowrite32be(cfg->cam_base_addr, &dma_rg->fmdmebcr);
 763
 764         /* Allocate MURAM for CAM */
 765         fman->cam_size =
 766                 (u32)(fman->cfg->dma_cam_num_of_entries * DMA_CAM_SIZEOF_ENTRY);
 767         fman->cam_offset = fman_muram_alloc(fman->muram, fman->cam_size);
 768         if (IS_ERR_VALUE(fman->cam_offset)) {
 769                 dev_err(fman->dev, "%s: MURAM alloc for DMA CAM failed\n",
 770                         __func__);
 771                 return -ENOMEM;
 772         }
 773
 774         if (fman->state->rev_info.major == 2) {
 775                 u32 __iomem *cam_base_addr;
 776
 777                 fman_muram_free_mem(fman->muram, fman->cam_offset,
 778                                     fman->cam_size);
 779
 780                 fman->cam_size = fman->cfg->dma_cam_num_of_entries * 72 + 128;
 781                 fman->cam_offset = fman_muram_alloc(fman->muram,
 782                                                     fman->cam_size);
 783                 if (IS_ERR_VALUE(fman->cam_offset)) {
 784                         dev_err(fman->dev, "%s: MURAM alloc for DMA CAM failed\n",
 785                                 __func__);
 786                         return -ENOMEM;
 787                 }
 788
 789                 if (fman->cfg->dma_cam_num_of_entries % 8 ||
 790                     fman->cfg->dma_cam_num_of_entries > 32) {
 791                         dev_err(fman->dev, "%s: wrong dma_cam_num_of_entries\n",
 792                                 __func__);
 793                         return -EINVAL;
 794                 }
 795
 796                 cam_base_addr = (u32 __iomem *)
 797                         fman_muram_offset_to_vbase(fman->muram,
 798                                                    fman->cam_offset);
 799                 iowrite32be(~((1 <<
 800                             (32 - fman->cfg->dma_cam_num_of_entries)) - 1),
 801                             cam_base_addr);
 802         }
 803
 804         fman->cfg->cam_base_addr = fman->cam_offset;
 805
 806         return 0;
 807 }
 808
 809 static void fpm_init(struct fman_fpm_regs __iomem *fpm_rg, struct fman_cfg *cfg)
 810 {
 811         u32 tmp_reg;
 812         int i;
 813
 814         /* Init FPM Registers */
 815
 816         tmp_reg = (u32)(cfg->disp_limit_tsh << FPM_DISP_LIMIT_SHIFT);
 817         iowrite32be(tmp_reg, &fpm_rg->fmfp_mxd);
 818
 819         tmp_reg = (((u32)cfg->prs_disp_tsh << FPM_THR1_PRS_SHIFT) |
 820                    ((u32)cfg->kg_disp_tsh << FPM_THR1_KG_SHIFT) |
 821                    ((u32)cfg->plcr_disp_tsh << FPM_THR1_PLCR_SHIFT) |
 822                    ((u32)cfg->bmi_disp_tsh << FPM_THR1_BMI_SHIFT));
 823         iowrite32be(tmp_reg, &fpm_rg->fmfp_dist1);
 824
 825         tmp_reg =
 826                 (((u32)cfg->qmi_enq_disp_tsh << FPM_THR2_QMI_ENQ_SHIFT) |
 827                  ((u32)cfg->qmi_deq_disp_tsh << FPM_THR2_QMI_DEQ_SHIFT) |
 828                  ((u32)cfg->fm_ctl1_disp_tsh << FPM_THR2_FM_CTL1_SHIFT) |
 829                  ((u32)cfg->fm_ctl2_disp_tsh << FPM_THR2_FM_CTL2_SHIFT));
 830         iowrite32be(tmp_reg, &fpm_rg->fmfp_dist2);
 831
 832         /* define exceptions and error behavior */
 833         tmp_reg = 0;
 834         /* Clear events */
 835         tmp_reg |= (FPM_EV_MASK_STALL | FPM_EV_MASK_DOUBLE_ECC |
 836                     FPM_EV_MASK_SINGLE_ECC);
 837         /* enable interrupts */
 838         if (cfg->exceptions & EX_FPM_STALL_ON_TASKS)
 839                 tmp_reg |= FPM_EV_MASK_STALL_EN;
 840         if (cfg->exceptions & EX_FPM_SINGLE_ECC)
 841                 tmp_reg |= FPM_EV_MASK_SINGLE_ECC_EN;
 842         if (cfg->exceptions & EX_FPM_DOUBLE_ECC)
 843                 tmp_reg |= FPM_EV_MASK_DOUBLE_ECC_EN;
 844         tmp_reg |= (cfg->catastrophic_err << FPM_EV_MASK_CAT_ERR_SHIFT);
 845         tmp_reg |= (cfg->dma_err << FPM_EV_MASK_DMA_ERR_SHIFT);
 846         /* FMan is not halted upon external halt activation */
 847         tmp_reg |= FPM_EV_MASK_EXTERNAL_HALT;
 848         /* Man is not halted upon  Unrecoverable ECC error behavior */
 849         tmp_reg |= FPM_EV_MASK_ECC_ERR_HALT;
 850         iowrite32be(tmp_reg, &fpm_rg->fmfp_ee);
 851
 852         /* clear all fmCtls event registers */
 853         for (i = 0; i < FM_NUM_OF_FMAN_CTRL_EVENT_REGS; i++)
 854                 iowrite32be(0xFFFFFFFF, &fpm_rg->fmfp_cev[i]);
 855
 856         /* RAM ECC -  enable and clear events */
 857         /* first we need to clear all parser memory,
 858          * as it is uninitialized and may cause ECC errors
 859          */
 860         /* event bits */
 861         tmp_reg = (FPM_RAM_MURAM_ECC | FPM_RAM_IRAM_ECC);
 862
 863         iowrite32be(tmp_reg, &fpm_rg->fm_rcr);
 864
 865         tmp_reg = 0;
 866         if (cfg->exceptions & EX_IRAM_ECC) {
 867                 tmp_reg |= FPM_IRAM_ECC_ERR_EX_EN;
 868                 enable_rams_ecc(fpm_rg);
 869         }
 870         if (cfg->exceptions & EX_MURAM_ECC) {
 871                 tmp_reg |= FPM_MURAM_ECC_ERR_EX_EN;
 872                 enable_rams_ecc(fpm_rg);
 873         }
 874         iowrite32be(tmp_reg, &fpm_rg->fm_rie);
 875 }
 876
 877 static void bmi_init(struct fman_bmi_regs __iomem *bmi_rg,
 878                      struct fman_cfg *cfg)
 879 {
 880         u32 tmp_reg;
 881
 882         /* Init BMI Registers */
 883
 884         /* define common resources */
 885         tmp_reg = cfg->fifo_base_addr;
 886         tmp_reg = tmp_reg / BMI_FIFO_ALIGN;
 887
 888         tmp_reg |= ((cfg->total_fifo_size / FMAN_BMI_FIFO_UNITS - 1) <<
 889                     BMI_CFG1_FIFO_SIZE_SHIFT);
 890         iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg1);
 891
 892         tmp_reg = ((cfg->total_num_of_tasks - 1) & BMI_CFG2_TASKS_MASK) <<
 893                    BMI_CFG2_TASKS_SHIFT;
 894         /* num of DMA's will be dynamically updated when each port is set */
 895         iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg2);
 896
 897         /* define unmaskable exceptions, enable and clear events */
 898         tmp_reg = 0;
 899         iowrite32be(BMI_ERR_INTR_EN_LIST_RAM_ECC |
 900                     BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC |
 901                     BMI_ERR_INTR_EN_STATISTICS_RAM_ECC |
 902                     BMI_ERR_INTR_EN_DISPATCH_RAM_ECC, &bmi_rg->fmbm_ievr);
 903
 904         if (cfg->exceptions & EX_BMI_LIST_RAM_ECC)
 905                 tmp_reg |= BMI_ERR_INTR_EN_LIST_RAM_ECC;
 906         if (cfg->exceptions & EX_BMI_STORAGE_PROFILE_ECC)
 907                 tmp_reg |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;
 908         if (cfg->exceptions & EX_BMI_STATISTICS_RAM_ECC)
 909                 tmp_reg |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
 910         if (cfg->exceptions & EX_BMI_DISPATCH_RAM_ECC)
 911                 tmp_reg |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
 912         iowrite32be(tmp_reg, &bmi_rg->fmbm_ier);
 913 }
 914
 915 static void qmi_init(struct fman_qmi_regs __iomem *qmi_rg,
 916                      struct fman_cfg *cfg)
 917 {
 918         u32 tmp_reg;
 919
 920         /* Init QMI Registers */
 921
 922         /* Clear error interrupt events */
 923
 924         iowrite32be(QMI_ERR_INTR_EN_DOUBLE_ECC | QMI_ERR_INTR_EN_DEQ_FROM_DEF,
 925                     &qmi_rg->fmqm_eie);
 926         tmp_reg = 0;
 927         if (cfg->exceptions & EX_QMI_DEQ_FROM_UNKNOWN_PORTID)
 928                 tmp_reg |= QMI_ERR_INTR_EN_DEQ_FROM_DEF;
 929         if (cfg->exceptions & EX_QMI_DOUBLE_ECC)
 930                 tmp_reg |= QMI_ERR_INTR_EN_DOUBLE_ECC;
 931         /* enable events */
 932         iowrite32be(tmp_reg, &qmi_rg->fmqm_eien);
 933
 934         tmp_reg = 0;
 935         /* Clear interrupt events */
 936         iowrite32be(QMI_INTR_EN_SINGLE_ECC, &qmi_rg->fmqm_ie);
 937         if (cfg->exceptions & EX_QMI_SINGLE_ECC)
 938                 tmp_reg |= QMI_INTR_EN_SINGLE_ECC;
 939         /* enable events */
 940         iowrite32be(tmp_reg, &qmi_rg->fmqm_ien);
 941 }
 942
 943 static void hwp_init(struct fman_hwp_regs __iomem *hwp_rg)
 944 {
 945         /* enable HW Parser */
 946         iowrite32be(HWP_RPIMAC_PEN, &hwp_rg->fmprrpimac);
 947 }
 948
 949 static int enable(struct fman *fman, struct fman_cfg *cfg)
 950 {
 951         u32 cfg_reg = 0;
 952
 953         /* Enable all modules */
 954
 955         /* clear&enable global counters - calculate reg and save for later,
 956          * because it's the same reg for QMI enable
 957          */
 958         cfg_reg = QMI_CFG_EN_COUNTERS;
 959
 960         /* Set enqueue and dequeue thresholds */
 961         cfg_reg |= (cfg->qmi_def_tnums_thresh << 8) | cfg->qmi_def_tnums_thresh;
 962
 963         iowrite32be(BMI_INIT_START, &fman->bmi_regs->fmbm_init);
 964         iowrite32be(cfg_reg | QMI_CFG_ENQ_EN | QMI_CFG_DEQ_EN,
 965                     &fman->qmi_regs->fmqm_gc);
 966
 967         return 0;
 968 }
 969
 970 static int set_exception(struct fman *fman,
 971                          enum fman_exceptions exception, bool enable)
 972 {
 973         u32 tmp;
 974
 975         switch (exception) {
 976         case FMAN_EX_DMA_BUS_ERROR:
 977                 tmp = ioread32be(&fman->dma_regs->fmdmmr);
 978                 if (enable)
 979                         tmp |= DMA_MODE_BER;
 980                 else
 981                         tmp &= ~DMA_MODE_BER;
 982                 /* disable bus error */
 983                 iowrite32be(tmp, &fman->dma_regs->fmdmmr);
 984                 break;
 985         case FMAN_EX_DMA_READ_ECC:
 986         case FMAN_EX_DMA_SYSTEM_WRITE_ECC:
 987         case FMAN_EX_DMA_FM_WRITE_ECC:
 988                 tmp = ioread32be(&fman->dma_regs->fmdmmr);
 989                 if (enable)
 990                         tmp |= DMA_MODE_ECC;
 991                 else
 992                         tmp &= ~DMA_MODE_ECC;
 993                 iowrite32be(tmp, &fman->dma_regs->fmdmmr);
 994                 break;
 995         case FMAN_EX_FPM_STALL_ON_TASKS:
 996                 tmp = ioread32be(&fman->fpm_regs->fmfp_ee);
 997                 if (enable)
 998                         tmp |= FPM_EV_MASK_STALL_EN;
 999                 else
1000                         tmp &= ~FPM_EV_MASK_STALL_EN;
1001                 iowrite32be(tmp, &fman->fpm_regs->fmfp_ee);
1002                 break;
1003         case FMAN_EX_FPM_SINGLE_ECC:
1004                 tmp = ioread32be(&fman->fpm_regs->fmfp_ee);
1005                 if (enable)
1006                         tmp |= FPM_EV_MASK_SINGLE_ECC_EN;
1007                 else
1008                         tmp &= ~FPM_EV_MASK_SINGLE_ECC_EN;
1009                 iowrite32be(tmp, &fman->fpm_regs->fmfp_ee);
1010                 break;
1011         case FMAN_EX_FPM_DOUBLE_ECC:
1012                 tmp = ioread32be(&fman->fpm_regs->fmfp_ee);
1013                 if (enable)
1014                         tmp |= FPM_EV_MASK_DOUBLE_ECC_EN;
1015                 else
1016                         tmp &= ~FPM_EV_MASK_DOUBLE_ECC_EN;
1017                 iowrite32be(tmp, &fman->fpm_regs->fmfp_ee);
1018                 break;
1019         case FMAN_EX_QMI_SINGLE_ECC:
1020                 tmp = ioread32be(&fman->qmi_regs->fmqm_ien);
1021                 if (enable)
1022                         tmp |= QMI_INTR_EN_SINGLE_ECC;
1023                 else
1024                         tmp &= ~QMI_INTR_EN_SINGLE_ECC;
1025                 iowrite32be(tmp, &fman->qmi_regs->fmqm_ien);
1026                 break;
1027         case FMAN_EX_QMI_DOUBLE_ECC:
1028                 tmp = ioread32be(&fman->qmi_regs->fmqm_eien);
1029                 if (enable)
1030                         tmp |= QMI_ERR_INTR_EN_DOUBLE_ECC;
1031                 else
1032                         tmp &= ~QMI_ERR_INTR_EN_DOUBLE_ECC;
1033                 iowrite32be(tmp, &fman->qmi_regs->fmqm_eien);
1034                 break;
1035         case FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID:
1036                 tmp = ioread32be(&fman->qmi_regs->fmqm_eien);
1037                 if (enable)
1038                         tmp |= QMI_ERR_INTR_EN_DEQ_FROM_DEF;
1039                 else
1040                         tmp &= ~QMI_ERR_INTR_EN_DEQ_FROM_DEF;
1041                 iowrite32be(tmp, &fman->qmi_regs->fmqm_eien);
1042                 break;
1043         case FMAN_EX_BMI_LIST_RAM_ECC:
1044                 tmp = ioread32be(&fman->bmi_regs->fmbm_ier);
1045                 if (enable)
1046                         tmp |= BMI_ERR_INTR_EN_LIST_RAM_ECC;
1047                 else
1048                         tmp &= ~BMI_ERR_INTR_EN_LIST_RAM_ECC;
1049                 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier);
1050                 break;
1051         case FMAN_EX_BMI_STORAGE_PROFILE_ECC:
1052                 tmp = ioread32be(&fman->bmi_regs->fmbm_ier);
1053                 if (enable)
1054                         tmp |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;
1055                 else
1056                         tmp &= ~BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;
1057                 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier);
1058                 break;
1059         case FMAN_EX_BMI_STATISTICS_RAM_ECC:
1060                 tmp = ioread32be(&fman->bmi_regs->fmbm_ier);
1061                 if (enable)
1062                         tmp |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
1063                 else
1064                         tmp &= ~BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
1065                 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier);
1066                 break;
1067         case FMAN_EX_BMI_DISPATCH_RAM_ECC:
1068                 tmp = ioread32be(&fman->bmi_regs->fmbm_ier);
1069                 if (enable)
1070                         tmp |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
1071                 else
1072                         tmp &= ~BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
1073                 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier);
1074                 break;
1075         case FMAN_EX_IRAM_ECC:
1076                 tmp = ioread32be(&fman->fpm_regs->fm_rie);
1077                 if (enable) {
1078                         /* enable ECC if not enabled */
1079                         enable_rams_ecc(fman->fpm_regs);
1080                         /* enable ECC interrupts */
1081                         tmp |= FPM_IRAM_ECC_ERR_EX_EN;
1082                 } else {
1083                         /* ECC mechanism may be disabled,
1084                          * depending on driver status
1085                          */
1086                         disable_rams_ecc(fman->fpm_regs);
1087                         tmp &= ~FPM_IRAM_ECC_ERR_EX_EN;
1088                 }
1089                 iowrite32be(tmp, &fman->fpm_regs->fm_rie);
1090                 break;
1091         case FMAN_EX_MURAM_ECC:
1092                 tmp = ioread32be(&fman->fpm_regs->fm_rie);
1093                 if (enable) {
1094                         /* enable ECC if not enabled */
1095                         enable_rams_ecc(fman->fpm_regs);
1096                         /* enable ECC interrupts */
1097                         tmp |= FPM_MURAM_ECC_ERR_EX_EN;
1098                 } else {
1099                         /* ECC mechanism may be disabled,
1100                          * depending on driver status
1101                          */
1102                         disable_rams_ecc(fman->fpm_regs);
1103                         tmp &= ~FPM_MURAM_ECC_ERR_EX_EN;
1104                 }
1105                 iowrite32be(tmp, &fman->fpm_regs->fm_rie);
1106                 break;
1107         default:
1108                 return -EINVAL;
1109         }
1110         return 0;
1111 }
1112
1113 static void resume(struct fman_fpm_regs __iomem *fpm_rg)
1114 {
1115         u32 tmp;
1116
1117         tmp = ioread32be(&fpm_rg->fmfp_ee);
1118         /* clear tmp_reg event bits in order not to clear standing events */
1119         tmp &= ~(FPM_EV_MASK_DOUBLE_ECC |
1120                  FPM_EV_MASK_STALL | FPM_EV_MASK_SINGLE_ECC);
1121         tmp |= FPM_EV_MASK_RELEASE_FM;
1122
1123         iowrite32be(tmp, &fpm_rg->fmfp_ee);
1124 }
1125
1126 static int fill_soc_specific_params(struct fman_state_struct *state)
1127 {
1128         u8 minor = state->rev_info.minor;
1129         /* P4080 - Major 2
1130          * P2041/P3041/P5020/P5040 - Major 3
1131          * Tx/Bx - Major 6
1132          */
1133         switch (state->rev_info.major) {
1134         case 3:
1135                 state->bmi_max_fifo_size        = 160 * 1024;
1136                 state->fm_iram_size             = 64 * 1024;
1137                 state->dma_thresh_max_commq     = 31;
1138                 state->dma_thresh_max_buf       = 127;
1139                 state->qmi_max_num_of_tnums     = 64;
1140                 state->qmi_def_tnums_thresh     = 48;
1141                 state->bmi_max_num_of_tasks     = 128;
1142                 state->max_num_of_open_dmas     = 32;
1143                 state->fm_port_num_of_cg        = 256;
1144                 state->num_of_rx_ports  = 6;
1145                 state->total_fifo_size  = 136 * 1024;
1146                 break;
1147
1148         case 2:
1149                 state->bmi_max_fifo_size        = 160 * 1024;
1150                 state->fm_iram_size             = 64 * 1024;
1151                 state->dma_thresh_max_commq     = 31;
1152                 state->dma_thresh_max_buf       = 127;
1153                 state->qmi_max_num_of_tnums     = 64;
1154                 state->qmi_def_tnums_thresh     = 48;
1155                 state->bmi_max_num_of_tasks     = 128;
1156                 state->max_num_of_open_dmas     = 32;
1157                 state->fm_port_num_of_cg        = 256;
1158                 state->num_of_rx_ports  = 5;
1159                 state->total_fifo_size  = 100 * 1024;
1160                 break;
1161
1162         case 6:
1163                 state->dma_thresh_max_commq     = 83;
1164                 state->dma_thresh_max_buf       = 127;
1165                 state->qmi_max_num_of_tnums     = 64;
1166                 state->qmi_def_tnums_thresh     = 32;
1167                 state->fm_port_num_of_cg        = 256;
1168
1169                 /* FManV3L */
1170                 if (minor == 1 || minor == 4) {
1171                         state->bmi_max_fifo_size        = 192 * 1024;
1172                         state->bmi_max_num_of_tasks     = 64;
1173                         state->max_num_of_open_dmas     = 32;
1174                         state->num_of_rx_ports          = 5;
1175                         if (minor == 1)
1176                                 state->fm_iram_size     = 32 * 1024;
1177                         else
1178                                 state->fm_iram_size     = 64 * 1024;
1179                         state->total_fifo_size          = 156 * 1024;
1180                 }
1181                 /* FManV3H */
1182                 else if (minor == 0 || minor == 2 || minor == 3) {
1183                         state->bmi_max_fifo_size        = 384 * 1024;
1184                         state->fm_iram_size             = 64 * 1024;
1185                         state->bmi_max_num_of_tasks     = 128;
1186                         state->max_num_of_open_dmas     = 84;
1187                         state->num_of_rx_ports          = 8;
1188                         state->total_fifo_size          = 295 * 1024;
1189                 } else {
1190                         pr_err("Unsupported FManv3 version\n");
1191                         return -EINVAL;
1192                 }
1193
1194                 break;
1195         default:
1196                 pr_err("Unsupported FMan version\n");
1197                 return -EINVAL;
1198         }
1199
1200         return 0;
1201 }
1202
1203 static bool is_init_done(struct fman_cfg *cfg)
1204 {
1205         /* Checks if FMan driver parameters were initialized */
1206         if (!cfg)
1207                 return true;
1208
1209         return false;
1210 }
1211
1212 static void free_init_resources(struct fman *fman)
1213 {
1214         if (fman->cam_offset)
1215                 fman_muram_free_mem(fman->muram, fman->cam_offset,
1216                                     fman->cam_size);
1217         if (fman->fifo_offset)
1218                 fman_muram_free_mem(fman->muram, fman->fifo_offset,
1219                                     fman->fifo_size);
1220 }
1221
1222 static irqreturn_t bmi_err_event(struct fman *fman)
1223 {
1224         u32 event, mask, force;
1225         struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs;
1226         irqreturn_t ret = IRQ_NONE;
1227
1228         event = ioread32be(&bmi_rg->fmbm_ievr);
1229         mask = ioread32be(&bmi_rg->fmbm_ier);
1230         event &= mask;
1231         /* clear the forced events */
1232         force = ioread32be(&bmi_rg->fmbm_ifr);
1233         if (force & event)
1234                 iowrite32be(force & ~event, &bmi_rg->fmbm_ifr);
1235         /* clear the acknowledged events */
1236         iowrite32be(event, &bmi_rg->fmbm_ievr);
1237
1238         if (event & BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC)
1239                 ret = fman->exception_cb(fman, FMAN_EX_BMI_STORAGE_PROFILE_ECC);
1240         if (event & BMI_ERR_INTR_EN_LIST_RAM_ECC)
1241                 ret = fman->exception_cb(fman, FMAN_EX_BMI_LIST_RAM_ECC);
1242         if (event & BMI_ERR_INTR_EN_STATISTICS_RAM_ECC)
1243                 ret = fman->exception_cb(fman, FMAN_EX_BMI_STATISTICS_RAM_ECC);
1244         if (event & BMI_ERR_INTR_EN_DISPATCH_RAM_ECC)
1245                 ret = fman->exception_cb(fman, FMAN_EX_BMI_DISPATCH_RAM_ECC);
1246
1247         return ret;
1248 }
1249
1250 static irqreturn_t qmi_err_event(struct fman *fman)
1251 {
1252         u32 event, mask, force;
1253         struct fman_qmi_regs __iomem *qmi_rg = fman->qmi_regs;
1254         irqreturn_t ret = IRQ_NONE;
1255
1256         event = ioread32be(&qmi_rg->fmqm_eie);
1257         mask = ioread32be(&qmi_rg->fmqm_eien);
1258         event &= mask;
1259
1260         /* clear the forced events */
1261         force = ioread32be(&qmi_rg->fmqm_eif);
1262         if (force & event)
1263                 iowrite32be(force & ~event, &qmi_rg->fmqm_eif);
1264         /* clear the acknowledged events */
1265         iowrite32be(event, &qmi_rg->fmqm_eie);
1266
1267         if (event & QMI_ERR_INTR_EN_DOUBLE_ECC)
1268                 ret = fman->exception_cb(fman, FMAN_EX_QMI_DOUBLE_ECC);
1269         if (event & QMI_ERR_INTR_EN_DEQ_FROM_DEF)
1270                 ret = fman->exception_cb(fman,
1271                                          FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID);
1272
1273         return ret;
1274 }
1275
1276 static irqreturn_t dma_err_event(struct fman *fman)
1277 {
1278         u32 status, mask, com_id;
1279         u8 tnum, port_id, relative_port_id;
1280         u16 liodn;
1281         struct fman_dma_regs __iomem *dma_rg = fman->dma_regs;
1282         irqreturn_t ret = IRQ_NONE;
1283
1284         status = ioread32be(&dma_rg->fmdmsr);
1285         mask = ioread32be(&dma_rg->fmdmmr);
1286
1287         /* clear DMA_STATUS_BUS_ERR if mask has no DMA_MODE_BER */
1288         if ((mask & DMA_MODE_BER) != DMA_MODE_BER)
1289                 status &= ~DMA_STATUS_BUS_ERR;
1290
1291         /* clear relevant bits if mask has no DMA_MODE_ECC */
1292         if ((mask & DMA_MODE_ECC) != DMA_MODE_ECC)
1293                 status &= ~(DMA_STATUS_FM_SPDAT_ECC |
1294                             DMA_STATUS_READ_ECC |
1295                             DMA_STATUS_SYSTEM_WRITE_ECC |
1296                             DMA_STATUS_FM_WRITE_ECC);
1297
1298         /* clear set events */
1299         iowrite32be(status, &dma_rg->fmdmsr);
1300
1301         if (status & DMA_STATUS_BUS_ERR) {
1302                 u64 addr;
1303
1304                 addr = (u64)ioread32be(&dma_rg->fmdmtal);
1305                 addr |= ((u64)(ioread32be(&dma_rg->fmdmtah)) << 32);
1306
1307                 com_id = ioread32be(&dma_rg->fmdmtcid);
1308                 port_id = (u8)(((com_id & DMA_TRANSFER_PORTID_MASK) >>
1309                                DMA_TRANSFER_PORTID_SHIFT));
1310                 relative_port_id =
1311                 hw_port_id_to_sw_port_id(fman->state->rev_info.major, port_id);
1312                 tnum = (u8)((com_id & DMA_TRANSFER_TNUM_MASK) >>
1313                             DMA_TRANSFER_TNUM_SHIFT);
1314                 liodn = (u16)(com_id & DMA_TRANSFER_LIODN_MASK);
1315                 ret = fman->bus_error_cb(fman, relative_port_id, addr, tnum,
1316                                          liodn);
1317         }
1318         if (status & DMA_STATUS_FM_SPDAT_ECC)
1319                 ret = fman->exception_cb(fman, FMAN_EX_DMA_SINGLE_PORT_ECC);
1320         if (status & DMA_STATUS_READ_ECC)
1321                 ret = fman->exception_cb(fman, FMAN_EX_DMA_READ_ECC);
1322         if (status & DMA_STATUS_SYSTEM_WRITE_ECC)
1323                 ret = fman->exception_cb(fman, FMAN_EX_DMA_SYSTEM_WRITE_ECC);
1324         if (status & DMA_STATUS_FM_WRITE_ECC)
1325                 ret = fman->exception_cb(fman, FMAN_EX_DMA_FM_WRITE_ECC);
1326
1327         return ret;
1328 }
1329
1330 static irqreturn_t fpm_err_event(struct fman *fman)
1331 {
1332         u32 event;
1333         struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs;
1334         irqreturn_t ret = IRQ_NONE;
1335
1336         event = ioread32be(&fpm_rg->fmfp_ee);
1337         /* clear the all occurred events */
1338         iowrite32be(event, &fpm_rg->fmfp_ee);
1339
1340         if ((event & FPM_EV_MASK_DOUBLE_ECC) &&
1341             (event & FPM_EV_MASK_DOUBLE_ECC_EN))
1342                 ret = fman->exception_cb(fman, FMAN_EX_FPM_DOUBLE_ECC);
1343         if ((event & FPM_EV_MASK_STALL) && (event & FPM_EV_MASK_STALL_EN))
1344                 ret = fman->exception_cb(fman, FMAN_EX_FPM_STALL_ON_TASKS);
1345         if ((event & FPM_EV_MASK_SINGLE_ECC) &&
1346             (event & FPM_EV_MASK_SINGLE_ECC_EN))
1347                 ret = fman->exception_cb(fman, FMAN_EX_FPM_SINGLE_ECC);
1348
1349         return ret;
1350 }
1351
1352 static irqreturn_t muram_err_intr(struct fman *fman)
1353 {
1354         u32 event, mask;
1355         struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs;
1356         irqreturn_t ret = IRQ_NONE;
1357
1358         event = ioread32be(&fpm_rg->fm_rcr);
1359         mask = ioread32be(&fpm_rg->fm_rie);
1360
1361         /* clear MURAM event bit (do not clear IRAM event) */
1362         iowrite32be(event & ~FPM_RAM_IRAM_ECC, &fpm_rg->fm_rcr);
1363
1364         if ((mask & FPM_MURAM_ECC_ERR_EX_EN) && (event & FPM_RAM_MURAM_ECC))
1365                 ret = fman->exception_cb(fman, FMAN_EX_MURAM_ECC);
1366
1367         return ret;
1368 }
1369
1370 static irqreturn_t qmi_event(struct fman *fman)
1371 {
1372         u32 event, mask, force;
1373         struct fman_qmi_regs __iomem *qmi_rg = fman->qmi_regs;
1374         irqreturn_t ret = IRQ_NONE;
1375
1376         event = ioread32be(&qmi_rg->fmqm_ie);
1377         mask = ioread32be(&qmi_rg->fmqm_ien);
1378         event &= mask;
1379         /* clear the forced events */
1380         force = ioread32be(&qmi_rg->fmqm_if);
1381         if (force & event)
1382                 iowrite32be(force & ~event, &qmi_rg->fmqm_if);
1383         /* clear the acknowledged events */
1384         iowrite32be(event, &qmi_rg->fmqm_ie);
1385
1386         if (event & QMI_INTR_EN_SINGLE_ECC)
1387                 ret = fman->exception_cb(fman, FMAN_EX_QMI_SINGLE_ECC);
1388
1389         return ret;
1390 }
1391
1392 static void enable_time_stamp(struct fman *fman)
1393 {
1394         struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs;
1395         u16 fm_clk_freq = fman->state->fm_clk_freq;
1396         u32 tmp, intgr, ts_freq;
1397         u64 frac;
1398
1399         ts_freq = (u32)(1 << fman->state->count1_micro_bit);
1400         /* configure timestamp so that bit 8 will count 1 microsecond
1401          * Find effective count rate at TIMESTAMP least significant bits:
1402          * Effective_Count_Rate = 1MHz x 2^8 = 256MHz
1403          * Find frequency ratio between effective count rate and the clock:
1404          * Effective_Count_Rate / CLK e.g. for 600 MHz clock:
1405          * 256/600 = 0.4266666...
1406          */
1407
1408         intgr = ts_freq / fm_clk_freq;
1409         /* we multiply by 2^16 to keep the fraction of the division
1410          * we do not div back, since we write this value as a fraction
1411          * see spec
1412          */
1413
1414         frac = ((ts_freq << 16) - (intgr << 16) * fm_clk_freq) / fm_clk_freq;
1415         /* we check remainder of the division in order to round up if not int */
1416         if (((ts_freq << 16) - (intgr << 16) * fm_clk_freq) % fm_clk_freq)
1417                 frac++;
1418
1419         tmp = (intgr << FPM_TS_INT_SHIFT) | (u16)frac;
1420         iowrite32be(tmp, &fpm_rg->fmfp_tsc2);
1421
1422         /* enable timestamp with original clock */
1423         iowrite32be(FPM_TS_CTL_EN, &fpm_rg->fmfp_tsc1);
1424         fman->state->enabled_time_stamp = true;
1425 }
1426
1427 static int clear_iram(struct fman *fman)
1428 {
1429         struct fman_iram_regs __iomem *iram;
1430         int i, count;
1431
1432         iram = fman->base_addr + IMEM_OFFSET;
1433
1434         /* Enable the auto-increment */
1435         iowrite32be(IRAM_IADD_AIE, &iram->iadd);
1436         count = 100;
1437         do {
1438                 udelay(1);
1439         } while ((ioread32be(&iram->iadd) != IRAM_IADD_AIE) && --count);
1440         if (count == 0)
1441                 return -EBUSY;
1442
1443         for (i = 0; i < (fman->state->fm_iram_size / 4); i++)
1444                 iowrite32be(0xffffffff, &iram->idata);
1445
1446         iowrite32be(fman->state->fm_iram_size - 4, &iram->iadd);
1447         count = 100;
1448         do {
1449                 udelay(1);
1450         } while ((ioread32be(&iram->idata) != 0xffffffff) && --count);
1451         if (count == 0)
1452                 return -EBUSY;
1453
1454         return 0;
1455 }
1456
1457 static u32 get_exception_flag(enum fman_exceptions exception)
1458 {
1459         u32 bit_mask;
1460
1461         switch (exception) {
1462         case FMAN_EX_DMA_BUS_ERROR:
1463                 bit_mask = EX_DMA_BUS_ERROR;
1464                 break;
1465         case FMAN_EX_DMA_SINGLE_PORT_ECC:
1466                 bit_mask = EX_DMA_SINGLE_PORT_ECC;
1467                 break;
1468         case FMAN_EX_DMA_READ_ECC:
1469                 bit_mask = EX_DMA_READ_ECC;
1470                 break;
1471         case FMAN_EX_DMA_SYSTEM_WRITE_ECC:
1472                 bit_mask = EX_DMA_SYSTEM_WRITE_ECC;
1473                 break;
1474         case FMAN_EX_DMA_FM_WRITE_ECC:
1475                 bit_mask = EX_DMA_FM_WRITE_ECC;
1476                 break;
1477         case FMAN_EX_FPM_STALL_ON_TASKS:
1478                 bit_mask = EX_FPM_STALL_ON_TASKS;
1479                 break;
1480         case FMAN_EX_FPM_SINGLE_ECC:
1481                 bit_mask = EX_FPM_SINGLE_ECC;
1482                 break;
1483         case FMAN_EX_FPM_DOUBLE_ECC:
1484                 bit_mask = EX_FPM_DOUBLE_ECC;
1485                 break;
1486         case FMAN_EX_QMI_SINGLE_ECC:
1487                 bit_mask = EX_QMI_SINGLE_ECC;
1488                 break;
1489         case FMAN_EX_QMI_DOUBLE_ECC:
1490                 bit_mask = EX_QMI_DOUBLE_ECC;
1491                 break;
1492         case FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID:
1493                 bit_mask = EX_QMI_DEQ_FROM_UNKNOWN_PORTID;
1494                 break;
1495         case FMAN_EX_BMI_LIST_RAM_ECC:
1496                 bit_mask = EX_BMI_LIST_RAM_ECC;
1497                 break;
1498         case FMAN_EX_BMI_STORAGE_PROFILE_ECC:
1499                 bit_mask = EX_BMI_STORAGE_PROFILE_ECC;
1500                 break;
1501         case FMAN_EX_BMI_STATISTICS_RAM_ECC:
1502                 bit_mask = EX_BMI_STATISTICS_RAM_ECC;
1503                 break;
1504         case FMAN_EX_BMI_DISPATCH_RAM_ECC:
1505                 bit_mask = EX_BMI_DISPATCH_RAM_ECC;
1506                 break;
1507         case FMAN_EX_MURAM_ECC:
1508                 bit_mask = EX_MURAM_ECC;
1509                 break;
1510         default:
1511                 bit_mask = 0;
1512                 break;
1513         }
1514
1515         return bit_mask;
1516 }
1517
1518 static int get_module_event(enum fman_event_modules module, u8 mod_id,
1519                             enum fman_intr_type intr_type)
1520 {
1521         int event;
1522
1523         switch (module) {
1524         case FMAN_MOD_MAC:
1525                 if (intr_type == FMAN_INTR_TYPE_ERR)
1526                         event = FMAN_EV_ERR_MAC0 + mod_id;
1527                 else
1528                         event = FMAN_EV_MAC0 + mod_id;
1529                 break;
1530         case FMAN_MOD_FMAN_CTRL:
1531                 if (intr_type == FMAN_INTR_TYPE_ERR)
1532                         event = FMAN_EV_CNT;
1533                 else
1534                         event = (FMAN_EV_FMAN_CTRL_0 + mod_id);
1535                 break;
1536         case FMAN_MOD_DUMMY_LAST:
1537                 event = FMAN_EV_CNT;
1538                 break;
1539         default:
1540                 event = FMAN_EV_CNT;
1541                 break;
1542         }
1543
1544         return event;
1545 }
1546
1547 static int set_size_of_fifo(struct fman *fman, u8 port_id, u32 *size_of_fifo,
1548                             u32 *extra_size_of_fifo)
1549 {
1550         struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs;
1551         u32 fifo = *size_of_fifo;
1552         u32 extra_fifo = *extra_size_of_fifo;
1553         u32 tmp;
1554
1555         /* if this is the first time a port requires extra_fifo_pool_size,
1556          * the total extra_fifo_pool_size must be initialized to 1 buffer per
1557          * port
1558          */
1559         if (extra_fifo && !fman->state->extra_fifo_pool_size)
1560                 fman->state->extra_fifo_pool_size =
1561                         fman->state->num_of_rx_ports * FMAN_BMI_FIFO_UNITS;
1562
1563         fman->state->extra_fifo_pool_size =
1564                 max(fman->state->extra_fifo_pool_size, extra_fifo);
1565
1566         /* check that there are enough uncommitted fifo size */
1567         if ((fman->state->accumulated_fifo_size + fifo) >
1568             (fman->state->total_fifo_size -
1569             fman->state->extra_fifo_pool_size)) {
1570                 dev_err(fman->dev, "%s: Requested fifo size and extra size exceed total FIFO size.\n",
1571                         __func__);
1572                 return -EAGAIN;
1573         }
1574
1575         /* Read, modify and write to HW */
1576         tmp = (fifo / FMAN_BMI_FIFO_UNITS - 1) |
1577                ((extra_fifo / FMAN_BMI_FIFO_UNITS) <<
1578                BMI_EXTRA_FIFO_SIZE_SHIFT);
1579         iowrite32be(tmp, &bmi_rg->fmbm_pfs[port_id - 1]);
1580
1581         /* update accumulated */
1582         fman->state->accumulated_fifo_size += fifo;
1583
1584         return 0;
1585 }
1586
1587 static int set_num_of_tasks(struct fman *fman, u8 port_id, u8 *num_of_tasks,
1588                             u8 *num_of_extra_tasks)
1589 {
1590         struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs;
1591         u8 tasks = *num_of_tasks;
1592         u8 extra_tasks = *num_of_extra_tasks;
1593         u32 tmp;
1594
1595         if (extra_tasks)
1596                 fman->state->extra_tasks_pool_size =
1597                 max(fman->state->extra_tasks_pool_size, extra_tasks);
1598
1599         /* check that there are enough uncommitted tasks */
1600         if ((fman->state->accumulated_num_of_tasks + tasks) >
1601             (fman->state->total_num_of_tasks -
1602              fman->state->extra_tasks_pool_size)) {
1603                 dev_err(fman->dev, "%s: Requested num_of_tasks and extra tasks pool for fm%d exceed total num_of_tasks.\n",
1604                         __func__, fman->state->fm_id);
1605                 return -EAGAIN;
1606         }
1607         /* update accumulated */
1608         fman->state->accumulated_num_of_tasks += tasks;
1609
1610         /* Write to HW */
1611         tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) &
1612             ~(BMI_NUM_OF_TASKS_MASK | BMI_NUM_OF_EXTRA_TASKS_MASK);
1613         tmp |= ((u32)((tasks - 1) << BMI_NUM_OF_TASKS_SHIFT) |
1614                 (u32)(extra_tasks << BMI_EXTRA_NUM_OF_TASKS_SHIFT));
1615         iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]);
1616
1617         return 0;
1618 }
1619
1620 static int set_num_of_open_dmas(struct fman *fman, u8 port_id,
1621                                 u8 *num_of_open_dmas,
1622                                 u8 *num_of_extra_open_dmas)
1623 {
1624         struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs;
1625         u8 open_dmas = *num_of_open_dmas;
1626         u8 extra_open_dmas = *num_of_extra_open_dmas;
1627         u8 total_num_dmas = 0, current_val = 0, current_extra_val = 0;
1628         u32 tmp;
1629
1630         if (!open_dmas) {
1631                 /* Configuration according to values in the HW.
1632                  * read the current number of open Dma's
1633                  */
1634                 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]);
1635                 current_extra_val = (u8)((tmp & BMI_NUM_OF_EXTRA_DMAS_MASK) >>
1636                                          BMI_EXTRA_NUM_OF_DMAS_SHIFT);
1637
1638                 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]);
1639                 current_val = (u8)(((tmp & BMI_NUM_OF_DMAS_MASK) >>
1640                                    BMI_NUM_OF_DMAS_SHIFT) + 1);
1641
1642                 /* This is the first configuration and user did not
1643                  * specify value (!open_dmas), reset values will be used
1644                  * and we just save these values for resource management
1645                  */
1646                 fman->state->extra_open_dmas_pool_size =
1647                         (u8)max(fman->state->extra_open_dmas_pool_size,
1648                                 current_extra_val);
1649                 fman->state->accumulated_num_of_open_dmas += current_val;
1650                 *num_of_open_dmas = current_val;
1651                 *num_of_extra_open_dmas = current_extra_val;
1652                 return 0;
1653         }
1654
1655         if (extra_open_dmas > current_extra_val)
1656                 fman->state->extra_open_dmas_pool_size =
1657                     (u8)max(fman->state->extra_open_dmas_pool_size,
1658                             extra_open_dmas);
1659
1660         if ((fman->state->rev_info.major < 6) &&
1661             (fman->state->accumulated_num_of_open_dmas - current_val +
1662              open_dmas > fman->state->max_num_of_open_dmas)) {
1663                 dev_err(fman->dev, "%s: Requested num_of_open_dmas for fm%d exceeds total num_of_open_dmas.\n",
1664                         __func__, fman->state->fm_id);
1665                 return -EAGAIN;
1666         } else if ((fman->state->rev_info.major >= 6) &&
1667                    !((fman->state->rev_info.major == 6) &&
1668                    (fman->state->rev_info.minor == 0)) &&
1669                    (fman->state->accumulated_num_of_open_dmas -
1670                    current_val + open_dmas >
1671                    fman->state->dma_thresh_max_commq + 1)) {
1672                 dev_err(fman->dev, "%s: Requested num_of_open_dmas for fm%d exceeds DMA Command queue (%d)\n",
1673                         __func__, fman->state->fm_id,
1674                        fman->state->dma_thresh_max_commq + 1);
1675                 return -EAGAIN;
1676         }
1677
1678         WARN_ON(fman->state->accumulated_num_of_open_dmas < current_val);
1679         /* update acummulated */
1680         fman->state->accumulated_num_of_open_dmas -= current_val;
1681         fman->state->accumulated_num_of_open_dmas += open_dmas;
1682
1683         if (fman->state->rev_info.major < 6)
1684                 total_num_dmas =
1685                     (u8)(fman->state->accumulated_num_of_open_dmas +
1686                     fman->state->extra_open_dmas_pool_size);
1687
1688         /* calculate reg */
1689         tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) &
1690             ~(BMI_NUM_OF_DMAS_MASK | BMI_NUM_OF_EXTRA_DMAS_MASK);
1691         tmp |= (u32)(((open_dmas - 1) << BMI_NUM_OF_DMAS_SHIFT) |
1692                            (extra_open_dmas << BMI_EXTRA_NUM_OF_DMAS_SHIFT));
1693         iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]);
1694
1695         /* update total num of DMA's with committed number of open DMAS,
1696          * and max uncommitted pool.
1697          */
1698         if (total_num_dmas) {
1699                 tmp = ioread32be(&bmi_rg->fmbm_cfg2) & ~BMI_CFG2_DMAS_MASK;
1700                 tmp |= (u32)(total_num_dmas - 1) << BMI_CFG2_DMAS_SHIFT;
1701                 iowrite32be(tmp, &bmi_rg->fmbm_cfg2);
1702         }
1703
1704         return 0;
1705 }
1706
1707 static int fman_config(struct fman *fman)
1708 {
1709         void __iomem *base_addr;
1710         int err;
1711
1712         base_addr = fman->dts_params.base_addr;
1713
1714         fman->state = kzalloc(sizeof(*fman->state), GFP_KERNEL);
1715         if (!fman->state)
1716                 goto err_fm_state;
1717
1718         /* Allocate the FM driver's parameters structure */
1719         fman->cfg = kzalloc(sizeof(*fman->cfg), GFP_KERNEL);
1720         if (!fman->cfg)
1721                 goto err_fm_drv;
1722
1723         /* Initialize MURAM block */
1724         fman->muram =
1725                 fman_muram_init(fman->dts_params.muram_res.start,
1726                                 resource_size(&fman->dts_params.muram_res));
1727         if (!fman->muram)
1728                 goto err_fm_soc_specific;
1729
1730         /* Initialize FM parameters which will be kept by the driver */
1731         fman->state->fm_id = fman->dts_params.id;
1732         fman->state->fm_clk_freq = fman->dts_params.clk_freq;
1733         fman->state->qman_channel_base = fman->dts_params.qman_channel_base;
1734         fman->state->num_of_qman_channels =
1735                 fman->dts_params.num_of_qman_channels;
1736         fman->state->res = fman->dts_params.res;
1737         fman->exception_cb = fman_exceptions;
1738         fman->bus_error_cb = fman_bus_error;
1739         fman->fpm_regs = base_addr + FPM_OFFSET;
1740         fman->bmi_regs = base_addr + BMI_OFFSET;
1741         fman->qmi_regs = base_addr + QMI_OFFSET;
1742         fman->dma_regs = base_addr + DMA_OFFSET;
1743         fman->hwp_regs = base_addr + HWP_OFFSET;
1744         fman->kg_regs = base_addr + KG_OFFSET;
1745         fman->base_addr = base_addr;
1746
1747         spin_lock_init(&fman->spinlock);
1748         fman_defconfig(fman->cfg);
1749
1750         fman->state->extra_fifo_pool_size = 0;
1751         fman->state->exceptions = (EX_DMA_BUS_ERROR                 |
1752                                         EX_DMA_READ_ECC              |
1753                                         EX_DMA_SYSTEM_WRITE_ECC      |
1754                                         EX_DMA_FM_WRITE_ECC          |
1755                                         EX_FPM_STALL_ON_TASKS        |
1756                                         EX_FPM_SINGLE_ECC            |
1757                                         EX_FPM_DOUBLE_ECC            |
1758                                         EX_QMI_DEQ_FROM_UNKNOWN_PORTID |
1759                                         EX_BMI_LIST_RAM_ECC          |
1760                                         EX_BMI_STORAGE_PROFILE_ECC   |
1761                                         EX_BMI_STATISTICS_RAM_ECC    |
1762                                         EX_MURAM_ECC                 |
1763                                         EX_BMI_DISPATCH_RAM_ECC      |
1764                                         EX_QMI_DOUBLE_ECC            |
1765                                         EX_QMI_SINGLE_ECC);
1766
1767         /* Read FMan revision for future use*/
1768         fman_get_revision(fman, &fman->state->rev_info);
1769
1770         err = fill_soc_specific_params(fman->state);
1771         if (err)
1772                 goto err_fm_soc_specific;
1773
1774         /* FM_AID_MODE_NO_TNUM_SW005 Errata workaround */
1775         if (fman->state->rev_info.major >= 6)
1776                 fman->cfg->dma_aid_mode = FMAN_DMA_AID_OUT_PORT_ID;
1777
1778         fman->cfg->qmi_def_tnums_thresh = fman->state->qmi_def_tnums_thresh;
1779
1780         fman->state->total_num_of_tasks =
1781         (u8)DFLT_TOTAL_NUM_OF_TASKS(fman->state->rev_info.major,
1782                                     fman->state->rev_info.minor,
1783                                     fman->state->bmi_max_num_of_tasks);
1784
1785         if (fman->state->rev_info.major < 6) {
1786                 fman->cfg->dma_comm_qtsh_clr_emer =
1787                 (u8)DFLT_DMA_COMM_Q_LOW(fman->state->rev_info.major,
1788                                         fman->state->dma_thresh_max_commq);
1789
1790                 fman->cfg->dma_comm_qtsh_asrt_emer =
1791                 (u8)DFLT_DMA_COMM_Q_HIGH(fman->state->rev_info.major,
1792                                          fman->state->dma_thresh_max_commq);
1793
1794                 fman->cfg->dma_cam_num_of_entries =
1795                 DFLT_DMA_CAM_NUM_OF_ENTRIES(fman->state->rev_info.major);
1796
1797                 fman->cfg->dma_read_buf_tsh_clr_emer =
1798                 DFLT_DMA_READ_INT_BUF_LOW(fman->state->dma_thresh_max_buf);
1799
1800                 fman->cfg->dma_read_buf_tsh_asrt_emer =
1801                 DFLT_DMA_READ_INT_BUF_HIGH(fman->state->dma_thresh_max_buf);
1802
1803                 fman->cfg->dma_write_buf_tsh_clr_emer =
1804                 DFLT_DMA_WRITE_INT_BUF_LOW(fman->state->dma_thresh_max_buf);
1805
1806                 fman->cfg->dma_write_buf_tsh_asrt_emer =
1807                 DFLT_DMA_WRITE_INT_BUF_HIGH(fman->state->dma_thresh_max_buf);
1808
1809                 fman->cfg->dma_axi_dbg_num_of_beats =
1810                 DFLT_AXI_DBG_NUM_OF_BEATS;
1811         }
1812
1813         return 0;
1814
1815 err_fm_soc_specific:
1816         kfree(fman->cfg);
1817 err_fm_drv:
1818         kfree(fman->state);
1819 err_fm_state:
1820         kfree(fman);
1821         return -EINVAL;
1822 }
1823
1824 static int fman_reset(struct fman *fman)
1825 {
1826         u32 count;
1827         int err = 0;
1828
1829         if (fman->state->rev_info.major < 6) {
1830                 iowrite32be(FPM_RSTC_FM_RESET, &fman->fpm_regs->fm_rstc);
1831                 /* Wait for reset completion */
1832                 count = 100;
1833                 do {
1834                         udelay(1);
1835                 } while (((ioread32be(&fman->fpm_regs->fm_rstc)) &
1836                          FPM_RSTC_FM_RESET) && --count);
1837                 if (count == 0)
1838                         err = -EBUSY;
1839
1840                 goto _return;
1841         } else {
1842 #ifdef CONFIG_PPC
1843                 struct device_node *guts_node;
1844                 struct ccsr_guts __iomem *guts_regs;
1845                 u32 devdisr2, reg;
1846
1847                 /* Errata A007273 */
1848                 guts_node =
1849                         of_find_compatible_node(NULL, NULL,
1850                                                 "fsl,qoriq-device-config-2.0");
1851                 if (!guts_node) {
1852                         dev_err(fman->dev, "%s: Couldn't find guts node\n",
1853                                 __func__);
1854                         goto guts_node;
1855                 }
1856
1857                 guts_regs = of_iomap(guts_node, 0);
1858                 if (!guts_regs) {
1859                         dev_err(fman->dev, "%s: Couldn't map %pOF regs\n",
1860                                 __func__, guts_node);
1861                         goto guts_regs;
1862                 }
1863 #define FMAN1_ALL_MACS_MASK     0xFCC00000
1864 #define FMAN2_ALL_MACS_MASK     0x000FCC00
1865                 /* Read current state */
1866                 devdisr2 = ioread32be(&guts_regs->devdisr2);
1867                 if (fman->dts_params.id == 0)
1868                         reg = devdisr2 & ~FMAN1_ALL_MACS_MASK;
1869                 else
1870                         reg = devdisr2 & ~FMAN2_ALL_MACS_MASK;
1871
1872                 /* Enable all MACs */
1873                 iowrite32be(reg, &guts_regs->devdisr2);
1874 #endif
1875
1876                 /* Perform FMan reset */
1877                 iowrite32be(FPM_RSTC_FM_RESET, &fman->fpm_regs->fm_rstc);
1878
1879                 /* Wait for reset completion */
1880                 count = 100;
1881                 do {
1882                         udelay(1);
1883                 } while (((ioread32be(&fman->fpm_regs->fm_rstc)) &
1884                          FPM_RSTC_FM_RESET) && --count);
1885                 if (count == 0) {
1886 #ifdef CONFIG_PPC
1887                         iounmap(guts_regs);
1888                         of_node_put(guts_node);
1889 #endif
1890                         err = -EBUSY;
1891                         goto _return;
1892                 }
1893 #ifdef CONFIG_PPC
1894
1895                 /* Restore devdisr2 value */
1896                 iowrite32be(devdisr2, &guts_regs->devdisr2);
1897
1898                 iounmap(guts_regs);
1899                 of_node_put(guts_node);
1900 #endif
1901
1902                 goto _return;
1903
1904 #ifdef CONFIG_PPC
1905 guts_regs:
1906                 of_node_put(guts_node);
1907 guts_node:
1908                 dev_dbg(fman->dev, "%s: Didn't perform FManV3 reset due to Errata A007273!\n",
1909                         __func__);
1910 #endif
1911         }
1912 _return:
1913         return err;
1914 }
1915
1916 static int fman_init(struct fman *fman)
1917 {
1918         struct fman_cfg *cfg = NULL;
1919         int err = 0, i, count;
1920
1921         if (is_init_done(fman->cfg))
1922                 return -EINVAL;
1923
1924         fman->state->count1_micro_bit = FM_TIMESTAMP_1_USEC_BIT;
1925
1926         cfg = fman->cfg;
1927
1928         /* clear revision-dependent non existing exception */
1929         if (fman->state->rev_info.major < 6)
1930                 fman->state->exceptions &= ~FMAN_EX_BMI_DISPATCH_RAM_ECC;
1931
1932         if (fman->state->rev_info.major >= 6)
1933                 fman->state->exceptions &= ~FMAN_EX_QMI_SINGLE_ECC;
1934
1935         /* clear CPG */
1936         memset_io((void __iomem *)(fman->base_addr + CGP_OFFSET), 0,
1937                   fman->state->fm_port_num_of_cg);
1938
1939         /* Save LIODN info before FMan reset
1940          * Skipping non-existent port 0 (i = 1)
1941          */
1942         for (i = 1; i < FMAN_LIODN_TBL; i++) {
1943                 u32 liodn_base;
1944
1945                 fman->liodn_offset[i] =
1946                         ioread32be(&fman->bmi_regs->fmbm_spliodn[i - 1]);
1947                 if (!IS_ENABLED(CONFIG_FSL_PAMU))
1948                         continue;
1949                 liodn_base = ioread32be(&fman->dma_regs->fmdmplr[i / 2]);
1950                 if (i % 2) {
1951                         /* FMDM_PLR LSB holds LIODN base for odd ports */
1952                         liodn_base &= DMA_LIODN_BASE_MASK;
1953                 } else {
1954                         /* FMDM_PLR MSB holds LIODN base for even ports */
1955                         liodn_base >>= DMA_LIODN_SHIFT;
1956                         liodn_base &= DMA_LIODN_BASE_MASK;
1957                 }
1958                 fman->liodn_base[i] = liodn_base;
1959         }
1960
1961         err = fman_reset(fman);
1962         if (err)
1963                 return err;
1964
1965         if (ioread32be(&fman->qmi_regs->fmqm_gs) & QMI_GS_HALT_NOT_BUSY) {
1966                 resume(fman->fpm_regs);
1967                 /* Wait until QMI is not in halt not busy state */
1968                 count = 100;
1969                 do {
1970                         udelay(1);
1971                 } while (((ioread32be(&fman->qmi_regs->fmqm_gs)) &
1972                          QMI_GS_HALT_NOT_BUSY) && --count);
1973                 if (count == 0)
1974                         dev_warn(fman->dev, "%s: QMI is in halt not busy state\n",
1975                                  __func__);
1976         }
1977
1978         if (clear_iram(fman) != 0)
1979                 return -EINVAL;
1980
1981         cfg->exceptions = fman->state->exceptions;
1982
1983         /* Init DMA Registers */
1984
1985         err = dma_init(fman);
1986         if (err != 0) {
1987                 free_init_resources(fman);
1988                 return err;
1989         }
1990
1991         /* Init FPM Registers */
1992         fpm_init(fman->fpm_regs, fman->cfg);
1993
1994         /* define common resources */
1995         /* allocate MURAM for FIFO according to total size */
1996         fman->fifo_offset = fman_muram_alloc(fman->muram,
1997                                              fman->state->total_fifo_size);
1998         if (IS_ERR_VALUE(fman->fifo_offset)) {
1999                 free_init_resources(fman);
2000                 dev_err(fman->dev, "%s: MURAM alloc for BMI FIFO failed\n",
2001                         __func__);
2002                 return -ENOMEM;
2003         }
2004
2005         cfg->fifo_base_addr = fman->fifo_offset;
2006         cfg->total_fifo_size = fman->state->total_fifo_size;
2007         cfg->total_num_of_tasks = fman->state->total_num_of_tasks;
2008         cfg->clk_freq = fman->state->fm_clk_freq;
2009
2010         /* Init BMI Registers */
2011         bmi_init(fman->bmi_regs, fman->cfg);
2012
2013         /* Init QMI Registers */
2014         qmi_init(fman->qmi_regs, fman->cfg);
2015
2016         /* Init HW Parser */
2017         hwp_init(fman->hwp_regs);
2018
2019         /* Init KeyGen */
2020         fman->keygen = keygen_init(fman->kg_regs);
2021         if (!fman->keygen)
2022                 return -EINVAL;
2023
2024         err = enable(fman, cfg);
2025         if (err != 0)
2026                 return err;
2027
2028         enable_time_stamp(fman);
2029
2030         kfree(fman->cfg);
2031         fman->cfg = NULL;
2032
2033         return 0;
2034 }
2035
2036 static int fman_set_exception(struct fman *fman,
2037                               enum fman_exceptions exception, bool enable)
2038 {
2039         u32 bit_mask = 0;
2040
2041         if (!is_init_done(fman->cfg))
2042                 return -EINVAL;
2043
2044         bit_mask = get_exception_flag(exception);
2045         if (bit_mask) {
2046                 if (enable)
2047                         fman->state->exceptions |= bit_mask;
2048                 else
2049                         fman->state->exceptions &= ~bit_mask;
2050         } else {
2051                 dev_err(fman->dev, "%s: Undefined exception (%d)\n",
2052                         __func__, exception);
2053                 return -EINVAL;
2054         }
2055
2056         return set_exception(fman, exception, enable);
2057 }
2058
2059 /**
2060  * fman_register_intr
2061  * @fman:       A Pointer to FMan device
2062  * @mod:        Calling module
2063  * @mod_id:     Module id (if more than 1 exists, '0' if not)
2064  * @intr_type:  Interrupt type (error/normal) selection.
2065  * @f_isr:      The interrupt service routine.
2066  * @h_src_arg:  Argument to be passed to f_isr.
2067  *
2068  * Used to register an event handler to be processed by FMan
2069  *
2070  * Return: 0 on success; Error code otherwise.
2071  */
2072 void fman_register_intr(struct fman *fman, enum fman_event_modules module,
2073                         u8 mod_id, enum fman_intr_type intr_type,
2074                         void (*isr_cb)(void *src_arg), void *src_arg)
2075 {
2076         int event = 0;
2077
2078         event = get_module_event(module, mod_id, intr_type);
2079         WARN_ON(event >= FMAN_EV_CNT);
2080
2081         /* register in local FM structure */
2082         fman->intr_mng[event].isr_cb = isr_cb;
2083         fman->intr_mng[event].src_handle = src_arg;
2084 }
2085 EXPORT_SYMBOL(fman_register_intr);
2086
2087 /**
2088  * fman_unregister_intr
2089  * @fman:       A Pointer to FMan device
2090  * @mod:        Calling module
2091  * @mod_id:     Module id (if more than 1 exists, '0' if not)
2092  * @intr_type:  Interrupt type (error/normal) selection.
2093  *
2094  * Used to unregister an event handler to be processed by FMan
2095  *
2096  * Return: 0 on success; Error code otherwise.
2097  */
2098 void fman_unregister_intr(struct fman *fman, enum fman_event_modules module,
2099                           u8 mod_id, enum fman_intr_type intr_type)
2100 {
2101         int event = 0;
2102
2103         event = get_module_event(module, mod_id, intr_type);
2104         WARN_ON(event >= FMAN_EV_CNT);
2105
2106         fman->intr_mng[event].isr_cb = NULL;
2107         fman->intr_mng[event].src_handle = NULL;
2108 }
2109 EXPORT_SYMBOL(fman_unregister_intr);
2110
2111 /**
2112  * fman_set_port_params
2113  * @fman:               A Pointer to FMan device
2114  * @port_params:        Port parameters
2115  *
2116  * Used by FMan Port to pass parameters to the FMan
2117  *
2118  * Return: 0 on success; Error code otherwise.
2119  */
2120 int fman_set_port_params(struct fman *fman,
2121                          struct fman_port_init_params *port_params)
2122 {
2123         int err;
2124         unsigned long flags;
2125         u8 port_id = port_params->port_id, mac_id;
2126
2127         spin_lock_irqsave(&fman->spinlock, flags);
2128
2129         err = set_num_of_tasks(fman, port_params->port_id,
2130                                &port_params->num_of_tasks,
2131                                &port_params->num_of_extra_tasks);
2132         if (err)
2133                 goto return_err;
2134
2135         /* TX Ports */
2136         if (port_params->port_type != FMAN_PORT_TYPE_RX) {
2137                 u32 enq_th, deq_th, reg;
2138
2139                 /* update qmi ENQ/DEQ threshold */
2140                 fman->state->accumulated_num_of_deq_tnums +=
2141                         port_params->deq_pipeline_depth;
2142                 enq_th = (ioread32be(&fman->qmi_regs->fmqm_gc) &
2143                           QMI_CFG_ENQ_MASK) >> QMI_CFG_ENQ_SHIFT;
2144                 /* if enq_th is too big, we reduce it to the max value
2145                  * that is still 0
2146                  */
2147                 if (enq_th >= (fman->state->qmi_max_num_of_tnums -
2148                     fman->state->accumulated_num_of_deq_tnums)) {
2149                         enq_th =
2150                         fman->state->qmi_max_num_of_tnums -
2151                         fman->state->accumulated_num_of_deq_tnums - 1;
2152
2153                         reg = ioread32be(&fman->qmi_regs->fmqm_gc);
2154                         reg &= ~QMI_CFG_ENQ_MASK;
2155                         reg |= (enq_th << QMI_CFG_ENQ_SHIFT);
2156                         iowrite32be(reg, &fman->qmi_regs->fmqm_gc);
2157                 }
2158
2159                 deq_th = ioread32be(&fman->qmi_regs->fmqm_gc) &
2160                                     QMI_CFG_DEQ_MASK;
2161                 /* if deq_th is too small, we enlarge it to the min
2162                  * value that is still 0.
2163                  * depTh may not be larger than 63
2164                  * (fman->state->qmi_max_num_of_tnums-1).
2165                  */
2166                 if ((deq_th <= fman->state->accumulated_num_of_deq_tnums) &&
2167                     (deq_th < fman->state->qmi_max_num_of_tnums - 1)) {
2168                         deq_th = fman->state->accumulated_num_of_deq_tnums + 1;
2169                         reg = ioread32be(&fman->qmi_regs->fmqm_gc);
2170                         reg &= ~QMI_CFG_DEQ_MASK;
2171                         reg |= deq_th;
2172                         iowrite32be(reg, &fman->qmi_regs->fmqm_gc);
2173                 }
2174         }
2175
2176         err = set_size_of_fifo(fman, port_params->port_id,
2177                                &port_params->size_of_fifo,
2178                                &port_params->extra_size_of_fifo);
2179         if (err)
2180                 goto return_err;
2181
2182         err = set_num_of_open_dmas(fman, port_params->port_id,
2183                                    &port_params->num_of_open_dmas,
2184                                    &port_params->num_of_extra_open_dmas);
2185         if (err)
2186                 goto return_err;
2187
2188         set_port_liodn(fman, port_id, fman->liodn_base[port_id],
2189                        fman->liodn_offset[port_id]);
2190
2191         if (fman->state->rev_info.major < 6)
2192                 set_port_order_restoration(fman->fpm_regs, port_id);
2193
2194         mac_id = hw_port_id_to_sw_port_id(fman->state->rev_info.major, port_id);
2195
2196         if (port_params->max_frame_length >= fman->state->mac_mfl[mac_id]) {
2197                 fman->state->port_mfl[mac_id] = port_params->max_frame_length;
2198         } else {
2199                 dev_warn(fman->dev, "%s: Port (%d) max_frame_length is smaller than MAC (%d) current MTU\n",
2200                          __func__, port_id, mac_id);
2201                 err = -EINVAL;
2202                 goto return_err;
2203         }
2204
2205         spin_unlock_irqrestore(&fman->spinlock, flags);
2206
2207         return 0;
2208
2209 return_err:
2210         spin_unlock_irqrestore(&fman->spinlock, flags);
2211         return err;
2212 }
2213 EXPORT_SYMBOL(fman_set_port_params);
2214
2215 /**
2216  * fman_reset_mac
2217  * @fman:       A Pointer to FMan device
2218  * @mac_id:     MAC id to be reset
2219  *
2220  * Reset a specific MAC
2221  *
2222  * Return: 0 on success; Error code otherwise.
2223  */
2224 int fman_reset_mac(struct fman *fman, u8 mac_id)
2225 {
2226         struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs;
2227         u32 msk, timeout = 100;
2228
2229         if (fman->state->rev_info.major >= 6) {
2230                 dev_err(fman->dev, "%s: FMan MAC reset no available for FMan V3!\n",
2231                         __func__);
2232                 return -EINVAL;
2233         }
2234
2235         /* Get the relevant bit mask */
2236         switch (mac_id) {
2237         case 0:
2238                 msk = FPM_RSTC_MAC0_RESET;
2239                 break;
2240         case 1:
2241                 msk = FPM_RSTC_MAC1_RESET;
2242                 break;
2243         case 2:
2244                 msk = FPM_RSTC_MAC2_RESET;
2245                 break;
2246         case 3:
2247                 msk = FPM_RSTC_MAC3_RESET;
2248                 break;
2249         case 4:
2250                 msk = FPM_RSTC_MAC4_RESET;
2251                 break;
2252         case 5:
2253                 msk = FPM_RSTC_MAC5_RESET;
2254                 break;
2255         case 6:
2256                 msk = FPM_RSTC_MAC6_RESET;
2257                 break;
2258         case 7:
2259                 msk = FPM_RSTC_MAC7_RESET;
2260                 break;
2261         case 8:
2262                 msk = FPM_RSTC_MAC8_RESET;
2263                 break;
2264         case 9:
2265                 msk = FPM_RSTC_MAC9_RESET;
2266                 break;
2267         default:
2268                 dev_warn(fman->dev, "%s: Illegal MAC Id [%d]\n",
2269                          __func__, mac_id);
2270                 return -EINVAL;
2271         }
2272
2273         /* reset */
2274         iowrite32be(msk, &fpm_rg->fm_rstc);
2275         while ((ioread32be(&fpm_rg->fm_rstc) & msk) && --timeout)
2276                 udelay(10);
2277
2278         if (!timeout)
2279                 return -EIO;
2280
2281         return 0;
2282 }
2283 EXPORT_SYMBOL(fman_reset_mac);
2284
2285 /**
2286  * fman_set_mac_max_frame
2287  * @fman:       A Pointer to FMan device
2288  * @mac_id:     MAC id
2289  * @mfl:        Maximum frame length
2290  *
2291  * Set maximum frame length of specific MAC in FMan driver
2292  *
2293  * Return: 0 on success; Error code otherwise.
2294  */
2295 int fman_set_mac_max_frame(struct fman *fman, u8 mac_id, u16 mfl)
2296 {
2297         /* if port is already initialized, check that MaxFrameLength is smaller
2298          * or equal to the port's max
2299          */
2300         if ((!fman->state->port_mfl[mac_id]) ||
2301             (mfl <= fman->state->port_mfl[mac_id])) {
2302                 fman->state->mac_mfl[mac_id] = mfl;
2303         } else {
2304                 dev_warn(fman->dev, "%s: MAC max_frame_length is larger than Port max_frame_length\n",
2305                          __func__);
2306                 return -EINVAL;
2307         }
2308         return 0;
2309 }
2310 EXPORT_SYMBOL(fman_set_mac_max_frame);
2311
2312 /**
2313  * fman_get_clock_freq
2314  * @fman:       A Pointer to FMan device
2315  *
2316  * Get FMan clock frequency
2317  *
2318  * Return: FMan clock frequency
2319  */
2320 u16 fman_get_clock_freq(struct fman *fman)
2321 {
2322         return fman->state->fm_clk_freq;
2323 }
2324
2325 /**
2326  * fman_get_bmi_max_fifo_size
2327  * @fman:       A Pointer to FMan device
2328  *
2329  * Get FMan maximum FIFO size
2330  *
2331  * Return: FMan Maximum FIFO size
2332  */
2333 u32 fman_get_bmi_max_fifo_size(struct fman *fman)
2334 {
2335         return fman->state->bmi_max_fifo_size;
2336 }
2337 EXPORT_SYMBOL(fman_get_bmi_max_fifo_size);
2338
2339 /**
2340  * fman_get_revision
2341  * @fman                - Pointer to the FMan module
2342  * @rev_info            - A structure of revision information parameters.
2343  *
2344  * Returns the FM revision
2345  *
2346  * Allowed only following fman_init().
2347  *
2348  * Return: 0 on success; Error code otherwise.
2349  */
2350 void fman_get_revision(struct fman *fman, struct fman_rev_info *rev_info)
2351 {
2352         u32 tmp;
2353
2354         tmp = ioread32be(&fman->fpm_regs->fm_ip_rev_1);
2355         rev_info->major = (u8)((tmp & FPM_REV1_MAJOR_MASK) >>
2356                                 FPM_REV1_MAJOR_SHIFT);
2357         rev_info->minor = tmp & FPM_REV1_MINOR_MASK;
2358 }
2359 EXPORT_SYMBOL(fman_get_revision);
2360
2361 /**
2362  * fman_get_qman_channel_id
2363  * @fman:       A Pointer to FMan device
2364  * @port_id:    Port id
2365  *
2366  * Get QMan channel ID associated to the Port id
2367  *
2368  * Return: QMan channel ID
2369  */
2370 u32 fman_get_qman_channel_id(struct fman *fman, u32 port_id)
2371 {
2372         int i;
2373
2374         if (fman->state->rev_info.major >= 6) {
2375                 static const u32 port_ids[] = {
2376                         0x30, 0x31, 0x28, 0x29, 0x2a, 0x2b,
2377                         0x2c, 0x2d, 0x2, 0x3, 0x4, 0x5, 0x7, 0x7
2378                 };
2379
2380                 for (i = 0; i < fman->state->num_of_qman_channels; i++) {
2381                         if (port_ids[i] == port_id)
2382                                 break;
2383                 }
2384         } else {
2385                 static const u32 port_ids[] = {
2386                         0x30, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x1,
2387                         0x2, 0x3, 0x4, 0x5, 0x7, 0x7
2388                 };
2389
2390                 for (i = 0; i < fman->state->num_of_qman_channels; i++) {
2391                         if (port_ids[i] == port_id)
2392                                 break;
2393                 }
2394         }
2395
2396         if (i == fman->state->num_of_qman_channels)
2397                 return 0;
2398
2399         return fman->state->qman_channel_base + i;
2400 }
2401 EXPORT_SYMBOL(fman_get_qman_channel_id);
2402
2403 /**
2404  * fman_get_mem_region
2405  * @fman:       A Pointer to FMan device
2406  *
2407  * Get FMan memory region
2408  *
2409  * Return: A structure with FMan memory region information
2410  */
2411 struct resource *fman_get_mem_region(struct fman *fman)
2412 {
2413         return fman->state->res;
2414 }
2415 EXPORT_SYMBOL(fman_get_mem_region);
2416
2417 /* Bootargs defines */
2418 /* Extra headroom for RX buffers - Default, min and max */
2419 #define FSL_FM_RX_EXTRA_HEADROOM        64
2420 #define FSL_FM_RX_EXTRA_HEADROOM_MIN    16
2421 #define FSL_FM_RX_EXTRA_HEADROOM_MAX    384
2422
2423 /* Maximum frame length */
2424 #define FSL_FM_MAX_FRAME_SIZE                   1522
2425 #define FSL_FM_MAX_POSSIBLE_FRAME_SIZE          9600
2426 #define FSL_FM_MIN_POSSIBLE_FRAME_SIZE          64
2427
2428 /* Extra headroom for Rx buffers.
2429  * FMan is instructed to allocate, on the Rx path, this amount of
2430  * space at the beginning of a data buffer, beside the DPA private
2431  * data area and the IC fields.
2432  * Does not impact Tx buffer layout.
2433  * Configurable from bootargs. 64 by default, it's needed on
2434  * particular forwarding scenarios that add extra headers to the
2435  * forwarded frame.
2436  */
2437 static int fsl_fm_rx_extra_headroom = FSL_FM_RX_EXTRA_HEADROOM;
2438 module_param(fsl_fm_rx_extra_headroom, int, 0);
2439 MODULE_PARM_DESC(fsl_fm_rx_extra_headroom, "Extra headroom for Rx buffers");
2440
2441 /* Max frame size, across all interfaces.
2442  * Configurable from bootargs, to avoid allocating oversized (socket)
2443  * buffers when not using jumbo frames.
2444  * Must be large enough to accommodate the network MTU, but small enough
2445  * to avoid wasting skb memory.
2446  */
2447 static int fsl_fm_max_frm = FSL_FM_MAX_FRAME_SIZE;
2448 module_param(fsl_fm_max_frm, int, 0);
2449 MODULE_PARM_DESC(fsl_fm_max_frm, "Maximum frame size, across all interfaces");
2450
2451 /**
2452  * fman_get_max_frm
2453  *
2454  * Return: Max frame length configured in the FM driver
2455  */
2456 u16 fman_get_max_frm(void)
2457 {
2458         static bool fm_check_mfl;
2459
2460         if (!fm_check_mfl) {
2461                 if (fsl_fm_max_frm > FSL_FM_MAX_POSSIBLE_FRAME_SIZE ||
2462                     fsl_fm_max_frm < FSL_FM_MIN_POSSIBLE_FRAME_SIZE) {
2463                         pr_warn("Invalid fsl_fm_max_frm value (%d) in bootargs, valid range is %d-%d. Falling back to the default (%d)\n",
2464                                 fsl_fm_max_frm,
2465                                 FSL_FM_MIN_POSSIBLE_FRAME_SIZE,
2466                                 FSL_FM_MAX_POSSIBLE_FRAME_SIZE,
2467                                 FSL_FM_MAX_FRAME_SIZE);
2468                         fsl_fm_max_frm = FSL_FM_MAX_FRAME_SIZE;
2469                 }
2470                 fm_check_mfl = true;
2471         }
2472
2473         return fsl_fm_max_frm;
2474 }
2475 EXPORT_SYMBOL(fman_get_max_frm);
2476
2477 /**
2478  * fman_get_rx_extra_headroom
2479  *
2480  * Return: Extra headroom size configured in the FM driver
2481  */
2482 int fman_get_rx_extra_headroom(void)
2483 {
2484         static bool fm_check_rx_extra_headroom;
2485
2486         if (!fm_check_rx_extra_headroom) {
2487                 if (fsl_fm_rx_extra_headroom > FSL_FM_RX_EXTRA_HEADROOM_MAX ||
2488                     fsl_fm_rx_extra_headroom < FSL_FM_RX_EXTRA_HEADROOM_MIN) {
2489                         pr_warn("Invalid fsl_fm_rx_extra_headroom value (%d) in bootargs, valid range is %d-%d. Falling back to the default (%d)\n",
2490                                 fsl_fm_rx_extra_headroom,
2491                                 FSL_FM_RX_EXTRA_HEADROOM_MIN,
2492                                 FSL_FM_RX_EXTRA_HEADROOM_MAX,
2493                                 FSL_FM_RX_EXTRA_HEADROOM);
2494                         fsl_fm_rx_extra_headroom = FSL_FM_RX_EXTRA_HEADROOM;
2495                 }
2496
2497                 fm_check_rx_extra_headroom = true;
2498                 fsl_fm_rx_extra_headroom = ALIGN(fsl_fm_rx_extra_headroom, 16);
2499         }
2500
2501         return fsl_fm_rx_extra_headroom;
2502 }
2503 EXPORT_SYMBOL(fman_get_rx_extra_headroom);
2504
2505 /**
2506  * fman_bind
2507  * @dev:        FMan OF device pointer
2508  *
2509  * Bind to a specific FMan device.
2510  *
2511  * Allowed only after the port was created.
2512  *
2513  * Return: A pointer to the FMan device
2514  */
2515 struct fman *fman_bind(struct device *fm_dev)
2516 {
2517         return (struct fman *)(dev_get_drvdata(get_device(fm_dev)));
2518 }
2519 EXPORT_SYMBOL(fman_bind);
2520
2521 static irqreturn_t fman_err_irq(int irq, void *handle)
2522 {
2523         struct fman *fman = (struct fman *)handle;
2524         u32 pending;
2525         struct fman_fpm_regs __iomem *fpm_rg;
2526         irqreturn_t single_ret, ret = IRQ_NONE;
2527
2528         if (!is_init_done(fman->cfg))
2529                 return IRQ_NONE;
2530
2531         fpm_rg = fman->fpm_regs;
2532
2533         /* error interrupts */
2534         pending = ioread32be(&fpm_rg->fm_epi);
2535         if (!pending)
2536                 return IRQ_NONE;
2537
2538         if (pending & ERR_INTR_EN_BMI) {
2539                 single_ret = bmi_err_event(fman);
2540                 if (single_ret == IRQ_HANDLED)
2541                         ret = IRQ_HANDLED;
2542         }
2543         if (pending & ERR_INTR_EN_QMI) {
2544                 single_ret = qmi_err_event(fman);
2545                 if (single_ret == IRQ_HANDLED)
2546                         ret = IRQ_HANDLED;
2547         }
2548         if (pending & ERR_INTR_EN_FPM) {
2549                 single_ret = fpm_err_event(fman);
2550                 if (single_ret == IRQ_HANDLED)
2551                         ret = IRQ_HANDLED;
2552         }
2553         if (pending & ERR_INTR_EN_DMA) {
2554                 single_ret = dma_err_event(fman);
2555                 if (single_ret == IRQ_HANDLED)
2556                         ret = IRQ_HANDLED;
2557         }
2558         if (pending & ERR_INTR_EN_MURAM) {
2559                 single_ret = muram_err_intr(fman);
2560                 if (single_ret == IRQ_HANDLED)
2561                         ret = IRQ_HANDLED;
2562         }
2563
2564         /* MAC error interrupts */
2565         if (pending & ERR_INTR_EN_MAC0) {
2566                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 0);
2567                 if (single_ret == IRQ_HANDLED)
2568                         ret = IRQ_HANDLED;
2569         }
2570         if (pending & ERR_INTR_EN_MAC1) {
2571                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 1);
2572                 if (single_ret == IRQ_HANDLED)
2573                         ret = IRQ_HANDLED;
2574         }
2575         if (pending & ERR_INTR_EN_MAC2) {
2576                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 2);
2577                 if (single_ret == IRQ_HANDLED)
2578                         ret = IRQ_HANDLED;
2579         }
2580         if (pending & ERR_INTR_EN_MAC3) {
2581                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 3);
2582                 if (single_ret == IRQ_HANDLED)
2583                         ret = IRQ_HANDLED;
2584         }
2585         if (pending & ERR_INTR_EN_MAC4) {
2586                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 4);
2587                 if (single_ret == IRQ_HANDLED)
2588                         ret = IRQ_HANDLED;
2589         }
2590         if (pending & ERR_INTR_EN_MAC5) {
2591                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 5);
2592                 if (single_ret == IRQ_HANDLED)
2593                         ret = IRQ_HANDLED;
2594         }
2595         if (pending & ERR_INTR_EN_MAC6) {
2596                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 6);
2597                 if (single_ret == IRQ_HANDLED)
2598                         ret = IRQ_HANDLED;
2599         }
2600         if (pending & ERR_INTR_EN_MAC7) {
2601                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 7);
2602                 if (single_ret == IRQ_HANDLED)
2603                         ret = IRQ_HANDLED;
2604         }
2605         if (pending & ERR_INTR_EN_MAC8) {
2606                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 8);
2607                 if (single_ret == IRQ_HANDLED)
2608                         ret = IRQ_HANDLED;
2609         }
2610         if (pending & ERR_INTR_EN_MAC9) {
2611                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 9);
2612                 if (single_ret == IRQ_HANDLED)
2613                         ret = IRQ_HANDLED;
2614         }
2615
2616         return ret;
2617 }
2618
2619 static irqreturn_t fman_irq(int irq, void *handle)
2620 {
2621         struct fman *fman = (struct fman *)handle;
2622         u32 pending;
2623         struct fman_fpm_regs __iomem *fpm_rg;
2624         irqreturn_t single_ret, ret = IRQ_NONE;
2625
2626         if (!is_init_done(fman->cfg))
2627                 return IRQ_NONE;
2628
2629         fpm_rg = fman->fpm_regs;
2630
2631         /* normal interrupts */
2632         pending = ioread32be(&fpm_rg->fm_npi);
2633         if (!pending)
2634                 return IRQ_NONE;
2635
2636         if (pending & INTR_EN_QMI) {
2637                 single_ret = qmi_event(fman);
2638                 if (single_ret == IRQ_HANDLED)
2639                         ret = IRQ_HANDLED;
2640         }
2641
2642         /* MAC interrupts */
2643         if (pending & INTR_EN_MAC0) {
2644                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 0);
2645                 if (single_ret == IRQ_HANDLED)
2646                         ret = IRQ_HANDLED;
2647         }
2648         if (pending & INTR_EN_MAC1) {
2649                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 1);
2650                 if (single_ret == IRQ_HANDLED)
2651                         ret = IRQ_HANDLED;
2652         }
2653         if (pending & INTR_EN_MAC2) {
2654                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 2);
2655                 if (single_ret == IRQ_HANDLED)
2656                         ret = IRQ_HANDLED;
2657         }
2658         if (pending & INTR_EN_MAC3) {
2659                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 3);
2660                 if (single_ret == IRQ_HANDLED)
2661                         ret = IRQ_HANDLED;
2662         }
2663         if (pending & INTR_EN_MAC4) {
2664                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 4);
2665                 if (single_ret == IRQ_HANDLED)
2666                         ret = IRQ_HANDLED;
2667         }
2668         if (pending & INTR_EN_MAC5) {
2669                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 5);
2670                 if (single_ret == IRQ_HANDLED)
2671                         ret = IRQ_HANDLED;
2672         }
2673         if (pending & INTR_EN_MAC6) {
2674                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 6);
2675                 if (single_ret == IRQ_HANDLED)
2676                         ret = IRQ_HANDLED;
2677         }
2678         if (pending & INTR_EN_MAC7) {
2679                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 7);
2680                 if (single_ret == IRQ_HANDLED)
2681                         ret = IRQ_HANDLED;
2682         }
2683         if (pending & INTR_EN_MAC8) {
2684                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 8);
2685                 if (single_ret == IRQ_HANDLED)
2686                         ret = IRQ_HANDLED;
2687         }
2688         if (pending & INTR_EN_MAC9) {
2689                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 9);
2690                 if (single_ret == IRQ_HANDLED)
2691                         ret = IRQ_HANDLED;
2692         }
2693
2694         return ret;
2695 }
2696
2697 static const struct of_device_id fman_muram_match[] = {
2698         {
2699                 .compatible = "fsl,fman-muram"},
2700         {}
2701 };
2702 MODULE_DEVICE_TABLE(of, fman_muram_match);
2703
2704 static struct fman *read_dts_node(struct platform_device *of_dev)
2705 {
2706         struct fman *fman;
2707         struct device_node *fm_node, *muram_node;
2708         struct resource *res;
2709         u32 val, range[2];
2710         int err, irq;
2711         struct clk *clk;
2712         u32 clk_rate;
2713         phys_addr_t phys_base_addr;
2714         resource_size_t mem_size;
2715
2716         fman = kzalloc(sizeof(*fman), GFP_KERNEL);
2717         if (!fman)
2718                 return NULL;
2719
2720         fm_node = of_node_get(of_dev->dev.of_node);
2721
2722         err = of_property_read_u32(fm_node, "cell-index", &val);
2723         if (err) {
2724                 dev_err(&of_dev->dev, "%s: failed to read cell-index for %pOF\n",
2725                         __func__, fm_node);
2726                 goto fman_node_put;
2727         }
2728         fman->dts_params.id = (u8)val;
2729
2730         /* Get the FM interrupt */
2731         res = platform_get_resource(of_dev, IORESOURCE_IRQ, 0);
2732         if (!res) {
2733                 dev_err(&of_dev->dev, "%s: Can't get FMan IRQ resource\n",
2734                         __func__);
2735                 goto fman_node_put;
2736         }
2737         irq = res->start;
2738
2739         /* Get the FM error interrupt */
2740         res = platform_get_resource(of_dev, IORESOURCE_IRQ, 1);
2741         if (!res) {
2742                 dev_err(&of_dev->dev, "%s: Can't get FMan Error IRQ resource\n",
2743                         __func__);
2744                 goto fman_node_put;
2745         }
2746         fman->dts_params.err_irq = res->start;
2747
2748         /* Get the FM address */
2749         res = platform_get_resource(of_dev, IORESOURCE_MEM, 0);
2750         if (!res) {
2751                 dev_err(&of_dev->dev, "%s: Can't get FMan memory resource\n",
2752                         __func__);
2753                 goto fman_node_put;
2754         }
2755
2756         phys_base_addr = res->start;
2757         mem_size = resource_size(res);
2758
2759         clk = of_clk_get(fm_node, 0);
2760         if (IS_ERR(clk)) {
2761                 dev_err(&of_dev->dev, "%s: Failed to get FM%d clock structure\n",
2762                         __func__, fman->dts_params.id);
2763                 goto fman_node_put;
2764         }
2765
2766         clk_rate = clk_get_rate(clk);
2767         if (!clk_rate) {
2768                 dev_err(&of_dev->dev, "%s: Failed to determine FM%d clock rate\n",
2769                         __func__, fman->dts_params.id);
2770                 goto fman_node_put;
2771         }
2772         /* Rounding to MHz */
2773         fman->dts_params.clk_freq = DIV_ROUND_UP(clk_rate, 1000000);
2774
2775         err = of_property_read_u32_array(fm_node, "fsl,qman-channel-range",
2776                                          &range[0], 2);
2777         if (err) {
2778                 dev_err(&of_dev->dev, "%s: failed to read fsl,qman-channel-range for %pOF\n",
2779                         __func__, fm_node);
2780                 goto fman_node_put;
2781         }
2782         fman->dts_params.qman_channel_base = range[0];
2783         fman->dts_params.num_of_qman_channels = range[1];
2784
2785         /* Get the MURAM base address and size */
2786         muram_node = of_find_matching_node(fm_node, fman_muram_match);
2787         if (!muram_node) {
2788                 dev_err(&of_dev->dev, "%s: could not find MURAM node\n",
2789                         __func__);
2790                 goto fman_free;
2791         }
2792
2793         err = of_address_to_resource(muram_node, 0,
2794                                      &fman->dts_params.muram_res);
2795         if (err) {
2796                 of_node_put(muram_node);
2797                 dev_err(&of_dev->dev, "%s: of_address_to_resource() = %d\n",
2798                         __func__, err);
2799                 goto fman_free;
2800         }
2801
2802         of_node_put(muram_node);
2803
2804         err = devm_request_irq(&of_dev->dev, irq, fman_irq, IRQF_SHARED,
2805                                "fman", fman);
2806         if (err < 0) {
2807                 dev_err(&of_dev->dev, "%s: irq %d allocation failed (error = %d)\n",
2808                         __func__, irq, err);
2809                 goto fman_free;
2810         }
2811
2812         if (fman->dts_params.err_irq != 0) {
2813                 err = devm_request_irq(&of_dev->dev, fman->dts_params.err_irq,
2814                                        fman_err_irq, IRQF_SHARED,
2815                                        "fman-err", fman);
2816                 if (err < 0) {
2817                         dev_err(&of_dev->dev, "%s: irq %d allocation failed (error = %d)\n",
2818                                 __func__, fman->dts_params.err_irq, err);
2819                         goto fman_free;
2820                 }
2821         }
2822
2823         fman->dts_params.res =
2824                 devm_request_mem_region(&of_dev->dev, phys_base_addr,
2825                                         mem_size, "fman");
2826         if (!fman->dts_params.res) {
2827                 dev_err(&of_dev->dev, "%s: request_mem_region() failed\n",
2828                         __func__);
2829                 goto fman_free;
2830         }
2831
2832         fman->dts_params.base_addr =
2833                 devm_ioremap(&of_dev->dev, phys_base_addr, mem_size);
2834         if (!fman->dts_params.base_addr) {
2835                 dev_err(&of_dev->dev, "%s: devm_ioremap() failed\n", __func__);
2836                 goto fman_free;
2837         }
2838
2839         fman->dev = &of_dev->dev;
2840
2841         err = of_platform_populate(fm_node, NULL, NULL, &of_dev->dev);
2842         if (err) {
2843                 dev_err(&of_dev->dev, "%s: of_platform_populate() failed\n",
2844                         __func__);
2845                 goto fman_free;
2846         }
2847
2848         return fman;
2849
2850 fman_node_put:
2851         of_node_put(fm_node);
2852 fman_free:
2853         kfree(fman);
2854         return NULL;
2855 }
2856
2857 static int fman_probe(struct platform_device *of_dev)
2858 {
2859         struct fman *fman;
2860         struct device *dev;
2861         int err;
2862
2863         dev = &of_dev->dev;
2864
2865         fman = read_dts_node(of_dev);
2866         if (!fman)
2867                 return -EIO;
2868
2869         err = fman_config(fman);
2870         if (err) {
2871                 dev_err(dev, "%s: FMan config failed\n", __func__);
2872                 return -EINVAL;
2873         }
2874
2875         if (fman_init(fman) != 0) {
2876                 dev_err(dev, "%s: FMan init failed\n", __func__);
2877                 return -EINVAL;
2878         }
2879
2880         if (fman->dts_params.err_irq == 0) {
2881                 fman_set_exception(fman, FMAN_EX_DMA_BUS_ERROR, false);
2882                 fman_set_exception(fman, FMAN_EX_DMA_READ_ECC, false);
2883                 fman_set_exception(fman, FMAN_EX_DMA_SYSTEM_WRITE_ECC, false);
2884                 fman_set_exception(fman, FMAN_EX_DMA_FM_WRITE_ECC, false);
2885                 fman_set_exception(fman, FMAN_EX_DMA_SINGLE_PORT_ECC, false);
2886                 fman_set_exception(fman, FMAN_EX_FPM_STALL_ON_TASKS, false);
2887                 fman_set_exception(fman, FMAN_EX_FPM_SINGLE_ECC, false);
2888                 fman_set_exception(fman, FMAN_EX_FPM_DOUBLE_ECC, false);
2889                 fman_set_exception(fman, FMAN_EX_QMI_SINGLE_ECC, false);
2890                 fman_set_exception(fman, FMAN_EX_QMI_DOUBLE_ECC, false);
2891                 fman_set_exception(fman,
2892                                    FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID, false);
2893                 fman_set_exception(fman, FMAN_EX_BMI_LIST_RAM_ECC, false);
2894                 fman_set_exception(fman, FMAN_EX_BMI_STORAGE_PROFILE_ECC,
2895                                    false);
2896                 fman_set_exception(fman, FMAN_EX_BMI_STATISTICS_RAM_ECC, false);
2897                 fman_set_exception(fman, FMAN_EX_BMI_DISPATCH_RAM_ECC, false);
2898         }
2899
2900         dev_set_drvdata(dev, fman);
2901
2902         dev_dbg(dev, "FMan%d probed\n", fman->dts_params.id);
2903
2904         return 0;
2905 }
2906
2907 static const struct of_device_id fman_match[] = {
2908         {
2909                 .compatible = "fsl,fman"},
2910         {}
2911 };
2912
2913 MODULE_DEVICE_TABLE(of, fman_match);
2914
2915 static struct platform_driver fman_driver = {
2916         .driver = {
2917                 .name = "fsl-fman",
2918                 .of_match_table = fman_match,
2919         },
2920         .probe = fman_probe,
2921 };
2922
2923 static int __init fman_load(void)
2924 {
2925         int err;
2926
2927         pr_debug("FSL DPAA FMan driver\n");
2928
2929         err = platform_driver_register(&fman_driver);
2930         if (err < 0)
2931                 pr_err("Error, platform_driver_register() = %d\n", err);
2932
2933         return err;
2934 }
2935 module_init(fman_load);
2936
2937 static void __exit fman_unload(void)
2938 {
2939         platform_driver_unregister(&fman_driver);
2940 }
2941 module_exit(fman_unload);
2942
2943 MODULE_LICENSE("Dual BSD/GPL");
2944 MODULE_DESCRIPTION("Freescale DPAA Frame Manager driver");