1 // SPDX-License-Identifier: GPL-2.0
3 * Fast Ethernet Controller (ENET) PTP driver for MX6x.
5 * Copyright (C) 2012 Freescale Semiconductor, Inc.
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/string.h>
13 #include <linux/ptrace.h>
14 #include <linux/errno.h>
15 #include <linux/ioport.h>
16 #include <linux/slab.h>
17 #include <linux/interrupt.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/netdevice.h>
21 #include <linux/etherdevice.h>
22 #include <linux/skbuff.h>
23 #include <linux/spinlock.h>
24 #include <linux/workqueue.h>
25 #include <linux/bitops.h>
27 #include <linux/irq.h>
28 #include <linux/clk.h>
29 #include <linux/platform_device.h>
30 #include <linux/phy.h>
31 #include <linux/fec.h>
33 #include <linux/of_device.h>
34 #include <linux/of_gpio.h>
35 #include <linux/of_net.h>
39 /* FEC 1588 register bits */
40 #define FEC_T_CTRL_SLAVE 0x00002000
41 #define FEC_T_CTRL_CAPTURE 0x00000800
42 #define FEC_T_CTRL_RESTART 0x00000200
43 #define FEC_T_CTRL_PERIOD_RST 0x00000030
44 #define FEC_T_CTRL_PERIOD_EN 0x00000010
45 #define FEC_T_CTRL_ENABLE 0x00000001
47 #define FEC_T_INC_MASK 0x0000007f
48 #define FEC_T_INC_OFFSET 0
49 #define FEC_T_INC_CORR_MASK 0x00007f00
50 #define FEC_T_INC_CORR_OFFSET 8
52 #define FEC_T_CTRL_PINPER 0x00000080
53 #define FEC_T_TF0_MASK 0x00000001
54 #define FEC_T_TF0_OFFSET 0
55 #define FEC_T_TF1_MASK 0x00000002
56 #define FEC_T_TF1_OFFSET 1
57 #define FEC_T_TF2_MASK 0x00000004
58 #define FEC_T_TF2_OFFSET 2
59 #define FEC_T_TF3_MASK 0x00000008
60 #define FEC_T_TF3_OFFSET 3
61 #define FEC_T_TDRE_MASK 0x00000001
62 #define FEC_T_TDRE_OFFSET 0
63 #define FEC_T_TMODE_MASK 0x0000003C
64 #define FEC_T_TMODE_OFFSET 2
65 #define FEC_T_TIE_MASK 0x00000040
66 #define FEC_T_TIE_OFFSET 6
67 #define FEC_T_TF_MASK 0x00000080
68 #define FEC_T_TF_OFFSET 7
70 #define FEC_ATIME_CTRL 0x400
71 #define FEC_ATIME 0x404
72 #define FEC_ATIME_EVT_OFFSET 0x408
73 #define FEC_ATIME_EVT_PERIOD 0x40c
74 #define FEC_ATIME_CORR 0x410
75 #define FEC_ATIME_INC 0x414
76 #define FEC_TS_TIMESTAMP 0x418
78 #define FEC_TGSR 0x604
79 #define FEC_TCSR(n) (0x608 + n * 0x08)
80 #define FEC_TCCR(n) (0x60C + n * 0x08)
81 #define MAX_TIMER_CHANNEL 3
82 #define FEC_TMODE_TOGGLE 0x05
83 #define FEC_HIGH_PULSE 0x0F
85 #define FEC_CC_MULT (1 << 31)
86 #define FEC_COUNTER_PERIOD (1 << 31)
87 #define PPS_OUPUT_RELOAD_PERIOD NSEC_PER_SEC
88 #define FEC_CHANNLE_0 0
89 #define DEFAULT_PPS_CHANNEL FEC_CHANNLE_0
93 * @fep: the fec_enet_private structure handle
94 * @enable: enable the channel pps output
96 * This function enble the PPS ouput on the timer channel.
98 static int fec_ptp_enable_pps(struct fec_enet_private *fep, uint enable)
102 struct timespec64 ts;
105 if (fep->pps_enable == enable)
108 fep->pps_channel = DEFAULT_PPS_CHANNEL;
109 fep->reload_period = PPS_OUPUT_RELOAD_PERIOD;
111 spin_lock_irqsave(&fep->tmreg_lock, flags);
114 /* clear capture or output compare interrupt status if have.
116 writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel));
118 /* It is recommended to double check the TMODE field in the
119 * TCSR register to be cleared before the first compare counter
120 * is written into TCCR register. Just add a double check.
122 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
124 val &= ~(FEC_T_TMODE_MASK);
125 writel(val, fep->hwp + FEC_TCSR(fep->pps_channel));
126 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
127 } while (val & FEC_T_TMODE_MASK);
129 /* Dummy read counter to update the counter */
130 timecounter_read(&fep->tc);
131 /* We want to find the first compare event in the next
132 * second point. So we need to know what the ptp time
133 * is now and how many nanoseconds is ahead to get next second.
134 * The remaining nanosecond ahead before the next second would be
135 * NSEC_PER_SEC - ts.tv_nsec. Add the remaining nanoseconds
136 * to current timer would be next second.
138 tempval = readl(fep->hwp + FEC_ATIME_CTRL);
139 tempval |= FEC_T_CTRL_CAPTURE;
140 writel(tempval, fep->hwp + FEC_ATIME_CTRL);
142 tempval = readl(fep->hwp + FEC_ATIME);
143 /* Convert the ptp local counter to 1588 timestamp */
144 ns = timecounter_cyc2time(&fep->tc, tempval);
145 ts = ns_to_timespec64(ns);
147 /* The tempval is less than 3 seconds, and so val is less than
148 * 4 seconds. No overflow for 32bit calculation.
150 val = NSEC_PER_SEC - (u32)ts.tv_nsec + tempval;
152 /* Need to consider the situation that the current time is
153 * very close to the second point, which means NSEC_PER_SEC
154 * - ts.tv_nsec is close to be zero(For example 20ns); Since the timer
155 * is still running when we calculate the first compare event, it is
156 * possible that the remaining nanoseonds run out before the compare
157 * counter is calculated and written into TCCR register. To avoid
158 * this possibility, we will set the compare event to be the next
159 * of next second. The current setting is 31-bit timer and wrap
160 * around over 2 seconds. So it is okay to set the next of next
161 * seond for the timer.
165 /* We add (2 * NSEC_PER_SEC - (u32)ts.tv_nsec) to current
166 * ptp counter, which maybe cause 32-bit wrap. Since the
167 * (NSEC_PER_SEC - (u32)ts.tv_nsec) is less than 2 second.
168 * We can ensure the wrap will not cause issue. If the offset
169 * is bigger than fep->cc.mask would be a error.
172 writel(val, fep->hwp + FEC_TCCR(fep->pps_channel));
174 /* Calculate the second the compare event timestamp */
175 fep->next_counter = (val + fep->reload_period) & fep->cc.mask;
177 /* * Enable compare event when overflow */
178 val = readl(fep->hwp + FEC_ATIME_CTRL);
179 val |= FEC_T_CTRL_PINPER;
180 writel(val, fep->hwp + FEC_ATIME_CTRL);
182 /* Compare channel setting. */
183 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
184 val |= (1 << FEC_T_TF_OFFSET | 1 << FEC_T_TIE_OFFSET);
185 val &= ~(1 << FEC_T_TDRE_OFFSET);
186 val &= ~(FEC_T_TMODE_MASK);
187 val |= (FEC_HIGH_PULSE << FEC_T_TMODE_OFFSET);
188 writel(val, fep->hwp + FEC_TCSR(fep->pps_channel));
190 /* Write the second compare event timestamp and calculate
191 * the third timestamp. Refer the TCCR register detail in the spec.
193 writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel));
194 fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask;
196 writel(0, fep->hwp + FEC_TCSR(fep->pps_channel));
199 fep->pps_enable = enable;
200 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
206 * fec_ptp_read - read raw cycle counter (to be used by time counter)
207 * @cc: the cyclecounter structure
209 * this function reads the cyclecounter registers and is called by the
210 * cyclecounter structure used to construct a ns counter from the
211 * arbitrary fixed point registers
213 static u64 fec_ptp_read(const struct cyclecounter *cc)
215 struct fec_enet_private *fep =
216 container_of(cc, struct fec_enet_private, cc);
219 tempval = readl(fep->hwp + FEC_ATIME_CTRL);
220 tempval |= FEC_T_CTRL_CAPTURE;
221 writel(tempval, fep->hwp + FEC_ATIME_CTRL);
223 if (fep->quirks & FEC_QUIRK_BUG_CAPTURE)
226 return readl(fep->hwp + FEC_ATIME);
230 * fec_ptp_start_cyclecounter - create the cycle counter from hw
231 * @ndev: network device
233 * this function initializes the timecounter and cyclecounter
234 * structures for use in generated a ns counter from the arbitrary
235 * fixed point cycles registers in the hardware.
237 void fec_ptp_start_cyclecounter(struct net_device *ndev)
239 struct fec_enet_private *fep = netdev_priv(ndev);
243 inc = 1000000000 / fep->cycle_speed;
245 /* grab the ptp lock */
246 spin_lock_irqsave(&fep->tmreg_lock, flags);
249 writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC);
251 /* use 31-bit timer counter */
252 writel(FEC_COUNTER_PERIOD, fep->hwp + FEC_ATIME_EVT_PERIOD);
254 writel(FEC_T_CTRL_ENABLE | FEC_T_CTRL_PERIOD_RST,
255 fep->hwp + FEC_ATIME_CTRL);
257 memset(&fep->cc, 0, sizeof(fep->cc));
258 fep->cc.read = fec_ptp_read;
259 fep->cc.mask = CLOCKSOURCE_MASK(31);
261 fep->cc.mult = FEC_CC_MULT;
263 /* reset the ns time counter */
264 timecounter_init(&fep->tc, &fep->cc, 0);
266 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
270 * fec_ptp_adjfreq - adjust ptp cycle frequency
271 * @ptp: the ptp clock structure
272 * @ppb: parts per billion adjustment from base
274 * Adjust the frequency of the ptp cycle counter by the
275 * indicated ppb from the base frequency.
277 * Because ENET hardware frequency adjust is complex,
278 * using software method to do that.
280 static int fec_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
285 u32 corr_inc, corr_period;
289 struct fec_enet_private *fep =
290 container_of(ptp, struct fec_enet_private, ptp_caps);
300 /* In theory, corr_inc/corr_period = ppb/NSEC_PER_SEC;
301 * Try to find the corr_inc between 1 to fep->ptp_inc to
302 * meet adjustment requirement.
305 rhs = (u64)ppb * (u64)fep->ptp_inc;
306 for (i = 1; i <= fep->ptp_inc; i++) {
309 corr_period = div_u64(lhs, rhs);
314 /* Not found? Set it to high value - double speed
315 * correct in every clock step.
317 if (i > fep->ptp_inc) {
318 corr_inc = fep->ptp_inc;
323 corr_ns = fep->ptp_inc - corr_inc;
325 corr_ns = fep->ptp_inc + corr_inc;
327 spin_lock_irqsave(&fep->tmreg_lock, flags);
329 tmp = readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK;
330 tmp |= corr_ns << FEC_T_INC_CORR_OFFSET;
331 writel(tmp, fep->hwp + FEC_ATIME_INC);
332 corr_period = corr_period > 1 ? corr_period - 1 : corr_period;
333 writel(corr_period, fep->hwp + FEC_ATIME_CORR);
334 /* dummy read to update the timer. */
335 timecounter_read(&fep->tc);
337 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
344 * @ptp: the ptp clock structure
345 * @delta: offset to adjust the cycle counter by
347 * adjust the timer by resetting the timecounter structure.
349 static int fec_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
351 struct fec_enet_private *fep =
352 container_of(ptp, struct fec_enet_private, ptp_caps);
355 spin_lock_irqsave(&fep->tmreg_lock, flags);
356 timecounter_adjtime(&fep->tc, delta);
357 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
364 * @ptp: the ptp clock structure
365 * @ts: timespec structure to hold the current time value
367 * read the timecounter and return the correct value on ns,
368 * after converting it into a struct timespec.
370 static int fec_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
372 struct fec_enet_private *adapter =
373 container_of(ptp, struct fec_enet_private, ptp_caps);
377 mutex_lock(&adapter->ptp_clk_mutex);
378 /* Check the ptp clock */
379 if (!adapter->ptp_clk_on) {
380 mutex_unlock(&adapter->ptp_clk_mutex);
383 spin_lock_irqsave(&adapter->tmreg_lock, flags);
384 ns = timecounter_read(&adapter->tc);
385 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
386 mutex_unlock(&adapter->ptp_clk_mutex);
388 *ts = ns_to_timespec64(ns);
395 * @ptp: the ptp clock structure
396 * @ts: the timespec containing the new time for the cycle counter
398 * reset the timecounter to use a new base value instead of the kernel
401 static int fec_ptp_settime(struct ptp_clock_info *ptp,
402 const struct timespec64 *ts)
404 struct fec_enet_private *fep =
405 container_of(ptp, struct fec_enet_private, ptp_caps);
411 mutex_lock(&fep->ptp_clk_mutex);
412 /* Check the ptp clock */
413 if (!fep->ptp_clk_on) {
414 mutex_unlock(&fep->ptp_clk_mutex);
418 ns = timespec64_to_ns(ts);
419 /* Get the timer value based on timestamp.
420 * Update the counter with the masked value.
422 counter = ns & fep->cc.mask;
424 spin_lock_irqsave(&fep->tmreg_lock, flags);
425 writel(counter, fep->hwp + FEC_ATIME);
426 timecounter_init(&fep->tc, &fep->cc, ns);
427 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
428 mutex_unlock(&fep->ptp_clk_mutex);
434 * @ptp: the ptp clock structure
435 * @rq: the requested feature to change
436 * @on: whether to enable or disable the feature
439 static int fec_ptp_enable(struct ptp_clock_info *ptp,
440 struct ptp_clock_request *rq, int on)
442 struct fec_enet_private *fep =
443 container_of(ptp, struct fec_enet_private, ptp_caps);
446 if (rq->type == PTP_CLK_REQ_PPS) {
447 ret = fec_ptp_enable_pps(fep, on);
455 * fec_ptp_disable_hwts - disable hardware time stamping
456 * @ndev: pointer to net_device
458 void fec_ptp_disable_hwts(struct net_device *ndev)
460 struct fec_enet_private *fep = netdev_priv(ndev);
466 int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr)
468 struct fec_enet_private *fep = netdev_priv(ndev);
470 struct hwtstamp_config config;
472 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
475 switch (config.tx_type) {
476 case HWTSTAMP_TX_OFF:
486 switch (config.rx_filter) {
487 case HWTSTAMP_FILTER_NONE:
493 config.rx_filter = HWTSTAMP_FILTER_ALL;
497 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
501 int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr)
503 struct fec_enet_private *fep = netdev_priv(ndev);
504 struct hwtstamp_config config;
507 config.tx_type = fep->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
508 config.rx_filter = (fep->hwts_rx_en ?
509 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
511 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
516 * fec_time_keep - call timecounter_read every second to avoid timer overrun
517 * because ENET just support 32bit counter, will timeout in 4s
519 static void fec_time_keep(struct work_struct *work)
521 struct delayed_work *dwork = to_delayed_work(work);
522 struct fec_enet_private *fep = container_of(dwork, struct fec_enet_private, time_keep);
525 mutex_lock(&fep->ptp_clk_mutex);
526 if (fep->ptp_clk_on) {
527 spin_lock_irqsave(&fep->tmreg_lock, flags);
528 timecounter_read(&fep->tc);
529 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
531 mutex_unlock(&fep->ptp_clk_mutex);
533 schedule_delayed_work(&fep->time_keep, HZ);
536 /* This function checks the pps event and reloads the timer compare counter. */
537 static irqreturn_t fec_pps_interrupt(int irq, void *dev_id)
539 struct net_device *ndev = dev_id;
540 struct fec_enet_private *fep = netdev_priv(ndev);
542 u8 channel = fep->pps_channel;
543 struct ptp_clock_event event;
545 val = readl(fep->hwp + FEC_TCSR(channel));
546 if (val & FEC_T_TF_MASK) {
547 /* Write the next next compare(not the next according the spec)
548 * value to the register
550 writel(fep->next_counter, fep->hwp + FEC_TCCR(channel));
552 writel(val, fep->hwp + FEC_TCSR(channel));
553 } while (readl(fep->hwp + FEC_TCSR(channel)) & FEC_T_TF_MASK);
555 /* Update the counter; */
556 fep->next_counter = (fep->next_counter + fep->reload_period) &
559 event.type = PTP_CLOCK_PPS;
560 ptp_clock_event(fep->ptp_clock, &event);
569 * @pdev: The FEC network adapter
570 * @irq_idx: the interrupt index
572 * This function performs the required steps for enabling ptp
573 * support. If ptp support has already been loaded it simply calls the
574 * cyclecounter init routine and exits.
577 void fec_ptp_init(struct platform_device *pdev, int irq_idx)
579 struct net_device *ndev = platform_get_drvdata(pdev);
580 struct fec_enet_private *fep = netdev_priv(ndev);
584 fep->ptp_caps.owner = THIS_MODULE;
585 strlcpy(fep->ptp_caps.name, "fec ptp", sizeof(fep->ptp_caps.name));
587 fep->ptp_caps.max_adj = 250000000;
588 fep->ptp_caps.n_alarm = 0;
589 fep->ptp_caps.n_ext_ts = 0;
590 fep->ptp_caps.n_per_out = 0;
591 fep->ptp_caps.n_pins = 0;
592 fep->ptp_caps.pps = 1;
593 fep->ptp_caps.adjfreq = fec_ptp_adjfreq;
594 fep->ptp_caps.adjtime = fec_ptp_adjtime;
595 fep->ptp_caps.gettime64 = fec_ptp_gettime;
596 fep->ptp_caps.settime64 = fec_ptp_settime;
597 fep->ptp_caps.enable = fec_ptp_enable;
599 fep->cycle_speed = clk_get_rate(fep->clk_ptp);
600 if (!fep->cycle_speed) {
601 fep->cycle_speed = NSEC_PER_SEC;
602 dev_err(&fep->pdev->dev, "clk_ptp clock rate is zero\n");
604 fep->ptp_inc = NSEC_PER_SEC / fep->cycle_speed;
606 spin_lock_init(&fep->tmreg_lock);
608 fec_ptp_start_cyclecounter(ndev);
610 INIT_DELAYED_WORK(&fep->time_keep, fec_time_keep);
612 irq = platform_get_irq_byname_optional(pdev, "pps");
614 irq = platform_get_irq_optional(pdev, irq_idx);
615 /* Failure to get an irq is not fatal,
616 * only the PTP_CLOCK_PPS clock events should stop
619 ret = devm_request_irq(&pdev->dev, irq, fec_pps_interrupt,
620 0, pdev->name, ndev);
622 dev_warn(&pdev->dev, "request for pps irq failed(%d)\n",
626 fep->ptp_clock = ptp_clock_register(&fep->ptp_caps, &pdev->dev);
627 if (IS_ERR(fep->ptp_clock)) {
628 fep->ptp_clock = NULL;
629 dev_err(&pdev->dev, "ptp_clock_register failed\n");
632 schedule_delayed_work(&fep->time_keep, HZ);
635 void fec_ptp_stop(struct platform_device *pdev)
637 struct net_device *ndev = platform_get_drvdata(pdev);
638 struct fec_enet_private *fep = netdev_priv(ndev);
640 cancel_delayed_work_sync(&fep->time_keep);
642 ptp_clock_unregister(fep->ptp_clock);