1 /* SPDX-License-Identifier: GPL-2.0 */
2 /****************************************************************************/
5 * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC
8 * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
9 * (C) Copyright 2000-2001, Lineo (www.lineo.com)
12 /****************************************************************************/
15 /****************************************************************************/
17 #include <linux/clocksource.h>
18 #include <linux/net_tstamp.h>
19 #include <linux/pm_qos.h>
20 #include <linux/ptp_clock_kernel.h>
21 #include <linux/timecounter.h>
23 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
24 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
25 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
27 * Just figures, Motorola would have to change the offsets for
28 * registers in the same peripheral device on different models
31 #define FEC_IEVENT 0x004 /* Interrupt event reg */
32 #define FEC_IMASK 0x008 /* Interrupt mask reg */
33 #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */
34 #define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */
35 #define FEC_ECNTRL 0x024 /* Ethernet control reg */
36 #define FEC_MII_DATA 0x040 /* MII manage frame reg */
37 #define FEC_MII_SPEED 0x044 /* MII speed control reg */
38 #define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */
39 #define FEC_R_CNTRL 0x084 /* Receive control reg */
40 #define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */
41 #define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */
42 #define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */
43 #define FEC_OPD 0x0ec /* Opcode + Pause duration */
44 #define FEC_TXIC0 0x0f0 /* Tx Interrupt Coalescing for ring 0 */
45 #define FEC_TXIC1 0x0f4 /* Tx Interrupt Coalescing for ring 1 */
46 #define FEC_TXIC2 0x0f8 /* Tx Interrupt Coalescing for ring 2 */
47 #define FEC_RXIC0 0x100 /* Rx Interrupt Coalescing for ring 0 */
48 #define FEC_RXIC1 0x104 /* Rx Interrupt Coalescing for ring 1 */
49 #define FEC_RXIC2 0x108 /* Rx Interrupt Coalescing for ring 2 */
50 #define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */
51 #define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */
52 #define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */
53 #define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */
54 #define FEC_X_WMRK 0x144 /* FIFO transmit water mark */
55 #define FEC_R_BOUND 0x14c /* FIFO receive bound reg */
56 #define FEC_R_FSTART 0x150 /* FIFO receive start reg */
57 #define FEC_R_DES_START_1 0x160 /* Receive descriptor ring 1 */
58 #define FEC_X_DES_START_1 0x164 /* Transmit descriptor ring 1 */
59 #define FEC_R_BUFF_SIZE_1 0x168 /* Maximum receive buff ring1 size */
60 #define FEC_R_DES_START_2 0x16c /* Receive descriptor ring 2 */
61 #define FEC_X_DES_START_2 0x170 /* Transmit descriptor ring 2 */
62 #define FEC_R_BUFF_SIZE_2 0x174 /* Maximum receive buff ring2 size */
63 #define FEC_R_DES_START_0 0x180 /* Receive descriptor ring */
64 #define FEC_X_DES_START_0 0x184 /* Transmit descriptor ring */
65 #define FEC_R_BUFF_SIZE_0 0x188 /* Maximum receive buff size */
66 #define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */
67 #define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */
68 #define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */
69 #define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */
70 #define FEC_FTRL 0x1b0 /* Frame truncation receive length*/
71 #define FEC_RACC 0x1c4 /* Receive Accelerator function */
72 #define FEC_RCMR_1 0x1c8 /* Receive classification match ring 1 */
73 #define FEC_RCMR_2 0x1cc /* Receive classification match ring 2 */
74 #define FEC_DMA_CFG_1 0x1d8 /* DMA class configuration for ring 1 */
75 #define FEC_DMA_CFG_2 0x1dc /* DMA class Configuration for ring 2 */
76 #define FEC_R_DES_ACTIVE_1 0x1e0 /* Rx descriptor active for ring 1 */
77 #define FEC_X_DES_ACTIVE_1 0x1e4 /* Tx descriptor active for ring 1 */
78 #define FEC_R_DES_ACTIVE_2 0x1e8 /* Rx descriptor active for ring 2 */
79 #define FEC_X_DES_ACTIVE_2 0x1ec /* Tx descriptor active for ring 2 */
80 #define FEC_QOS_SCHEME 0x1f0 /* Set multi queues Qos scheme */
81 #define FEC_LPI_SLEEP 0x1f4 /* Set IEEE802.3az LPI Sleep Ts time */
82 #define FEC_LPI_WAKE 0x1f8 /* Set IEEE802.3az LPI Wake Tw time */
83 #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */
84 #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */
86 #define BM_MIIGSK_CFGR_MII 0x00
87 #define BM_MIIGSK_CFGR_RMII 0x01
88 #define BM_MIIGSK_CFGR_FRCONT_10M 0x40
90 #define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */
91 #define RMON_T_PACKETS 0x204 /* RMON TX packet count */
92 #define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */
93 #define RMON_T_MC_PKT 0x20c /* RMON TX multicast pkts */
94 #define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */
95 #define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */
96 #define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
97 #define RMON_T_FRAG 0x21c /* RMON TX pkts < 64 bytes, bad CRC */
98 #define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
99 #define RMON_T_COL 0x224 /* RMON TX collision count */
100 #define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */
101 #define RMON_T_P65TO127 0x22c /* RMON TX 65 to 127 byte pkts */
102 #define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */
103 #define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */
104 #define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */
105 #define RMON_T_P1024TO2047 0x23c /* RMON TX 1024 to 2047 byte pkts */
106 #define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */
107 #define RMON_T_OCTETS 0x244 /* RMON TX octets */
108 #define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */
109 #define IEEE_T_FRAME_OK 0x24c /* Frames tx'd OK */
110 #define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */
111 #define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */
112 #define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */
113 #define IEEE_T_LCOL 0x25c /* Frames tx'd with late collision */
114 #define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */
115 #define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */
116 #define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */
117 #define IEEE_T_SQE 0x26c /* Frames tx'd with SQE err */
118 #define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */
119 #define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */
120 #define RMON_R_PACKETS 0x284 /* RMON RX packet count */
121 #define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */
122 #define RMON_R_MC_PKT 0x28c /* RMON RX multicast pkts */
123 #define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */
124 #define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */
125 #define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
126 #define RMON_R_FRAG 0x29c /* RMON RX pkts < 64 bytes, bad CRC */
127 #define RMON_R_JAB 0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
128 #define RMON_R_RESVD_O 0x2a4 /* Reserved */
129 #define RMON_R_P64 0x2a8 /* RMON RX 64 byte pkts */
130 #define RMON_R_P65TO127 0x2ac /* RMON RX 65 to 127 byte pkts */
131 #define RMON_R_P128TO255 0x2b0 /* RMON RX 128 to 255 byte pkts */
132 #define RMON_R_P256TO511 0x2b4 /* RMON RX 256 to 511 byte pkts */
133 #define RMON_R_P512TO1023 0x2b8 /* RMON RX 512 to 1023 byte pkts */
134 #define RMON_R_P1024TO2047 0x2bc /* RMON RX 1024 to 2047 byte pkts */
135 #define RMON_R_P_GTE2048 0x2c0 /* RMON RX pkts > 2048 bytes */
136 #define RMON_R_OCTETS 0x2c4 /* RMON RX octets */
137 #define IEEE_R_DROP 0x2c8 /* Count frames not counted correctly */
138 #define IEEE_R_FRAME_OK 0x2cc /* Frames rx'd OK */
139 #define IEEE_R_CRC 0x2d0 /* Frames rx'd with CRC err */
140 #define IEEE_R_ALIGN 0x2d4 /* Frames rx'd with alignment err */
141 #define IEEE_R_MACERR 0x2d8 /* Receive FIFO overflow count */
142 #define IEEE_R_FDXFC 0x2dc /* Flow control pause frames rx'd */
143 #define IEEE_R_OCTETS_OK 0x2e0 /* Octet cnt for frames rx'd w/o err */
147 #define FEC_ECNTRL 0x000 /* Ethernet control reg */
148 #define FEC_IEVENT 0x004 /* Interrupt even reg */
149 #define FEC_IMASK 0x008 /* Interrupt mask reg */
150 #define FEC_IVEC 0x00c /* Interrupt vec status reg */
151 #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */
152 #define FEC_R_DES_ACTIVE_1 FEC_R_DES_ACTIVE_0
153 #define FEC_R_DES_ACTIVE_2 FEC_R_DES_ACTIVE_0
154 #define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */
155 #define FEC_X_DES_ACTIVE_1 FEC_X_DES_ACTIVE_0
156 #define FEC_X_DES_ACTIVE_2 FEC_X_DES_ACTIVE_0
157 #define FEC_MII_DATA 0x040 /* MII manage frame reg */
158 #define FEC_MII_SPEED 0x044 /* MII speed control reg */
159 #define FEC_R_BOUND 0x08c /* FIFO receive bound reg */
160 #define FEC_R_FSTART 0x090 /* FIFO receive start reg */
161 #define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */
162 #define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */
163 #define FEC_R_CNTRL 0x104 /* Receive control reg */
164 #define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */
165 #define FEC_X_CNTRL 0x144 /* Transmit Control reg */
166 #define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */
167 #define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */
168 #define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */
169 #define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */
170 #define FEC_R_DES_START_0 0x3d0 /* Receive descriptor ring */
171 #define FEC_R_DES_START_1 FEC_R_DES_START_0
172 #define FEC_R_DES_START_2 FEC_R_DES_START_0
173 #define FEC_X_DES_START_0 0x3d4 /* Transmit descriptor ring */
174 #define FEC_X_DES_START_1 FEC_X_DES_START_0
175 #define FEC_X_DES_START_2 FEC_X_DES_START_0
176 #define FEC_R_BUFF_SIZE_0 0x3d8 /* Maximum receive buff size */
177 #define FEC_R_BUFF_SIZE_1 FEC_R_BUFF_SIZE_0
178 #define FEC_R_BUFF_SIZE_2 FEC_R_BUFF_SIZE_0
179 #define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */
180 /* Not existed in real chip
181 * Just for pass build.
183 #define FEC_RCMR_1 0xfff
184 #define FEC_RCMR_2 0xfff
185 #define FEC_DMA_CFG_1 0xfff
186 #define FEC_DMA_CFG_2 0xfff
187 #define FEC_TXIC0 0xfff
188 #define FEC_TXIC1 0xfff
189 #define FEC_TXIC2 0xfff
190 #define FEC_RXIC0 0xfff
191 #define FEC_RXIC1 0xfff
192 #define FEC_RXIC2 0xfff
193 #define FEC_LPI_SLEEP 0xfff
194 #define FEC_LPI_WAKE 0xfff
195 #endif /* CONFIG_M5272 */
199 * Define the buffer descriptor structure.
201 * Evidently, ARM SoCs have the FEC block generated in a
202 * little endian mode so adjust endianness accordingly.
204 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
205 #define fec32_to_cpu le32_to_cpu
206 #define fec16_to_cpu le16_to_cpu
207 #define cpu_to_fec32 cpu_to_le32
208 #define cpu_to_fec16 cpu_to_le16
209 #define __fec32 __le32
210 #define __fec16 __le16
213 __fec16 cbd_datlen; /* Data length */
214 __fec16 cbd_sc; /* Control and status info */
215 __fec32 cbd_bufaddr; /* Buffer address */
218 #define fec32_to_cpu be32_to_cpu
219 #define fec16_to_cpu be16_to_cpu
220 #define cpu_to_fec32 cpu_to_be32
221 #define cpu_to_fec16 cpu_to_be16
222 #define __fec32 __be32
223 #define __fec16 __be16
226 __fec16 cbd_sc; /* Control and status info */
227 __fec16 cbd_datlen; /* Data length */
228 __fec32 cbd_bufaddr; /* Buffer address */
242 * The following definitions courtesy of commproc.h, which where
243 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
245 #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
246 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
247 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
248 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
249 #define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
250 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
251 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
252 #define BD_SC_BR ((ushort)0x0020) /* Break received */
253 #define BD_SC_FR ((ushort)0x0010) /* Framing error */
254 #define BD_SC_PR ((ushort)0x0008) /* Parity error */
255 #define BD_SC_OV ((ushort)0x0002) /* Overrun */
256 #define BD_SC_CD ((ushort)0x0001) /* ?? */
258 /* Buffer descriptor control/status used by Ethernet receive.
260 #define BD_ENET_RX_EMPTY ((ushort)0x8000)
261 #define BD_ENET_RX_WRAP ((ushort)0x2000)
262 #define BD_ENET_RX_INTR ((ushort)0x1000)
263 #define BD_ENET_RX_LAST ((ushort)0x0800)
264 #define BD_ENET_RX_FIRST ((ushort)0x0400)
265 #define BD_ENET_RX_MISS ((ushort)0x0100)
266 #define BD_ENET_RX_LG ((ushort)0x0020)
267 #define BD_ENET_RX_NO ((ushort)0x0010)
268 #define BD_ENET_RX_SH ((ushort)0x0008)
269 #define BD_ENET_RX_CR ((ushort)0x0004)
270 #define BD_ENET_RX_OV ((ushort)0x0002)
271 #define BD_ENET_RX_CL ((ushort)0x0001)
272 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
274 /* Enhanced buffer descriptor control/status used by Ethernet receive */
275 #define BD_ENET_RX_VLAN 0x00000004
277 /* Buffer descriptor control/status used by Ethernet transmit.
279 #define BD_ENET_TX_READY ((ushort)0x8000)
280 #define BD_ENET_TX_PAD ((ushort)0x4000)
281 #define BD_ENET_TX_WRAP ((ushort)0x2000)
282 #define BD_ENET_TX_INTR ((ushort)0x1000)
283 #define BD_ENET_TX_LAST ((ushort)0x0800)
284 #define BD_ENET_TX_TC ((ushort)0x0400)
285 #define BD_ENET_TX_DEF ((ushort)0x0200)
286 #define BD_ENET_TX_HB ((ushort)0x0100)
287 #define BD_ENET_TX_LC ((ushort)0x0080)
288 #define BD_ENET_TX_RL ((ushort)0x0040)
289 #define BD_ENET_TX_RCMASK ((ushort)0x003c)
290 #define BD_ENET_TX_UN ((ushort)0x0002)
291 #define BD_ENET_TX_CSL ((ushort)0x0001)
292 #define BD_ENET_TX_STATS ((ushort)0x0fff) /* All status bits */
294 /* enhanced buffer descriptor control/status used by Ethernet transmit */
295 #define BD_ENET_TX_INT 0x40000000
296 #define BD_ENET_TX_TS 0x20000000
297 #define BD_ENET_TX_PINS 0x10000000
298 #define BD_ENET_TX_IINS 0x08000000
301 /* This device has up to three irqs on some platforms */
302 #define FEC_IRQ_NUM 3
304 /* Maximum number of queues supported
305 * ENET with AVB IP can support up to 3 independent tx queues and rx queues.
306 * User can point the queue number that is less than or equal to 3.
308 #define FEC_ENET_MAX_TX_QS 3
309 #define FEC_ENET_MAX_RX_QS 3
311 #define FEC_R_DES_START(X) (((X) == 1) ? FEC_R_DES_START_1 : \
313 FEC_R_DES_START_2 : FEC_R_DES_START_0))
314 #define FEC_X_DES_START(X) (((X) == 1) ? FEC_X_DES_START_1 : \
316 FEC_X_DES_START_2 : FEC_X_DES_START_0))
317 #define FEC_R_BUFF_SIZE(X) (((X) == 1) ? FEC_R_BUFF_SIZE_1 : \
319 FEC_R_BUFF_SIZE_2 : FEC_R_BUFF_SIZE_0))
321 #define FEC_DMA_CFG(X) (((X) == 2) ? FEC_DMA_CFG_2 : FEC_DMA_CFG_1)
323 #define DMA_CLASS_EN (1 << 16)
324 #define FEC_RCMR(X) (((X) == 2) ? FEC_RCMR_2 : FEC_RCMR_1)
325 #define IDLE_SLOPE_MASK 0xffff
326 #define IDLE_SLOPE_1 0x200 /* BW fraction: 0.5 */
327 #define IDLE_SLOPE_2 0x200 /* BW fraction: 0.5 */
328 #define IDLE_SLOPE(X) (((X) == 1) ? \
329 (IDLE_SLOPE_1 & IDLE_SLOPE_MASK) : \
330 (IDLE_SLOPE_2 & IDLE_SLOPE_MASK))
331 #define RCMR_MATCHEN (0x1 << 16)
332 #define RCMR_CMP_CFG(v, n) (((v) & 0x7) << (n << 2))
333 #define RCMR_CMP_1 (RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \
334 RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3))
335 #define RCMR_CMP_2 (RCMR_CMP_CFG(4, 0) | RCMR_CMP_CFG(5, 1) | \
336 RCMR_CMP_CFG(6, 2) | RCMR_CMP_CFG(7, 3))
337 #define RCMR_CMP(X) (((X) == 1) ? RCMR_CMP_1 : RCMR_CMP_2)
338 #define FEC_TX_BD_FTYPE(X) (((X) & 0xf) << 20)
340 /* The number of Tx and Rx buffers. These are allocated from the page
341 * pool. The code may assume these are power of two, so it it best
342 * to keep them that size.
343 * We don't need to allocate pages for the transmitter. We just use
344 * the skbuffer directly.
347 #define FEC_ENET_RX_PAGES 256
348 #define FEC_ENET_RX_FRSIZE 2048
349 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
350 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
351 #define FEC_ENET_TX_FRSIZE 2048
352 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
353 #define TX_RING_SIZE 512 /* Must be power of two */
354 #define TX_RING_MOD_MASK 511 /* for this to work */
356 #define BD_ENET_RX_INT 0x00800000
357 #define BD_ENET_RX_PTP ((ushort)0x0400)
358 #define BD_ENET_RX_ICE 0x00000020
359 #define BD_ENET_RX_PCR 0x00000010
360 #define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE | BD_ENET_RX_PCR)
361 #define FLAG_RX_CSUM_ERROR (BD_ENET_RX_ICE | BD_ENET_RX_PCR)
363 /* Interrupt events/masks. */
364 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
365 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
366 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
367 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
368 #define FEC_ENET_TXF_0 ((uint)0x08000000) /* Full frame transmitted */
369 #define FEC_ENET_TXF_1 ((uint)0x00000008) /* Full frame transmitted */
370 #define FEC_ENET_TXF_2 ((uint)0x00000080) /* Full frame transmitted */
371 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
372 #define FEC_ENET_RXF_0 ((uint)0x02000000) /* Full frame received */
373 #define FEC_ENET_RXF_1 ((uint)0x00000002) /* Full frame received */
374 #define FEC_ENET_RXF_2 ((uint)0x00000020) /* Full frame received */
375 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
376 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
377 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
378 #define FEC_ENET_WAKEUP ((uint)0x00020000) /* Wakeup request */
379 #define FEC_ENET_TXF (FEC_ENET_TXF_0 | FEC_ENET_TXF_1 | FEC_ENET_TXF_2)
380 #define FEC_ENET_RXF (FEC_ENET_RXF_0 | FEC_ENET_RXF_1 | FEC_ENET_RXF_2)
381 #define FEC_ENET_RXF_GET(X) (((X) == 0) ? FEC_ENET_RXF_0 : \
382 (((X) == 1) ? FEC_ENET_RXF_1 : \
384 #define FEC_ENET_TS_AVAIL ((uint)0x00010000)
385 #define FEC_ENET_TS_TIMER ((uint)0x00008000)
387 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF)
388 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
390 #define FEC_ENET_TXC_DLY ((uint)0x00010000)
391 #define FEC_ENET_RXC_DLY ((uint)0x00020000)
393 /* ENET interrupt coalescing macro define */
394 #define FEC_ITR_CLK_SEL (0x1 << 30)
395 #define FEC_ITR_EN (0x1 << 31)
396 #define FEC_ITR_ICFT(X) (((X) & 0xff) << 20)
397 #define FEC_ITR_ICTT(X) ((X) & 0xffff)
398 #define FEC_ITR_ICFT_DEFAULT 200 /* Set 200 frame count threshold */
399 #define FEC_ITR_ICTT_DEFAULT 1000 /* Set 1000us timer threshold */
401 #define FEC_VLAN_TAG_LEN 0x04
402 #define FEC_ETHTYPE_LEN 0x02
404 /* Controller is ENET-MAC */
405 #define FEC_QUIRK_ENET_MAC (1 << 0)
406 /* Controller needs driver to swap frame */
407 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
408 /* Controller uses gasket */
409 #define FEC_QUIRK_USE_GASKET (1 << 2)
410 /* Controller has GBIT support */
411 #define FEC_QUIRK_HAS_GBIT (1 << 3)
412 /* Controller has extend desc buffer */
413 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
414 /* Controller has hardware checksum support */
415 #define FEC_QUIRK_HAS_CSUM (1 << 5)
416 /* Controller has hardware vlan support */
417 #define FEC_QUIRK_HAS_VLAN (1 << 6)
418 /* ENET IP errata ERR006358
420 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
421 * detected as not set during a prior frame transmission, then the
422 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
423 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
424 * frames not being transmitted until there is a 0-to-1 transition on
427 #define FEC_QUIRK_ERR006358 (1 << 7)
430 * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support.
431 * - Two class indicators on receive with configurable priority
432 * - Two class indicators and line speed timer on transmit allowing
433 * implementation class credit based shapers externally
434 * - Additional DMA registers provisioned to allow managing up to 3
437 #define FEC_QUIRK_HAS_AVB (1 << 8)
438 /* There is a TDAR race condition for mutliQ when the software sets TDAR
439 * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
440 * This will cause the udma_tx and udma_tx_arbiter state machines to hang.
441 * The issue exist at i.MX6SX enet IP.
443 #define FEC_QUIRK_ERR007885 (1 << 9)
444 /* ENET Block Guide/ Chapter for the iMX6SX (PELE) address one issue:
445 * After set ENET_ATCR[Capture], there need some time cycles before the counter
446 * value is capture in the register clock domain.
447 * The wait-time-cycles is at least 6 clock cycles of the slower clock between
448 * the register clock and the 1588 clock. The 1588 ts_clk is fixed to 25Mhz,
449 * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns
452 #define FEC_QUIRK_BUG_CAPTURE (1 << 10)
453 /* Controller has only one MDIO bus */
454 #define FEC_QUIRK_SINGLE_MDIO (1 << 11)
455 /* Controller supports RACC register */
456 #define FEC_QUIRK_HAS_RACC (1 << 12)
457 /* Controller supports interrupt coalesc */
458 #define FEC_QUIRK_HAS_COALESCE (1 << 13)
459 /* Interrupt doesn't wake CPU from deep idle */
460 #define FEC_QUIRK_ERR006687 (1 << 14)
461 /* The MIB counters should be cleared and enabled during
464 #define FEC_QUIRK_MIB_CLEAR (1 << 15)
465 /* Only i.MX25/i.MX27/i.MX28 controller supports FRBR,FRSR registers,
466 * those FIFO receive registers are resolved in other platforms.
468 #define FEC_QUIRK_HAS_FRREG (1 << 16)
470 /* Some FEC hardware blocks need the MMFR cleared at setup time to avoid
471 * the generation of an MII event. This must be avoided in the older
472 * FEC blocks where it will stop MII events being generated.
474 #define FEC_QUIRK_CLEAR_SETUP_MII (1 << 17)
476 /* Some link partners do not tolerate the momentary reset of the REF_CLK
477 * frequency when the RNCTL register is cleared by hardware reset.
479 #define FEC_QUIRK_NO_HARD_RESET (1 << 18)
481 /* i.MX6SX ENET IP supports multiple queues (3 queues), use this quirk to
482 * represents this ENET IP.
484 #define FEC_QUIRK_HAS_MULTI_QUEUES (1 << 19)
486 /* i.MX8MQ ENET IP version add new feature to support IEEE 802.3az EEE
487 * standard. For the transmission, MAC supply two user registers to set
488 * Sleep (TS) and Wake (TW) time.
490 #define FEC_QUIRK_HAS_EEE (1 << 20)
492 /* i.MX8QM ENET IP version add new feture to generate delayed TXC/RXC
493 * as an alternative option to make sure it works well with various PHYs.
494 * For the implementation of delayed clock, ENET takes synchronized 250MHz
495 * clocks to generate 2ns delay.
497 #define FEC_QUIRK_DELAYED_CLKS_SUPPORT (1 << 21)
499 /* i.MX8MQ SoC integration mix wakeup interrupt signal into "int2" interrupt line. */
500 #define FEC_QUIRK_WAKEUP_FROM_INT2 (1 << 22)
502 /* i.MX6Q adds pm_qos support */
503 #define FEC_QUIRK_HAS_PMQOS BIT(23)
505 struct bufdesc_prop {
507 /* Address of Rx and Tx buffers */
508 struct bufdesc *base;
509 struct bufdesc *last;
511 void __iomem *reg_desc_active;
513 unsigned short ring_size;
515 unsigned char dsize_log2;
518 struct fec_enet_priv_tx_q {
519 struct bufdesc_prop bd;
520 unsigned char *tx_bounce[TX_RING_SIZE];
521 struct sk_buff *tx_skbuff[TX_RING_SIZE];
523 unsigned short tx_stop_threshold;
524 unsigned short tx_wake_threshold;
526 struct bufdesc *dirty_tx;
528 dma_addr_t tso_hdrs_dma;
531 struct fec_enet_priv_rx_q {
532 struct bufdesc_prop bd;
533 struct sk_buff *rx_skbuff[RX_RING_SIZE];
536 struct fec_stop_mode_gpr {
542 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
543 * tx_bd_base always point to the base of the buffer descriptors. The
544 * cur_rx and cur_tx point to the currently available buffer.
545 * The dirty_tx tracks the current buffer that is being sent by the
546 * controller. The cur_tx and dirty_tx are equal under both completely
547 * empty and completely full conditions. The empty/ready indicator in
548 * the buffer descriptor determines the actual condition.
550 struct fec_enet_private {
551 /* Hardware registers of the FEC device */
554 struct net_device *netdev;
559 struct clk *clk_enet_out;
561 struct clk *clk_2x_txclk;
564 unsigned int num_tx_queues;
565 unsigned int num_rx_queues;
567 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
568 struct fec_enet_priv_tx_q *tx_queue[FEC_ENET_MAX_TX_QS];
569 struct fec_enet_priv_rx_q *rx_queue[FEC_ENET_MAX_RX_QS];
571 unsigned int total_tx_ring_size;
572 unsigned int total_rx_ring_size;
574 struct platform_device *pdev;
578 /* Phylib and MDIO interface */
579 struct mii_bus *mii_bus;
581 phy_interface_t phy_interface;
582 struct device_node *phy_node;
588 int irq[FEC_IRQ_NUM];
595 struct napi_struct napi;
598 struct work_struct tx_timeout_work;
600 struct ptp_clock *ptp_clock;
601 struct ptp_clock_info ptp_caps;
602 unsigned long last_overflow_check;
603 spinlock_t tmreg_lock;
604 struct cyclecounter cc;
605 struct timecounter tc;
606 int rx_hwtstamp_filter;
611 struct delayed_work time_keep;
612 struct regulator *reg_phy;
613 struct fec_stop_mode_gpr stop_gpr;
614 struct pm_qos_request pm_qos_req;
616 unsigned int tx_align;
617 unsigned int rx_align;
619 /* hw interrupt coalesce */
620 unsigned int rx_pkts_itr;
621 unsigned int rx_time_itr;
622 unsigned int tx_pkts_itr;
623 unsigned int tx_time_itr;
624 unsigned int itr_clk_rate;
626 /* tx lpi eee mode */
627 struct ethtool_eee eee;
628 unsigned int clk_ref_rate;
632 /* ptp clock period in ns*/
633 unsigned int ptp_inc;
637 unsigned int reload_period;
639 unsigned int next_counter;
642 struct timespec64 ts_phc;
651 void fec_ptp_init(struct platform_device *pdev, int irq_idx);
652 void fec_ptp_stop(struct platform_device *pdev);
653 void fec_ptp_start_cyclecounter(struct net_device *ndev);
654 void fec_ptp_disable_hwts(struct net_device *ndev);
655 int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr);
656 int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr);
658 void fec_ptp_save_state(struct fec_enet_private *fep);
659 int fec_ptp_restore_state(struct fec_enet_private *fep);
661 /****************************************************************************/