1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2017-2019 NXP */
4 #include <linux/bitops.h>
7 #define ENETC_DEV_ID_PF 0xe100
8 #define ENETC_DEV_ID_VF 0xef00
9 #define ENETC_DEV_ID_PTP 0xee02
11 /* ENETC register block BAR */
12 #define ENETC_BAR_REGS 0
14 /** SI regs, offset: 0h */
16 #define ENETC_SIMR_EN BIT(31)
17 #define ENETC_SIMR_RSSE BIT(0)
18 #define ENETC_SICTR0 0x18
19 #define ENETC_SICTR1 0x1c
20 #define ENETC_SIPCAPR0 0x20
21 #define ENETC_SIPCAPR0_QBV BIT(4)
22 #define ENETC_SIPCAPR0_RSS BIT(8)
23 #define ENETC_SIPCAPR1 0x24
24 #define ENETC_SITGTGR 0x30
25 #define ENETC_SIRBGCR 0x38
26 /* cache attribute registers for transactions initiated by ENETC */
27 #define ENETC_SICAR0 0x40
28 #define ENETC_SICAR1 0x44
29 #define ENETC_SICAR2 0x48
31 * wr snoop, no alloc, partial cache line update for BDs and full cache line
34 #define ENETC_SICAR_RD_COHERENT 0x2b2b0000
35 #define ENETC_SICAR_WR_COHERENT 0x00006727
36 #define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */
38 #define ENETC_SIPMAR0 0x80
39 #define ENETC_SIPMAR1 0x84
41 /* VF-PF Message passing */
42 #define ENETC_DEFAULT_MSG_SIZE 1024 /* and max size */
43 /* msg size encoding: default and max msg value of 1024B encoded as 0 */
44 static inline u32 enetc_vsi_set_msize(u32 size)
46 return size < ENETC_DEFAULT_MSG_SIZE ? size >> 5 : 0;
49 #define ENETC_PSIMSGRR 0x204
50 #define ENETC_PSIMSGRR_MR_MASK GENMASK(2, 1)
51 #define ENETC_PSIMSGRR_MR(n) BIT((n) + 1) /* n = VSI index */
52 #define ENETC_PSIVMSGRCVAR0(n) (0x210 + (n) * 0x8) /* n = VSI index */
53 #define ENETC_PSIVMSGRCVAR1(n) (0x214 + (n) * 0x8)
55 #define ENETC_VSIMSGSR 0x204 /* RO */
56 #define ENETC_VSIMSGSR_MB BIT(0)
57 #define ENETC_VSIMSGSR_MS BIT(1)
58 #define ENETC_VSIMSGSNDAR0 0x210
59 #define ENETC_VSIMSGSNDAR1 0x214
61 #define ENETC_SIMSGSR_SET_MC(val) ((val) << 16)
62 #define ENETC_SIMSGSR_GET_MC(val) ((val) >> 16)
65 #define ENETC_SIROCT 0x300
66 #define ENETC_SIRFRM 0x308
67 #define ENETC_SIRUCA 0x310
68 #define ENETC_SIRMCA 0x318
69 #define ENETC_SITOCT 0x320
70 #define ENETC_SITFRM 0x328
71 #define ENETC_SITUCA 0x330
72 #define ENETC_SITMCA 0x338
73 #define ENETC_RBDCR(n) (0x8180 + (n) * 0x200)
75 /* Control BDR regs */
76 #define ENETC_SICBDRMR 0x800
77 #define ENETC_SICBDRSR 0x804 /* RO */
78 #define ENETC_SICBDRBAR0 0x810
79 #define ENETC_SICBDRBAR1 0x814
80 #define ENETC_SICBDRPIR 0x818
81 #define ENETC_SICBDRCIR 0x81c
82 #define ENETC_SICBDRLENR 0x820
84 #define ENETC_SICAPR0 0x900
85 #define ENETC_SICAPR1 0x904
87 #define ENETC_PSIIER 0xa00
88 #define ENETC_PSIIER_MR_MASK GENMASK(2, 1)
89 #define ENETC_PSIIDR 0xa08
90 #define ENETC_SITXIDR 0xa18
91 #define ENETC_SIRXIDR 0xa28
92 #define ENETC_SIMSIVR 0xa30
94 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4)
95 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4)
97 #define ENETC_SIUEFDCR 0xe28
99 #define ENETC_SIRFSCAPR 0x1200
100 #define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f)
101 #define ENETC_SIRSSCAPR 0x1600
102 #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32)
104 /** SI BDR sub-blocks, n = 0..7 */
105 enum enetc_bdr_type {TX, RX};
106 #define ENETC_BDR_OFF(i) ((i) * 0x200)
107 #define ENETC_BDR(t, i, r) (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r))
108 /* RX BDR reg offsets */
110 #define ENETC_RBMR_BDS BIT(2)
111 #define ENETC_RBMR_VTE BIT(5)
112 #define ENETC_RBMR_EN BIT(31)
113 #define ENETC_RBSR 0x4
114 #define ENETC_RBBSR 0x8
115 #define ENETC_RBCIR 0xc
116 #define ENETC_RBBAR0 0x10
117 #define ENETC_RBBAR1 0x14
118 #define ENETC_RBPIR 0x18
119 #define ENETC_RBLENR 0x20
120 #define ENETC_RBIER 0xa0
121 #define ENETC_RBIER_RXTIE BIT(0)
122 #define ENETC_RBIDR 0xa4
123 #define ENETC_RBICIR0 0xa8
124 #define ENETC_RBICIR0_ICEN BIT(31)
126 /* TX BDR reg offsets */
128 #define ENETC_TBSR_BUSY BIT(0)
129 #define ENETC_TBMR_VIH BIT(9)
130 #define ENETC_TBMR_PRIO_MASK GENMASK(2, 0)
131 #define ENETC_TBMR_SET_PRIO(val) ((val) & ENETC_TBMR_PRIO_MASK)
132 #define ENETC_TBMR_EN BIT(31)
133 #define ENETC_TBSR 0x4
134 #define ENETC_TBBAR0 0x10
135 #define ENETC_TBBAR1 0x14
136 #define ENETC_TBPIR 0x18
137 #define ENETC_TBCIR 0x1c
138 #define ENETC_TBCIR_IDX_MASK 0xffff
139 #define ENETC_TBLENR 0x20
140 #define ENETC_TBIER 0xa0
141 #define ENETC_TBIER_TXTIE BIT(0)
142 #define ENETC_TBIDR 0xa4
143 #define ENETC_TBICIR0 0xa8
144 #define ENETC_TBICIR0_ICEN BIT(31)
146 #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7)
148 /* Port regs, offset: 1_0000h */
149 #define ENETC_PORT_BASE 0x10000
150 #define ENETC_PMR 0x0000
151 #define ENETC_PMR_EN GENMASK(18, 16)
152 #define ENETC_PMR_PSPEED_MASK GENMASK(11, 8)
153 #define ENETC_PMR_PSPEED_10M 0
154 #define ENETC_PMR_PSPEED_100M BIT(8)
155 #define ENETC_PMR_PSPEED_1000M BIT(9)
156 #define ENETC_PMR_PSPEED_2500M BIT(10)
157 #define ENETC_PSR 0x0004 /* RO */
158 #define ENETC_PSIPMR 0x0018
159 #define ENETC_PSIPMR_SET_UP(n) BIT(n) /* n = SI index */
160 #define ENETC_PSIPMR_SET_MP(n) BIT((n) + 16)
161 #define ENETC_PSIPVMR 0x001c
162 #define ENETC_VLAN_PROMISC_MAP_ALL 0x7
163 #define ENETC_PSIPVMR_SET_VP(simap) ((simap) & 0x7)
164 #define ENETC_PSIPVMR_SET_VUTA(simap) (((simap) & 0x7) << 16)
165 #define ENETC_PSIPMAR0(n) (0x0100 + (n) * 0x8) /* n = SI index */
166 #define ENETC_PSIPMAR1(n) (0x0104 + (n) * 0x8)
167 #define ENETC_PVCLCTR 0x0208
168 #define ENETC_VLAN_TYPE_C BIT(0)
169 #define ENETC_VLAN_TYPE_S BIT(1)
170 #define ENETC_PVCLCTR_OVTPIDL(bmp) ((bmp) & 0xff) /* VLAN_TYPE */
171 #define ENETC_PSIVLANR(n) (0x0240 + (n) * 4) /* n = SI index */
172 #define ENETC_PSIVLAN_EN BIT(31)
173 #define ENETC_PSIVLAN_SET_QOS(val) ((u32)(val) << 12)
174 #define ENETC_PTXMBAR 0x0608
175 #define ENETC_PCAPR0 0x0900
176 #define ENETC_PCAPR0_RXBDR(val) ((val) >> 24)
177 #define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff)
178 #define ENETC_PCAPR1 0x0904
179 #define ENETC_PSICFGR0(n) (0x0940 + (n) * 0xc) /* n = SI index */
180 #define ENETC_PSICFGR0_SET_TXBDR(val) ((val) & 0xff)
181 #define ENETC_PSICFGR0_SET_RXBDR(val) (((val) & 0xff) << 16)
182 #define ENETC_PSICFGR0_VTE BIT(12)
183 #define ENETC_PSICFGR0_SIVIE BIT(14)
184 #define ENETC_PSICFGR0_ASE BIT(15)
185 #define ENETC_PSICFGR0_SIVC(bmp) (((bmp) & 0xff) << 24) /* VLAN_TYPE */
187 #define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/
188 #define ENETC_CBSE BIT(31)
189 #define ENETC_CBS_BW_MASK GENMASK(6, 0)
190 #define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/
191 #define ENETC_RSSHASH_KEY_SIZE 40
192 #define ENETC_PRSSK(n) (0x1410 + (n) * 4) /* n = [0..9] */
193 #define ENETC_PSIVLANFMR 0x1700
194 #define ENETC_PSIVLANFMR_VS BIT(0)
195 #define ENETC_PRFSMR 0x1800
196 #define ENETC_PRFSMR_RFSE BIT(31)
197 #define ENETC_PRFSCAPR 0x1804
198 #define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16)
199 #define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */
200 #define ENETC_PFPMR 0x1900
201 #define ENETC_PFPMR_PMACE BIT(1)
202 #define ENETC_PFPMR_MWLM BIT(0)
203 #define ENETC_EMDIO_BASE 0x1c00
204 #define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10)
205 #define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10)
206 #define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10)
207 #define ENETC_PSIMMHFR1(n) (0x1d0c + (n) * 0x10)
208 #define ENETC_PSIVHFR0(n) (0x1e00 + (n) * 8) /* n = SI index */
209 #define ENETC_PSIVHFR1(n) (0x1e04 + (n) * 8) /* n = SI index */
210 #define ENETC_MMCSR 0x1f00
211 #define ENETC_MMCSR_ME BIT(16)
212 #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */
214 #define ENETC_PM0_CMD_CFG 0x8008
215 #define ENETC_PM1_CMD_CFG 0x9008
216 #define ENETC_PM0_TX_EN BIT(0)
217 #define ENETC_PM0_RX_EN BIT(1)
218 #define ENETC_PM0_PROMISC BIT(4)
219 #define ENETC_PM0_CMD_XGLP BIT(10)
220 #define ENETC_PM0_CMD_TXP BIT(11)
221 #define ENETC_PM0_CMD_PHY_TX_EN BIT(15)
222 #define ENETC_PM0_CMD_SFD BIT(21)
223 #define ENETC_PM0_MAXFRM 0x8014
224 #define ENETC_SET_TX_MTU(val) ((val) << 16)
225 #define ENETC_SET_MAXFRM(val) ((val) & 0xffff)
226 #define ENETC_PM0_IF_MODE 0x8300
227 #define ENETC_PMO_IFM_RG BIT(2)
228 #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11))
229 #define ENETC_PM0_IFM_RGAUTO (BIT(15) | ENETC_PMO_IFM_RG | BIT(1))
230 #define ENETC_PM0_IFM_XGMII BIT(12)
233 #define ENETC_PM0_REOCT 0x8100
234 #define ENETC_PM0_RALN 0x8110
235 #define ENETC_PM0_RXPF 0x8118
236 #define ENETC_PM0_RFRM 0x8120
237 #define ENETC_PM0_RFCS 0x8128
238 #define ENETC_PM0_RVLAN 0x8130
239 #define ENETC_PM0_RERR 0x8138
240 #define ENETC_PM0_RUCA 0x8140
241 #define ENETC_PM0_RMCA 0x8148
242 #define ENETC_PM0_RBCA 0x8150
243 #define ENETC_PM0_RDRP 0x8158
244 #define ENETC_PM0_RPKT 0x8160
245 #define ENETC_PM0_RUND 0x8168
246 #define ENETC_PM0_R64 0x8170
247 #define ENETC_PM0_R127 0x8178
248 #define ENETC_PM0_R255 0x8180
249 #define ENETC_PM0_R511 0x8188
250 #define ENETC_PM0_R1023 0x8190
251 #define ENETC_PM0_R1518 0x8198
252 #define ENETC_PM0_R1519X 0x81A0
253 #define ENETC_PM0_ROVR 0x81A8
254 #define ENETC_PM0_RJBR 0x81B0
255 #define ENETC_PM0_RFRG 0x81B8
256 #define ENETC_PM0_RCNP 0x81C0
257 #define ENETC_PM0_RDRNTP 0x81C8
258 #define ENETC_PM0_TEOCT 0x8200
259 #define ENETC_PM0_TOCT 0x8208
260 #define ENETC_PM0_TCRSE 0x8210
261 #define ENETC_PM0_TXPF 0x8218
262 #define ENETC_PM0_TFRM 0x8220
263 #define ENETC_PM0_TFCS 0x8228
264 #define ENETC_PM0_TVLAN 0x8230
265 #define ENETC_PM0_TERR 0x8238
266 #define ENETC_PM0_TUCA 0x8240
267 #define ENETC_PM0_TMCA 0x8248
268 #define ENETC_PM0_TBCA 0x8250
269 #define ENETC_PM0_TPKT 0x8260
270 #define ENETC_PM0_TUND 0x8268
271 #define ENETC_PM0_T127 0x8278
272 #define ENETC_PM0_T1023 0x8290
273 #define ENETC_PM0_T1518 0x8298
274 #define ENETC_PM0_TCNP 0x82C0
275 #define ENETC_PM0_TDFR 0x82D0
276 #define ENETC_PM0_TMCOL 0x82D8
277 #define ENETC_PM0_TSCOL 0x82E0
278 #define ENETC_PM0_TLCOL 0x82E8
279 #define ENETC_PM0_TECOL 0x82F0
282 #define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */
283 #define ENETC_PBFDSIR 0x0810
284 #define ENETC_PFDMSAPR 0x0814
285 #define ENETC_UFDMF 0x1680
286 #define ENETC_MFDMF 0x1684
287 #define ENETC_PUFDVFR 0x1780
288 #define ENETC_PMFDVFR 0x1784
289 #define ENETC_PBFDVFR 0x1788
291 /** Global regs, offset: 2_0000h */
292 #define ENETC_GLOBAL_BASE 0x20000
293 #define ENETC_G_EIPBRR0 0x0bf8
294 #define ENETC_G_EIPBRR1 0x0bfc
295 #define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n))
296 #define ENETC_G_EPFBLPR1_XGMII 0x80000000
298 /* PCI device info */
300 /* SI registers, used by all PCI functions */
302 /* Port registers, PF only */
304 /* IP global registers, PF only */
305 void __iomem *global;
308 /* general register accessors */
309 #define enetc_rd_reg(reg) ioread32((reg))
310 #define enetc_wr_reg(reg, val) iowrite32((val), (reg))
312 #define enetc_rd_reg64(reg) ioread64((reg))
314 /* using this to read out stats on 32b systems */
315 static inline u64 enetc_rd_reg64(void __iomem *reg)
320 high = ioread32(reg + 4);
322 tmp = ioread32(reg + 4);
323 } while (high != tmp);
325 return le64_to_cpu((__le64)high << 32 | low);
329 #define enetc_rd(hw, off) enetc_rd_reg((hw)->reg + (off))
330 #define enetc_wr(hw, off, val) enetc_wr_reg((hw)->reg + (off), val)
331 #define enetc_rd64(hw, off) enetc_rd_reg64((hw)->reg + (off))
332 /* port register accessors - PF only */
333 #define enetc_port_rd(hw, off) enetc_rd_reg((hw)->port + (off))
334 #define enetc_port_wr(hw, off, val) enetc_wr_reg((hw)->port + (off), val)
335 /* global register accessors - PF only */
336 #define enetc_global_rd(hw, off) enetc_rd_reg((hw)->global + (off))
337 #define enetc_global_wr(hw, off, val) enetc_wr_reg((hw)->global + (off), val)
338 /* BDR register accessors, see ENETC_BDR() */
339 #define enetc_bdr_rd(hw, t, n, off) \
340 enetc_rd(hw, ENETC_BDR(t, n, off))
341 #define enetc_bdr_wr(hw, t, n, off, val) \
342 enetc_wr(hw, ENETC_BDR(t, n, off), val)
343 #define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off)
344 #define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off)
345 #define enetc_txbdr_wr(hw, n, off, val) \
346 enetc_bdr_wr(hw, TX, n, off, val)
347 #define enetc_rxbdr_wr(hw, n, off, val) \
348 enetc_bdr_wr(hw, RX, n, off, val)
350 /* Buffer Descriptors (BD) */
361 }; /* default layout */
373 } ext; /* Tx BD extension */
379 } wb; /* writeback descriptor */
382 #define ENETC_TXBD_FLAGS_L4CS BIT(0)
383 #define ENETC_TXBD_FLAGS_TSE BIT(1)
384 #define ENETC_TXBD_FLAGS_W BIT(2)
385 #define ENETC_TXBD_FLAGS_CSUM BIT(3)
386 #define ENETC_TXBD_FLAGS_TXSTART BIT(4)
387 #define ENETC_TXBD_FLAGS_EX BIT(6)
388 #define ENETC_TXBD_FLAGS_F BIT(7)
389 #define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0)
390 #define ENETC_TXBD_FLAGS_OFFSET 24
391 static inline void enetc_clear_tx_bd(union enetc_tx_bd *txbd)
393 memset(txbd, 0, sizeof(*txbd));
397 #define ENETC_TXBD_L3_IPCS BIT(7)
398 #define ENETC_TXBD_L3_IPV6 BIT(15)
400 #define ENETC_TXBD_L3_START_MASK GENMASK(6, 0)
401 #define ENETC_TXBD_L3_SET_HSIZE(val) ((((val) >> 2) & 0x7f) << 8)
403 /* Extension flags */
404 #define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0)
405 #define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP BIT(2)
407 static inline __le16 enetc_txbd_l3_csoff(int start, int hdr_sz, u16 l3_flags)
409 return cpu_to_le16(l3_flags | ENETC_TXBD_L3_SET_HSIZE(hdr_sz) |
410 (start & ENETC_TXBD_L3_START_MASK));
414 #define ENETC_TXBD_L4_UDP BIT(5)
415 #define ENETC_TXBD_L4_TCP BIT(6)
421 #ifdef CONFIG_FSL_ENETC_HW_TIMESTAMPING
427 __le16 parse_summary;
438 #ifdef CONFIG_FSL_ENETC_HW_TIMESTAMPING
445 #define ENETC_RXBD_LSTATUS_R BIT(30)
446 #define ENETC_RXBD_LSTATUS_F BIT(31)
447 #define ENETC_RXBD_ERR_MASK 0xff
448 #define ENETC_RXBD_LSTATUS(flags) ((flags) << 16)
449 #define ENETC_RXBD_FLAG_VLAN BIT(9)
450 #define ENETC_RXBD_FLAG_TSTMP BIT(10)
452 #define ENETC_MAC_ADDR_FILT_CNT 8 /* # of supported entries per port */
453 #define EMETC_MAC_ADDR_FILT_RES 3 /* # of reserved entries at the beginning */
454 #define ENETC_MAX_NUM_VFS 2
456 #define ENETC_CBD_FLAGS_SF BIT(7) /* short format */
457 #define ENETC_CBD_STATUS_MASK 0xf
459 struct enetc_cmd_rfse {
485 #define ENETC_RFSE_EN BIT(15)
486 #define ENETC_RFSE_MODE_BD 2
488 static inline void enetc_get_primary_mac_addr(struct enetc_hw *hw, u8 *addr)
490 *(u32 *)addr = __raw_readl(hw->reg + ENETC_SIPMAR0);
491 *(u16 *)(addr + 4) = __raw_readw(hw->reg + ENETC_SIPMAR1);
494 #define ENETC_SI_INT_IDX 0
495 /* base index for Rx/Tx interrupts */
496 #define ENETC_BDR_INT_BASE_IDX 1
500 /* Command completion status */
501 enum enetc_msg_cmd_status {
502 ENETC_MSG_CMD_STATUS_OK,
503 ENETC_MSG_CMD_STATUS_FAIL
506 /* VSI-PSI command message types */
507 enum enetc_msg_cmd_type {
508 ENETC_MSG_CMD_MNG_MAC = 1, /* manage MAC address */
509 ENETC_MSG_CMD_MNG_RX_MAC_FILTER,/* manage RX MAC table */
510 ENETC_MSG_CMD_MNG_RX_VLAN_FILTER /* manage RX VLAN table */
513 /* VSI-PSI command action types */
514 enum enetc_msg_cmd_action_type {
515 ENETC_MSG_CMD_MNG_ADD = 1,
516 ENETC_MSG_CMD_MNG_REMOVE
519 /* PSI-VSI command header format */
520 struct enetc_msg_cmd_header {
521 u16 type; /* command class type */
522 u16 id; /* denotes the specific required action */
525 /* Common H/W utility functions */
527 static inline void enetc_enable_rxvlan(struct enetc_hw *hw, int si_idx,
530 u32 val = enetc_rxbdr_rd(hw, si_idx, ENETC_RBMR);
532 val = (val & ~ENETC_RBMR_VTE) | (en ? ENETC_RBMR_VTE : 0);
533 enetc_rxbdr_wr(hw, si_idx, ENETC_RBMR, val);
536 static inline void enetc_enable_txvlan(struct enetc_hw *hw, int si_idx,
539 u32 val = enetc_txbdr_rd(hw, si_idx, ENETC_TBMR);
541 val = (val & ~ENETC_TBMR_VIH) | (en ? ENETC_TBMR_VIH : 0);
542 enetc_txbdr_wr(hw, si_idx, ENETC_TBMR, val);
545 static inline void enetc_set_bdr_prio(struct enetc_hw *hw, int bdr_idx,
548 u32 val = enetc_txbdr_rd(hw, bdr_idx, ENETC_TBMR);
550 val &= ~ENETC_TBMR_PRIO_MASK;
551 val |= ENETC_TBMR_SET_PRIO(prio);
552 enetc_txbdr_wr(hw, bdr_idx, ENETC_TBMR, val);
555 enum bdcr_cmd_class {
558 BDCR_CMD_VLAN_FILTER,
562 BDCR_CMD_RECV_CLASSIFIER,
564 BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1,
567 /* class 5, command 0 */
568 struct tgs_gcl_conf {
569 u8 atc; /* init gate value */
578 /* gate control list entry */
585 /* tgs_gcl_conf address point to this data space */
586 struct tgs_gcl_data {
600 struct tgs_gcl_conf gcl_conf;
613 #define ENETC_CLK 400000000ULL
615 /* port time gating control register */
616 #define ENETC_QBV_PTGCR_OFFSET 0x11a00
617 #define ENETC_QBV_TGE BIT(31)
618 #define ENETC_QBV_TGPE BIT(30)
620 /* Port time gating capability register */
621 #define ENETC_QBV_PTGCAPR_OFFSET 0x11a08
622 #define ENETC_QBV_MAX_GCL_LEN_MASK GENMASK(15, 0)
624 /* Port time specific departure */
625 #define ENETC_PTCTSDR(n) (0x1210 + 4 * (n))
626 #define ENETC_TSDE BIT(31)